Cross Reference: /external/llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines Matching refs:VA
1245     CCValAssign VA = RVLocs[i];
1248     if (VA.needsCustom()) {
1250       SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1254       VA = RVLocs[++i]; // skip ahead to next loc
1255       SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1261       if (VA.getLocVT() == MVT::v2f64) {
1266         VA = RVLocs[++i]; // skip ahead to next loc
1267         Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1270         VA = RVLocs[++i]; // skip ahead to next loc
1271         Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1279       Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1285     switch (VA.getLocInfo()) {
1289       Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1304                                     const CCValAssign &VA,
1306   unsigned LocMemOffset = VA.getLocMemOffset();
1317                                          CCValAssign &VA, CCValAssign &NextVA,
1324   RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1406     CCValAssign &VA = ArgLocs[i];
1412     switch (VA.getLocInfo()) {
1416       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1419       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1422       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1425       Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1430     if (VA.needsCustom()) {
1431       if (VA.getLocVT() == MVT::v2f64) {
1438                          VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1440         VA = ArgLocs[++i]; // skip ahead to next loc
1441         if (VA.isRegLoc()) {
1443                            VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1445           assert(VA.isMemLoc());
1448                                                  dl, DAG, VA, Flags));
1451         PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1454     } else if (VA.isRegLoc()) {
1455       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1457       assert(VA.isMemLoc());
1479         unsigned LocMemOffset = VA.getLocMemOffset();
1495       assert(VA.isMemLoc());
1498                                              dl, DAG, VA, Flags));
1893         CCValAssign &VA = ArgLocs[i];
1894         EVT RegVT = VA.getLocVT();
1897         if (VA.getLocInfo() == CCValAssign::Indirect)
1899         if (VA.needsCustom()) {
1904           if (!VA.isRegLoc())
1914         } else if (!VA.isRegLoc()) {
1915           if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1963     CCValAssign &VA = RVLocs[i];
1964     assert(VA.isRegLoc() && "Can only return in registers!");
1968     switch (VA.getLocInfo()) {
1972       Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1976     if (VA.needsCustom()) {
1977       if (VA.getLocVT() == MVT::v2f64) {
1984         Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1986         RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1987         VA = RVLocs[++i]; // skip ahead to next loc
1988         Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1991         RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1992         VA = RVLocs[++i]; // skip ahead to next loc
2002       Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
2004       RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2005       VA = RVLocs[++i]; // skip ahead to next loc
2006       Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
2009       Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2014     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2545 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2558   unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2692     CCValAssign &VA = ArgLocs[i];
2693     std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2694     CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2696     if (VA.isRegLoc()) {
2697       EVT RegVT = VA.getLocVT();
2699       if (VA.needsCustom()) {
2702         if (VA.getLocVT() == MVT::v2f64) {
2703           SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2705           VA = ArgLocs[++i]; // skip ahead to next loc
2707           if (VA.isMemLoc()) {
2708             int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2714             ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2723           ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2742         unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2749       switch (VA.getLocInfo()) {
2753         ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2757                                DAG.getValueType(VA.getValVT()));
2758         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2762                                DAG.getValueType(VA.getValVT()));
2763         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2769     } else { // VA.isRegLoc()
2772       assert(VA.isMemLoc());
2773       assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2792                                    Ins[VA.getValNo()].PartOffset,
2793                                    VA.getLocMemOffset(),
2799                                               VA.getLocMemOffset(), false);
2803             int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2804                                             VA.getLocMemOffset(), true);
2808             InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,