Lines Matching refs:Inst
188 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
189 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
190 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
192 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
194 void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
196 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
198 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
200 void cvtStWriteBackRegAddrMode2(MCInst &Inst,
202 void cvtStWriteBackRegAddrMode3(MCInst &Inst,
204 void cvtLdExtTWriteBackImm(MCInst &Inst,
206 void cvtLdExtTWriteBackReg(MCInst &Inst,
208 void cvtStExtTWriteBackImm(MCInst &Inst,
210 void cvtStExtTWriteBackReg(MCInst &Inst,
212 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
213 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
214 void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
216 void cvtThumbMultiply(MCInst &Inst,
218 void cvtVLDwbFixed(MCInst &Inst,
220 void cvtVLDwbRegister(MCInst &Inst,
222 void cvtVSTwbFixed(MCInst &Inst,
224 void cvtVSTwbRegister(MCInst &Inst,
226 bool validateInstruction(MCInst &Inst,
228 bool processInstruction(MCInst &Inst,
273 unsigned checkTargetMatchPredicate(MCInst &Inst);
1429 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1432 Inst.addOperand(MCOperand::CreateImm(0));
1434 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1436 Inst.addOperand(MCOperand::CreateExpr(Expr));
1439 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1441 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1443 Inst.addOperand(MCOperand::CreateReg(RegNum));
1446 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1448 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1451 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1453 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1456 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1458 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1461 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1463 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1466 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1468 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1471 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1473 Inst.addOperand(MCOperand::CreateReg(getReg()));
1476 void addRegOperands(MCInst &Inst, unsigned N) const {
1478 Inst.addOperand(MCOperand::CreateReg(getReg()));
1481 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1485 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1486 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1487 Inst.addOperand(MCOperand::CreateImm(
1491 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1495 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1498 Inst.addOperand(MCOperand::CreateImm(
1502 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1504 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1508 void addRegListOperands(MCInst &Inst, unsigned N) const {
1513 Inst.addOperand(MCOperand::CreateReg(*I));
1516 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1517 addRegListOperands(Inst, N);
1520 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1521 addRegListOperands(Inst, N);
1524 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1527 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1530 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1538 Inst.addOperand(MCOperand::CreateImm(Mask));
1541 void addImmOperands(MCInst &Inst, unsigned N) const {
1543 addExpr(Inst, getImm());
1546 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1549 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1552 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1555 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1558 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1562 Inst.addOperand(MCOperand::CreateImm(Val));
1565 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1570 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1573 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1578 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1581 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1586 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1589 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1594 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1597 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1602 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1605 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1610 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1613 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1619 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1622 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1628 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1631 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1636 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1639 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1644 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1647 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1652 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1655 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1660 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1663 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1668 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1671 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1673 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1676 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1678 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1681 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1686 Inst.addOperand(MCOperand::CreateImm(Imm));
1689 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1696 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1702 Inst.addOperand(MCOperand::CreateImm(Val));
1705 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1707 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1708 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1711 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1726 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1727 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1728 Inst.addOperand(MCOperand::CreateImm(Val));
1731 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1741 Inst.addOperand(MCOperand::CreateReg(0));
1742 Inst.addOperand(MCOperand::CreateImm(Val));
1745 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1751 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1752 Inst.addOperand(MCOperand::CreateReg(0));
1753 Inst.addOperand(MCOperand::CreateImm(0));
1769 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1770 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1771 Inst.addOperand(MCOperand::CreateImm(Val));
1774 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1779 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1780 Inst.addOperand(MCOperand::CreateImm(Val));
1792 Inst.addOperand(MCOperand::CreateReg(0));
1793 Inst.addOperand(MCOperand::CreateImm(Val));
1796 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1802 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1803 Inst.addOperand(MCOperand::CreateImm(0));
1814 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1815 Inst.addOperand(MCOperand::CreateImm(Val));
1818 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1824 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1825 Inst.addOperand(MCOperand::CreateImm(0));
1830 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1831 Inst.addOperand(MCOperand::CreateImm(Val));
1834 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1838 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1839 Inst.addOperand(MCOperand::CreateImm(Val));
1842 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1845 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1846 Inst.addOperand(MCOperand::CreateImm(Val));
1849 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1850 addMemImm8OffsetOperands(Inst, N);
1853 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1854 addMemImm8OffsetOperands(Inst, N);
1857 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1861 addExpr(Inst, getImm());
1862 Inst.addOperand(MCOperand::CreateImm(0));
1868 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1869 Inst.addOperand(MCOperand::CreateImm(Val));
1872 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1876 addExpr(Inst, getImm());
1877 Inst.addOperand(MCOperand::CreateImm(0));
1883 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1884 Inst.addOperand(MCOperand::CreateImm(Val));
1887 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1889 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1890 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1893 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1895 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1896 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1899 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1904 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1905 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1906 Inst.addOperand(MCOperand::CreateImm(Val));
1909 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1911 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1912 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1913 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1916 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1918 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1919 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1922 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1925 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1926 Inst.addOperand(MCOperand::CreateImm(Val));
1929 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1932 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1933 Inst.addOperand(MCOperand::CreateImm(Val));
1936 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1939 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1940 Inst.addOperand(MCOperand::CreateImm(Val));
1943 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1946 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1947 Inst.addOperand(MCOperand::CreateImm(Val));
1950 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1958 Inst.addOperand(MCOperand::CreateImm(Imm));
1961 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1970 Inst.addOperand(MCOperand::CreateImm(Imm));
1973 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1975 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1976 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1979 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1981 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1987 Inst.addOperand(MCOperand::CreateImm(Imm));
1990 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1992 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1995 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1997 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2000 void addVecListOperands(MCInst &Inst, unsigned N) const {
2002 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2005 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2007 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2008 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2011 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2013 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2016 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2018 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2021 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2023 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2026 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2031 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2034 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2043 Inst.addOperand(MCOperand::CreateImm(Value));
2046 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2057 Inst.addOperand(MCOperand::CreateImm(Value));
2060 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2071 Inst.addOperand(MCOperand::CreateImm(Value));
2074 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2085 Inst.addOperand(MCOperand::CreateImm(Value));
2088 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2097 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
3926 cvtT2LdrdPre(MCInst &Inst,
3929 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3930 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3932 Inst.addOperand(MCOperand::CreateReg(0));
3934 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3936 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3943 cvtT2StrdPre(MCInst &Inst,
3946 Inst.addOperand(MCOperand::CreateReg(0));
3948 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3949 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3951 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3953 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3960 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
3962 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3965 Inst.addOperand(MCOperand::CreateImm(0));
3967 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3968 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3975 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
3978 Inst.addOperand(MCOperand::CreateImm(0));
3979 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3980 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3981 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3988 cvtLdWriteBackRegAddrMode2(MCInst &Inst,
3990 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3993 Inst.addOperand(MCOperand::CreateImm(0));
3995 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3996 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4003 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
4005 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4008 Inst.addOperand(MCOperand::CreateImm(0));
4010 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4011 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4019 cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
4022 Inst.addOperand(MCOperand::CreateImm(0));
4023 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4024 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4025 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4032 cvtStWriteBackRegAddrMode2(MCInst &Inst,
4035 Inst.addOperand(MCOperand::CreateImm(0));
4036 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4037 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4038 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4045 cvtStWriteBackRegAddrMode3(MCInst &Inst,
4048 Inst.addOperand(MCOperand::CreateImm(0));
4049 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4050 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4051 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4058 cvtLdExtTWriteBackImm(MCInst &Inst,
4061 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4063 Inst.addOperand(MCOperand::CreateImm(0));
4065 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4067 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4069 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4076 cvtLdExtTWriteBackReg(MCInst &Inst,
4079 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4081 Inst.addOperand(MCOperand::CreateImm(0));
4083 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4085 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4087 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4094 cvtStExtTWriteBackImm(MCInst &Inst,
4097 Inst.addOperand(MCOperand::CreateImm(0));
4099 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4101 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4103 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4105 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4112 cvtStExtTWriteBackReg(MCInst &Inst,
4115 Inst.addOperand(MCOperand::CreateImm(0));
4117 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4119 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4121 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4123 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4130 cvtLdrdPre(MCInst &Inst,
4133 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4134 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4136 Inst.addOperand(MCOperand::CreateImm(0));
4138 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4140 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4147 cvtStrdPre(MCInst &Inst,
4150 Inst.addOperand(MCOperand::CreateImm(0));
4152 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4153 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4155 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4157 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4164 cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4166 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4168 Inst.addOperand(MCOperand::CreateImm(0));
4169 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4170 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4177 cvtThumbMultiply(MCInst &Inst,
4179 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4180 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4188 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4189 Inst.addOperand(Inst.getOperand(0));
4190 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4194 cvtVLDwbFixed(MCInst &Inst,
4197 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4199 Inst.addOperand(MCOperand::CreateImm(0));
4201 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4203 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4207 cvtVLDwbRegister(MCInst &Inst,
4210 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4212 Inst.addOperand(MCOperand::CreateImm(0));
4214 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4216 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4218 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4222 cvtVSTwbFixed(MCInst &Inst,
4225 Inst.addOperand(MCOperand::CreateImm(0));
4227 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4229 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4231 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4235 cvtVSTwbRegister(MCInst &Inst,
4238 Inst.addOperand(MCOperand::CreateImm(0));
4240 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4242 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4244 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4246 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
5246 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5249 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5250 unsigned OpReg = Inst.getOperand(i).getReg();
5262 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5263 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5264 unsigned OpReg = Inst.getOperand(i).getReg();
5283 validateInstruction(MCInst &Inst,
5285 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5291 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5292 Inst.getOpcode() != ARM::BKPT) {
5301 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5317 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5318 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5319 Inst.getOpcode() != ARM::t2B)
5322 switch (Inst.getOpcode()) {
5327 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5328 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5336 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5337 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5346 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5347 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5356 unsigned lsb = Inst.getOperand(2).getImm();
5357 unsigned widthm1 = Inst.getOperand(3).getImm();
5371 unsigned Rn = Inst.getOperand(0).getReg();
5376 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5393 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5405 // this first statement is always true for the new Inst. Essentially, the
5423 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5431 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5439 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5448 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5716 processInstruction(MCInst &Inst,
5718 switch (Inst.getOpcode()) {
5721 if (Inst.getOperand(1).getReg() != ARM::PC ||
5722 Inst.getOperand(5).getReg() != 0)
5726 TmpInst.addOperand(Inst.getOperand(0));
5727 TmpInst.addOperand(Inst.getOperand(2));
5728 TmpInst.addOperand(Inst.getOperand(3));
5729 TmpInst.addOperand(Inst.getOperand(4));
5730 Inst = TmpInst;
5736 if (Inst.getOperand(1).getImm() > 0 &&
5737 Inst.getOperand(1).getImm() <= 0xff)
5738 Inst.setOpcode(ARM::tLDRpci);
5740 Inst.setOpcode(ARM::t2LDRpci);
5743 Inst.setOpcode(ARM::t2LDRBpci);
5746 Inst.setOpcode(ARM::t2LDRHpci);
5749 Inst.setOpcode(ARM::t2LDRSBpci);
5752 Inst.setOpcode(ARM::t2LDRSHpci);
5762 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5763 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5764 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5765 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5766 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5767 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5768 TmpInst.addOperand(Inst.getOperand(1)); // lane
5769 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5770 TmpInst.addOperand(Inst.getOperand(6));
5771 Inst = TmpInst;
5784 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5785 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5786 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5787 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5788 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5789 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5790 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5792 TmpInst.addOperand(Inst.getOperand(1)); // lane
5793 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5794 TmpInst.addOperand(Inst.getOperand(6));
5795 Inst = TmpInst;
5808 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5809 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5810 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5811 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5812 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5813 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5814 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5816 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5818 TmpInst.addOperand(Inst.getOperand(1)); // lane
5819 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5820 TmpInst.addOperand(Inst.getOperand(6));
5821 Inst = TmpInst;
5834 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5835 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5836 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5837 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5838 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5839 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5840 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5842 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5844 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5846 TmpInst.addOperand(Inst.getOperand(1)); // lane
5847 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5848 TmpInst.addOperand(Inst.getOperand(6));
5849 Inst = TmpInst;
5860 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5861 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5862 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5863 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5865 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5866 TmpInst.addOperand(Inst.getOperand(1)); // lane
5867 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5868 TmpInst.addOperand(Inst.getOperand(5));
5869 Inst = TmpInst;
5882 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5883 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5884 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5885 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5887 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5890 TmpInst.addOperand(Inst.getOperand(1)); // lane
5891 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5892 TmpInst.addOperand(Inst.getOperand(5));
5893 Inst = TmpInst;
5906 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5907 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5908 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5909 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5911 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5912 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5914 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5916 TmpInst.addOperand(Inst.getOperand(1)); // lane
5917 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5918 TmpInst.addOperand(Inst.getOperand(5));
5919 Inst = TmpInst;
5932 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5933 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5934 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5935 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5937 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5938 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5940 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5942 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5944 TmpInst.addOperand(Inst.getOperand(1)); // lane
5945 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5946 TmpInst.addOperand(Inst.getOperand(5));
5947 Inst = TmpInst;
5958 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5959 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5960 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5961 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5962 TmpInst.addOperand(Inst.getOperand(1)); // lane
5963 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5964 TmpInst.addOperand(Inst.getOperand(5));
5965 Inst = TmpInst;
5978 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5979 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5980 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5981 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5982 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5984 TmpInst.addOperand(Inst.getOperand(1)); // lane
5985 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5986 TmpInst.addOperand(Inst.getOperand(5));
5987 Inst = TmpInst;
6000 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6001 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6002 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6003 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6004 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6006 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6008 TmpInst.addOperand(Inst.getOperand(1)); // lane
6009 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6010 TmpInst.addOperand(Inst.getOperand(5));
6011 Inst = TmpInst;
6024 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6025 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6026 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6027 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6028 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6030 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6032 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6034 TmpInst.addOperand(Inst.getOperand(1)); // lane
6035 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6036 TmpInst.addOperand(Inst.getOperand(5));
6037 Inst = TmpInst;
6049 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6050 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6051 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6052 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6053 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6054 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6055 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6056 TmpInst.addOperand(Inst.getOperand(1)); // lane
6057 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6058 TmpInst.addOperand(Inst.getOperand(6));
6059 Inst = TmpInst;
6072 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6073 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6074 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6076 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6077 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6078 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6079 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6080 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6083 TmpInst.addOperand(Inst.getOperand(1)); // lane
6084 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6085 TmpInst.addOperand(Inst.getOperand(6));
6086 Inst = TmpInst;
6099 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6100 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6101 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6103 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6105 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6106 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6107 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6108 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6109 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6110 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6112 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6114 TmpInst.addOperand(Inst.getOperand(1)); // lane
6115 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6116 TmpInst.addOperand(Inst.getOperand(6));
6117 Inst = TmpInst;
6130 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6131 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6132 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6134 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6136 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6138 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6139 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6140 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6141 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6142 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6143 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6145 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6147 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6149 TmpInst.addOperand(Inst.getOperand(1)); // lane
6150 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6151 TmpInst.addOperand(Inst.getOperand(6));
6152 Inst = TmpInst;
6163 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6164 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6165 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6166 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6167 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6169 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6170 TmpInst.addOperand(Inst.getOperand(1)); // lane
6171 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6172 TmpInst.addOperand(Inst.getOperand(5));
6173 Inst = TmpInst;
6186 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6187 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6188 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6190 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6191 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6192 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6194 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6195 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6197 TmpInst.addOperand(Inst.getOperand(1)); // lane
6198 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6199 TmpInst.addOperand(Inst.getOperand(5));
6200 Inst = TmpInst;
6213 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6214 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6215 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6217 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6219 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6220 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6221 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6223 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6224 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6226 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6228 TmpInst.addOperand(Inst.getOperand(1)); // lane
6229 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6230 TmpInst.addOperand(Inst.getOperand(5));
6231 Inst = TmpInst;
6244 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6245 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6246 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6248 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6250 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6252 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6253 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6254 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6256 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6257 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6259 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6261 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6263 TmpInst.addOperand(Inst.getOperand(1)); // lane
6264 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6265 TmpInst.addOperand(Inst.getOperand(5));
6266 Inst = TmpInst;
6277 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6278 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6279 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6280 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6281 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6282 TmpInst.addOperand(Inst.getOperand(1)); // lane
6283 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6284 TmpInst.addOperand(Inst.getOperand(5));
6285 Inst = TmpInst;
6298 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6299 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6300 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6302 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6303 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6304 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6307 TmpInst.addOperand(Inst.getOperand(1)); // lane
6308 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6309 TmpInst.addOperand(Inst.getOperand(5));
6310 Inst = TmpInst;
6323 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6324 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6325 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6327 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6329 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6330 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6331 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6332 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6334 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6336 TmpInst.addOperand(Inst.getOperand(1)); // lane
6337 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6338 TmpInst.addOperand(Inst.getOperand(5));
6339 Inst = TmpInst;
6352 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6353 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6354 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6356 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6358 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6360 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6361 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6362 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6363 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6367 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6369 TmpInst.addOperand(Inst.getOperand(1)); // lane
6370 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6371 TmpInst.addOperand(Inst.getOperand(5));
6372 Inst = TmpInst;
6385 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6386 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6387 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6389 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6391 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6392 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6393 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6394 TmpInst.addOperand(Inst.getOperand(4));
6395 Inst = TmpInst;
6407 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6408 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6409 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6411 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6413 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6414 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6415 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6417 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6418 TmpInst.addOperand(Inst.getOperand(4));
6419 Inst = TmpInst;
6431 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6432 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6433 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6435 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6437 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6438 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6439 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6440 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6441 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6442 TmpInst.addOperand(Inst.getOperand(5));
6443 Inst = TmpInst;
6456 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6457 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6458 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6460 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6462 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6463 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6464 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6465 TmpInst.addOperand(Inst.getOperand(4));
6466 Inst = TmpInst;
6478 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6479 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6480 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6482 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6484 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6485 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6486 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6488 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6489 TmpInst.addOperand(Inst.getOperand(4));
6490 Inst = TmpInst;
6502 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6503 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6504 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6506 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6508 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6509 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6510 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6511 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6512 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6513 TmpInst.addOperand(Inst.getOperand(5));
6514 Inst = TmpInst;
6527 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6528 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6529 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6531 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6533 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6535 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6536 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6537 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6538 TmpInst.addOperand(Inst.getOperand(4));
6539 Inst = TmpInst;
6551 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6552 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6553 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6555 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6557 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6559 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6560 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6561 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6563 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6564 TmpInst.addOperand(Inst.getOperand(4));
6565 Inst = TmpInst;
6577 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6578 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6579 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6581 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6583 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6585 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6586 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6587 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6588 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6589 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6590 TmpInst.addOperand(Inst.getOperand(5));
6591 Inst = TmpInst;
6604 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6605 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6606 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6608 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6610 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6612 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6613 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6614 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6615 TmpInst.addOperand(Inst.getOperand(4));
6616 Inst = TmpInst;
6628 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6629 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6630 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6632 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6634 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6636 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6637 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6638 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6640 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6641 TmpInst.addOperand(Inst.getOperand(4));
6642 Inst = TmpInst;
6654 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6655 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6656 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6658 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6660 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6662 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6663 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6664 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6665 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6666 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6667 TmpInst.addOperand(Inst.getOperand(5));
6668 Inst = TmpInst;
6681 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6682 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6683 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6684 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6685 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6687 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6689 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6690 TmpInst.addOperand(Inst.getOperand(4));
6691 Inst = TmpInst;
6703 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6704 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6705 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6706 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6708 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6709 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6711 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6713 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6714 TmpInst.addOperand(Inst.getOperand(4));
6715 Inst = TmpInst;
6727 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6728 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6729 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6730 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6731 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6732 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6733 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6735 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6737 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6738 TmpInst.addOperand(Inst.getOperand(5));
6739 Inst = TmpInst;
6752 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6753 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6754 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6755 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6756 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6758 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6760 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6762 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6763 TmpInst.addOperand(Inst.getOperand(4));
6764 Inst = TmpInst;
6776 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6777 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6778 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6779 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6781 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6784 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6786 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6788 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6789 TmpInst.addOperand(Inst.getOperand(4));
6790 Inst = TmpInst;
6802 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6803 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6804 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6805 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6806 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6807 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6808 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6810 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6812 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6814 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6815 TmpInst.addOperand(Inst.getOperand(5));
6816 Inst = TmpInst;
6824 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6825 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6826 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6830 switch (Inst.getOpcode()) {
6839 TmpInst.addOperand(Inst.getOperand(0));
6840 TmpInst.addOperand(Inst.getOperand(5));
6841 TmpInst.addOperand(Inst.getOperand(1));
6842 TmpInst.addOperand(Inst.getOperand(2));
6843 TmpInst.addOperand(Inst.getOperand(3));
6844 TmpInst.addOperand(Inst.getOperand(4));
6845 Inst = TmpInst;
6858 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6859 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6860 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6861 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6862 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6866 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6874 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6877 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6878 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6879 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6880 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6881 TmpInst.addOperand(Inst.getOperand(5));
6884 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6885 Inst = TmpInst;
6894 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6895 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6896 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6900 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6908 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6911 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6914 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6915 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6918 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6919 TmpInst.addOperand(Inst.getOperand(4));
6922 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6923 Inst = TmpInst;
6932 switch(Inst.getOpcode()) {
6942 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6943 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6944 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6946 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6947 TmpInst.addOperand(Inst.getOperand(4));
6948 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6949 Inst = TmpInst;
6957 switch(Inst.getOpcode()) {
6965 unsigned Amt = Inst.getOperand(2).getImm();
6973 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6974 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6977 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6978 TmpInst.addOperand(Inst.getOperand(4));
6979 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6980 Inst = TmpInst;
6987 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6988 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6990 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6991 TmpInst.addOperand(Inst.getOperand(3));
6992 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6993 Inst = TmpInst;
6999 if (Inst.getNumOperands() != 5)
7003 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7004 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7005 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7007 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7008 TmpInst.addOperand(Inst.getOperand(3));
7009 Inst = TmpInst;
7015 if (Inst.getNumOperands() != 5)
7019 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7020 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7021 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7023 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7024 TmpInst.addOperand(Inst.getOperand(3));
7025 Inst = TmpInst;
7032 Inst.getNumOperands() == 5) {
7035 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7036 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7037 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7040 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7041 TmpInst.addOperand(Inst.getOperand(3));
7042 Inst = TmpInst;
7050 Inst.getNumOperands() == 5) {
7053 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7054 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7055 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7057 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7058 TmpInst.addOperand(Inst.getOperand(3));
7059 Inst = TmpInst;
7066 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7068 Inst.setOpcode(ARM::t2ADDri);
7069 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7075 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7077 Inst.setOpcode(ARM::t2SUBri);
7078 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7085 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7086 Inst.setOpcode(ARM::tADDi3);
7095 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7096 Inst.setOpcode(ARM::tSUBi3);
7106 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7107 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7108 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7109 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7110 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7115 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7117 TmpInst.addOperand(Inst.getOperand(0));
7118 TmpInst.addOperand(Inst.getOperand(5));
7119 TmpInst.addOperand(Inst.getOperand(0));
7120 TmpInst.addOperand(Inst.getOperand(2));
7121 TmpInst.addOperand(Inst.getOperand(3));
7122 TmpInst.addOperand(Inst.getOperand(4));
7123 Inst = TmpInst;
7131 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7132 Inst.getOperand(5).getReg() != 0 ||
7138 TmpInst.addOperand(Inst.getOperand(0));
7139 TmpInst.addOperand(Inst.getOperand(0));
7140 TmpInst.addOperand(Inst.getOperand(2));
7141 TmpInst.addOperand(Inst.getOperand(3));
7142 TmpInst.addOperand(Inst.getOperand(4));
7143 Inst = TmpInst;
7149 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7150 Inst.setOpcode(ARM::t2ADDrr);
7151 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7158 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7159 Inst.setOpcode(ARM::tBcc);
7165 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7166 Inst.setOpcode(ARM::t2Bcc);
7172 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7173 Inst.setOpcode(ARM::t2B);
7179 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7180 Inst.setOpcode(ARM::tB);
7189 unsigned Rn = Inst.getOperand(0).getReg();
7194 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7199 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7203 Inst.insert(Inst.begin(),
7204 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7213 unsigned Rn = Inst.getOperand(0).getReg();
7215 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7218 Inst.setOpcode(ARM::t2STMIA_UPD);
7228 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7231 Inst.setOpcode(ARM::t2LDMIA_UPD);
7233 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7234 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7239 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7242 Inst.setOpcode(ARM::t2STMDB_UPD);
7244 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7245 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7251 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7252 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7253 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7254 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7255 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7261 TmpInst.addOperand(Inst.getOperand(0));
7262 TmpInst.addOperand(Inst.getOperand(4));
7263 TmpInst.addOperand(Inst.getOperand(1));
7264 TmpInst.addOperand(Inst.getOperand(2));
7265 TmpInst.addOperand(Inst.getOperand(3));
7266 Inst = TmpInst;
7274 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7275 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7276 Inst.getOperand(2).getImm() == ARMCC::AL &&
7277 Inst.getOperand(4).getReg() == ARM::CPSR &&
7282 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7283 TmpInst.addOperand(Inst.getOperand(0));
7284 TmpInst.addOperand(Inst.getOperand(1));
7285 TmpInst.addOperand(Inst.getOperand(2));
7286 TmpInst.addOperand(Inst.getOperand(3));
7287 Inst = TmpInst;
7298 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7299 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7300 Inst.getOperand(2).getImm() == 0 &&
7304 switch (Inst.getOpcode()) {
7314 TmpInst.addOperand(Inst.getOperand(0));
7315 TmpInst.addOperand(Inst.getOperand(1));
7316 TmpInst.addOperand(Inst.getOperand(3));
7317 TmpInst.addOperand(Inst.getOperand(4));
7318 Inst = TmpInst;
7324 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7328 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7332 TmpInst.addOperand(Inst.getOperand(0));
7333 TmpInst.addOperand(Inst.getOperand(1));
7334 TmpInst.addOperand(Inst.getOperand(3));
7335 TmpInst.addOperand(Inst.getOperand(4));
7336 TmpInst.addOperand(Inst.getOperand(5));
7337 Inst = TmpInst;
7349 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7351 switch (Inst.getOpcode()) {
7362 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7366 TmpInst.addOperand(Inst.getOperand(0));
7367 TmpInst.addOperand(Inst.getOperand(1));
7368 TmpInst.addOperand(Inst.getOperand(2));
7369 TmpInst.addOperand(Inst.getOperand(4));
7370 TmpInst.addOperand(Inst.getOperand(5));
7371 TmpInst.addOperand(Inst.getOperand(6));
7372 Inst = TmpInst;
7383 MCOperand &MO = Inst.getOperand(1);
7387 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7397 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7411 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7412 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7413 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7414 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7415 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7419 switch (Inst.getOpcode()) {
7430 TmpInst.addOperand(Inst.getOperand(0));
7431 TmpInst.addOperand(Inst.getOperand(5));
7432 TmpInst.addOperand(Inst.getOperand(1));
7433 TmpInst.addOperand(Inst.getOperand(2));
7434 TmpInst.addOperand(Inst.getOperand(3));
7435 TmpInst.addOperand(Inst.getOperand(4));
7436 Inst = TmpInst;
7449 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7450 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7451 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7452 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7453 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7454 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7458 switch (Inst.getOpcode()) {
7467 TmpInst.addOperand(Inst.getOperand(0));
7468 TmpInst.addOperand(Inst.getOperand(5));
7469 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7470 TmpInst.addOperand(Inst.getOperand(1));
7471 TmpInst.addOperand(Inst.getOperand(2));
7473 TmpInst.addOperand(Inst.getOperand(2));
7474 TmpInst.addOperand(Inst.getOperand(1));
7476 TmpInst.addOperand(Inst.getOperand(3));
7477 TmpInst.addOperand(Inst.getOperand(4));
7478 Inst = TmpInst;
7487 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7490 unsigned Opc = Inst.getOpcode();
7495 assert(MCID.NumOperands == Inst.getNumOperands() &&
7504 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7508 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7511 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7518 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7519 isARMLowRegister(Inst.getOperand(2).getReg()))
7523 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7524 isARMLowRegister(Inst.getOperand(1).getReg()))
7535 MCInst Inst;
7538 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7545 if (validateInstruction(Inst, Operands)) {
7556 while (processInstruction(Inst, Operands))
7566 if (Inst.getOpcode() == ARM::ITasm)
7569 Inst.setLoc(IDLoc);
7570 Out.EmitInstruction(Inst);