Lines Matching refs:MCID
203 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
204 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
523 const MCInstrDesc &MCID = MI->getDesc();
524 if (MCID.hasOptionalDef() &&
525 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
673 const MCInstrDesc &MCID = MI->getDesc();
674 if (MCID.hasOptionalDef()) {
675 unsigned NumOps = MCID.getNumOperands();
701 unsigned NumOps = MCID.getNumOperands();
703 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
705 if (SkipPred && MCID.OpInfo[i].isPredicate())
738 const MCInstrDesc &MCID = MI->getDesc();
739 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
740 if (MCID.OpInfo[i].isPredicate())
750 !MCID.OpInfo[i].isPredicate()) {
771 if (MCID.hasOptionalDef()) {
772 unsigned NumOps = MCID.getNumOperands();
798 unsigned NumOps = MCID.getNumOperands();
800 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
802 if ((MCID.getOpcode() == ARM::t2RSBSri ||
803 MCID.getOpcode() == ARM::t2RSBri ||
804 MCID.getOpcode() == ARM::t2SXTB ||
805 MCID.getOpcode() == ARM::t2SXTH ||
806 MCID.getOpcode() == ARM::t2UXTB ||
807 MCID.getOpcode() == ARM::t2UXTH) && i == 2)
810 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
820 if (!MCID.isPredicable() && NewMCID.isPredicable())