Cross Reference: /external/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Lines Matching refs:Inst
91 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
96 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
101 static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
106 static DecodeStatus DecodeDSPRegsRegisterClass(MCInst &Inst,
111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
121 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
126 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
131 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
136 static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
141 static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
146 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
151 static DecodeStatus DecodeBC1(MCInst &Inst,
157 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
162 static DecodeStatus DecodeMem(MCInst &Inst,
167 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
171 static DecodeStatus DecodeSimm16(MCInst &Inst,
176 static DecodeStatus DecodeCondCode(MCInst &Inst,
181 static DecodeStatus DecodeInsSize(MCInst &Inst,
186 static DecodeStatus DecodeExtSize(MCInst &Inst,
330 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
339 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
348   Inst.addOperand(MCOperand::CreateReg(Reg));
352 static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
359   Inst.addOperand(MCOperand::CreateReg(Reg));
363 static DecodeStatus DecodeDSPRegsRegisterClass(MCInst &Inst,
367   return DecodeCPURegsRegisterClass(Inst, RegNo, Address, Decoder);
370 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
378   Inst.addOperand(MCOperand::CreateReg(Reg));
382 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
390   Inst.addOperand(MCOperand::CreateReg(Reg));
394 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
398   Inst.addOperand(MCOperand::CreateReg(RegNo));
402 static DecodeStatus DecodeMem(MCInst &Inst,
413   if(Inst.getOpcode() == Mips::SC){
414     Inst.addOperand(MCOperand::CreateReg(Reg));
417   Inst.addOperand(MCOperand::CreateReg(Reg));
418   Inst.addOperand(MCOperand::CreateReg(Base));
419   Inst.addOperand(MCOperand::CreateImm(Offset));
424 static DecodeStatus DecodeFMem(MCInst &Inst,
435   Inst.addOperand(MCOperand::CreateReg(Reg));
436   Inst.addOperand(MCOperand::CreateReg(Base));
437   Inst.addOperand(MCOperand::CreateImm(Offset));
443 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
450   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
454 static DecodeStatus DecodeCondCode(MCInst &Inst,
459   Inst.addOperand(MCOperand::CreateImm(CondCode));
463 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
472   Inst.addOperand(MCOperand::CreateReg(Reg));
476 static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
483   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
487 static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
495   Inst.addOperand(MCOperand::CreateReg(Reg));
499 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
505   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
509 static DecodeStatus DecodeBC1(MCInst &Inst,
515   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
519 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
525   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
530 static DecodeStatus DecodeSimm16(MCInst &Inst,
534   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
538 static DecodeStatus DecodeInsSize(MCInst &Inst,
543   int Pos = Inst.getOperand(2).getImm();
545   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
549 static DecodeStatus DecodeExtSize(MCInst &Inst,
554   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));