Lines Matching refs:Cond
79 SmallVectorImpl<MachineOperand> &Cond) const {
86 Cond.push_back(MachineOperand::CreateImm(Opc));
89 Cond.push_back(Inst->getOperand(i));
95 SmallVectorImpl<MachineOperand> &Cond,
98 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
105 const SmallVectorImpl<MachineOperand>& Cond)
107 unsigned Opc = Cond[0].getImm();
111 for (unsigned i = 1; i < Cond.size(); ++i) {
112 if (Cond[i].isReg())
113 MIB.addReg(Cond[i].getReg());
114 else if (Cond[i].isImm())
115 MIB.addImm(Cond[i].getImm());
125 const SmallVectorImpl<MachineOperand> &Cond,
135 assert((Cond.size() <= 3) &&
140 BuildCondBr(MBB, TBB, DL, Cond);
147 if (Cond.empty())
150 BuildCondBr(MBB, TBB, DL, Cond);
181 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
183 assert( (Cond.size() && Cond.size() <= 3) &&
185 Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm()));
191 MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond,
238 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
267 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);