Lines Matching refs:DL

83     void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
219 DebugLoc DL, MachineBasicBlock *MBBOpnd) {
223 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
245 DebugLoc DL = I.Br->getDebugLoc();
283 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
285 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
289 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
290 .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
294 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT)
296 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
298 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
302 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
303 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
330 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
332 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
334 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi64), Mips::AT_64)
336 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
338 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
340 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
344 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
345 .append(BuildMI(*MF, DL, TII->get(Mips::DSLL), Mips::AT_64)
350 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
352 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
354 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
358 .append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64))
359 .append(BuildMI(*MF, DL, TII->get(Mips::DADDiu), Mips::SP_64)
374 .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
375 .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
387 replaceBranch(*MBB, I.Br, DL, FallThroughMBB);
393 DebugLoc DL = MBB.findDebugLoc(MBB.begin());
394 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
396 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)