Cross Reference: /external/llvm/lib/Target/R600/R600ExpandSpecialInstrs.cpp

Lines Matching refs:TII
34   const R600InstrInfo *TII;
41     TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
60   const R600RegisterInfo &TRI = TII->getRegisterInfo();
77         MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
82         TII->addFlag(PredSet, 0, MO_FLAG_MASK);
84           TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1);
86           TII->setImmOperand(PredSet, R600Operands::UPDATE_PREDICATE, 1);
92         MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
97         TII->addFlag(PredSet, 0, MO_FLAG_MASK);
98         TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1);
101                 TII->get(AMDGPU::PREDICATED_BREAK))
120           BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
127             TII->addFlag(BMI, 0, MO_FLAG_MASK);
129             TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
149           BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
156             TII->addFlag(BMI, 0, MO_FLAG_MASK);
158             TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
166         const R600RegisterInfo &TRI = TII->getRegisterInfo();
173           BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
179             TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
187       bool IsReduction = TII->isReductionOp(MI.getOpcode());
188       bool IsVector = TII->isVector(MI);
189       bool IsCube = TII->isCubeOp(MI.getOpcode());
221                             TII->getOperandIdx(MI, R600Operands::DST)).getReg();
223                            TII->getOperandIdx(MI, R600Operands::SRC0)).getReg();
228           int Src1Idx = TII->getOperandIdx(MI, R600Operands::SRC1);
282           TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
287           TII->addFlag(NewMI, 0, MO_FLAG_MASK);
290           TII->addFlag(NewMI, 0, MO_FLAG_NOT_LAST);