Cross Reference: /external/llvm/lib/Target/R600/SILowerControlFlow.cpp

Lines Matching refs:TII
70   const TargetInstrInfo *TII;
95     TII(tm.getInstrInfo()) { }
139   BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
156   BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
161   BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
173   BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
182   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
185   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
200   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
203   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
219   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
234   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
249   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
261   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
265   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
278           TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
304   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
321     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
332   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
336   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
340   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
344   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
349   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
356   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
361   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
366   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
382     BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
400     BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))