Lines Matching defs:SRA
796 setOperationAction(ISD::SRA, VT, Expand);
1053 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1054 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1063 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1071 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1136 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1137 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1195 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1220 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1326 setTargetDAGCombine(ISD::SRA);
7916 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7926 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
10565 Opcode = ISD::SRA;
11480 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
11485 return SRA;
11489 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
11519 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11549 if (Op.getOpcode() == ISD::SRA) {
11593 if (Op.getOpcode() == ISD::SRA) {
12160 case ISD::SRA:
16020 case ISD::SRA:
16354 // Check that the SRA is all signbits.
16459 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
16464 N1.getOpcode() == ISD::SRA &&
16675 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
16692 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
17594 case ISD::SRA: