Cross Reference: /external/llvm/lib/Target/X86/X86ISelLowering.cpp

Lines Matching defs:SRL
797     setOperationAction(ISD::SRL, VT, Expand);
1047     setOperationAction(ISD::SRL,               MVT::v8i16, Custom);
1048     setOperationAction(ISD::SRL,               MVT::v16i8, Custom);
1057       setOperationAction(ISD::SRL,             MVT::v2i64, Legal);
1058       setOperationAction(ISD::SRL,             MVT::v4i32, Legal);
1065       setOperationAction(ISD::SRL,             MVT::v2i64, Custom);
1066       setOperationAction(ISD::SRL,             MVT::v4i32, Custom);
1130     setOperationAction(ISD::SRL,               MVT::v16i16, Custom);
1131     setOperationAction(ISD::SRL,               MVT::v32i8, Custom);
1189       setOperationAction(ISD::SRL,             MVT::v4i64, Legal);
1190       setOperationAction(ISD::SRL,             MVT::v8i32, Legal);
1214       setOperationAction(ISD::SRL,             MVT::v4i64, Custom);
1215       setOperationAction(ISD::SRL,             MVT::v8i32, Custom);
1327   setTargetDAGCombine(ISD::SRL);
6123         InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
7926     Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
9117   SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9163     if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
10561       Opcode = ISD::SRL;
11235     DAG.getNode(ISD::SRL, DL, MVT::i16,
11240     DAG.getNode(ISD::SRL, DL, MVT::i16,
11477     SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
11478     SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
11516         if (Op.getOpcode() == ISD::SRL)
11537         if (Op.getOpcode() == ISD::SRL) {
11539           SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11541           SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11546           return DAG.getNode(ISD::AND, dl, VT, SRL,
11557           SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11581         if (Op.getOpcode() == ISD::SRL) {
11583           SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11585           SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11590           return DAG.getNode(ISD::AND, dl, VT, SRL,
11601           SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12161   case ISD::SRL:
16029   case ISD::SRL:
16392   if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16394   if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17595   case ISD::SRL:            return PerformShiftCombine(N, DAG, DCI, Subtarget);
17658   case ISD::SRL:
17704   case ISD::SRL: {