Cross Reference: /external/llvm/lib/Target/X86/X86ISelLowering.cpp

Lines Matching refs:Op0
3653   SDValue Op0 = SVOp->getOperand(0);
3663     Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3666   return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
6357       SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6365       Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
8687   SDValue Op0 = Op.getOperand(0);
8729     // Op0 is MVT::f32, Op1 is MVT::f64.
8758   SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8868 /// Emit nodes that will be selected as "test Op0,Op0", or something
9079 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9081 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9085       return EmitTest(Op0, X86CC, DAG);
9087   DebugLoc dl = Op0.getDebugLoc();
9088   if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9089        Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9091     SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9093                               Op0, Op1);
9096   return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9132   SDValue Op0 = And.getOperand(0);
9134   if (Op0.getOpcode() == ISD::TRUNCATE)
9135     Op0 = Op0.getOperand(0);
9141     std::swap(Op0, Op1);
9142   if (Op0.getOpcode() == ISD::SHL) {
9143     if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9147         unsigned BitWidth = Op0.getValueSizeInBits();
9151           DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9156         RHS = Op0.getOperand(1);
9161     SDValue AndLHS = Op0;
9243   SDValue Op0 = Op.getOperand(0);
9253     MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
9293       std::swap(Op0, Op1);
9306       SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9308       SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9313     return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9341     std::swap(Op0, Op1);
9354       Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9358       SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9381     Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9385   SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9401   SDValue Op0 = Op.getOperand(0);
9410   if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9414     SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9428     if (Op0.getOpcode() == X86ISD::SETCC) {
9429       X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9432       if (!Invert) return Op0;
9436                          DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9441   unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9445   SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
16412   SDValue Op0 = N0.getOperand(0);
16416     std::swap(Op0, Op1);
16429                            Op0, Op1,
17420   SDValue Op0 = N->getOperand(0);
17421   EVT InVT = Op0->getValueType(0);
17427     SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
17433   if (Op0.getOpcode() == ISD::LOAD) {
17434     LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
17437         ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
17441                                           Ld->getChain(), Op0, DAG);
17442       DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
17518   SDValue Op0 = N->getOperand(0);
17524       isHorizontalBinOp(Op0, Op1, true))
17525     return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
17532   SDValue Op0 = N->getOperand(0);
17537   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
17544       EVT VT = Op0.getValueType();
17557       isHorizontalBinOp(Op0, Op1, true))
17558     return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);