Lines Matching refs:Cond
189 SmallVectorImpl<MachineOperand> &Cond,
222 Cond.push_back(MachineOperand::CreateImm(BranchCode));
223 Cond.push_back(LastInst->getOperand(0));
244 Cond.push_back(MachineOperand::CreateImm(BranchCode));
245 Cond.push_back(SecondLastInst->getOperand(0));
277 const SmallVectorImpl<MachineOperand> &Cond,
281 assert((Cond.size() == 2 || Cond.size() == 0) &&
285 if (Cond.empty()) {
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
298 assert(Cond.size() == 2 && "Unexpected number of components!");
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
401 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
402 assert((Cond.size() == 2) &&
404 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));