Lines Matching refs:VA
820 /* The VA field in a VA, VX or VXR form instruction. */
821 #define VA UI + 1
824 /* The VB field in a VA, VX or VXR form instruction. */
825 #define VB VA + 1
828 /* The VC field in a VA form instruction. */
832 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
846 /* The SHB field in a VA form instruction. */
1723 /* An VA form instruction. */
1726 /* The mask for an VA form instruction. */
2184 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2185 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2186 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2187 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2188 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2189 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2190 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2191 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2192 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2193 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2194 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2195 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2196 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2197 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2198 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2199 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2200 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2201 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2202 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2205 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2206 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2207 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2208 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2209 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2210 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2211 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2212 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2213 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2214 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2215 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2216 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2217 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2218 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2219 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2220 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2221 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2222 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2223 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2224 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2225 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2226 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2227 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2228 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2229 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2230 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2235 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2236 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2237 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2238 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2239 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2240 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2241 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2242 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2243 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2244 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2245 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2246 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2247 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2248 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2249 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2250 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2251 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2252 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2253 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2254 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2255 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2256 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2257 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2258 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2259 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2260 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2261 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2262 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2263 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2264 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2265 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2266 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2267 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2268 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2269 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2270 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2271 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2272 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2273 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2274 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2275 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2276 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2277 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2278 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2279 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2280 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2281 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2282 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2283 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2284 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2285 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2291 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2292 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2293 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2295 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2296 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2297 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2298 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2299 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2300 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2301 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2308 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2309 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2310 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2311 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2312 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2313 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2314 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2315 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2316 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2317 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2318 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2319 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2320 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2321 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2322 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2323 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2324 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2325 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2326 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2327 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2328 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2329 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2330 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2331 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2338 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },