Lines Matching defs:not
24 along with this program; if not, write to the Free Software
58 * some of the FCOM cases could do with testing -- not convinced
61 * FSAVE does not re-initialise the FPU; it should do
63 * FINIT not only initialises the FPU environment, it also zeroes
73 This module uses global variables and so is not MT-safe (if that
137 jump. It's not such a big deal with casLE since the side exit is
159 dis_Grp3 (not, neg)
195 /* Pointer to the guest code area (points to start of BB, not to the
505 bits, which is not a complete register number. You should avoid
590 if this is called with size==8. Should not happen. */
645 * if REX is not present then REXW,REXR,REXX,REXB will read
647 * F2 and F3 will not both be 1.
670 /* The extra register field VEX.vvvv is encoded (after not-ing it) as
805 The 0xF0000000 isn't significant, except so as to make it not
833 e component refers to a register and not to memory).
849 do not refer to %ah %ch %dh %bh but instead to the lowest 8 bits of
1943 if taddr is not IRTemp_INVALID, then a store (using taddr as
1949 if texpVal is not IRTemp_INVALID then a cas-style store is
2387 this fn should not be called if the R/M part of the address denotes
2397 length of the amode itself and does not include the value supplied
2428 /* REX.B==0: (%rax) .. (%rdi), not including (%rsp) or (%rbp).
2429 REX.B==1: (%r8) .. (%r15), not including (%r12) or (%r13).
2440 /* REX.B==0: d8(%rax) ... d8(%rdi), not including d8(%rsp)
2441 REX.B==1: d8(%r8) ... d8(%r15), not including d8(%r12)
2458 /* REX.B==0: d32(%rax) ... d32(%rdi), not including d32(%rsp)
2459 REX.B==1: d32(%r8) ... d32(%r15), not including d32(%r12)
2476 vpanic("disAMode(amd64): not an addr!");
2695 /* REX.B==0: (%rax) .. (%rdi), not including (%rsp) or (%rbp).
2696 REX.B==1: (%r8) .. (%r15), not including (%r12) or (%r13).
2702 /* REX.B==0: d8(%rax) ... d8(%rdi), not including d8(%rsp)
2703 REX.B==1: d8(%r8) ... d8(%r15), not including d8(%r12)
2709 /* REX.B==0: d32(%rax) ... d32(%rdi), not including d32(%rsp)
2710 REX.B==1: d32(%r8) ... d32(%r15), not including d32(%r12)
2774 If E is mem and OP is not reversible,
3422 /* Call a helper; this insn is so ridiculous it does not deserve
3685 Intel docs do however not indicate any use for 0 .. 3, so
3876 DIP("not%c %s\n", nameISize(sz),
3959 DIP("not%c %s\n", nameISize(sz), dis_buf);
4779 state of the register is not checked. */
4880 Need to check ST(0)'s tag on read, but not on write.
4906 Need to check ST(0)'s tag on read, but not on write.
4932 Check dst and src tags when reading but not on write.
4951 Check dst and src tags when reading but not on write.
5402 regardless of whether the tag says it's empty or not.
5571 case 0xF8: { /* FPREM -- not IEEE compliant */
6338 is not generated. Hence put_ST_UNCHECKED. */
6347 is not generated. Hence put_ST_UNCHECKED. */
6608 /* not really right since COMIP != UCOMIP */
6688 sense that it does not first call do_MMX_preamble() -- that is the
7442 supplies bits to be shifted into the E-part, but is not
7579 /* Handle BT/BTS/BTR/BTC Gv, Ev. Apparently b-size is not
7788 /* First, widen src to 64 bits if it is not already. */
7978 reg-mem, not locked: ignore any lock prefix, generate sequence
8132 reg-mem, not locked: ignore any lock prefix, generate 'naive'
8292 /* Worker function; do not call directly.
8293 Handles full width G = G `op` E and G = (not G) `op` E.
8341 /* All lanes SSE binary operation, G = (not G) `op` E. */
8596 Bool not = False;
8598 # define XXX(_pre, _op, _not) { pre = _pre; op = _op; not = _not; }
8695 *preSwapP = pre; *opP = op; *postNotP = not;
9099 /* Helper for the SSSE3 (not SSE3) PMULHRSW insns. Given two 64-bit
9170 /* Helper for the SSSE3 (not SSE3) PSIGN{B,W,D} insns. Given two 64-bit
9210 /* Helper for the SSSE3 (not SSE3) PABS{B,W,D} insns. Given a 64-bit
9346 if effective_addr is not 16-aligned. This is required behaviour
9423 F6 /2 = not rm8
9424 F7 /2 = not rm32 and not rm16
10294 /* FIXME: why not just use InterleaveLO / InterleaveHI? I think the
10310 /* FIXME: why not just use InterleaveLO / InterleaveHI ?? */
11310 /* fall through; apparently reg-reg is not possible */
11449 /* fall through; apparently reg-reg is not possible */
11786 to MMX mode even if 64-bit operand is M64 and not MMX. At
12003 present, a 64-bit register is written; when not present, only
12102 /* 0F 55 = ANDNPS -- G = (not G) and E */
12108 /* 66 0F 55 = ANDNPD -- G = (not G) and E */
13016 images are packed back-to-back. If not, the settings for
13027 not bothering with the FPU DP and IP fields. */
13095 images are packed back-to-back. If not, the settings for
13417 /* F2 0F D6 = MOVDQ2Q -- move from E (lo half xmm, not mem) to G (mmx). */
13656 Intel manual does not say anything about the usual business of
14019 /*--- Top-level SSE3 (not SupSSE3): dis_ESC_0F__SSE3 ---*/
15491 Set C=1 iff (vecE & not vecG) == 0
15494 /* andV, andnV: vecE & vecG, vecE and not(vecG) */
15622 Set C=1 iff (vecE & not vecG) == 0
15625 /* andV, andnV: vecE & vecG, vecE and not(vecG) */
15671 Set C=1 iff (vecE & not vecG) == 0
15674 /* andV, andnV: vecE & vecG, vecE and not(vecG) */
16096 /* It's not really a dirty call, but we can't use the clean
16171 /* Who ya gonna call? Presumably not Ghostbusters. */
16188 /* It's not really a dirty call, but we can't use the clean
16640 /* F2 0F 38 F0 /r = CRC32 r/m8, r32 (REX.W ok, 66 not ok)
16671 mask off the upper 32 bits so as to not get memcheck false
16917 cases for which the helper function has not been verified. */
16932 /* Who ya gonna call? Presumably not Ghostbusters. */
16952 /* It's not really a dirty call, but we can't use the clean helper
18001 not by any means a complete implementation.)
18367 /* Note, sz==4 is not possible in 64-bit mode. Hence ... */
18380 /* Note, sz==4 is not possible in 64-bit mode. Hence ... */
18405 case 0x73: /* JNBb/JAEb (jump not below) */
18407 case 0x75: /* JNZb/JNEb (jump not zero) */
18409 case 0x77: /* JNBEb/JAb (jump not below or equal) */
18411 case 0x79: /* JSb (jump not negative) */
18452 /* Speculation: assume this forward branch is not taken. So
18463 comment = "(assumed not taken)";
18639 /* "observe" the hint. The Vex client needs to be careful not
18648 /* If REX.B is 1, we're not exchanging rAX with itself */
19093 for the second operand (nesting depth) are not handled. */
19247 address size override, not the operand one. */
19713 am not sure if that translates in to SEGV or to something
19796 case 0x43: /* CMOVNBb/CMOVAEb (cmov not below) */
19798 case 0x45: /* CMOVNZb/CMOVNEb (cmov not zero) */
19800 case 0x47: /* CMOVNBEb/CMOVAb (cmov not below or equal) */
19802 case 0x49: /* CMOVSb (cmov not negative) */
19816 case 0x83: /* JNBb/JAEb (jump not below) */
19818 case 0x85: /* JNZb/JNEb (jump not zero) */
19820 case 0x87: /* JNBEb/JAb (jump not below or equal) */
19822 case 0x89: /* JSb (jump not negative) */
19863 /* Speculation: assume this forward branch is not taken.
19876 comment = "(assumed not taken)";
19892 case 0x93: /* set-NBb/set-AEb (set if not below) */
19894 case 0x95: /* set-NZb/set-NEb (set if not zero) */
19896 case 0x97: /* set-NBEb/set-Ab (set if not below or equal) */
19898 case 0x99: /* set-Sb (set if not negative) */
19999 getIRegCL(), False, /* not literal */
20023 getIRegCL(), False, /* not literal */
20250 /* Sheesh. Aren't you glad it was me and not you that had to
20580 but not both. */
21072 argR, which is not correct. */
21242 but not both. */
22500 /* VANDNPD r/m, rV, r ::: r = (not rV) & r/m */
23109 vassert(sz == 2); /* even tho we are transferring 4, not 2. */
23134 vassert(sz == 2); /* even tho we are transferring 8, not 2. */
23524 vassert(sz == 4); /* even tho we are transferring 8, not 4. */
26412 not by any means a complete implementation.)
27023 not been executed, and (is currently) the next to be executed.
27031 /* We also need to say that a CAS is not expected now, regardless
27034 SIGILL) does not involve any CAS, and presumably no other IR has