Lines Matching refs:isLoad
490 void dtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
492 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, op2);
495 void dtr_ur(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
497 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP | OP2_OFSREG, rd, rb, rm);
500 void dtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
502 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0), rd, rb, op2);
505 void dtr_dr(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
507 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | OP2_OFSREG, rd, rb, rm);
530 void fdtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
533 emitInst(static_cast<ARMWord>(cc) | FDTR | DT_UP | (isLoad ? DT_LOAD : 0), rd, rb, op2);
536 void fdtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
539 emitInst(static_cast<ARMWord>(cc) | FDTR | (isLoad ? DT_LOAD : 0), rd, rb, op2);
888 void dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset, bool bytes = false);
889 void baseIndexTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
890 void doubleTransfer(bool isLoad, FPRegisterID srcDst, RegisterID base, int32_t offset);