Searched defs:rm (Results 76 - 100 of 112) sorted by relevance

12345

/external/qemu/tcg/x86_64/
H A Dtcg-target.c238 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) argument
245 rex |= (rm & 8) >> 3; /* REX.B */
253 rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
264 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) argument
266 tcg_out_opc(s, opc, r, rm, 0);
267 tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
270 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
271 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, argument
274 if (rm <
320 tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm, int index, int shift, tcg_target_long offset) argument
[all...]
/external/sepolicy/tools/
H A Dcheck_seapp.c431 * @param rm
434 static void rule_map_free(rule_map *rm, rule_map_switch s) { argument
437 int len = rm->length;
439 key_map *m = &(rm->m[i]);
445 if(s == rule_map_destroy_key && rm->key)
446 free(rm->key);
449 free(rm);
712 * @param rm
758 * @param rm
761 static void rule_add(rule_map *rm) { argument
[all...]
/external/v8/src/arm/
H A Dassembler-arm.cc183 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { argument
186 rm_ = rm;
199 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { argument
201 rm_ = rm;
215 MemOperand::MemOperand(Register rn, Register rm, AddrMode am) { argument
217 rm_ = rm;
224 MemOperand::MemOperand(Register rn, Register rm, argument
228 rm_ = rm;
255 // blxcc rm
1162 ASSERT(!(src.is_reg() && src.rm()
[all...]
H A Dassembler-arm.h410 // rm
411 INLINE(explicit Operand(Register rm));
413 // rm <shift_op> shift_imm
414 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
416 // rm <shift_op> rs
417 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
435 Register rm() const { return rm_; } function in class:v8::internal::BASE_EMBEDDED
461 // [rn +/- rm] Offset/NegOffset
462 // [rn +/- rm]! PreIndex/NegPreIndex
463 // [rn], +/- rm PostInde
483 Register rm() const { return rm_; } function in class:v8::internal::BASE_EMBEDDED
[all...]
/external/v8/src/ia32/
H A Ddisasm-ia32.cc335 static void get_modrm(byte data, int* mod, int* regop, int* rm) { argument
338 *rm = data & 7;
391 int mod, regop, rm; local
392 get_modrm(*modrmp, &mod, &regop, &rm);
397 if (rm == ebp) {
401 } else if (rm == esp) {
406 AppendToBuffer("[%s]", (this->*register_name)(rm));
427 AppendToBuffer("[%s]", (this->*register_name)(rm));
433 if (rm == esp) {
439 if (index == base && index == rm /*es
491 int mod, regop, rm; local
519 int mod, regop, rm; local
548 int mod, regop, rm; local
581 int mod, regop, rm; local
961 { int mod, regop, rm; local
975 int mod, regop, rm; local
998 int mod, regop, rm; local
1027 int mod, regop, rm; local
1035 int mod, regop, rm; local
1056 int mod, regop, rm; local
1073 int mod, regop, rm; local
1084 int mod, regop, rm; local
1122 int mod, regop, rm; local
1141 int mod, regop, rm; local
1167 int mod, regop, rm; local
1178 int mod, regop, rm; local
1187 int mod, regop, rm; local
1198 int mod, regop, rm; local
1208 int mod, regop, rm; local
1218 int mod, regop, rm; local
1228 int mod, regop, rm; local
1242 int mod, regop, rm; local
1255 int mod, regop, rm; local
1263 int mod, regop, rm; local
1271 int mod, regop, rm; local
1279 int mod, regop, rm; local
1285 int mod, regop, rm; local
1291 int mod, regop, rm; local
1304 int mod, regop, rm; local
1312 int mod, regop, rm; local
1323 int mod, regop, rm; local
1332 int mod, regop, rm; local
1338 int mod, regop, rm; local
1345 int mod, regop, rm; local
1353 int mod, regop, rm; local
1364 int mod, regop, rm; local
1372 int mod, regop, rm; local
1388 int mod, regop, rm; local
1445 int mod, regop, rm; local
1451 int mod, regop, rm; local
1457 int mod, regop, rm; local
1473 int mod, regop, rm; local
1514 int mod, regop, rm; local
1520 int mod, regop, rm; local
1526 int mod, regop, rm; local
1532 int mod, regop, rm; local
1538 int mod, regop, rm; local
1545 int mod, regop, rm; local
[all...]
/external/valgrind/main/none/tests/amd64/
H A Dsse4-64.c2445 UInt rm; local
2472 rm = get_sse_roundingmode();
2473 assert(rm == 0); // 0 == RN == default
2478 for (rm = 0; rm <= 3; rm++) {
2479 set_sse_roundingmode(rm);
2485 printf("r (rm=%u) roundsd_1XX ", rm);
2496 printf("m (rm
2761 UInt rm; local
3092 UInt rm; local
3459 UInt rm; local
[all...]
/external/clang/lib/StaticAnalyzer/Core/
H A DRegionStore.cpp617 ClusterAnalysis(RegionStoreManager &rm, ProgramStateManager &StateMgr, argument
619 : RM(rm), Ctx(StateMgr.getContext()),
876 invalidateRegionsWorker(RegionStoreManager &rm, argument
884 : ClusterAnalysis<invalidateRegionsWorker>(rm, stateMgr, b, includeGlobals),
2033 removeDeadBindingsWorker(RegionStoreManager &rm, argument
2037 : ClusterAnalysis<removeDeadBindingsWorker>(rm, stateMgr, b,
/external/icu4c/tools/gennorm2/
H A Dn2builder.cpp709 UnicodeString &rm=*p->rawMapping; local
710 int32_t rmLength=rm.length();
718 UChar rm0=rm.charAt(0);
721 0==rm.compare(1, 99, m, 2, 99) &&
735 dataString.append(rm);
/external/qemu/
H A Darm-dis.c2070 const char *rm = arm_regnames [given & 0xf]; local
2078 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
2090 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
2285 int rm = ((given >> 0) & 0xf); local
2304 if (rm == 0xd)
2306 else if (rm != 0xf)
2307 func (stream, ", %s", arm_regnames[rm]);
2315 int rm = ((given >> 0) & 0xf); local
2379 if (rm == 0xd)
2381 else if (rm !
2390 int rm = ((given >> 0) & 0xf); local
[all...]
/external/qemu/target-arm/
H A Dneon_helper.c1840 void HELPER(neon_qunzip8)(uint32_t rd, uint32_t rm) argument
1842 uint64_t zm0 = float64_val(env->vfp.regs[rm]);
1843 uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
1862 env->vfp.regs[rm] = make_float64(m0);
1863 env->vfp.regs[rm + 1] = make_float64(m1);
1868 void HELPER(neon_qunzip16)(uint32_t rd, uint32_t rm) argument
1870 uint64_t zm0 = float64_val(env->vfp.regs[rm]);
1871 uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
1882 env->vfp.regs[rm] = make_float64(m0);
1883 env->vfp.regs[rm
1888 neon_qunzip32(uint32_t rd, uint32_t rm) argument
1904 neon_unzip8(uint32_t rd, uint32_t rm) argument
1920 neon_unzip16(uint32_t rd, uint32_t rm) argument
1932 neon_qzip8(uint32_t rd, uint32_t rm) argument
1960 neon_qzip16(uint32_t rd, uint32_t rm) argument
1980 neon_qzip32(uint32_t rd, uint32_t rm) argument
1996 neon_zip8(uint32_t rd, uint32_t rm) argument
2012 neon_zip16(uint32_t rd, uint32_t rm) argument
[all...]
H A Dtranslate.c855 int val, rm, shift, shiftop; local
867 rm = (insn) & 0xf;
870 offset = load_reg(s, rm);
883 int val, rm; local
898 rm = (insn) & 0xf;
899 offset = load_reg(s, rm);
2727 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; local
2965 rm = VFP_SREG_M(insn);
2967 VFP_DREG_M(rm, insn);
2980 rm
3687 gen_neon_unzip(int rd, int rm, int size, int q) argument
3726 gen_neon_zip(int rd, int rm, int size, int q) argument
3829 int rd, rn, rm; local
4420 int rd, rn, rm; local
6417 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; local
7782 uint32_t rd, rn, rm, rs; local
8852 uint32_t val, insn, op, rm, rn, rd, shift, cond; local
[all...]
/external/qemu/tcg/arm/
H A Dtcg-target.c385 int cond, int opc, int rd, int rn, int rm, int shift)
388 (rn << 16) | (rd << 12) | shift | rm);
453 int cond, int rd, int rs, int rm)
455 if (rd != rm)
457 (rs << 8) | 0x90 | rm); local
460 (rm << 8) | 0x90 | rs);
463 (rs << 8) | 0x90 | rm); local
470 int cond, int rd0, int rd1, int rs, int rm)
472 if (rd0 != rm && rd1 != rm)
384 tcg_out_dat_reg(TCGContext *s, int cond, int opc, int rd, int rn, int rm, int shift) argument
452 tcg_out_mul32(TCGContext *s, int cond, int rd, int rs, int rm) argument
469 tcg_out_umull32(TCGContext *s, int cond, int rd0, int rd1, int rs, int rm) argument
486 tcg_out_smull32(TCGContext *s, int cond, int rd0, int rd1, int rs, int rm) argument
620 tcg_out_ld32_r(TCGContext *s, int cond, int rd, int rn, int rm) argument
627 tcg_out_st32_r(TCGContext *s, int cond, int rd, int rn, int rm) argument
635 tcg_out_ld32_rwb(TCGContext *s, int cond, int rd, int rn, int rm) argument
642 tcg_out_st32_rwb(TCGContext *s, int cond, int rd, int rn, int rm) argument
675 tcg_out_ld16u_r(TCGContext *s, int cond, int rd, int rn, int rm) argument
682 tcg_out_st16_r(TCGContext *s, int cond, int rd, int rn, int rm) argument
702 tcg_out_ld16s_r(TCGContext *s, int cond, int rd, int rn, int rm) argument
731 tcg_out_ld8_r(TCGContext *s, int cond, int rd, int rn, int rm) argument
738 tcg_out_st8_r(TCGContext *s, int cond, int rd, int rn, int rm) argument
758 tcg_out_ld8s_r(TCGContext *s, int cond, int rd, int rn, int rm) argument
[all...]
/external/qemu/tcg/i386/
H A Dtcg-target.c351 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) argument
368 rex |= (rm & 8) >> 3; /* REX.B */
376 rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
401 #define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc)
404 static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) argument
406 tcg_out_opc(s, opc, r, rm, 0);
407 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
410 /* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
415 static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, argument
421 if (index < 0 && rm <
499 tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, tcg_target_long offset) argument
[all...]
/external/quake/quake/src/WinQuake/
H A Dgl_rmain.cpp1089 static void setRotateM(float* rm, int rmOffset, argument
1092 rm[rmOffset + 3] = 0;
1093 rm[rmOffset + 7] = 0;
1094 rm[rmOffset + 11]= 0;
1095 rm[rmOffset + 12]= 0;
1096 rm[rmOffset + 13]= 0;
1097 rm[rmOffset + 14]= 0;
1098 rm[rmOffset + 15]= 1;
1103 rm[rmOffset + 5] = c; rm[rmOffse
[all...]
/external/v8/src/mips/
H A Dassembler-mips.h370 INLINE(explicit Operand(Register rm));
375 Register rm() const { return rm_; } function in class:v8::internal::BASE_EMBEDDED
H A Dassembler-mips.cc229 MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) { argument
1342 ASSERT(!src.rm().is(at));
1345 addu(at, at, src.rm()); // Add base register.
1351 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
1361 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
1371 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_);
1381 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_);
1391 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
1400 GenInstrImmediate(LWL, rs.rm(), r
[all...]
/external/v8/src/x64/
H A Ddisasm-x64.cc397 int* rm) {
400 *rm = (data & 7) | (rex_b() ? 8 : 0);
460 int mod, regop, rm; local
461 get_modrm(*modrmp, &mod, &regop, &rm);
466 if ((rm & 7) == 5) {
470 } else if ((rm & 7) == 4) {
499 AppendToBuffer("[%s]", NameOfCPURegister(rm));
505 if ((rm & 7) == 4) {
538 AppendToBuffer("[%s-0x%x]", NameOfCPURegister(rm), -disp);
540 AppendToBuffer("[%s+0x%x]", NameOfCPURegister(rm), dis
394 get_modrm(byte data, int* mod, int* regop, int* rm) argument
610 int mod, regop, rm; local
646 int mod, regop, rm; local
690 int mod, regop, rm; local
735 int mod, regop, rm; local
1022 int mod, regop, rm; local
1112 int mod, regop, rm; local
1123 int mod, regop, rm; local
1130 int mod, regop, rm; local
1137 int mod, regop, rm; local
1144 int mod, regop, rm; local
1156 int mod, regop, rm; local
1167 int mod, regop, rm; local
1174 int mod, regop, rm; local
1182 int mod, regop, rm; local
1187 int mod, regop, rm; local
1196 int mod, regop, rm; local
1211 int mod, regop, rm; local
1218 int mod, regop, rm; local
1237 int mod, regop, rm; local
1258 int mod, regop, rm; local
1442 int mod, regop, rm; local
1465 int mod, regop, rm; local
1476 int mod, regop, rm; local
1540 int mod, regop, rm; local
1609 int mod, regop, rm; local
[all...]
/external/valgrind/main/VEX/priv/
H A Dguest_mips_toIR.c1401 IRExpr *rm = get_IR_roundingmode(); local
1402 putFReg(fd, mkWidenFromF32(tyF, binop(Iop_SqrtF32, rm,
1408 IRExpr *rm = get_IR_roundingmode(); local
1409 putDReg(fd, binop(Iop_SqrtF64, rm, getDReg(fs)));
1436 IRExpr *rm = get_IR_roundingmode(); local
1437 putDReg(fd, triop(Iop_MulF64, rm, getDReg(fs),
1444 IRExpr *rm = get_IR_roundingmode(); local
1445 putFReg(fd, mkWidenFromF32(tyF, triop(Iop_MulF32, rm,
1460 IRExpr *rm = get_IR_roundingmode(); local
1461 putDReg(fd, triop(Iop_DivF64, rm, getDRe
1468 IRExpr *rm = get_IR_roundingmode(); local
1484 IRExpr *rm = get_IR_roundingmode(); local
1491 IRExpr *rm = get_IR_roundingmode(); local
1540 IRExpr *rm = get_IR_roundingmode(); local
1550 IRExpr *rm = get_IR_roundingmode(); local
1762 IRExpr *rm = get_IR_roundingmode(); local
1771 IRExpr *rm = get_IR_roundingmode(); local
2086 IRExpr *rm = get_IR_roundingmode(); local
2096 IRExpr *rm = get_IR_roundingmode(); local
2303 IRExpr *rm = get_IR_roundingmode(); local
2314 IRExpr *rm = get_IR_roundingmode(); local
2323 IRExpr *rm = get_IR_roundingmode(); local
2334 IRExpr *rm = get_IR_roundingmode(); local
2343 IRExpr *rm = get_IR_roundingmode(); local
2357 IRExpr *rm = get_IR_roundingmode(); local
2368 IRExpr *rm = get_IR_roundingmode(); local
2382 IRExpr *rm = get_IR_roundingmode(); local
[all...]
H A Dhost_x86_isel.c1613 X86RM* rm = iselIntExpr_RM_wrk(env, e); local
1615 switch (rm->tag) {
1617 vassert(hregClass(rm->Xrm.Reg.reg) == HRcInt32);
1618 vassert(hregIsVirtual(rm->Xrm.Reg.reg));
1619 return rm;
1621 vassert(sane_AMode(rm->Xrm.Mem.am));
1622 return rm;
1700 X86RM* rm = iselIntExpr_RM(env, e->Iex.Unop.arg); local
1701 addInstr(env, X86Instr_Test32(1,rm));
1710 X86RM* rm local
1720 X86RM* rm = iselIntExpr_RM(env, e->Iex.Unop.arg); local
[all...]
H A Dhost_amd64_isel.c1998 AMD64RM* rm = iselIntExpr_RM_wrk(env, e); local
2000 switch (rm->tag) {
2002 vassert(hregClass(rm->Arm.Reg.reg) == HRcInt64);
2003 vassert(hregIsVirtual(rm->Arm.Reg.reg));
2004 return rm;
2006 vassert(sane_AMode(rm->Arm.Mem.am));
2007 return rm;
/external/kernel-headers/original/asm-x86/
H A Dprocessor_32.h276 unsigned char ftop, changed, lookahead, no_update, rm, alimit; member in struct:i387_soft_struct
/external/webkit/Source/JavaScriptCore/assembler/
H A DARMAssembler.h435 void mul_r(int rd, int rn, int rm, Condition cc = AL) argument
437 m_buffer.putInt(static_cast<ARMWord>(cc) | MUL | RN(rd) | RS(rn) | RM(rm));
440 void muls_r(int rd, int rn, int rm, Condition cc = AL) argument
442 m_buffer.putInt(static_cast<ARMWord>(cc) | MUL | SET_CC | RN(rd) | RS(rn) | RM(rm));
445 void mull_r(int rdhi, int rdlo, int rn, int rm, Condition cc = AL) argument
447 m_buffer.putInt(static_cast<ARMWord>(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
495 void dtr_ur(bool isLoad, int rd, int rb, int rm, Condition cc = AL) argument
497 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP | OP2_OFSREG, rd, rb, rm); local
505 void dtr_dr(bool isLoad, int rd, int rb, int rm, Condition cc = AL) argument
507 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | OP2_OFSREG, rd, rb, rm);
510 ldrh_r(int rd, int rn, int rm, Condition cc = AL) argument
512 emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_UP | DT_PRE, rd, rn, rm); local
525 strh_r(int rn, int rm, int rd, Condition cc = AL) argument
527 emitInst(static_cast<ARMWord>(cc) | STRH | HDT_UH | DT_UP | DT_PRE, rd, rn, rm); local
600 clz_r(int rd, int rm, Condition cc = AL) argument
616 bx(int rm, Condition cc = AL) argument
625 blx(int rm, Condition cc = AL) argument
[all...]
/external/icu4c/test/cintltst/
H A Dcbiditst.c1695 UBiDiReorderingMode rm; local
1758 rm = ubidi_getReorderingMode(bidi);
1760 if (rm != ubidi_getReorderingMode(bidi)) {
1764 if (rm != ubidi_getReorderingMode(bidi)) {
/external/qemu/target-i386/
H A Dop_helper.c1196 int is_hw, int rm)
1206 if (!rm && exeption_has_error_code(intno)) {
1195 handle_even_inj(int intno, int is_int, int error_code, int is_hw, int rm) argument
H A Dtranslate.c1973 int mod, rm, code, override, must_add_seg; local
1980 rm = modrm & 7;
1985 base = rm;
2078 if (rm == 6) {
2082 rm = 0; /* avoid SS override */
2097 switch(rm) {
2134 if (rm == 2 || rm == 3 || rm == 6)
2151 int mod, rm, bas local
2227 int mod, rm, opreg, disp; local
3091 int modrm, mod, rm, reg, reg_addr, offset_addr; local
4045 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val; local
[all...]

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