| /external/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) local
784 MIB.addOperand(MI->getOperand(OpNum));
787 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1082 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), local
1086 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1088 MachineInstrBuilder MIB local
1743 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) local
1757 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) local
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 681 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); local
682 MIB.addReg(SrcReg, getKillRegState(KillSrc));
684 MIB.addReg(SrcReg, getKillRegState(KillSrc));
685 AddDefaultPred(MIB);
751 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, argument
755 return MIB.addReg(Reg, State);
758 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
759 return MIB.addReg(Reg, State, SubIdx);
798 MachineInstrBuilder MIB = local
802 MIB
833 MachineInstrBuilder MIB = local
854 MachineInstrBuilder MIB = local
868 MachineInstrBuilder MIB = local
979 MachineInstrBuilder MIB = local
1010 MachineInstrBuilder MIB = local
1030 MachineInstrBuilder MIB = local
1046 MachineInstrBuilder MIB = local
1195 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) local
1263 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), local
[all...] |
| H A D | ARMFastISel.cpp | 224 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
226 const MachineInstrBuilder &MIB,
272 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { argument
273 MachineInstr *MI = &*MIB;
279 AddDefaultPred(MIB);
286 AddDefaultT1CC(MIB);
288 AddDefaultCC(MIB);
290 return MIB;
672 MachineInstrBuilder MIB; local
675 MIB
692 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
703 MachineInstrBuilder MIB; local
956 AddLoadStoreOperands(MVT VT, Address &Addr, const MachineInstrBuilder &MIB, unsigned Flags, bool useAM3) argument
1090 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, local
1210 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, local
1499 MachineInstrBuilder MIB; local
2169 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, local
2262 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
2403 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
2638 MachineInstrBuilder MIB; local
2876 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
[all...] |
| H A D | ARMISelLowering.cpp | 5741 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); local
5743 MIB.addImm(0);
5744 AddDefaultPred(MIB);
5757 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
5759 MIB.addImm(0);
5760 AddDefaultPred(MIB);
5847 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); local
5849 MIB.addImm(0);
5850 AddDefaultPred(MIB);
5861 MIB
5960 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); local
6389 MachineInstrBuilder MIB; local
6952 MachineInstrBuilder MIB = BuildMI(BB, dl, local
7061 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); local
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 830 MachineInstrBuilder MIB = local
833 MIB.addReg(RetRegs[i], RegState::Implicit);
1914 MachineInstrBuilder MIB; local
1922 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1956 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc));
1958 MIB.addExternalSymbol(MemIntName, OpFlags);
1960 MIB.addGlobalAddress(GV, 0, OpFlags);
1965 MIB.addRegMask(TRI.getCallPreservedMask(CS.getCallingConv()));
1969 MIB.addReg(X86::EBX, RegState::Implicit);
1972 MIB
[all...] |
| H A D | X86InstrInfo.cpp | 1809 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), local
1815 MIB.addReg(0).addImm(1 << ShAmt)
1821 addRegOffset(MIB, leaInReg, true, 1);
1825 addRegOffset(MIB, leaInReg, true, -1);
1831 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1842 addRegReg(MIB, leaInReg, true, leaInReg, false);
1847 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1849 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1852 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1860 MachineInstr *NewMI = MIB;
3013 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); local
3047 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); local
3527 Expand2AddrUndef(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) argument
3580 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); local
3642 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); local
[all...] |
| H A D | X86ISelLowering.cpp | 12984 MachineInstrBuilder MIB; local
12992 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
12997 MIB.addOperand(NewMO);
13008 MIB.addMemOperand(MMO);
13117 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
13120 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13135 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13140 MIB.addOperand(NewMO);
13142 MIB.addReg(t2);
13143 MIB
13270 MachineInstrBuilder MIB; local
13479 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); local
13516 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); local
13543 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); local
14188 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, local
14199 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, local
14210 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, local
14283 MachineInstrBuilder MIB; local
14385 MachineInstrBuilder MIB; local
[all...] |