Searched defs:reg (Results 26 - 46 of 46) sorted by relevance

12

/dalvik/dx/src/com/android/dx/ssa/back/
H A DFirstFitLocalCombiningAllocator.java58 /** indexed by SSA reg; the set of SSA regs we've mapped */
166 for (RegisterSpec reg : e.getValue()) {
168 regs.append(reg.getReg());
271 * Tries to map a list of SSA registers into the a rop reg, marking
372 int reg;
374 reg = reservedRopRegs.nextClearBit(startReg);
379 while (i < width && !reservedRopRegs.get(reg + i)) {
384 return reg;
387 reg = reservedRopRegs.nextClearBit(reg
1072 private final int[] reg; field in class:FirstFitLocalCombiningAllocator.Multiset
[all...]
/dalvik/vm/compiler/codegen/x86/libenc/
H A Denc_wrapper.cpp46 RegName reg = map_of_regno_2_regname[physicalReg]; local
47 if (sz != getRegSize(reg)) {
48 reg = getAliasReg(reg, sz);
50 args.add(EncoderBase::Operand(reg, ext));
110 getRegNameString(opnd.reg()));
208 int reg, bool isPhysical, LowOpndRegType type, char * stream) {
214 add_r(args, reg, size);
225 int reg, bool isPhysical,
227 if((m == Mnemonic_MOV || m == Mnemonic_MOVQ) && reg
207 encoder_reg(Mnemonic m, OpndSize size, int reg, bool isPhysical, LowOpndRegType type, char * stream) argument
224 encoder_reg_reg(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type, char * stream) argument
242 encoder_mem_reg(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical, LowOpndRegType type, char * stream) argument
256 encoder_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type, char * stream) argument
270 encoder_reg_mem_scale(Mnemonic m, OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, LowOpndRegType type, char * stream) argument
285 encoder_mem_disp_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type, char * stream) argument
299 encoder_movzs_mem_disp_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type, char * stream) argument
314 encoder_reg_mem_disp_scale(Mnemonic m, OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, LowOpndRegType type, char* stream) argument
330 encoder_reg_mem(Mnemonic m, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, LowOpndRegType type, char * stream) argument
344 encoder_imm_reg(Mnemonic m, OpndSize size, int imm, int reg, bool isPhysical, LowOpndRegType type, char * stream) argument
392 encoder_fp_mem(Mnemonic m, OpndSize size, int reg, int disp, int base_reg, bool isBasePhysical, char * stream) argument
406 encoder_mem_fp(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, char * stream) argument
432 encoder_compare_fp_stack(bool pop, int reg, bool isDouble, char * stream) argument
447 encoder_movez_mem_to_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical, char * stream) argument
461 encoder_moves_mem_to_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical, char * stream) argument
475 encoder_movez_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type, char * stream) argument
489 encoder_moves_reg_to_reg(OpndSize size, int reg, bool isPhysical,int reg2, bool isPhysical2, LowOpndRegType type, char * stream) argument
[all...]
H A Denc_prvt.h279 unsigned char reg:3; member in struct:ModRM
H A Denc_defs.h705 inline unsigned getRegMask(RegName reg) argument
707 return 1<<(reg&0xff);
712 inline OpndKind getRegKind(RegName reg) argument
714 return (OpndKind)(reg>>24);
719 inline OpndSize getRegSize(RegName reg) argument
721 return (OpndSize)((reg>>16)&0xFF);
726 inline unsigned char getRegIndex(RegName reg) argument
728 return (unsigned char)(reg&0xFF);
734 const char * getRegNameString(RegName reg);
768 inline RegName getAliasReg(RegName reg, OpndSiz argument
[all...]
/dalvik/dx/src/com/android/dx/ssa/
H A DSsaBasicBlock.java103 * {@code null-ok;} indexed by reg: the regs that are live-in at
109 * {@code null-ok;} indexed by reg: the regs that are live-out at
202 * @param reg {@code >=0;} result reg
204 public void addPhiInsnForReg(int reg) { argument
205 insns.add(0, new PhiInsn(reg, this));
213 * @param resultSpec {@code non-null;} reg
671 int reg = rs.getReg();
674 return regsUsed.get(reg)
675 || (category == 2 ? regsUsed.get(reg
[all...]
/dalvik/vm/compiler/codegen/
H A DRallocUtil.cpp62 regs[i].reg = regNums[i];
77 p[i].reg, p[i].inUse, p[i].pair, p[i].partner, p[i].live,
83 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg) argument
89 if (p[i].reg == reg) {
96 if (p[i].reg == reg) {
100 ALOGE("Tried to get info on a non-existant temp: r%d",reg);
110 (info1->partner == info2->reg) &&
111 (info2->partner == info1->reg));
124 dvmCompilerFlushReg(CompilationUnit *cUnit, int reg) argument
136 clobberRegBody(CompilationUnit *cUnit, RegisterInfo *p, int numTemps, int reg) argument
165 dvmCompilerClobber(CompilationUnit *cUnit, int reg) argument
342 dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg) argument
367 dvmCompilerIsLive(CompilationUnit *cUnit, int reg) argument
387 dvmCompilerIsTemp(CompilationUnit *cUnit, int reg) argument
412 dvmCompilerLockTemp(CompilationUnit *cUnit, int reg) argument
437 dvmCompilerResetDef(CompilationUnit *cUnit, int reg) argument
606 regClassMatches(int regClass, int reg) argument
617 dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg) argument
641 dvmCompilerMarkClean(CompilationUnit *cUnit, int reg) argument
647 dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg) argument
653 dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg) argument
[all...]
/dalvik/vm/compiler/codegen/arm/Thumb/
H A DFactory.cpp884 ArmConditionCode cond, int reg,
890 newLIR2(cUnit, kThumbCmpRR, reg, tReg);
893 newLIR2(cUnit, kThumbCmpRI8, reg, checkValue);
883 genCmpImmBranch(CompilationUnit *cUnit, ArmConditionCode cond, int reg, int checkValue) argument
/dalvik/vm/compiler/codegen/mips/Mips32/
H A DFactory.cpp907 MipsConditionCode cond, int reg,
931 branch = opCompareBranch(cUnit, opc, reg, -1);
935 newLIR3(cUnit, kMipsSlti, tReg, reg, checkValue);
906 genRegImmCheck(CompilationUnit *cUnit, MipsConditionCode cond, int reg, int checkValue, int dOffset, MipsLIR *pcrLabel) argument
/dalvik/vm/compiler/codegen/mips/
H A DRallocUtil.cpp64 regs[i].reg = regNums[i];
79 p[i].reg, p[i].inUse, p[i].pair, p[i].partner, p[i].live,
85 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg) argument
91 if (p[i].reg == reg) {
98 if (p[i].reg == reg) {
102 ALOGE("Tried to get info on a non-existant temp: r%d",reg);
112 (info1->partner == info2->reg) &&
113 (info2->partner == info1->reg));
126 flushReg(CompilationUnit *cUnit, int reg) argument
138 clobberRegBody(CompilationUnit *cUnit, RegisterInfo *p, int numTemps, int reg) argument
167 dvmCompilerClobber(CompilationUnit *cUnit, int reg) argument
343 dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg) argument
372 dvmCompilerIsLive(CompilationUnit *cUnit, int reg) argument
392 dvmCompilerIsTemp(CompilationUnit *cUnit, int reg) argument
417 dvmCompilerLockTemp(CompilationUnit *cUnit, int reg) argument
503 dvmCompilerResetDef(CompilationUnit *cUnit, int reg) argument
678 regClassMatches(int regClass, int reg) argument
689 dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg) argument
713 dvmCompilerMarkClean(CompilationUnit *cUnit, int reg) argument
719 dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg) argument
725 dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg) argument
1022 dvmCompilerFlushRegForV5TEVFP(CompilationUnit *cUnit, int reg) argument
[all...]
H A DAssemble.cpp203 ENCODING_MAP(kMipsMove, 0x00000025, /* or using zero reg */
1729 static int selfVerificationMemRegLoad(int* sp, int reg) argument
1732 return *(sp + reg);
1736 static s8 selfVerificationMemRegLoadDouble(int* sp, int reg) argument
1739 return *((s8*)(sp + reg));
1743 static void selfVerificationMemRegStore(int* sp, int data, int reg) argument
1746 *(sp + reg) = data;
1750 static void selfVerificationMemRegStoreDouble(int* sp, s8 data, int reg) argument
1753 *((s8*)(sp + reg)) = data;
H A DMipsLIR.h25 * at is scratch for Jit (normally used as temp reg by assembler)
80 * code that reg locations always describe doubles as a pair of singles.
132 int reg; // Reg number member in struct:RegisterInfo
135 int partner; // If pair, other reg of pair
563 kFmtDfp, /* Double FP reg */
564 kFmtSfp, /* Single FP reg */
/dalvik/vm/compiler/codegen/x86/
H A DLowerInvoke.cpp723 int spill_reg(int reg, bool isPhysical) { argument
725 move_reg_to_mem(OpndSize_32, reg, isPhysical, 0, PhysicalReg_ESP, true);
731 int unspill_reg(int reg, bool isPhysical) { argument
732 move_mem_to_reg(OpndSize_32, 0, PhysicalReg_ESP, true, reg, isPhysical);
H A DAnalysisO1.cpp77 int convertType(int type, int reg, bool isPhysical) { argument
82 /* reg number for a VR can exceed PhysicalReg_SCRATCH_1 */
83 if(reg >= PhysicalReg_SCRATCH_1 && reg < PhysicalReg_GLUE_DVMDEX)
426 ALOGI("REGALLOC: physical reg %d is used by a GG VR %d %d at beginning of BB", tReg, compileTable[k].regNum, compileTable[k].physicalType);
716 ALOGI("sort virtual reg %d type %d -------", bb->infoBasicBlock[kk].regNum,
890 ALOGW("refCount for a temporary reg %d %d is %d after a bytecode", compileTable[k].regNum, compileTable[k].physicalType, compileTable[k].refCount);
1924 inline void loadFromSpillRegion_with_self(OpndSize size, int reg_self, bool selfPhysical, int reg, int offset) { argument
1929 reg, true);
1931 inline void loadFromSpillRegion(OpndSize size, int reg, in argument
1940 saveToSpillRegion_with_self(OpndSize size, int selfReg, bool selfPhysical, int reg, int offset) argument
1946 saveToSpillRegion(OpndSize size, int reg, int offset) argument
1955 loadFromSpillRegion(OpndSize size, int reg, int offset) argument
1962 saveToSpillRegion(OpndSize size, int reg, int offset) argument
2061 invalidateVRDueToConst(int reg, OpndSize size) argument
2129 invalidateVR(int reg, LowOpndRegType pType) argument
2213 updateVirtualReg(int reg, LowOpndRegType pType) argument
2289 registerAlloc(int type, int reg, bool isPhysical, bool updateRefCount) argument
2368 registerAllocMove(int reg, int type, bool isPhysical, int srcReg) argument
2400 getFreeReg(int type, int reg, int indexToCompileTable) argument
[all...]
H A DLowerJump.cpp73 //assume size of "jump reg" is 2
600 \brief generate a single native instruction "jmp reg"
603 void unconditional_jump_reg(int reg, bool isPhysical) { argument
604 dump_reg(Mnemonic_JMP, ATOM_NORMAL, OpndSize_32, reg, isPhysical, LowOpndRegType_gp);
630 void call_reg(int reg, bool isPhysical) { argument
632 dump_reg(m, ATOM_NORMAL, OpndSize_32, reg, isPhysical, LowOpndRegType_gp);
634 void call_reg_noalloc(int reg, bool isPhysical) { argument
636 dump_reg_noalloc(m, OpndSize_32, reg, isPhysical, LowOpndRegType_gp);
643 void call_mem(int disp, int reg, bool isPhysical) { argument
645 dump_mem(m, ATOM_NORMAL, OpndSize_32, disp, reg, isPhysica
[all...]
H A DLowerHelper.cpp110 void set_reg_opnd(LowOpndReg* op_reg, int reg, bool isPhysical, LowOpndRegType type) { argument
114 op_reg->physicalReg = reg;
117 op_reg->logicalReg = reg;
291 //!update fields of LowOp and generate a x86 instruction that takes a single reg operand
295 int reg, LowOpndRegType type) {
296 stream = encoder_reg(m, size, reg, true, type, stream);
301 int reg, bool isPhysical, LowOpndRegType type) {
309 int regAll = registerAlloc(type, reg, isPhysical, true);
312 stream = encoder_reg(m, size, reg, isPhysical, type, stream);
317 int reg, boo
294 lower_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, LowOpndRegType type) argument
300 dump_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, LowOpndRegType type) argument
316 dump_reg_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, LowOpndRegType type) argument
321 lower_reg_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, int reg2, LowOpndRegType type) argument
336 dump_reg_reg_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
350 dump_reg_reg_noalloc_dst(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
366 dump_reg_reg_noalloc_src(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
387 dump_reg_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
420 lower_mem_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int disp, int base_reg, MemoryAccessType mType, int mIndex, int reg, LowOpndRegType type, bool isMoves) argument
442 dump_mem_reg_noalloc(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical, LowOpndRegType type) argument
451 dump_mem_reg_noalloc_mem(Mnemonic m, AtomOpCode m2, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical, LowOpndRegType type) argument
467 dump_mem_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical, LowOpndRegType type) argument
493 dump_moves_mem_reg(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
513 dump_movez_mem_reg(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
534 dump_movez_reg_reg(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
566 lower_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, int disp, int index_reg, int scale, int reg, LowOpndRegType type) argument
583 dump_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type) argument
611 lower_reg_mem_scale(Mnemonic m, OpndSize size, int reg, int base_reg, int disp, int index_reg, int scale, LowOpndRegType type) argument
622 dump_reg_mem_scale(Mnemonic m, OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, LowOpndRegType type) argument
645 lower_reg_mem(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, int disp, int base_reg, MemoryAccessType mType, int mIndex, LowOpndRegType type) argument
652 dump_reg_mem_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, LowOpndRegType type) argument
661 dump_reg_mem(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, LowOpndRegType type) argument
681 lower_imm_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int imm, int reg, LowOpndRegType type, bool chaining) argument
687 dump_imm_reg_noalloc(Mnemonic m, OpndSize size, int imm, int reg, bool isPhysical, LowOpndRegType type) argument
694 dump_imm_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int imm, int reg, bool isPhysical, LowOpndRegType type, bool chaining) argument
746 lower_fp_mem(Mnemonic m, OpndSize size, int reg, int disp, int base_reg, MemoryAccessType mType, int mIndex) argument
752 dump_fp_mem(Mnemonic m, OpndSize size, int reg, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex) argument
767 lower_mem_fp(Mnemonic m, OpndSize size, int disp, int base_reg, MemoryAccessType mType, int mIndex, int reg) argument
773 dump_mem_fp(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg) argument
796 load_effective_addr(int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
805 load_effective_addr_scale(int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
873 compare_reg_mem(LowOp* op, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
881 compare_mem_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
890 compare_VR_reg_all(OpndSize size, int vA, int reg, bool isPhysical, Mnemonic m) argument
954 compare_VR_reg(OpndSize size, int vA, int reg, bool isPhysical) argument
960 compare_VR_ss_reg(int vA, int reg, bool isPhysical) argument
964 compare_VR_sd_reg(int vA, int reg, bool isPhysical) argument
1078 compare_imm_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1145 compare_ss_mem_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1162 compare_sd_mem_with_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1179 compare_fp_stack(bool pop, int reg, bool isDouble) argument
1200 test_imm_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1206 test_imm_mem(OpndSize size, int imm, int disp, int reg, bool isPhysical) argument
1212 alu_unary_reg(OpndSize size, ALU_Opcode opc, int reg, bool isPhysical) argument
1245 alu_binary_imm_reg(OpndSize size, ALU_Opcode opc, int imm, int reg, bool isPhysical) argument
1256 alu_binary_mem_reg(OpndSize size, ALU_Opcode opc, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1267 alu_sd_binary_VR_reg(ALU_Opcode opc, int vA, int reg, bool isPhysical, bool isSD) argument
1320 alu_binary_VR_reg(OpndSize size, ALU_Opcode opc, int vA, int reg, bool isPhysical) argument
1382 alu_binary_reg_mem(OpndSize size, ALU_Opcode opc, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1402 alu_ss_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1410 alu_sd_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1418 push_reg_to_stack(OpndSize size, int reg, bool isPhysical) argument
1430 move_reg_to_mem(OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1439 move_reg_to_mem_noalloc(OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex) argument
1449 move_mem_to_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1458 move_mem_to_reg_noalloc(OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical) argument
1468 move_ss_mem_to_reg_noalloc(int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical) argument
1476 move_ss_reg_to_mem_noalloc(int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex) argument
1484 movez_mem_to_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1494 movez_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1501 movez_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1509 moves_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1521 moves_mem_to_reg(LowOp* op, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1530 move_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1539 move_reg_to_reg_noalloc(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1548 move_mem_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1555 move_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1565 move_reg_to_mem_scale(OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale) argument
1573 move_reg_to_mem_disp_scale(OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale) argument
1638 move_chain_to_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1645 move_imm_to_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1654 move_imm_to_reg_noalloc(OpndSize size, int imm, int reg, bool isPhysical) argument
1663 conditional_move_reg_to_reg(OpndSize size, ConditionCode cc, int reg1, bool isPhysical1, int reg, bool isPhysical) argument
1670 move_ss_mem_to_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1678 move_ss_reg_to_mem(LowOp* op, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1685 move_sd_mem_to_reg(int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1692 move_sd_reg_to_mem(LowOp* op, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1701 get_virtual_reg_all(u2 vB, OpndSize size, int reg, bool isPhysical, Mnemonic m) argument
1788 get_virtual_reg(u2 vB, OpndSize size, int reg, bool isPhysical) argument
1792 get_virtual_reg_noalloc(u2 vB, OpndSize size, int reg, bool isPhysical) argument
1802 set_virtual_reg_all(u2 vA, OpndSize size, int reg, bool isPhysical, Mnemonic m) argument
1861 set_virtual_reg(u2 vA, OpndSize size, int reg, bool isPhysical) argument
1865 set_virtual_reg_noalloc(u2 vA, OpndSize size, int reg, bool isPhysical) argument
1870 get_VR_ss(int vB, int reg, bool isPhysical) argument
1873 set_VR_ss(int vA, int reg, bool isPhysical) argument
1876 get_VR_sd(int vB, int reg, bool isPhysical) argument
1879 set_VR_sd(int vA, int reg, bool isPhysical) argument
1886 get_currentpc(int reg, bool isPhysical) argument
1893 simpleNullCheck(int reg, bool isPhysical, int vr) argument
1934 nullCheck(int reg, bool isPhysical, int exceptionNum, int vr) argument
2009 get_self_pointer(int reg, bool isPhysical) argument
2016 get_res_strings(int reg, bool isPhysical) argument
2044 get_res_classes(int reg, bool isPhysical) argument
2069 get_res_fields(int reg, bool isPhysical) argument
2094 get_res_methods(int reg, bool isPhysical) argument
2119 get_glue_method_class(int reg, bool isPhysical) argument
2128 get_glue_method(int reg, bool isPhysical) argument
2136 set_glue_method(int reg, bool isPhysical) argument
2145 get_glue_dvmdex(int reg, bool isPhysical) argument
2170 set_glue_dvmdex(int reg, bool isPhysical) argument
2178 get_suspendCount(int reg, bool isPhysical) argument
2187 get_return_value(OpndSize size, int reg, bool isPhysical) argument
2195 set_return_value(OpndSize size, int reg, bool isPhysical) argument
2211 get_exception(int reg, bool isPhysical) argument
2219 set_exception(int reg, bool isPhysical) argument
2239 savearea_from_fp(int reg, bool isPhysical) argument
[all...]
/dalvik/vm/compiler/codegen/arm/Thumb2/
H A DFactory.cpp1166 ArmConditionCode cond, int reg,
1171 if ((LOWREG(reg)) && (checkValue == 0) &&
1175 reg, 0);
1178 if (LOWREG(reg) && ((checkValue & 0xff) == checkValue)) {
1179 newLIR2(cUnit, kThumbCmpRI8, reg, checkValue);
1181 newLIR2(cUnit, kThumb2CmpRI8, reg, modImm);
1185 opRegReg(cUnit, kOpCmp, reg, tReg);
1165 genCmpImmBranch(CompilationUnit *cUnit, ArmConditionCode cond, int reg, int checkValue) argument
/dalvik/dexdump/
H A DDexDump.cpp627 static void dumpLocalsCb(void *cnxt, u2 reg, u4 startAddress, argument
631 printf(" 0x%04x - 0x%04x reg=%d %s %s %s\n",
632 startAddress, endAddress, reg, name, descriptor,
/dalvik/vm/compiler/codegen/arm/
H A DAssemble.cpp2358 static int selfVerificationMemRegLoad(int* sp, int reg) argument
2360 return *(sp + reg);
2364 static s8 selfVerificationMemRegLoadDouble(int* sp, int reg) argument
2366 return *((s8*)(sp + reg));
2370 static void selfVerificationMemRegStore(int* sp, int data, int reg) argument
2372 *(sp + reg) = data;
2376 static void selfVerificationMemRegStoreDouble(int* sp, s8 data, int reg) argument
2378 *((s8*)(sp + reg)) = data;
H A DArmLIR.h79 * code that reg locations always describe doubles as a pair of singles.
103 int reg; // Reg number member in struct:RegisterInfo
106 int partner; // If pair, other reg of pair
713 kFmtDfp, /* Double FP reg */
714 kFmtSfp, /* Single FP reg */
/dalvik/vm/
H A DDebugger.cpp209 static ObjectId registerObject(const Object* obj, RegistryType type, bool reg) argument
220 if (!reg)
1381 static void variableTableCb (void *cnxt, u2 reg, u4 startAddress, argument
1387 reg = (u2) tweakSlot(reg, name);
1391 name, descriptor, reg);
1400 expandBufAdd4BE(pContext->pReply, reg);
/dalvik/vm/analysis/
H A DCodeVerify.cpp1592 //ALOGD("check-reg v%u = %d", vsrc, checkType);
1656 LOG_VFY("VFY: uninitialized ref not expected as reg check");
2196 static RegType adjustForRightShift(RegisterLine* registerLine, int reg, argument
2199 RegType srcType = getRegisterType(registerLine, reg);
2844 LOG_VFY_METH(meth, "Invalid reg type for array index (%d)",
4304 /* resClass can be null if the reg type is Zero */
4642 LOG_VFY("VFY: invalid reg type %d on aput instr (need %d)",
4652 /* resClass can be null if the reg type is Zero */
4915 LOG_VFY("VFY: invalid reg type %d on iput instr (need %d)",
5181 LOG_VFY("VFY: invalid reg typ
5854 int reg = RESULT_REGISTER(insnRegCount); local
6064 logLocalsCb(void *cnxt, u2 reg, u4 startAddress, u4 endAddress, const char *name, const char *descriptor, const char *signature) argument
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