/external/v8/src/arm/ |
H A D | macro-assembler-arm.cc | 228 void MacroAssembler::Swap(Register reg1, argument 233 eor(reg1, reg1, Operand(reg2), LeaveCC, cond); 234 eor(reg2, reg2, Operand(reg1), LeaveCC, cond); 235 eor(reg1, reg1, Operand(reg2), LeaveCC, cond); 237 mov(scratch, reg1, LeaveCC, cond); 238 mov(reg1, reg2, LeaveCC, cond); 2948 void MacroAssembler::JumpIfNotBothSmi(Register reg1, 2952 tst(reg1, Operan [all...] |
H A D | regexp-macro-assembler-arm.cc | 435 void RegExpMacroAssemblerARM::CheckNotRegistersEqual(int reg1, argument 438 __ ldr(r0, register_location(reg1));
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/external/webkit/Source/JavaScriptCore/dfg/ |
H A D | DFGNonSpeculativeJIT.cpp | 237 MacroAssembler::RegisterID reg1 = op1.registerID(); local 239 bitOp(op, reg1, reg2, result.registerID()); 264 MacroAssembler::RegisterID reg1 = op1.registerID(); local 266 shiftOp(op, reg1, reg2, result.registerID()); 369 MacroAssembler::FPRegisterID reg1 = op1.registerID(); local 371 m_jit.addDouble(reg1, reg2, result.registerID()); 382 MacroAssembler::FPRegisterID reg1 = op1.registerID(); local 384 m_jit.subDouble(reg1, reg2, result.registerID()); 395 MacroAssembler::FPRegisterID reg1 = op1.registerID(); local 397 m_jit.mulDouble(reg1, reg 408 MacroAssembler::FPRegisterID reg1 = op1.registerID(); local [all...] |
H A D | DFGSpeculativeJIT.cpp | 290 MacroAssembler::RegisterID reg1 = op1.registerID(); local 292 bitOp(op, reg1, reg2, result.registerID()); 314 MacroAssembler::RegisterID reg1 = op1.registerID(); local 316 shiftOp(op, reg1, reg2, result.registerID()); 429 MacroAssembler::RegisterID reg1 = op1.registerID(); local 431 speculationCheck(m_jit.branchSub32(MacroAssembler::Overflow, reg1, reg2, result.registerID())); 442 MacroAssembler::RegisterID reg1 = op1.registerID(); local 444 speculationCheck(m_jit.branchMul32(MacroAssembler::Overflow, reg1, reg2, result.registerID())); 447 speculationCheck(m_jit.branch32(MacroAssembler::LessThan, reg1, TrustedImm32(0)));
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/external/v8/src/mips/ |
H A D | regexp-macro-assembler-mips.cc | 447 void RegExpMacroAssemblerMIPS::CheckNotRegistersEqual(int reg1, argument
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H A D | macro-assembler-mips.cc | 463 Register reg1, 483 // reg1 - Used to hold the capacity mask of the dictionary. 489 GetNumberHash(reg0, reg1); 492 lw(reg1, FieldMemOperand(elements, SeededNumberDictionary::kCapacityOffset)); 493 sra(reg1, reg1, kSmiTagSize); 494 Subu(reg1, reg1, Operand(1)); 505 and_(reg2, reg2, reg1); 529 lw(reg1, FieldMemOperan 458 LoadFromNumberDictionary(Label* miss, Register elements, Register key, Register result, Register reg0, Register reg1, Register reg2) argument 4754 JumpIfNotBothSmi(Register reg1, Register reg2, Label* on_not_both_smi) argument 4764 JumpIfEitherSmi(Register reg1, Register reg2, Label* on_either_smi) argument [all...] |
/external/v8/src/ |
H A D | regexp-macro-assembler-tracer.cc | 299 void RegExpMacroAssemblerTracer::CheckNotRegistersEqual(int reg1, argument 302 PrintF(" CheckNotRegistersEqual(reg1=%d, reg2=%d, label[%08x]);\n", 303 reg1, 306 assembler_->CheckNotRegistersEqual(reg1, reg2, on_not_equal);
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H A D | regexp-macro-assembler-irregexp.cc | 374 void RegExpMacroAssemblerIrregexp::CheckNotRegistersEqual(int reg1, argument 377 ASSERT(reg1 >= 0); 378 ASSERT(reg1 <= kMaxRegister); 379 Emit(BC_CHECK_NOT_REGS_EQUAL, reg1);
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/external/aac/libFDK/src/ |
H A D | fixpoint_math.cpp | 388 FIXP_DBL reg1, reg2, regtmp ; local 403 reg1 = invSqrtTab[ (INT)(val>>(DFRACT_BITS-1-(SQRT_BITS+1))) & SQRT_BITS_MASK ]; 406 regtmp= fPow2Div2(reg1); /* a = Q^2 */ 408 reg1 += (fMultDiv2(regtmp, reg1)<<4); /* Q = Q + Q*b */ 413 reg1 = fMultDiv2(reg1, reg2) << 2; 418 return(reg1);
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/external/v8/src/ia32/ |
H A D | regexp-macro-assembler-ia32.cc | 485 void RegExpMacroAssemblerIA32::CheckNotRegistersEqual(int reg1, argument 488 __ mov(eax, register_location(reg1));
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/external/webkit/Source/JavaScriptCore/assembler/ |
H A D | MacroAssemblerARM.h | 371 void swap(RegisterID reg1, RegisterID reg2) argument 373 m_assembler.mov_r(ARMRegisters::S0, reg1); 374 m_assembler.mov_r(reg1, reg2);
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H A D | MacroAssemblerMIPS.h | 866 void swap(RegisterID reg1, RegisterID reg2) argument 868 move(reg1, immTempRegister); 869 move(reg2, reg1); 897 // jle32(reg1, TrustedImm32(5)) will branch if the value held in reg1, when
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H A D | MacroAssemblerX86Common.h | 733 void swap(RegisterID reg1, RegisterID reg2) argument 735 if (reg1 != reg2) 736 m_assembler.xchgq_rr(reg1, reg2); 760 void swap(RegisterID reg1, RegisterID reg2) argument 762 if (reg1 != reg2) 763 m_assembler.xchgl_rr(reg1, reg2); 790 // jle32(reg1, TrustedImm32(5)) will branch if the value held in reg1, when
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H A D | MacroAssemblerARMv7.h | 792 void swap(RegisterID reg1, RegisterID reg2) argument 794 move(reg1, dataTempRegister); 795 move(reg2, reg1); 824 // jle32(reg1, TrustedImm32(5)) will branch if the value held in reg1, when
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H A D | ARMv7Assembler.h | 2196 void oneWordOp5Imm5Reg3Reg3(OpcodeID op, uint8_t imm, RegisterID reg1, RegisterID reg2) argument 2198 m_buffer.putShort(op | (imm << 6) | (reg1 << 3) | reg2); 2201 void oneWordOp7Reg3Reg3Reg3(OpcodeID op, RegisterID reg1, RegisterID reg2, RegisterID reg3) argument 2203 m_buffer.putShort(op | (reg1 << 6) | (reg2 << 3) | reg3); 2211 void oneWordOp8RegReg143(OpcodeID op, RegisterID reg1, RegisterID reg2) argument 2213 m_buffer.putShort(op | ((reg2 & 8) << 4) | (reg1 << 3) | (reg2 & 7)); 2220 void oneWordOp10Reg3Reg3(OpcodeID op, RegisterID reg1, RegisterID reg2) argument 2222 m_buffer.putShort(op | (reg1 << 3) | reg2); 2252 void twoWordOp12Reg4Reg4Imm12(OpcodeID1 op, RegisterID reg1, RegisterID reg2, uint16_t imm) argument 2254 m_buffer.putShort(op | reg1); [all...] |
/external/webkit/Source/JavaScriptCore/jit/ |
H A D | JITInlineMethods.h | 716 ALWAYS_INLINE JIT::Jump JIT::emitJumpIfBothJSCells(RegisterID reg1, RegisterID reg2, RegisterID scratch) argument 718 move(reg1, scratch); 787 ALWAYS_INLINE JIT::Jump JIT::emitJumpIfNotImmediateIntegers(RegisterID reg1, RegisterID reg2, RegisterID scratch) argument 789 move(reg1, scratch); 799 ALWAYS_INLINE void JIT::emitJumpSlowCaseIfNotImmediateIntegers(RegisterID reg1, RegisterID reg2, RegisterID scratch) argument 801 addSlowCase(emitJumpIfNotImmediateIntegers(reg1, reg2, scratch));
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/external/qemu/tcg/ |
H A D | tcg.c | 1483 /* Allocate a register belonging to reg1 & ~reg2 */ 1484 static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2) argument 1489 tcg_regset_andnot(reg_ct, reg1, reg2);
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/external/valgrind/main/VEX/priv/ |
H A D | host_s390_isel.c | 2089 HReg reg1, reg2; local 2125 reg1 = newVRegI(env); 2126 addInstr(env, s390_insn_unop(4, op, reg1, op1)); 2133 addInstr(env, s390_insn_compare(4, reg1, op2, False));
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/external/valgrind/main/perf/ |
H A D | tinycc.c | 16262 int mod, reg1, reg2, sib_reg1; 16284 reg1 = op->reg; 16286 reg1 = 4; 16287 g(mod + (reg << 3) + reg1); 16288 if (reg1 == 4) { 16260 int mod, reg1, reg2, sib_reg1; local
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/external/sqlite/dist/orig/ |
H A D | sqlite3.c | 82059 int reg1, reg2, reg3; local [all...] |
/external/sqlite/dist/ |
H A D | sqlite3.c | 82095 int reg1, reg2, reg3; local [all...] |