Searched refs:TII (Results 51 - 75 of 193) sorted by relevance

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/external/llvm/lib/Target/R600/
H A DAMDGPURegisterInfo.cpp24 TII(tii)
H A DAMDGPURegisterInfo.h33 const TargetInstrInfo &TII; member in struct:llvm::AMDGPURegisterInfo
H A DAMDILISelDAGToDAG.cpp202 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo()); local
252 if (!TII->isALUInstr(Use->getMachineOpcode()) ||
253 (TII->get(Use->getMachineOpcode()).TSFlags &
258 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
295 const R600InstrInfo *TII = local
298 !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
299 && TII->isALUInstr(Result->getMachineOpcode())) {
309 IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
321 TII->getOperandIdx(Result->getMachineOpcode(), R600Operands::CLAMP);
340 const R600InstrInfo *TII, st
339 FoldOperands(unsigned Opcode, const R600InstrInfo *TII, std::vector<SDValue> &Ops) argument
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H A DSIInsertWaits.cpp49 const SIInstrInfo *TII; member in class:__anon9785::SIInsertWaits
100 TII(static_cast<const SIInstrInfo*>(tm.getInstrInfo())),
101 TRI(TII->getRegisterInfo()) { }
124 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
290 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
/external/llvm/lib/Target/Sparc/
H A DFPMover.cpp105 const TargetInstrInfo *TII = TM.getInstrInfo(); local
107 MI->setDesc(TII->get(SP::FMOVS));
109 MI->setDesc(TII->get(SP::FNEGS));
111 MI->setDesc(TII->get(SP::FABSS));
H A DDelaySlotFiller.cpp42 const TargetInstrInfo *TII; member in struct:__anon9789::Filler
46 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
114 BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::NOP));
122 TII->get(SP::UNIMP)).addImm(structSize);
147 slot->setDesc(TII->get(SP::RET));
/external/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.h28 const TargetInstrInfo &TII; member in struct:llvm::XCoreRegisterInfo
/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp59 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
60 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
H A DThumb2InstrInfo.cpp181 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
193 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
199 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
208 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
214 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
229 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
241 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
280 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
390 const ARMBaseInstrInfo &TII) {
406 MI.setDesc(TII
177 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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H A DARMFastISel.cpp81 const TargetInstrInfo &TII; member in class:__anon9662::ARMFastISel
94 TII(*TM.getInstrInfo()),
278 if (TII.isPredicable(MI) || isARMNEONPred(MI))
296 const MCInstrDesc &II = TII.get(MachineInstOpcode);
306 const MCInstrDesc &II = TII.get(MachineInstOpcode);
315 TII.get(TargetOpcode::COPY), ResultReg)
326 const MCInstrDesc &II = TII.get(MachineInstOpcode);
337 TII.get(TargetOpcode::COPY), ResultReg)
349 const MCInstrDesc &II = TII.get(MachineInstOpcode);
362 TII
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H A DARMExpandPseudoInsts.cpp42 const ARMBaseInstrInfo *TII; member in class:__anon9660::ARMExpandPseudo
384 TII->get(TableEntry->RealOpc));
449 TII->get(TableEntry->RealOpc));
501 TII->get(TableEntry->RealOpc));
584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
626 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
627 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
656 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
657 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
693 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII
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/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp152 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
177 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
181 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
183 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
187 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
191 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
H A DMips16ISelLowering.cpp419 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
452 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
469 TII->get(Mips::PHI), MI->getOperand(0).getReg())
482 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
515 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
517 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
533 TII->get(Mips::PHI), MI->getOperand(0).getReg())
547 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
580 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
582 BuildMI(BB, DL, TII
613 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
628 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
660 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
677 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
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H A DMips16ISelDAGToDAG.cpp68 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
78 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
80 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
82 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
83 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
98 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
102 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
/external/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp93 const TargetInstrInfo *TII; member in class:__anon9495::PeepholeOptimizer
151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
285 TII->get(TargetOpcode::COPY), NewVR)
383 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
389 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
403 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
407 if (!TII->optimizeSelect(MI))
473 if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
489 TII = TM->getInstrInfo();
555 MachineInstr *FoldMI = TII
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H A DMachineBasicBlock.cpp350 const TargetInstrInfo *TII = getParent()->getTarget().getInstrInfo(); local
357 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
365 TII->RemoveBranch(*this);
385 TII->InsertBranch(*this, TBB, 0, Cond, dl);
393 if (TII->ReverseBranchCondition(Cond))
395 TII->RemoveBranch(*this);
396 TII->InsertBranch(*this, FBB, 0, Cond, dl);
398 TII->RemoveBranch(*this);
399 TII->InsertBranch(*this, TBB, 0, Cond, dl);
418 TII
605 const TargetInstrInfo *TII = getParent()->getTarget().getInstrInfo(); local
645 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); local
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H A DMachineSSAUpdater.cpp40 TII = MF.getTarget().getInstrInfo();
116 const TargetInstrInfo *TII) {
118 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
151 VRC, MRI, TII);
187 Loc, VRC, MRI, TII);
299 Updater->TII);
310 Updater->TII);
112 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
H A DDeadMachineInstructionElim.cpp34 const TargetInstrInfo *TII; member in class:__anon9451::DeadMachineInstructionElim
62 if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
90 TII = MF.getTarget().getInstrInfo();
H A DProcessImplicitDefs.cpp28 const TargetInstrInfo *TII; member in class:__anon9497::ProcessImplicitDefs
92 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
144 TII = MF.getTarget().getInstrInfo();
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp68 const HexagonInstrInfo *TII; member in struct:__anon9699::HexagonHardwareLoops
305 TII = static_cast<const HexagonInstrInfo*>(TM->getInstrInfo());
374 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
388 bool CmpAnalyzed = TII->analyzeCompare(PredI, CmpReg1, CmpReg2,
482 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
506 bool AnalyzedCmp = TII->analyzeCompare(CondI, CmpReg1, CmpReg2,
787 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::SUB_rr) :
788 (RegToImm ? TII->get(Hexagon::SUB_ri) :
789 TII->get(Hexagon::ADD_ri));
817 const MCInstrDesc &AddD = TII
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/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp230 DL, TII.get(Opc), ResultReg), AM);
249 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
280 DL, TII.get(Opc)), AM).addReg(Val);
309 DL, TII.get(Opc)), AM)
564 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
809 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
824 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
911 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
923 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII
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H A DX86VZeroUpper.cpp44 const TargetInstrInfo *TII; // Machine instruction info. member in struct:__anon9846::VZeroUpperInserter
149 TII = MF.getTarget().getInstrInfo();
264 BuildMI(BB, I, dl, TII->get(X86::VZEROUPPER));
/external/llvm/lib/Target/AArch64/
H A DAArch64BranchFixupPass.cpp133 const AArch64InstrInfo *TII; member in class:__anon9638::AArch64BranchFixup
194 TII = (const AArch64InstrInfo*)MF->getTarget().getInstrInfo();
329 BBI.Size += TII->getInstSizeInBytes(*I);
351 Offset += TII->getInstSizeInBytes(*I);
376 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::Bimm)).addMBB(NewBB);
512 InvertedMI = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(InvertedOpcode));
556 int delta = TII->getInstSizeInBytes(MBB->back());
588 BuildMI(MBB, DebugLoc(), TII->get(AArch64::Bimm))
592 BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
H A DAArch64RegisterInfo.cpp34 : AArch64GenRegisterInfo(AArch64::X30), TII(tii) {
132 TII.getAddressConstraints(MI, OffsetScale, MinOffset, MaxOffset);
141 emitRegUpdate(MBB, MBBI, MBBI->getDebugLoc(), TII,
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp112 const TargetInstrInfo *TII,
123 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
228 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
257 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
299 const MCInstrDesc &MCID = TII->get(Opc);
358 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
376 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
434 const MCInstrDesc &MCID = TII->get(Opc);
448 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
453 if (NumUsed > TII
110 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
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