Searched refs:TM (Results 101 - 125 of 299) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DTargetLoweringObjectFileImpl.cpp64 const TargetMachine &TM,
79 unsigned Size = TM.getDataLayout()->getPointerSize();
81 Streamer.EmitValueToAlignment(TM.getDataLayout()->getPointerABIAlignment());
205 Mangler *Mang, const TargetMachine &TM) const {
238 Mangler *Mang, const TargetMachine &TM) const {
243 EmitUniquedSection = TM.getFunctionSections();
245 EmitUniquedSection = TM.getDataSections();
279 TM.getDataLayout()->getPreferredAlignment(cast<GlobalVariable>(GV));
412 Mangler *Mang, const TargetMachine &TM) const {
486 Mangler *Mang, const TargetMachine &TM) cons
63 emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, const MCSymbol *Sym) const argument
[all...]
H A DDFAPacketizer.cpp130 bool IsPostRA) : TM(MF.getTarget()), MF(MF) {
131 TII = TM.getInstrInfo();
132 ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
H A DDwarfEHPrepare.cpp35 const TargetMachine *TM; member in class:__anon9452::DwarfEHPrepare
47 FunctionPass(ID), TM(tm), TLI(TM->getTargetLowering()),
H A DPasses.cpp226 Started(true), Stopped(false), TM(tm), Impl(0), Initialized(false),
241 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
337 if (TM->shouldPrintMachineCode())
375 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
383 addPass(createSjLjEHPreparePass(TM->getTargetLowering()));
388 addPass(createDwarfEHPass(TM));
391 addPass(createLowerInvokePass(TM->getTargetLowering()));
446 TM->Options.PrintMachineCode = true;
/external/llvm/lib/Target/Mips/
H A DMipsCodeEmitter.cpp53 TargetMachine &TM; member in class:__anon9742::MipsCodeEmitter
70 TM(tm), MCE(mce), MCPEs(0), MJTEs(0),
71 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
133 Subtarget = &TM.getSubtarget<MipsSubtarget> ();
219 return TM.getRegisterInfo()->getEncodingValue(MO.getReg());
322 FunctionPass *llvm::createMipsJITCodeEmitterPass(MipsTargetMachine &TM, argument
324 return new MipsCodeEmitter(TM, JCE);
H A DMipsInstrInfo.cpp32 TM(tm), UncondBrOpc(UncondBr) {}
34 const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) { argument
35 if (TM.getSubtargetImpl()->inMips16Mode())
36 return llvm::createMips16InstrInfo(TM);
38 return llvm::createMipsSEInstrInfo(TM);
H A DMipsSEISelLowering.cpp27 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) argument
28 : MipsTargetLowering(TM) {
51 if (!TM.Options.UseSoftFloat) {
72 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { argument
73 return new MipsSETargetLowering(TM);
/external/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinter.cpp96 TM(tm), MAI(tm.getMCAsmInfo()),
128 return TM.getTargetLowering()->getObjFileLowering();
133 return *TM.getDataLayout();
160 .Initialize(OutContext, TM);
162 Mang = new Mangler(OutContext, *TM.getDataLayout());
280 SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM);
282 const DataLayout *TD = TM.getDataLayout();
308 getObjFileLowering().SectionForGlobal(GV, GVKind, Mang, TM);
337 getObjFileLowering().SectionForGlobal(GV, GVKind, Mang, TM);
427 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
492 const TargetMachine &TM = MF->getTarget(); local
1582 isRepeatedByteSequence(const Value *V, TargetMachine &TM) argument
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/external/llvm/lib/ExecutionEngine/JIT/
H A DJIT.cpp211 TargetMachine *TM) {
218 if (TargetJITInfo *TJ = TM->getJITInfo()) {
219 return new JIT(M, *TM, *TJ, JMM, GVsWithCode);
272 : ExecutionEngine(M), TM(tm), TJI(tji),
275 setDataLayout(TM.getDataLayout());
280 JCE = createEmitter(*this, JMM, TM);
288 PM.add(new DataLayout(*TM.getDataLayout()));
292 if (TM.addPassesToEmitMachineCode(PM, *JCE)) {
328 delete &TM;
342 PM.add(new DataLayout(*TM
207 createJIT(Module *M, std::string *ErrorStr, JITMemoryManager *JMM, bool GVsWithCode, TargetMachine *TM) argument
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/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp36 const X86TargetMachine *TM; member in class:__anon9845::X86TTI
45 X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
49 X86TTI(const X86TargetMachine *TM) argument
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
112 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) { argument
113 return new X86TTI(TM);
/external/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp126 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM) argument
127 : TargetPassConfig(TM, PM) {}
150 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
151 addPass(createGlobalMergePass(TM->getTargetLowering()));
161 TM->Options.EnableFastISel)
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp52 HexagonExpandPredSpillCode(HexagonTargetMachine& TM) : argument
53 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
178 FunctionPass *llvm::createHexagonExpandPredSpillCode(HexagonTargetMachine &TM) { argument
179 return new HexagonExpandPredSpillCode(TM);
H A DHexagonSplitTFRCondSets.cpp60 HexagonSplitTFRCondSets(HexagonTargetMachine& TM) : argument
61 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
214 FunctionPass *llvm::createHexagonSplitTFRCondSets(HexagonTargetMachine &TM) { argument
215 return new HexagonSplitTFRCondSets(TM);
H A DHexagonAsmPrinter.h28 explicit HexagonAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument
29 : AsmPrinter(TM, Streamer) {
30 Subtarget = &TM.getSubtarget<HexagonSubtarget>();
H A DHexagonCallingConvLower.h50 const TargetMachine &TM; member in class:llvm::Hexagon_CCState
58 Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM,
66 const TargetMachine &getTarget() const { return TM; }
H A DHexagonMachineScheduler.h58 VLIWResourceModel(const TargetMachine &TM, const TargetSchedModel *SM) : argument
60 ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL);
H A DHexagonTargetMachine.cpp98 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) argument
99 : TargetPassConfig(TM, PM) {
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp36 SparcTargetMachine& TM; member in class:__anon9792::SparcDAGToDAGISel
41 TM(tm) {
69 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
209 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) { argument
210 return new SparcDAGToDAGISel(TM);
/external/llvm/lib/Target/
H A DTargetMachineC.cpp154 TargetMachine* TM = unwrap(T); local
161 const DataLayout* td = TM->getDataLayout();
186 if (TM->addPassesToEmitFile(pass, destf, ft)) {
/external/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp44 XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) argument
45 : SelectionDAGISel(TM, OptLevel),
46 Lowering(*TM.getTargetLowering()),
47 Subtarget(*TM.getSubtargetImpl()) { }
86 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, argument
88 return new XCoreDAGToDAGISel(TM, OptLevel);
/external/llvm/lib/Target/MSP430/
H A DMSP430AsmPrinter.cpp42 MSP430AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument
43 : AsmPrinter(TM, Streamer) {}
/external/llvm/lib/Target/NVPTX/
H A DNVPTXTargetObjectFile.h48 virtual void Initialize(MCContext &ctx, const TargetMachine &TM) { argument
97 const TargetMachine &TM) const {
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp82 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM) argument
83 : TargetPassConfig(TM, PM) {}
/external/llvm/lib/Target/R600/
H A DAMDGPUAsmPrinter.cpp43 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
66 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
/external/llvm/include/llvm/Target/
H A DTargetSelectionDAGInfo.h40 explicit TargetSelectionDAGInfo(const TargetMachine &TM);

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