/external/llvm/lib/CodeGen/ |
H A D | TargetLoweringObjectFileImpl.cpp | 64 const TargetMachine &TM, 79 unsigned Size = TM.getDataLayout()->getPointerSize(); 81 Streamer.EmitValueToAlignment(TM.getDataLayout()->getPointerABIAlignment()); 205 Mangler *Mang, const TargetMachine &TM) const { 238 Mangler *Mang, const TargetMachine &TM) const { 243 EmitUniquedSection = TM.getFunctionSections(); 245 EmitUniquedSection = TM.getDataSections(); 279 TM.getDataLayout()->getPreferredAlignment(cast<GlobalVariable>(GV)); 412 Mangler *Mang, const TargetMachine &TM) const { 486 Mangler *Mang, const TargetMachine &TM) cons 63 emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, const MCSymbol *Sym) const argument [all...] |
H A D | DFAPacketizer.cpp | 130 bool IsPostRA) : TM(MF.getTarget()), MF(MF) { 131 TII = TM.getInstrInfo(); 132 ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
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H A D | DwarfEHPrepare.cpp | 35 const TargetMachine *TM; member in class:__anon9452::DwarfEHPrepare 47 FunctionPass(ID), TM(tm), TLI(TM->getTargetLowering()),
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H A D | Passes.cpp | 226 Started(true), Stopped(false), TM(tm), Impl(0), Initialized(false), 241 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>(); 337 if (TM->shouldPrintMachineCode()) 375 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) { 383 addPass(createSjLjEHPreparePass(TM->getTargetLowering())); 388 addPass(createDwarfEHPass(TM)); 391 addPass(createLowerInvokePass(TM->getTargetLowering())); 446 TM->Options.PrintMachineCode = true;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsCodeEmitter.cpp | 53 TargetMachine &TM; member in class:__anon9742::MipsCodeEmitter 70 TM(tm), MCE(mce), MCPEs(0), MJTEs(0), 71 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 133 Subtarget = &TM.getSubtarget<MipsSubtarget> (); 219 return TM.getRegisterInfo()->getEncodingValue(MO.getReg()); 322 FunctionPass *llvm::createMipsJITCodeEmitterPass(MipsTargetMachine &TM, argument 324 return new MipsCodeEmitter(TM, JCE);
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H A D | MipsInstrInfo.cpp | 32 TM(tm), UncondBrOpc(UncondBr) {} 34 const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) { argument 35 if (TM.getSubtargetImpl()->inMips16Mode()) 36 return llvm::createMips16InstrInfo(TM); 38 return llvm::createMipsSEInstrInfo(TM);
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H A D | MipsSEISelLowering.cpp | 27 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) argument 28 : MipsTargetLowering(TM) { 51 if (!TM.Options.UseSoftFloat) { 72 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { argument 73 return new MipsSETargetLowering(TM);
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinter.cpp | 96 TM(tm), MAI(tm.getMCAsmInfo()), 128 return TM.getTargetLowering()->getObjFileLowering(); 133 return *TM.getDataLayout(); 160 .Initialize(OutContext, TM); 162 Mang = new Mangler(OutContext, *TM.getDataLayout()); 280 SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM); 282 const DataLayout *TD = TM.getDataLayout(); 308 getObjFileLowering().SectionForGlobal(GV, GVKind, Mang, TM); 337 getObjFileLowering().SectionForGlobal(GV, GVKind, Mang, TM); 427 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM)); 492 const TargetMachine &TM = MF->getTarget(); local 1582 isRepeatedByteSequence(const Value *V, TargetMachine &TM) argument [all...] |
/external/llvm/lib/ExecutionEngine/JIT/ |
H A D | JIT.cpp | 211 TargetMachine *TM) { 218 if (TargetJITInfo *TJ = TM->getJITInfo()) { 219 return new JIT(M, *TM, *TJ, JMM, GVsWithCode); 272 : ExecutionEngine(M), TM(tm), TJI(tji), 275 setDataLayout(TM.getDataLayout()); 280 JCE = createEmitter(*this, JMM, TM); 288 PM.add(new DataLayout(*TM.getDataLayout())); 292 if (TM.addPassesToEmitMachineCode(PM, *JCE)) { 328 delete &TM; 342 PM.add(new DataLayout(*TM 207 createJIT(Module *M, std::string *ErrorStr, JITMemoryManager *JMM, bool GVsWithCode, TargetMachine *TM) argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 36 const X86TargetMachine *TM; member in class:__anon9845::X86TTI 45 X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) { 49 X86TTI(const X86TargetMachine *TM) argument 50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()), 51 TLI(TM->getTargetLowering()) { 112 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) { argument 113 return new X86TTI(TM);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetMachine.cpp | 126 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM) argument 127 : TargetPassConfig(TM, PM) {} 150 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge) 151 addPass(createGlobalMergePass(TM->getTargetLowering())); 161 TM->Options.EnableFastISel)
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 52 HexagonExpandPredSpillCode(HexagonTargetMachine& TM) : argument 53 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {} 178 FunctionPass *llvm::createHexagonExpandPredSpillCode(HexagonTargetMachine &TM) { argument 179 return new HexagonExpandPredSpillCode(TM);
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H A D | HexagonSplitTFRCondSets.cpp | 60 HexagonSplitTFRCondSets(HexagonTargetMachine& TM) : argument 61 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {} 214 FunctionPass *llvm::createHexagonSplitTFRCondSets(HexagonTargetMachine &TM) { argument 215 return new HexagonSplitTFRCondSets(TM);
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H A D | HexagonAsmPrinter.h | 28 explicit HexagonAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 29 : AsmPrinter(TM, Streamer) { 30 Subtarget = &TM.getSubtarget<HexagonSubtarget>();
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H A D | HexagonCallingConvLower.h | 50 const TargetMachine &TM; member in class:llvm::Hexagon_CCState 58 Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM, 66 const TargetMachine &getTarget() const { return TM; }
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H A D | HexagonMachineScheduler.h | 58 VLIWResourceModel(const TargetMachine &TM, const TargetSchedModel *SM) : argument 60 ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL);
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H A D | HexagonTargetMachine.cpp | 98 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) argument 99 : TargetPassConfig(TM, PM) {
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 36 SparcTargetMachine& TM; member in class:__anon9792::SparcDAGToDAGISel 41 TM(tm) { 69 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF); 209 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) { argument 210 return new SparcDAGToDAGISel(TM);
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/external/llvm/lib/Target/ |
H A D | TargetMachineC.cpp | 154 TargetMachine* TM = unwrap(T); local 161 const DataLayout* td = TM->getDataLayout(); 186 if (TM->addPassesToEmitFile(pass, destf, ft)) {
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 44 XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) argument 45 : SelectionDAGISel(TM, OptLevel), 46 Lowering(*TM.getTargetLowering()), 47 Subtarget(*TM.getSubtargetImpl()) { } 86 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, argument 88 return new XCoreDAGToDAGISel(TM, OptLevel);
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430AsmPrinter.cpp | 42 MSP430AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 43 : AsmPrinter(TM, Streamer) {}
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetObjectFile.h | 48 virtual void Initialize(MCContext &ctx, const TargetMachine &TM) { argument 97 const TargetMachine &TM) const {
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetMachine.cpp | 82 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM) argument 83 : TargetPassConfig(TM, PM) {}
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUAsmPrinter.cpp | 43 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); 66 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
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/external/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 40 explicit TargetSelectionDAGInfo(const TargetMachine &TM);
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