/external/llvm/lib/Target/R600/ |
H A D | SILowerControlFlow.cpp | 69 const TargetRegisterInfo *TRI; member in class:__anon9788::SILowerControlFlowPass 94 MachineFunctionPass(ID), TRI(tm.getRegisterInfo()), 383 .addReg(TRI->getSubReg(Vec, AMDGPU::sub0) + Off) 401 .addReg(TRI->getSubReg(Dst, AMDGPU::sub0) + Off, RegState::Define)
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H A D | SIISelLowering.cpp | 33 TRI(TM.getRegisterInfo()) { 88 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local 167 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0, 174 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); 515 return TRI->getRegClass(RegClass)->hasSubClassEq(TRI->getRegClass(OpClass));
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H A D | AMDILCFGStructurizer.cpp | 306 const AMDGPURegisterInfo *TRI; member in class:llvmCFGStruct::CFGStructurizer 326 TRI = tri; 393 TRI = tri; 1185 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1290 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1324 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1732 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 2008 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 2478 const AMDGPURegisterInfo *TRI; member in class:llvm::AMDGPUCFGStructurizer 2491 TRI(static_cas [all...] |
H A D | R600MachineScheduler.cpp | 32 TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.cpp | 96 const TargetRegisterInfo *TRI) const { 106 const TargetRegisterInfo *TRI) const {
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 183 const TargetRegisterInfo *TRI) const { 209 const TargetRegisterInfo *TRI) const {
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H A D | MSP430InstrInfo.cpp | 38 const TargetRegisterInfo *TRI) const { 66 const TargetRegisterInfo *TRI) const{
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 366 const TargetRegisterInfo *TRI) const 380 const TargetRegisterInfo *TRI) const
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/external/llvm/lib/CodeGen/ |
H A D | MachineFunction.cpp | 335 const TargetRegisterInfo *TRI = getTarget().getRegisterInfo(); local 341 OS << PrintReg(I->first, TRI); 343 OS << " in " << PrintReg(I->second, TRI); 553 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local 554 BitVector BV(TRI->getNumRegs()); 561 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(MF); CSR && *CSR; ++CSR)
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H A D | InlineSpiller.cpp | 65 const TargetRegisterInfo &TRI; member in class:__anon9463::InlineSpiller 149 TRI(*mf.getTarget().getRegisterInfo()) {} 726 MRI.getRegClass(SVI.SpillReg), &TRI); 889 TRI); 942 MI->addRegisterDead(Reg, &TRI); 1081 MRI.getRegClass(NewLI.reg), &TRI); 1099 MRI.getRegClass(NewLI.reg), &TRI);
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H A D | MachineScheduler.cpp | 460 DEBUG(RPTracker.getPressure().dump(TRI)); 484 unsigned Limit = TRI->getRegPressureSetLimit(i); 485 DEBUG(dbgs() << TRI->getRegPressureSetName(i) 493 dbgs() << TRI->getRegPressureSetName( 766 const TargetRegisterInfo *TRI; member in class:__anon9482::LoadClusterMutation 770 : TII(tii), TRI(tri) {} 793 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI)) 1142 const TargetRegisterInfo *TRI; member in class:__anon9484::ConvergingScheduler 1158 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {} 1240 TRI [all...] |
H A D | ShrinkWrapping.cpp | 404 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); local 426 TRI->isSubRegister(Reg, MOReg))) { 1056 const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo(); local 1069 srep << TRI->getName(reg); 1073 srep << TRI->getName(reg);
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H A D | ScheduleDAG.cpp | 39 TRI(TM.getRegisterInfo()), 351 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI); 371 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
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H A D | ScheduleDAGInstrs.cpp | 216 if (TRI->isPhysicalRegister(Reg)) 248 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 295 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 717 Defs.setUniverse(TRI->getNumRegs()); 718 Uses.setUniverse(TRI->getNumRegs()); 763 if (TRI->isPhysicalRegister(Reg))
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H A D | MachineSink.cpp | 47 const TargetRegisterInfo *TRI; member in class:__anon9488::MachineSinking 226 TRI = TM.getRegisterInfo();
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H A D | SplitKit.h | 217 const TargetRegisterInfo &TRI; member in class:llvm::SplitEditor
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/external/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 66 const TargetRegisterInfo *TRI; member in struct:__anon9669::ARMLoadStoreOpt 459 unsigned PRegNum = PMO.isUndef() ? UINT_MAX : TRI->getEncodingValue(PReg); 485 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); 1106 unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false); 1107 unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); 1171 (TRI->regsOverlap(EvenReg, BaseReg))) { 1172 assert(!TRI->regsOverlap(OddReg, BaseReg)); 1422 TRI = TM.getRegisterInfo(); 1452 const TargetRegisterInfo *TRI; member in struct:__anon9670::ARMPreAllocLoadStoreOpt 1482 TRI 1495 IsSafeAndProfitableToMove(bool isLd, unsigned Base, MachineBasicBlock::iterator I, MachineBasicBlock::iterator E, SmallPtrSet<MachineInstr*, 4> &MemOps, SmallSet<unsigned, 4> &MemRegs, const TargetRegisterInfo *TRI) argument [all...] |
H A D | ARMAsmPrinter.cpp | 347 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 348 Reg = TRI->getSubReg(Reg, ARM::gsub_0); 447 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 450 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { 453 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; 524 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 525 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? 539 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 543 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
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H A D | Thumb1FrameLowering.cpp | 332 const TargetRegisterInfo *TRI) const { 371 const TargetRegisterInfo *TRI) const {
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.cpp | 198 TRI = DAG->TRI; 412 dbgs() << TRI->getRegPressureSetName(P.PSetID) << ":" << P.UnitIncrease
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/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 91 const TargetRegisterInfo &TRI, 128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) 149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) { 169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit); 1242 const TargetRegisterInfo *TRI) const { 1251 unsigned FPReg = TRI->getFrameRegister(MF); 1286 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1288 RC, TRI); 1297 const TargetRegisterInfo *TRI) const { 1312 const TargetRegisterClass *RC = TRI 89 findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetRegisterInfo &TRI, bool Is64Bit) argument 146 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned StackPtr, int64_t NumBytes, bool Is64Bit, bool IsLP64, bool UseLEA, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 301 const TargetRegisterInfo *TRI) const { 323 const TargetRegisterInfo *TRI) const {
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/external/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 160 const TargetRegisterInfo &TRI; member in class:llvm::CCState
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H A D | FastISel.h | 60 const TargetRegisterInfo &TRI; member in class:llvm::FastISel
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H A D | LiveIntervalAnalysis.h | 53 const TargetRegisterInfo* TRI; member in class:llvm::LiveIntervals
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