| /external/llvm/lib/CodeGen/ |
| H A D | TailDuplication.cpp | 63 const TargetRegisterInfo *TRI; member in class:__anon9543::TailDuplicatePass
132 TRI = MF.getTarget().getRegisterInfo();
137 if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
794 BitVector RegsLiveAtExit(TRI->getNumRegs());
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| H A D | TargetLoweringBase.cpp | 838 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
844 BitVector SuperRegRC(TRI->getNumRegClasses());
845 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
851 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
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| H A D | SplitKit.cpp | 333 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
444 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, TRI, Late);
1027 MI->addRegisterDead(LI->reg, &TRI);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 1071 const TargetRegisterInfo *TRI) const {
1122 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1124 CSI[i].getFrameIdx(), RC, TRI);
1215 const TargetRegisterInfo *TRI) const {
1264 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1266 RC, TRI);
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| H A D | PPCInstrInfo.cpp | 545 const TargetRegisterInfo *TRI) const {
653 const TargetRegisterInfo *TRI) const {
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16InstrInfo.cpp | 104 const TargetRegisterInfo *TRI) const {
120 const TargetRegisterInfo *TRI) const {
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 69 const HexagonRegisterInfo *TRI; member in struct:__anon9699::HexagonHardwareLoops
269 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; local
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
306 TRI = static_cast<const HexagonRegisterInfo*>(TM->getRegisterInfo());
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| H A D | HexagonISelLowering.cpp | 966 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
983 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
989 const HexagonRegisterInfo *TRI = TM.getRegisterInfo(); local
997 TRI->getFrameRegister(), VT);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 111 const TargetRegisterInfo *TRI,
128 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
471 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
110 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
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| H A D | FastISel.cpp | 622 Reg = TRI.getFrameRegister(*FuncInfo.MF);
1093 TRI(*TM.getRegisterInfo()),
1422 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfCompileUnit.cpp | 370 const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo(); local
371 if (Reg == TRI->getFrameRegister(*Asm->MF))
1531 const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo(); local
1533 TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) {
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| H A D | AsmPrinter.cpp | 799 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
800 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
802 for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid() && Reg < 0;
804 Reg = TRI->getDwarfRegNum(*SR, false);
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXAsmPrinter.cpp | 435 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); local
436 unsigned numRegClasses = TRI.getNumRegClasses();
1631 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local
1632 //unsigned numRegClasses = TRI->getNumRegClasses();
1657 unsigned int vr = TRI->index2VirtReg(i);
1678 // const TargetRegisterClass *RC = TRI->getRegClass(i);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1724 const TargetRegisterInfo &TRI) const {
1759 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2988 const TargetRegisterInfo *TRI) const {
3026 const TargetRegisterInfo *TRI) const {
3282 const TargetRegisterInfo *TRI = &getRegisterInfo(); local
3304 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3305 Instr->readsRegister(X86::EFLAGS, TRI)) {
3315 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3341 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3342 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 384 const TargetRegisterInfo *TRI) const {
430 const TargetRegisterInfo *TRI) const {
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| /external/eigen/blas/testing/ |
| H A D | cblat2.f | 2713 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:CMAKE
2722 TRI = TYPE( 1: 1 ).EQ.'T'
2723 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2724 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2725 UNIT = TRI.AND.DIAG.EQ.'U'
2742 ELSE IF( TRI )THEN
2750 IF( TRI )
|
| H A D | cblat3.f | 2907 LOGICAL GEN, HER, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:CMAKE
2917 TRI = TYPE.EQ.'TR'
2918 UPPER = ( HER.OR.SYM.OR.TRI ).AND.UPLO.EQ.'U'
2919 LOWER = ( HER.OR.SYM.OR.TRI ).AND.UPLO.EQ.'L'
2920 UNIT = TRI.AND.DIAG.EQ.'U'
2937 ELSE IF( TRI )THEN
2945 IF( TRI )
|
| H A D | dblat2.f | 2643 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:DMAKE
2652 TRI = TYPE( 1: 1 ).EQ.'T'
2653 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2654 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2655 UNIT = TRI.AND.DIAG.EQ.'U'
2672 ELSE IF( TRI )THEN
2678 IF( TRI )
|
| H A D | dblat3.f | 2376 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:DMAKE
2383 TRI = TYPE.EQ.'TR'
2384 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2385 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2386 UNIT = TRI.AND.DIAG.EQ.'U'
2401 ELSE IF( TRI )THEN
2407 IF( TRI )
|
| H A D | sblat2.f | 2643 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:SMAKE
2652 TRI = TYPE( 1: 1 ).EQ.'T'
2653 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2654 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2655 UNIT = TRI.AND.DIAG.EQ.'U'
2672 ELSE IF( TRI )THEN
2678 IF( TRI )
|
| H A D | sblat3.f | 2376 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:SMAKE
2383 TRI = TYPE.EQ.'TR'
2384 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2385 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2386 UNIT = TRI.AND.DIAG.EQ.'U'
2401 ELSE IF( TRI )THEN
2407 IF( TRI )
|
| H A D | zblat2.f | 2721 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:ZMAKE
2730 TRI = TYPE( 1: 1 ).EQ.'T'
2731 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2732 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2733 UNIT = TRI.AND.DIAG.EQ.'U'
2750 ELSE IF( TRI )THEN
2758 IF( TRI )
|
| H A D | zblat3.f | 2911 LOGICAL GEN, HER, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:ZMAKE
2921 TRI = TYPE.EQ.'TR'
2922 UPPER = ( HER.OR.SYM.OR.TRI ).AND.UPLO.EQ.'U'
2923 LOWER = ( HER.OR.SYM.OR.TRI ).AND.UPLO.EQ.'L'
2924 UNIT = TRI.AND.DIAG.EQ.'U'
2941 ELSE IF( TRI )THEN
2949 IF( TRI )
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineBasicBlock.h | 595 LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI,
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| H A D | ScheduleDAG.h | 560 const TargetRegisterInfo *TRI; // Target processor register info member in class:llvm::ScheduleDAG
|