Searched refs:CSR2 (Results 1 - 5 of 5) sorted by relevance
/external/grub/netboot/ |
H A D | davicom.c | 64 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, 553 outl(0, ioaddr + CSR2); 63 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:davicom_offsets
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H A D | depca.c | 253 #define CSR2 2 macro 505 outw(CSR2, DEPCA_ADDR); /* initialisation block address MSW */
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H A D | sk_g16.c | 255 * CSR2 - High order bits of initialize block (bits 07:00, 15:08 are reserved) 264 #define CSR2 0x02 macro 981 * CSR2 is built of: 988 SK_write_reg(CSR2, 0); /* Set high order bits 23:16 */
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H A D | otulip.c | 57 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:tulip_offsets
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H A D | tulip.c | 291 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, 357 0x02000000 means use the ring start address in CSR2/3. 290 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:tulip_offsets
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