Searched refs:Reg2 (Results 1 - 18 of 18) sorted by relevance

/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h116 unsigned Reg2, bool isKill2) {
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
114 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
H A DX86FastISel.cpp1494 unsigned Reg2 = getRegForValue(Op2); local
1496 if (Reg1 == 0 || Reg2 == 0)
1512 .addReg(Reg1).addReg(Reg2);
/external/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h101 // UnionGroups - Union Reg1's and Reg2's groups to form a new
104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
H A DTargetInstrInfo.cpp137 unsigned Reg2 = MI->getOperand(Idx2).getReg(); local
148 Reg0 = Reg2;
150 } else if (HasDef && Reg0 == Reg2 &&
168 MI->getOperand(Idx1).setReg(Reg2);
H A DAggressiveAntiDepBreaker.cpp79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) argument
86 unsigned Group2 = GetGroup(Reg2);
H A DStrongPHIElimination.cpp438 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) { argument
440 Node *Node2 = RegNodeMap[Reg2]->getLeader();
/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h111 unsigned Reg1, unsigned Reg2) const;
H A DMips16InstrInfo.cpp266 unsigned Reg1, unsigned Reg2) const {
270 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
280 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
284 MIB3.addReg(Reg2, RegState::Kill);
H A DMipsISelLowering.cpp2486 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); local
2487 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2914 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), local
2916 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h80 bool contains(unsigned Reg1, unsigned Reg2) const {
81 return contains(Reg1) && contains(Reg2);
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp620 unsigned Reg2 = MI->getOperand(2).getReg(); local
623 || !isARMLowRegister(Reg2))
625 if (Reg0 != Reg2) {
653 unsigned Reg2 = MI->getOperand(2).getReg(); local
654 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
H A DA15SDOptimizer.cpp90 unsigned Reg1, unsigned Reg2);
470 unsigned Reg1, unsigned Reg2) {
478 .addReg(Reg2)
467 createRegSequence(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg1, unsigned Reg2) argument
H A DARMFastISel.cpp2704 unsigned Reg2 = 0; local
2706 Reg2 = getRegForValue(Src2Value);
2707 if (Reg2 == 0) return false;
2720 MIB.addReg(Reg2);
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp155 unsigned Reg2 = MI->getOperand(2).getReg(); local
175 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
179 .addReg(Reg2, getKillRegState(Reg2IsKill))
186 MI->getOperand(0).setReg(Reg2);
188 MI->getOperand(1).setReg(Reg2);
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h81 bool contains(unsigned Reg1, unsigned Reg2) const {
82 return MC->contains(Reg1, Reg2);
/external/llvm/lib/MC/
H A DMCDwarf.cpp976 unsigned Reg2 = Instr.getRegister2(); local
980 Streamer.AddComment(Twine("Reg2 ") + Twine(Reg2));
984 Streamer.EmitULEB128IntValue(Reg2);
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1160 CodeGenRegister *Reg2 = i1->second; local
1162 if (Reg1 == Reg2)
1164 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1171 if (Reg2 == Reg3)
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5217 unsigned Reg2 = Op2->getReg(); local
5219 unsigned Rt2 = MRI->getEncodingValue(Reg2);

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