| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitTFRCondSets.cpp | 92 int SrcReg2 = MI->getOperand(3).getReg(); local
110 if (DestReg != SrcReg2) {
112 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
149 int SrcReg2 = MI->getOperand(3).getReg(); local
165 if (DestReg != SrcReg2) {
168 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
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| H A D | HexagonInstrInfo.h | 70 unsigned &SrcReg, unsigned &SrcReg2,
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| H A D | HexagonInstrInfo.cpp | 309 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
313 unsigned &SrcReg, unsigned &SrcReg2,
371 SrcReg2 = MI->getOperand(2).getReg();
381 SrcReg2 = 0;
312 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
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| /external/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 381 unsigned SrcReg, SrcReg2; local
383 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
385 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
389 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 193 /// in SrcReg and SrcReg2 if having two register operands, and the value it
197 unsigned &SrcReg2, int &CmpMask,
205 unsigned SrcReg2, int CmpMask, int CmpValue,
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| H A D | ARMBaseInstrInfo.cpp | 1943 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1947 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
1954 SrcReg2 = 0;
1961 SrcReg2 = MI->getOperand(1).getReg();
1968 SrcReg2 = 0;
2031 unsigned SrcReg2, int ImmValue,
2038 OI->getOperand(2).getReg() == SrcReg2) ||
2039 (OI->getOperand(1).getReg() == SrcReg2 &&
2061 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, argument
2098 if (SrcReg2 !
2030 isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) argument
[all...] |
| H A D | ARMFastISel.cpp | 1478 unsigned SrcReg2 = 0; local
1480 SrcReg2 = getRegForValue(Src2Value);
1481 if (SrcReg2 == 0) return false;
1489 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1490 if (SrcReg2 == 0) return false;
1497 .addReg(SrcReg1).addReg(SrcReg2));
1802 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); local
1803 if (SrcReg2 == 0) return false;
1808 .addReg(SrcReg1).addReg(SrcReg2));
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 379 /// in SrcReg and SrcReg2 if having two register operands, and the value it
383 unsigned &SrcReg2,
390 unsigned SrcReg2, int CmpMask, int CmpValue,
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| H A D | X86InstrInfo.cpp | 3055 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, argument
3067 SrcReg2 = 0;
3077 SrcReg2 = 0;
3086 SrcReg2 = MI->getOperand(2).getReg();
3098 SrcReg2 = 0;
3107 SrcReg2 = MI->getOperand(1).getReg();
3118 SrcReg2 = 0;
3133 unsigned SrcReg2, int ImmValue,
3144 OI->getOperand(2).getReg() == SrcReg2) ||
3145 (OI->getOperand(1).getReg() == SrcReg2
3132 isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) argument
3213 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
[all...] |
| /external/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 743 /// in SrcReg and SrcReg2 if having two register operands, and the value it
747 unsigned &SrcReg, unsigned &SrcReg2,
756 unsigned SrcReg, unsigned SrcReg2,
746 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
755 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument
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