Searched refs:uncached_cpsr (Results 1 - 5 of 5) sorted by relevance

/external/qemu/target-arm/
H A Dcpu.h88 uint32_t uncached_cpsr; member in struct:CPUARMState
466 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
474 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR;
531 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
H A Dhelper.c279 env->uncached_cpsr = ARM_CPU_MODE_USR;
289 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
295 env->uncached_cpsr &= ~CPSR_I;
478 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
509 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
513 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
668 old_mode = env->uncached_cpsr & CPSR_M;
816 env->uncached_cpsr &= ~CPSR_IT;
864 && (env->uncached_cpsr
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H A Dop_helper.c308 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
323 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
H A Dmachine.c127 env->uncached_cpsr = val & CPSR_M;
/external/qemu/
H A Dcpu-exec.c524 && !(env->uncached_cpsr & CPSR_F)) {
540 || !(env->uncached_cpsr & CPSR_I))) {

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