InterpAsm-armv5te-vfp.S revision 3475f9cdb47a6d6f8ad2ce49bbc3af46bca92f09
1/* 2 * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: armv5te/header.S */ 8/* 9 * Copyright (C) 2008 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 * ARMv5 definitions and declarations. 26 */ 27 28/* 29ARM EABI general notes: 30 31r0-r3 hold first 4 args to a method; they are not preserved across method calls 32r4-r8 are available for general use 33r9 is given special treatment in some situations, but not for us 34r10 (sl) seems to be generally available 35r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36r12 (ip) is scratch -- not preserved across method calls 37r13 (sp) should be managed carefully in case a signal arrives 38r14 (lr) must be preserved 39r15 (pc) can be tinkered with directly 40 41r0 holds returns of <= 4 bytes 42r0-r1 hold returns of 8 bytes, low word in r0 43 44Callee must save/restore r4+ (except r12) if it modifies them. If VFP 45is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46s0-s15 (d0-d7, q0-a3) do not need to be. 47 48Stack is "full descending". Only the arguments that don't fit in the first 4 49registers are placed on the stack. "sp" points at the first stacked argument 50(i.e. the 5th arg). 51 52VFP: single-precision results in s0, double-precision results in d0. 53 54In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 5564-bit quantities (long long, double) must be 64-bit aligned. 56*/ 57 58/* 59Mterp and ARM notes: 60 61The following registers have fixed assignments: 62 63 reg nick purpose 64 r4 rPC interpreted program counter, used for fetching instructions 65 r5 rFP interpreted frame pointer, used for accessing locals and args 66 r6 rSELF self (Thread) pointer 67 r7 rINST first 16-bit code unit of current instruction 68 r8 rIBASE interpreted instruction base pointer, used for computed goto 69 70Macros are provided for common operations. Each macro MUST emit only 71one instruction to make instruction-counting easier. They MUST NOT alter 72unspecified registers or condition codes. 73*/ 74 75/* single-purpose registers, given names for clarity */ 76#define rPC r4 77#define rFP r5 78#define rSELF r6 79#define rINST r7 80#define rIBASE r8 81 82/* save/restore the PC and/or FP from the thread struct */ 83#define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc] 84#define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc] 85#define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_fp] 86#define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_fp] 87#define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP} 88#define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP} 89 90/* 91 * "export" the PC to the stack frame, f/b/o future exception objects. Must 92 * be done *before* something throws. 93 * 94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96 * 97 * It's okay to do this more than once. 98 */ 99#define EXPORT_PC() \ 100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101 102/* 103 * Given a frame pointer, find the stack save area. 104 * 105 * In C this is "((StackSaveArea*)(_fp) -1)". 106 */ 107#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108 sub _reg, _fpreg, #sizeofStackSaveArea 109 110/* 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112 */ 113#define FETCH_INST() ldrh rINST, [rPC] 114 115/* 116 * Fetch the next instruction from the specified offset. Advances rPC 117 * to point to the next instruction. "_count" is in 16-bit code units. 118 * 119 * Because of the limited size of immediate constants on ARM, this is only 120 * suitable for small forward movements (i.e. don't try to implement "goto" 121 * with this). 122 * 123 * This must come AFTER anything that can throw an exception, or the 124 * exception catch may miss. (This also implies that it must come after 125 * EXPORT_PC().) 126 */ 127#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 128 129/* 130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132 */ 133#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134 ldrh _dreg, [_sreg, #((_count)*2)]! 135 136/* 137 * Fetch the next instruction from an offset specified by _reg. Updates 138 * rPC to point to the next instruction. "_reg" must specify the distance 139 * in bytes, *not* 16-bit code units, and may be a signed value. 140 * 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 142 * bits that hold the shift distance are used for the half/byte/sign flags. 143 * In some cases we can pre-double _reg for free, so we require a byte offset 144 * here. 145 */ 146#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147 148/* 149 * Fetch a half-word code unit from an offset past the current PC. The 150 * "_count" value is in 16-bit code units. Does not advance rPC. 151 * 152 * The "_S" variant works the same but treats the value as signed. 153 */ 154#define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)] 155#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #((_count)*2)] 156 157/* 158 * Fetch one byte from an offset past the current PC. Pass in the same 159 * "_count" as you would for FETCH, and an additional 0/1 indicating which 160 * byte of the halfword you want (lo/hi). 161 */ 162#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #((_count)*2+(_byte))] 163 164/* 165 * Put the instruction's opcode field into the specified register. 166 */ 167#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168 169/* 170 * Put the prefetched instruction's opcode field into the specified register. 171 */ 172#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173 174/* 175 * Begin executing the opcode in _reg. Because this only jumps within the 176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177 */ 178#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 180#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 181 182/* 183 * Get/set the 32-bit value from a Dalvik register. 184 */ 185#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 186#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 187 188#if defined(WITH_JIT) 189#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rSELF,#offThread_pJitProfTable] 190#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rSELF,#offThread_jitThreshold] 191#endif 192 193/* 194 * Convert a virtual register index into an address. 195 */ 196#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 197 add _reg, rFP, _vreg, lsl #2 198 199/* 200 * This is a #include, not a %include, because we want the C pre-processor 201 * to expand the macros into assembler assignment statements. 202 */ 203#include "../common/asm-constants.h" 204 205#if defined(WITH_JIT) 206#include "../common/jit-config.h" 207#endif 208 209/* File: armv5te/platform.S */ 210/* 211 * =========================================================================== 212 * CPU-version-specific defines 213 * =========================================================================== 214 */ 215 216/* 217 * Macro for data memory barrier; not meaningful pre-ARMv6K. 218 */ 219.macro SMP_DMB 220.endm 221 222/* 223 * Macro for data memory barrier; not meaningful pre-ARMv6K. 224 */ 225.macro SMP_DMB_ST 226.endm 227 228/* File: armv5te/entry.S */ 229/* 230 * Copyright (C) 2008 The Android Open Source Project 231 * 232 * Licensed under the Apache License, Version 2.0 (the "License"); 233 * you may not use this file except in compliance with the License. 234 * You may obtain a copy of the License at 235 * 236 * http://www.apache.org/licenses/LICENSE-2.0 237 * 238 * Unless required by applicable law or agreed to in writing, software 239 * distributed under the License is distributed on an "AS IS" BASIS, 240 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 241 * See the License for the specific language governing permissions and 242 * limitations under the License. 243 */ 244/* 245 * Interpreter entry point. 246 */ 247 248/* 249 * We don't have formal stack frames, so gdb scans upward in the code 250 * to find the start of the function (a label with the %function type), 251 * and then looks at the next few instructions to figure out what 252 * got pushed onto the stack. From this it figures out how to restore 253 * the registers, including PC, for the previous stack frame. If gdb 254 * sees a non-function label, it stops scanning, so either we need to 255 * have nothing but assembler-local labels between the entry point and 256 * the break, or we need to fake it out. 257 * 258 * When this is defined, we add some stuff to make gdb less confused. 259 */ 260#define ASSIST_DEBUGGER 1 261 262 .text 263 .align 2 264 .global dvmMterpStdRun 265 .type dvmMterpStdRun, %function 266 267/* 268 * On entry: 269 * r0 Thread* self 270 * 271 * This function returns a boolean "changeInterp" value. The return comes 272 * via a call to dvmMterpStdBail(). 273 */ 274dvmMterpStdRun: 275#define MTERP_ENTRY1 \ 276 .save {r4-r10,fp,lr}; \ 277 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 278#define MTERP_ENTRY2 \ 279 .pad #4; \ 280 sub sp, sp, #4 @ align 64 281 282 .fnstart 283 MTERP_ENTRY1 284 MTERP_ENTRY2 285 286 /* save stack pointer, add magic word for debuggerd */ 287 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return 288 289 /* set up "named" registers, figure out entry point */ 290 mov rSELF, r0 @ set rSELF 291 ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI 292 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread" 293 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE 294 cmp r1, #kInterpEntryInstr @ usual case? 295 bne .Lnot_instr @ no, handle it 296 297#if defined(WITH_JIT) 298.LentryInstr: 299 /* Entry is always a possible trace start */ 300 GET_JIT_PROF_TABLE(r0) 301 FETCH_INST() 302 mov r1, #0 @ prepare the value for the new state 303 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 304 cmp r0,#0 @ is profiling disabled? 305#if !defined(WITH_SELF_VERIFICATION) 306 bne common_updateProfile @ profiling is enabled 307#else 308 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state 309 beq 1f @ profiling is disabled 310 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 311 cmp r3, #kSVSTraceSelect @ hot trace following? 312 moveq r2,#kJitTSelectRequestHot @ ask for trace selection 313 beq common_selectTrace @ go build the trace 314 cmp r3, #kSVSNoProfile @ don't profile the next instruction? 315 beq 1f @ intrepret the next instruction 316 b common_updateProfile @ collect profiles 317#endif 3181: 319 GET_INST_OPCODE(ip) 320 GOTO_OPCODE(ip) 321#else 322 /* start executing the instruction at rPC */ 323 FETCH_INST() @ load rINST from rPC 324 GET_INST_OPCODE(ip) @ extract opcode from rINST 325 GOTO_OPCODE(ip) @ jump to next instruction 326#endif 327 328.Lnot_instr: 329 cmp r1, #kInterpEntryReturn @ were we returning from a method? 330 beq common_returnFromMethod 331 332.Lnot_return: 333 cmp r1, #kInterpEntryThrow @ were we throwing an exception? 334 beq common_exceptionThrown 335 336#if defined(WITH_JIT) 337.Lnot_throw: 338 ldr r10,[rSELF, #offThread_jitResumeNPC] 339 ldr r2,[rSELF, #offThread_jitResumeDPC] 340 cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 341 bne .Lbad_arg 342 cmp rPC,r2 343 bne .LentryInstr @ must have branched, don't resume 344#if defined(WITH_SELF_VERIFICATION) 345 @ self->entryPoint will be set in dvmSelfVerificationSaveState 346 b jitSVShadowRunStart @ re-enter the translation after the 347 @ single-stepped instruction 348 @noreturn 349#endif 350 mov r1, #kInterpEntryInstr 351 str r1, [rSELF, #offThread_entryPoint] 352 bx r10 @ re-enter the translation 353#endif 354 355.Lbad_arg: 356 ldr r0, strBadEntryPoint 357 @ r1 holds value of entryPoint 358 bl printf 359 bl dvmAbort 360 .fnend 361 .size dvmMterpStdRun, .-dvmMterpStdRun 362 363 364 .global dvmMterpStdBail 365 .type dvmMterpStdBail, %function 366 367/* 368 * Restore the stack pointer and PC from the save point established on entry. 369 * This is essentially the same as a longjmp, but should be cheaper. The 370 * last instruction causes us to return to whoever called dvmMterpStdRun. 371 * 372 * We pushed some registers on the stack in dvmMterpStdRun, then saved 373 * SP and LR. Here we restore SP, restore the registers, and then restore 374 * LR to PC. 375 * 376 * On entry: 377 * r0 Thread* self 378 * r1 bool changeInterp 379 */ 380dvmMterpStdBail: 381 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP 382 mov r0, r1 @ return the changeInterp value 383 add sp, sp, #4 @ un-align 64 384 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return 385 386 387/* 388 * String references. 389 */ 390strBadEntryPoint: 391 .word .LstrBadEntryPoint 392 393 394 .global dvmAsmInstructionStart 395 .type dvmAsmInstructionStart, %function 396dvmAsmInstructionStart = .L_OP_NOP 397 .text 398 399/* ------------------------------ */ 400 .balign 64 401.L_OP_NOP: /* 0x00 */ 402/* File: armv5te/OP_NOP.S */ 403 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 404 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 405 GOTO_OPCODE(ip) @ execute it 406 407#ifdef ASSIST_DEBUGGER 408 /* insert fake function header to help gdb find the stack frame */ 409 .type dalvik_inst, %function 410dalvik_inst: 411 .fnstart 412 MTERP_ENTRY1 413 MTERP_ENTRY2 414 .fnend 415#endif 416 417/* ------------------------------ */ 418 .balign 64 419.L_OP_MOVE: /* 0x01 */ 420/* File: armv5te/OP_MOVE.S */ 421 /* for move, move-object, long-to-int */ 422 /* op vA, vB */ 423 mov r1, rINST, lsr #12 @ r1<- B from 15:12 424 mov r0, rINST, lsr #8 @ r0<- A from 11:8 425 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 426 GET_VREG(r2, r1) @ r2<- fp[B] 427 and r0, r0, #15 428 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 429 SET_VREG(r2, r0) @ fp[A]<- r2 430 GOTO_OPCODE(ip) @ execute next instruction 431 432/* ------------------------------ */ 433 .balign 64 434.L_OP_MOVE_FROM16: /* 0x02 */ 435/* File: armv5te/OP_MOVE_FROM16.S */ 436 /* for: move/from16, move-object/from16 */ 437 /* op vAA, vBBBB */ 438 FETCH(r1, 1) @ r1<- BBBB 439 mov r0, rINST, lsr #8 @ r0<- AA 440 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 441 GET_VREG(r2, r1) @ r2<- fp[BBBB] 442 GET_INST_OPCODE(ip) @ extract opcode from rINST 443 SET_VREG(r2, r0) @ fp[AA]<- r2 444 GOTO_OPCODE(ip) @ jump to next instruction 445 446/* ------------------------------ */ 447 .balign 64 448.L_OP_MOVE_16: /* 0x03 */ 449/* File: armv5te/OP_MOVE_16.S */ 450 /* for: move/16, move-object/16 */ 451 /* op vAAAA, vBBBB */ 452 FETCH(r1, 2) @ r1<- BBBB 453 FETCH(r0, 1) @ r0<- AAAA 454 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 455 GET_VREG(r2, r1) @ r2<- fp[BBBB] 456 GET_INST_OPCODE(ip) @ extract opcode from rINST 457 SET_VREG(r2, r0) @ fp[AAAA]<- r2 458 GOTO_OPCODE(ip) @ jump to next instruction 459 460/* ------------------------------ */ 461 .balign 64 462.L_OP_MOVE_WIDE: /* 0x04 */ 463/* File: armv5te/OP_MOVE_WIDE.S */ 464 /* move-wide vA, vB */ 465 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 466 mov r2, rINST, lsr #8 @ r2<- A(+) 467 mov r3, rINST, lsr #12 @ r3<- B 468 and r2, r2, #15 469 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 470 add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 471 ldmia r3, {r0-r1} @ r0/r1<- fp[B] 472 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 473 GET_INST_OPCODE(ip) @ extract opcode from rINST 474 stmia r2, {r0-r1} @ fp[A]<- r0/r1 475 GOTO_OPCODE(ip) @ jump to next instruction 476 477/* ------------------------------ */ 478 .balign 64 479.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 480/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 481 /* move-wide/from16 vAA, vBBBB */ 482 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 483 FETCH(r3, 1) @ r3<- BBBB 484 mov r2, rINST, lsr #8 @ r2<- AA 485 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 486 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 487 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 488 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 489 GET_INST_OPCODE(ip) @ extract opcode from rINST 490 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 491 GOTO_OPCODE(ip) @ jump to next instruction 492 493/* ------------------------------ */ 494 .balign 64 495.L_OP_MOVE_WIDE_16: /* 0x06 */ 496/* File: armv5te/OP_MOVE_WIDE_16.S */ 497 /* move-wide/16 vAAAA, vBBBB */ 498 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 499 FETCH(r3, 2) @ r3<- BBBB 500 FETCH(r2, 1) @ r2<- AAAA 501 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 502 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 503 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 504 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 505 GET_INST_OPCODE(ip) @ extract opcode from rINST 506 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 507 GOTO_OPCODE(ip) @ jump to next instruction 508 509/* ------------------------------ */ 510 .balign 64 511.L_OP_MOVE_OBJECT: /* 0x07 */ 512/* File: armv5te/OP_MOVE_OBJECT.S */ 513/* File: armv5te/OP_MOVE.S */ 514 /* for move, move-object, long-to-int */ 515 /* op vA, vB */ 516 mov r1, rINST, lsr #12 @ r1<- B from 15:12 517 mov r0, rINST, lsr #8 @ r0<- A from 11:8 518 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 519 GET_VREG(r2, r1) @ r2<- fp[B] 520 and r0, r0, #15 521 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 522 SET_VREG(r2, r0) @ fp[A]<- r2 523 GOTO_OPCODE(ip) @ execute next instruction 524 525 526/* ------------------------------ */ 527 .balign 64 528.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 529/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 530/* File: armv5te/OP_MOVE_FROM16.S */ 531 /* for: move/from16, move-object/from16 */ 532 /* op vAA, vBBBB */ 533 FETCH(r1, 1) @ r1<- BBBB 534 mov r0, rINST, lsr #8 @ r0<- AA 535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 536 GET_VREG(r2, r1) @ r2<- fp[BBBB] 537 GET_INST_OPCODE(ip) @ extract opcode from rINST 538 SET_VREG(r2, r0) @ fp[AA]<- r2 539 GOTO_OPCODE(ip) @ jump to next instruction 540 541 542/* ------------------------------ */ 543 .balign 64 544.L_OP_MOVE_OBJECT_16: /* 0x09 */ 545/* File: armv5te/OP_MOVE_OBJECT_16.S */ 546/* File: armv5te/OP_MOVE_16.S */ 547 /* for: move/16, move-object/16 */ 548 /* op vAAAA, vBBBB */ 549 FETCH(r1, 2) @ r1<- BBBB 550 FETCH(r0, 1) @ r0<- AAAA 551 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 552 GET_VREG(r2, r1) @ r2<- fp[BBBB] 553 GET_INST_OPCODE(ip) @ extract opcode from rINST 554 SET_VREG(r2, r0) @ fp[AAAA]<- r2 555 GOTO_OPCODE(ip) @ jump to next instruction 556 557 558/* ------------------------------ */ 559 .balign 64 560.L_OP_MOVE_RESULT: /* 0x0a */ 561/* File: armv5te/OP_MOVE_RESULT.S */ 562 /* for: move-result, move-result-object */ 563 /* op vAA */ 564 mov r2, rINST, lsr #8 @ r2<- AA 565 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 566 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 567 GET_INST_OPCODE(ip) @ extract opcode from rINST 568 SET_VREG(r0, r2) @ fp[AA]<- r0 569 GOTO_OPCODE(ip) @ jump to next instruction 570 571/* ------------------------------ */ 572 .balign 64 573.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 574/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 575 /* move-result-wide vAA */ 576 mov r2, rINST, lsr #8 @ r2<- AA 577 add r3, rSELF, #offThread_retval @ r3<- &self->retval 578 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 579 ldmia r3, {r0-r1} @ r0/r1<- retval.j 580 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 581 GET_INST_OPCODE(ip) @ extract opcode from rINST 582 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 583 GOTO_OPCODE(ip) @ jump to next instruction 584 585/* ------------------------------ */ 586 .balign 64 587.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 588/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 589/* File: armv5te/OP_MOVE_RESULT.S */ 590 /* for: move-result, move-result-object */ 591 /* op vAA */ 592 mov r2, rINST, lsr #8 @ r2<- AA 593 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 594 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 595 GET_INST_OPCODE(ip) @ extract opcode from rINST 596 SET_VREG(r0, r2) @ fp[AA]<- r0 597 GOTO_OPCODE(ip) @ jump to next instruction 598 599 600/* ------------------------------ */ 601 .balign 64 602.L_OP_MOVE_EXCEPTION: /* 0x0d */ 603/* File: armv5te/OP_MOVE_EXCEPTION.S */ 604 /* move-exception vAA */ 605 mov r2, rINST, lsr #8 @ r2<- AA 606 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass 607 mov r1, #0 @ r1<- 0 608 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 609 SET_VREG(r3, r2) @ fp[AA]<- exception obj 610 GET_INST_OPCODE(ip) @ extract opcode from rINST 611 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass 612 GOTO_OPCODE(ip) @ jump to next instruction 613 614/* ------------------------------ */ 615 .balign 64 616.L_OP_RETURN_VOID: /* 0x0e */ 617/* File: armv5te/OP_RETURN_VOID.S */ 618 b common_returnFromMethod 619 620/* ------------------------------ */ 621 .balign 64 622.L_OP_RETURN: /* 0x0f */ 623/* File: armv5te/OP_RETURN.S */ 624 /* 625 * Return a 32-bit value. Copies the return value into the "thread" 626 * structure, then jumps to the return handler. 627 * 628 * for: return, return-object 629 */ 630 /* op vAA */ 631 mov r2, rINST, lsr #8 @ r2<- AA 632 GET_VREG(r0, r2) @ r0<- vAA 633 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 634 b common_returnFromMethod 635 636/* ------------------------------ */ 637 .balign 64 638.L_OP_RETURN_WIDE: /* 0x10 */ 639/* File: armv5te/OP_RETURN_WIDE.S */ 640 /* 641 * Return a 64-bit value. Copies the return value into the "thread" 642 * structure, then jumps to the return handler. 643 */ 644 /* return-wide vAA */ 645 mov r2, rINST, lsr #8 @ r2<- AA 646 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 647 add r3, rSELF, #offThread_retval @ r3<- &self->retval 648 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 649 stmia r3, {r0-r1} @ retval<- r0/r1 650 b common_returnFromMethod 651 652/* ------------------------------ */ 653 .balign 64 654.L_OP_RETURN_OBJECT: /* 0x11 */ 655/* File: armv5te/OP_RETURN_OBJECT.S */ 656/* File: armv5te/OP_RETURN.S */ 657 /* 658 * Return a 32-bit value. Copies the return value into the "thread" 659 * structure, then jumps to the return handler. 660 * 661 * for: return, return-object 662 */ 663 /* op vAA */ 664 mov r2, rINST, lsr #8 @ r2<- AA 665 GET_VREG(r0, r2) @ r0<- vAA 666 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 667 b common_returnFromMethod 668 669 670/* ------------------------------ */ 671 .balign 64 672.L_OP_CONST_4: /* 0x12 */ 673/* File: armv5te/OP_CONST_4.S */ 674 /* const/4 vA, #+B */ 675 mov r1, rINST, lsl #16 @ r1<- Bxxx0000 676 mov r0, rINST, lsr #8 @ r0<- A+ 677 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 678 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 679 and r0, r0, #15 680 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 681 SET_VREG(r1, r0) @ fp[A]<- r1 682 GOTO_OPCODE(ip) @ execute next instruction 683 684/* ------------------------------ */ 685 .balign 64 686.L_OP_CONST_16: /* 0x13 */ 687/* File: armv5te/OP_CONST_16.S */ 688 /* const/16 vAA, #+BBBB */ 689 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 690 mov r3, rINST, lsr #8 @ r3<- AA 691 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 692 SET_VREG(r0, r3) @ vAA<- r0 693 GET_INST_OPCODE(ip) @ extract opcode from rINST 694 GOTO_OPCODE(ip) @ jump to next instruction 695 696/* ------------------------------ */ 697 .balign 64 698.L_OP_CONST: /* 0x14 */ 699/* File: armv5te/OP_CONST.S */ 700 /* const vAA, #+BBBBbbbb */ 701 mov r3, rINST, lsr #8 @ r3<- AA 702 FETCH(r0, 1) @ r0<- bbbb (low) 703 FETCH(r1, 2) @ r1<- BBBB (high) 704 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 705 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 706 GET_INST_OPCODE(ip) @ extract opcode from rINST 707 SET_VREG(r0, r3) @ vAA<- r0 708 GOTO_OPCODE(ip) @ jump to next instruction 709 710/* ------------------------------ */ 711 .balign 64 712.L_OP_CONST_HIGH16: /* 0x15 */ 713/* File: armv5te/OP_CONST_HIGH16.S */ 714 /* const/high16 vAA, #+BBBB0000 */ 715 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 716 mov r3, rINST, lsr #8 @ r3<- AA 717 mov r0, r0, lsl #16 @ r0<- BBBB0000 718 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 719 SET_VREG(r0, r3) @ vAA<- r0 720 GET_INST_OPCODE(ip) @ extract opcode from rINST 721 GOTO_OPCODE(ip) @ jump to next instruction 722 723/* ------------------------------ */ 724 .balign 64 725.L_OP_CONST_WIDE_16: /* 0x16 */ 726/* File: armv5te/OP_CONST_WIDE_16.S */ 727 /* const-wide/16 vAA, #+BBBB */ 728 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 729 mov r3, rINST, lsr #8 @ r3<- AA 730 mov r1, r0, asr #31 @ r1<- ssssssss 731 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 732 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 733 GET_INST_OPCODE(ip) @ extract opcode from rINST 734 stmia r3, {r0-r1} @ vAA<- r0/r1 735 GOTO_OPCODE(ip) @ jump to next instruction 736 737/* ------------------------------ */ 738 .balign 64 739.L_OP_CONST_WIDE_32: /* 0x17 */ 740/* File: armv5te/OP_CONST_WIDE_32.S */ 741 /* const-wide/32 vAA, #+BBBBbbbb */ 742 FETCH(r0, 1) @ r0<- 0000bbbb (low) 743 mov r3, rINST, lsr #8 @ r3<- AA 744 FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 745 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 746 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 747 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 748 mov r1, r0, asr #31 @ r1<- ssssssss 749 GET_INST_OPCODE(ip) @ extract opcode from rINST 750 stmia r3, {r0-r1} @ vAA<- r0/r1 751 GOTO_OPCODE(ip) @ jump to next instruction 752 753/* ------------------------------ */ 754 .balign 64 755.L_OP_CONST_WIDE: /* 0x18 */ 756/* File: armv5te/OP_CONST_WIDE.S */ 757 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 758 FETCH(r0, 1) @ r0<- bbbb (low) 759 FETCH(r1, 2) @ r1<- BBBB (low middle) 760 FETCH(r2, 3) @ r2<- hhhh (high middle) 761 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 762 FETCH(r3, 4) @ r3<- HHHH (high) 763 mov r9, rINST, lsr #8 @ r9<- AA 764 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 765 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 766 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 767 GET_INST_OPCODE(ip) @ extract opcode from rINST 768 stmia r9, {r0-r1} @ vAA<- r0/r1 769 GOTO_OPCODE(ip) @ jump to next instruction 770 771/* ------------------------------ */ 772 .balign 64 773.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 774/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 775 /* const-wide/high16 vAA, #+BBBB000000000000 */ 776 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 777 mov r3, rINST, lsr #8 @ r3<- AA 778 mov r0, #0 @ r0<- 00000000 779 mov r1, r1, lsl #16 @ r1<- BBBB0000 780 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 781 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 782 GET_INST_OPCODE(ip) @ extract opcode from rINST 783 stmia r3, {r0-r1} @ vAA<- r0/r1 784 GOTO_OPCODE(ip) @ jump to next instruction 785 786/* ------------------------------ */ 787 .balign 64 788.L_OP_CONST_STRING: /* 0x1a */ 789/* File: armv5te/OP_CONST_STRING.S */ 790 /* const/string vAA, String@BBBB */ 791 FETCH(r1, 1) @ r1<- BBBB 792 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 793 mov r9, rINST, lsr #8 @ r9<- AA 794 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 795 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 796 cmp r0, #0 @ not yet resolved? 797 beq .LOP_CONST_STRING_resolve 798 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 799 GET_INST_OPCODE(ip) @ extract opcode from rINST 800 SET_VREG(r0, r9) @ vAA<- r0 801 GOTO_OPCODE(ip) @ jump to next instruction 802 803/* ------------------------------ */ 804 .balign 64 805.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 806/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 807 /* const/string vAA, String@BBBBBBBB */ 808 FETCH(r0, 1) @ r0<- bbbb (low) 809 FETCH(r1, 2) @ r1<- BBBB (high) 810 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 811 mov r9, rINST, lsr #8 @ r9<- AA 812 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 813 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 814 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 815 cmp r0, #0 816 beq .LOP_CONST_STRING_JUMBO_resolve 817 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 818 GET_INST_OPCODE(ip) @ extract opcode from rINST 819 SET_VREG(r0, r9) @ vAA<- r0 820 GOTO_OPCODE(ip) @ jump to next instruction 821 822/* ------------------------------ */ 823 .balign 64 824.L_OP_CONST_CLASS: /* 0x1c */ 825/* File: armv5te/OP_CONST_CLASS.S */ 826 /* const/class vAA, Class@BBBB */ 827 FETCH(r1, 1) @ r1<- BBBB 828 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 829 mov r9, rINST, lsr #8 @ r9<- AA 830 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 831 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 832 cmp r0, #0 @ not yet resolved? 833 beq .LOP_CONST_CLASS_resolve 834 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 835 GET_INST_OPCODE(ip) @ extract opcode from rINST 836 SET_VREG(r0, r9) @ vAA<- r0 837 GOTO_OPCODE(ip) @ jump to next instruction 838 839/* ------------------------------ */ 840 .balign 64 841.L_OP_MONITOR_ENTER: /* 0x1d */ 842/* File: armv5te/OP_MONITOR_ENTER.S */ 843 /* 844 * Synchronize on an object. 845 */ 846 /* monitor-enter vAA */ 847 mov r2, rINST, lsr #8 @ r2<- AA 848 GET_VREG(r1, r2) @ r1<- vAA (object) 849 mov r0, rSELF @ r0<- self 850 cmp r1, #0 @ null object? 851 EXPORT_PC() @ need for precise GC 852 beq common_errNullObject @ null object, throw an exception 853 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 854 bl dvmLockObject @ call(self, obj) 855 GET_INST_OPCODE(ip) @ extract opcode from rINST 856 GOTO_OPCODE(ip) @ jump to next instruction 857 858/* ------------------------------ */ 859 .balign 64 860.L_OP_MONITOR_EXIT: /* 0x1e */ 861/* File: armv5te/OP_MONITOR_EXIT.S */ 862 /* 863 * Unlock an object. 864 * 865 * Exceptions that occur when unlocking a monitor need to appear as 866 * if they happened at the following instruction. See the Dalvik 867 * instruction spec. 868 */ 869 /* monitor-exit vAA */ 870 mov r2, rINST, lsr #8 @ r2<- AA 871 EXPORT_PC() @ before fetch: export the PC 872 GET_VREG(r1, r2) @ r1<- vAA (object) 873 cmp r1, #0 @ null object? 874 beq 1f @ yes 875 mov r0, rSELF @ r0<- self 876 bl dvmUnlockObject @ r0<- success for unlock(self, obj) 877 cmp r0, #0 @ failed? 878 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 879 beq common_exceptionThrown @ yes, exception is pending 880 GET_INST_OPCODE(ip) @ extract opcode from rINST 881 GOTO_OPCODE(ip) @ jump to next instruction 8821: 883 FETCH_ADVANCE_INST(1) @ advance before throw 884 b common_errNullObject 885 886/* ------------------------------ */ 887 .balign 64 888.L_OP_CHECK_CAST: /* 0x1f */ 889/* File: armv5te/OP_CHECK_CAST.S */ 890 /* 891 * Check to see if a cast from one class to another is allowed. 892 */ 893 /* check-cast vAA, class@BBBB */ 894 mov r3, rINST, lsr #8 @ r3<- AA 895 FETCH(r2, 1) @ r2<- BBBB 896 GET_VREG(r9, r3) @ r9<- object 897 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 898 cmp r9, #0 @ is object null? 899 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 900 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 901 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 902 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 903 cmp r1, #0 @ have we resolved this before? 904 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 905.LOP_CHECK_CAST_resolved: 906 cmp r0, r1 @ same class (trivial success)? 907 bne .LOP_CHECK_CAST_fullcheck @ no, do full check 908.LOP_CHECK_CAST_okay: 909 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 910 GET_INST_OPCODE(ip) @ extract opcode from rINST 911 GOTO_OPCODE(ip) @ jump to next instruction 912 913/* ------------------------------ */ 914 .balign 64 915.L_OP_INSTANCE_OF: /* 0x20 */ 916/* File: armv5te/OP_INSTANCE_OF.S */ 917 /* 918 * Check to see if an object reference is an instance of a class. 919 * 920 * Most common situation is a non-null object, being compared against 921 * an already-resolved class. 922 */ 923 /* instance-of vA, vB, class@CCCC */ 924 mov r3, rINST, lsr #12 @ r3<- B 925 mov r9, rINST, lsr #8 @ r9<- A+ 926 GET_VREG(r0, r3) @ r0<- vB (object) 927 and r9, r9, #15 @ r9<- A 928 cmp r0, #0 @ is object null? 929 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 930 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 931 FETCH(r3, 1) @ r3<- CCCC 932 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 933 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 934 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 935 cmp r1, #0 @ have we resolved this before? 936 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 937.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 938 cmp r0, r1 @ same class (trivial success)? 939 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 940 b .LOP_INSTANCE_OF_fullcheck @ no, do full check 941 942/* ------------------------------ */ 943 .balign 64 944.L_OP_ARRAY_LENGTH: /* 0x21 */ 945/* File: armv5te/OP_ARRAY_LENGTH.S */ 946 /* 947 * Return the length of an array. 948 */ 949 mov r1, rINST, lsr #12 @ r1<- B 950 mov r2, rINST, lsr #8 @ r2<- A+ 951 GET_VREG(r0, r1) @ r0<- vB (object ref) 952 and r2, r2, #15 @ r2<- A 953 cmp r0, #0 @ is object null? 954 beq common_errNullObject @ yup, fail 955 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 956 ldr r3, [r0, #offArrayObject_length] @ r3<- array length 957 GET_INST_OPCODE(ip) @ extract opcode from rINST 958 SET_VREG(r3, r2) @ vB<- length 959 GOTO_OPCODE(ip) @ jump to next instruction 960 961/* ------------------------------ */ 962 .balign 64 963.L_OP_NEW_INSTANCE: /* 0x22 */ 964/* File: armv5te/OP_NEW_INSTANCE.S */ 965 /* 966 * Create a new instance of a class. 967 */ 968 /* new-instance vAA, class@BBBB */ 969 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 970 FETCH(r1, 1) @ r1<- BBBB 971 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 972 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 973 EXPORT_PC() @ req'd for init, resolve, alloc 974 cmp r0, #0 @ already resolved? 975 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 976.LOP_NEW_INSTANCE_resolved: @ r0=class 977 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 978 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 979 bne .LOP_NEW_INSTANCE_needinit @ no, init class now 980.LOP_NEW_INSTANCE_initialized: @ r0=class 981 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 982 bl dvmAllocObject @ r0<- new object 983 b .LOP_NEW_INSTANCE_finish @ continue 984 985/* ------------------------------ */ 986 .balign 64 987.L_OP_NEW_ARRAY: /* 0x23 */ 988/* File: armv5te/OP_NEW_ARRAY.S */ 989 /* 990 * Allocate an array of objects, specified with the array class 991 * and a count. 992 * 993 * The verifier guarantees that this is an array class, so we don't 994 * check for it here. 995 */ 996 /* new-array vA, vB, class@CCCC */ 997 mov r0, rINST, lsr #12 @ r0<- B 998 FETCH(r2, 1) @ r2<- CCCC 999 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1000 GET_VREG(r1, r0) @ r1<- vB (array length) 1001 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1002 cmp r1, #0 @ check length 1003 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1004 bmi common_errNegativeArraySize @ negative length, bail - len in r1 1005 cmp r0, #0 @ already resolved? 1006 EXPORT_PC() @ req'd for resolve, alloc 1007 bne .LOP_NEW_ARRAY_finish @ resolved, continue 1008 b .LOP_NEW_ARRAY_resolve @ do resolve now 1009 1010/* ------------------------------ */ 1011 .balign 64 1012.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1013/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1014 /* 1015 * Create a new array with elements filled from registers. 1016 * 1017 * for: filled-new-array, filled-new-array/range 1018 */ 1019 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1020 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1021 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1022 FETCH(r1, 1) @ r1<- BBBB 1023 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1024 EXPORT_PC() @ need for resolve and alloc 1025 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1026 mov r10, rINST, lsr #8 @ r10<- AA or BA 1027 cmp r0, #0 @ already resolved? 1028 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 10298: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1030 mov r2, #0 @ r2<- false 1031 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1032 bl dvmResolveClass @ r0<- call(clazz, ref) 1033 cmp r0, #0 @ got null? 1034 beq common_exceptionThrown @ yes, handle exception 1035 b .LOP_FILLED_NEW_ARRAY_continue 1036 1037/* ------------------------------ */ 1038 .balign 64 1039.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1040/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1041/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1042 /* 1043 * Create a new array with elements filled from registers. 1044 * 1045 * for: filled-new-array, filled-new-array/range 1046 */ 1047 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1048 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1049 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1050 FETCH(r1, 1) @ r1<- BBBB 1051 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1052 EXPORT_PC() @ need for resolve and alloc 1053 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1054 mov r10, rINST, lsr #8 @ r10<- AA or BA 1055 cmp r0, #0 @ already resolved? 1056 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 10578: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1058 mov r2, #0 @ r2<- false 1059 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1060 bl dvmResolveClass @ r0<- call(clazz, ref) 1061 cmp r0, #0 @ got null? 1062 beq common_exceptionThrown @ yes, handle exception 1063 b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1064 1065 1066/* ------------------------------ */ 1067 .balign 64 1068.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1069/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1070 /* fill-array-data vAA, +BBBBBBBB */ 1071 FETCH(r0, 1) @ r0<- bbbb (lo) 1072 FETCH(r1, 2) @ r1<- BBBB (hi) 1073 mov r3, rINST, lsr #8 @ r3<- AA 1074 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1075 GET_VREG(r0, r3) @ r0<- vAA (array object) 1076 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1077 EXPORT_PC(); 1078 bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1079 cmp r0, #0 @ 0 means an exception is thrown 1080 beq common_exceptionThrown @ has exception 1081 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1082 GET_INST_OPCODE(ip) @ extract opcode from rINST 1083 GOTO_OPCODE(ip) @ jump to next instruction 1084 1085/* ------------------------------ */ 1086 .balign 64 1087.L_OP_THROW: /* 0x27 */ 1088/* File: armv5te/OP_THROW.S */ 1089 /* 1090 * Throw an exception object in the current thread. 1091 */ 1092 /* throw vAA */ 1093 mov r2, rINST, lsr #8 @ r2<- AA 1094 GET_VREG(r1, r2) @ r1<- vAA (exception object) 1095 EXPORT_PC() @ exception handler can throw 1096 cmp r1, #0 @ null object? 1097 beq common_errNullObject @ yes, throw an NPE instead 1098 @ bypass dvmSetException, just store it 1099 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj 1100 b common_exceptionThrown 1101 1102/* ------------------------------ */ 1103 .balign 64 1104.L_OP_GOTO: /* 0x28 */ 1105/* File: armv5te/OP_GOTO.S */ 1106 /* 1107 * Unconditional branch, 8-bit offset. 1108 * 1109 * The branch distance is a signed code-unit offset, which we need to 1110 * double to get a byte offset. 1111 */ 1112 /* goto +AA */ 1113 mov r0, rINST, lsl #16 @ r0<- AAxx0000 1114 movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1115 mov r9, r9, lsl #1 @ r9<- byte offset 1116 bmi common_backwardBranch @ backward branch, do periodic checks 1117#if defined(WITH_JIT) 1118 GET_JIT_PROF_TABLE(r0) 1119 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1120 cmp r0,#0 1121 bne common_updateProfile 1122 GET_INST_OPCODE(ip) @ extract opcode from rINST 1123 GOTO_OPCODE(ip) @ jump to next instruction 1124#else 1125 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1126 GET_INST_OPCODE(ip) @ extract opcode from rINST 1127 GOTO_OPCODE(ip) @ jump to next instruction 1128#endif 1129 1130/* ------------------------------ */ 1131 .balign 64 1132.L_OP_GOTO_16: /* 0x29 */ 1133/* File: armv5te/OP_GOTO_16.S */ 1134 /* 1135 * Unconditional branch, 16-bit offset. 1136 * 1137 * The branch distance is a signed code-unit offset, which we need to 1138 * double to get a byte offset. 1139 */ 1140 /* goto/16 +AAAA */ 1141 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1142 movs r9, r0, asl #1 @ r9<- byte offset, check sign 1143 bmi common_backwardBranch @ backward branch, do periodic checks 1144#if defined(WITH_JIT) 1145 GET_JIT_PROF_TABLE(r0) 1146 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1147 cmp r0,#0 1148 bne common_updateProfile 1149 GET_INST_OPCODE(ip) @ extract opcode from rINST 1150 GOTO_OPCODE(ip) @ jump to next instruction 1151#else 1152 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1153 GET_INST_OPCODE(ip) @ extract opcode from rINST 1154 GOTO_OPCODE(ip) @ jump to next instruction 1155#endif 1156 1157/* ------------------------------ */ 1158 .balign 64 1159.L_OP_GOTO_32: /* 0x2a */ 1160/* File: armv5te/OP_GOTO_32.S */ 1161 /* 1162 * Unconditional branch, 32-bit offset. 1163 * 1164 * The branch distance is a signed code-unit offset, which we need to 1165 * double to get a byte offset. 1166 * 1167 * Unlike most opcodes, this one is allowed to branch to itself, so 1168 * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1169 * instruction doesn't affect the V flag, so we need to clear it 1170 * explicitly. 1171 */ 1172 /* goto/32 +AAAAAAAA */ 1173 FETCH(r0, 1) @ r0<- aaaa (lo) 1174 FETCH(r1, 2) @ r1<- AAAA (hi) 1175 cmp ip, ip @ (clear V flag during stall) 1176 orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1177 mov r9, r0, asl #1 @ r9<- byte offset 1178 ble common_backwardBranch @ backward branch, do periodic checks 1179#if defined(WITH_JIT) 1180 GET_JIT_PROF_TABLE(r0) 1181 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1182 cmp r0,#0 1183 bne common_updateProfile 1184 GET_INST_OPCODE(ip) @ extract opcode from rINST 1185 GOTO_OPCODE(ip) @ jump to next instruction 1186#else 1187 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1188 GET_INST_OPCODE(ip) @ extract opcode from rINST 1189 GOTO_OPCODE(ip) @ jump to next instruction 1190#endif 1191 1192/* ------------------------------ */ 1193 .balign 64 1194.L_OP_PACKED_SWITCH: /* 0x2b */ 1195/* File: armv5te/OP_PACKED_SWITCH.S */ 1196 /* 1197 * Handle a packed-switch or sparse-switch instruction. In both cases 1198 * we decode it and hand it off to a helper function. 1199 * 1200 * We don't really expect backward branches in a switch statement, but 1201 * they're perfectly legal, so we check for them here. 1202 * 1203 * for: packed-switch, sparse-switch 1204 */ 1205 /* op vAA, +BBBB */ 1206 FETCH(r0, 1) @ r0<- bbbb (lo) 1207 FETCH(r1, 2) @ r1<- BBBB (hi) 1208 mov r3, rINST, lsr #8 @ r3<- AA 1209 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1210 GET_VREG(r1, r3) @ r1<- vAA 1211 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1212 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1213 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1214 bmi common_backwardBranch @ backward branch, do periodic checks 1215 beq common_backwardBranch @ (want to use BLE but V is unknown) 1216#if defined(WITH_JIT) 1217 GET_JIT_PROF_TABLE(r0) 1218 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1219 cmp r0,#0 1220 bne common_updateProfile 1221 GET_INST_OPCODE(ip) @ extract opcode from rINST 1222 GOTO_OPCODE(ip) @ jump to next instruction 1223#else 1224 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1225 GET_INST_OPCODE(ip) @ extract opcode from rINST 1226 GOTO_OPCODE(ip) @ jump to next instruction 1227#endif 1228 1229/* ------------------------------ */ 1230 .balign 64 1231.L_OP_SPARSE_SWITCH: /* 0x2c */ 1232/* File: armv5te/OP_SPARSE_SWITCH.S */ 1233/* File: armv5te/OP_PACKED_SWITCH.S */ 1234 /* 1235 * Handle a packed-switch or sparse-switch instruction. In both cases 1236 * we decode it and hand it off to a helper function. 1237 * 1238 * We don't really expect backward branches in a switch statement, but 1239 * they're perfectly legal, so we check for them here. 1240 * 1241 * for: packed-switch, sparse-switch 1242 */ 1243 /* op vAA, +BBBB */ 1244 FETCH(r0, 1) @ r0<- bbbb (lo) 1245 FETCH(r1, 2) @ r1<- BBBB (hi) 1246 mov r3, rINST, lsr #8 @ r3<- AA 1247 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1248 GET_VREG(r1, r3) @ r1<- vAA 1249 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1250 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1251 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1252 bmi common_backwardBranch @ backward branch, do periodic checks 1253 beq common_backwardBranch @ (want to use BLE but V is unknown) 1254#if defined(WITH_JIT) 1255 GET_JIT_PROF_TABLE(r0) 1256 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1257 cmp r0,#0 1258 bne common_updateProfile 1259 GET_INST_OPCODE(ip) @ extract opcode from rINST 1260 GOTO_OPCODE(ip) @ jump to next instruction 1261#else 1262 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1263 GET_INST_OPCODE(ip) @ extract opcode from rINST 1264 GOTO_OPCODE(ip) @ jump to next instruction 1265#endif 1266 1267 1268/* ------------------------------ */ 1269 .balign 64 1270.L_OP_CMPL_FLOAT: /* 0x2d */ 1271/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1272 /* 1273 * Compare two floating-point values. Puts 0, 1, or -1 into the 1274 * destination register based on the results of the comparison. 1275 * 1276 * int compare(x, y) { 1277 * if (x == y) { 1278 * return 0; 1279 * } else if (x > y) { 1280 * return 1; 1281 * } else if (x < y) { 1282 * return -1; 1283 * } else { 1284 * return -1; 1285 * } 1286 * } 1287 */ 1288 /* op vAA, vBB, vCC */ 1289 FETCH(r0, 1) @ r0<- CCBB 1290 mov r9, rINST, lsr #8 @ r9<- AA 1291 and r2, r0, #255 @ r2<- BB 1292 mov r3, r0, lsr #8 @ r3<- CC 1293 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1294 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1295 flds s0, [r2] @ s0<- vBB 1296 flds s1, [r3] @ s1<- vCC 1297 fcmpes s0, s1 @ compare (vBB, vCC) 1298 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1299 mvn r0, #0 @ r0<- -1 (default) 1300 GET_INST_OPCODE(ip) @ extract opcode from rINST 1301 fmstat @ export status flags 1302 movgt r0, #1 @ (greater than) r1<- 1 1303 moveq r0, #0 @ (equal) r1<- 0 1304 b .LOP_CMPL_FLOAT_finish @ argh 1305 1306 1307/* ------------------------------ */ 1308 .balign 64 1309.L_OP_CMPG_FLOAT: /* 0x2e */ 1310/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1311 /* 1312 * Compare two floating-point values. Puts 0, 1, or -1 into the 1313 * destination register based on the results of the comparison. 1314 * 1315 * int compare(x, y) { 1316 * if (x == y) { 1317 * return 0; 1318 * } else if (x < y) { 1319 * return -1; 1320 * } else if (x > y) { 1321 * return 1; 1322 * } else { 1323 * return 1; 1324 * } 1325 * } 1326 */ 1327 /* op vAA, vBB, vCC */ 1328 FETCH(r0, 1) @ r0<- CCBB 1329 mov r9, rINST, lsr #8 @ r9<- AA 1330 and r2, r0, #255 @ r2<- BB 1331 mov r3, r0, lsr #8 @ r3<- CC 1332 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1333 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1334 flds s0, [r2] @ s0<- vBB 1335 flds s1, [r3] @ s1<- vCC 1336 fcmpes s0, s1 @ compare (vBB, vCC) 1337 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1338 mov r0, #1 @ r0<- 1 (default) 1339 GET_INST_OPCODE(ip) @ extract opcode from rINST 1340 fmstat @ export status flags 1341 mvnmi r0, #0 @ (less than) r1<- -1 1342 moveq r0, #0 @ (equal) r1<- 0 1343 b .LOP_CMPG_FLOAT_finish @ argh 1344 1345 1346/* ------------------------------ */ 1347 .balign 64 1348.L_OP_CMPL_DOUBLE: /* 0x2f */ 1349/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1350 /* 1351 * Compare two floating-point values. Puts 0, 1, or -1 into the 1352 * destination register based on the results of the comparison. 1353 * 1354 * int compare(x, y) { 1355 * if (x == y) { 1356 * return 0; 1357 * } else if (x > y) { 1358 * return 1; 1359 * } else if (x < y) { 1360 * return -1; 1361 * } else { 1362 * return -1; 1363 * } 1364 * } 1365 */ 1366 /* op vAA, vBB, vCC */ 1367 FETCH(r0, 1) @ r0<- CCBB 1368 mov r9, rINST, lsr #8 @ r9<- AA 1369 and r2, r0, #255 @ r2<- BB 1370 mov r3, r0, lsr #8 @ r3<- CC 1371 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1372 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1373 fldd d0, [r2] @ d0<- vBB 1374 fldd d1, [r3] @ d1<- vCC 1375 fcmped d0, d1 @ compare (vBB, vCC) 1376 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1377 mvn r0, #0 @ r0<- -1 (default) 1378 GET_INST_OPCODE(ip) @ extract opcode from rINST 1379 fmstat @ export status flags 1380 movgt r0, #1 @ (greater than) r1<- 1 1381 moveq r0, #0 @ (equal) r1<- 0 1382 b .LOP_CMPL_DOUBLE_finish @ argh 1383 1384 1385/* ------------------------------ */ 1386 .balign 64 1387.L_OP_CMPG_DOUBLE: /* 0x30 */ 1388/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1389 /* 1390 * Compare two floating-point values. Puts 0, 1, or -1 into the 1391 * destination register based on the results of the comparison. 1392 * 1393 * int compare(x, y) { 1394 * if (x == y) { 1395 * return 0; 1396 * } else if (x < y) { 1397 * return -1; 1398 * } else if (x > y) { 1399 * return 1; 1400 * } else { 1401 * return 1; 1402 * } 1403 * } 1404 */ 1405 /* op vAA, vBB, vCC */ 1406 FETCH(r0, 1) @ r0<- CCBB 1407 mov r9, rINST, lsr #8 @ r9<- AA 1408 and r2, r0, #255 @ r2<- BB 1409 mov r3, r0, lsr #8 @ r3<- CC 1410 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1411 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1412 fldd d0, [r2] @ d0<- vBB 1413 fldd d1, [r3] @ d1<- vCC 1414 fcmped d0, d1 @ compare (vBB, vCC) 1415 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1416 mov r0, #1 @ r0<- 1 (default) 1417 GET_INST_OPCODE(ip) @ extract opcode from rINST 1418 fmstat @ export status flags 1419 mvnmi r0, #0 @ (less than) r1<- -1 1420 moveq r0, #0 @ (equal) r1<- 0 1421 b .LOP_CMPG_DOUBLE_finish @ argh 1422 1423 1424/* ------------------------------ */ 1425 .balign 64 1426.L_OP_CMP_LONG: /* 0x31 */ 1427/* File: armv5te/OP_CMP_LONG.S */ 1428 /* 1429 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1430 * register based on the results of the comparison. 1431 * 1432 * We load the full values with LDM, but in practice many values could 1433 * be resolved by only looking at the high word. This could be made 1434 * faster or slower by splitting the LDM into a pair of LDRs. 1435 * 1436 * If we just wanted to set condition flags, we could do this: 1437 * subs ip, r0, r2 1438 * sbcs ip, r1, r3 1439 * subeqs ip, r0, r2 1440 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1441 * integer value, which we can do with 2 conditional mov/mvn instructions 1442 * (set 1, set -1; if they're equal we already have 0 in ip), giving 1443 * us a constant 5-cycle path plus a branch at the end to the 1444 * instruction epilogue code. The multi-compare approach below needs 1445 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1446 * in the worst case (the 64-bit values are equal). 1447 */ 1448 /* cmp-long vAA, vBB, vCC */ 1449 FETCH(r0, 1) @ r0<- CCBB 1450 mov r9, rINST, lsr #8 @ r9<- AA 1451 and r2, r0, #255 @ r2<- BB 1452 mov r3, r0, lsr #8 @ r3<- CC 1453 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1454 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1455 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1456 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1457 cmp r1, r3 @ compare (vBB+1, vCC+1) 1458 blt .LOP_CMP_LONG_less @ signed compare on high part 1459 bgt .LOP_CMP_LONG_greater 1460 subs r1, r0, r2 @ r1<- r0 - r2 1461 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1462 bne .LOP_CMP_LONG_less 1463 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1464 1465/* ------------------------------ */ 1466 .balign 64 1467.L_OP_IF_EQ: /* 0x32 */ 1468/* File: armv5te/OP_IF_EQ.S */ 1469/* File: armv5te/bincmp.S */ 1470 /* 1471 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1472 * fragment that specifies the *reverse* comparison to perform, e.g. 1473 * for "if-le" you would use "gt". 1474 * 1475 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1476 */ 1477 /* if-cmp vA, vB, +CCCC */ 1478 mov r0, rINST, lsr #8 @ r0<- A+ 1479 mov r1, rINST, lsr #12 @ r1<- B 1480 and r0, r0, #15 1481 GET_VREG(r3, r1) @ r3<- vB 1482 GET_VREG(r2, r0) @ r2<- vA 1483 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1484 cmp r2, r3 @ compare (vA, vB) 1485 bne 1f @ branch to 1 if comparison failed 1486 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1487 movs r9, r9, asl #1 @ convert to bytes, check sign 1488 bmi common_backwardBranch @ yes, do periodic checks 14891: 1490#if defined(WITH_JIT) 1491 GET_JIT_PROF_TABLE(r0) 1492 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1493 b common_testUpdateProfile 1494#else 1495 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1496 GET_INST_OPCODE(ip) @ extract opcode from rINST 1497 GOTO_OPCODE(ip) @ jump to next instruction 1498#endif 1499 1500 1501/* ------------------------------ */ 1502 .balign 64 1503.L_OP_IF_NE: /* 0x33 */ 1504/* File: armv5te/OP_IF_NE.S */ 1505/* File: armv5te/bincmp.S */ 1506 /* 1507 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1508 * fragment that specifies the *reverse* comparison to perform, e.g. 1509 * for "if-le" you would use "gt". 1510 * 1511 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1512 */ 1513 /* if-cmp vA, vB, +CCCC */ 1514 mov r0, rINST, lsr #8 @ r0<- A+ 1515 mov r1, rINST, lsr #12 @ r1<- B 1516 and r0, r0, #15 1517 GET_VREG(r3, r1) @ r3<- vB 1518 GET_VREG(r2, r0) @ r2<- vA 1519 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1520 cmp r2, r3 @ compare (vA, vB) 1521 beq 1f @ branch to 1 if comparison failed 1522 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1523 movs r9, r9, asl #1 @ convert to bytes, check sign 1524 bmi common_backwardBranch @ yes, do periodic checks 15251: 1526#if defined(WITH_JIT) 1527 GET_JIT_PROF_TABLE(r0) 1528 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1529 b common_testUpdateProfile 1530#else 1531 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1532 GET_INST_OPCODE(ip) @ extract opcode from rINST 1533 GOTO_OPCODE(ip) @ jump to next instruction 1534#endif 1535 1536 1537/* ------------------------------ */ 1538 .balign 64 1539.L_OP_IF_LT: /* 0x34 */ 1540/* File: armv5te/OP_IF_LT.S */ 1541/* File: armv5te/bincmp.S */ 1542 /* 1543 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1544 * fragment that specifies the *reverse* comparison to perform, e.g. 1545 * for "if-le" you would use "gt". 1546 * 1547 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1548 */ 1549 /* if-cmp vA, vB, +CCCC */ 1550 mov r0, rINST, lsr #8 @ r0<- A+ 1551 mov r1, rINST, lsr #12 @ r1<- B 1552 and r0, r0, #15 1553 GET_VREG(r3, r1) @ r3<- vB 1554 GET_VREG(r2, r0) @ r2<- vA 1555 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1556 cmp r2, r3 @ compare (vA, vB) 1557 bge 1f @ branch to 1 if comparison failed 1558 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1559 movs r9, r9, asl #1 @ convert to bytes, check sign 1560 bmi common_backwardBranch @ yes, do periodic checks 15611: 1562#if defined(WITH_JIT) 1563 GET_JIT_PROF_TABLE(r0) 1564 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1565 b common_testUpdateProfile 1566#else 1567 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1568 GET_INST_OPCODE(ip) @ extract opcode from rINST 1569 GOTO_OPCODE(ip) @ jump to next instruction 1570#endif 1571 1572 1573/* ------------------------------ */ 1574 .balign 64 1575.L_OP_IF_GE: /* 0x35 */ 1576/* File: armv5te/OP_IF_GE.S */ 1577/* File: armv5te/bincmp.S */ 1578 /* 1579 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1580 * fragment that specifies the *reverse* comparison to perform, e.g. 1581 * for "if-le" you would use "gt". 1582 * 1583 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1584 */ 1585 /* if-cmp vA, vB, +CCCC */ 1586 mov r0, rINST, lsr #8 @ r0<- A+ 1587 mov r1, rINST, lsr #12 @ r1<- B 1588 and r0, r0, #15 1589 GET_VREG(r3, r1) @ r3<- vB 1590 GET_VREG(r2, r0) @ r2<- vA 1591 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1592 cmp r2, r3 @ compare (vA, vB) 1593 blt 1f @ branch to 1 if comparison failed 1594 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1595 movs r9, r9, asl #1 @ convert to bytes, check sign 1596 bmi common_backwardBranch @ yes, do periodic checks 15971: 1598#if defined(WITH_JIT) 1599 GET_JIT_PROF_TABLE(r0) 1600 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1601 b common_testUpdateProfile 1602#else 1603 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1604 GET_INST_OPCODE(ip) @ extract opcode from rINST 1605 GOTO_OPCODE(ip) @ jump to next instruction 1606#endif 1607 1608 1609/* ------------------------------ */ 1610 .balign 64 1611.L_OP_IF_GT: /* 0x36 */ 1612/* File: armv5te/OP_IF_GT.S */ 1613/* File: armv5te/bincmp.S */ 1614 /* 1615 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1616 * fragment that specifies the *reverse* comparison to perform, e.g. 1617 * for "if-le" you would use "gt". 1618 * 1619 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1620 */ 1621 /* if-cmp vA, vB, +CCCC */ 1622 mov r0, rINST, lsr #8 @ r0<- A+ 1623 mov r1, rINST, lsr #12 @ r1<- B 1624 and r0, r0, #15 1625 GET_VREG(r3, r1) @ r3<- vB 1626 GET_VREG(r2, r0) @ r2<- vA 1627 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1628 cmp r2, r3 @ compare (vA, vB) 1629 ble 1f @ branch to 1 if comparison failed 1630 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1631 movs r9, r9, asl #1 @ convert to bytes, check sign 1632 bmi common_backwardBranch @ yes, do periodic checks 16331: 1634#if defined(WITH_JIT) 1635 GET_JIT_PROF_TABLE(r0) 1636 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1637 b common_testUpdateProfile 1638#else 1639 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1640 GET_INST_OPCODE(ip) @ extract opcode from rINST 1641 GOTO_OPCODE(ip) @ jump to next instruction 1642#endif 1643 1644 1645/* ------------------------------ */ 1646 .balign 64 1647.L_OP_IF_LE: /* 0x37 */ 1648/* File: armv5te/OP_IF_LE.S */ 1649/* File: armv5te/bincmp.S */ 1650 /* 1651 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1652 * fragment that specifies the *reverse* comparison to perform, e.g. 1653 * for "if-le" you would use "gt". 1654 * 1655 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1656 */ 1657 /* if-cmp vA, vB, +CCCC */ 1658 mov r0, rINST, lsr #8 @ r0<- A+ 1659 mov r1, rINST, lsr #12 @ r1<- B 1660 and r0, r0, #15 1661 GET_VREG(r3, r1) @ r3<- vB 1662 GET_VREG(r2, r0) @ r2<- vA 1663 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1664 cmp r2, r3 @ compare (vA, vB) 1665 bgt 1f @ branch to 1 if comparison failed 1666 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1667 movs r9, r9, asl #1 @ convert to bytes, check sign 1668 bmi common_backwardBranch @ yes, do periodic checks 16691: 1670#if defined(WITH_JIT) 1671 GET_JIT_PROF_TABLE(r0) 1672 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1673 b common_testUpdateProfile 1674#else 1675 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1676 GET_INST_OPCODE(ip) @ extract opcode from rINST 1677 GOTO_OPCODE(ip) @ jump to next instruction 1678#endif 1679 1680 1681/* ------------------------------ */ 1682 .balign 64 1683.L_OP_IF_EQZ: /* 0x38 */ 1684/* File: armv5te/OP_IF_EQZ.S */ 1685/* File: armv5te/zcmp.S */ 1686 /* 1687 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1688 * fragment that specifies the *reverse* comparison to perform, e.g. 1689 * for "if-le" you would use "gt". 1690 * 1691 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1692 */ 1693 /* if-cmp vAA, +BBBB */ 1694 mov r0, rINST, lsr #8 @ r0<- AA 1695 GET_VREG(r2, r0) @ r2<- vAA 1696 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1697 cmp r2, #0 @ compare (vA, 0) 1698 bne 1f @ branch to 1 if comparison failed 1699 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1700 movs r9, r9, asl #1 @ convert to bytes, check sign 1701 bmi common_backwardBranch @ backward branch, do periodic checks 17021: 1703#if defined(WITH_JIT) 1704 GET_JIT_PROF_TABLE(r0) 1705 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1706 cmp r0,#0 1707 bne common_updateProfile 1708 GET_INST_OPCODE(ip) @ extract opcode from rINST 1709 GOTO_OPCODE(ip) @ jump to next instruction 1710#else 1711 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1712 GET_INST_OPCODE(ip) @ extract opcode from rINST 1713 GOTO_OPCODE(ip) @ jump to next instruction 1714#endif 1715 1716 1717/* ------------------------------ */ 1718 .balign 64 1719.L_OP_IF_NEZ: /* 0x39 */ 1720/* File: armv5te/OP_IF_NEZ.S */ 1721/* File: armv5te/zcmp.S */ 1722 /* 1723 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1724 * fragment that specifies the *reverse* comparison to perform, e.g. 1725 * for "if-le" you would use "gt". 1726 * 1727 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1728 */ 1729 /* if-cmp vAA, +BBBB */ 1730 mov r0, rINST, lsr #8 @ r0<- AA 1731 GET_VREG(r2, r0) @ r2<- vAA 1732 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1733 cmp r2, #0 @ compare (vA, 0) 1734 beq 1f @ branch to 1 if comparison failed 1735 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1736 movs r9, r9, asl #1 @ convert to bytes, check sign 1737 bmi common_backwardBranch @ backward branch, do periodic checks 17381: 1739#if defined(WITH_JIT) 1740 GET_JIT_PROF_TABLE(r0) 1741 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1742 cmp r0,#0 1743 bne common_updateProfile 1744 GET_INST_OPCODE(ip) @ extract opcode from rINST 1745 GOTO_OPCODE(ip) @ jump to next instruction 1746#else 1747 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1748 GET_INST_OPCODE(ip) @ extract opcode from rINST 1749 GOTO_OPCODE(ip) @ jump to next instruction 1750#endif 1751 1752 1753/* ------------------------------ */ 1754 .balign 64 1755.L_OP_IF_LTZ: /* 0x3a */ 1756/* File: armv5te/OP_IF_LTZ.S */ 1757/* File: armv5te/zcmp.S */ 1758 /* 1759 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1760 * fragment that specifies the *reverse* comparison to perform, e.g. 1761 * for "if-le" you would use "gt". 1762 * 1763 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1764 */ 1765 /* if-cmp vAA, +BBBB */ 1766 mov r0, rINST, lsr #8 @ r0<- AA 1767 GET_VREG(r2, r0) @ r2<- vAA 1768 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1769 cmp r2, #0 @ compare (vA, 0) 1770 bge 1f @ branch to 1 if comparison failed 1771 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1772 movs r9, r9, asl #1 @ convert to bytes, check sign 1773 bmi common_backwardBranch @ backward branch, do periodic checks 17741: 1775#if defined(WITH_JIT) 1776 GET_JIT_PROF_TABLE(r0) 1777 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1778 cmp r0,#0 1779 bne common_updateProfile 1780 GET_INST_OPCODE(ip) @ extract opcode from rINST 1781 GOTO_OPCODE(ip) @ jump to next instruction 1782#else 1783 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1784 GET_INST_OPCODE(ip) @ extract opcode from rINST 1785 GOTO_OPCODE(ip) @ jump to next instruction 1786#endif 1787 1788 1789/* ------------------------------ */ 1790 .balign 64 1791.L_OP_IF_GEZ: /* 0x3b */ 1792/* File: armv5te/OP_IF_GEZ.S */ 1793/* File: armv5te/zcmp.S */ 1794 /* 1795 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1796 * fragment that specifies the *reverse* comparison to perform, e.g. 1797 * for "if-le" you would use "gt". 1798 * 1799 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1800 */ 1801 /* if-cmp vAA, +BBBB */ 1802 mov r0, rINST, lsr #8 @ r0<- AA 1803 GET_VREG(r2, r0) @ r2<- vAA 1804 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1805 cmp r2, #0 @ compare (vA, 0) 1806 blt 1f @ branch to 1 if comparison failed 1807 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1808 movs r9, r9, asl #1 @ convert to bytes, check sign 1809 bmi common_backwardBranch @ backward branch, do periodic checks 18101: 1811#if defined(WITH_JIT) 1812 GET_JIT_PROF_TABLE(r0) 1813 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1814 cmp r0,#0 1815 bne common_updateProfile 1816 GET_INST_OPCODE(ip) @ extract opcode from rINST 1817 GOTO_OPCODE(ip) @ jump to next instruction 1818#else 1819 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1820 GET_INST_OPCODE(ip) @ extract opcode from rINST 1821 GOTO_OPCODE(ip) @ jump to next instruction 1822#endif 1823 1824 1825/* ------------------------------ */ 1826 .balign 64 1827.L_OP_IF_GTZ: /* 0x3c */ 1828/* File: armv5te/OP_IF_GTZ.S */ 1829/* File: armv5te/zcmp.S */ 1830 /* 1831 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1832 * fragment that specifies the *reverse* comparison to perform, e.g. 1833 * for "if-le" you would use "gt". 1834 * 1835 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1836 */ 1837 /* if-cmp vAA, +BBBB */ 1838 mov r0, rINST, lsr #8 @ r0<- AA 1839 GET_VREG(r2, r0) @ r2<- vAA 1840 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1841 cmp r2, #0 @ compare (vA, 0) 1842 ble 1f @ branch to 1 if comparison failed 1843 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1844 movs r9, r9, asl #1 @ convert to bytes, check sign 1845 bmi common_backwardBranch @ backward branch, do periodic checks 18461: 1847#if defined(WITH_JIT) 1848 GET_JIT_PROF_TABLE(r0) 1849 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1850 cmp r0,#0 1851 bne common_updateProfile 1852 GET_INST_OPCODE(ip) @ extract opcode from rINST 1853 GOTO_OPCODE(ip) @ jump to next instruction 1854#else 1855 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1856 GET_INST_OPCODE(ip) @ extract opcode from rINST 1857 GOTO_OPCODE(ip) @ jump to next instruction 1858#endif 1859 1860 1861/* ------------------------------ */ 1862 .balign 64 1863.L_OP_IF_LEZ: /* 0x3d */ 1864/* File: armv5te/OP_IF_LEZ.S */ 1865/* File: armv5te/zcmp.S */ 1866 /* 1867 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1868 * fragment that specifies the *reverse* comparison to perform, e.g. 1869 * for "if-le" you would use "gt". 1870 * 1871 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1872 */ 1873 /* if-cmp vAA, +BBBB */ 1874 mov r0, rINST, lsr #8 @ r0<- AA 1875 GET_VREG(r2, r0) @ r2<- vAA 1876 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1877 cmp r2, #0 @ compare (vA, 0) 1878 bgt 1f @ branch to 1 if comparison failed 1879 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1880 movs r9, r9, asl #1 @ convert to bytes, check sign 1881 bmi common_backwardBranch @ backward branch, do periodic checks 18821: 1883#if defined(WITH_JIT) 1884 GET_JIT_PROF_TABLE(r0) 1885 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1886 cmp r0,#0 1887 bne common_updateProfile 1888 GET_INST_OPCODE(ip) @ extract opcode from rINST 1889 GOTO_OPCODE(ip) @ jump to next instruction 1890#else 1891 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1892 GET_INST_OPCODE(ip) @ extract opcode from rINST 1893 GOTO_OPCODE(ip) @ jump to next instruction 1894#endif 1895 1896 1897/* ------------------------------ */ 1898 .balign 64 1899.L_OP_UNUSED_3E: /* 0x3e */ 1900/* File: armv5te/OP_UNUSED_3E.S */ 1901/* File: armv5te/unused.S */ 1902 bl common_abort 1903 1904 1905/* ------------------------------ */ 1906 .balign 64 1907.L_OP_UNUSED_3F: /* 0x3f */ 1908/* File: armv5te/OP_UNUSED_3F.S */ 1909/* File: armv5te/unused.S */ 1910 bl common_abort 1911 1912 1913/* ------------------------------ */ 1914 .balign 64 1915.L_OP_UNUSED_40: /* 0x40 */ 1916/* File: armv5te/OP_UNUSED_40.S */ 1917/* File: armv5te/unused.S */ 1918 bl common_abort 1919 1920 1921/* ------------------------------ */ 1922 .balign 64 1923.L_OP_UNUSED_41: /* 0x41 */ 1924/* File: armv5te/OP_UNUSED_41.S */ 1925/* File: armv5te/unused.S */ 1926 bl common_abort 1927 1928 1929/* ------------------------------ */ 1930 .balign 64 1931.L_OP_UNUSED_42: /* 0x42 */ 1932/* File: armv5te/OP_UNUSED_42.S */ 1933/* File: armv5te/unused.S */ 1934 bl common_abort 1935 1936 1937/* ------------------------------ */ 1938 .balign 64 1939.L_OP_UNUSED_43: /* 0x43 */ 1940/* File: armv5te/OP_UNUSED_43.S */ 1941/* File: armv5te/unused.S */ 1942 bl common_abort 1943 1944 1945/* ------------------------------ */ 1946 .balign 64 1947.L_OP_AGET: /* 0x44 */ 1948/* File: armv5te/OP_AGET.S */ 1949 /* 1950 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1951 * 1952 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1953 * instructions. We use a pair of FETCH_Bs instead. 1954 * 1955 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1956 */ 1957 /* op vAA, vBB, vCC */ 1958 FETCH_B(r2, 1, 0) @ r2<- BB 1959 mov r9, rINST, lsr #8 @ r9<- AA 1960 FETCH_B(r3, 1, 1) @ r3<- CC 1961 GET_VREG(r0, r2) @ r0<- vBB (array object) 1962 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1963 cmp r0, #0 @ null array object? 1964 beq common_errNullObject @ yes, bail 1965 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1966 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1967 cmp r1, r3 @ compare unsigned index, length 1968 bcs common_errArrayIndex @ index >= length, bail 1969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1970 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 1971 GET_INST_OPCODE(ip) @ extract opcode from rINST 1972 SET_VREG(r2, r9) @ vAA<- r2 1973 GOTO_OPCODE(ip) @ jump to next instruction 1974 1975/* ------------------------------ */ 1976 .balign 64 1977.L_OP_AGET_WIDE: /* 0x45 */ 1978/* File: armv5te/OP_AGET_WIDE.S */ 1979 /* 1980 * Array get, 64 bits. vAA <- vBB[vCC]. 1981 * 1982 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 1983 */ 1984 /* aget-wide vAA, vBB, vCC */ 1985 FETCH(r0, 1) @ r0<- CCBB 1986 mov r9, rINST, lsr #8 @ r9<- AA 1987 and r2, r0, #255 @ r2<- BB 1988 mov r3, r0, lsr #8 @ r3<- CC 1989 GET_VREG(r0, r2) @ r0<- vBB (array object) 1990 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1991 cmp r0, #0 @ null array object? 1992 beq common_errNullObject @ yes, bail 1993 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1994 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 1995 cmp r1, r3 @ compare unsigned index, length 1996 bcc .LOP_AGET_WIDE_finish @ okay, continue below 1997 b common_errArrayIndex @ index >= length, bail 1998 @ May want to swap the order of these two branches depending on how the 1999 @ branch prediction (if any) handles conditional forward branches vs. 2000 @ unconditional forward branches. 2001 2002/* ------------------------------ */ 2003 .balign 64 2004.L_OP_AGET_OBJECT: /* 0x46 */ 2005/* File: armv5te/OP_AGET_OBJECT.S */ 2006/* File: armv5te/OP_AGET.S */ 2007 /* 2008 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2009 * 2010 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2011 * instructions. We use a pair of FETCH_Bs instead. 2012 * 2013 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2014 */ 2015 /* op vAA, vBB, vCC */ 2016 FETCH_B(r2, 1, 0) @ r2<- BB 2017 mov r9, rINST, lsr #8 @ r9<- AA 2018 FETCH_B(r3, 1, 1) @ r3<- CC 2019 GET_VREG(r0, r2) @ r0<- vBB (array object) 2020 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2021 cmp r0, #0 @ null array object? 2022 beq common_errNullObject @ yes, bail 2023 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2024 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2025 cmp r1, r3 @ compare unsigned index, length 2026 bcs common_errArrayIndex @ index >= length, bail 2027 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2028 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2029 GET_INST_OPCODE(ip) @ extract opcode from rINST 2030 SET_VREG(r2, r9) @ vAA<- r2 2031 GOTO_OPCODE(ip) @ jump to next instruction 2032 2033 2034/* ------------------------------ */ 2035 .balign 64 2036.L_OP_AGET_BOOLEAN: /* 0x47 */ 2037/* File: armv5te/OP_AGET_BOOLEAN.S */ 2038/* File: armv5te/OP_AGET.S */ 2039 /* 2040 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2041 * 2042 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2043 * instructions. We use a pair of FETCH_Bs instead. 2044 * 2045 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2046 */ 2047 /* op vAA, vBB, vCC */ 2048 FETCH_B(r2, 1, 0) @ r2<- BB 2049 mov r9, rINST, lsr #8 @ r9<- AA 2050 FETCH_B(r3, 1, 1) @ r3<- CC 2051 GET_VREG(r0, r2) @ r0<- vBB (array object) 2052 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2053 cmp r0, #0 @ null array object? 2054 beq common_errNullObject @ yes, bail 2055 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2056 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2057 cmp r1, r3 @ compare unsigned index, length 2058 bcs common_errArrayIndex @ index >= length, bail 2059 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2060 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2061 GET_INST_OPCODE(ip) @ extract opcode from rINST 2062 SET_VREG(r2, r9) @ vAA<- r2 2063 GOTO_OPCODE(ip) @ jump to next instruction 2064 2065 2066/* ------------------------------ */ 2067 .balign 64 2068.L_OP_AGET_BYTE: /* 0x48 */ 2069/* File: armv5te/OP_AGET_BYTE.S */ 2070/* File: armv5te/OP_AGET.S */ 2071 /* 2072 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2073 * 2074 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2075 * instructions. We use a pair of FETCH_Bs instead. 2076 * 2077 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2078 */ 2079 /* op vAA, vBB, vCC */ 2080 FETCH_B(r2, 1, 0) @ r2<- BB 2081 mov r9, rINST, lsr #8 @ r9<- AA 2082 FETCH_B(r3, 1, 1) @ r3<- CC 2083 GET_VREG(r0, r2) @ r0<- vBB (array object) 2084 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2085 cmp r0, #0 @ null array object? 2086 beq common_errNullObject @ yes, bail 2087 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2088 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2089 cmp r1, r3 @ compare unsigned index, length 2090 bcs common_errArrayIndex @ index >= length, bail 2091 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2092 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2093 GET_INST_OPCODE(ip) @ extract opcode from rINST 2094 SET_VREG(r2, r9) @ vAA<- r2 2095 GOTO_OPCODE(ip) @ jump to next instruction 2096 2097 2098/* ------------------------------ */ 2099 .balign 64 2100.L_OP_AGET_CHAR: /* 0x49 */ 2101/* File: armv5te/OP_AGET_CHAR.S */ 2102/* File: armv5te/OP_AGET.S */ 2103 /* 2104 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2105 * 2106 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2107 * instructions. We use a pair of FETCH_Bs instead. 2108 * 2109 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2110 */ 2111 /* op vAA, vBB, vCC */ 2112 FETCH_B(r2, 1, 0) @ r2<- BB 2113 mov r9, rINST, lsr #8 @ r9<- AA 2114 FETCH_B(r3, 1, 1) @ r3<- CC 2115 GET_VREG(r0, r2) @ r0<- vBB (array object) 2116 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2117 cmp r0, #0 @ null array object? 2118 beq common_errNullObject @ yes, bail 2119 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2120 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2121 cmp r1, r3 @ compare unsigned index, length 2122 bcs common_errArrayIndex @ index >= length, bail 2123 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2124 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2125 GET_INST_OPCODE(ip) @ extract opcode from rINST 2126 SET_VREG(r2, r9) @ vAA<- r2 2127 GOTO_OPCODE(ip) @ jump to next instruction 2128 2129 2130/* ------------------------------ */ 2131 .balign 64 2132.L_OP_AGET_SHORT: /* 0x4a */ 2133/* File: armv5te/OP_AGET_SHORT.S */ 2134/* File: armv5te/OP_AGET.S */ 2135 /* 2136 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2137 * 2138 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2139 * instructions. We use a pair of FETCH_Bs instead. 2140 * 2141 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2142 */ 2143 /* op vAA, vBB, vCC */ 2144 FETCH_B(r2, 1, 0) @ r2<- BB 2145 mov r9, rINST, lsr #8 @ r9<- AA 2146 FETCH_B(r3, 1, 1) @ r3<- CC 2147 GET_VREG(r0, r2) @ r0<- vBB (array object) 2148 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2149 cmp r0, #0 @ null array object? 2150 beq common_errNullObject @ yes, bail 2151 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2152 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2153 cmp r1, r3 @ compare unsigned index, length 2154 bcs common_errArrayIndex @ index >= length, bail 2155 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2156 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2157 GET_INST_OPCODE(ip) @ extract opcode from rINST 2158 SET_VREG(r2, r9) @ vAA<- r2 2159 GOTO_OPCODE(ip) @ jump to next instruction 2160 2161 2162/* ------------------------------ */ 2163 .balign 64 2164.L_OP_APUT: /* 0x4b */ 2165/* File: armv5te/OP_APUT.S */ 2166 /* 2167 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2168 * 2169 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2170 * instructions. We use a pair of FETCH_Bs instead. 2171 * 2172 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2173 */ 2174 /* op vAA, vBB, vCC */ 2175 FETCH_B(r2, 1, 0) @ r2<- BB 2176 mov r9, rINST, lsr #8 @ r9<- AA 2177 FETCH_B(r3, 1, 1) @ r3<- CC 2178 GET_VREG(r0, r2) @ r0<- vBB (array object) 2179 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2180 cmp r0, #0 @ null array object? 2181 beq common_errNullObject @ yes, bail 2182 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2183 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2184 cmp r1, r3 @ compare unsigned index, length 2185 bcs common_errArrayIndex @ index >= length, bail 2186 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2187 GET_VREG(r2, r9) @ r2<- vAA 2188 GET_INST_OPCODE(ip) @ extract opcode from rINST 2189 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2190 GOTO_OPCODE(ip) @ jump to next instruction 2191 2192/* ------------------------------ */ 2193 .balign 64 2194.L_OP_APUT_WIDE: /* 0x4c */ 2195/* File: armv5te/OP_APUT_WIDE.S */ 2196 /* 2197 * Array put, 64 bits. vBB[vCC] <- vAA. 2198 * 2199 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2200 */ 2201 /* aput-wide vAA, vBB, vCC */ 2202 FETCH(r0, 1) @ r0<- CCBB 2203 mov r9, rINST, lsr #8 @ r9<- AA 2204 and r2, r0, #255 @ r2<- BB 2205 mov r3, r0, lsr #8 @ r3<- CC 2206 GET_VREG(r0, r2) @ r0<- vBB (array object) 2207 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2208 cmp r0, #0 @ null array object? 2209 beq common_errNullObject @ yes, bail 2210 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2211 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2212 cmp r1, r3 @ compare unsigned index, length 2213 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2214 bcc .LOP_APUT_WIDE_finish @ okay, continue below 2215 b common_errArrayIndex @ index >= length, bail 2216 @ May want to swap the order of these two branches depending on how the 2217 @ branch prediction (if any) handles conditional forward branches vs. 2218 @ unconditional forward branches. 2219 2220/* ------------------------------ */ 2221 .balign 64 2222.L_OP_APUT_OBJECT: /* 0x4d */ 2223/* File: armv5te/OP_APUT_OBJECT.S */ 2224 /* 2225 * Store an object into an array. vBB[vCC] <- vAA. 2226 */ 2227 /* op vAA, vBB, vCC */ 2228 FETCH(r0, 1) @ r0<- CCBB 2229 mov r9, rINST, lsr #8 @ r9<- AA 2230 and r2, r0, #255 @ r2<- BB 2231 mov r3, r0, lsr #8 @ r3<- CC 2232 GET_VREG(rINST, r2) @ rINST<- vBB (array object) 2233 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2234 cmp rINST, #0 @ null array object? 2235 GET_VREG(r9, r9) @ r9<- vAA 2236 beq common_errNullObject @ yes, bail 2237 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length 2238 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width 2239 cmp r1, r3 @ compare unsigned index, length 2240 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2241 b common_errArrayIndex @ index >= length, bail 2242 2243 2244/* ------------------------------ */ 2245 .balign 64 2246.L_OP_APUT_BOOLEAN: /* 0x4e */ 2247/* File: armv5te/OP_APUT_BOOLEAN.S */ 2248/* File: armv5te/OP_APUT.S */ 2249 /* 2250 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2251 * 2252 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2253 * instructions. We use a pair of FETCH_Bs instead. 2254 * 2255 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2256 */ 2257 /* op vAA, vBB, vCC */ 2258 FETCH_B(r2, 1, 0) @ r2<- BB 2259 mov r9, rINST, lsr #8 @ r9<- AA 2260 FETCH_B(r3, 1, 1) @ r3<- CC 2261 GET_VREG(r0, r2) @ r0<- vBB (array object) 2262 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2263 cmp r0, #0 @ null array object? 2264 beq common_errNullObject @ yes, bail 2265 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2266 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2267 cmp r1, r3 @ compare unsigned index, length 2268 bcs common_errArrayIndex @ index >= length, bail 2269 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2270 GET_VREG(r2, r9) @ r2<- vAA 2271 GET_INST_OPCODE(ip) @ extract opcode from rINST 2272 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2273 GOTO_OPCODE(ip) @ jump to next instruction 2274 2275 2276/* ------------------------------ */ 2277 .balign 64 2278.L_OP_APUT_BYTE: /* 0x4f */ 2279/* File: armv5te/OP_APUT_BYTE.S */ 2280/* File: armv5te/OP_APUT.S */ 2281 /* 2282 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2283 * 2284 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2285 * instructions. We use a pair of FETCH_Bs instead. 2286 * 2287 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2288 */ 2289 /* op vAA, vBB, vCC */ 2290 FETCH_B(r2, 1, 0) @ r2<- BB 2291 mov r9, rINST, lsr #8 @ r9<- AA 2292 FETCH_B(r3, 1, 1) @ r3<- CC 2293 GET_VREG(r0, r2) @ r0<- vBB (array object) 2294 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2295 cmp r0, #0 @ null array object? 2296 beq common_errNullObject @ yes, bail 2297 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2298 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2299 cmp r1, r3 @ compare unsigned index, length 2300 bcs common_errArrayIndex @ index >= length, bail 2301 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2302 GET_VREG(r2, r9) @ r2<- vAA 2303 GET_INST_OPCODE(ip) @ extract opcode from rINST 2304 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2305 GOTO_OPCODE(ip) @ jump to next instruction 2306 2307 2308/* ------------------------------ */ 2309 .balign 64 2310.L_OP_APUT_CHAR: /* 0x50 */ 2311/* File: armv5te/OP_APUT_CHAR.S */ 2312/* File: armv5te/OP_APUT.S */ 2313 /* 2314 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2315 * 2316 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2317 * instructions. We use a pair of FETCH_Bs instead. 2318 * 2319 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2320 */ 2321 /* op vAA, vBB, vCC */ 2322 FETCH_B(r2, 1, 0) @ r2<- BB 2323 mov r9, rINST, lsr #8 @ r9<- AA 2324 FETCH_B(r3, 1, 1) @ r3<- CC 2325 GET_VREG(r0, r2) @ r0<- vBB (array object) 2326 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2327 cmp r0, #0 @ null array object? 2328 beq common_errNullObject @ yes, bail 2329 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2330 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2331 cmp r1, r3 @ compare unsigned index, length 2332 bcs common_errArrayIndex @ index >= length, bail 2333 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2334 GET_VREG(r2, r9) @ r2<- vAA 2335 GET_INST_OPCODE(ip) @ extract opcode from rINST 2336 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2337 GOTO_OPCODE(ip) @ jump to next instruction 2338 2339 2340/* ------------------------------ */ 2341 .balign 64 2342.L_OP_APUT_SHORT: /* 0x51 */ 2343/* File: armv5te/OP_APUT_SHORT.S */ 2344/* File: armv5te/OP_APUT.S */ 2345 /* 2346 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2347 * 2348 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2349 * instructions. We use a pair of FETCH_Bs instead. 2350 * 2351 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2352 */ 2353 /* op vAA, vBB, vCC */ 2354 FETCH_B(r2, 1, 0) @ r2<- BB 2355 mov r9, rINST, lsr #8 @ r9<- AA 2356 FETCH_B(r3, 1, 1) @ r3<- CC 2357 GET_VREG(r0, r2) @ r0<- vBB (array object) 2358 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2359 cmp r0, #0 @ null array object? 2360 beq common_errNullObject @ yes, bail 2361 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2362 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2363 cmp r1, r3 @ compare unsigned index, length 2364 bcs common_errArrayIndex @ index >= length, bail 2365 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2366 GET_VREG(r2, r9) @ r2<- vAA 2367 GET_INST_OPCODE(ip) @ extract opcode from rINST 2368 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2369 GOTO_OPCODE(ip) @ jump to next instruction 2370 2371 2372/* ------------------------------ */ 2373 .balign 64 2374.L_OP_IGET: /* 0x52 */ 2375/* File: armv5te/OP_IGET.S */ 2376 /* 2377 * General 32-bit instance field get. 2378 * 2379 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2380 */ 2381 /* op vA, vB, field@CCCC */ 2382 mov r0, rINST, lsr #12 @ r0<- B 2383 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2384 FETCH(r1, 1) @ r1<- field ref CCCC 2385 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2386 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2387 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2388 cmp r0, #0 @ is resolved entry null? 2389 bne .LOP_IGET_finish @ no, already resolved 23908: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2391 EXPORT_PC() @ resolve() could throw 2392 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2393 bl dvmResolveInstField @ r0<- resolved InstField ptr 2394 cmp r0, #0 2395 bne .LOP_IGET_finish 2396 b common_exceptionThrown 2397 2398/* ------------------------------ */ 2399 .balign 64 2400.L_OP_IGET_WIDE: /* 0x53 */ 2401/* File: armv5te/OP_IGET_WIDE.S */ 2402 /* 2403 * Wide 32-bit instance field get. 2404 */ 2405 /* iget-wide vA, vB, field@CCCC */ 2406 mov r0, rINST, lsr #12 @ r0<- B 2407 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2408 FETCH(r1, 1) @ r1<- field ref CCCC 2409 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2410 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2411 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2412 cmp r0, #0 @ is resolved entry null? 2413 bne .LOP_IGET_WIDE_finish @ no, already resolved 24148: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2415 EXPORT_PC() @ resolve() could throw 2416 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2417 bl dvmResolveInstField @ r0<- resolved InstField ptr 2418 cmp r0, #0 2419 bne .LOP_IGET_WIDE_finish 2420 b common_exceptionThrown 2421 2422/* ------------------------------ */ 2423 .balign 64 2424.L_OP_IGET_OBJECT: /* 0x54 */ 2425/* File: armv5te/OP_IGET_OBJECT.S */ 2426/* File: armv5te/OP_IGET.S */ 2427 /* 2428 * General 32-bit instance field get. 2429 * 2430 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2431 */ 2432 /* op vA, vB, field@CCCC */ 2433 mov r0, rINST, lsr #12 @ r0<- B 2434 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2435 FETCH(r1, 1) @ r1<- field ref CCCC 2436 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2437 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2438 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2439 cmp r0, #0 @ is resolved entry null? 2440 bne .LOP_IGET_OBJECT_finish @ no, already resolved 24418: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2442 EXPORT_PC() @ resolve() could throw 2443 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2444 bl dvmResolveInstField @ r0<- resolved InstField ptr 2445 cmp r0, #0 2446 bne .LOP_IGET_OBJECT_finish 2447 b common_exceptionThrown 2448 2449 2450/* ------------------------------ */ 2451 .balign 64 2452.L_OP_IGET_BOOLEAN: /* 0x55 */ 2453/* File: armv5te/OP_IGET_BOOLEAN.S */ 2454@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2455/* File: armv5te/OP_IGET.S */ 2456 /* 2457 * General 32-bit instance field get. 2458 * 2459 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2460 */ 2461 /* op vA, vB, field@CCCC */ 2462 mov r0, rINST, lsr #12 @ r0<- B 2463 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2464 FETCH(r1, 1) @ r1<- field ref CCCC 2465 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2466 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2467 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2468 cmp r0, #0 @ is resolved entry null? 2469 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 24708: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2471 EXPORT_PC() @ resolve() could throw 2472 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2473 bl dvmResolveInstField @ r0<- resolved InstField ptr 2474 cmp r0, #0 2475 bne .LOP_IGET_BOOLEAN_finish 2476 b common_exceptionThrown 2477 2478 2479/* ------------------------------ */ 2480 .balign 64 2481.L_OP_IGET_BYTE: /* 0x56 */ 2482/* File: armv5te/OP_IGET_BYTE.S */ 2483@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2484/* File: armv5te/OP_IGET.S */ 2485 /* 2486 * General 32-bit instance field get. 2487 * 2488 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2489 */ 2490 /* op vA, vB, field@CCCC */ 2491 mov r0, rINST, lsr #12 @ r0<- B 2492 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2493 FETCH(r1, 1) @ r1<- field ref CCCC 2494 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2495 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2496 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2497 cmp r0, #0 @ is resolved entry null? 2498 bne .LOP_IGET_BYTE_finish @ no, already resolved 24998: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2500 EXPORT_PC() @ resolve() could throw 2501 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2502 bl dvmResolveInstField @ r0<- resolved InstField ptr 2503 cmp r0, #0 2504 bne .LOP_IGET_BYTE_finish 2505 b common_exceptionThrown 2506 2507 2508/* ------------------------------ */ 2509 .balign 64 2510.L_OP_IGET_CHAR: /* 0x57 */ 2511/* File: armv5te/OP_IGET_CHAR.S */ 2512@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2513/* File: armv5te/OP_IGET.S */ 2514 /* 2515 * General 32-bit instance field get. 2516 * 2517 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2518 */ 2519 /* op vA, vB, field@CCCC */ 2520 mov r0, rINST, lsr #12 @ r0<- B 2521 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2522 FETCH(r1, 1) @ r1<- field ref CCCC 2523 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2524 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2525 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2526 cmp r0, #0 @ is resolved entry null? 2527 bne .LOP_IGET_CHAR_finish @ no, already resolved 25288: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2529 EXPORT_PC() @ resolve() could throw 2530 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2531 bl dvmResolveInstField @ r0<- resolved InstField ptr 2532 cmp r0, #0 2533 bne .LOP_IGET_CHAR_finish 2534 b common_exceptionThrown 2535 2536 2537/* ------------------------------ */ 2538 .balign 64 2539.L_OP_IGET_SHORT: /* 0x58 */ 2540/* File: armv5te/OP_IGET_SHORT.S */ 2541@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2542/* File: armv5te/OP_IGET.S */ 2543 /* 2544 * General 32-bit instance field get. 2545 * 2546 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2547 */ 2548 /* op vA, vB, field@CCCC */ 2549 mov r0, rINST, lsr #12 @ r0<- B 2550 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2551 FETCH(r1, 1) @ r1<- field ref CCCC 2552 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2553 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2554 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2555 cmp r0, #0 @ is resolved entry null? 2556 bne .LOP_IGET_SHORT_finish @ no, already resolved 25578: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2558 EXPORT_PC() @ resolve() could throw 2559 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2560 bl dvmResolveInstField @ r0<- resolved InstField ptr 2561 cmp r0, #0 2562 bne .LOP_IGET_SHORT_finish 2563 b common_exceptionThrown 2564 2565 2566/* ------------------------------ */ 2567 .balign 64 2568.L_OP_IPUT: /* 0x59 */ 2569/* File: armv5te/OP_IPUT.S */ 2570 /* 2571 * General 32-bit instance field put. 2572 * 2573 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2574 */ 2575 /* op vA, vB, field@CCCC */ 2576 mov r0, rINST, lsr #12 @ r0<- B 2577 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2578 FETCH(r1, 1) @ r1<- field ref CCCC 2579 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2580 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2581 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2582 cmp r0, #0 @ is resolved entry null? 2583 bne .LOP_IPUT_finish @ no, already resolved 25848: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2585 EXPORT_PC() @ resolve() could throw 2586 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2587 bl dvmResolveInstField @ r0<- resolved InstField ptr 2588 cmp r0, #0 @ success? 2589 bne .LOP_IPUT_finish @ yes, finish up 2590 b common_exceptionThrown 2591 2592/* ------------------------------ */ 2593 .balign 64 2594.L_OP_IPUT_WIDE: /* 0x5a */ 2595/* File: armv5te/OP_IPUT_WIDE.S */ 2596 /* iput-wide vA, vB, field@CCCC */ 2597 mov r0, rINST, lsr #12 @ r0<- B 2598 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2599 FETCH(r1, 1) @ r1<- field ref CCCC 2600 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2601 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2602 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2603 cmp r0, #0 @ is resolved entry null? 2604 bne .LOP_IPUT_WIDE_finish @ no, already resolved 26058: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2606 EXPORT_PC() @ resolve() could throw 2607 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2608 bl dvmResolveInstField @ r0<- resolved InstField ptr 2609 cmp r0, #0 @ success? 2610 bne .LOP_IPUT_WIDE_finish @ yes, finish up 2611 b common_exceptionThrown 2612 2613/* ------------------------------ */ 2614 .balign 64 2615.L_OP_IPUT_OBJECT: /* 0x5b */ 2616/* File: armv5te/OP_IPUT_OBJECT.S */ 2617 /* 2618 * 32-bit instance field put. 2619 * 2620 * for: iput-object, iput-object-volatile 2621 */ 2622 /* op vA, vB, field@CCCC */ 2623 mov r0, rINST, lsr #12 @ r0<- B 2624 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2625 FETCH(r1, 1) @ r1<- field ref CCCC 2626 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2627 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2628 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2629 cmp r0, #0 @ is resolved entry null? 2630 bne .LOP_IPUT_OBJECT_finish @ no, already resolved 26318: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2632 EXPORT_PC() @ resolve() could throw 2633 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2634 bl dvmResolveInstField @ r0<- resolved InstField ptr 2635 cmp r0, #0 @ success? 2636 bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2637 b common_exceptionThrown 2638 2639/* ------------------------------ */ 2640 .balign 64 2641.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2642/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2643@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2644/* File: armv5te/OP_IPUT.S */ 2645 /* 2646 * General 32-bit instance field put. 2647 * 2648 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2649 */ 2650 /* op vA, vB, field@CCCC */ 2651 mov r0, rINST, lsr #12 @ r0<- B 2652 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2653 FETCH(r1, 1) @ r1<- field ref CCCC 2654 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2655 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2656 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2657 cmp r0, #0 @ is resolved entry null? 2658 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 26598: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2660 EXPORT_PC() @ resolve() could throw 2661 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2662 bl dvmResolveInstField @ r0<- resolved InstField ptr 2663 cmp r0, #0 @ success? 2664 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2665 b common_exceptionThrown 2666 2667 2668/* ------------------------------ */ 2669 .balign 64 2670.L_OP_IPUT_BYTE: /* 0x5d */ 2671/* File: armv5te/OP_IPUT_BYTE.S */ 2672@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2673/* File: armv5te/OP_IPUT.S */ 2674 /* 2675 * General 32-bit instance field put. 2676 * 2677 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2678 */ 2679 /* op vA, vB, field@CCCC */ 2680 mov r0, rINST, lsr #12 @ r0<- B 2681 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2682 FETCH(r1, 1) @ r1<- field ref CCCC 2683 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2684 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2685 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2686 cmp r0, #0 @ is resolved entry null? 2687 bne .LOP_IPUT_BYTE_finish @ no, already resolved 26888: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2689 EXPORT_PC() @ resolve() could throw 2690 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2691 bl dvmResolveInstField @ r0<- resolved InstField ptr 2692 cmp r0, #0 @ success? 2693 bne .LOP_IPUT_BYTE_finish @ yes, finish up 2694 b common_exceptionThrown 2695 2696 2697/* ------------------------------ */ 2698 .balign 64 2699.L_OP_IPUT_CHAR: /* 0x5e */ 2700/* File: armv5te/OP_IPUT_CHAR.S */ 2701@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2702/* File: armv5te/OP_IPUT.S */ 2703 /* 2704 * General 32-bit instance field put. 2705 * 2706 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2707 */ 2708 /* op vA, vB, field@CCCC */ 2709 mov r0, rINST, lsr #12 @ r0<- B 2710 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2711 FETCH(r1, 1) @ r1<- field ref CCCC 2712 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2713 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2714 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2715 cmp r0, #0 @ is resolved entry null? 2716 bne .LOP_IPUT_CHAR_finish @ no, already resolved 27178: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2718 EXPORT_PC() @ resolve() could throw 2719 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2720 bl dvmResolveInstField @ r0<- resolved InstField ptr 2721 cmp r0, #0 @ success? 2722 bne .LOP_IPUT_CHAR_finish @ yes, finish up 2723 b common_exceptionThrown 2724 2725 2726/* ------------------------------ */ 2727 .balign 64 2728.L_OP_IPUT_SHORT: /* 0x5f */ 2729/* File: armv5te/OP_IPUT_SHORT.S */ 2730@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2731/* File: armv5te/OP_IPUT.S */ 2732 /* 2733 * General 32-bit instance field put. 2734 * 2735 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2736 */ 2737 /* op vA, vB, field@CCCC */ 2738 mov r0, rINST, lsr #12 @ r0<- B 2739 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2740 FETCH(r1, 1) @ r1<- field ref CCCC 2741 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2742 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2743 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2744 cmp r0, #0 @ is resolved entry null? 2745 bne .LOP_IPUT_SHORT_finish @ no, already resolved 27468: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2747 EXPORT_PC() @ resolve() could throw 2748 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2749 bl dvmResolveInstField @ r0<- resolved InstField ptr 2750 cmp r0, #0 @ success? 2751 bne .LOP_IPUT_SHORT_finish @ yes, finish up 2752 b common_exceptionThrown 2753 2754 2755/* ------------------------------ */ 2756 .balign 64 2757.L_OP_SGET: /* 0x60 */ 2758/* File: armv5te/OP_SGET.S */ 2759 /* 2760 * General 32-bit SGET handler. 2761 * 2762 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2763 */ 2764 /* op vAA, field@BBBB */ 2765 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2766 FETCH(r1, 1) @ r1<- field ref BBBB 2767 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2768 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2769 cmp r0, #0 @ is resolved entry null? 2770 beq .LOP_SGET_resolve @ yes, do resolve 2771.LOP_SGET_finish: @ field ptr in r0 2772 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2773 @ no-op @ acquiring load 2774 mov r2, rINST, lsr #8 @ r2<- AA 2775 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2776 SET_VREG(r1, r2) @ fp[AA]<- r1 2777 GET_INST_OPCODE(ip) @ extract opcode from rINST 2778 GOTO_OPCODE(ip) @ jump to next instruction 2779 2780/* ------------------------------ */ 2781 .balign 64 2782.L_OP_SGET_WIDE: /* 0x61 */ 2783/* File: armv5te/OP_SGET_WIDE.S */ 2784 /* 2785 * 64-bit SGET handler. 2786 */ 2787 /* sget-wide vAA, field@BBBB */ 2788 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2789 FETCH(r1, 1) @ r1<- field ref BBBB 2790 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2791 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2792 cmp r0, #0 @ is resolved entry null? 2793 beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2794.LOP_SGET_WIDE_finish: 2795 mov r9, rINST, lsr #8 @ r9<- AA 2796 .if 0 2797 add r0, r0, #offStaticField_value @ r0<- pointer to data 2798 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2799 .else 2800 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2801 .endif 2802 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2803 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2804 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2805 GET_INST_OPCODE(ip) @ extract opcode from rINST 2806 GOTO_OPCODE(ip) @ jump to next instruction 2807 2808/* ------------------------------ */ 2809 .balign 64 2810.L_OP_SGET_OBJECT: /* 0x62 */ 2811/* File: armv5te/OP_SGET_OBJECT.S */ 2812/* File: armv5te/OP_SGET.S */ 2813 /* 2814 * General 32-bit SGET handler. 2815 * 2816 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2817 */ 2818 /* op vAA, field@BBBB */ 2819 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2820 FETCH(r1, 1) @ r1<- field ref BBBB 2821 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2822 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2823 cmp r0, #0 @ is resolved entry null? 2824 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2825.LOP_SGET_OBJECT_finish: @ field ptr in r0 2826 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2827 @ no-op @ acquiring load 2828 mov r2, rINST, lsr #8 @ r2<- AA 2829 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2830 SET_VREG(r1, r2) @ fp[AA]<- r1 2831 GET_INST_OPCODE(ip) @ extract opcode from rINST 2832 GOTO_OPCODE(ip) @ jump to next instruction 2833 2834 2835/* ------------------------------ */ 2836 .balign 64 2837.L_OP_SGET_BOOLEAN: /* 0x63 */ 2838/* File: armv5te/OP_SGET_BOOLEAN.S */ 2839/* File: armv5te/OP_SGET.S */ 2840 /* 2841 * General 32-bit SGET handler. 2842 * 2843 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2844 */ 2845 /* op vAA, field@BBBB */ 2846 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2847 FETCH(r1, 1) @ r1<- field ref BBBB 2848 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2849 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2850 cmp r0, #0 @ is resolved entry null? 2851 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2852.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2853 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2854 @ no-op @ acquiring load 2855 mov r2, rINST, lsr #8 @ r2<- AA 2856 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2857 SET_VREG(r1, r2) @ fp[AA]<- r1 2858 GET_INST_OPCODE(ip) @ extract opcode from rINST 2859 GOTO_OPCODE(ip) @ jump to next instruction 2860 2861 2862/* ------------------------------ */ 2863 .balign 64 2864.L_OP_SGET_BYTE: /* 0x64 */ 2865/* File: armv5te/OP_SGET_BYTE.S */ 2866/* File: armv5te/OP_SGET.S */ 2867 /* 2868 * General 32-bit SGET handler. 2869 * 2870 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2871 */ 2872 /* op vAA, field@BBBB */ 2873 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2874 FETCH(r1, 1) @ r1<- field ref BBBB 2875 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2876 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2877 cmp r0, #0 @ is resolved entry null? 2878 beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2879.LOP_SGET_BYTE_finish: @ field ptr in r0 2880 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2881 @ no-op @ acquiring load 2882 mov r2, rINST, lsr #8 @ r2<- AA 2883 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2884 SET_VREG(r1, r2) @ fp[AA]<- r1 2885 GET_INST_OPCODE(ip) @ extract opcode from rINST 2886 GOTO_OPCODE(ip) @ jump to next instruction 2887 2888 2889/* ------------------------------ */ 2890 .balign 64 2891.L_OP_SGET_CHAR: /* 0x65 */ 2892/* File: armv5te/OP_SGET_CHAR.S */ 2893/* File: armv5te/OP_SGET.S */ 2894 /* 2895 * General 32-bit SGET handler. 2896 * 2897 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2898 */ 2899 /* op vAA, field@BBBB */ 2900 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2901 FETCH(r1, 1) @ r1<- field ref BBBB 2902 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2903 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2904 cmp r0, #0 @ is resolved entry null? 2905 beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2906.LOP_SGET_CHAR_finish: @ field ptr in r0 2907 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2908 @ no-op @ acquiring load 2909 mov r2, rINST, lsr #8 @ r2<- AA 2910 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2911 SET_VREG(r1, r2) @ fp[AA]<- r1 2912 GET_INST_OPCODE(ip) @ extract opcode from rINST 2913 GOTO_OPCODE(ip) @ jump to next instruction 2914 2915 2916/* ------------------------------ */ 2917 .balign 64 2918.L_OP_SGET_SHORT: /* 0x66 */ 2919/* File: armv5te/OP_SGET_SHORT.S */ 2920/* File: armv5te/OP_SGET.S */ 2921 /* 2922 * General 32-bit SGET handler. 2923 * 2924 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2925 */ 2926 /* op vAA, field@BBBB */ 2927 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2928 FETCH(r1, 1) @ r1<- field ref BBBB 2929 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2930 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2931 cmp r0, #0 @ is resolved entry null? 2932 beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2933.LOP_SGET_SHORT_finish: @ field ptr in r0 2934 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2935 @ no-op @ acquiring load 2936 mov r2, rINST, lsr #8 @ r2<- AA 2937 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2938 SET_VREG(r1, r2) @ fp[AA]<- r1 2939 GET_INST_OPCODE(ip) @ extract opcode from rINST 2940 GOTO_OPCODE(ip) @ jump to next instruction 2941 2942 2943/* ------------------------------ */ 2944 .balign 64 2945.L_OP_SPUT: /* 0x67 */ 2946/* File: armv5te/OP_SPUT.S */ 2947 /* 2948 * General 32-bit SPUT handler. 2949 * 2950 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2951 */ 2952 /* op vAA, field@BBBB */ 2953 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2954 FETCH(r1, 1) @ r1<- field ref BBBB 2955 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2956 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2957 cmp r0, #0 @ is resolved entry null? 2958 beq .LOP_SPUT_resolve @ yes, do resolve 2959.LOP_SPUT_finish: @ field ptr in r0 2960 mov r2, rINST, lsr #8 @ r2<- AA 2961 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2962 GET_VREG(r1, r2) @ r1<- fp[AA] 2963 GET_INST_OPCODE(ip) @ extract opcode from rINST 2964 @ no-op @ releasing store 2965 str r1, [r0, #offStaticField_value] @ field<- vAA 2966 GOTO_OPCODE(ip) @ jump to next instruction 2967 2968/* ------------------------------ */ 2969 .balign 64 2970.L_OP_SPUT_WIDE: /* 0x68 */ 2971/* File: armv5te/OP_SPUT_WIDE.S */ 2972 /* 2973 * 64-bit SPUT handler. 2974 */ 2975 /* sput-wide vAA, field@BBBB */ 2976 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 2977 FETCH(r1, 1) @ r1<- field ref BBBB 2978 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 2979 mov r9, rINST, lsr #8 @ r9<- AA 2980 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 2981 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2982 cmp r2, #0 @ is resolved entry null? 2983 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 2984.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 2985 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2986 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 2987 GET_INST_OPCODE(r10) @ extract opcode from rINST 2988 .if 0 2989 add r2, r2, #offStaticField_value @ r2<- pointer to data 2990 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 2991 .else 2992 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 2993 .endif 2994 GOTO_OPCODE(r10) @ jump to next instruction 2995 2996/* ------------------------------ */ 2997 .balign 64 2998.L_OP_SPUT_OBJECT: /* 0x69 */ 2999/* File: armv5te/OP_SPUT_OBJECT.S */ 3000 /* 3001 * 32-bit SPUT handler for objects 3002 * 3003 * for: sput-object, sput-object-volatile 3004 */ 3005 /* op vAA, field@BBBB */ 3006 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3007 FETCH(r1, 1) @ r1<- field ref BBBB 3008 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3009 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3010 cmp r0, #0 @ is resolved entry null? 3011 bne .LOP_SPUT_OBJECT_finish @ no, continue 3012 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3013 EXPORT_PC() @ resolve() could throw, so export now 3014 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 3015 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 3016 cmp r0, #0 @ success? 3017 bne .LOP_SPUT_OBJECT_finish @ yes, finish 3018 b common_exceptionThrown @ no, handle exception 3019 3020 3021/* ------------------------------ */ 3022 .balign 64 3023.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3024/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3025/* File: armv5te/OP_SPUT.S */ 3026 /* 3027 * General 32-bit SPUT handler. 3028 * 3029 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3030 */ 3031 /* op vAA, field@BBBB */ 3032 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3033 FETCH(r1, 1) @ r1<- field ref BBBB 3034 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3035 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3036 cmp r0, #0 @ is resolved entry null? 3037 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3038.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3039 mov r2, rINST, lsr #8 @ r2<- AA 3040 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3041 GET_VREG(r1, r2) @ r1<- fp[AA] 3042 GET_INST_OPCODE(ip) @ extract opcode from rINST 3043 @ no-op @ releasing store 3044 str r1, [r0, #offStaticField_value] @ field<- vAA 3045 GOTO_OPCODE(ip) @ jump to next instruction 3046 3047 3048/* ------------------------------ */ 3049 .balign 64 3050.L_OP_SPUT_BYTE: /* 0x6b */ 3051/* File: armv5te/OP_SPUT_BYTE.S */ 3052/* File: armv5te/OP_SPUT.S */ 3053 /* 3054 * General 32-bit SPUT handler. 3055 * 3056 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3057 */ 3058 /* op vAA, field@BBBB */ 3059 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3060 FETCH(r1, 1) @ r1<- field ref BBBB 3061 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3062 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3063 cmp r0, #0 @ is resolved entry null? 3064 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3065.LOP_SPUT_BYTE_finish: @ field ptr in r0 3066 mov r2, rINST, lsr #8 @ r2<- AA 3067 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3068 GET_VREG(r1, r2) @ r1<- fp[AA] 3069 GET_INST_OPCODE(ip) @ extract opcode from rINST 3070 @ no-op @ releasing store 3071 str r1, [r0, #offStaticField_value] @ field<- vAA 3072 GOTO_OPCODE(ip) @ jump to next instruction 3073 3074 3075/* ------------------------------ */ 3076 .balign 64 3077.L_OP_SPUT_CHAR: /* 0x6c */ 3078/* File: armv5te/OP_SPUT_CHAR.S */ 3079/* File: armv5te/OP_SPUT.S */ 3080 /* 3081 * General 32-bit SPUT handler. 3082 * 3083 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3084 */ 3085 /* op vAA, field@BBBB */ 3086 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3087 FETCH(r1, 1) @ r1<- field ref BBBB 3088 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3089 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3090 cmp r0, #0 @ is resolved entry null? 3091 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3092.LOP_SPUT_CHAR_finish: @ field ptr in r0 3093 mov r2, rINST, lsr #8 @ r2<- AA 3094 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3095 GET_VREG(r1, r2) @ r1<- fp[AA] 3096 GET_INST_OPCODE(ip) @ extract opcode from rINST 3097 @ no-op @ releasing store 3098 str r1, [r0, #offStaticField_value] @ field<- vAA 3099 GOTO_OPCODE(ip) @ jump to next instruction 3100 3101 3102/* ------------------------------ */ 3103 .balign 64 3104.L_OP_SPUT_SHORT: /* 0x6d */ 3105/* File: armv5te/OP_SPUT_SHORT.S */ 3106/* File: armv5te/OP_SPUT.S */ 3107 /* 3108 * General 32-bit SPUT handler. 3109 * 3110 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3111 */ 3112 /* op vAA, field@BBBB */ 3113 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3114 FETCH(r1, 1) @ r1<- field ref BBBB 3115 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3116 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3117 cmp r0, #0 @ is resolved entry null? 3118 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3119.LOP_SPUT_SHORT_finish: @ field ptr in r0 3120 mov r2, rINST, lsr #8 @ r2<- AA 3121 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3122 GET_VREG(r1, r2) @ r1<- fp[AA] 3123 GET_INST_OPCODE(ip) @ extract opcode from rINST 3124 @ no-op @ releasing store 3125 str r1, [r0, #offStaticField_value] @ field<- vAA 3126 GOTO_OPCODE(ip) @ jump to next instruction 3127 3128 3129/* ------------------------------ */ 3130 .balign 64 3131.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3132/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3133 /* 3134 * Handle a virtual method call. 3135 * 3136 * for: invoke-virtual, invoke-virtual/range 3137 */ 3138 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3139 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3140 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3141 FETCH(r1, 1) @ r1<- BBBB 3142 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3143 FETCH(r10, 2) @ r10<- GFED or CCCC 3144 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3145 .if (!0) 3146 and r10, r10, #15 @ r10<- D (or stays CCCC) 3147 .endif 3148 cmp r0, #0 @ already resolved? 3149 EXPORT_PC() @ must export for invoke 3150 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3151 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3152 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3153 mov r2, #METHOD_VIRTUAL @ resolver method type 3154 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3155 cmp r0, #0 @ got null? 3156 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3157 b common_exceptionThrown @ yes, handle exception 3158 3159/* ------------------------------ */ 3160 .balign 64 3161.L_OP_INVOKE_SUPER: /* 0x6f */ 3162/* File: armv5te/OP_INVOKE_SUPER.S */ 3163 /* 3164 * Handle a "super" method call. 3165 * 3166 * for: invoke-super, invoke-super/range 3167 */ 3168 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3169 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3170 FETCH(r10, 2) @ r10<- GFED or CCCC 3171 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3172 .if (!0) 3173 and r10, r10, #15 @ r10<- D (or stays CCCC) 3174 .endif 3175 FETCH(r1, 1) @ r1<- BBBB 3176 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3177 GET_VREG(r2, r10) @ r2<- "this" ptr 3178 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3179 cmp r2, #0 @ null "this"? 3180 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3181 beq common_errNullObject @ null "this", throw exception 3182 cmp r0, #0 @ already resolved? 3183 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3184 EXPORT_PC() @ must export for invoke 3185 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3186 b .LOP_INVOKE_SUPER_resolve @ do resolve now 3187 3188/* ------------------------------ */ 3189 .balign 64 3190.L_OP_INVOKE_DIRECT: /* 0x70 */ 3191/* File: armv5te/OP_INVOKE_DIRECT.S */ 3192 /* 3193 * Handle a direct method call. 3194 * 3195 * (We could defer the "is 'this' pointer null" test to the common 3196 * method invocation code, and use a flag to indicate that static 3197 * calls don't count. If we do this as part of copying the arguments 3198 * out we could avoiding loading the first arg twice.) 3199 * 3200 * for: invoke-direct, invoke-direct/range 3201 */ 3202 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3203 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3204 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3205 FETCH(r1, 1) @ r1<- BBBB 3206 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3207 FETCH(r10, 2) @ r10<- GFED or CCCC 3208 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3209 .if (!0) 3210 and r10, r10, #15 @ r10<- D (or stays CCCC) 3211 .endif 3212 cmp r0, #0 @ already resolved? 3213 EXPORT_PC() @ must export for invoke 3214 GET_VREG(r2, r10) @ r2<- "this" ptr 3215 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3216.LOP_INVOKE_DIRECT_finish: 3217 cmp r2, #0 @ null "this" ref? 3218 bne common_invokeMethodNoRange @ no, continue on 3219 b common_errNullObject @ yes, throw exception 3220 3221/* ------------------------------ */ 3222 .balign 64 3223.L_OP_INVOKE_STATIC: /* 0x71 */ 3224/* File: armv5te/OP_INVOKE_STATIC.S */ 3225 /* 3226 * Handle a static method call. 3227 * 3228 * for: invoke-static, invoke-static/range 3229 */ 3230 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3231 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3232 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3233 FETCH(r1, 1) @ r1<- BBBB 3234 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3235 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3236 cmp r0, #0 @ already resolved? 3237 EXPORT_PC() @ must export for invoke 3238 bne common_invokeMethodNoRange @ yes, continue on 32390: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3240 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3241 mov r2, #METHOD_STATIC @ resolver method type 3242 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3243 cmp r0, #0 @ got null? 3244 bne common_invokeMethodNoRange @ no, continue 3245 b common_exceptionThrown @ yes, handle exception 3246 3247/* ------------------------------ */ 3248 .balign 64 3249.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3250/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3251 /* 3252 * Handle an interface method call. 3253 * 3254 * for: invoke-interface, invoke-interface/range 3255 */ 3256 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3257 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3258 FETCH(r2, 2) @ r2<- FEDC or CCCC 3259 FETCH(r1, 1) @ r1<- BBBB 3260 .if (!0) 3261 and r2, r2, #15 @ r2<- C (or stays CCCC) 3262 .endif 3263 EXPORT_PC() @ must export for invoke 3264 GET_VREG(r0, r2) @ r0<- first arg ("this") 3265 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3266 cmp r0, #0 @ null obj? 3267 ldr r2, [rSELF, #offThread_method] @ r2<- method 3268 beq common_errNullObject @ yes, fail 3269 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3270 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3271 cmp r0, #0 @ failed? 3272 beq common_exceptionThrown @ yes, handle exception 3273 b common_invokeMethodNoRange @ jump to common handler 3274 3275/* ------------------------------ */ 3276 .balign 64 3277.L_OP_UNUSED_73: /* 0x73 */ 3278/* File: armv5te/OP_UNUSED_73.S */ 3279/* File: armv5te/unused.S */ 3280 bl common_abort 3281 3282 3283/* ------------------------------ */ 3284 .balign 64 3285.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3286/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3287/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3288 /* 3289 * Handle a virtual method call. 3290 * 3291 * for: invoke-virtual, invoke-virtual/range 3292 */ 3293 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3294 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3295 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3296 FETCH(r1, 1) @ r1<- BBBB 3297 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3298 FETCH(r10, 2) @ r10<- GFED or CCCC 3299 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3300 .if (!1) 3301 and r10, r10, #15 @ r10<- D (or stays CCCC) 3302 .endif 3303 cmp r0, #0 @ already resolved? 3304 EXPORT_PC() @ must export for invoke 3305 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3306 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3307 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3308 mov r2, #METHOD_VIRTUAL @ resolver method type 3309 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3310 cmp r0, #0 @ got null? 3311 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3312 b common_exceptionThrown @ yes, handle exception 3313 3314 3315/* ------------------------------ */ 3316 .balign 64 3317.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3318/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3319/* File: armv5te/OP_INVOKE_SUPER.S */ 3320 /* 3321 * Handle a "super" method call. 3322 * 3323 * for: invoke-super, invoke-super/range 3324 */ 3325 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3326 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3327 FETCH(r10, 2) @ r10<- GFED or CCCC 3328 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3329 .if (!1) 3330 and r10, r10, #15 @ r10<- D (or stays CCCC) 3331 .endif 3332 FETCH(r1, 1) @ r1<- BBBB 3333 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3334 GET_VREG(r2, r10) @ r2<- "this" ptr 3335 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3336 cmp r2, #0 @ null "this"? 3337 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3338 beq common_errNullObject @ null "this", throw exception 3339 cmp r0, #0 @ already resolved? 3340 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3341 EXPORT_PC() @ must export for invoke 3342 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3343 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3344 3345 3346/* ------------------------------ */ 3347 .balign 64 3348.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3349/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3350/* File: armv5te/OP_INVOKE_DIRECT.S */ 3351 /* 3352 * Handle a direct method call. 3353 * 3354 * (We could defer the "is 'this' pointer null" test to the common 3355 * method invocation code, and use a flag to indicate that static 3356 * calls don't count. If we do this as part of copying the arguments 3357 * out we could avoiding loading the first arg twice.) 3358 * 3359 * for: invoke-direct, invoke-direct/range 3360 */ 3361 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3362 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3363 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3364 FETCH(r1, 1) @ r1<- BBBB 3365 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3366 FETCH(r10, 2) @ r10<- GFED or CCCC 3367 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3368 .if (!1) 3369 and r10, r10, #15 @ r10<- D (or stays CCCC) 3370 .endif 3371 cmp r0, #0 @ already resolved? 3372 EXPORT_PC() @ must export for invoke 3373 GET_VREG(r2, r10) @ r2<- "this" ptr 3374 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3375.LOP_INVOKE_DIRECT_RANGE_finish: 3376 cmp r2, #0 @ null "this" ref? 3377 bne common_invokeMethodRange @ no, continue on 3378 b common_errNullObject @ yes, throw exception 3379 3380 3381/* ------------------------------ */ 3382 .balign 64 3383.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3384/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3385/* File: armv5te/OP_INVOKE_STATIC.S */ 3386 /* 3387 * Handle a static method call. 3388 * 3389 * for: invoke-static, invoke-static/range 3390 */ 3391 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3392 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3393 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3394 FETCH(r1, 1) @ r1<- BBBB 3395 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3396 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3397 cmp r0, #0 @ already resolved? 3398 EXPORT_PC() @ must export for invoke 3399 bne common_invokeMethodRange @ yes, continue on 34000: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3401 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3402 mov r2, #METHOD_STATIC @ resolver method type 3403 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3404 cmp r0, #0 @ got null? 3405 bne common_invokeMethodRange @ no, continue 3406 b common_exceptionThrown @ yes, handle exception 3407 3408 3409/* ------------------------------ */ 3410 .balign 64 3411.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3412/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3413/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3414 /* 3415 * Handle an interface method call. 3416 * 3417 * for: invoke-interface, invoke-interface/range 3418 */ 3419 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3420 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3421 FETCH(r2, 2) @ r2<- FEDC or CCCC 3422 FETCH(r1, 1) @ r1<- BBBB 3423 .if (!1) 3424 and r2, r2, #15 @ r2<- C (or stays CCCC) 3425 .endif 3426 EXPORT_PC() @ must export for invoke 3427 GET_VREG(r0, r2) @ r0<- first arg ("this") 3428 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3429 cmp r0, #0 @ null obj? 3430 ldr r2, [rSELF, #offThread_method] @ r2<- method 3431 beq common_errNullObject @ yes, fail 3432 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3433 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3434 cmp r0, #0 @ failed? 3435 beq common_exceptionThrown @ yes, handle exception 3436 b common_invokeMethodRange @ jump to common handler 3437 3438 3439/* ------------------------------ */ 3440 .balign 64 3441.L_OP_UNUSED_79: /* 0x79 */ 3442/* File: armv5te/OP_UNUSED_79.S */ 3443/* File: armv5te/unused.S */ 3444 bl common_abort 3445 3446 3447/* ------------------------------ */ 3448 .balign 64 3449.L_OP_UNUSED_7A: /* 0x7a */ 3450/* File: armv5te/OP_UNUSED_7A.S */ 3451/* File: armv5te/unused.S */ 3452 bl common_abort 3453 3454 3455/* ------------------------------ */ 3456 .balign 64 3457.L_OP_NEG_INT: /* 0x7b */ 3458/* File: armv5te/OP_NEG_INT.S */ 3459/* File: armv5te/unop.S */ 3460 /* 3461 * Generic 32-bit unary operation. Provide an "instr" line that 3462 * specifies an instruction that performs "result = op r0". 3463 * This could be an ARM instruction or a function call. 3464 * 3465 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3466 * int-to-byte, int-to-char, int-to-short 3467 */ 3468 /* unop vA, vB */ 3469 mov r3, rINST, lsr #12 @ r3<- B 3470 mov r9, rINST, lsr #8 @ r9<- A+ 3471 GET_VREG(r0, r3) @ r0<- vB 3472 and r9, r9, #15 3473 @ optional op; may set condition codes 3474 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3475 rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3476 GET_INST_OPCODE(ip) @ extract opcode from rINST 3477 SET_VREG(r0, r9) @ vAA<- r0 3478 GOTO_OPCODE(ip) @ jump to next instruction 3479 /* 9-10 instructions */ 3480 3481 3482/* ------------------------------ */ 3483 .balign 64 3484.L_OP_NOT_INT: /* 0x7c */ 3485/* File: armv5te/OP_NOT_INT.S */ 3486/* File: armv5te/unop.S */ 3487 /* 3488 * Generic 32-bit unary operation. Provide an "instr" line that 3489 * specifies an instruction that performs "result = op r0". 3490 * This could be an ARM instruction or a function call. 3491 * 3492 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3493 * int-to-byte, int-to-char, int-to-short 3494 */ 3495 /* unop vA, vB */ 3496 mov r3, rINST, lsr #12 @ r3<- B 3497 mov r9, rINST, lsr #8 @ r9<- A+ 3498 GET_VREG(r0, r3) @ r0<- vB 3499 and r9, r9, #15 3500 @ optional op; may set condition codes 3501 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3502 mvn r0, r0 @ r0<- op, r0-r3 changed 3503 GET_INST_OPCODE(ip) @ extract opcode from rINST 3504 SET_VREG(r0, r9) @ vAA<- r0 3505 GOTO_OPCODE(ip) @ jump to next instruction 3506 /* 9-10 instructions */ 3507 3508 3509/* ------------------------------ */ 3510 .balign 64 3511.L_OP_NEG_LONG: /* 0x7d */ 3512/* File: armv5te/OP_NEG_LONG.S */ 3513/* File: armv5te/unopWide.S */ 3514 /* 3515 * Generic 64-bit unary operation. Provide an "instr" line that 3516 * specifies an instruction that performs "result = op r0/r1". 3517 * This could be an ARM instruction or a function call. 3518 * 3519 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3520 */ 3521 /* unop vA, vB */ 3522 mov r9, rINST, lsr #8 @ r9<- A+ 3523 mov r3, rINST, lsr #12 @ r3<- B 3524 and r9, r9, #15 3525 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3526 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3527 ldmia r3, {r0-r1} @ r0/r1<- vAA 3528 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3529 rsbs r0, r0, #0 @ optional op; may set condition codes 3530 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3531 GET_INST_OPCODE(ip) @ extract opcode from rINST 3532 stmia r9, {r0-r1} @ vAA<- r0/r1 3533 GOTO_OPCODE(ip) @ jump to next instruction 3534 /* 12-13 instructions */ 3535 3536 3537/* ------------------------------ */ 3538 .balign 64 3539.L_OP_NOT_LONG: /* 0x7e */ 3540/* File: armv5te/OP_NOT_LONG.S */ 3541/* File: armv5te/unopWide.S */ 3542 /* 3543 * Generic 64-bit unary operation. Provide an "instr" line that 3544 * specifies an instruction that performs "result = op r0/r1". 3545 * This could be an ARM instruction or a function call. 3546 * 3547 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3548 */ 3549 /* unop vA, vB */ 3550 mov r9, rINST, lsr #8 @ r9<- A+ 3551 mov r3, rINST, lsr #12 @ r3<- B 3552 and r9, r9, #15 3553 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3554 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3555 ldmia r3, {r0-r1} @ r0/r1<- vAA 3556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3557 mvn r0, r0 @ optional op; may set condition codes 3558 mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3559 GET_INST_OPCODE(ip) @ extract opcode from rINST 3560 stmia r9, {r0-r1} @ vAA<- r0/r1 3561 GOTO_OPCODE(ip) @ jump to next instruction 3562 /* 12-13 instructions */ 3563 3564 3565/* ------------------------------ */ 3566 .balign 64 3567.L_OP_NEG_FLOAT: /* 0x7f */ 3568/* File: armv5te/OP_NEG_FLOAT.S */ 3569/* File: armv5te/unop.S */ 3570 /* 3571 * Generic 32-bit unary operation. Provide an "instr" line that 3572 * specifies an instruction that performs "result = op r0". 3573 * This could be an ARM instruction or a function call. 3574 * 3575 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3576 * int-to-byte, int-to-char, int-to-short 3577 */ 3578 /* unop vA, vB */ 3579 mov r3, rINST, lsr #12 @ r3<- B 3580 mov r9, rINST, lsr #8 @ r9<- A+ 3581 GET_VREG(r0, r3) @ r0<- vB 3582 and r9, r9, #15 3583 @ optional op; may set condition codes 3584 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3585 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3586 GET_INST_OPCODE(ip) @ extract opcode from rINST 3587 SET_VREG(r0, r9) @ vAA<- r0 3588 GOTO_OPCODE(ip) @ jump to next instruction 3589 /* 9-10 instructions */ 3590 3591 3592/* ------------------------------ */ 3593 .balign 64 3594.L_OP_NEG_DOUBLE: /* 0x80 */ 3595/* File: armv5te/OP_NEG_DOUBLE.S */ 3596/* File: armv5te/unopWide.S */ 3597 /* 3598 * Generic 64-bit unary operation. Provide an "instr" line that 3599 * specifies an instruction that performs "result = op r0/r1". 3600 * This could be an ARM instruction or a function call. 3601 * 3602 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3603 */ 3604 /* unop vA, vB */ 3605 mov r9, rINST, lsr #8 @ r9<- A+ 3606 mov r3, rINST, lsr #12 @ r3<- B 3607 and r9, r9, #15 3608 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3609 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3610 ldmia r3, {r0-r1} @ r0/r1<- vAA 3611 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3612 @ optional op; may set condition codes 3613 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3614 GET_INST_OPCODE(ip) @ extract opcode from rINST 3615 stmia r9, {r0-r1} @ vAA<- r0/r1 3616 GOTO_OPCODE(ip) @ jump to next instruction 3617 /* 12-13 instructions */ 3618 3619 3620/* ------------------------------ */ 3621 .balign 64 3622.L_OP_INT_TO_LONG: /* 0x81 */ 3623/* File: armv5te/OP_INT_TO_LONG.S */ 3624/* File: armv5te/unopWider.S */ 3625 /* 3626 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3627 * that specifies an instruction that performs "result = op r0", where 3628 * "result" is a 64-bit quantity in r0/r1. 3629 * 3630 * For: int-to-long, int-to-double, float-to-long, float-to-double 3631 */ 3632 /* unop vA, vB */ 3633 mov r9, rINST, lsr #8 @ r9<- A+ 3634 mov r3, rINST, lsr #12 @ r3<- B 3635 and r9, r9, #15 3636 GET_VREG(r0, r3) @ r0<- vB 3637 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3638 @ optional op; may set condition codes 3639 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3640 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3641 GET_INST_OPCODE(ip) @ extract opcode from rINST 3642 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3643 GOTO_OPCODE(ip) @ jump to next instruction 3644 /* 10-11 instructions */ 3645 3646 3647/* ------------------------------ */ 3648 .balign 64 3649.L_OP_INT_TO_FLOAT: /* 0x82 */ 3650/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3651/* File: arm-vfp/funop.S */ 3652 /* 3653 * Generic 32-bit unary floating-point operation. Provide an "instr" 3654 * line that specifies an instruction that performs "s1 = op s0". 3655 * 3656 * for: int-to-float, float-to-int 3657 */ 3658 /* unop vA, vB */ 3659 mov r3, rINST, lsr #12 @ r3<- B 3660 mov r9, rINST, lsr #8 @ r9<- A+ 3661 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3662 flds s0, [r3] @ s0<- vB 3663 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3664 and r9, r9, #15 @ r9<- A 3665 fsitos s1, s0 @ s1<- op 3666 GET_INST_OPCODE(ip) @ extract opcode from rINST 3667 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3668 fsts s1, [r9] @ vA<- s1 3669 GOTO_OPCODE(ip) @ jump to next instruction 3670 3671 3672/* ------------------------------ */ 3673 .balign 64 3674.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3675/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3676/* File: arm-vfp/funopWider.S */ 3677 /* 3678 * Generic 32bit-to-64bit floating point unary operation. Provide an 3679 * "instr" line that specifies an instruction that performs "d0 = op s0". 3680 * 3681 * For: int-to-double, float-to-double 3682 */ 3683 /* unop vA, vB */ 3684 mov r3, rINST, lsr #12 @ r3<- B 3685 mov r9, rINST, lsr #8 @ r9<- A+ 3686 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3687 flds s0, [r3] @ s0<- vB 3688 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3689 and r9, r9, #15 @ r9<- A 3690 fsitod d0, s0 @ d0<- op 3691 GET_INST_OPCODE(ip) @ extract opcode from rINST 3692 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3693 fstd d0, [r9] @ vA<- d0 3694 GOTO_OPCODE(ip) @ jump to next instruction 3695 3696 3697/* ------------------------------ */ 3698 .balign 64 3699.L_OP_LONG_TO_INT: /* 0x84 */ 3700/* File: armv5te/OP_LONG_TO_INT.S */ 3701/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3702/* File: armv5te/OP_MOVE.S */ 3703 /* for move, move-object, long-to-int */ 3704 /* op vA, vB */ 3705 mov r1, rINST, lsr #12 @ r1<- B from 15:12 3706 mov r0, rINST, lsr #8 @ r0<- A from 11:8 3707 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3708 GET_VREG(r2, r1) @ r2<- fp[B] 3709 and r0, r0, #15 3710 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3711 SET_VREG(r2, r0) @ fp[A]<- r2 3712 GOTO_OPCODE(ip) @ execute next instruction 3713 3714 3715/* ------------------------------ */ 3716 .balign 64 3717.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3718/* File: armv5te/OP_LONG_TO_FLOAT.S */ 3719/* File: armv5te/unopNarrower.S */ 3720 /* 3721 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3722 * that specifies an instruction that performs "result = op r0/r1", where 3723 * "result" is a 32-bit quantity in r0. 3724 * 3725 * For: long-to-float, double-to-int, double-to-float 3726 * 3727 * (This would work for long-to-int, but that instruction is actually 3728 * an exact match for OP_MOVE.) 3729 */ 3730 /* unop vA, vB */ 3731 mov r3, rINST, lsr #12 @ r3<- B 3732 mov r9, rINST, lsr #8 @ r9<- A+ 3733 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3734 and r9, r9, #15 3735 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3736 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3737 @ optional op; may set condition codes 3738 bl __aeabi_l2f @ r0<- op, r0-r3 changed 3739 GET_INST_OPCODE(ip) @ extract opcode from rINST 3740 SET_VREG(r0, r9) @ vA<- r0 3741 GOTO_OPCODE(ip) @ jump to next instruction 3742 /* 10-11 instructions */ 3743 3744 3745/* ------------------------------ */ 3746 .balign 64 3747.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3748/* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3749/* File: armv5te/unopWide.S */ 3750 /* 3751 * Generic 64-bit unary operation. Provide an "instr" line that 3752 * specifies an instruction that performs "result = op r0/r1". 3753 * This could be an ARM instruction or a function call. 3754 * 3755 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3756 */ 3757 /* unop vA, vB */ 3758 mov r9, rINST, lsr #8 @ r9<- A+ 3759 mov r3, rINST, lsr #12 @ r3<- B 3760 and r9, r9, #15 3761 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3762 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3763 ldmia r3, {r0-r1} @ r0/r1<- vAA 3764 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3765 @ optional op; may set condition codes 3766 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3767 GET_INST_OPCODE(ip) @ extract opcode from rINST 3768 stmia r9, {r0-r1} @ vAA<- r0/r1 3769 GOTO_OPCODE(ip) @ jump to next instruction 3770 /* 12-13 instructions */ 3771 3772 3773/* ------------------------------ */ 3774 .balign 64 3775.L_OP_FLOAT_TO_INT: /* 0x87 */ 3776/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3777/* File: arm-vfp/funop.S */ 3778 /* 3779 * Generic 32-bit unary floating-point operation. Provide an "instr" 3780 * line that specifies an instruction that performs "s1 = op s0". 3781 * 3782 * for: int-to-float, float-to-int 3783 */ 3784 /* unop vA, vB */ 3785 mov r3, rINST, lsr #12 @ r3<- B 3786 mov r9, rINST, lsr #8 @ r9<- A+ 3787 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3788 flds s0, [r3] @ s0<- vB 3789 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3790 and r9, r9, #15 @ r9<- A 3791 ftosizs s1, s0 @ s1<- op 3792 GET_INST_OPCODE(ip) @ extract opcode from rINST 3793 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3794 fsts s1, [r9] @ vA<- s1 3795 GOTO_OPCODE(ip) @ jump to next instruction 3796 3797 3798/* ------------------------------ */ 3799 .balign 64 3800.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3801/* File: armv5te/OP_FLOAT_TO_LONG.S */ 3802@include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3803/* File: armv5te/unopWider.S */ 3804 /* 3805 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3806 * that specifies an instruction that performs "result = op r0", where 3807 * "result" is a 64-bit quantity in r0/r1. 3808 * 3809 * For: int-to-long, int-to-double, float-to-long, float-to-double 3810 */ 3811 /* unop vA, vB */ 3812 mov r9, rINST, lsr #8 @ r9<- A+ 3813 mov r3, rINST, lsr #12 @ r3<- B 3814 and r9, r9, #15 3815 GET_VREG(r0, r3) @ r0<- vB 3816 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3817 @ optional op; may set condition codes 3818 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3819 bl f2l_doconv @ r0<- op, r0-r3 changed 3820 GET_INST_OPCODE(ip) @ extract opcode from rINST 3821 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3822 GOTO_OPCODE(ip) @ jump to next instruction 3823 /* 10-11 instructions */ 3824 3825 3826 3827/* ------------------------------ */ 3828 .balign 64 3829.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3830/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3831/* File: arm-vfp/funopWider.S */ 3832 /* 3833 * Generic 32bit-to-64bit floating point unary operation. Provide an 3834 * "instr" line that specifies an instruction that performs "d0 = op s0". 3835 * 3836 * For: int-to-double, float-to-double 3837 */ 3838 /* unop vA, vB */ 3839 mov r3, rINST, lsr #12 @ r3<- B 3840 mov r9, rINST, lsr #8 @ r9<- A+ 3841 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3842 flds s0, [r3] @ s0<- vB 3843 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3844 and r9, r9, #15 @ r9<- A 3845 fcvtds d0, s0 @ d0<- op 3846 GET_INST_OPCODE(ip) @ extract opcode from rINST 3847 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3848 fstd d0, [r9] @ vA<- d0 3849 GOTO_OPCODE(ip) @ jump to next instruction 3850 3851 3852/* ------------------------------ */ 3853 .balign 64 3854.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3855/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3856/* File: arm-vfp/funopNarrower.S */ 3857 /* 3858 * Generic 64bit-to-32bit unary floating point operation. Provide an 3859 * "instr" line that specifies an instruction that performs "s0 = op d0". 3860 * 3861 * For: double-to-int, double-to-float 3862 */ 3863 /* unop vA, vB */ 3864 mov r3, rINST, lsr #12 @ r3<- B 3865 mov r9, rINST, lsr #8 @ r9<- A+ 3866 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3867 fldd d0, [r3] @ d0<- vB 3868 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3869 and r9, r9, #15 @ r9<- A 3870 ftosizd s0, d0 @ s0<- op 3871 GET_INST_OPCODE(ip) @ extract opcode from rINST 3872 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3873 fsts s0, [r9] @ vA<- s0 3874 GOTO_OPCODE(ip) @ jump to next instruction 3875 3876 3877/* ------------------------------ */ 3878 .balign 64 3879.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3880/* File: armv5te/OP_DOUBLE_TO_LONG.S */ 3881@include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3882/* File: armv5te/unopWide.S */ 3883 /* 3884 * Generic 64-bit unary operation. Provide an "instr" line that 3885 * specifies an instruction that performs "result = op r0/r1". 3886 * This could be an ARM instruction or a function call. 3887 * 3888 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3889 */ 3890 /* unop vA, vB */ 3891 mov r9, rINST, lsr #8 @ r9<- A+ 3892 mov r3, rINST, lsr #12 @ r3<- B 3893 and r9, r9, #15 3894 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3895 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3896 ldmia r3, {r0-r1} @ r0/r1<- vAA 3897 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3898 @ optional op; may set condition codes 3899 bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3900 GET_INST_OPCODE(ip) @ extract opcode from rINST 3901 stmia r9, {r0-r1} @ vAA<- r0/r1 3902 GOTO_OPCODE(ip) @ jump to next instruction 3903 /* 12-13 instructions */ 3904 3905 3906 3907/* ------------------------------ */ 3908 .balign 64 3909.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3910/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3911/* File: arm-vfp/funopNarrower.S */ 3912 /* 3913 * Generic 64bit-to-32bit unary floating point operation. Provide an 3914 * "instr" line that specifies an instruction that performs "s0 = op d0". 3915 * 3916 * For: double-to-int, double-to-float 3917 */ 3918 /* unop vA, vB */ 3919 mov r3, rINST, lsr #12 @ r3<- B 3920 mov r9, rINST, lsr #8 @ r9<- A+ 3921 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3922 fldd d0, [r3] @ d0<- vB 3923 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3924 and r9, r9, #15 @ r9<- A 3925 fcvtsd s0, d0 @ s0<- op 3926 GET_INST_OPCODE(ip) @ extract opcode from rINST 3927 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3928 fsts s0, [r9] @ vA<- s0 3929 GOTO_OPCODE(ip) @ jump to next instruction 3930 3931 3932/* ------------------------------ */ 3933 .balign 64 3934.L_OP_INT_TO_BYTE: /* 0x8d */ 3935/* File: armv5te/OP_INT_TO_BYTE.S */ 3936/* File: armv5te/unop.S */ 3937 /* 3938 * Generic 32-bit unary operation. Provide an "instr" line that 3939 * specifies an instruction that performs "result = op r0". 3940 * This could be an ARM instruction or a function call. 3941 * 3942 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3943 * int-to-byte, int-to-char, int-to-short 3944 */ 3945 /* unop vA, vB */ 3946 mov r3, rINST, lsr #12 @ r3<- B 3947 mov r9, rINST, lsr #8 @ r9<- A+ 3948 GET_VREG(r0, r3) @ r0<- vB 3949 and r9, r9, #15 3950 mov r0, r0, asl #24 @ optional op; may set condition codes 3951 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3952 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 3953 GET_INST_OPCODE(ip) @ extract opcode from rINST 3954 SET_VREG(r0, r9) @ vAA<- r0 3955 GOTO_OPCODE(ip) @ jump to next instruction 3956 /* 9-10 instructions */ 3957 3958 3959/* ------------------------------ */ 3960 .balign 64 3961.L_OP_INT_TO_CHAR: /* 0x8e */ 3962/* File: armv5te/OP_INT_TO_CHAR.S */ 3963/* File: armv5te/unop.S */ 3964 /* 3965 * Generic 32-bit unary operation. Provide an "instr" line that 3966 * specifies an instruction that performs "result = op r0". 3967 * This could be an ARM instruction or a function call. 3968 * 3969 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3970 * int-to-byte, int-to-char, int-to-short 3971 */ 3972 /* unop vA, vB */ 3973 mov r3, rINST, lsr #12 @ r3<- B 3974 mov r9, rINST, lsr #8 @ r9<- A+ 3975 GET_VREG(r0, r3) @ r0<- vB 3976 and r9, r9, #15 3977 mov r0, r0, asl #16 @ optional op; may set condition codes 3978 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3979 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 3980 GET_INST_OPCODE(ip) @ extract opcode from rINST 3981 SET_VREG(r0, r9) @ vAA<- r0 3982 GOTO_OPCODE(ip) @ jump to next instruction 3983 /* 9-10 instructions */ 3984 3985 3986/* ------------------------------ */ 3987 .balign 64 3988.L_OP_INT_TO_SHORT: /* 0x8f */ 3989/* File: armv5te/OP_INT_TO_SHORT.S */ 3990/* File: armv5te/unop.S */ 3991 /* 3992 * Generic 32-bit unary operation. Provide an "instr" line that 3993 * specifies an instruction that performs "result = op r0". 3994 * This could be an ARM instruction or a function call. 3995 * 3996 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3997 * int-to-byte, int-to-char, int-to-short 3998 */ 3999 /* unop vA, vB */ 4000 mov r3, rINST, lsr #12 @ r3<- B 4001 mov r9, rINST, lsr #8 @ r9<- A+ 4002 GET_VREG(r0, r3) @ r0<- vB 4003 and r9, r9, #15 4004 mov r0, r0, asl #16 @ optional op; may set condition codes 4005 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4006 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 4007 GET_INST_OPCODE(ip) @ extract opcode from rINST 4008 SET_VREG(r0, r9) @ vAA<- r0 4009 GOTO_OPCODE(ip) @ jump to next instruction 4010 /* 9-10 instructions */ 4011 4012 4013/* ------------------------------ */ 4014 .balign 64 4015.L_OP_ADD_INT: /* 0x90 */ 4016/* File: armv5te/OP_ADD_INT.S */ 4017/* File: armv5te/binop.S */ 4018 /* 4019 * Generic 32-bit binary operation. Provide an "instr" line that 4020 * specifies an instruction that performs "result = r0 op r1". 4021 * This could be an ARM instruction or a function call. (If the result 4022 * comes back in a register other than r0, you can override "result".) 4023 * 4024 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4025 * vCC (r1). Useful for integer division and modulus. Note that we 4026 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4027 * handles it correctly. 4028 * 4029 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4030 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4031 * mul-float, div-float, rem-float 4032 */ 4033 /* binop vAA, vBB, vCC */ 4034 FETCH(r0, 1) @ r0<- CCBB 4035 mov r9, rINST, lsr #8 @ r9<- AA 4036 mov r3, r0, lsr #8 @ r3<- CC 4037 and r2, r0, #255 @ r2<- BB 4038 GET_VREG(r1, r3) @ r1<- vCC 4039 GET_VREG(r0, r2) @ r0<- vBB 4040 .if 0 4041 cmp r1, #0 @ is second operand zero? 4042 beq common_errDivideByZero 4043 .endif 4044 4045 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4046 @ optional op; may set condition codes 4047 add r0, r0, r1 @ r0<- op, r0-r3 changed 4048 GET_INST_OPCODE(ip) @ extract opcode from rINST 4049 SET_VREG(r0, r9) @ vAA<- r0 4050 GOTO_OPCODE(ip) @ jump to next instruction 4051 /* 11-14 instructions */ 4052 4053 4054/* ------------------------------ */ 4055 .balign 64 4056.L_OP_SUB_INT: /* 0x91 */ 4057/* File: armv5te/OP_SUB_INT.S */ 4058/* File: armv5te/binop.S */ 4059 /* 4060 * Generic 32-bit binary operation. Provide an "instr" line that 4061 * specifies an instruction that performs "result = r0 op r1". 4062 * This could be an ARM instruction or a function call. (If the result 4063 * comes back in a register other than r0, you can override "result".) 4064 * 4065 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4066 * vCC (r1). Useful for integer division and modulus. Note that we 4067 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4068 * handles it correctly. 4069 * 4070 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4071 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4072 * mul-float, div-float, rem-float 4073 */ 4074 /* binop vAA, vBB, vCC */ 4075 FETCH(r0, 1) @ r0<- CCBB 4076 mov r9, rINST, lsr #8 @ r9<- AA 4077 mov r3, r0, lsr #8 @ r3<- CC 4078 and r2, r0, #255 @ r2<- BB 4079 GET_VREG(r1, r3) @ r1<- vCC 4080 GET_VREG(r0, r2) @ r0<- vBB 4081 .if 0 4082 cmp r1, #0 @ is second operand zero? 4083 beq common_errDivideByZero 4084 .endif 4085 4086 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4087 @ optional op; may set condition codes 4088 sub r0, r0, r1 @ r0<- op, r0-r3 changed 4089 GET_INST_OPCODE(ip) @ extract opcode from rINST 4090 SET_VREG(r0, r9) @ vAA<- r0 4091 GOTO_OPCODE(ip) @ jump to next instruction 4092 /* 11-14 instructions */ 4093 4094 4095/* ------------------------------ */ 4096 .balign 64 4097.L_OP_MUL_INT: /* 0x92 */ 4098/* File: armv5te/OP_MUL_INT.S */ 4099/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4100/* File: armv5te/binop.S */ 4101 /* 4102 * Generic 32-bit binary operation. Provide an "instr" line that 4103 * specifies an instruction that performs "result = r0 op r1". 4104 * This could be an ARM instruction or a function call. (If the result 4105 * comes back in a register other than r0, you can override "result".) 4106 * 4107 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4108 * vCC (r1). Useful for integer division and modulus. Note that we 4109 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4110 * handles it correctly. 4111 * 4112 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4113 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4114 * mul-float, div-float, rem-float 4115 */ 4116 /* binop vAA, vBB, vCC */ 4117 FETCH(r0, 1) @ r0<- CCBB 4118 mov r9, rINST, lsr #8 @ r9<- AA 4119 mov r3, r0, lsr #8 @ r3<- CC 4120 and r2, r0, #255 @ r2<- BB 4121 GET_VREG(r1, r3) @ r1<- vCC 4122 GET_VREG(r0, r2) @ r0<- vBB 4123 .if 0 4124 cmp r1, #0 @ is second operand zero? 4125 beq common_errDivideByZero 4126 .endif 4127 4128 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4129 @ optional op; may set condition codes 4130 mul r0, r1, r0 @ r0<- op, r0-r3 changed 4131 GET_INST_OPCODE(ip) @ extract opcode from rINST 4132 SET_VREG(r0, r9) @ vAA<- r0 4133 GOTO_OPCODE(ip) @ jump to next instruction 4134 /* 11-14 instructions */ 4135 4136 4137/* ------------------------------ */ 4138 .balign 64 4139.L_OP_DIV_INT: /* 0x93 */ 4140/* File: armv5te/OP_DIV_INT.S */ 4141/* File: armv5te/binop.S */ 4142 /* 4143 * Generic 32-bit binary operation. Provide an "instr" line that 4144 * specifies an instruction that performs "result = r0 op r1". 4145 * This could be an ARM instruction or a function call. (If the result 4146 * comes back in a register other than r0, you can override "result".) 4147 * 4148 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4149 * vCC (r1). Useful for integer division and modulus. Note that we 4150 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4151 * handles it correctly. 4152 * 4153 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4154 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4155 * mul-float, div-float, rem-float 4156 */ 4157 /* binop vAA, vBB, vCC */ 4158 FETCH(r0, 1) @ r0<- CCBB 4159 mov r9, rINST, lsr #8 @ r9<- AA 4160 mov r3, r0, lsr #8 @ r3<- CC 4161 and r2, r0, #255 @ r2<- BB 4162 GET_VREG(r1, r3) @ r1<- vCC 4163 GET_VREG(r0, r2) @ r0<- vBB 4164 .if 1 4165 cmp r1, #0 @ is second operand zero? 4166 beq common_errDivideByZero 4167 .endif 4168 4169 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4170 @ optional op; may set condition codes 4171 bl __aeabi_idiv @ r0<- op, r0-r3 changed 4172 GET_INST_OPCODE(ip) @ extract opcode from rINST 4173 SET_VREG(r0, r9) @ vAA<- r0 4174 GOTO_OPCODE(ip) @ jump to next instruction 4175 /* 11-14 instructions */ 4176 4177 4178/* ------------------------------ */ 4179 .balign 64 4180.L_OP_REM_INT: /* 0x94 */ 4181/* File: armv5te/OP_REM_INT.S */ 4182/* idivmod returns quotient in r0 and remainder in r1 */ 4183/* File: armv5te/binop.S */ 4184 /* 4185 * Generic 32-bit binary operation. Provide an "instr" line that 4186 * specifies an instruction that performs "result = r0 op r1". 4187 * This could be an ARM instruction or a function call. (If the result 4188 * comes back in a register other than r0, you can override "result".) 4189 * 4190 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4191 * vCC (r1). Useful for integer division and modulus. Note that we 4192 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4193 * handles it correctly. 4194 * 4195 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4196 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4197 * mul-float, div-float, rem-float 4198 */ 4199 /* binop vAA, vBB, vCC */ 4200 FETCH(r0, 1) @ r0<- CCBB 4201 mov r9, rINST, lsr #8 @ r9<- AA 4202 mov r3, r0, lsr #8 @ r3<- CC 4203 and r2, r0, #255 @ r2<- BB 4204 GET_VREG(r1, r3) @ r1<- vCC 4205 GET_VREG(r0, r2) @ r0<- vBB 4206 .if 1 4207 cmp r1, #0 @ is second operand zero? 4208 beq common_errDivideByZero 4209 .endif 4210 4211 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4212 @ optional op; may set condition codes 4213 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4214 GET_INST_OPCODE(ip) @ extract opcode from rINST 4215 SET_VREG(r1, r9) @ vAA<- r1 4216 GOTO_OPCODE(ip) @ jump to next instruction 4217 /* 11-14 instructions */ 4218 4219 4220/* ------------------------------ */ 4221 .balign 64 4222.L_OP_AND_INT: /* 0x95 */ 4223/* File: armv5te/OP_AND_INT.S */ 4224/* File: armv5te/binop.S */ 4225 /* 4226 * Generic 32-bit binary operation. Provide an "instr" line that 4227 * specifies an instruction that performs "result = r0 op r1". 4228 * This could be an ARM instruction or a function call. (If the result 4229 * comes back in a register other than r0, you can override "result".) 4230 * 4231 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4232 * vCC (r1). Useful for integer division and modulus. Note that we 4233 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4234 * handles it correctly. 4235 * 4236 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4237 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4238 * mul-float, div-float, rem-float 4239 */ 4240 /* binop vAA, vBB, vCC */ 4241 FETCH(r0, 1) @ r0<- CCBB 4242 mov r9, rINST, lsr #8 @ r9<- AA 4243 mov r3, r0, lsr #8 @ r3<- CC 4244 and r2, r0, #255 @ r2<- BB 4245 GET_VREG(r1, r3) @ r1<- vCC 4246 GET_VREG(r0, r2) @ r0<- vBB 4247 .if 0 4248 cmp r1, #0 @ is second operand zero? 4249 beq common_errDivideByZero 4250 .endif 4251 4252 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4253 @ optional op; may set condition codes 4254 and r0, r0, r1 @ r0<- op, r0-r3 changed 4255 GET_INST_OPCODE(ip) @ extract opcode from rINST 4256 SET_VREG(r0, r9) @ vAA<- r0 4257 GOTO_OPCODE(ip) @ jump to next instruction 4258 /* 11-14 instructions */ 4259 4260 4261/* ------------------------------ */ 4262 .balign 64 4263.L_OP_OR_INT: /* 0x96 */ 4264/* File: armv5te/OP_OR_INT.S */ 4265/* File: armv5te/binop.S */ 4266 /* 4267 * Generic 32-bit binary operation. Provide an "instr" line that 4268 * specifies an instruction that performs "result = r0 op r1". 4269 * This could be an ARM instruction or a function call. (If the result 4270 * comes back in a register other than r0, you can override "result".) 4271 * 4272 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4273 * vCC (r1). Useful for integer division and modulus. Note that we 4274 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4275 * handles it correctly. 4276 * 4277 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4278 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4279 * mul-float, div-float, rem-float 4280 */ 4281 /* binop vAA, vBB, vCC */ 4282 FETCH(r0, 1) @ r0<- CCBB 4283 mov r9, rINST, lsr #8 @ r9<- AA 4284 mov r3, r0, lsr #8 @ r3<- CC 4285 and r2, r0, #255 @ r2<- BB 4286 GET_VREG(r1, r3) @ r1<- vCC 4287 GET_VREG(r0, r2) @ r0<- vBB 4288 .if 0 4289 cmp r1, #0 @ is second operand zero? 4290 beq common_errDivideByZero 4291 .endif 4292 4293 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4294 @ optional op; may set condition codes 4295 orr r0, r0, r1 @ r0<- op, r0-r3 changed 4296 GET_INST_OPCODE(ip) @ extract opcode from rINST 4297 SET_VREG(r0, r9) @ vAA<- r0 4298 GOTO_OPCODE(ip) @ jump to next instruction 4299 /* 11-14 instructions */ 4300 4301 4302/* ------------------------------ */ 4303 .balign 64 4304.L_OP_XOR_INT: /* 0x97 */ 4305/* File: armv5te/OP_XOR_INT.S */ 4306/* File: armv5te/binop.S */ 4307 /* 4308 * Generic 32-bit binary operation. Provide an "instr" line that 4309 * specifies an instruction that performs "result = r0 op r1". 4310 * This could be an ARM instruction or a function call. (If the result 4311 * comes back in a register other than r0, you can override "result".) 4312 * 4313 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4314 * vCC (r1). Useful for integer division and modulus. Note that we 4315 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4316 * handles it correctly. 4317 * 4318 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4319 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4320 * mul-float, div-float, rem-float 4321 */ 4322 /* binop vAA, vBB, vCC */ 4323 FETCH(r0, 1) @ r0<- CCBB 4324 mov r9, rINST, lsr #8 @ r9<- AA 4325 mov r3, r0, lsr #8 @ r3<- CC 4326 and r2, r0, #255 @ r2<- BB 4327 GET_VREG(r1, r3) @ r1<- vCC 4328 GET_VREG(r0, r2) @ r0<- vBB 4329 .if 0 4330 cmp r1, #0 @ is second operand zero? 4331 beq common_errDivideByZero 4332 .endif 4333 4334 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4335 @ optional op; may set condition codes 4336 eor r0, r0, r1 @ r0<- op, r0-r3 changed 4337 GET_INST_OPCODE(ip) @ extract opcode from rINST 4338 SET_VREG(r0, r9) @ vAA<- r0 4339 GOTO_OPCODE(ip) @ jump to next instruction 4340 /* 11-14 instructions */ 4341 4342 4343/* ------------------------------ */ 4344 .balign 64 4345.L_OP_SHL_INT: /* 0x98 */ 4346/* File: armv5te/OP_SHL_INT.S */ 4347/* File: armv5te/binop.S */ 4348 /* 4349 * Generic 32-bit binary operation. Provide an "instr" line that 4350 * specifies an instruction that performs "result = r0 op r1". 4351 * This could be an ARM instruction or a function call. (If the result 4352 * comes back in a register other than r0, you can override "result".) 4353 * 4354 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4355 * vCC (r1). Useful for integer division and modulus. Note that we 4356 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4357 * handles it correctly. 4358 * 4359 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4360 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4361 * mul-float, div-float, rem-float 4362 */ 4363 /* binop vAA, vBB, vCC */ 4364 FETCH(r0, 1) @ r0<- CCBB 4365 mov r9, rINST, lsr #8 @ r9<- AA 4366 mov r3, r0, lsr #8 @ r3<- CC 4367 and r2, r0, #255 @ r2<- BB 4368 GET_VREG(r1, r3) @ r1<- vCC 4369 GET_VREG(r0, r2) @ r0<- vBB 4370 .if 0 4371 cmp r1, #0 @ is second operand zero? 4372 beq common_errDivideByZero 4373 .endif 4374 4375 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4376 and r1, r1, #31 @ optional op; may set condition codes 4377 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4378 GET_INST_OPCODE(ip) @ extract opcode from rINST 4379 SET_VREG(r0, r9) @ vAA<- r0 4380 GOTO_OPCODE(ip) @ jump to next instruction 4381 /* 11-14 instructions */ 4382 4383 4384/* ------------------------------ */ 4385 .balign 64 4386.L_OP_SHR_INT: /* 0x99 */ 4387/* File: armv5te/OP_SHR_INT.S */ 4388/* File: armv5te/binop.S */ 4389 /* 4390 * Generic 32-bit binary operation. Provide an "instr" line that 4391 * specifies an instruction that performs "result = r0 op r1". 4392 * This could be an ARM instruction or a function call. (If the result 4393 * comes back in a register other than r0, you can override "result".) 4394 * 4395 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4396 * vCC (r1). Useful for integer division and modulus. Note that we 4397 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4398 * handles it correctly. 4399 * 4400 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4401 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4402 * mul-float, div-float, rem-float 4403 */ 4404 /* binop vAA, vBB, vCC */ 4405 FETCH(r0, 1) @ r0<- CCBB 4406 mov r9, rINST, lsr #8 @ r9<- AA 4407 mov r3, r0, lsr #8 @ r3<- CC 4408 and r2, r0, #255 @ r2<- BB 4409 GET_VREG(r1, r3) @ r1<- vCC 4410 GET_VREG(r0, r2) @ r0<- vBB 4411 .if 0 4412 cmp r1, #0 @ is second operand zero? 4413 beq common_errDivideByZero 4414 .endif 4415 4416 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4417 and r1, r1, #31 @ optional op; may set condition codes 4418 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4419 GET_INST_OPCODE(ip) @ extract opcode from rINST 4420 SET_VREG(r0, r9) @ vAA<- r0 4421 GOTO_OPCODE(ip) @ jump to next instruction 4422 /* 11-14 instructions */ 4423 4424 4425/* ------------------------------ */ 4426 .balign 64 4427.L_OP_USHR_INT: /* 0x9a */ 4428/* File: armv5te/OP_USHR_INT.S */ 4429/* File: armv5te/binop.S */ 4430 /* 4431 * Generic 32-bit binary operation. Provide an "instr" line that 4432 * specifies an instruction that performs "result = r0 op r1". 4433 * This could be an ARM instruction or a function call. (If the result 4434 * comes back in a register other than r0, you can override "result".) 4435 * 4436 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4437 * vCC (r1). Useful for integer division and modulus. Note that we 4438 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4439 * handles it correctly. 4440 * 4441 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4442 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4443 * mul-float, div-float, rem-float 4444 */ 4445 /* binop vAA, vBB, vCC */ 4446 FETCH(r0, 1) @ r0<- CCBB 4447 mov r9, rINST, lsr #8 @ r9<- AA 4448 mov r3, r0, lsr #8 @ r3<- CC 4449 and r2, r0, #255 @ r2<- BB 4450 GET_VREG(r1, r3) @ r1<- vCC 4451 GET_VREG(r0, r2) @ r0<- vBB 4452 .if 0 4453 cmp r1, #0 @ is second operand zero? 4454 beq common_errDivideByZero 4455 .endif 4456 4457 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4458 and r1, r1, #31 @ optional op; may set condition codes 4459 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4460 GET_INST_OPCODE(ip) @ extract opcode from rINST 4461 SET_VREG(r0, r9) @ vAA<- r0 4462 GOTO_OPCODE(ip) @ jump to next instruction 4463 /* 11-14 instructions */ 4464 4465 4466/* ------------------------------ */ 4467 .balign 64 4468.L_OP_ADD_LONG: /* 0x9b */ 4469/* File: armv5te/OP_ADD_LONG.S */ 4470/* File: armv5te/binopWide.S */ 4471 /* 4472 * Generic 64-bit binary operation. Provide an "instr" line that 4473 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4474 * This could be an ARM instruction or a function call. (If the result 4475 * comes back in a register other than r0, you can override "result".) 4476 * 4477 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4478 * vCC (r1). Useful for integer division and modulus. 4479 * 4480 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4481 * xor-long, add-double, sub-double, mul-double, div-double, 4482 * rem-double 4483 * 4484 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4485 */ 4486 /* binop vAA, vBB, vCC */ 4487 FETCH(r0, 1) @ r0<- CCBB 4488 mov r9, rINST, lsr #8 @ r9<- AA 4489 and r2, r0, #255 @ r2<- BB 4490 mov r3, r0, lsr #8 @ r3<- CC 4491 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4492 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4493 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4494 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4495 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4496 .if 0 4497 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4498 beq common_errDivideByZero 4499 .endif 4500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4501 4502 adds r0, r0, r2 @ optional op; may set condition codes 4503 adc r1, r1, r3 @ result<- op, r0-r3 changed 4504 GET_INST_OPCODE(ip) @ extract opcode from rINST 4505 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4506 GOTO_OPCODE(ip) @ jump to next instruction 4507 /* 14-17 instructions */ 4508 4509 4510/* ------------------------------ */ 4511 .balign 64 4512.L_OP_SUB_LONG: /* 0x9c */ 4513/* File: armv5te/OP_SUB_LONG.S */ 4514/* File: armv5te/binopWide.S */ 4515 /* 4516 * Generic 64-bit binary operation. Provide an "instr" line that 4517 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4518 * This could be an ARM instruction or a function call. (If the result 4519 * comes back in a register other than r0, you can override "result".) 4520 * 4521 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4522 * vCC (r1). Useful for integer division and modulus. 4523 * 4524 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4525 * xor-long, add-double, sub-double, mul-double, div-double, 4526 * rem-double 4527 * 4528 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4529 */ 4530 /* binop vAA, vBB, vCC */ 4531 FETCH(r0, 1) @ r0<- CCBB 4532 mov r9, rINST, lsr #8 @ r9<- AA 4533 and r2, r0, #255 @ r2<- BB 4534 mov r3, r0, lsr #8 @ r3<- CC 4535 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4536 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4537 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4538 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4539 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4540 .if 0 4541 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4542 beq common_errDivideByZero 4543 .endif 4544 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4545 4546 subs r0, r0, r2 @ optional op; may set condition codes 4547 sbc r1, r1, r3 @ result<- op, r0-r3 changed 4548 GET_INST_OPCODE(ip) @ extract opcode from rINST 4549 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4550 GOTO_OPCODE(ip) @ jump to next instruction 4551 /* 14-17 instructions */ 4552 4553 4554/* ------------------------------ */ 4555 .balign 64 4556.L_OP_MUL_LONG: /* 0x9d */ 4557/* File: armv5te/OP_MUL_LONG.S */ 4558 /* 4559 * Signed 64-bit integer multiply. 4560 * 4561 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4562 * WX 4563 * x YZ 4564 * -------- 4565 * ZW ZX 4566 * YW YX 4567 * 4568 * The low word of the result holds ZX, the high word holds 4569 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4570 * it doesn't fit in the low 64 bits. 4571 * 4572 * Unlike most ARM math operations, multiply instructions have 4573 * restrictions on using the same register more than once (Rd and Rm 4574 * cannot be the same). 4575 */ 4576 /* mul-long vAA, vBB, vCC */ 4577 FETCH(r0, 1) @ r0<- CCBB 4578 and r2, r0, #255 @ r2<- BB 4579 mov r3, r0, lsr #8 @ r3<- CC 4580 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4581 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4582 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4583 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4584 mul ip, r2, r1 @ ip<- ZxW 4585 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4586 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4587 mov r0, rINST, lsr #8 @ r0<- AA 4588 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4589 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4590 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4591 b .LOP_MUL_LONG_finish 4592 4593/* ------------------------------ */ 4594 .balign 64 4595.L_OP_DIV_LONG: /* 0x9e */ 4596/* File: armv5te/OP_DIV_LONG.S */ 4597/* File: armv5te/binopWide.S */ 4598 /* 4599 * Generic 64-bit binary operation. Provide an "instr" line that 4600 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4601 * This could be an ARM instruction or a function call. (If the result 4602 * comes back in a register other than r0, you can override "result".) 4603 * 4604 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4605 * vCC (r1). Useful for integer division and modulus. 4606 * 4607 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4608 * xor-long, add-double, sub-double, mul-double, div-double, 4609 * rem-double 4610 * 4611 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4612 */ 4613 /* binop vAA, vBB, vCC */ 4614 FETCH(r0, 1) @ r0<- CCBB 4615 mov r9, rINST, lsr #8 @ r9<- AA 4616 and r2, r0, #255 @ r2<- BB 4617 mov r3, r0, lsr #8 @ r3<- CC 4618 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4619 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4620 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4621 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4622 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4623 .if 1 4624 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4625 beq common_errDivideByZero 4626 .endif 4627 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4628 4629 @ optional op; may set condition codes 4630 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4631 GET_INST_OPCODE(ip) @ extract opcode from rINST 4632 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4633 GOTO_OPCODE(ip) @ jump to next instruction 4634 /* 14-17 instructions */ 4635 4636 4637/* ------------------------------ */ 4638 .balign 64 4639.L_OP_REM_LONG: /* 0x9f */ 4640/* File: armv5te/OP_REM_LONG.S */ 4641/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4642/* File: armv5te/binopWide.S */ 4643 /* 4644 * Generic 64-bit binary operation. Provide an "instr" line that 4645 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4646 * This could be an ARM instruction or a function call. (If the result 4647 * comes back in a register other than r0, you can override "result".) 4648 * 4649 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4650 * vCC (r1). Useful for integer division and modulus. 4651 * 4652 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4653 * xor-long, add-double, sub-double, mul-double, div-double, 4654 * rem-double 4655 * 4656 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4657 */ 4658 /* binop vAA, vBB, vCC */ 4659 FETCH(r0, 1) @ r0<- CCBB 4660 mov r9, rINST, lsr #8 @ r9<- AA 4661 and r2, r0, #255 @ r2<- BB 4662 mov r3, r0, lsr #8 @ r3<- CC 4663 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4664 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4665 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4666 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4667 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4668 .if 1 4669 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4670 beq common_errDivideByZero 4671 .endif 4672 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4673 4674 @ optional op; may set condition codes 4675 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4676 GET_INST_OPCODE(ip) @ extract opcode from rINST 4677 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4678 GOTO_OPCODE(ip) @ jump to next instruction 4679 /* 14-17 instructions */ 4680 4681 4682/* ------------------------------ */ 4683 .balign 64 4684.L_OP_AND_LONG: /* 0xa0 */ 4685/* File: armv5te/OP_AND_LONG.S */ 4686/* File: armv5te/binopWide.S */ 4687 /* 4688 * Generic 64-bit binary operation. Provide an "instr" line that 4689 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4690 * This could be an ARM instruction or a function call. (If the result 4691 * comes back in a register other than r0, you can override "result".) 4692 * 4693 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4694 * vCC (r1). Useful for integer division and modulus. 4695 * 4696 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4697 * xor-long, add-double, sub-double, mul-double, div-double, 4698 * rem-double 4699 * 4700 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4701 */ 4702 /* binop vAA, vBB, vCC */ 4703 FETCH(r0, 1) @ r0<- CCBB 4704 mov r9, rINST, lsr #8 @ r9<- AA 4705 and r2, r0, #255 @ r2<- BB 4706 mov r3, r0, lsr #8 @ r3<- CC 4707 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4708 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4709 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4710 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4711 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4712 .if 0 4713 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4714 beq common_errDivideByZero 4715 .endif 4716 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4717 4718 and r0, r0, r2 @ optional op; may set condition codes 4719 and r1, r1, r3 @ result<- op, r0-r3 changed 4720 GET_INST_OPCODE(ip) @ extract opcode from rINST 4721 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4722 GOTO_OPCODE(ip) @ jump to next instruction 4723 /* 14-17 instructions */ 4724 4725 4726/* ------------------------------ */ 4727 .balign 64 4728.L_OP_OR_LONG: /* 0xa1 */ 4729/* File: armv5te/OP_OR_LONG.S */ 4730/* File: armv5te/binopWide.S */ 4731 /* 4732 * Generic 64-bit binary operation. Provide an "instr" line that 4733 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4734 * This could be an ARM instruction or a function call. (If the result 4735 * comes back in a register other than r0, you can override "result".) 4736 * 4737 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4738 * vCC (r1). Useful for integer division and modulus. 4739 * 4740 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4741 * xor-long, add-double, sub-double, mul-double, div-double, 4742 * rem-double 4743 * 4744 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4745 */ 4746 /* binop vAA, vBB, vCC */ 4747 FETCH(r0, 1) @ r0<- CCBB 4748 mov r9, rINST, lsr #8 @ r9<- AA 4749 and r2, r0, #255 @ r2<- BB 4750 mov r3, r0, lsr #8 @ r3<- CC 4751 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4752 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4753 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4754 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4755 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4756 .if 0 4757 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4758 beq common_errDivideByZero 4759 .endif 4760 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4761 4762 orr r0, r0, r2 @ optional op; may set condition codes 4763 orr r1, r1, r3 @ result<- op, r0-r3 changed 4764 GET_INST_OPCODE(ip) @ extract opcode from rINST 4765 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4766 GOTO_OPCODE(ip) @ jump to next instruction 4767 /* 14-17 instructions */ 4768 4769 4770/* ------------------------------ */ 4771 .balign 64 4772.L_OP_XOR_LONG: /* 0xa2 */ 4773/* File: armv5te/OP_XOR_LONG.S */ 4774/* File: armv5te/binopWide.S */ 4775 /* 4776 * Generic 64-bit binary operation. Provide an "instr" line that 4777 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4778 * This could be an ARM instruction or a function call. (If the result 4779 * comes back in a register other than r0, you can override "result".) 4780 * 4781 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4782 * vCC (r1). Useful for integer division and modulus. 4783 * 4784 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4785 * xor-long, add-double, sub-double, mul-double, div-double, 4786 * rem-double 4787 * 4788 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4789 */ 4790 /* binop vAA, vBB, vCC */ 4791 FETCH(r0, 1) @ r0<- CCBB 4792 mov r9, rINST, lsr #8 @ r9<- AA 4793 and r2, r0, #255 @ r2<- BB 4794 mov r3, r0, lsr #8 @ r3<- CC 4795 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4796 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4797 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4798 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4799 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4800 .if 0 4801 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4802 beq common_errDivideByZero 4803 .endif 4804 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4805 4806 eor r0, r0, r2 @ optional op; may set condition codes 4807 eor r1, r1, r3 @ result<- op, r0-r3 changed 4808 GET_INST_OPCODE(ip) @ extract opcode from rINST 4809 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4810 GOTO_OPCODE(ip) @ jump to next instruction 4811 /* 14-17 instructions */ 4812 4813 4814/* ------------------------------ */ 4815 .balign 64 4816.L_OP_SHL_LONG: /* 0xa3 */ 4817/* File: armv5te/OP_SHL_LONG.S */ 4818 /* 4819 * Long integer shift. This is different from the generic 32/64-bit 4820 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4821 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4822 * 6 bits of the shift distance. 4823 */ 4824 /* shl-long vAA, vBB, vCC */ 4825 FETCH(r0, 1) @ r0<- CCBB 4826 mov r9, rINST, lsr #8 @ r9<- AA 4827 and r3, r0, #255 @ r3<- BB 4828 mov r0, r0, lsr #8 @ r0<- CC 4829 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4830 GET_VREG(r2, r0) @ r2<- vCC 4831 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4832 and r2, r2, #63 @ r2<- r2 & 0x3f 4833 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4834 4835 mov r1, r1, asl r2 @ r1<- r1 << r2 4836 rsb r3, r2, #32 @ r3<- 32 - r2 4837 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4838 subs ip, r2, #32 @ ip<- r2 - 32 4839 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4840 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4841 b .LOP_SHL_LONG_finish 4842 4843/* ------------------------------ */ 4844 .balign 64 4845.L_OP_SHR_LONG: /* 0xa4 */ 4846/* File: armv5te/OP_SHR_LONG.S */ 4847 /* 4848 * Long integer shift. This is different from the generic 32/64-bit 4849 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4850 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4851 * 6 bits of the shift distance. 4852 */ 4853 /* shr-long vAA, vBB, vCC */ 4854 FETCH(r0, 1) @ r0<- CCBB 4855 mov r9, rINST, lsr #8 @ r9<- AA 4856 and r3, r0, #255 @ r3<- BB 4857 mov r0, r0, lsr #8 @ r0<- CC 4858 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4859 GET_VREG(r2, r0) @ r2<- vCC 4860 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4861 and r2, r2, #63 @ r0<- r0 & 0x3f 4862 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4863 4864 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4865 rsb r3, r2, #32 @ r3<- 32 - r2 4866 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4867 subs ip, r2, #32 @ ip<- r2 - 32 4868 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4869 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4870 b .LOP_SHR_LONG_finish 4871 4872/* ------------------------------ */ 4873 .balign 64 4874.L_OP_USHR_LONG: /* 0xa5 */ 4875/* File: armv5te/OP_USHR_LONG.S */ 4876 /* 4877 * Long integer shift. This is different from the generic 32/64-bit 4878 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4879 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4880 * 6 bits of the shift distance. 4881 */ 4882 /* ushr-long vAA, vBB, vCC */ 4883 FETCH(r0, 1) @ r0<- CCBB 4884 mov r9, rINST, lsr #8 @ r9<- AA 4885 and r3, r0, #255 @ r3<- BB 4886 mov r0, r0, lsr #8 @ r0<- CC 4887 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4888 GET_VREG(r2, r0) @ r2<- vCC 4889 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4890 and r2, r2, #63 @ r0<- r0 & 0x3f 4891 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4892 4893 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4894 rsb r3, r2, #32 @ r3<- 32 - r2 4895 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4896 subs ip, r2, #32 @ ip<- r2 - 32 4897 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4898 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4899 b .LOP_USHR_LONG_finish 4900 4901/* ------------------------------ */ 4902 .balign 64 4903.L_OP_ADD_FLOAT: /* 0xa6 */ 4904/* File: arm-vfp/OP_ADD_FLOAT.S */ 4905/* File: arm-vfp/fbinop.S */ 4906 /* 4907 * Generic 32-bit floating-point operation. Provide an "instr" line that 4908 * specifies an instruction that performs "s2 = s0 op s1". Because we 4909 * use the "softfp" ABI, this must be an instruction, not a function call. 4910 * 4911 * For: add-float, sub-float, mul-float, div-float 4912 */ 4913 /* floatop vAA, vBB, vCC */ 4914 FETCH(r0, 1) @ r0<- CCBB 4915 mov r9, rINST, lsr #8 @ r9<- AA 4916 mov r3, r0, lsr #8 @ r3<- CC 4917 and r2, r0, #255 @ r2<- BB 4918 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4919 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4920 flds s1, [r3] @ s1<- vCC 4921 flds s0, [r2] @ s0<- vBB 4922 4923 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4924 fadds s2, s0, s1 @ s2<- op 4925 GET_INST_OPCODE(ip) @ extract opcode from rINST 4926 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4927 fsts s2, [r9] @ vAA<- s2 4928 GOTO_OPCODE(ip) @ jump to next instruction 4929 4930 4931/* ------------------------------ */ 4932 .balign 64 4933.L_OP_SUB_FLOAT: /* 0xa7 */ 4934/* File: arm-vfp/OP_SUB_FLOAT.S */ 4935/* File: arm-vfp/fbinop.S */ 4936 /* 4937 * Generic 32-bit floating-point operation. Provide an "instr" line that 4938 * specifies an instruction that performs "s2 = s0 op s1". Because we 4939 * use the "softfp" ABI, this must be an instruction, not a function call. 4940 * 4941 * For: add-float, sub-float, mul-float, div-float 4942 */ 4943 /* floatop vAA, vBB, vCC */ 4944 FETCH(r0, 1) @ r0<- CCBB 4945 mov r9, rINST, lsr #8 @ r9<- AA 4946 mov r3, r0, lsr #8 @ r3<- CC 4947 and r2, r0, #255 @ r2<- BB 4948 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4949 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4950 flds s1, [r3] @ s1<- vCC 4951 flds s0, [r2] @ s0<- vBB 4952 4953 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4954 fsubs s2, s0, s1 @ s2<- op 4955 GET_INST_OPCODE(ip) @ extract opcode from rINST 4956 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4957 fsts s2, [r9] @ vAA<- s2 4958 GOTO_OPCODE(ip) @ jump to next instruction 4959 4960 4961/* ------------------------------ */ 4962 .balign 64 4963.L_OP_MUL_FLOAT: /* 0xa8 */ 4964/* File: arm-vfp/OP_MUL_FLOAT.S */ 4965/* File: arm-vfp/fbinop.S */ 4966 /* 4967 * Generic 32-bit floating-point operation. Provide an "instr" line that 4968 * specifies an instruction that performs "s2 = s0 op s1". Because we 4969 * use the "softfp" ABI, this must be an instruction, not a function call. 4970 * 4971 * For: add-float, sub-float, mul-float, div-float 4972 */ 4973 /* floatop vAA, vBB, vCC */ 4974 FETCH(r0, 1) @ r0<- CCBB 4975 mov r9, rINST, lsr #8 @ r9<- AA 4976 mov r3, r0, lsr #8 @ r3<- CC 4977 and r2, r0, #255 @ r2<- BB 4978 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4979 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4980 flds s1, [r3] @ s1<- vCC 4981 flds s0, [r2] @ s0<- vBB 4982 4983 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4984 fmuls s2, s0, s1 @ s2<- op 4985 GET_INST_OPCODE(ip) @ extract opcode from rINST 4986 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4987 fsts s2, [r9] @ vAA<- s2 4988 GOTO_OPCODE(ip) @ jump to next instruction 4989 4990 4991/* ------------------------------ */ 4992 .balign 64 4993.L_OP_DIV_FLOAT: /* 0xa9 */ 4994/* File: arm-vfp/OP_DIV_FLOAT.S */ 4995/* File: arm-vfp/fbinop.S */ 4996 /* 4997 * Generic 32-bit floating-point operation. Provide an "instr" line that 4998 * specifies an instruction that performs "s2 = s0 op s1". Because we 4999 * use the "softfp" ABI, this must be an instruction, not a function call. 5000 * 5001 * For: add-float, sub-float, mul-float, div-float 5002 */ 5003 /* floatop vAA, vBB, vCC */ 5004 FETCH(r0, 1) @ r0<- CCBB 5005 mov r9, rINST, lsr #8 @ r9<- AA 5006 mov r3, r0, lsr #8 @ r3<- CC 5007 and r2, r0, #255 @ r2<- BB 5008 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5009 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5010 flds s1, [r3] @ s1<- vCC 5011 flds s0, [r2] @ s0<- vBB 5012 5013 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5014 fdivs s2, s0, s1 @ s2<- op 5015 GET_INST_OPCODE(ip) @ extract opcode from rINST 5016 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5017 fsts s2, [r9] @ vAA<- s2 5018 GOTO_OPCODE(ip) @ jump to next instruction 5019 5020 5021/* ------------------------------ */ 5022 .balign 64 5023.L_OP_REM_FLOAT: /* 0xaa */ 5024/* File: armv5te/OP_REM_FLOAT.S */ 5025/* EABI doesn't define a float remainder function, but libm does */ 5026/* File: armv5te/binop.S */ 5027 /* 5028 * Generic 32-bit binary operation. Provide an "instr" line that 5029 * specifies an instruction that performs "result = r0 op r1". 5030 * This could be an ARM instruction or a function call. (If the result 5031 * comes back in a register other than r0, you can override "result".) 5032 * 5033 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5034 * vCC (r1). Useful for integer division and modulus. Note that we 5035 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5036 * handles it correctly. 5037 * 5038 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5039 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5040 * mul-float, div-float, rem-float 5041 */ 5042 /* binop vAA, vBB, vCC */ 5043 FETCH(r0, 1) @ r0<- CCBB 5044 mov r9, rINST, lsr #8 @ r9<- AA 5045 mov r3, r0, lsr #8 @ r3<- CC 5046 and r2, r0, #255 @ r2<- BB 5047 GET_VREG(r1, r3) @ r1<- vCC 5048 GET_VREG(r0, r2) @ r0<- vBB 5049 .if 0 5050 cmp r1, #0 @ is second operand zero? 5051 beq common_errDivideByZero 5052 .endif 5053 5054 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5055 @ optional op; may set condition codes 5056 bl fmodf @ r0<- op, r0-r3 changed 5057 GET_INST_OPCODE(ip) @ extract opcode from rINST 5058 SET_VREG(r0, r9) @ vAA<- r0 5059 GOTO_OPCODE(ip) @ jump to next instruction 5060 /* 11-14 instructions */ 5061 5062 5063/* ------------------------------ */ 5064 .balign 64 5065.L_OP_ADD_DOUBLE: /* 0xab */ 5066/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5067/* File: arm-vfp/fbinopWide.S */ 5068 /* 5069 * Generic 64-bit double-precision floating point binary operation. 5070 * Provide an "instr" line that specifies an instruction that performs 5071 * "d2 = d0 op d1". 5072 * 5073 * for: add-double, sub-double, mul-double, div-double 5074 */ 5075 /* doubleop vAA, vBB, vCC */ 5076 FETCH(r0, 1) @ r0<- CCBB 5077 mov r9, rINST, lsr #8 @ r9<- AA 5078 mov r3, r0, lsr #8 @ r3<- CC 5079 and r2, r0, #255 @ r2<- BB 5080 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5081 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5082 fldd d1, [r3] @ d1<- vCC 5083 fldd d0, [r2] @ d0<- vBB 5084 5085 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5086 faddd d2, d0, d1 @ s2<- op 5087 GET_INST_OPCODE(ip) @ extract opcode from rINST 5088 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5089 fstd d2, [r9] @ vAA<- d2 5090 GOTO_OPCODE(ip) @ jump to next instruction 5091 5092 5093/* ------------------------------ */ 5094 .balign 64 5095.L_OP_SUB_DOUBLE: /* 0xac */ 5096/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5097/* File: arm-vfp/fbinopWide.S */ 5098 /* 5099 * Generic 64-bit double-precision floating point binary operation. 5100 * Provide an "instr" line that specifies an instruction that performs 5101 * "d2 = d0 op d1". 5102 * 5103 * for: add-double, sub-double, mul-double, div-double 5104 */ 5105 /* doubleop vAA, vBB, vCC */ 5106 FETCH(r0, 1) @ r0<- CCBB 5107 mov r9, rINST, lsr #8 @ r9<- AA 5108 mov r3, r0, lsr #8 @ r3<- CC 5109 and r2, r0, #255 @ r2<- BB 5110 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5111 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5112 fldd d1, [r3] @ d1<- vCC 5113 fldd d0, [r2] @ d0<- vBB 5114 5115 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5116 fsubd d2, d0, d1 @ s2<- op 5117 GET_INST_OPCODE(ip) @ extract opcode from rINST 5118 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5119 fstd d2, [r9] @ vAA<- d2 5120 GOTO_OPCODE(ip) @ jump to next instruction 5121 5122 5123/* ------------------------------ */ 5124 .balign 64 5125.L_OP_MUL_DOUBLE: /* 0xad */ 5126/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5127/* File: arm-vfp/fbinopWide.S */ 5128 /* 5129 * Generic 64-bit double-precision floating point binary operation. 5130 * Provide an "instr" line that specifies an instruction that performs 5131 * "d2 = d0 op d1". 5132 * 5133 * for: add-double, sub-double, mul-double, div-double 5134 */ 5135 /* doubleop vAA, vBB, vCC */ 5136 FETCH(r0, 1) @ r0<- CCBB 5137 mov r9, rINST, lsr #8 @ r9<- AA 5138 mov r3, r0, lsr #8 @ r3<- CC 5139 and r2, r0, #255 @ r2<- BB 5140 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5141 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5142 fldd d1, [r3] @ d1<- vCC 5143 fldd d0, [r2] @ d0<- vBB 5144 5145 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5146 fmuld d2, d0, d1 @ s2<- op 5147 GET_INST_OPCODE(ip) @ extract opcode from rINST 5148 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5149 fstd d2, [r9] @ vAA<- d2 5150 GOTO_OPCODE(ip) @ jump to next instruction 5151 5152 5153/* ------------------------------ */ 5154 .balign 64 5155.L_OP_DIV_DOUBLE: /* 0xae */ 5156/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5157/* File: arm-vfp/fbinopWide.S */ 5158 /* 5159 * Generic 64-bit double-precision floating point binary operation. 5160 * Provide an "instr" line that specifies an instruction that performs 5161 * "d2 = d0 op d1". 5162 * 5163 * for: add-double, sub-double, mul-double, div-double 5164 */ 5165 /* doubleop vAA, vBB, vCC */ 5166 FETCH(r0, 1) @ r0<- CCBB 5167 mov r9, rINST, lsr #8 @ r9<- AA 5168 mov r3, r0, lsr #8 @ r3<- CC 5169 and r2, r0, #255 @ r2<- BB 5170 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5171 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5172 fldd d1, [r3] @ d1<- vCC 5173 fldd d0, [r2] @ d0<- vBB 5174 5175 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5176 fdivd d2, d0, d1 @ s2<- op 5177 GET_INST_OPCODE(ip) @ extract opcode from rINST 5178 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5179 fstd d2, [r9] @ vAA<- d2 5180 GOTO_OPCODE(ip) @ jump to next instruction 5181 5182 5183/* ------------------------------ */ 5184 .balign 64 5185.L_OP_REM_DOUBLE: /* 0xaf */ 5186/* File: armv5te/OP_REM_DOUBLE.S */ 5187/* EABI doesn't define a double remainder function, but libm does */ 5188/* File: armv5te/binopWide.S */ 5189 /* 5190 * Generic 64-bit binary operation. Provide an "instr" line that 5191 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5192 * This could be an ARM instruction or a function call. (If the result 5193 * comes back in a register other than r0, you can override "result".) 5194 * 5195 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5196 * vCC (r1). Useful for integer division and modulus. 5197 * 5198 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5199 * xor-long, add-double, sub-double, mul-double, div-double, 5200 * rem-double 5201 * 5202 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5203 */ 5204 /* binop vAA, vBB, vCC */ 5205 FETCH(r0, 1) @ r0<- CCBB 5206 mov r9, rINST, lsr #8 @ r9<- AA 5207 and r2, r0, #255 @ r2<- BB 5208 mov r3, r0, lsr #8 @ r3<- CC 5209 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5210 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5211 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5212 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5213 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5214 .if 0 5215 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5216 beq common_errDivideByZero 5217 .endif 5218 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5219 5220 @ optional op; may set condition codes 5221 bl fmod @ result<- op, r0-r3 changed 5222 GET_INST_OPCODE(ip) @ extract opcode from rINST 5223 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5224 GOTO_OPCODE(ip) @ jump to next instruction 5225 /* 14-17 instructions */ 5226 5227 5228/* ------------------------------ */ 5229 .balign 64 5230.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5231/* File: armv5te/OP_ADD_INT_2ADDR.S */ 5232/* File: armv5te/binop2addr.S */ 5233 /* 5234 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5235 * that specifies an instruction that performs "result = r0 op r1". 5236 * This could be an ARM instruction or a function call. (If the result 5237 * comes back in a register other than r0, you can override "result".) 5238 * 5239 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5240 * vCC (r1). Useful for integer division and modulus. 5241 * 5242 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5243 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5244 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5245 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5246 */ 5247 /* binop/2addr vA, vB */ 5248 mov r9, rINST, lsr #8 @ r9<- A+ 5249 mov r3, rINST, lsr #12 @ r3<- B 5250 and r9, r9, #15 5251 GET_VREG(r1, r3) @ r1<- vB 5252 GET_VREG(r0, r9) @ r0<- vA 5253 .if 0 5254 cmp r1, #0 @ is second operand zero? 5255 beq common_errDivideByZero 5256 .endif 5257 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5258 5259 @ optional op; may set condition codes 5260 add r0, r0, r1 @ r0<- op, r0-r3 changed 5261 GET_INST_OPCODE(ip) @ extract opcode from rINST 5262 SET_VREG(r0, r9) @ vAA<- r0 5263 GOTO_OPCODE(ip) @ jump to next instruction 5264 /* 10-13 instructions */ 5265 5266 5267/* ------------------------------ */ 5268 .balign 64 5269.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5270/* File: armv5te/OP_SUB_INT_2ADDR.S */ 5271/* File: armv5te/binop2addr.S */ 5272 /* 5273 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5274 * that specifies an instruction that performs "result = r0 op r1". 5275 * This could be an ARM instruction or a function call. (If the result 5276 * comes back in a register other than r0, you can override "result".) 5277 * 5278 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5279 * vCC (r1). Useful for integer division and modulus. 5280 * 5281 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5282 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5283 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5284 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5285 */ 5286 /* binop/2addr vA, vB */ 5287 mov r9, rINST, lsr #8 @ r9<- A+ 5288 mov r3, rINST, lsr #12 @ r3<- B 5289 and r9, r9, #15 5290 GET_VREG(r1, r3) @ r1<- vB 5291 GET_VREG(r0, r9) @ r0<- vA 5292 .if 0 5293 cmp r1, #0 @ is second operand zero? 5294 beq common_errDivideByZero 5295 .endif 5296 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5297 5298 @ optional op; may set condition codes 5299 sub r0, r0, r1 @ r0<- op, r0-r3 changed 5300 GET_INST_OPCODE(ip) @ extract opcode from rINST 5301 SET_VREG(r0, r9) @ vAA<- r0 5302 GOTO_OPCODE(ip) @ jump to next instruction 5303 /* 10-13 instructions */ 5304 5305 5306/* ------------------------------ */ 5307 .balign 64 5308.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5309/* File: armv5te/OP_MUL_INT_2ADDR.S */ 5310/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5311/* File: armv5te/binop2addr.S */ 5312 /* 5313 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5314 * that specifies an instruction that performs "result = r0 op r1". 5315 * This could be an ARM instruction or a function call. (If the result 5316 * comes back in a register other than r0, you can override "result".) 5317 * 5318 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5319 * vCC (r1). Useful for integer division and modulus. 5320 * 5321 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5322 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5323 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5324 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5325 */ 5326 /* binop/2addr vA, vB */ 5327 mov r9, rINST, lsr #8 @ r9<- A+ 5328 mov r3, rINST, lsr #12 @ r3<- B 5329 and r9, r9, #15 5330 GET_VREG(r1, r3) @ r1<- vB 5331 GET_VREG(r0, r9) @ r0<- vA 5332 .if 0 5333 cmp r1, #0 @ is second operand zero? 5334 beq common_errDivideByZero 5335 .endif 5336 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5337 5338 @ optional op; may set condition codes 5339 mul r0, r1, r0 @ r0<- op, r0-r3 changed 5340 GET_INST_OPCODE(ip) @ extract opcode from rINST 5341 SET_VREG(r0, r9) @ vAA<- r0 5342 GOTO_OPCODE(ip) @ jump to next instruction 5343 /* 10-13 instructions */ 5344 5345 5346/* ------------------------------ */ 5347 .balign 64 5348.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5349/* File: armv5te/OP_DIV_INT_2ADDR.S */ 5350/* File: armv5te/binop2addr.S */ 5351 /* 5352 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5353 * that specifies an instruction that performs "result = r0 op r1". 5354 * This could be an ARM instruction or a function call. (If the result 5355 * comes back in a register other than r0, you can override "result".) 5356 * 5357 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5358 * vCC (r1). Useful for integer division and modulus. 5359 * 5360 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5361 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5362 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5363 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5364 */ 5365 /* binop/2addr vA, vB */ 5366 mov r9, rINST, lsr #8 @ r9<- A+ 5367 mov r3, rINST, lsr #12 @ r3<- B 5368 and r9, r9, #15 5369 GET_VREG(r1, r3) @ r1<- vB 5370 GET_VREG(r0, r9) @ r0<- vA 5371 .if 1 5372 cmp r1, #0 @ is second operand zero? 5373 beq common_errDivideByZero 5374 .endif 5375 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5376 5377 @ optional op; may set condition codes 5378 bl __aeabi_idiv @ r0<- op, r0-r3 changed 5379 GET_INST_OPCODE(ip) @ extract opcode from rINST 5380 SET_VREG(r0, r9) @ vAA<- r0 5381 GOTO_OPCODE(ip) @ jump to next instruction 5382 /* 10-13 instructions */ 5383 5384 5385/* ------------------------------ */ 5386 .balign 64 5387.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5388/* File: armv5te/OP_REM_INT_2ADDR.S */ 5389/* idivmod returns quotient in r0 and remainder in r1 */ 5390/* File: armv5te/binop2addr.S */ 5391 /* 5392 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5393 * that specifies an instruction that performs "result = r0 op r1". 5394 * This could be an ARM instruction or a function call. (If the result 5395 * comes back in a register other than r0, you can override "result".) 5396 * 5397 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5398 * vCC (r1). Useful for integer division and modulus. 5399 * 5400 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5401 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5402 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5403 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5404 */ 5405 /* binop/2addr vA, vB */ 5406 mov r9, rINST, lsr #8 @ r9<- A+ 5407 mov r3, rINST, lsr #12 @ r3<- B 5408 and r9, r9, #15 5409 GET_VREG(r1, r3) @ r1<- vB 5410 GET_VREG(r0, r9) @ r0<- vA 5411 .if 1 5412 cmp r1, #0 @ is second operand zero? 5413 beq common_errDivideByZero 5414 .endif 5415 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5416 5417 @ optional op; may set condition codes 5418 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5419 GET_INST_OPCODE(ip) @ extract opcode from rINST 5420 SET_VREG(r1, r9) @ vAA<- r1 5421 GOTO_OPCODE(ip) @ jump to next instruction 5422 /* 10-13 instructions */ 5423 5424 5425/* ------------------------------ */ 5426 .balign 64 5427.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5428/* File: armv5te/OP_AND_INT_2ADDR.S */ 5429/* File: armv5te/binop2addr.S */ 5430 /* 5431 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5432 * that specifies an instruction that performs "result = r0 op r1". 5433 * This could be an ARM instruction or a function call. (If the result 5434 * comes back in a register other than r0, you can override "result".) 5435 * 5436 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5437 * vCC (r1). Useful for integer division and modulus. 5438 * 5439 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5440 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5441 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5442 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5443 */ 5444 /* binop/2addr vA, vB */ 5445 mov r9, rINST, lsr #8 @ r9<- A+ 5446 mov r3, rINST, lsr #12 @ r3<- B 5447 and r9, r9, #15 5448 GET_VREG(r1, r3) @ r1<- vB 5449 GET_VREG(r0, r9) @ r0<- vA 5450 .if 0 5451 cmp r1, #0 @ is second operand zero? 5452 beq common_errDivideByZero 5453 .endif 5454 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5455 5456 @ optional op; may set condition codes 5457 and r0, r0, r1 @ r0<- op, r0-r3 changed 5458 GET_INST_OPCODE(ip) @ extract opcode from rINST 5459 SET_VREG(r0, r9) @ vAA<- r0 5460 GOTO_OPCODE(ip) @ jump to next instruction 5461 /* 10-13 instructions */ 5462 5463 5464/* ------------------------------ */ 5465 .balign 64 5466.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5467/* File: armv5te/OP_OR_INT_2ADDR.S */ 5468/* File: armv5te/binop2addr.S */ 5469 /* 5470 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5471 * that specifies an instruction that performs "result = r0 op r1". 5472 * This could be an ARM instruction or a function call. (If the result 5473 * comes back in a register other than r0, you can override "result".) 5474 * 5475 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5476 * vCC (r1). Useful for integer division and modulus. 5477 * 5478 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5479 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5480 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5481 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5482 */ 5483 /* binop/2addr vA, vB */ 5484 mov r9, rINST, lsr #8 @ r9<- A+ 5485 mov r3, rINST, lsr #12 @ r3<- B 5486 and r9, r9, #15 5487 GET_VREG(r1, r3) @ r1<- vB 5488 GET_VREG(r0, r9) @ r0<- vA 5489 .if 0 5490 cmp r1, #0 @ is second operand zero? 5491 beq common_errDivideByZero 5492 .endif 5493 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5494 5495 @ optional op; may set condition codes 5496 orr r0, r0, r1 @ r0<- op, r0-r3 changed 5497 GET_INST_OPCODE(ip) @ extract opcode from rINST 5498 SET_VREG(r0, r9) @ vAA<- r0 5499 GOTO_OPCODE(ip) @ jump to next instruction 5500 /* 10-13 instructions */ 5501 5502 5503/* ------------------------------ */ 5504 .balign 64 5505.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5506/* File: armv5te/OP_XOR_INT_2ADDR.S */ 5507/* File: armv5te/binop2addr.S */ 5508 /* 5509 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5510 * that specifies an instruction that performs "result = r0 op r1". 5511 * This could be an ARM instruction or a function call. (If the result 5512 * comes back in a register other than r0, you can override "result".) 5513 * 5514 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5515 * vCC (r1). Useful for integer division and modulus. 5516 * 5517 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5518 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5519 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5520 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5521 */ 5522 /* binop/2addr vA, vB */ 5523 mov r9, rINST, lsr #8 @ r9<- A+ 5524 mov r3, rINST, lsr #12 @ r3<- B 5525 and r9, r9, #15 5526 GET_VREG(r1, r3) @ r1<- vB 5527 GET_VREG(r0, r9) @ r0<- vA 5528 .if 0 5529 cmp r1, #0 @ is second operand zero? 5530 beq common_errDivideByZero 5531 .endif 5532 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5533 5534 @ optional op; may set condition codes 5535 eor r0, r0, r1 @ r0<- op, r0-r3 changed 5536 GET_INST_OPCODE(ip) @ extract opcode from rINST 5537 SET_VREG(r0, r9) @ vAA<- r0 5538 GOTO_OPCODE(ip) @ jump to next instruction 5539 /* 10-13 instructions */ 5540 5541 5542/* ------------------------------ */ 5543 .balign 64 5544.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5545/* File: armv5te/OP_SHL_INT_2ADDR.S */ 5546/* File: armv5te/binop2addr.S */ 5547 /* 5548 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5549 * that specifies an instruction that performs "result = r0 op r1". 5550 * This could be an ARM instruction or a function call. (If the result 5551 * comes back in a register other than r0, you can override "result".) 5552 * 5553 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5554 * vCC (r1). Useful for integer division and modulus. 5555 * 5556 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5557 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5558 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5559 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5560 */ 5561 /* binop/2addr vA, vB */ 5562 mov r9, rINST, lsr #8 @ r9<- A+ 5563 mov r3, rINST, lsr #12 @ r3<- B 5564 and r9, r9, #15 5565 GET_VREG(r1, r3) @ r1<- vB 5566 GET_VREG(r0, r9) @ r0<- vA 5567 .if 0 5568 cmp r1, #0 @ is second operand zero? 5569 beq common_errDivideByZero 5570 .endif 5571 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5572 5573 and r1, r1, #31 @ optional op; may set condition codes 5574 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5575 GET_INST_OPCODE(ip) @ extract opcode from rINST 5576 SET_VREG(r0, r9) @ vAA<- r0 5577 GOTO_OPCODE(ip) @ jump to next instruction 5578 /* 10-13 instructions */ 5579 5580 5581/* ------------------------------ */ 5582 .balign 64 5583.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5584/* File: armv5te/OP_SHR_INT_2ADDR.S */ 5585/* File: armv5te/binop2addr.S */ 5586 /* 5587 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5588 * that specifies an instruction that performs "result = r0 op r1". 5589 * This could be an ARM instruction or a function call. (If the result 5590 * comes back in a register other than r0, you can override "result".) 5591 * 5592 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5593 * vCC (r1). Useful for integer division and modulus. 5594 * 5595 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5596 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5597 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5598 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5599 */ 5600 /* binop/2addr vA, vB */ 5601 mov r9, rINST, lsr #8 @ r9<- A+ 5602 mov r3, rINST, lsr #12 @ r3<- B 5603 and r9, r9, #15 5604 GET_VREG(r1, r3) @ r1<- vB 5605 GET_VREG(r0, r9) @ r0<- vA 5606 .if 0 5607 cmp r1, #0 @ is second operand zero? 5608 beq common_errDivideByZero 5609 .endif 5610 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5611 5612 and r1, r1, #31 @ optional op; may set condition codes 5613 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5614 GET_INST_OPCODE(ip) @ extract opcode from rINST 5615 SET_VREG(r0, r9) @ vAA<- r0 5616 GOTO_OPCODE(ip) @ jump to next instruction 5617 /* 10-13 instructions */ 5618 5619 5620/* ------------------------------ */ 5621 .balign 64 5622.L_OP_USHR_INT_2ADDR: /* 0xba */ 5623/* File: armv5te/OP_USHR_INT_2ADDR.S */ 5624/* File: armv5te/binop2addr.S */ 5625 /* 5626 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5627 * that specifies an instruction that performs "result = r0 op r1". 5628 * This could be an ARM instruction or a function call. (If the result 5629 * comes back in a register other than r0, you can override "result".) 5630 * 5631 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5632 * vCC (r1). Useful for integer division and modulus. 5633 * 5634 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5635 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5636 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5637 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5638 */ 5639 /* binop/2addr vA, vB */ 5640 mov r9, rINST, lsr #8 @ r9<- A+ 5641 mov r3, rINST, lsr #12 @ r3<- B 5642 and r9, r9, #15 5643 GET_VREG(r1, r3) @ r1<- vB 5644 GET_VREG(r0, r9) @ r0<- vA 5645 .if 0 5646 cmp r1, #0 @ is second operand zero? 5647 beq common_errDivideByZero 5648 .endif 5649 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5650 5651 and r1, r1, #31 @ optional op; may set condition codes 5652 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5653 GET_INST_OPCODE(ip) @ extract opcode from rINST 5654 SET_VREG(r0, r9) @ vAA<- r0 5655 GOTO_OPCODE(ip) @ jump to next instruction 5656 /* 10-13 instructions */ 5657 5658 5659/* ------------------------------ */ 5660 .balign 64 5661.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5662/* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5663/* File: armv5te/binopWide2addr.S */ 5664 /* 5665 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5666 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5667 * This could be an ARM instruction or a function call. (If the result 5668 * comes back in a register other than r0, you can override "result".) 5669 * 5670 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5671 * vCC (r1). Useful for integer division and modulus. 5672 * 5673 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5674 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5675 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5676 * rem-double/2addr 5677 */ 5678 /* binop/2addr vA, vB */ 5679 mov r9, rINST, lsr #8 @ r9<- A+ 5680 mov r1, rINST, lsr #12 @ r1<- B 5681 and r9, r9, #15 5682 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5683 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5684 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5685 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5686 .if 0 5687 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5688 beq common_errDivideByZero 5689 .endif 5690 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5691 5692 adds r0, r0, r2 @ optional op; may set condition codes 5693 adc r1, r1, r3 @ result<- op, r0-r3 changed 5694 GET_INST_OPCODE(ip) @ extract opcode from rINST 5695 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5696 GOTO_OPCODE(ip) @ jump to next instruction 5697 /* 12-15 instructions */ 5698 5699 5700/* ------------------------------ */ 5701 .balign 64 5702.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5703/* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5704/* File: armv5te/binopWide2addr.S */ 5705 /* 5706 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5707 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5708 * This could be an ARM instruction or a function call. (If the result 5709 * comes back in a register other than r0, you can override "result".) 5710 * 5711 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5712 * vCC (r1). Useful for integer division and modulus. 5713 * 5714 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5715 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5716 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5717 * rem-double/2addr 5718 */ 5719 /* binop/2addr vA, vB */ 5720 mov r9, rINST, lsr #8 @ r9<- A+ 5721 mov r1, rINST, lsr #12 @ r1<- B 5722 and r9, r9, #15 5723 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5724 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5725 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5726 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5727 .if 0 5728 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5729 beq common_errDivideByZero 5730 .endif 5731 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5732 5733 subs r0, r0, r2 @ optional op; may set condition codes 5734 sbc r1, r1, r3 @ result<- op, r0-r3 changed 5735 GET_INST_OPCODE(ip) @ extract opcode from rINST 5736 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5737 GOTO_OPCODE(ip) @ jump to next instruction 5738 /* 12-15 instructions */ 5739 5740 5741/* ------------------------------ */ 5742 .balign 64 5743.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5744/* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5745 /* 5746 * Signed 64-bit integer multiply, "/2addr" version. 5747 * 5748 * See OP_MUL_LONG for an explanation. 5749 * 5750 * We get a little tight on registers, so to avoid looking up &fp[A] 5751 * again we stuff it into rINST. 5752 */ 5753 /* mul-long/2addr vA, vB */ 5754 mov r9, rINST, lsr #8 @ r9<- A+ 5755 mov r1, rINST, lsr #12 @ r1<- B 5756 and r9, r9, #15 5757 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5758 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5759 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5760 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5761 mul ip, r2, r1 @ ip<- ZxW 5762 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5763 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5764 mov r0, rINST @ r0<- &fp[A] (free up rINST) 5765 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5766 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5767 GET_INST_OPCODE(ip) @ extract opcode from rINST 5768 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5769 GOTO_OPCODE(ip) @ jump to next instruction 5770 5771/* ------------------------------ */ 5772 .balign 64 5773.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5774/* File: armv5te/OP_DIV_LONG_2ADDR.S */ 5775/* File: armv5te/binopWide2addr.S */ 5776 /* 5777 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5778 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5779 * This could be an ARM instruction or a function call. (If the result 5780 * comes back in a register other than r0, you can override "result".) 5781 * 5782 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5783 * vCC (r1). Useful for integer division and modulus. 5784 * 5785 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5786 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5787 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5788 * rem-double/2addr 5789 */ 5790 /* binop/2addr vA, vB */ 5791 mov r9, rINST, lsr #8 @ r9<- A+ 5792 mov r1, rINST, lsr #12 @ r1<- B 5793 and r9, r9, #15 5794 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5795 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5796 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5797 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5798 .if 1 5799 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5800 beq common_errDivideByZero 5801 .endif 5802 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5803 5804 @ optional op; may set condition codes 5805 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5806 GET_INST_OPCODE(ip) @ extract opcode from rINST 5807 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5808 GOTO_OPCODE(ip) @ jump to next instruction 5809 /* 12-15 instructions */ 5810 5811 5812/* ------------------------------ */ 5813 .balign 64 5814.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5815/* File: armv5te/OP_REM_LONG_2ADDR.S */ 5816/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5817/* File: armv5te/binopWide2addr.S */ 5818 /* 5819 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5820 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5821 * This could be an ARM instruction or a function call. (If the result 5822 * comes back in a register other than r0, you can override "result".) 5823 * 5824 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5825 * vCC (r1). Useful for integer division and modulus. 5826 * 5827 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5828 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5829 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5830 * rem-double/2addr 5831 */ 5832 /* binop/2addr vA, vB */ 5833 mov r9, rINST, lsr #8 @ r9<- A+ 5834 mov r1, rINST, lsr #12 @ r1<- B 5835 and r9, r9, #15 5836 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5837 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5838 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5839 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5840 .if 1 5841 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5842 beq common_errDivideByZero 5843 .endif 5844 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5845 5846 @ optional op; may set condition codes 5847 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5848 GET_INST_OPCODE(ip) @ extract opcode from rINST 5849 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5850 GOTO_OPCODE(ip) @ jump to next instruction 5851 /* 12-15 instructions */ 5852 5853 5854/* ------------------------------ */ 5855 .balign 64 5856.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5857/* File: armv5te/OP_AND_LONG_2ADDR.S */ 5858/* File: armv5te/binopWide2addr.S */ 5859 /* 5860 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5861 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5862 * This could be an ARM instruction or a function call. (If the result 5863 * comes back in a register other than r0, you can override "result".) 5864 * 5865 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5866 * vCC (r1). Useful for integer division and modulus. 5867 * 5868 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5869 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5870 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5871 * rem-double/2addr 5872 */ 5873 /* binop/2addr vA, vB */ 5874 mov r9, rINST, lsr #8 @ r9<- A+ 5875 mov r1, rINST, lsr #12 @ r1<- B 5876 and r9, r9, #15 5877 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5878 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5879 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5880 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5881 .if 0 5882 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5883 beq common_errDivideByZero 5884 .endif 5885 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5886 5887 and r0, r0, r2 @ optional op; may set condition codes 5888 and r1, r1, r3 @ result<- op, r0-r3 changed 5889 GET_INST_OPCODE(ip) @ extract opcode from rINST 5890 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5891 GOTO_OPCODE(ip) @ jump to next instruction 5892 /* 12-15 instructions */ 5893 5894 5895/* ------------------------------ */ 5896 .balign 64 5897.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5898/* File: armv5te/OP_OR_LONG_2ADDR.S */ 5899/* File: armv5te/binopWide2addr.S */ 5900 /* 5901 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5902 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5903 * This could be an ARM instruction or a function call. (If the result 5904 * comes back in a register other than r0, you can override "result".) 5905 * 5906 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5907 * vCC (r1). Useful for integer division and modulus. 5908 * 5909 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5910 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5911 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5912 * rem-double/2addr 5913 */ 5914 /* binop/2addr vA, vB */ 5915 mov r9, rINST, lsr #8 @ r9<- A+ 5916 mov r1, rINST, lsr #12 @ r1<- B 5917 and r9, r9, #15 5918 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5919 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5920 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5921 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5922 .if 0 5923 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5924 beq common_errDivideByZero 5925 .endif 5926 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5927 5928 orr r0, r0, r2 @ optional op; may set condition codes 5929 orr r1, r1, r3 @ result<- op, r0-r3 changed 5930 GET_INST_OPCODE(ip) @ extract opcode from rINST 5931 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5932 GOTO_OPCODE(ip) @ jump to next instruction 5933 /* 12-15 instructions */ 5934 5935 5936/* ------------------------------ */ 5937 .balign 64 5938.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5939/* File: armv5te/OP_XOR_LONG_2ADDR.S */ 5940/* File: armv5te/binopWide2addr.S */ 5941 /* 5942 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5943 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5944 * This could be an ARM instruction or a function call. (If the result 5945 * comes back in a register other than r0, you can override "result".) 5946 * 5947 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5948 * vCC (r1). Useful for integer division and modulus. 5949 * 5950 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5951 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5952 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5953 * rem-double/2addr 5954 */ 5955 /* binop/2addr vA, vB */ 5956 mov r9, rINST, lsr #8 @ r9<- A+ 5957 mov r1, rINST, lsr #12 @ r1<- B 5958 and r9, r9, #15 5959 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5960 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5961 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5962 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5963 .if 0 5964 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5965 beq common_errDivideByZero 5966 .endif 5967 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5968 5969 eor r0, r0, r2 @ optional op; may set condition codes 5970 eor r1, r1, r3 @ result<- op, r0-r3 changed 5971 GET_INST_OPCODE(ip) @ extract opcode from rINST 5972 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5973 GOTO_OPCODE(ip) @ jump to next instruction 5974 /* 12-15 instructions */ 5975 5976 5977/* ------------------------------ */ 5978 .balign 64 5979.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 5980/* File: armv5te/OP_SHL_LONG_2ADDR.S */ 5981 /* 5982 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5983 * 32-bit shift distance. 5984 */ 5985 /* shl-long/2addr vA, vB */ 5986 mov r9, rINST, lsr #8 @ r9<- A+ 5987 mov r3, rINST, lsr #12 @ r3<- B 5988 and r9, r9, #15 5989 GET_VREG(r2, r3) @ r2<- vB 5990 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5991 and r2, r2, #63 @ r2<- r2 & 0x3f 5992 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5993 5994 mov r1, r1, asl r2 @ r1<- r1 << r2 5995 rsb r3, r2, #32 @ r3<- 32 - r2 5996 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 5997 subs ip, r2, #32 @ ip<- r2 - 32 5998 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5999 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6000 mov r0, r0, asl r2 @ r0<- r0 << r2 6001 b .LOP_SHL_LONG_2ADDR_finish 6002 6003/* ------------------------------ */ 6004 .balign 64 6005.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6006/* File: armv5te/OP_SHR_LONG_2ADDR.S */ 6007 /* 6008 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6009 * 32-bit shift distance. 6010 */ 6011 /* shr-long/2addr vA, vB */ 6012 mov r9, rINST, lsr #8 @ r9<- A+ 6013 mov r3, rINST, lsr #12 @ r3<- B 6014 and r9, r9, #15 6015 GET_VREG(r2, r3) @ r2<- vB 6016 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6017 and r2, r2, #63 @ r2<- r2 & 0x3f 6018 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6019 6020 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6021 rsb r3, r2, #32 @ r3<- 32 - r2 6022 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6023 subs ip, r2, #32 @ ip<- r2 - 32 6024 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6025 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6026 mov r1, r1, asr r2 @ r1<- r1 >> r2 6027 b .LOP_SHR_LONG_2ADDR_finish 6028 6029/* ------------------------------ */ 6030 .balign 64 6031.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6032/* File: armv5te/OP_USHR_LONG_2ADDR.S */ 6033 /* 6034 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6035 * 32-bit shift distance. 6036 */ 6037 /* ushr-long/2addr vA, vB */ 6038 mov r9, rINST, lsr #8 @ r9<- A+ 6039 mov r3, rINST, lsr #12 @ r3<- B 6040 and r9, r9, #15 6041 GET_VREG(r2, r3) @ r2<- vB 6042 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6043 and r2, r2, #63 @ r2<- r2 & 0x3f 6044 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6045 6046 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6047 rsb r3, r2, #32 @ r3<- 32 - r2 6048 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6049 subs ip, r2, #32 @ ip<- r2 - 32 6050 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6051 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6052 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6053 b .LOP_USHR_LONG_2ADDR_finish 6054 6055/* ------------------------------ */ 6056 .balign 64 6057.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6058/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6059/* File: arm-vfp/fbinop2addr.S */ 6060 /* 6061 * Generic 32-bit floating point "/2addr" binary operation. Provide 6062 * an "instr" line that specifies an instruction that performs 6063 * "s2 = s0 op s1". 6064 * 6065 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6066 */ 6067 /* binop/2addr vA, vB */ 6068 mov r3, rINST, lsr #12 @ r3<- B 6069 mov r9, rINST, lsr #8 @ r9<- A+ 6070 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6071 and r9, r9, #15 @ r9<- A 6072 flds s1, [r3] @ s1<- vB 6073 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6074 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6075 flds s0, [r9] @ s0<- vA 6076 6077 fadds s2, s0, s1 @ s2<- op 6078 GET_INST_OPCODE(ip) @ extract opcode from rINST 6079 fsts s2, [r9] @ vAA<- s2 6080 GOTO_OPCODE(ip) @ jump to next instruction 6081 6082 6083/* ------------------------------ */ 6084 .balign 64 6085.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6086/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6087/* File: arm-vfp/fbinop2addr.S */ 6088 /* 6089 * Generic 32-bit floating point "/2addr" binary operation. Provide 6090 * an "instr" line that specifies an instruction that performs 6091 * "s2 = s0 op s1". 6092 * 6093 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6094 */ 6095 /* binop/2addr vA, vB */ 6096 mov r3, rINST, lsr #12 @ r3<- B 6097 mov r9, rINST, lsr #8 @ r9<- A+ 6098 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6099 and r9, r9, #15 @ r9<- A 6100 flds s1, [r3] @ s1<- vB 6101 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6102 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6103 flds s0, [r9] @ s0<- vA 6104 6105 fsubs s2, s0, s1 @ s2<- op 6106 GET_INST_OPCODE(ip) @ extract opcode from rINST 6107 fsts s2, [r9] @ vAA<- s2 6108 GOTO_OPCODE(ip) @ jump to next instruction 6109 6110 6111/* ------------------------------ */ 6112 .balign 64 6113.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6114/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6115/* File: arm-vfp/fbinop2addr.S */ 6116 /* 6117 * Generic 32-bit floating point "/2addr" binary operation. Provide 6118 * an "instr" line that specifies an instruction that performs 6119 * "s2 = s0 op s1". 6120 * 6121 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6122 */ 6123 /* binop/2addr vA, vB */ 6124 mov r3, rINST, lsr #12 @ r3<- B 6125 mov r9, rINST, lsr #8 @ r9<- A+ 6126 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6127 and r9, r9, #15 @ r9<- A 6128 flds s1, [r3] @ s1<- vB 6129 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6130 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6131 flds s0, [r9] @ s0<- vA 6132 6133 fmuls s2, s0, s1 @ s2<- op 6134 GET_INST_OPCODE(ip) @ extract opcode from rINST 6135 fsts s2, [r9] @ vAA<- s2 6136 GOTO_OPCODE(ip) @ jump to next instruction 6137 6138 6139/* ------------------------------ */ 6140 .balign 64 6141.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6142/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6143/* File: arm-vfp/fbinop2addr.S */ 6144 /* 6145 * Generic 32-bit floating point "/2addr" binary operation. Provide 6146 * an "instr" line that specifies an instruction that performs 6147 * "s2 = s0 op s1". 6148 * 6149 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6150 */ 6151 /* binop/2addr vA, vB */ 6152 mov r3, rINST, lsr #12 @ r3<- B 6153 mov r9, rINST, lsr #8 @ r9<- A+ 6154 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6155 and r9, r9, #15 @ r9<- A 6156 flds s1, [r3] @ s1<- vB 6157 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6158 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6159 flds s0, [r9] @ s0<- vA 6160 6161 fdivs s2, s0, s1 @ s2<- op 6162 GET_INST_OPCODE(ip) @ extract opcode from rINST 6163 fsts s2, [r9] @ vAA<- s2 6164 GOTO_OPCODE(ip) @ jump to next instruction 6165 6166 6167/* ------------------------------ */ 6168 .balign 64 6169.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6170/* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6171/* EABI doesn't define a float remainder function, but libm does */ 6172/* File: armv5te/binop2addr.S */ 6173 /* 6174 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6175 * that specifies an instruction that performs "result = r0 op r1". 6176 * This could be an ARM instruction or a function call. (If the result 6177 * comes back in a register other than r0, you can override "result".) 6178 * 6179 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6180 * vCC (r1). Useful for integer division and modulus. 6181 * 6182 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6183 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6184 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6185 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6186 */ 6187 /* binop/2addr vA, vB */ 6188 mov r9, rINST, lsr #8 @ r9<- A+ 6189 mov r3, rINST, lsr #12 @ r3<- B 6190 and r9, r9, #15 6191 GET_VREG(r1, r3) @ r1<- vB 6192 GET_VREG(r0, r9) @ r0<- vA 6193 .if 0 6194 cmp r1, #0 @ is second operand zero? 6195 beq common_errDivideByZero 6196 .endif 6197 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6198 6199 @ optional op; may set condition codes 6200 bl fmodf @ r0<- op, r0-r3 changed 6201 GET_INST_OPCODE(ip) @ extract opcode from rINST 6202 SET_VREG(r0, r9) @ vAA<- r0 6203 GOTO_OPCODE(ip) @ jump to next instruction 6204 /* 10-13 instructions */ 6205 6206 6207/* ------------------------------ */ 6208 .balign 64 6209.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6210/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6211/* File: arm-vfp/fbinopWide2addr.S */ 6212 /* 6213 * Generic 64-bit floating point "/2addr" binary operation. Provide 6214 * an "instr" line that specifies an instruction that performs 6215 * "d2 = d0 op d1". 6216 * 6217 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6218 * div-double/2addr 6219 */ 6220 /* binop/2addr vA, vB */ 6221 mov r3, rINST, lsr #12 @ r3<- B 6222 mov r9, rINST, lsr #8 @ r9<- A+ 6223 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6224 and r9, r9, #15 @ r9<- A 6225 fldd d1, [r3] @ d1<- vB 6226 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6227 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6228 fldd d0, [r9] @ d0<- vA 6229 6230 faddd d2, d0, d1 @ d2<- op 6231 GET_INST_OPCODE(ip) @ extract opcode from rINST 6232 fstd d2, [r9] @ vAA<- d2 6233 GOTO_OPCODE(ip) @ jump to next instruction 6234 6235 6236/* ------------------------------ */ 6237 .balign 64 6238.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6239/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6240/* File: arm-vfp/fbinopWide2addr.S */ 6241 /* 6242 * Generic 64-bit floating point "/2addr" binary operation. Provide 6243 * an "instr" line that specifies an instruction that performs 6244 * "d2 = d0 op d1". 6245 * 6246 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6247 * div-double/2addr 6248 */ 6249 /* binop/2addr vA, vB */ 6250 mov r3, rINST, lsr #12 @ r3<- B 6251 mov r9, rINST, lsr #8 @ r9<- A+ 6252 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6253 and r9, r9, #15 @ r9<- A 6254 fldd d1, [r3] @ d1<- vB 6255 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6256 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6257 fldd d0, [r9] @ d0<- vA 6258 6259 fsubd d2, d0, d1 @ d2<- op 6260 GET_INST_OPCODE(ip) @ extract opcode from rINST 6261 fstd d2, [r9] @ vAA<- d2 6262 GOTO_OPCODE(ip) @ jump to next instruction 6263 6264 6265/* ------------------------------ */ 6266 .balign 64 6267.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6268/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6269/* File: arm-vfp/fbinopWide2addr.S */ 6270 /* 6271 * Generic 64-bit floating point "/2addr" binary operation. Provide 6272 * an "instr" line that specifies an instruction that performs 6273 * "d2 = d0 op d1". 6274 * 6275 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6276 * div-double/2addr 6277 */ 6278 /* binop/2addr vA, vB */ 6279 mov r3, rINST, lsr #12 @ r3<- B 6280 mov r9, rINST, lsr #8 @ r9<- A+ 6281 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6282 and r9, r9, #15 @ r9<- A 6283 fldd d1, [r3] @ d1<- vB 6284 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6285 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6286 fldd d0, [r9] @ d0<- vA 6287 6288 fmuld d2, d0, d1 @ d2<- op 6289 GET_INST_OPCODE(ip) @ extract opcode from rINST 6290 fstd d2, [r9] @ vAA<- d2 6291 GOTO_OPCODE(ip) @ jump to next instruction 6292 6293 6294/* ------------------------------ */ 6295 .balign 64 6296.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6297/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6298/* File: arm-vfp/fbinopWide2addr.S */ 6299 /* 6300 * Generic 64-bit floating point "/2addr" binary operation. Provide 6301 * an "instr" line that specifies an instruction that performs 6302 * "d2 = d0 op d1". 6303 * 6304 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6305 * div-double/2addr 6306 */ 6307 /* binop/2addr vA, vB */ 6308 mov r3, rINST, lsr #12 @ r3<- B 6309 mov r9, rINST, lsr #8 @ r9<- A+ 6310 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6311 and r9, r9, #15 @ r9<- A 6312 fldd d1, [r3] @ d1<- vB 6313 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6314 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6315 fldd d0, [r9] @ d0<- vA 6316 6317 fdivd d2, d0, d1 @ d2<- op 6318 GET_INST_OPCODE(ip) @ extract opcode from rINST 6319 fstd d2, [r9] @ vAA<- d2 6320 GOTO_OPCODE(ip) @ jump to next instruction 6321 6322 6323/* ------------------------------ */ 6324 .balign 64 6325.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6326/* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6327/* EABI doesn't define a double remainder function, but libm does */ 6328/* File: armv5te/binopWide2addr.S */ 6329 /* 6330 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6331 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6332 * This could be an ARM instruction or a function call. (If the result 6333 * comes back in a register other than r0, you can override "result".) 6334 * 6335 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6336 * vCC (r1). Useful for integer division and modulus. 6337 * 6338 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6339 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6340 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6341 * rem-double/2addr 6342 */ 6343 /* binop/2addr vA, vB */ 6344 mov r9, rINST, lsr #8 @ r9<- A+ 6345 mov r1, rINST, lsr #12 @ r1<- B 6346 and r9, r9, #15 6347 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6348 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6349 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6350 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6351 .if 0 6352 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6353 beq common_errDivideByZero 6354 .endif 6355 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6356 6357 @ optional op; may set condition codes 6358 bl fmod @ result<- op, r0-r3 changed 6359 GET_INST_OPCODE(ip) @ extract opcode from rINST 6360 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6361 GOTO_OPCODE(ip) @ jump to next instruction 6362 /* 12-15 instructions */ 6363 6364 6365/* ------------------------------ */ 6366 .balign 64 6367.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6368/* File: armv5te/OP_ADD_INT_LIT16.S */ 6369/* File: armv5te/binopLit16.S */ 6370 /* 6371 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6372 * that specifies an instruction that performs "result = r0 op r1". 6373 * This could be an ARM instruction or a function call. (If the result 6374 * comes back in a register other than r0, you can override "result".) 6375 * 6376 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6377 * vCC (r1). Useful for integer division and modulus. 6378 * 6379 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6380 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6381 */ 6382 /* binop/lit16 vA, vB, #+CCCC */ 6383 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6384 mov r2, rINST, lsr #12 @ r2<- B 6385 mov r9, rINST, lsr #8 @ r9<- A+ 6386 GET_VREG(r0, r2) @ r0<- vB 6387 and r9, r9, #15 6388 .if 0 6389 cmp r1, #0 @ is second operand zero? 6390 beq common_errDivideByZero 6391 .endif 6392 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6393 6394 add r0, r0, r1 @ r0<- op, r0-r3 changed 6395 GET_INST_OPCODE(ip) @ extract opcode from rINST 6396 SET_VREG(r0, r9) @ vAA<- r0 6397 GOTO_OPCODE(ip) @ jump to next instruction 6398 /* 10-13 instructions */ 6399 6400 6401/* ------------------------------ */ 6402 .balign 64 6403.L_OP_RSUB_INT: /* 0xd1 */ 6404/* File: armv5te/OP_RSUB_INT.S */ 6405/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6406/* File: armv5te/binopLit16.S */ 6407 /* 6408 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6409 * that specifies an instruction that performs "result = r0 op r1". 6410 * This could be an ARM instruction or a function call. (If the result 6411 * comes back in a register other than r0, you can override "result".) 6412 * 6413 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6414 * vCC (r1). Useful for integer division and modulus. 6415 * 6416 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6417 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6418 */ 6419 /* binop/lit16 vA, vB, #+CCCC */ 6420 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6421 mov r2, rINST, lsr #12 @ r2<- B 6422 mov r9, rINST, lsr #8 @ r9<- A+ 6423 GET_VREG(r0, r2) @ r0<- vB 6424 and r9, r9, #15 6425 .if 0 6426 cmp r1, #0 @ is second operand zero? 6427 beq common_errDivideByZero 6428 .endif 6429 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6430 6431 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6432 GET_INST_OPCODE(ip) @ extract opcode from rINST 6433 SET_VREG(r0, r9) @ vAA<- r0 6434 GOTO_OPCODE(ip) @ jump to next instruction 6435 /* 10-13 instructions */ 6436 6437 6438/* ------------------------------ */ 6439 .balign 64 6440.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6441/* File: armv5te/OP_MUL_INT_LIT16.S */ 6442/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6443/* File: armv5te/binopLit16.S */ 6444 /* 6445 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6446 * that specifies an instruction that performs "result = r0 op r1". 6447 * This could be an ARM instruction or a function call. (If the result 6448 * comes back in a register other than r0, you can override "result".) 6449 * 6450 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6451 * vCC (r1). Useful for integer division and modulus. 6452 * 6453 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6454 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6455 */ 6456 /* binop/lit16 vA, vB, #+CCCC */ 6457 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6458 mov r2, rINST, lsr #12 @ r2<- B 6459 mov r9, rINST, lsr #8 @ r9<- A+ 6460 GET_VREG(r0, r2) @ r0<- vB 6461 and r9, r9, #15 6462 .if 0 6463 cmp r1, #0 @ is second operand zero? 6464 beq common_errDivideByZero 6465 .endif 6466 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6467 6468 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6469 GET_INST_OPCODE(ip) @ extract opcode from rINST 6470 SET_VREG(r0, r9) @ vAA<- r0 6471 GOTO_OPCODE(ip) @ jump to next instruction 6472 /* 10-13 instructions */ 6473 6474 6475/* ------------------------------ */ 6476 .balign 64 6477.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6478/* File: armv5te/OP_DIV_INT_LIT16.S */ 6479/* File: armv5te/binopLit16.S */ 6480 /* 6481 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6482 * that specifies an instruction that performs "result = r0 op r1". 6483 * This could be an ARM instruction or a function call. (If the result 6484 * comes back in a register other than r0, you can override "result".) 6485 * 6486 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6487 * vCC (r1). Useful for integer division and modulus. 6488 * 6489 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6490 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6491 */ 6492 /* binop/lit16 vA, vB, #+CCCC */ 6493 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6494 mov r2, rINST, lsr #12 @ r2<- B 6495 mov r9, rINST, lsr #8 @ r9<- A+ 6496 GET_VREG(r0, r2) @ r0<- vB 6497 and r9, r9, #15 6498 .if 1 6499 cmp r1, #0 @ is second operand zero? 6500 beq common_errDivideByZero 6501 .endif 6502 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6503 6504 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6505 GET_INST_OPCODE(ip) @ extract opcode from rINST 6506 SET_VREG(r0, r9) @ vAA<- r0 6507 GOTO_OPCODE(ip) @ jump to next instruction 6508 /* 10-13 instructions */ 6509 6510 6511/* ------------------------------ */ 6512 .balign 64 6513.L_OP_REM_INT_LIT16: /* 0xd4 */ 6514/* File: armv5te/OP_REM_INT_LIT16.S */ 6515/* idivmod returns quotient in r0 and remainder in r1 */ 6516/* File: armv5te/binopLit16.S */ 6517 /* 6518 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6519 * that specifies an instruction that performs "result = r0 op r1". 6520 * This could be an ARM instruction or a function call. (If the result 6521 * comes back in a register other than r0, you can override "result".) 6522 * 6523 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6524 * vCC (r1). Useful for integer division and modulus. 6525 * 6526 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6527 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6528 */ 6529 /* binop/lit16 vA, vB, #+CCCC */ 6530 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6531 mov r2, rINST, lsr #12 @ r2<- B 6532 mov r9, rINST, lsr #8 @ r9<- A+ 6533 GET_VREG(r0, r2) @ r0<- vB 6534 and r9, r9, #15 6535 .if 1 6536 cmp r1, #0 @ is second operand zero? 6537 beq common_errDivideByZero 6538 .endif 6539 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6540 6541 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6542 GET_INST_OPCODE(ip) @ extract opcode from rINST 6543 SET_VREG(r1, r9) @ vAA<- r1 6544 GOTO_OPCODE(ip) @ jump to next instruction 6545 /* 10-13 instructions */ 6546 6547 6548/* ------------------------------ */ 6549 .balign 64 6550.L_OP_AND_INT_LIT16: /* 0xd5 */ 6551/* File: armv5te/OP_AND_INT_LIT16.S */ 6552/* File: armv5te/binopLit16.S */ 6553 /* 6554 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6555 * that specifies an instruction that performs "result = r0 op r1". 6556 * This could be an ARM instruction or a function call. (If the result 6557 * comes back in a register other than r0, you can override "result".) 6558 * 6559 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6560 * vCC (r1). Useful for integer division and modulus. 6561 * 6562 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6563 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6564 */ 6565 /* binop/lit16 vA, vB, #+CCCC */ 6566 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6567 mov r2, rINST, lsr #12 @ r2<- B 6568 mov r9, rINST, lsr #8 @ r9<- A+ 6569 GET_VREG(r0, r2) @ r0<- vB 6570 and r9, r9, #15 6571 .if 0 6572 cmp r1, #0 @ is second operand zero? 6573 beq common_errDivideByZero 6574 .endif 6575 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6576 6577 and r0, r0, r1 @ r0<- op, r0-r3 changed 6578 GET_INST_OPCODE(ip) @ extract opcode from rINST 6579 SET_VREG(r0, r9) @ vAA<- r0 6580 GOTO_OPCODE(ip) @ jump to next instruction 6581 /* 10-13 instructions */ 6582 6583 6584/* ------------------------------ */ 6585 .balign 64 6586.L_OP_OR_INT_LIT16: /* 0xd6 */ 6587/* File: armv5te/OP_OR_INT_LIT16.S */ 6588/* File: armv5te/binopLit16.S */ 6589 /* 6590 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6591 * that specifies an instruction that performs "result = r0 op r1". 6592 * This could be an ARM instruction or a function call. (If the result 6593 * comes back in a register other than r0, you can override "result".) 6594 * 6595 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6596 * vCC (r1). Useful for integer division and modulus. 6597 * 6598 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6599 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6600 */ 6601 /* binop/lit16 vA, vB, #+CCCC */ 6602 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6603 mov r2, rINST, lsr #12 @ r2<- B 6604 mov r9, rINST, lsr #8 @ r9<- A+ 6605 GET_VREG(r0, r2) @ r0<- vB 6606 and r9, r9, #15 6607 .if 0 6608 cmp r1, #0 @ is second operand zero? 6609 beq common_errDivideByZero 6610 .endif 6611 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6612 6613 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6614 GET_INST_OPCODE(ip) @ extract opcode from rINST 6615 SET_VREG(r0, r9) @ vAA<- r0 6616 GOTO_OPCODE(ip) @ jump to next instruction 6617 /* 10-13 instructions */ 6618 6619 6620/* ------------------------------ */ 6621 .balign 64 6622.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6623/* File: armv5te/OP_XOR_INT_LIT16.S */ 6624/* File: armv5te/binopLit16.S */ 6625 /* 6626 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6627 * that specifies an instruction that performs "result = r0 op r1". 6628 * This could be an ARM instruction or a function call. (If the result 6629 * comes back in a register other than r0, you can override "result".) 6630 * 6631 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6632 * vCC (r1). Useful for integer division and modulus. 6633 * 6634 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6635 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6636 */ 6637 /* binop/lit16 vA, vB, #+CCCC */ 6638 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6639 mov r2, rINST, lsr #12 @ r2<- B 6640 mov r9, rINST, lsr #8 @ r9<- A+ 6641 GET_VREG(r0, r2) @ r0<- vB 6642 and r9, r9, #15 6643 .if 0 6644 cmp r1, #0 @ is second operand zero? 6645 beq common_errDivideByZero 6646 .endif 6647 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6648 6649 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6650 GET_INST_OPCODE(ip) @ extract opcode from rINST 6651 SET_VREG(r0, r9) @ vAA<- r0 6652 GOTO_OPCODE(ip) @ jump to next instruction 6653 /* 10-13 instructions */ 6654 6655 6656/* ------------------------------ */ 6657 .balign 64 6658.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6659/* File: armv5te/OP_ADD_INT_LIT8.S */ 6660/* File: armv5te/binopLit8.S */ 6661 /* 6662 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6663 * that specifies an instruction that performs "result = r0 op r1". 6664 * This could be an ARM instruction or a function call. (If the result 6665 * comes back in a register other than r0, you can override "result".) 6666 * 6667 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6668 * vCC (r1). Useful for integer division and modulus. 6669 * 6670 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6671 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6672 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6673 */ 6674 /* binop/lit8 vAA, vBB, #+CC */ 6675 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6676 mov r9, rINST, lsr #8 @ r9<- AA 6677 and r2, r3, #255 @ r2<- BB 6678 GET_VREG(r0, r2) @ r0<- vBB 6679 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6680 .if 0 6681 @cmp r1, #0 @ is second operand zero? 6682 beq common_errDivideByZero 6683 .endif 6684 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6685 6686 @ optional op; may set condition codes 6687 add r0, r0, r1 @ r0<- op, r0-r3 changed 6688 GET_INST_OPCODE(ip) @ extract opcode from rINST 6689 SET_VREG(r0, r9) @ vAA<- r0 6690 GOTO_OPCODE(ip) @ jump to next instruction 6691 /* 10-12 instructions */ 6692 6693 6694/* ------------------------------ */ 6695 .balign 64 6696.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6697/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6698/* File: armv5te/binopLit8.S */ 6699 /* 6700 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6701 * that specifies an instruction that performs "result = r0 op r1". 6702 * This could be an ARM instruction or a function call. (If the result 6703 * comes back in a register other than r0, you can override "result".) 6704 * 6705 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6706 * vCC (r1). Useful for integer division and modulus. 6707 * 6708 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6709 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6710 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6711 */ 6712 /* binop/lit8 vAA, vBB, #+CC */ 6713 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6714 mov r9, rINST, lsr #8 @ r9<- AA 6715 and r2, r3, #255 @ r2<- BB 6716 GET_VREG(r0, r2) @ r0<- vBB 6717 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6718 .if 0 6719 @cmp r1, #0 @ is second operand zero? 6720 beq common_errDivideByZero 6721 .endif 6722 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6723 6724 @ optional op; may set condition codes 6725 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6726 GET_INST_OPCODE(ip) @ extract opcode from rINST 6727 SET_VREG(r0, r9) @ vAA<- r0 6728 GOTO_OPCODE(ip) @ jump to next instruction 6729 /* 10-12 instructions */ 6730 6731 6732/* ------------------------------ */ 6733 .balign 64 6734.L_OP_MUL_INT_LIT8: /* 0xda */ 6735/* File: armv5te/OP_MUL_INT_LIT8.S */ 6736/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6737/* File: armv5te/binopLit8.S */ 6738 /* 6739 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6740 * that specifies an instruction that performs "result = r0 op r1". 6741 * This could be an ARM instruction or a function call. (If the result 6742 * comes back in a register other than r0, you can override "result".) 6743 * 6744 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6745 * vCC (r1). Useful for integer division and modulus. 6746 * 6747 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6748 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6749 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6750 */ 6751 /* binop/lit8 vAA, vBB, #+CC */ 6752 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6753 mov r9, rINST, lsr #8 @ r9<- AA 6754 and r2, r3, #255 @ r2<- BB 6755 GET_VREG(r0, r2) @ r0<- vBB 6756 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6757 .if 0 6758 @cmp r1, #0 @ is second operand zero? 6759 beq common_errDivideByZero 6760 .endif 6761 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6762 6763 @ optional op; may set condition codes 6764 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6765 GET_INST_OPCODE(ip) @ extract opcode from rINST 6766 SET_VREG(r0, r9) @ vAA<- r0 6767 GOTO_OPCODE(ip) @ jump to next instruction 6768 /* 10-12 instructions */ 6769 6770 6771/* ------------------------------ */ 6772 .balign 64 6773.L_OP_DIV_INT_LIT8: /* 0xdb */ 6774/* File: armv5te/OP_DIV_INT_LIT8.S */ 6775/* File: armv5te/binopLit8.S */ 6776 /* 6777 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6778 * that specifies an instruction that performs "result = r0 op r1". 6779 * This could be an ARM instruction or a function call. (If the result 6780 * comes back in a register other than r0, you can override "result".) 6781 * 6782 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6783 * vCC (r1). Useful for integer division and modulus. 6784 * 6785 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6786 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6787 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6788 */ 6789 /* binop/lit8 vAA, vBB, #+CC */ 6790 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6791 mov r9, rINST, lsr #8 @ r9<- AA 6792 and r2, r3, #255 @ r2<- BB 6793 GET_VREG(r0, r2) @ r0<- vBB 6794 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6795 .if 1 6796 @cmp r1, #0 @ is second operand zero? 6797 beq common_errDivideByZero 6798 .endif 6799 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6800 6801 @ optional op; may set condition codes 6802 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6803 GET_INST_OPCODE(ip) @ extract opcode from rINST 6804 SET_VREG(r0, r9) @ vAA<- r0 6805 GOTO_OPCODE(ip) @ jump to next instruction 6806 /* 10-12 instructions */ 6807 6808 6809/* ------------------------------ */ 6810 .balign 64 6811.L_OP_REM_INT_LIT8: /* 0xdc */ 6812/* File: armv5te/OP_REM_INT_LIT8.S */ 6813/* idivmod returns quotient in r0 and remainder in r1 */ 6814/* File: armv5te/binopLit8.S */ 6815 /* 6816 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6817 * that specifies an instruction that performs "result = r0 op r1". 6818 * This could be an ARM instruction or a function call. (If the result 6819 * comes back in a register other than r0, you can override "result".) 6820 * 6821 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6822 * vCC (r1). Useful for integer division and modulus. 6823 * 6824 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6825 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6826 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6827 */ 6828 /* binop/lit8 vAA, vBB, #+CC */ 6829 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6830 mov r9, rINST, lsr #8 @ r9<- AA 6831 and r2, r3, #255 @ r2<- BB 6832 GET_VREG(r0, r2) @ r0<- vBB 6833 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6834 .if 1 6835 @cmp r1, #0 @ is second operand zero? 6836 beq common_errDivideByZero 6837 .endif 6838 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6839 6840 @ optional op; may set condition codes 6841 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6842 GET_INST_OPCODE(ip) @ extract opcode from rINST 6843 SET_VREG(r1, r9) @ vAA<- r1 6844 GOTO_OPCODE(ip) @ jump to next instruction 6845 /* 10-12 instructions */ 6846 6847 6848/* ------------------------------ */ 6849 .balign 64 6850.L_OP_AND_INT_LIT8: /* 0xdd */ 6851/* File: armv5te/OP_AND_INT_LIT8.S */ 6852/* File: armv5te/binopLit8.S */ 6853 /* 6854 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6855 * that specifies an instruction that performs "result = r0 op r1". 6856 * This could be an ARM instruction or a function call. (If the result 6857 * comes back in a register other than r0, you can override "result".) 6858 * 6859 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6860 * vCC (r1). Useful for integer division and modulus. 6861 * 6862 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6863 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6864 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6865 */ 6866 /* binop/lit8 vAA, vBB, #+CC */ 6867 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6868 mov r9, rINST, lsr #8 @ r9<- AA 6869 and r2, r3, #255 @ r2<- BB 6870 GET_VREG(r0, r2) @ r0<- vBB 6871 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6872 .if 0 6873 @cmp r1, #0 @ is second operand zero? 6874 beq common_errDivideByZero 6875 .endif 6876 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6877 6878 @ optional op; may set condition codes 6879 and r0, r0, r1 @ r0<- op, r0-r3 changed 6880 GET_INST_OPCODE(ip) @ extract opcode from rINST 6881 SET_VREG(r0, r9) @ vAA<- r0 6882 GOTO_OPCODE(ip) @ jump to next instruction 6883 /* 10-12 instructions */ 6884 6885 6886/* ------------------------------ */ 6887 .balign 64 6888.L_OP_OR_INT_LIT8: /* 0xde */ 6889/* File: armv5te/OP_OR_INT_LIT8.S */ 6890/* File: armv5te/binopLit8.S */ 6891 /* 6892 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6893 * that specifies an instruction that performs "result = r0 op r1". 6894 * This could be an ARM instruction or a function call. (If the result 6895 * comes back in a register other than r0, you can override "result".) 6896 * 6897 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6898 * vCC (r1). Useful for integer division and modulus. 6899 * 6900 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6901 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6902 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6903 */ 6904 /* binop/lit8 vAA, vBB, #+CC */ 6905 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6906 mov r9, rINST, lsr #8 @ r9<- AA 6907 and r2, r3, #255 @ r2<- BB 6908 GET_VREG(r0, r2) @ r0<- vBB 6909 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6910 .if 0 6911 @cmp r1, #0 @ is second operand zero? 6912 beq common_errDivideByZero 6913 .endif 6914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6915 6916 @ optional op; may set condition codes 6917 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6918 GET_INST_OPCODE(ip) @ extract opcode from rINST 6919 SET_VREG(r0, r9) @ vAA<- r0 6920 GOTO_OPCODE(ip) @ jump to next instruction 6921 /* 10-12 instructions */ 6922 6923 6924/* ------------------------------ */ 6925 .balign 64 6926.L_OP_XOR_INT_LIT8: /* 0xdf */ 6927/* File: armv5te/OP_XOR_INT_LIT8.S */ 6928/* File: armv5te/binopLit8.S */ 6929 /* 6930 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6931 * that specifies an instruction that performs "result = r0 op r1". 6932 * This could be an ARM instruction or a function call. (If the result 6933 * comes back in a register other than r0, you can override "result".) 6934 * 6935 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6936 * vCC (r1). Useful for integer division and modulus. 6937 * 6938 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6939 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6940 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6941 */ 6942 /* binop/lit8 vAA, vBB, #+CC */ 6943 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6944 mov r9, rINST, lsr #8 @ r9<- AA 6945 and r2, r3, #255 @ r2<- BB 6946 GET_VREG(r0, r2) @ r0<- vBB 6947 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6948 .if 0 6949 @cmp r1, #0 @ is second operand zero? 6950 beq common_errDivideByZero 6951 .endif 6952 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6953 6954 @ optional op; may set condition codes 6955 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6956 GET_INST_OPCODE(ip) @ extract opcode from rINST 6957 SET_VREG(r0, r9) @ vAA<- r0 6958 GOTO_OPCODE(ip) @ jump to next instruction 6959 /* 10-12 instructions */ 6960 6961 6962/* ------------------------------ */ 6963 .balign 64 6964.L_OP_SHL_INT_LIT8: /* 0xe0 */ 6965/* File: armv5te/OP_SHL_INT_LIT8.S */ 6966/* File: armv5te/binopLit8.S */ 6967 /* 6968 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6969 * that specifies an instruction that performs "result = r0 op r1". 6970 * This could be an ARM instruction or a function call. (If the result 6971 * comes back in a register other than r0, you can override "result".) 6972 * 6973 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6974 * vCC (r1). Useful for integer division and modulus. 6975 * 6976 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6977 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6978 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6979 */ 6980 /* binop/lit8 vAA, vBB, #+CC */ 6981 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6982 mov r9, rINST, lsr #8 @ r9<- AA 6983 and r2, r3, #255 @ r2<- BB 6984 GET_VREG(r0, r2) @ r0<- vBB 6985 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6986 .if 0 6987 @cmp r1, #0 @ is second operand zero? 6988 beq common_errDivideByZero 6989 .endif 6990 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6991 6992 and r1, r1, #31 @ optional op; may set condition codes 6993 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 6994 GET_INST_OPCODE(ip) @ extract opcode from rINST 6995 SET_VREG(r0, r9) @ vAA<- r0 6996 GOTO_OPCODE(ip) @ jump to next instruction 6997 /* 10-12 instructions */ 6998 6999 7000/* ------------------------------ */ 7001 .balign 64 7002.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7003/* File: armv5te/OP_SHR_INT_LIT8.S */ 7004/* File: armv5te/binopLit8.S */ 7005 /* 7006 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7007 * that specifies an instruction that performs "result = r0 op r1". 7008 * This could be an ARM instruction or a function call. (If the result 7009 * comes back in a register other than r0, you can override "result".) 7010 * 7011 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7012 * vCC (r1). Useful for integer division and modulus. 7013 * 7014 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7015 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7016 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7017 */ 7018 /* binop/lit8 vAA, vBB, #+CC */ 7019 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7020 mov r9, rINST, lsr #8 @ r9<- AA 7021 and r2, r3, #255 @ r2<- BB 7022 GET_VREG(r0, r2) @ r0<- vBB 7023 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7024 .if 0 7025 @cmp r1, #0 @ is second operand zero? 7026 beq common_errDivideByZero 7027 .endif 7028 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7029 7030 and r1, r1, #31 @ optional op; may set condition codes 7031 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7032 GET_INST_OPCODE(ip) @ extract opcode from rINST 7033 SET_VREG(r0, r9) @ vAA<- r0 7034 GOTO_OPCODE(ip) @ jump to next instruction 7035 /* 10-12 instructions */ 7036 7037 7038/* ------------------------------ */ 7039 .balign 64 7040.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7041/* File: armv5te/OP_USHR_INT_LIT8.S */ 7042/* File: armv5te/binopLit8.S */ 7043 /* 7044 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7045 * that specifies an instruction that performs "result = r0 op r1". 7046 * This could be an ARM instruction or a function call. (If the result 7047 * comes back in a register other than r0, you can override "result".) 7048 * 7049 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7050 * vCC (r1). Useful for integer division and modulus. 7051 * 7052 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7053 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7054 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7055 */ 7056 /* binop/lit8 vAA, vBB, #+CC */ 7057 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7058 mov r9, rINST, lsr #8 @ r9<- AA 7059 and r2, r3, #255 @ r2<- BB 7060 GET_VREG(r0, r2) @ r0<- vBB 7061 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7062 .if 0 7063 @cmp r1, #0 @ is second operand zero? 7064 beq common_errDivideByZero 7065 .endif 7066 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7067 7068 and r1, r1, #31 @ optional op; may set condition codes 7069 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7070 GET_INST_OPCODE(ip) @ extract opcode from rINST 7071 SET_VREG(r0, r9) @ vAA<- r0 7072 GOTO_OPCODE(ip) @ jump to next instruction 7073 /* 10-12 instructions */ 7074 7075 7076/* ------------------------------ */ 7077 .balign 64 7078.L_OP_IGET_VOLATILE: /* 0xe3 */ 7079/* File: armv5te/OP_IGET_VOLATILE.S */ 7080/* File: armv5te/OP_IGET.S */ 7081 /* 7082 * General 32-bit instance field get. 7083 * 7084 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7085 */ 7086 /* op vA, vB, field@CCCC */ 7087 mov r0, rINST, lsr #12 @ r0<- B 7088 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7089 FETCH(r1, 1) @ r1<- field ref CCCC 7090 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7091 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7092 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7093 cmp r0, #0 @ is resolved entry null? 7094 bne .LOP_IGET_VOLATILE_finish @ no, already resolved 70958: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7096 EXPORT_PC() @ resolve() could throw 7097 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7098 bl dvmResolveInstField @ r0<- resolved InstField ptr 7099 cmp r0, #0 7100 bne .LOP_IGET_VOLATILE_finish 7101 b common_exceptionThrown 7102 7103 7104/* ------------------------------ */ 7105 .balign 64 7106.L_OP_IPUT_VOLATILE: /* 0xe4 */ 7107/* File: armv5te/OP_IPUT_VOLATILE.S */ 7108/* File: armv5te/OP_IPUT.S */ 7109 /* 7110 * General 32-bit instance field put. 7111 * 7112 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7113 */ 7114 /* op vA, vB, field@CCCC */ 7115 mov r0, rINST, lsr #12 @ r0<- B 7116 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7117 FETCH(r1, 1) @ r1<- field ref CCCC 7118 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7119 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7120 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7121 cmp r0, #0 @ is resolved entry null? 7122 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 71238: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7124 EXPORT_PC() @ resolve() could throw 7125 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7126 bl dvmResolveInstField @ r0<- resolved InstField ptr 7127 cmp r0, #0 @ success? 7128 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7129 b common_exceptionThrown 7130 7131 7132/* ------------------------------ */ 7133 .balign 64 7134.L_OP_SGET_VOLATILE: /* 0xe5 */ 7135/* File: armv5te/OP_SGET_VOLATILE.S */ 7136/* File: armv5te/OP_SGET.S */ 7137 /* 7138 * General 32-bit SGET handler. 7139 * 7140 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7141 */ 7142 /* op vAA, field@BBBB */ 7143 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7144 FETCH(r1, 1) @ r1<- field ref BBBB 7145 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7146 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7147 cmp r0, #0 @ is resolved entry null? 7148 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7149.LOP_SGET_VOLATILE_finish: @ field ptr in r0 7150 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7151 SMP_DMB @ acquiring load 7152 mov r2, rINST, lsr #8 @ r2<- AA 7153 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7154 SET_VREG(r1, r2) @ fp[AA]<- r1 7155 GET_INST_OPCODE(ip) @ extract opcode from rINST 7156 GOTO_OPCODE(ip) @ jump to next instruction 7157 7158 7159/* ------------------------------ */ 7160 .balign 64 7161.L_OP_SPUT_VOLATILE: /* 0xe6 */ 7162/* File: armv5te/OP_SPUT_VOLATILE.S */ 7163/* File: armv5te/OP_SPUT.S */ 7164 /* 7165 * General 32-bit SPUT handler. 7166 * 7167 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7168 */ 7169 /* op vAA, field@BBBB */ 7170 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7171 FETCH(r1, 1) @ r1<- field ref BBBB 7172 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7173 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7174 cmp r0, #0 @ is resolved entry null? 7175 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7176.LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7177 mov r2, rINST, lsr #8 @ r2<- AA 7178 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7179 GET_VREG(r1, r2) @ r1<- fp[AA] 7180 GET_INST_OPCODE(ip) @ extract opcode from rINST 7181 SMP_DMB @ releasing store 7182 str r1, [r0, #offStaticField_value] @ field<- vAA 7183 GOTO_OPCODE(ip) @ jump to next instruction 7184 7185 7186/* ------------------------------ */ 7187 .balign 64 7188.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7189/* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7190/* File: armv5te/OP_IGET.S */ 7191 /* 7192 * General 32-bit instance field get. 7193 * 7194 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7195 */ 7196 /* op vA, vB, field@CCCC */ 7197 mov r0, rINST, lsr #12 @ r0<- B 7198 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7199 FETCH(r1, 1) @ r1<- field ref CCCC 7200 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7201 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7202 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7203 cmp r0, #0 @ is resolved entry null? 7204 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 72058: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7206 EXPORT_PC() @ resolve() could throw 7207 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7208 bl dvmResolveInstField @ r0<- resolved InstField ptr 7209 cmp r0, #0 7210 bne .LOP_IGET_OBJECT_VOLATILE_finish 7211 b common_exceptionThrown 7212 7213 7214/* ------------------------------ */ 7215 .balign 64 7216.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 7217/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 7218/* File: armv5te/OP_IGET_WIDE.S */ 7219 /* 7220 * Wide 32-bit instance field get. 7221 */ 7222 /* iget-wide vA, vB, field@CCCC */ 7223 mov r0, rINST, lsr #12 @ r0<- B 7224 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7225 FETCH(r1, 1) @ r1<- field ref CCCC 7226 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7227 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7228 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7229 cmp r0, #0 @ is resolved entry null? 7230 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 72318: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7232 EXPORT_PC() @ resolve() could throw 7233 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7234 bl dvmResolveInstField @ r0<- resolved InstField ptr 7235 cmp r0, #0 7236 bne .LOP_IGET_WIDE_VOLATILE_finish 7237 b common_exceptionThrown 7238 7239 7240/* ------------------------------ */ 7241 .balign 64 7242.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 7243/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 7244/* File: armv5te/OP_IPUT_WIDE.S */ 7245 /* iput-wide vA, vB, field@CCCC */ 7246 mov r0, rINST, lsr #12 @ r0<- B 7247 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7248 FETCH(r1, 1) @ r1<- field ref CCCC 7249 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7250 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7251 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7252 cmp r0, #0 @ is resolved entry null? 7253 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 72548: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7255 EXPORT_PC() @ resolve() could throw 7256 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7257 bl dvmResolveInstField @ r0<- resolved InstField ptr 7258 cmp r0, #0 @ success? 7259 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 7260 b common_exceptionThrown 7261 7262 7263/* ------------------------------ */ 7264 .balign 64 7265.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 7266/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 7267/* File: armv5te/OP_SGET_WIDE.S */ 7268 /* 7269 * 64-bit SGET handler. 7270 */ 7271 /* sget-wide vAA, field@BBBB */ 7272 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7273 FETCH(r1, 1) @ r1<- field ref BBBB 7274 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7275 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7276 cmp r0, #0 @ is resolved entry null? 7277 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 7278.LOP_SGET_WIDE_VOLATILE_finish: 7279 mov r9, rINST, lsr #8 @ r9<- AA 7280 .if 1 7281 add r0, r0, #offStaticField_value @ r0<- pointer to data 7282 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7283 .else 7284 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7285 .endif 7286 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7287 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7288 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 7289 GET_INST_OPCODE(ip) @ extract opcode from rINST 7290 GOTO_OPCODE(ip) @ jump to next instruction 7291 7292 7293/* ------------------------------ */ 7294 .balign 64 7295.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 7296/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 7297/* File: armv5te/OP_SPUT_WIDE.S */ 7298 /* 7299 * 64-bit SPUT handler. 7300 */ 7301 /* sput-wide vAA, field@BBBB */ 7302 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 7303 FETCH(r1, 1) @ r1<- field ref BBBB 7304 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 7305 mov r9, rINST, lsr #8 @ r9<- AA 7306 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 7307 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7308 cmp r2, #0 @ is resolved entry null? 7309 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7310.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 7311 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7312 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7313 GET_INST_OPCODE(r10) @ extract opcode from rINST 7314 .if 1 7315 add r2, r2, #offStaticField_value @ r2<- pointer to data 7316 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 7317 .else 7318 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7319 .endif 7320 GOTO_OPCODE(r10) @ jump to next instruction 7321 7322 7323/* ------------------------------ */ 7324 .balign 64 7325.L_OP_BREAKPOINT: /* 0xec */ 7326/* File: armv5te/OP_BREAKPOINT.S */ 7327/* File: armv5te/unused.S */ 7328 bl common_abort 7329 7330 7331/* ------------------------------ */ 7332 .balign 64 7333.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7334/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7335 /* 7336 * Handle a throw-verification-error instruction. This throws an 7337 * exception for an error discovered during verification. The 7338 * exception is indicated by AA, with some detail provided by BBBB. 7339 */ 7340 /* op AA, ref@BBBB */ 7341 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 7342 FETCH(r2, 1) @ r2<- BBBB 7343 EXPORT_PC() @ export the PC 7344 mov r1, rINST, lsr #8 @ r1<- AA 7345 bl dvmThrowVerificationError @ always throws 7346 b common_exceptionThrown @ handle exception 7347 7348/* ------------------------------ */ 7349 .balign 64 7350.L_OP_EXECUTE_INLINE: /* 0xee */ 7351/* File: armv5te/OP_EXECUTE_INLINE.S */ 7352 /* 7353 * Execute a "native inline" instruction. 7354 * 7355 * We need to call an InlineOp4Func: 7356 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7357 * 7358 * The first four args are in r0-r3, pointer to return value storage 7359 * is on the stack. The function's return value is a flag that tells 7360 * us if an exception was thrown. 7361 */ 7362 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7363 FETCH(r10, 1) @ r10<- BBBB 7364 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7365 EXPORT_PC() @ can throw 7366 sub sp, sp, #8 @ make room for arg, +64 bit align 7367 mov r0, rINST, lsr #12 @ r0<- B 7368 str r1, [sp] @ push &self->retval 7369 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7370 add sp, sp, #8 @ pop stack 7371 cmp r0, #0 @ test boolean result of inline 7372 beq common_exceptionThrown @ returned false, handle exception 7373 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7374 GET_INST_OPCODE(ip) @ extract opcode from rINST 7375 GOTO_OPCODE(ip) @ jump to next instruction 7376 7377/* ------------------------------ */ 7378 .balign 64 7379.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7380/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7381 /* 7382 * Execute a "native inline" instruction, using "/range" semantics. 7383 * Same idea as execute-inline, but we get the args differently. 7384 * 7385 * We need to call an InlineOp4Func: 7386 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7387 * 7388 * The first four args are in r0-r3, pointer to return value storage 7389 * is on the stack. The function's return value is a flag that tells 7390 * us if an exception was thrown. 7391 */ 7392 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7393 FETCH(r10, 1) @ r10<- BBBB 7394 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7395 EXPORT_PC() @ can throw 7396 sub sp, sp, #8 @ make room for arg, +64 bit align 7397 mov r0, rINST, lsr #8 @ r0<- AA 7398 str r1, [sp] @ push &self->retval 7399 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7400 add sp, sp, #8 @ pop stack 7401 cmp r0, #0 @ test boolean result of inline 7402 beq common_exceptionThrown @ returned false, handle exception 7403 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7404 GET_INST_OPCODE(ip) @ extract opcode from rINST 7405 GOTO_OPCODE(ip) @ jump to next instruction 7406 7407/* ------------------------------ */ 7408 .balign 64 7409.L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 7410/* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */ 7411 /* 7412 * Invoke Object.<init> on an object. In practice we know that 7413 * Object's nullary constructor doesn't do anything, so we just 7414 * skip it (we know a debugger isn't active). 7415 */ 7416 FETCH(r1, 2) @ r1<- CCCC 7417 GET_VREG(r0, r1) @ r0<- "this" ptr 7418 cmp r0, #0 @ check for NULL 7419 beq common_errNullObject @ export PC and throw NPE 7420 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 7421 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 7422 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 7423 beq 1f @ nope, done 7424 EXPORT_PC() @ can throw 7425 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 74261: FETCH_ADVANCE_INST(2+1) @ advance to next instr, load rINST 7427 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7428 GOTO_OPCODE(ip) @ execute it 7429 7430/* ------------------------------ */ 7431 .balign 64 7432.L_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 7433/* File: armv5te/OP_RETURN_VOID_BARRIER.S */ 7434 SMP_DMB_ST 7435 b common_returnFromMethod 7436 7437/* ------------------------------ */ 7438 .balign 64 7439.L_OP_IGET_QUICK: /* 0xf2 */ 7440/* File: armv5te/OP_IGET_QUICK.S */ 7441 /* For: iget-quick, iget-object-quick */ 7442 /* op vA, vB, offset@CCCC */ 7443 mov r2, rINST, lsr #12 @ r2<- B 7444 GET_VREG(r3, r2) @ r3<- object we're operating on 7445 FETCH(r1, 1) @ r1<- field byte offset 7446 cmp r3, #0 @ check object for null 7447 mov r2, rINST, lsr #8 @ r2<- A(+) 7448 beq common_errNullObject @ object was null 7449 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7450 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7451 and r2, r2, #15 7452 GET_INST_OPCODE(ip) @ extract opcode from rINST 7453 SET_VREG(r0, r2) @ fp[A]<- r0 7454 GOTO_OPCODE(ip) @ jump to next instruction 7455 7456/* ------------------------------ */ 7457 .balign 64 7458.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7459/* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7460 /* iget-wide-quick vA, vB, offset@CCCC */ 7461 mov r2, rINST, lsr #12 @ r2<- B 7462 GET_VREG(r3, r2) @ r3<- object we're operating on 7463 FETCH(ip, 1) @ ip<- field byte offset 7464 cmp r3, #0 @ check object for null 7465 mov r2, rINST, lsr #8 @ r2<- A(+) 7466 beq common_errNullObject @ object was null 7467 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7468 and r2, r2, #15 7469 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7470 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7471 GET_INST_OPCODE(ip) @ extract opcode from rINST 7472 stmia r3, {r0-r1} @ fp[A]<- r0/r1 7473 GOTO_OPCODE(ip) @ jump to next instruction 7474 7475/* ------------------------------ */ 7476 .balign 64 7477.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7478/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7479/* File: armv5te/OP_IGET_QUICK.S */ 7480 /* For: iget-quick, iget-object-quick */ 7481 /* op vA, vB, offset@CCCC */ 7482 mov r2, rINST, lsr #12 @ r2<- B 7483 GET_VREG(r3, r2) @ r3<- object we're operating on 7484 FETCH(r1, 1) @ r1<- field byte offset 7485 cmp r3, #0 @ check object for null 7486 mov r2, rINST, lsr #8 @ r2<- A(+) 7487 beq common_errNullObject @ object was null 7488 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7489 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7490 and r2, r2, #15 7491 GET_INST_OPCODE(ip) @ extract opcode from rINST 7492 SET_VREG(r0, r2) @ fp[A]<- r0 7493 GOTO_OPCODE(ip) @ jump to next instruction 7494 7495 7496/* ------------------------------ */ 7497 .balign 64 7498.L_OP_IPUT_QUICK: /* 0xf5 */ 7499/* File: armv5te/OP_IPUT_QUICK.S */ 7500 /* For: iput-quick */ 7501 /* op vA, vB, offset@CCCC */ 7502 mov r2, rINST, lsr #12 @ r2<- B 7503 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7504 FETCH(r1, 1) @ r1<- field byte offset 7505 cmp r3, #0 @ check object for null 7506 mov r2, rINST, lsr #8 @ r2<- A(+) 7507 beq common_errNullObject @ object was null 7508 and r2, r2, #15 7509 GET_VREG(r0, r2) @ r0<- fp[A] 7510 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7511 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7512 GET_INST_OPCODE(ip) @ extract opcode from rINST 7513 GOTO_OPCODE(ip) @ jump to next instruction 7514 7515/* ------------------------------ */ 7516 .balign 64 7517.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7518/* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7519 /* iput-wide-quick vA, vB, offset@CCCC */ 7520 mov r0, rINST, lsr #8 @ r0<- A(+) 7521 mov r1, rINST, lsr #12 @ r1<- B 7522 and r0, r0, #15 7523 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7524 add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7525 cmp r2, #0 @ check object for null 7526 ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7527 beq common_errNullObject @ object was null 7528 FETCH(r3, 1) @ r3<- field byte offset 7529 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7530 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7531 GET_INST_OPCODE(ip) @ extract opcode from rINST 7532 GOTO_OPCODE(ip) @ jump to next instruction 7533 7534/* ------------------------------ */ 7535 .balign 64 7536.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7537/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7538 /* For: iput-object-quick */ 7539 /* op vA, vB, offset@CCCC */ 7540 mov r2, rINST, lsr #12 @ r2<- B 7541 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7542 FETCH(r1, 1) @ r1<- field byte offset 7543 cmp r3, #0 @ check object for null 7544 mov r2, rINST, lsr #8 @ r2<- A(+) 7545 beq common_errNullObject @ object was null 7546 and r2, r2, #15 7547 GET_VREG(r0, r2) @ r0<- fp[A] 7548 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 7549 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7550 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7551 cmp r0, #0 7552 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head 7553 GET_INST_OPCODE(ip) @ extract opcode from rINST 7554 GOTO_OPCODE(ip) @ jump to next instruction 7555 7556/* ------------------------------ */ 7557 .balign 64 7558.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7559/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7560 /* 7561 * Handle an optimized virtual method call. 7562 * 7563 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7564 */ 7565 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7566 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7567 FETCH(r3, 2) @ r3<- FEDC or CCCC 7568 FETCH(r1, 1) @ r1<- BBBB 7569 .if (!0) 7570 and r3, r3, #15 @ r3<- C (or stays CCCC) 7571 .endif 7572 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7573 cmp r2, #0 @ is "this" null? 7574 beq common_errNullObject @ null "this", throw exception 7575 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7576 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7577 EXPORT_PC() @ invoke must export 7578 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7579 bl common_invokeMethodNoRange @ continue on 7580 7581/* ------------------------------ */ 7582 .balign 64 7583.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7584/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7585/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7586 /* 7587 * Handle an optimized virtual method call. 7588 * 7589 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7590 */ 7591 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7592 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7593 FETCH(r3, 2) @ r3<- FEDC or CCCC 7594 FETCH(r1, 1) @ r1<- BBBB 7595 .if (!1) 7596 and r3, r3, #15 @ r3<- C (or stays CCCC) 7597 .endif 7598 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7599 cmp r2, #0 @ is "this" null? 7600 beq common_errNullObject @ null "this", throw exception 7601 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7602 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7603 EXPORT_PC() @ invoke must export 7604 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7605 bl common_invokeMethodRange @ continue on 7606 7607 7608/* ------------------------------ */ 7609 .balign 64 7610.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7611/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7612 /* 7613 * Handle an optimized "super" method call. 7614 * 7615 * for: [opt] invoke-super-quick, invoke-super-quick/range 7616 */ 7617 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7618 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7619 FETCH(r10, 2) @ r10<- GFED or CCCC 7620 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7621 .if (!0) 7622 and r10, r10, #15 @ r10<- D (or stays CCCC) 7623 .endif 7624 FETCH(r1, 1) @ r1<- BBBB 7625 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7626 EXPORT_PC() @ must export for invoke 7627 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7628 GET_VREG(r3, r10) @ r3<- "this" 7629 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7630 cmp r3, #0 @ null "this" ref? 7631 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7632 beq common_errNullObject @ "this" is null, throw exception 7633 bl common_invokeMethodNoRange @ continue on 7634 7635/* ------------------------------ */ 7636 .balign 64 7637.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7638/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7639/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7640 /* 7641 * Handle an optimized "super" method call. 7642 * 7643 * for: [opt] invoke-super-quick, invoke-super-quick/range 7644 */ 7645 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7646 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7647 FETCH(r10, 2) @ r10<- GFED or CCCC 7648 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7649 .if (!1) 7650 and r10, r10, #15 @ r10<- D (or stays CCCC) 7651 .endif 7652 FETCH(r1, 1) @ r1<- BBBB 7653 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7654 EXPORT_PC() @ must export for invoke 7655 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7656 GET_VREG(r3, r10) @ r3<- "this" 7657 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7658 cmp r3, #0 @ null "this" ref? 7659 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7660 beq common_errNullObject @ "this" is null, throw exception 7661 bl common_invokeMethodRange @ continue on 7662 7663 7664/* ------------------------------ */ 7665 .balign 64 7666.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7667/* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7668/* File: armv5te/OP_IPUT_OBJECT.S */ 7669 /* 7670 * 32-bit instance field put. 7671 * 7672 * for: iput-object, iput-object-volatile 7673 */ 7674 /* op vA, vB, field@CCCC */ 7675 mov r0, rINST, lsr #12 @ r0<- B 7676 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7677 FETCH(r1, 1) @ r1<- field ref CCCC 7678 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7679 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7680 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7681 cmp r0, #0 @ is resolved entry null? 7682 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 76838: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7684 EXPORT_PC() @ resolve() could throw 7685 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7686 bl dvmResolveInstField @ r0<- resolved InstField ptr 7687 cmp r0, #0 @ success? 7688 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 7689 b common_exceptionThrown 7690 7691 7692/* ------------------------------ */ 7693 .balign 64 7694.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 7695/* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 7696/* File: armv5te/OP_SGET.S */ 7697 /* 7698 * General 32-bit SGET handler. 7699 * 7700 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7701 */ 7702 /* op vAA, field@BBBB */ 7703 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7704 FETCH(r1, 1) @ r1<- field ref BBBB 7705 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7706 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7707 cmp r0, #0 @ is resolved entry null? 7708 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 7709.LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 7710 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7711 SMP_DMB @ acquiring load 7712 mov r2, rINST, lsr #8 @ r2<- AA 7713 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7714 SET_VREG(r1, r2) @ fp[AA]<- r1 7715 GET_INST_OPCODE(ip) @ extract opcode from rINST 7716 GOTO_OPCODE(ip) @ jump to next instruction 7717 7718 7719/* ------------------------------ */ 7720 .balign 64 7721.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 7722/* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 7723/* File: armv5te/OP_SPUT_OBJECT.S */ 7724 /* 7725 * 32-bit SPUT handler for objects 7726 * 7727 * for: sput-object, sput-object-volatile 7728 */ 7729 /* op vAA, field@BBBB */ 7730 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7731 FETCH(r1, 1) @ r1<- field ref BBBB 7732 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7733 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7734 cmp r0, #0 @ is resolved entry null? 7735 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue 7736 ldr r9, [rSELF, #offThread_method] @ r9<- current method 7737 EXPORT_PC() @ resolve() could throw, so export now 7738 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 7739 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 7740 cmp r0, #0 @ success? 7741 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish 7742 b common_exceptionThrown @ no, handle exception 7743 7744 7745 7746/* ------------------------------ */ 7747 .balign 64 7748.L_OP_DISPATCH_FF: /* 0xff */ 7749/* File: armv5te/OP_DISPATCH_FF.S */ 7750 mov ip, rINST, lsr #8 @ ip<- extended opcode 7751 add ip, ip, #256 @ add offset for extended opcodes 7752 GOTO_OPCODE(ip) @ go to proper extended handler 7753 7754 7755/* ------------------------------ */ 7756 .balign 64 7757.L_OP_CONST_CLASS_JUMBO: /* 0x100 */ 7758/* File: armv5te/OP_CONST_CLASS_JUMBO.S */ 7759 /* const-class/jumbo vBBBB, Class@AAAAAAAA */ 7760 FETCH(r0, 1) @ r0<- aaaa (lo) 7761 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex 7762 FETCH(r1, 2) @ r1<- AAAA (hi) 7763 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 7764 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7765 FETCH(r9, 3) @ r9<- BBBB 7766 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa] 7767 cmp r0, #0 @ not yet resolved? 7768 beq .LOP_CONST_CLASS_JUMBO_resolve 7769 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 7770 GET_INST_OPCODE(ip) @ extract opcode from rINST 7771 SET_VREG(r0, r9) @ vBBBB<- r0 7772 GOTO_OPCODE(ip) @ jump to next instruction 7773 7774/* ------------------------------ */ 7775 .balign 64 7776.L_OP_CHECK_CAST_JUMBO: /* 0x101 */ 7777/* File: armv5te/OP_CHECK_CAST_JUMBO.S */ 7778 /* 7779 * Check to see if a cast from one class to another is allowed. 7780 */ 7781 /* check-cast/jumbo vBBBB, class@AAAAAAAA */ 7782 FETCH(r0, 1) @ r0<- aaaa (lo) 7783 FETCH(r2, 2) @ r2<- AAAA (hi) 7784 FETCH(r3, 3) @ r3<- BBBB 7785 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa 7786 GET_VREG(r9, r3) @ r9<- object 7787 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 7788 cmp r9, #0 @ is object null? 7789 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 7790 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds 7791 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 7792 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7793 cmp r1, #0 @ have we resolved this before? 7794 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now 7795.LOP_CHECK_CAST_JUMBO_resolved: 7796 cmp r0, r1 @ same class (trivial success)? 7797 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check 7798 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up 7799 7800/* ------------------------------ */ 7801 .balign 64 7802.L_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 7803/* File: armv5te/OP_INSTANCE_OF_JUMBO.S */ 7804 /* 7805 * Check to see if an object reference is an instance of a class. 7806 * 7807 * Most common situation is a non-null object, being compared against 7808 * an already-resolved class. 7809 * 7810 * TODO: convert most of this into a common subroutine, shared with 7811 * OP_INSTANCE_OF.S. 7812 */ 7813 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7814 FETCH(r3, 4) @ r3<- vCCCC 7815 FETCH(r9, 3) @ r9<- vBBBB 7816 GET_VREG(r0, r3) @ r0<- vCCCC (object) 7817 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 7818 cmp r0, #0 @ is object null? 7819 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0 7820 FETCH(r1, 1) @ r1<- aaaa (lo) 7821 FETCH(r3, 2) @ r3<- AAAA (hi) 7822 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 7823 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa 7824 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 7825 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7826 cmp r1, #0 @ have we resolved this before? 7827 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now 7828 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue 7829 7830/* ------------------------------ */ 7831 .balign 64 7832.L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 7833/* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */ 7834 /* 7835 * Create a new instance of a class. 7836 */ 7837 /* new-instance/jumbo vBBBB, class@AAAAAAAA */ 7838 FETCH(r0, 1) @ r0<- aaaa (lo) 7839 FETCH(r1, 2) @ r1<- AAAA (hi) 7840 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7841 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7842 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7843 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7844 EXPORT_PC() @ req'd for init, resolve, alloc 7845 cmp r0, #0 @ already resolved? 7846 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now 7847.LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class 7848 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 7849 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 7850 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now 7851.LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class 7852 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 7853 bl dvmAllocObject @ r0<- new object 7854 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue 7855 7856/* ------------------------------ */ 7857 .balign 64 7858.L_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 7859/* File: armv5te/OP_NEW_ARRAY_JUMBO.S */ 7860 /* 7861 * Allocate an array of objects, specified with the array class 7862 * and a count. 7863 * 7864 * The verifier guarantees that this is an array class, so we don't 7865 * check for it here. 7866 */ 7867 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7868 FETCH(r2, 1) @ r2<- aaaa (lo) 7869 FETCH(r3, 2) @ r3<- AAAA (hi) 7870 FETCH(r0, 4) @ r0<- vCCCC 7871 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa 7872 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7873 GET_VREG(r1, r0) @ r1<- vCCCC (array length) 7874 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7875 cmp r1, #0 @ check length 7876 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 7877 bmi common_errNegativeArraySize @ negative length, bail - len in r1 7878 cmp r0, #0 @ already resolved? 7879 EXPORT_PC() @ req'd for resolve, alloc 7880 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue 7881 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now 7882 7883/* ------------------------------ */ 7884 .balign 64 7885.L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 7886/* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */ 7887 /* 7888 * Create a new array with elements filled from registers. 7889 * 7890 * TODO: convert most of this into a common subroutine, shared with 7891 * OP_FILLED_NEW_ARRAY.S. 7892 */ 7893 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */ 7894 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7895 FETCH(r0, 1) @ r0<- aaaa (lo) 7896 FETCH(r1, 2) @ r1<- AAAA (hi) 7897 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7898 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7899 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7900 EXPORT_PC() @ need for resolve and alloc 7901 cmp r0, #0 @ already resolved? 7902 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on 79038: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 7904 mov r2, #0 @ r2<- false 7905 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7906 bl dvmResolveClass @ r0<- call(clazz, ref) 7907 cmp r0, #0 @ got null? 7908 beq common_exceptionThrown @ yes, handle exception 7909 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue 7910 7911/* ------------------------------ */ 7912 .balign 64 7913.L_OP_IGET_JUMBO: /* 0x106 */ 7914/* File: armv5te/OP_IGET_JUMBO.S */ 7915 /* 7916 * Jumbo 32-bit instance field get. 7917 * 7918 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7919 * iget-char/jumbo, iget-short/jumbo 7920 */ 7921 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7922 FETCH(r1, 1) @ r1<- aaaa (lo) 7923 FETCH(r2, 2) @ r2<- AAAA (hi) 7924 FETCH(r0, 4) @ r0<- CCCC 7925 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7926 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7927 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7928 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7929 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7930 cmp r0, #0 @ is resolved entry null? 7931 bne .LOP_IGET_JUMBO_finish @ no, already resolved 79328: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7933 EXPORT_PC() @ resolve() could throw 7934 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7935 bl dvmResolveInstField @ r0<- resolved InstField ptr 7936 b .LOP_IGET_JUMBO_resolved @ resolved, continue 7937 7938/* ------------------------------ */ 7939 .balign 64 7940.L_OP_IGET_WIDE_JUMBO: /* 0x107 */ 7941/* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 7942 /* 7943 * Jumbo 64-bit instance field get. 7944 */ 7945 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 7946 FETCH(r1, 1) @ r1<- aaaa (lo) 7947 FETCH(r2, 2) @ r2<- AAAA (hi) 7948 FETCH(r0, 4) @ r0<- CCCC 7949 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7950 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7951 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7952 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7953 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7954 cmp r0, #0 @ is resolved entry null? 7955 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved 7956 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7957 EXPORT_PC() @ resolve() could throw 7958 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7959 bl dvmResolveInstField @ r0<- resolved InstField ptr 7960 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue 7961 7962/* ------------------------------ */ 7963 .balign 64 7964.L_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 7965/* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 7966/* File: armv5te/OP_IGET_JUMBO.S */ 7967 /* 7968 * Jumbo 32-bit instance field get. 7969 * 7970 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7971 * iget-char/jumbo, iget-short/jumbo 7972 */ 7973 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7974 FETCH(r1, 1) @ r1<- aaaa (lo) 7975 FETCH(r2, 2) @ r2<- AAAA (hi) 7976 FETCH(r0, 4) @ r0<- CCCC 7977 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7978 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7979 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7980 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7981 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7982 cmp r0, #0 @ is resolved entry null? 7983 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved 79848: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7985 EXPORT_PC() @ resolve() could throw 7986 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7987 bl dvmResolveInstField @ r0<- resolved InstField ptr 7988 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue 7989 7990 7991/* ------------------------------ */ 7992 .balign 64 7993.L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 7994/* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */ 7995@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" } 7996/* File: armv5te/OP_IGET_JUMBO.S */ 7997 /* 7998 * Jumbo 32-bit instance field get. 7999 * 8000 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8001 * iget-char/jumbo, iget-short/jumbo 8002 */ 8003 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8004 FETCH(r1, 1) @ r1<- aaaa (lo) 8005 FETCH(r2, 2) @ r2<- AAAA (hi) 8006 FETCH(r0, 4) @ r0<- CCCC 8007 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8008 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8009 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8010 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8011 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8012 cmp r0, #0 @ is resolved entry null? 8013 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved 80148: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8015 EXPORT_PC() @ resolve() could throw 8016 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8017 bl dvmResolveInstField @ r0<- resolved InstField ptr 8018 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue 8019 8020 8021/* ------------------------------ */ 8022 .balign 64 8023.L_OP_IGET_BYTE_JUMBO: /* 0x10a */ 8024/* File: armv5te/OP_IGET_BYTE_JUMBO.S */ 8025@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" } 8026/* File: armv5te/OP_IGET_JUMBO.S */ 8027 /* 8028 * Jumbo 32-bit instance field get. 8029 * 8030 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8031 * iget-char/jumbo, iget-short/jumbo 8032 */ 8033 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8034 FETCH(r1, 1) @ r1<- aaaa (lo) 8035 FETCH(r2, 2) @ r2<- AAAA (hi) 8036 FETCH(r0, 4) @ r0<- CCCC 8037 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8038 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8039 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8040 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8041 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8042 cmp r0, #0 @ is resolved entry null? 8043 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved 80448: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8045 EXPORT_PC() @ resolve() could throw 8046 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8047 bl dvmResolveInstField @ r0<- resolved InstField ptr 8048 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue 8049 8050 8051/* ------------------------------ */ 8052 .balign 64 8053.L_OP_IGET_CHAR_JUMBO: /* 0x10b */ 8054/* File: armv5te/OP_IGET_CHAR_JUMBO.S */ 8055@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" } 8056/* File: armv5te/OP_IGET_JUMBO.S */ 8057 /* 8058 * Jumbo 32-bit instance field get. 8059 * 8060 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8061 * iget-char/jumbo, iget-short/jumbo 8062 */ 8063 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8064 FETCH(r1, 1) @ r1<- aaaa (lo) 8065 FETCH(r2, 2) @ r2<- AAAA (hi) 8066 FETCH(r0, 4) @ r0<- CCCC 8067 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8068 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8069 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8070 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8071 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8072 cmp r0, #0 @ is resolved entry null? 8073 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved 80748: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8075 EXPORT_PC() @ resolve() could throw 8076 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8077 bl dvmResolveInstField @ r0<- resolved InstField ptr 8078 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue 8079 8080 8081/* ------------------------------ */ 8082 .balign 64 8083.L_OP_IGET_SHORT_JUMBO: /* 0x10c */ 8084/* File: armv5te/OP_IGET_SHORT_JUMBO.S */ 8085@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" } 8086/* File: armv5te/OP_IGET_JUMBO.S */ 8087 /* 8088 * Jumbo 32-bit instance field get. 8089 * 8090 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8091 * iget-char/jumbo, iget-short/jumbo 8092 */ 8093 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8094 FETCH(r1, 1) @ r1<- aaaa (lo) 8095 FETCH(r2, 2) @ r2<- AAAA (hi) 8096 FETCH(r0, 4) @ r0<- CCCC 8097 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8098 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8099 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8100 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8101 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8102 cmp r0, #0 @ is resolved entry null? 8103 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved 81048: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8105 EXPORT_PC() @ resolve() could throw 8106 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8107 bl dvmResolveInstField @ r0<- resolved InstField ptr 8108 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue 8109 8110 8111/* ------------------------------ */ 8112 .balign 64 8113.L_OP_IPUT_JUMBO: /* 0x10d */ 8114/* File: armv5te/OP_IPUT_JUMBO.S */ 8115 /* 8116 * Jumbo 32-bit instance field put. 8117 * 8118 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8119 * iput-short/jumbo 8120 */ 8121 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8122 FETCH(r1, 1) @ r1<- aaaa (lo) 8123 FETCH(r2, 2) @ r2<- AAAA (hi) 8124 FETCH(r0, 4) @ r0<- CCCC 8125 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8126 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8127 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8128 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8129 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8130 cmp r0, #0 @ is resolved entry null? 8131 bne .LOP_IPUT_JUMBO_finish @ no, already resolved 81328: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8133 EXPORT_PC() @ resolve() could throw 8134 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8135 bl dvmResolveInstField @ r0<- resolved InstField ptr 8136 b .LOP_IPUT_JUMBO_resolved @ resolved, continue 8137 8138/* ------------------------------ */ 8139 .balign 64 8140.L_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 8141/* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 8142 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8143 FETCH(r1, 1) @ r1<- aaaa (lo) 8144 FETCH(r2, 2) @ r2<- AAAA (hi) 8145 FETCH(r0, 4) @ r0<- CCCC 8146 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8147 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8148 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 8149 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 8150 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8151 cmp r0, #0 @ is resolved entry null? 8152 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved 81538: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8154 EXPORT_PC() @ resolve() could throw 8155 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8156 bl dvmResolveInstField @ r0<- resolved InstField ptr 8157 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue 8158 8159/* ------------------------------ */ 8160 .balign 64 8161.L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 8162/* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 8163 /* 8164 * Jumbo 32-bit instance field put. 8165 */ 8166 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8167 FETCH(r1, 1) @ r1<- aaaa (lo) 8168 FETCH(r2, 2) @ r2<- AAAA (hi) 8169 FETCH(r0, 4) @ r0<- CCCC 8170 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8171 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8172 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8173 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8174 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8175 cmp r0, #0 @ is resolved entry null? 8176 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved 81778: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8178 EXPORT_PC() @ resolve() could throw 8179 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8180 bl dvmResolveInstField @ r0<- resolved InstField ptr 8181 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue 8182 8183/* ------------------------------ */ 8184 .balign 64 8185.L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 8186/* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */ 8187@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" } 8188/* File: armv5te/OP_IPUT_JUMBO.S */ 8189 /* 8190 * Jumbo 32-bit instance field put. 8191 * 8192 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8193 * iput-short/jumbo 8194 */ 8195 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8196 FETCH(r1, 1) @ r1<- aaaa (lo) 8197 FETCH(r2, 2) @ r2<- AAAA (hi) 8198 FETCH(r0, 4) @ r0<- CCCC 8199 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8200 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8201 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8202 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8203 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8204 cmp r0, #0 @ is resolved entry null? 8205 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved 82068: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8207 EXPORT_PC() @ resolve() could throw 8208 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8209 bl dvmResolveInstField @ r0<- resolved InstField ptr 8210 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue 8211 8212 8213/* ------------------------------ */ 8214 .balign 64 8215.L_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 8216/* File: armv5te/OP_IPUT_BYTE_JUMBO.S */ 8217@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" } 8218/* File: armv5te/OP_IPUT_JUMBO.S */ 8219 /* 8220 * Jumbo 32-bit instance field put. 8221 * 8222 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8223 * iput-short/jumbo 8224 */ 8225 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8226 FETCH(r1, 1) @ r1<- aaaa (lo) 8227 FETCH(r2, 2) @ r2<- AAAA (hi) 8228 FETCH(r0, 4) @ r0<- CCCC 8229 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8230 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8231 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8232 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8233 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8234 cmp r0, #0 @ is resolved entry null? 8235 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved 82368: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8237 EXPORT_PC() @ resolve() could throw 8238 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8239 bl dvmResolveInstField @ r0<- resolved InstField ptr 8240 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue 8241 8242 8243/* ------------------------------ */ 8244 .balign 64 8245.L_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 8246/* File: armv5te/OP_IPUT_CHAR_JUMBO.S */ 8247@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" } 8248/* File: armv5te/OP_IPUT_JUMBO.S */ 8249 /* 8250 * Jumbo 32-bit instance field put. 8251 * 8252 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8253 * iput-short/jumbo 8254 */ 8255 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8256 FETCH(r1, 1) @ r1<- aaaa (lo) 8257 FETCH(r2, 2) @ r2<- AAAA (hi) 8258 FETCH(r0, 4) @ r0<- CCCC 8259 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8260 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8261 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8262 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8263 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8264 cmp r0, #0 @ is resolved entry null? 8265 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved 82668: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8267 EXPORT_PC() @ resolve() could throw 8268 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8269 bl dvmResolveInstField @ r0<- resolved InstField ptr 8270 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue 8271 8272 8273/* ------------------------------ */ 8274 .balign 64 8275.L_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 8276/* File: armv5te/OP_IPUT_SHORT_JUMBO.S */ 8277@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" } 8278/* File: armv5te/OP_IPUT_JUMBO.S */ 8279 /* 8280 * Jumbo 32-bit instance field put. 8281 * 8282 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8283 * iput-short/jumbo 8284 */ 8285 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8286 FETCH(r1, 1) @ r1<- aaaa (lo) 8287 FETCH(r2, 2) @ r2<- AAAA (hi) 8288 FETCH(r0, 4) @ r0<- CCCC 8289 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8290 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8291 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8292 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8293 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8294 cmp r0, #0 @ is resolved entry null? 8295 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved 82968: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8297 EXPORT_PC() @ resolve() could throw 8298 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8299 bl dvmResolveInstField @ r0<- resolved InstField ptr 8300 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue 8301 8302 8303/* ------------------------------ */ 8304 .balign 64 8305.L_OP_SGET_JUMBO: /* 0x114 */ 8306/* File: armv5te/OP_SGET_JUMBO.S */ 8307 /* 8308 * Jumbo 32-bit SGET handler. 8309 * 8310 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8311 * sget-char/jumbo, sget-short/jumbo 8312 */ 8313 /* exop vBBBB, field@AAAAAAAA */ 8314 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8315 FETCH(r0, 1) @ r0<- aaaa (lo) 8316 FETCH(r1, 2) @ r1<- AAAA (hi) 8317 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8318 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8319 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8320 cmp r0, #0 @ is resolved entry null? 8321 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve 8322.LOP_SGET_JUMBO_finish: @ field ptr in r0 8323 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8324 @ no-op @ acquiring load 8325 FETCH(r2, 3) @ r2<- BBBB 8326 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8327 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8328 GET_INST_OPCODE(ip) @ extract opcode from rINST 8329 GOTO_OPCODE(ip) @ jump to next instruction 8330 8331/* ------------------------------ */ 8332 .balign 64 8333.L_OP_SGET_WIDE_JUMBO: /* 0x115 */ 8334/* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 8335 /* 8336 * Jumbo 64-bit SGET handler. 8337 */ 8338 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 8339 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8340 FETCH(r0, 1) @ r0<- aaaa (lo) 8341 FETCH(r1, 2) @ r1<- AAAA (hi) 8342 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8343 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8344 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8345 cmp r0, #0 @ is resolved entry null? 8346 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve 8347.LOP_SGET_WIDE_JUMBO_finish: 8348 FETCH(r9, 3) @ r9<- BBBB 8349 .if 0 8350 add r0, r0, #offStaticField_value @ r0<- pointer to data 8351 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 8352 .else 8353 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 8354 .endif 8355 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8356 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8357 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 8358 GET_INST_OPCODE(ip) @ extract opcode from rINST 8359 GOTO_OPCODE(ip) @ jump to next instruction 8360 8361/* ------------------------------ */ 8362 .balign 64 8363.L_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 8364/* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 8365/* File: armv5te/OP_SGET_JUMBO.S */ 8366 /* 8367 * Jumbo 32-bit SGET handler. 8368 * 8369 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8370 * sget-char/jumbo, sget-short/jumbo 8371 */ 8372 /* exop vBBBB, field@AAAAAAAA */ 8373 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8374 FETCH(r0, 1) @ r0<- aaaa (lo) 8375 FETCH(r1, 2) @ r1<- AAAA (hi) 8376 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8377 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8378 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8379 cmp r0, #0 @ is resolved entry null? 8380 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve 8381.LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0 8382 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8383 @ no-op @ acquiring load 8384 FETCH(r2, 3) @ r2<- BBBB 8385 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8386 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8387 GET_INST_OPCODE(ip) @ extract opcode from rINST 8388 GOTO_OPCODE(ip) @ jump to next instruction 8389 8390 8391/* ------------------------------ */ 8392 .balign 64 8393.L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 8394/* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */ 8395/* File: armv5te/OP_SGET_JUMBO.S */ 8396 /* 8397 * Jumbo 32-bit SGET handler. 8398 * 8399 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8400 * sget-char/jumbo, sget-short/jumbo 8401 */ 8402 /* exop vBBBB, field@AAAAAAAA */ 8403 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8404 FETCH(r0, 1) @ r0<- aaaa (lo) 8405 FETCH(r1, 2) @ r1<- AAAA (hi) 8406 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8407 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8408 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8409 cmp r0, #0 @ is resolved entry null? 8410 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve 8411.LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0 8412 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8413 @ no-op @ acquiring load 8414 FETCH(r2, 3) @ r2<- BBBB 8415 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8416 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8417 GET_INST_OPCODE(ip) @ extract opcode from rINST 8418 GOTO_OPCODE(ip) @ jump to next instruction 8419 8420 8421/* ------------------------------ */ 8422 .balign 64 8423.L_OP_SGET_BYTE_JUMBO: /* 0x118 */ 8424/* File: armv5te/OP_SGET_BYTE_JUMBO.S */ 8425/* File: armv5te/OP_SGET_JUMBO.S */ 8426 /* 8427 * Jumbo 32-bit SGET handler. 8428 * 8429 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8430 * sget-char/jumbo, sget-short/jumbo 8431 */ 8432 /* exop vBBBB, field@AAAAAAAA */ 8433 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8434 FETCH(r0, 1) @ r0<- aaaa (lo) 8435 FETCH(r1, 2) @ r1<- AAAA (hi) 8436 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8437 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8438 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8439 cmp r0, #0 @ is resolved entry null? 8440 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve 8441.LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0 8442 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8443 @ no-op @ acquiring load 8444 FETCH(r2, 3) @ r2<- BBBB 8445 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8446 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8447 GET_INST_OPCODE(ip) @ extract opcode from rINST 8448 GOTO_OPCODE(ip) @ jump to next instruction 8449 8450 8451/* ------------------------------ */ 8452 .balign 64 8453.L_OP_SGET_CHAR_JUMBO: /* 0x119 */ 8454/* File: armv5te/OP_SGET_CHAR_JUMBO.S */ 8455/* File: armv5te/OP_SGET_JUMBO.S */ 8456 /* 8457 * Jumbo 32-bit SGET handler. 8458 * 8459 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8460 * sget-char/jumbo, sget-short/jumbo 8461 */ 8462 /* exop vBBBB, field@AAAAAAAA */ 8463 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8464 FETCH(r0, 1) @ r0<- aaaa (lo) 8465 FETCH(r1, 2) @ r1<- AAAA (hi) 8466 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8467 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8468 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8469 cmp r0, #0 @ is resolved entry null? 8470 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve 8471.LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0 8472 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8473 @ no-op @ acquiring load 8474 FETCH(r2, 3) @ r2<- BBBB 8475 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8476 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8477 GET_INST_OPCODE(ip) @ extract opcode from rINST 8478 GOTO_OPCODE(ip) @ jump to next instruction 8479 8480 8481/* ------------------------------ */ 8482 .balign 64 8483.L_OP_SGET_SHORT_JUMBO: /* 0x11a */ 8484/* File: armv5te/OP_SGET_SHORT_JUMBO.S */ 8485/* File: armv5te/OP_SGET_JUMBO.S */ 8486 /* 8487 * Jumbo 32-bit SGET handler. 8488 * 8489 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8490 * sget-char/jumbo, sget-short/jumbo 8491 */ 8492 /* exop vBBBB, field@AAAAAAAA */ 8493 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8494 FETCH(r0, 1) @ r0<- aaaa (lo) 8495 FETCH(r1, 2) @ r1<- AAAA (hi) 8496 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8497 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8498 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8499 cmp r0, #0 @ is resolved entry null? 8500 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve 8501.LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0 8502 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8503 @ no-op @ acquiring load 8504 FETCH(r2, 3) @ r2<- BBBB 8505 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8506 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8507 GET_INST_OPCODE(ip) @ extract opcode from rINST 8508 GOTO_OPCODE(ip) @ jump to next instruction 8509 8510 8511/* ------------------------------ */ 8512 .balign 64 8513.L_OP_SPUT_JUMBO: /* 0x11b */ 8514/* File: armv5te/OP_SPUT_JUMBO.S */ 8515 /* 8516 * Jumbo 32-bit SPUT handler. 8517 * 8518 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8519 * sput-short/jumbo 8520 */ 8521 /* exop vBBBB, field@AAAAAAAA */ 8522 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8523 FETCH(r0, 1) @ r0<- aaaa (lo) 8524 FETCH(r1, 2) @ r1<- AAAA (hi) 8525 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8526 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8527 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8528 cmp r0, #0 @ is resolved entry null? 8529 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve 8530.LOP_SPUT_JUMBO_finish: @ field ptr in r0 8531 FETCH(r2, 3) @ r2<- BBBB 8532 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8533 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8534 GET_INST_OPCODE(ip) @ extract opcode from rINST 8535 @ no-op @ releasing store 8536 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8537 GOTO_OPCODE(ip) @ jump to next instruction 8538 8539/* ------------------------------ */ 8540 .balign 64 8541.L_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 8542/* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 8543 /* 8544 * Jumbo 64-bit SPUT handler. 8545 */ 8546 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 8547 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 8548 FETCH(r1, 1) @ r1<- aaaa (lo) 8549 FETCH(r2, 2) @ r2<- AAAA (hi) 8550 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 8551 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8552 FETCH(r9, 3) @ r9<- BBBB 8553 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 8554 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8555 cmp r2, #0 @ is resolved entry null? 8556 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve 8557.LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9 8558 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8559 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 8560 GET_INST_OPCODE(r10) @ extract opcode from rINST 8561 .if 0 8562 add r2, r2, #offStaticField_value @ r2<- pointer to data 8563 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 8564 .else 8565 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 8566 .endif 8567 GOTO_OPCODE(r10) @ jump to next instruction 8568 8569/* ------------------------------ */ 8570 .balign 64 8571.L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 8572/* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 8573 /* 8574 * Jumbo 32-bit SPUT handler for objects 8575 */ 8576 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 8577 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8578 FETCH(r0, 1) @ r0<- aaaa (lo) 8579 FETCH(r1, 2) @ r1<- AAAA (hi) 8580 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8581 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8582 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8583 cmp r0, #0 @ is resolved entry null? 8584 bne .LOP_SPUT_OBJECT_JUMBO_finish @ no, continue 8585 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8586 EXPORT_PC() @ resolve() could throw, so export now 8587 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 8588 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8589 cmp r0, #0 @ success? 8590 bne .LOP_SPUT_OBJECT_JUMBO_finish @ yes, finish 8591 b common_exceptionThrown @ no, handle exception 8592 8593/* ------------------------------ */ 8594 .balign 64 8595.L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 8596/* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */ 8597/* File: armv5te/OP_SPUT_JUMBO.S */ 8598 /* 8599 * Jumbo 32-bit SPUT handler. 8600 * 8601 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8602 * sput-short/jumbo 8603 */ 8604 /* exop vBBBB, field@AAAAAAAA */ 8605 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8606 FETCH(r0, 1) @ r0<- aaaa (lo) 8607 FETCH(r1, 2) @ r1<- AAAA (hi) 8608 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8609 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8610 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8611 cmp r0, #0 @ is resolved entry null? 8612 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve 8613.LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0 8614 FETCH(r2, 3) @ r2<- BBBB 8615 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8616 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8617 GET_INST_OPCODE(ip) @ extract opcode from rINST 8618 @ no-op @ releasing store 8619 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8620 GOTO_OPCODE(ip) @ jump to next instruction 8621 8622 8623/* ------------------------------ */ 8624 .balign 64 8625.L_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 8626/* File: armv5te/OP_SPUT_BYTE_JUMBO.S */ 8627/* File: armv5te/OP_SPUT_JUMBO.S */ 8628 /* 8629 * Jumbo 32-bit SPUT handler. 8630 * 8631 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8632 * sput-short/jumbo 8633 */ 8634 /* exop vBBBB, field@AAAAAAAA */ 8635 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8636 FETCH(r0, 1) @ r0<- aaaa (lo) 8637 FETCH(r1, 2) @ r1<- AAAA (hi) 8638 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8639 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8640 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8641 cmp r0, #0 @ is resolved entry null? 8642 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve 8643.LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0 8644 FETCH(r2, 3) @ r2<- BBBB 8645 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8646 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8647 GET_INST_OPCODE(ip) @ extract opcode from rINST 8648 @ no-op @ releasing store 8649 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8650 GOTO_OPCODE(ip) @ jump to next instruction 8651 8652 8653/* ------------------------------ */ 8654 .balign 64 8655.L_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 8656/* File: armv5te/OP_SPUT_CHAR_JUMBO.S */ 8657/* File: armv5te/OP_SPUT_JUMBO.S */ 8658 /* 8659 * Jumbo 32-bit SPUT handler. 8660 * 8661 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8662 * sput-short/jumbo 8663 */ 8664 /* exop vBBBB, field@AAAAAAAA */ 8665 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8666 FETCH(r0, 1) @ r0<- aaaa (lo) 8667 FETCH(r1, 2) @ r1<- AAAA (hi) 8668 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8669 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8670 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8671 cmp r0, #0 @ is resolved entry null? 8672 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve 8673.LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0 8674 FETCH(r2, 3) @ r2<- BBBB 8675 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8676 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8677 GET_INST_OPCODE(ip) @ extract opcode from rINST 8678 @ no-op @ releasing store 8679 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8680 GOTO_OPCODE(ip) @ jump to next instruction 8681 8682 8683/* ------------------------------ */ 8684 .balign 64 8685.L_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 8686/* File: armv5te/OP_SPUT_SHORT_JUMBO.S */ 8687/* File: armv5te/OP_SPUT_JUMBO.S */ 8688 /* 8689 * Jumbo 32-bit SPUT handler. 8690 * 8691 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8692 * sput-short/jumbo 8693 */ 8694 /* exop vBBBB, field@AAAAAAAA */ 8695 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8696 FETCH(r0, 1) @ r0<- aaaa (lo) 8697 FETCH(r1, 2) @ r1<- AAAA (hi) 8698 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8699 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8700 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8701 cmp r0, #0 @ is resolved entry null? 8702 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve 8703.LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0 8704 FETCH(r2, 3) @ r2<- BBBB 8705 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8706 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8707 GET_INST_OPCODE(ip) @ extract opcode from rINST 8708 @ no-op @ releasing store 8709 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8710 GOTO_OPCODE(ip) @ jump to next instruction 8711 8712 8713/* ------------------------------ */ 8714 .balign 64 8715.L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 8716/* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */ 8717 /* 8718 * Handle a virtual method call. 8719 */ 8720 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8721 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8722 FETCH(r0, 1) @ r1<- aaaa (lo) 8723 FETCH(r1, 2) @ r1<- AAAA (hi) 8724 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8725 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8726 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8727 cmp r0, #0 @ already resolved? 8728 EXPORT_PC() @ must export for invoke 8729 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on 8730 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8731 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8732 mov r2, #METHOD_VIRTUAL @ resolver method type 8733 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8734 cmp r0, #0 @ got null? 8735 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue 8736 b common_exceptionThrown @ yes, handle exception 8737 8738/* ------------------------------ */ 8739 .balign 64 8740.L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 8741/* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */ 8742 /* 8743 * Handle a "super" method call. 8744 */ 8745 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8746 FETCH(r10, 4) @ r10<- CCCC 8747 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8748 FETCH(r0, 1) @ r1<- aaaa (lo) 8749 FETCH(r1, 2) @ r1<- AAAA (hi) 8750 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8751 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8752 GET_VREG(r2, r10) @ r2<- "this" ptr 8753 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8754 cmp r2, #0 @ null "this"? 8755 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8756 beq common_errNullObject @ null "this", throw exception 8757 cmp r0, #0 @ already resolved? 8758 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 8759 EXPORT_PC() @ must export for invoke 8760 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on 8761 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now 8762 8763/* ------------------------------ */ 8764 .balign 64 8765.L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 8766/* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */ 8767 /* 8768 * Handle a direct method call. 8769 * 8770 * (We could defer the "is 'this' pointer null" test to the common 8771 * method invocation code, and use a flag to indicate that static 8772 * calls don't count. If we do this as part of copying the arguments 8773 * out we could avoiding loading the first arg twice.) 8774 * 8775 */ 8776 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8777 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8778 FETCH(r0, 1) @ r1<- aaaa (lo) 8779 FETCH(r1, 2) @ r1<- AAAA (hi) 8780 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8781 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8782 FETCH(r10, 4) @ r10<- CCCC 8783 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8784 cmp r0, #0 @ already resolved? 8785 EXPORT_PC() @ must export for invoke 8786 GET_VREG(r2, r10) @ r2<- "this" ptr 8787 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now 8788.LOP_INVOKE_DIRECT_JUMBO_finish: 8789 cmp r2, #0 @ null "this" ref? 8790 bne common_invokeMethodJumbo @ no, continue on 8791 b common_errNullObject @ yes, throw exception 8792 8793/* ------------------------------ */ 8794 .balign 64 8795.L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 8796/* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */ 8797 /* 8798 * Handle a static method call. 8799 */ 8800 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8801 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8802 FETCH(r0, 1) @ r1<- aaaa (lo) 8803 FETCH(r1, 2) @ r1<- AAAA (hi) 8804 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8805 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8806 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8807 cmp r0, #0 @ already resolved? 8808 EXPORT_PC() @ must export for invoke 8809 bne common_invokeMethodJumbo @ yes, continue on 88100: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8811 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8812 mov r2, #METHOD_STATIC @ resolver method type 8813 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8814 cmp r0, #0 @ got null? 8815 bne common_invokeMethodJumbo @ no, continue 8816 b common_exceptionThrown @ yes, handle exception 8817 8818/* ------------------------------ */ 8819 .balign 64 8820.L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 8821/* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */ 8822 /* 8823 * Handle an interface method call. 8824 */ 8825 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8826 FETCH(r2, 4) @ r2<- CCCC 8827 FETCH(r0, 1) @ r0<- aaaa (lo) 8828 FETCH(r1, 2) @ r1<- AAAA (hi) 8829 EXPORT_PC() @ must export for invoke 8830 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8831 GET_VREG(r0, r2) @ r0<- first arg ("this") 8832 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 8833 cmp r0, #0 @ null obj? 8834 ldr r2, [rSELF, #offThread_method] @ r2<- method 8835 beq common_errNullObject @ yes, fail 8836 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 8837 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 8838 cmp r0, #0 @ failed? 8839 beq common_exceptionThrown @ yes, handle exception 8840 b common_invokeMethodJumbo @ jump to common handler 8841 8842/* ------------------------------ */ 8843 .balign 64 8844.L_OP_UNUSED_27FF: /* 0x127 */ 8845/* File: armv5te/OP_UNUSED_27FF.S */ 8846/* File: armv5te/unused.S */ 8847 bl common_abort 8848 8849 8850/* ------------------------------ */ 8851 .balign 64 8852.L_OP_UNUSED_28FF: /* 0x128 */ 8853/* File: armv5te/OP_UNUSED_28FF.S */ 8854/* File: armv5te/unused.S */ 8855 bl common_abort 8856 8857 8858/* ------------------------------ */ 8859 .balign 64 8860.L_OP_UNUSED_29FF: /* 0x129 */ 8861/* File: armv5te/OP_UNUSED_29FF.S */ 8862/* File: armv5te/unused.S */ 8863 bl common_abort 8864 8865 8866/* ------------------------------ */ 8867 .balign 64 8868.L_OP_UNUSED_2AFF: /* 0x12a */ 8869/* File: armv5te/OP_UNUSED_2AFF.S */ 8870/* File: armv5te/unused.S */ 8871 bl common_abort 8872 8873 8874/* ------------------------------ */ 8875 .balign 64 8876.L_OP_UNUSED_2BFF: /* 0x12b */ 8877/* File: armv5te/OP_UNUSED_2BFF.S */ 8878/* File: armv5te/unused.S */ 8879 bl common_abort 8880 8881 8882/* ------------------------------ */ 8883 .balign 64 8884.L_OP_UNUSED_2CFF: /* 0x12c */ 8885/* File: armv5te/OP_UNUSED_2CFF.S */ 8886/* File: armv5te/unused.S */ 8887 bl common_abort 8888 8889 8890/* ------------------------------ */ 8891 .balign 64 8892.L_OP_UNUSED_2DFF: /* 0x12d */ 8893/* File: armv5te/OP_UNUSED_2DFF.S */ 8894/* File: armv5te/unused.S */ 8895 bl common_abort 8896 8897 8898/* ------------------------------ */ 8899 .balign 64 8900.L_OP_UNUSED_2EFF: /* 0x12e */ 8901/* File: armv5te/OP_UNUSED_2EFF.S */ 8902/* File: armv5te/unused.S */ 8903 bl common_abort 8904 8905 8906/* ------------------------------ */ 8907 .balign 64 8908.L_OP_UNUSED_2FFF: /* 0x12f */ 8909/* File: armv5te/OP_UNUSED_2FFF.S */ 8910/* File: armv5te/unused.S */ 8911 bl common_abort 8912 8913 8914/* ------------------------------ */ 8915 .balign 64 8916.L_OP_UNUSED_30FF: /* 0x130 */ 8917/* File: armv5te/OP_UNUSED_30FF.S */ 8918/* File: armv5te/unused.S */ 8919 bl common_abort 8920 8921 8922/* ------------------------------ */ 8923 .balign 64 8924.L_OP_UNUSED_31FF: /* 0x131 */ 8925/* File: armv5te/OP_UNUSED_31FF.S */ 8926/* File: armv5te/unused.S */ 8927 bl common_abort 8928 8929 8930/* ------------------------------ */ 8931 .balign 64 8932.L_OP_UNUSED_32FF: /* 0x132 */ 8933/* File: armv5te/OP_UNUSED_32FF.S */ 8934/* File: armv5te/unused.S */ 8935 bl common_abort 8936 8937 8938/* ------------------------------ */ 8939 .balign 64 8940.L_OP_UNUSED_33FF: /* 0x133 */ 8941/* File: armv5te/OP_UNUSED_33FF.S */ 8942/* File: armv5te/unused.S */ 8943 bl common_abort 8944 8945 8946/* ------------------------------ */ 8947 .balign 64 8948.L_OP_UNUSED_34FF: /* 0x134 */ 8949/* File: armv5te/OP_UNUSED_34FF.S */ 8950/* File: armv5te/unused.S */ 8951 bl common_abort 8952 8953 8954/* ------------------------------ */ 8955 .balign 64 8956.L_OP_UNUSED_35FF: /* 0x135 */ 8957/* File: armv5te/OP_UNUSED_35FF.S */ 8958/* File: armv5te/unused.S */ 8959 bl common_abort 8960 8961 8962/* ------------------------------ */ 8963 .balign 64 8964.L_OP_UNUSED_36FF: /* 0x136 */ 8965/* File: armv5te/OP_UNUSED_36FF.S */ 8966/* File: armv5te/unused.S */ 8967 bl common_abort 8968 8969 8970/* ------------------------------ */ 8971 .balign 64 8972.L_OP_UNUSED_37FF: /* 0x137 */ 8973/* File: armv5te/OP_UNUSED_37FF.S */ 8974/* File: armv5te/unused.S */ 8975 bl common_abort 8976 8977 8978/* ------------------------------ */ 8979 .balign 64 8980.L_OP_UNUSED_38FF: /* 0x138 */ 8981/* File: armv5te/OP_UNUSED_38FF.S */ 8982/* File: armv5te/unused.S */ 8983 bl common_abort 8984 8985 8986/* ------------------------------ */ 8987 .balign 64 8988.L_OP_UNUSED_39FF: /* 0x139 */ 8989/* File: armv5te/OP_UNUSED_39FF.S */ 8990/* File: armv5te/unused.S */ 8991 bl common_abort 8992 8993 8994/* ------------------------------ */ 8995 .balign 64 8996.L_OP_UNUSED_3AFF: /* 0x13a */ 8997/* File: armv5te/OP_UNUSED_3AFF.S */ 8998/* File: armv5te/unused.S */ 8999 bl common_abort 9000 9001 9002/* ------------------------------ */ 9003 .balign 64 9004.L_OP_UNUSED_3BFF: /* 0x13b */ 9005/* File: armv5te/OP_UNUSED_3BFF.S */ 9006/* File: armv5te/unused.S */ 9007 bl common_abort 9008 9009 9010/* ------------------------------ */ 9011 .balign 64 9012.L_OP_UNUSED_3CFF: /* 0x13c */ 9013/* File: armv5te/OP_UNUSED_3CFF.S */ 9014/* File: armv5te/unused.S */ 9015 bl common_abort 9016 9017 9018/* ------------------------------ */ 9019 .balign 64 9020.L_OP_UNUSED_3DFF: /* 0x13d */ 9021/* File: armv5te/OP_UNUSED_3DFF.S */ 9022/* File: armv5te/unused.S */ 9023 bl common_abort 9024 9025 9026/* ------------------------------ */ 9027 .balign 64 9028.L_OP_UNUSED_3EFF: /* 0x13e */ 9029/* File: armv5te/OP_UNUSED_3EFF.S */ 9030/* File: armv5te/unused.S */ 9031 bl common_abort 9032 9033 9034/* ------------------------------ */ 9035 .balign 64 9036.L_OP_UNUSED_3FFF: /* 0x13f */ 9037/* File: armv5te/OP_UNUSED_3FFF.S */ 9038/* File: armv5te/unused.S */ 9039 bl common_abort 9040 9041 9042/* ------------------------------ */ 9043 .balign 64 9044.L_OP_UNUSED_40FF: /* 0x140 */ 9045/* File: armv5te/OP_UNUSED_40FF.S */ 9046/* File: armv5te/unused.S */ 9047 bl common_abort 9048 9049 9050/* ------------------------------ */ 9051 .balign 64 9052.L_OP_UNUSED_41FF: /* 0x141 */ 9053/* File: armv5te/OP_UNUSED_41FF.S */ 9054/* File: armv5te/unused.S */ 9055 bl common_abort 9056 9057 9058/* ------------------------------ */ 9059 .balign 64 9060.L_OP_UNUSED_42FF: /* 0x142 */ 9061/* File: armv5te/OP_UNUSED_42FF.S */ 9062/* File: armv5te/unused.S */ 9063 bl common_abort 9064 9065 9066/* ------------------------------ */ 9067 .balign 64 9068.L_OP_UNUSED_43FF: /* 0x143 */ 9069/* File: armv5te/OP_UNUSED_43FF.S */ 9070/* File: armv5te/unused.S */ 9071 bl common_abort 9072 9073 9074/* ------------------------------ */ 9075 .balign 64 9076.L_OP_UNUSED_44FF: /* 0x144 */ 9077/* File: armv5te/OP_UNUSED_44FF.S */ 9078/* File: armv5te/unused.S */ 9079 bl common_abort 9080 9081 9082/* ------------------------------ */ 9083 .balign 64 9084.L_OP_UNUSED_45FF: /* 0x145 */ 9085/* File: armv5te/OP_UNUSED_45FF.S */ 9086/* File: armv5te/unused.S */ 9087 bl common_abort 9088 9089 9090/* ------------------------------ */ 9091 .balign 64 9092.L_OP_UNUSED_46FF: /* 0x146 */ 9093/* File: armv5te/OP_UNUSED_46FF.S */ 9094/* File: armv5te/unused.S */ 9095 bl common_abort 9096 9097 9098/* ------------------------------ */ 9099 .balign 64 9100.L_OP_UNUSED_47FF: /* 0x147 */ 9101/* File: armv5te/OP_UNUSED_47FF.S */ 9102/* File: armv5te/unused.S */ 9103 bl common_abort 9104 9105 9106/* ------------------------------ */ 9107 .balign 64 9108.L_OP_UNUSED_48FF: /* 0x148 */ 9109/* File: armv5te/OP_UNUSED_48FF.S */ 9110/* File: armv5te/unused.S */ 9111 bl common_abort 9112 9113 9114/* ------------------------------ */ 9115 .balign 64 9116.L_OP_UNUSED_49FF: /* 0x149 */ 9117/* File: armv5te/OP_UNUSED_49FF.S */ 9118/* File: armv5te/unused.S */ 9119 bl common_abort 9120 9121 9122/* ------------------------------ */ 9123 .balign 64 9124.L_OP_UNUSED_4AFF: /* 0x14a */ 9125/* File: armv5te/OP_UNUSED_4AFF.S */ 9126/* File: armv5te/unused.S */ 9127 bl common_abort 9128 9129 9130/* ------------------------------ */ 9131 .balign 64 9132.L_OP_UNUSED_4BFF: /* 0x14b */ 9133/* File: armv5te/OP_UNUSED_4BFF.S */ 9134/* File: armv5te/unused.S */ 9135 bl common_abort 9136 9137 9138/* ------------------------------ */ 9139 .balign 64 9140.L_OP_UNUSED_4CFF: /* 0x14c */ 9141/* File: armv5te/OP_UNUSED_4CFF.S */ 9142/* File: armv5te/unused.S */ 9143 bl common_abort 9144 9145 9146/* ------------------------------ */ 9147 .balign 64 9148.L_OP_UNUSED_4DFF: /* 0x14d */ 9149/* File: armv5te/OP_UNUSED_4DFF.S */ 9150/* File: armv5te/unused.S */ 9151 bl common_abort 9152 9153 9154/* ------------------------------ */ 9155 .balign 64 9156.L_OP_UNUSED_4EFF: /* 0x14e */ 9157/* File: armv5te/OP_UNUSED_4EFF.S */ 9158/* File: armv5te/unused.S */ 9159 bl common_abort 9160 9161 9162/* ------------------------------ */ 9163 .balign 64 9164.L_OP_UNUSED_4FFF: /* 0x14f */ 9165/* File: armv5te/OP_UNUSED_4FFF.S */ 9166/* File: armv5te/unused.S */ 9167 bl common_abort 9168 9169 9170/* ------------------------------ */ 9171 .balign 64 9172.L_OP_UNUSED_50FF: /* 0x150 */ 9173/* File: armv5te/OP_UNUSED_50FF.S */ 9174/* File: armv5te/unused.S */ 9175 bl common_abort 9176 9177 9178/* ------------------------------ */ 9179 .balign 64 9180.L_OP_UNUSED_51FF: /* 0x151 */ 9181/* File: armv5te/OP_UNUSED_51FF.S */ 9182/* File: armv5te/unused.S */ 9183 bl common_abort 9184 9185 9186/* ------------------------------ */ 9187 .balign 64 9188.L_OP_UNUSED_52FF: /* 0x152 */ 9189/* File: armv5te/OP_UNUSED_52FF.S */ 9190/* File: armv5te/unused.S */ 9191 bl common_abort 9192 9193 9194/* ------------------------------ */ 9195 .balign 64 9196.L_OP_UNUSED_53FF: /* 0x153 */ 9197/* File: armv5te/OP_UNUSED_53FF.S */ 9198/* File: armv5te/unused.S */ 9199 bl common_abort 9200 9201 9202/* ------------------------------ */ 9203 .balign 64 9204.L_OP_UNUSED_54FF: /* 0x154 */ 9205/* File: armv5te/OP_UNUSED_54FF.S */ 9206/* File: armv5te/unused.S */ 9207 bl common_abort 9208 9209 9210/* ------------------------------ */ 9211 .balign 64 9212.L_OP_UNUSED_55FF: /* 0x155 */ 9213/* File: armv5te/OP_UNUSED_55FF.S */ 9214/* File: armv5te/unused.S */ 9215 bl common_abort 9216 9217 9218/* ------------------------------ */ 9219 .balign 64 9220.L_OP_UNUSED_56FF: /* 0x156 */ 9221/* File: armv5te/OP_UNUSED_56FF.S */ 9222/* File: armv5te/unused.S */ 9223 bl common_abort 9224 9225 9226/* ------------------------------ */ 9227 .balign 64 9228.L_OP_UNUSED_57FF: /* 0x157 */ 9229/* File: armv5te/OP_UNUSED_57FF.S */ 9230/* File: armv5te/unused.S */ 9231 bl common_abort 9232 9233 9234/* ------------------------------ */ 9235 .balign 64 9236.L_OP_UNUSED_58FF: /* 0x158 */ 9237/* File: armv5te/OP_UNUSED_58FF.S */ 9238/* File: armv5te/unused.S */ 9239 bl common_abort 9240 9241 9242/* ------------------------------ */ 9243 .balign 64 9244.L_OP_UNUSED_59FF: /* 0x159 */ 9245/* File: armv5te/OP_UNUSED_59FF.S */ 9246/* File: armv5te/unused.S */ 9247 bl common_abort 9248 9249 9250/* ------------------------------ */ 9251 .balign 64 9252.L_OP_UNUSED_5AFF: /* 0x15a */ 9253/* File: armv5te/OP_UNUSED_5AFF.S */ 9254/* File: armv5te/unused.S */ 9255 bl common_abort 9256 9257 9258/* ------------------------------ */ 9259 .balign 64 9260.L_OP_UNUSED_5BFF: /* 0x15b */ 9261/* File: armv5te/OP_UNUSED_5BFF.S */ 9262/* File: armv5te/unused.S */ 9263 bl common_abort 9264 9265 9266/* ------------------------------ */ 9267 .balign 64 9268.L_OP_UNUSED_5CFF: /* 0x15c */ 9269/* File: armv5te/OP_UNUSED_5CFF.S */ 9270/* File: armv5te/unused.S */ 9271 bl common_abort 9272 9273 9274/* ------------------------------ */ 9275 .balign 64 9276.L_OP_UNUSED_5DFF: /* 0x15d */ 9277/* File: armv5te/OP_UNUSED_5DFF.S */ 9278/* File: armv5te/unused.S */ 9279 bl common_abort 9280 9281 9282/* ------------------------------ */ 9283 .balign 64 9284.L_OP_UNUSED_5EFF: /* 0x15e */ 9285/* File: armv5te/OP_UNUSED_5EFF.S */ 9286/* File: armv5te/unused.S */ 9287 bl common_abort 9288 9289 9290/* ------------------------------ */ 9291 .balign 64 9292.L_OP_UNUSED_5FFF: /* 0x15f */ 9293/* File: armv5te/OP_UNUSED_5FFF.S */ 9294/* File: armv5te/unused.S */ 9295 bl common_abort 9296 9297 9298/* ------------------------------ */ 9299 .balign 64 9300.L_OP_UNUSED_60FF: /* 0x160 */ 9301/* File: armv5te/OP_UNUSED_60FF.S */ 9302/* File: armv5te/unused.S */ 9303 bl common_abort 9304 9305 9306/* ------------------------------ */ 9307 .balign 64 9308.L_OP_UNUSED_61FF: /* 0x161 */ 9309/* File: armv5te/OP_UNUSED_61FF.S */ 9310/* File: armv5te/unused.S */ 9311 bl common_abort 9312 9313 9314/* ------------------------------ */ 9315 .balign 64 9316.L_OP_UNUSED_62FF: /* 0x162 */ 9317/* File: armv5te/OP_UNUSED_62FF.S */ 9318/* File: armv5te/unused.S */ 9319 bl common_abort 9320 9321 9322/* ------------------------------ */ 9323 .balign 64 9324.L_OP_UNUSED_63FF: /* 0x163 */ 9325/* File: armv5te/OP_UNUSED_63FF.S */ 9326/* File: armv5te/unused.S */ 9327 bl common_abort 9328 9329 9330/* ------------------------------ */ 9331 .balign 64 9332.L_OP_UNUSED_64FF: /* 0x164 */ 9333/* File: armv5te/OP_UNUSED_64FF.S */ 9334/* File: armv5te/unused.S */ 9335 bl common_abort 9336 9337 9338/* ------------------------------ */ 9339 .balign 64 9340.L_OP_UNUSED_65FF: /* 0x165 */ 9341/* File: armv5te/OP_UNUSED_65FF.S */ 9342/* File: armv5te/unused.S */ 9343 bl common_abort 9344 9345 9346/* ------------------------------ */ 9347 .balign 64 9348.L_OP_UNUSED_66FF: /* 0x166 */ 9349/* File: armv5te/OP_UNUSED_66FF.S */ 9350/* File: armv5te/unused.S */ 9351 bl common_abort 9352 9353 9354/* ------------------------------ */ 9355 .balign 64 9356.L_OP_UNUSED_67FF: /* 0x167 */ 9357/* File: armv5te/OP_UNUSED_67FF.S */ 9358/* File: armv5te/unused.S */ 9359 bl common_abort 9360 9361 9362/* ------------------------------ */ 9363 .balign 64 9364.L_OP_UNUSED_68FF: /* 0x168 */ 9365/* File: armv5te/OP_UNUSED_68FF.S */ 9366/* File: armv5te/unused.S */ 9367 bl common_abort 9368 9369 9370/* ------------------------------ */ 9371 .balign 64 9372.L_OP_UNUSED_69FF: /* 0x169 */ 9373/* File: armv5te/OP_UNUSED_69FF.S */ 9374/* File: armv5te/unused.S */ 9375 bl common_abort 9376 9377 9378/* ------------------------------ */ 9379 .balign 64 9380.L_OP_UNUSED_6AFF: /* 0x16a */ 9381/* File: armv5te/OP_UNUSED_6AFF.S */ 9382/* File: armv5te/unused.S */ 9383 bl common_abort 9384 9385 9386/* ------------------------------ */ 9387 .balign 64 9388.L_OP_UNUSED_6BFF: /* 0x16b */ 9389/* File: armv5te/OP_UNUSED_6BFF.S */ 9390/* File: armv5te/unused.S */ 9391 bl common_abort 9392 9393 9394/* ------------------------------ */ 9395 .balign 64 9396.L_OP_UNUSED_6CFF: /* 0x16c */ 9397/* File: armv5te/OP_UNUSED_6CFF.S */ 9398/* File: armv5te/unused.S */ 9399 bl common_abort 9400 9401 9402/* ------------------------------ */ 9403 .balign 64 9404.L_OP_UNUSED_6DFF: /* 0x16d */ 9405/* File: armv5te/OP_UNUSED_6DFF.S */ 9406/* File: armv5te/unused.S */ 9407 bl common_abort 9408 9409 9410/* ------------------------------ */ 9411 .balign 64 9412.L_OP_UNUSED_6EFF: /* 0x16e */ 9413/* File: armv5te/OP_UNUSED_6EFF.S */ 9414/* File: armv5te/unused.S */ 9415 bl common_abort 9416 9417 9418/* ------------------------------ */ 9419 .balign 64 9420.L_OP_UNUSED_6FFF: /* 0x16f */ 9421/* File: armv5te/OP_UNUSED_6FFF.S */ 9422/* File: armv5te/unused.S */ 9423 bl common_abort 9424 9425 9426/* ------------------------------ */ 9427 .balign 64 9428.L_OP_UNUSED_70FF: /* 0x170 */ 9429/* File: armv5te/OP_UNUSED_70FF.S */ 9430/* File: armv5te/unused.S */ 9431 bl common_abort 9432 9433 9434/* ------------------------------ */ 9435 .balign 64 9436.L_OP_UNUSED_71FF: /* 0x171 */ 9437/* File: armv5te/OP_UNUSED_71FF.S */ 9438/* File: armv5te/unused.S */ 9439 bl common_abort 9440 9441 9442/* ------------------------------ */ 9443 .balign 64 9444.L_OP_UNUSED_72FF: /* 0x172 */ 9445/* File: armv5te/OP_UNUSED_72FF.S */ 9446/* File: armv5te/unused.S */ 9447 bl common_abort 9448 9449 9450/* ------------------------------ */ 9451 .balign 64 9452.L_OP_UNUSED_73FF: /* 0x173 */ 9453/* File: armv5te/OP_UNUSED_73FF.S */ 9454/* File: armv5te/unused.S */ 9455 bl common_abort 9456 9457 9458/* ------------------------------ */ 9459 .balign 64 9460.L_OP_UNUSED_74FF: /* 0x174 */ 9461/* File: armv5te/OP_UNUSED_74FF.S */ 9462/* File: armv5te/unused.S */ 9463 bl common_abort 9464 9465 9466/* ------------------------------ */ 9467 .balign 64 9468.L_OP_UNUSED_75FF: /* 0x175 */ 9469/* File: armv5te/OP_UNUSED_75FF.S */ 9470/* File: armv5te/unused.S */ 9471 bl common_abort 9472 9473 9474/* ------------------------------ */ 9475 .balign 64 9476.L_OP_UNUSED_76FF: /* 0x176 */ 9477/* File: armv5te/OP_UNUSED_76FF.S */ 9478/* File: armv5te/unused.S */ 9479 bl common_abort 9480 9481 9482/* ------------------------------ */ 9483 .balign 64 9484.L_OP_UNUSED_77FF: /* 0x177 */ 9485/* File: armv5te/OP_UNUSED_77FF.S */ 9486/* File: armv5te/unused.S */ 9487 bl common_abort 9488 9489 9490/* ------------------------------ */ 9491 .balign 64 9492.L_OP_UNUSED_78FF: /* 0x178 */ 9493/* File: armv5te/OP_UNUSED_78FF.S */ 9494/* File: armv5te/unused.S */ 9495 bl common_abort 9496 9497 9498/* ------------------------------ */ 9499 .balign 64 9500.L_OP_UNUSED_79FF: /* 0x179 */ 9501/* File: armv5te/OP_UNUSED_79FF.S */ 9502/* File: armv5te/unused.S */ 9503 bl common_abort 9504 9505 9506/* ------------------------------ */ 9507 .balign 64 9508.L_OP_UNUSED_7AFF: /* 0x17a */ 9509/* File: armv5te/OP_UNUSED_7AFF.S */ 9510/* File: armv5te/unused.S */ 9511 bl common_abort 9512 9513 9514/* ------------------------------ */ 9515 .balign 64 9516.L_OP_UNUSED_7BFF: /* 0x17b */ 9517/* File: armv5te/OP_UNUSED_7BFF.S */ 9518/* File: armv5te/unused.S */ 9519 bl common_abort 9520 9521 9522/* ------------------------------ */ 9523 .balign 64 9524.L_OP_UNUSED_7CFF: /* 0x17c */ 9525/* File: armv5te/OP_UNUSED_7CFF.S */ 9526/* File: armv5te/unused.S */ 9527 bl common_abort 9528 9529 9530/* ------------------------------ */ 9531 .balign 64 9532.L_OP_UNUSED_7DFF: /* 0x17d */ 9533/* File: armv5te/OP_UNUSED_7DFF.S */ 9534/* File: armv5te/unused.S */ 9535 bl common_abort 9536 9537 9538/* ------------------------------ */ 9539 .balign 64 9540.L_OP_UNUSED_7EFF: /* 0x17e */ 9541/* File: armv5te/OP_UNUSED_7EFF.S */ 9542/* File: armv5te/unused.S */ 9543 bl common_abort 9544 9545 9546/* ------------------------------ */ 9547 .balign 64 9548.L_OP_UNUSED_7FFF: /* 0x17f */ 9549/* File: armv5te/OP_UNUSED_7FFF.S */ 9550/* File: armv5te/unused.S */ 9551 bl common_abort 9552 9553 9554/* ------------------------------ */ 9555 .balign 64 9556.L_OP_UNUSED_80FF: /* 0x180 */ 9557/* File: armv5te/OP_UNUSED_80FF.S */ 9558/* File: armv5te/unused.S */ 9559 bl common_abort 9560 9561 9562/* ------------------------------ */ 9563 .balign 64 9564.L_OP_UNUSED_81FF: /* 0x181 */ 9565/* File: armv5te/OP_UNUSED_81FF.S */ 9566/* File: armv5te/unused.S */ 9567 bl common_abort 9568 9569 9570/* ------------------------------ */ 9571 .balign 64 9572.L_OP_UNUSED_82FF: /* 0x182 */ 9573/* File: armv5te/OP_UNUSED_82FF.S */ 9574/* File: armv5te/unused.S */ 9575 bl common_abort 9576 9577 9578/* ------------------------------ */ 9579 .balign 64 9580.L_OP_UNUSED_83FF: /* 0x183 */ 9581/* File: armv5te/OP_UNUSED_83FF.S */ 9582/* File: armv5te/unused.S */ 9583 bl common_abort 9584 9585 9586/* ------------------------------ */ 9587 .balign 64 9588.L_OP_UNUSED_84FF: /* 0x184 */ 9589/* File: armv5te/OP_UNUSED_84FF.S */ 9590/* File: armv5te/unused.S */ 9591 bl common_abort 9592 9593 9594/* ------------------------------ */ 9595 .balign 64 9596.L_OP_UNUSED_85FF: /* 0x185 */ 9597/* File: armv5te/OP_UNUSED_85FF.S */ 9598/* File: armv5te/unused.S */ 9599 bl common_abort 9600 9601 9602/* ------------------------------ */ 9603 .balign 64 9604.L_OP_UNUSED_86FF: /* 0x186 */ 9605/* File: armv5te/OP_UNUSED_86FF.S */ 9606/* File: armv5te/unused.S */ 9607 bl common_abort 9608 9609 9610/* ------------------------------ */ 9611 .balign 64 9612.L_OP_UNUSED_87FF: /* 0x187 */ 9613/* File: armv5te/OP_UNUSED_87FF.S */ 9614/* File: armv5te/unused.S */ 9615 bl common_abort 9616 9617 9618/* ------------------------------ */ 9619 .balign 64 9620.L_OP_UNUSED_88FF: /* 0x188 */ 9621/* File: armv5te/OP_UNUSED_88FF.S */ 9622/* File: armv5te/unused.S */ 9623 bl common_abort 9624 9625 9626/* ------------------------------ */ 9627 .balign 64 9628.L_OP_UNUSED_89FF: /* 0x189 */ 9629/* File: armv5te/OP_UNUSED_89FF.S */ 9630/* File: armv5te/unused.S */ 9631 bl common_abort 9632 9633 9634/* ------------------------------ */ 9635 .balign 64 9636.L_OP_UNUSED_8AFF: /* 0x18a */ 9637/* File: armv5te/OP_UNUSED_8AFF.S */ 9638/* File: armv5te/unused.S */ 9639 bl common_abort 9640 9641 9642/* ------------------------------ */ 9643 .balign 64 9644.L_OP_UNUSED_8BFF: /* 0x18b */ 9645/* File: armv5te/OP_UNUSED_8BFF.S */ 9646/* File: armv5te/unused.S */ 9647 bl common_abort 9648 9649 9650/* ------------------------------ */ 9651 .balign 64 9652.L_OP_UNUSED_8CFF: /* 0x18c */ 9653/* File: armv5te/OP_UNUSED_8CFF.S */ 9654/* File: armv5te/unused.S */ 9655 bl common_abort 9656 9657 9658/* ------------------------------ */ 9659 .balign 64 9660.L_OP_UNUSED_8DFF: /* 0x18d */ 9661/* File: armv5te/OP_UNUSED_8DFF.S */ 9662/* File: armv5te/unused.S */ 9663 bl common_abort 9664 9665 9666/* ------------------------------ */ 9667 .balign 64 9668.L_OP_UNUSED_8EFF: /* 0x18e */ 9669/* File: armv5te/OP_UNUSED_8EFF.S */ 9670/* File: armv5te/unused.S */ 9671 bl common_abort 9672 9673 9674/* ------------------------------ */ 9675 .balign 64 9676.L_OP_UNUSED_8FFF: /* 0x18f */ 9677/* File: armv5te/OP_UNUSED_8FFF.S */ 9678/* File: armv5te/unused.S */ 9679 bl common_abort 9680 9681 9682/* ------------------------------ */ 9683 .balign 64 9684.L_OP_UNUSED_90FF: /* 0x190 */ 9685/* File: armv5te/OP_UNUSED_90FF.S */ 9686/* File: armv5te/unused.S */ 9687 bl common_abort 9688 9689 9690/* ------------------------------ */ 9691 .balign 64 9692.L_OP_UNUSED_91FF: /* 0x191 */ 9693/* File: armv5te/OP_UNUSED_91FF.S */ 9694/* File: armv5te/unused.S */ 9695 bl common_abort 9696 9697 9698/* ------------------------------ */ 9699 .balign 64 9700.L_OP_UNUSED_92FF: /* 0x192 */ 9701/* File: armv5te/OP_UNUSED_92FF.S */ 9702/* File: armv5te/unused.S */ 9703 bl common_abort 9704 9705 9706/* ------------------------------ */ 9707 .balign 64 9708.L_OP_UNUSED_93FF: /* 0x193 */ 9709/* File: armv5te/OP_UNUSED_93FF.S */ 9710/* File: armv5te/unused.S */ 9711 bl common_abort 9712 9713 9714/* ------------------------------ */ 9715 .balign 64 9716.L_OP_UNUSED_94FF: /* 0x194 */ 9717/* File: armv5te/OP_UNUSED_94FF.S */ 9718/* File: armv5te/unused.S */ 9719 bl common_abort 9720 9721 9722/* ------------------------------ */ 9723 .balign 64 9724.L_OP_UNUSED_95FF: /* 0x195 */ 9725/* File: armv5te/OP_UNUSED_95FF.S */ 9726/* File: armv5te/unused.S */ 9727 bl common_abort 9728 9729 9730/* ------------------------------ */ 9731 .balign 64 9732.L_OP_UNUSED_96FF: /* 0x196 */ 9733/* File: armv5te/OP_UNUSED_96FF.S */ 9734/* File: armv5te/unused.S */ 9735 bl common_abort 9736 9737 9738/* ------------------------------ */ 9739 .balign 64 9740.L_OP_UNUSED_97FF: /* 0x197 */ 9741/* File: armv5te/OP_UNUSED_97FF.S */ 9742/* File: armv5te/unused.S */ 9743 bl common_abort 9744 9745 9746/* ------------------------------ */ 9747 .balign 64 9748.L_OP_UNUSED_98FF: /* 0x198 */ 9749/* File: armv5te/OP_UNUSED_98FF.S */ 9750/* File: armv5te/unused.S */ 9751 bl common_abort 9752 9753 9754/* ------------------------------ */ 9755 .balign 64 9756.L_OP_UNUSED_99FF: /* 0x199 */ 9757/* File: armv5te/OP_UNUSED_99FF.S */ 9758/* File: armv5te/unused.S */ 9759 bl common_abort 9760 9761 9762/* ------------------------------ */ 9763 .balign 64 9764.L_OP_UNUSED_9AFF: /* 0x19a */ 9765/* File: armv5te/OP_UNUSED_9AFF.S */ 9766/* File: armv5te/unused.S */ 9767 bl common_abort 9768 9769 9770/* ------------------------------ */ 9771 .balign 64 9772.L_OP_UNUSED_9BFF: /* 0x19b */ 9773/* File: armv5te/OP_UNUSED_9BFF.S */ 9774/* File: armv5te/unused.S */ 9775 bl common_abort 9776 9777 9778/* ------------------------------ */ 9779 .balign 64 9780.L_OP_UNUSED_9CFF: /* 0x19c */ 9781/* File: armv5te/OP_UNUSED_9CFF.S */ 9782/* File: armv5te/unused.S */ 9783 bl common_abort 9784 9785 9786/* ------------------------------ */ 9787 .balign 64 9788.L_OP_UNUSED_9DFF: /* 0x19d */ 9789/* File: armv5te/OP_UNUSED_9DFF.S */ 9790/* File: armv5te/unused.S */ 9791 bl common_abort 9792 9793 9794/* ------------------------------ */ 9795 .balign 64 9796.L_OP_UNUSED_9EFF: /* 0x19e */ 9797/* File: armv5te/OP_UNUSED_9EFF.S */ 9798/* File: armv5te/unused.S */ 9799 bl common_abort 9800 9801 9802/* ------------------------------ */ 9803 .balign 64 9804.L_OP_UNUSED_9FFF: /* 0x19f */ 9805/* File: armv5te/OP_UNUSED_9FFF.S */ 9806/* File: armv5te/unused.S */ 9807 bl common_abort 9808 9809 9810/* ------------------------------ */ 9811 .balign 64 9812.L_OP_UNUSED_A0FF: /* 0x1a0 */ 9813/* File: armv5te/OP_UNUSED_A0FF.S */ 9814/* File: armv5te/unused.S */ 9815 bl common_abort 9816 9817 9818/* ------------------------------ */ 9819 .balign 64 9820.L_OP_UNUSED_A1FF: /* 0x1a1 */ 9821/* File: armv5te/OP_UNUSED_A1FF.S */ 9822/* File: armv5te/unused.S */ 9823 bl common_abort 9824 9825 9826/* ------------------------------ */ 9827 .balign 64 9828.L_OP_UNUSED_A2FF: /* 0x1a2 */ 9829/* File: armv5te/OP_UNUSED_A2FF.S */ 9830/* File: armv5te/unused.S */ 9831 bl common_abort 9832 9833 9834/* ------------------------------ */ 9835 .balign 64 9836.L_OP_UNUSED_A3FF: /* 0x1a3 */ 9837/* File: armv5te/OP_UNUSED_A3FF.S */ 9838/* File: armv5te/unused.S */ 9839 bl common_abort 9840 9841 9842/* ------------------------------ */ 9843 .balign 64 9844.L_OP_UNUSED_A4FF: /* 0x1a4 */ 9845/* File: armv5te/OP_UNUSED_A4FF.S */ 9846/* File: armv5te/unused.S */ 9847 bl common_abort 9848 9849 9850/* ------------------------------ */ 9851 .balign 64 9852.L_OP_UNUSED_A5FF: /* 0x1a5 */ 9853/* File: armv5te/OP_UNUSED_A5FF.S */ 9854/* File: armv5te/unused.S */ 9855 bl common_abort 9856 9857 9858/* ------------------------------ */ 9859 .balign 64 9860.L_OP_UNUSED_A6FF: /* 0x1a6 */ 9861/* File: armv5te/OP_UNUSED_A6FF.S */ 9862/* File: armv5te/unused.S */ 9863 bl common_abort 9864 9865 9866/* ------------------------------ */ 9867 .balign 64 9868.L_OP_UNUSED_A7FF: /* 0x1a7 */ 9869/* File: armv5te/OP_UNUSED_A7FF.S */ 9870/* File: armv5te/unused.S */ 9871 bl common_abort 9872 9873 9874/* ------------------------------ */ 9875 .balign 64 9876.L_OP_UNUSED_A8FF: /* 0x1a8 */ 9877/* File: armv5te/OP_UNUSED_A8FF.S */ 9878/* File: armv5te/unused.S */ 9879 bl common_abort 9880 9881 9882/* ------------------------------ */ 9883 .balign 64 9884.L_OP_UNUSED_A9FF: /* 0x1a9 */ 9885/* File: armv5te/OP_UNUSED_A9FF.S */ 9886/* File: armv5te/unused.S */ 9887 bl common_abort 9888 9889 9890/* ------------------------------ */ 9891 .balign 64 9892.L_OP_UNUSED_AAFF: /* 0x1aa */ 9893/* File: armv5te/OP_UNUSED_AAFF.S */ 9894/* File: armv5te/unused.S */ 9895 bl common_abort 9896 9897 9898/* ------------------------------ */ 9899 .balign 64 9900.L_OP_UNUSED_ABFF: /* 0x1ab */ 9901/* File: armv5te/OP_UNUSED_ABFF.S */ 9902/* File: armv5te/unused.S */ 9903 bl common_abort 9904 9905 9906/* ------------------------------ */ 9907 .balign 64 9908.L_OP_UNUSED_ACFF: /* 0x1ac */ 9909/* File: armv5te/OP_UNUSED_ACFF.S */ 9910/* File: armv5te/unused.S */ 9911 bl common_abort 9912 9913 9914/* ------------------------------ */ 9915 .balign 64 9916.L_OP_UNUSED_ADFF: /* 0x1ad */ 9917/* File: armv5te/OP_UNUSED_ADFF.S */ 9918/* File: armv5te/unused.S */ 9919 bl common_abort 9920 9921 9922/* ------------------------------ */ 9923 .balign 64 9924.L_OP_UNUSED_AEFF: /* 0x1ae */ 9925/* File: armv5te/OP_UNUSED_AEFF.S */ 9926/* File: armv5te/unused.S */ 9927 bl common_abort 9928 9929 9930/* ------------------------------ */ 9931 .balign 64 9932.L_OP_UNUSED_AFFF: /* 0x1af */ 9933/* File: armv5te/OP_UNUSED_AFFF.S */ 9934/* File: armv5te/unused.S */ 9935 bl common_abort 9936 9937 9938/* ------------------------------ */ 9939 .balign 64 9940.L_OP_UNUSED_B0FF: /* 0x1b0 */ 9941/* File: armv5te/OP_UNUSED_B0FF.S */ 9942/* File: armv5te/unused.S */ 9943 bl common_abort 9944 9945 9946/* ------------------------------ */ 9947 .balign 64 9948.L_OP_UNUSED_B1FF: /* 0x1b1 */ 9949/* File: armv5te/OP_UNUSED_B1FF.S */ 9950/* File: armv5te/unused.S */ 9951 bl common_abort 9952 9953 9954/* ------------------------------ */ 9955 .balign 64 9956.L_OP_UNUSED_B2FF: /* 0x1b2 */ 9957/* File: armv5te/OP_UNUSED_B2FF.S */ 9958/* File: armv5te/unused.S */ 9959 bl common_abort 9960 9961 9962/* ------------------------------ */ 9963 .balign 64 9964.L_OP_UNUSED_B3FF: /* 0x1b3 */ 9965/* File: armv5te/OP_UNUSED_B3FF.S */ 9966/* File: armv5te/unused.S */ 9967 bl common_abort 9968 9969 9970/* ------------------------------ */ 9971 .balign 64 9972.L_OP_UNUSED_B4FF: /* 0x1b4 */ 9973/* File: armv5te/OP_UNUSED_B4FF.S */ 9974/* File: armv5te/unused.S */ 9975 bl common_abort 9976 9977 9978/* ------------------------------ */ 9979 .balign 64 9980.L_OP_UNUSED_B5FF: /* 0x1b5 */ 9981/* File: armv5te/OP_UNUSED_B5FF.S */ 9982/* File: armv5te/unused.S */ 9983 bl common_abort 9984 9985 9986/* ------------------------------ */ 9987 .balign 64 9988.L_OP_UNUSED_B6FF: /* 0x1b6 */ 9989/* File: armv5te/OP_UNUSED_B6FF.S */ 9990/* File: armv5te/unused.S */ 9991 bl common_abort 9992 9993 9994/* ------------------------------ */ 9995 .balign 64 9996.L_OP_UNUSED_B7FF: /* 0x1b7 */ 9997/* File: armv5te/OP_UNUSED_B7FF.S */ 9998/* File: armv5te/unused.S */ 9999 bl common_abort 10000 10001 10002/* ------------------------------ */ 10003 .balign 64 10004.L_OP_UNUSED_B8FF: /* 0x1b8 */ 10005/* File: armv5te/OP_UNUSED_B8FF.S */ 10006/* File: armv5te/unused.S */ 10007 bl common_abort 10008 10009 10010/* ------------------------------ */ 10011 .balign 64 10012.L_OP_UNUSED_B9FF: /* 0x1b9 */ 10013/* File: armv5te/OP_UNUSED_B9FF.S */ 10014/* File: armv5te/unused.S */ 10015 bl common_abort 10016 10017 10018/* ------------------------------ */ 10019 .balign 64 10020.L_OP_UNUSED_BAFF: /* 0x1ba */ 10021/* File: armv5te/OP_UNUSED_BAFF.S */ 10022/* File: armv5te/unused.S */ 10023 bl common_abort 10024 10025 10026/* ------------------------------ */ 10027 .balign 64 10028.L_OP_UNUSED_BBFF: /* 0x1bb */ 10029/* File: armv5te/OP_UNUSED_BBFF.S */ 10030/* File: armv5te/unused.S */ 10031 bl common_abort 10032 10033 10034/* ------------------------------ */ 10035 .balign 64 10036.L_OP_UNUSED_BCFF: /* 0x1bc */ 10037/* File: armv5te/OP_UNUSED_BCFF.S */ 10038/* File: armv5te/unused.S */ 10039 bl common_abort 10040 10041 10042/* ------------------------------ */ 10043 .balign 64 10044.L_OP_UNUSED_BDFF: /* 0x1bd */ 10045/* File: armv5te/OP_UNUSED_BDFF.S */ 10046/* File: armv5te/unused.S */ 10047 bl common_abort 10048 10049 10050/* ------------------------------ */ 10051 .balign 64 10052.L_OP_UNUSED_BEFF: /* 0x1be */ 10053/* File: armv5te/OP_UNUSED_BEFF.S */ 10054/* File: armv5te/unused.S */ 10055 bl common_abort 10056 10057 10058/* ------------------------------ */ 10059 .balign 64 10060.L_OP_UNUSED_BFFF: /* 0x1bf */ 10061/* File: armv5te/OP_UNUSED_BFFF.S */ 10062/* File: armv5te/unused.S */ 10063 bl common_abort 10064 10065 10066/* ------------------------------ */ 10067 .balign 64 10068.L_OP_UNUSED_C0FF: /* 0x1c0 */ 10069/* File: armv5te/OP_UNUSED_C0FF.S */ 10070/* File: armv5te/unused.S */ 10071 bl common_abort 10072 10073 10074/* ------------------------------ */ 10075 .balign 64 10076.L_OP_UNUSED_C1FF: /* 0x1c1 */ 10077/* File: armv5te/OP_UNUSED_C1FF.S */ 10078/* File: armv5te/unused.S */ 10079 bl common_abort 10080 10081 10082/* ------------------------------ */ 10083 .balign 64 10084.L_OP_UNUSED_C2FF: /* 0x1c2 */ 10085/* File: armv5te/OP_UNUSED_C2FF.S */ 10086/* File: armv5te/unused.S */ 10087 bl common_abort 10088 10089 10090/* ------------------------------ */ 10091 .balign 64 10092.L_OP_UNUSED_C3FF: /* 0x1c3 */ 10093/* File: armv5te/OP_UNUSED_C3FF.S */ 10094/* File: armv5te/unused.S */ 10095 bl common_abort 10096 10097 10098/* ------------------------------ */ 10099 .balign 64 10100.L_OP_UNUSED_C4FF: /* 0x1c4 */ 10101/* File: armv5te/OP_UNUSED_C4FF.S */ 10102/* File: armv5te/unused.S */ 10103 bl common_abort 10104 10105 10106/* ------------------------------ */ 10107 .balign 64 10108.L_OP_UNUSED_C5FF: /* 0x1c5 */ 10109/* File: armv5te/OP_UNUSED_C5FF.S */ 10110/* File: armv5te/unused.S */ 10111 bl common_abort 10112 10113 10114/* ------------------------------ */ 10115 .balign 64 10116.L_OP_UNUSED_C6FF: /* 0x1c6 */ 10117/* File: armv5te/OP_UNUSED_C6FF.S */ 10118/* File: armv5te/unused.S */ 10119 bl common_abort 10120 10121 10122/* ------------------------------ */ 10123 .balign 64 10124.L_OP_UNUSED_C7FF: /* 0x1c7 */ 10125/* File: armv5te/OP_UNUSED_C7FF.S */ 10126/* File: armv5te/unused.S */ 10127 bl common_abort 10128 10129 10130/* ------------------------------ */ 10131 .balign 64 10132.L_OP_UNUSED_C8FF: /* 0x1c8 */ 10133/* File: armv5te/OP_UNUSED_C8FF.S */ 10134/* File: armv5te/unused.S */ 10135 bl common_abort 10136 10137 10138/* ------------------------------ */ 10139 .balign 64 10140.L_OP_UNUSED_C9FF: /* 0x1c9 */ 10141/* File: armv5te/OP_UNUSED_C9FF.S */ 10142/* File: armv5te/unused.S */ 10143 bl common_abort 10144 10145 10146/* ------------------------------ */ 10147 .balign 64 10148.L_OP_UNUSED_CAFF: /* 0x1ca */ 10149/* File: armv5te/OP_UNUSED_CAFF.S */ 10150/* File: armv5te/unused.S */ 10151 bl common_abort 10152 10153 10154/* ------------------------------ */ 10155 .balign 64 10156.L_OP_UNUSED_CBFF: /* 0x1cb */ 10157/* File: armv5te/OP_UNUSED_CBFF.S */ 10158/* File: armv5te/unused.S */ 10159 bl common_abort 10160 10161 10162/* ------------------------------ */ 10163 .balign 64 10164.L_OP_UNUSED_CCFF: /* 0x1cc */ 10165/* File: armv5te/OP_UNUSED_CCFF.S */ 10166/* File: armv5te/unused.S */ 10167 bl common_abort 10168 10169 10170/* ------------------------------ */ 10171 .balign 64 10172.L_OP_UNUSED_CDFF: /* 0x1cd */ 10173/* File: armv5te/OP_UNUSED_CDFF.S */ 10174/* File: armv5te/unused.S */ 10175 bl common_abort 10176 10177 10178/* ------------------------------ */ 10179 .balign 64 10180.L_OP_UNUSED_CEFF: /* 0x1ce */ 10181/* File: armv5te/OP_UNUSED_CEFF.S */ 10182/* File: armv5te/unused.S */ 10183 bl common_abort 10184 10185 10186/* ------------------------------ */ 10187 .balign 64 10188.L_OP_UNUSED_CFFF: /* 0x1cf */ 10189/* File: armv5te/OP_UNUSED_CFFF.S */ 10190/* File: armv5te/unused.S */ 10191 bl common_abort 10192 10193 10194/* ------------------------------ */ 10195 .balign 64 10196.L_OP_UNUSED_D0FF: /* 0x1d0 */ 10197/* File: armv5te/OP_UNUSED_D0FF.S */ 10198/* File: armv5te/unused.S */ 10199 bl common_abort 10200 10201 10202/* ------------------------------ */ 10203 .balign 64 10204.L_OP_UNUSED_D1FF: /* 0x1d1 */ 10205/* File: armv5te/OP_UNUSED_D1FF.S */ 10206/* File: armv5te/unused.S */ 10207 bl common_abort 10208 10209 10210/* ------------------------------ */ 10211 .balign 64 10212.L_OP_UNUSED_D2FF: /* 0x1d2 */ 10213/* File: armv5te/OP_UNUSED_D2FF.S */ 10214/* File: armv5te/unused.S */ 10215 bl common_abort 10216 10217 10218/* ------------------------------ */ 10219 .balign 64 10220.L_OP_UNUSED_D3FF: /* 0x1d3 */ 10221/* File: armv5te/OP_UNUSED_D3FF.S */ 10222/* File: armv5te/unused.S */ 10223 bl common_abort 10224 10225 10226/* ------------------------------ */ 10227 .balign 64 10228.L_OP_UNUSED_D4FF: /* 0x1d4 */ 10229/* File: armv5te/OP_UNUSED_D4FF.S */ 10230/* File: armv5te/unused.S */ 10231 bl common_abort 10232 10233 10234/* ------------------------------ */ 10235 .balign 64 10236.L_OP_UNUSED_D5FF: /* 0x1d5 */ 10237/* File: armv5te/OP_UNUSED_D5FF.S */ 10238/* File: armv5te/unused.S */ 10239 bl common_abort 10240 10241 10242/* ------------------------------ */ 10243 .balign 64 10244.L_OP_UNUSED_D6FF: /* 0x1d6 */ 10245/* File: armv5te/OP_UNUSED_D6FF.S */ 10246/* File: armv5te/unused.S */ 10247 bl common_abort 10248 10249 10250/* ------------------------------ */ 10251 .balign 64 10252.L_OP_UNUSED_D7FF: /* 0x1d7 */ 10253/* File: armv5te/OP_UNUSED_D7FF.S */ 10254/* File: armv5te/unused.S */ 10255 bl common_abort 10256 10257 10258/* ------------------------------ */ 10259 .balign 64 10260.L_OP_UNUSED_D8FF: /* 0x1d8 */ 10261/* File: armv5te/OP_UNUSED_D8FF.S */ 10262/* File: armv5te/unused.S */ 10263 bl common_abort 10264 10265 10266/* ------------------------------ */ 10267 .balign 64 10268.L_OP_UNUSED_D9FF: /* 0x1d9 */ 10269/* File: armv5te/OP_UNUSED_D9FF.S */ 10270/* File: armv5te/unused.S */ 10271 bl common_abort 10272 10273 10274/* ------------------------------ */ 10275 .balign 64 10276.L_OP_UNUSED_DAFF: /* 0x1da */ 10277/* File: armv5te/OP_UNUSED_DAFF.S */ 10278/* File: armv5te/unused.S */ 10279 bl common_abort 10280 10281 10282/* ------------------------------ */ 10283 .balign 64 10284.L_OP_UNUSED_DBFF: /* 0x1db */ 10285/* File: armv5te/OP_UNUSED_DBFF.S */ 10286/* File: armv5te/unused.S */ 10287 bl common_abort 10288 10289 10290/* ------------------------------ */ 10291 .balign 64 10292.L_OP_UNUSED_DCFF: /* 0x1dc */ 10293/* File: armv5te/OP_UNUSED_DCFF.S */ 10294/* File: armv5te/unused.S */ 10295 bl common_abort 10296 10297 10298/* ------------------------------ */ 10299 .balign 64 10300.L_OP_UNUSED_DDFF: /* 0x1dd */ 10301/* File: armv5te/OP_UNUSED_DDFF.S */ 10302/* File: armv5te/unused.S */ 10303 bl common_abort 10304 10305 10306/* ------------------------------ */ 10307 .balign 64 10308.L_OP_UNUSED_DEFF: /* 0x1de */ 10309/* File: armv5te/OP_UNUSED_DEFF.S */ 10310/* File: armv5te/unused.S */ 10311 bl common_abort 10312 10313 10314/* ------------------------------ */ 10315 .balign 64 10316.L_OP_UNUSED_DFFF: /* 0x1df */ 10317/* File: armv5te/OP_UNUSED_DFFF.S */ 10318/* File: armv5te/unused.S */ 10319 bl common_abort 10320 10321 10322/* ------------------------------ */ 10323 .balign 64 10324.L_OP_UNUSED_E0FF: /* 0x1e0 */ 10325/* File: armv5te/OP_UNUSED_E0FF.S */ 10326/* File: armv5te/unused.S */ 10327 bl common_abort 10328 10329 10330/* ------------------------------ */ 10331 .balign 64 10332.L_OP_UNUSED_E1FF: /* 0x1e1 */ 10333/* File: armv5te/OP_UNUSED_E1FF.S */ 10334/* File: armv5te/unused.S */ 10335 bl common_abort 10336 10337 10338/* ------------------------------ */ 10339 .balign 64 10340.L_OP_UNUSED_E2FF: /* 0x1e2 */ 10341/* File: armv5te/OP_UNUSED_E2FF.S */ 10342/* File: armv5te/unused.S */ 10343 bl common_abort 10344 10345 10346/* ------------------------------ */ 10347 .balign 64 10348.L_OP_UNUSED_E3FF: /* 0x1e3 */ 10349/* File: armv5te/OP_UNUSED_E3FF.S */ 10350/* File: armv5te/unused.S */ 10351 bl common_abort 10352 10353 10354/* ------------------------------ */ 10355 .balign 64 10356.L_OP_UNUSED_E4FF: /* 0x1e4 */ 10357/* File: armv5te/OP_UNUSED_E4FF.S */ 10358/* File: armv5te/unused.S */ 10359 bl common_abort 10360 10361 10362/* ------------------------------ */ 10363 .balign 64 10364.L_OP_UNUSED_E5FF: /* 0x1e5 */ 10365/* File: armv5te/OP_UNUSED_E5FF.S */ 10366/* File: armv5te/unused.S */ 10367 bl common_abort 10368 10369 10370/* ------------------------------ */ 10371 .balign 64 10372.L_OP_UNUSED_E6FF: /* 0x1e6 */ 10373/* File: armv5te/OP_UNUSED_E6FF.S */ 10374/* File: armv5te/unused.S */ 10375 bl common_abort 10376 10377 10378/* ------------------------------ */ 10379 .balign 64 10380.L_OP_UNUSED_E7FF: /* 0x1e7 */ 10381/* File: armv5te/OP_UNUSED_E7FF.S */ 10382/* File: armv5te/unused.S */ 10383 bl common_abort 10384 10385 10386/* ------------------------------ */ 10387 .balign 64 10388.L_OP_UNUSED_E8FF: /* 0x1e8 */ 10389/* File: armv5te/OP_UNUSED_E8FF.S */ 10390/* File: armv5te/unused.S */ 10391 bl common_abort 10392 10393 10394/* ------------------------------ */ 10395 .balign 64 10396.L_OP_UNUSED_E9FF: /* 0x1e9 */ 10397/* File: armv5te/OP_UNUSED_E9FF.S */ 10398/* File: armv5te/unused.S */ 10399 bl common_abort 10400 10401 10402/* ------------------------------ */ 10403 .balign 64 10404.L_OP_UNUSED_EAFF: /* 0x1ea */ 10405/* File: armv5te/OP_UNUSED_EAFF.S */ 10406/* File: armv5te/unused.S */ 10407 bl common_abort 10408 10409 10410/* ------------------------------ */ 10411 .balign 64 10412.L_OP_UNUSED_EBFF: /* 0x1eb */ 10413/* File: armv5te/OP_UNUSED_EBFF.S */ 10414/* File: armv5te/unused.S */ 10415 bl common_abort 10416 10417 10418/* ------------------------------ */ 10419 .balign 64 10420.L_OP_UNUSED_ECFF: /* 0x1ec */ 10421/* File: armv5te/OP_UNUSED_ECFF.S */ 10422/* File: armv5te/unused.S */ 10423 bl common_abort 10424 10425 10426/* ------------------------------ */ 10427 .balign 64 10428.L_OP_UNUSED_EDFF: /* 0x1ed */ 10429/* File: armv5te/OP_UNUSED_EDFF.S */ 10430/* File: armv5te/unused.S */ 10431 bl common_abort 10432 10433 10434/* ------------------------------ */ 10435 .balign 64 10436.L_OP_UNUSED_EEFF: /* 0x1ee */ 10437/* File: armv5te/OP_UNUSED_EEFF.S */ 10438/* File: armv5te/unused.S */ 10439 bl common_abort 10440 10441 10442/* ------------------------------ */ 10443 .balign 64 10444.L_OP_UNUSED_EFFF: /* 0x1ef */ 10445/* File: armv5te/OP_UNUSED_EFFF.S */ 10446/* File: armv5te/unused.S */ 10447 bl common_abort 10448 10449 10450/* ------------------------------ */ 10451 .balign 64 10452.L_OP_UNUSED_F0FF: /* 0x1f0 */ 10453/* File: armv5te/OP_UNUSED_F0FF.S */ 10454/* File: armv5te/unused.S */ 10455 bl common_abort 10456 10457 10458/* ------------------------------ */ 10459 .balign 64 10460.L_OP_UNUSED_F1FF: /* 0x1f1 */ 10461/* File: armv5te/OP_UNUSED_F1FF.S */ 10462/* File: armv5te/unused.S */ 10463 bl common_abort 10464 10465 10466/* ------------------------------ */ 10467 .balign 64 10468.L_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */ 10469/* File: armv5te/OP_INVOKE_OBJECT_INIT_JUMBO.S */ 10470/* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */ 10471 /* 10472 * Invoke Object.<init> on an object. In practice we know that 10473 * Object's nullary constructor doesn't do anything, so we just 10474 * skip it (we know a debugger isn't active). 10475 */ 10476 FETCH(r1, 4) @ r1<- CCCC 10477 GET_VREG(r0, r1) @ r0<- "this" ptr 10478 cmp r0, #0 @ check for NULL 10479 beq common_errNullObject @ export PC and throw NPE 10480 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 10481 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 10482 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 10483 beq 1f @ nope, done 10484 EXPORT_PC() @ can throw 10485 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 104861: FETCH_ADVANCE_INST(4+1) @ advance to next instr, load rINST 10487 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 10488 GOTO_OPCODE(ip) @ execute it 10489 10490 10491/* ------------------------------ */ 10492 .balign 64 10493.L_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */ 10494/* File: armv5te/OP_IGET_VOLATILE_JUMBO.S */ 10495/* File: armv5te/OP_IGET_JUMBO.S */ 10496 /* 10497 * Jumbo 32-bit instance field get. 10498 * 10499 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 10500 * iget-char/jumbo, iget-short/jumbo 10501 */ 10502 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 10503 FETCH(r1, 1) @ r1<- aaaa (lo) 10504 FETCH(r2, 2) @ r2<- AAAA (hi) 10505 FETCH(r0, 4) @ r0<- CCCC 10506 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10507 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10508 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10509 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10510 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10511 cmp r0, #0 @ is resolved entry null? 10512 bne .LOP_IGET_VOLATILE_JUMBO_finish @ no, already resolved 105138: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10514 EXPORT_PC() @ resolve() could throw 10515 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10516 bl dvmResolveInstField @ r0<- resolved InstField ptr 10517 b .LOP_IGET_VOLATILE_JUMBO_resolved @ resolved, continue 10518 10519 10520/* ------------------------------ */ 10521 .balign 64 10522.L_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */ 10523/* File: armv5te/OP_IGET_WIDE_VOLATILE_JUMBO.S */ 10524/* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 10525 /* 10526 * Jumbo 64-bit instance field get. 10527 */ 10528 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 10529 FETCH(r1, 1) @ r1<- aaaa (lo) 10530 FETCH(r2, 2) @ r2<- AAAA (hi) 10531 FETCH(r0, 4) @ r0<- CCCC 10532 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10533 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10534 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 10535 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10536 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10537 cmp r0, #0 @ is resolved entry null? 10538 bne .LOP_IGET_WIDE_VOLATILE_JUMBO_finish @ no, already resolved 10539 ldr r2, [rSELF, #offThread_method] @ r2<- current method 10540 EXPORT_PC() @ resolve() could throw 10541 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10542 bl dvmResolveInstField @ r0<- resolved InstField ptr 10543 b .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue 10544 10545 10546/* ------------------------------ */ 10547 .balign 64 10548.L_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */ 10549/* File: armv5te/OP_IGET_OBJECT_VOLATILE_JUMBO.S */ 10550/* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 10551/* File: armv5te/OP_IGET_JUMBO.S */ 10552 /* 10553 * Jumbo 32-bit instance field get. 10554 * 10555 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 10556 * iget-char/jumbo, iget-short/jumbo 10557 */ 10558 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 10559 FETCH(r1, 1) @ r1<- aaaa (lo) 10560 FETCH(r2, 2) @ r2<- AAAA (hi) 10561 FETCH(r0, 4) @ r0<- CCCC 10562 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10563 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10564 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10565 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10566 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10567 cmp r0, #0 @ is resolved entry null? 10568 bne .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved 105698: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10570 EXPORT_PC() @ resolve() could throw 10571 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10572 bl dvmResolveInstField @ r0<- resolved InstField ptr 10573 b .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue 10574 10575 10576 10577/* ------------------------------ */ 10578 .balign 64 10579.L_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */ 10580/* File: armv5te/OP_IPUT_VOLATILE_JUMBO.S */ 10581/* File: armv5te/OP_IPUT_JUMBO.S */ 10582 /* 10583 * Jumbo 32-bit instance field put. 10584 * 10585 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 10586 * iput-short/jumbo 10587 */ 10588 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 10589 FETCH(r1, 1) @ r1<- aaaa (lo) 10590 FETCH(r2, 2) @ r2<- AAAA (hi) 10591 FETCH(r0, 4) @ r0<- CCCC 10592 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10593 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10594 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10595 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10596 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10597 cmp r0, #0 @ is resolved entry null? 10598 bne .LOP_IPUT_VOLATILE_JUMBO_finish @ no, already resolved 105998: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10600 EXPORT_PC() @ resolve() could throw 10601 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10602 bl dvmResolveInstField @ r0<- resolved InstField ptr 10603 b .LOP_IPUT_VOLATILE_JUMBO_resolved @ resolved, continue 10604 10605 10606/* ------------------------------ */ 10607 .balign 64 10608.L_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */ 10609/* File: armv5te/OP_IPUT_WIDE_VOLATILE_JUMBO.S */ 10610/* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 10611 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 10612 FETCH(r1, 1) @ r1<- aaaa (lo) 10613 FETCH(r2, 2) @ r2<- AAAA (hi) 10614 FETCH(r0, 4) @ r0<- CCCC 10615 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10616 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10617 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 10618 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 10619 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10620 cmp r0, #0 @ is resolved entry null? 10621 bne .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish @ no, already resolved 106228: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10623 EXPORT_PC() @ resolve() could throw 10624 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10625 bl dvmResolveInstField @ r0<- resolved InstField ptr 10626 b .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue 10627 10628 10629/* ------------------------------ */ 10630 .balign 64 10631.L_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */ 10632/* File: armv5te/OP_IPUT_OBJECT_VOLATILE_JUMBO.S */ 10633/* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 10634 /* 10635 * Jumbo 32-bit instance field put. 10636 */ 10637 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 10638 FETCH(r1, 1) @ r1<- aaaa (lo) 10639 FETCH(r2, 2) @ r2<- AAAA (hi) 10640 FETCH(r0, 4) @ r0<- CCCC 10641 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10642 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10643 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10644 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10645 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10646 cmp r0, #0 @ is resolved entry null? 10647 bne .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved 106488: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10649 EXPORT_PC() @ resolve() could throw 10650 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10651 bl dvmResolveInstField @ r0<- resolved InstField ptr 10652 b .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue 10653 10654 10655/* ------------------------------ */ 10656 .balign 64 10657.L_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */ 10658/* File: armv5te/OP_SGET_VOLATILE_JUMBO.S */ 10659/* File: armv5te/OP_SGET_JUMBO.S */ 10660 /* 10661 * Jumbo 32-bit SGET handler. 10662 * 10663 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 10664 * sget-char/jumbo, sget-short/jumbo 10665 */ 10666 /* exop vBBBB, field@AAAAAAAA */ 10667 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10668 FETCH(r0, 1) @ r0<- aaaa (lo) 10669 FETCH(r1, 2) @ r1<- AAAA (hi) 10670 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10671 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10672 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10673 cmp r0, #0 @ is resolved entry null? 10674 beq .LOP_SGET_VOLATILE_JUMBO_resolve @ yes, do resolve 10675.LOP_SGET_VOLATILE_JUMBO_finish: @ field ptr in r0 10676 ldr r1, [r0, #offStaticField_value] @ r1<- field value 10677 SMP_DMB @ acquiring load 10678 FETCH(r2, 3) @ r2<- BBBB 10679 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10680 SET_VREG(r1, r2) @ fp[BBBB]<- r1 10681 GET_INST_OPCODE(ip) @ extract opcode from rINST 10682 GOTO_OPCODE(ip) @ jump to next instruction 10683 10684 10685/* ------------------------------ */ 10686 .balign 64 10687.L_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */ 10688/* File: armv5te/OP_SGET_WIDE_VOLATILE_JUMBO.S */ 10689/* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 10690 /* 10691 * Jumbo 64-bit SGET handler. 10692 */ 10693 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 10694 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10695 FETCH(r0, 1) @ r0<- aaaa (lo) 10696 FETCH(r1, 2) @ r1<- AAAA (hi) 10697 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10698 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10699 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10700 cmp r0, #0 @ is resolved entry null? 10701 beq .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve 10702.LOP_SGET_WIDE_VOLATILE_JUMBO_finish: 10703 FETCH(r9, 3) @ r9<- BBBB 10704 .if 1 10705 add r0, r0, #offStaticField_value @ r0<- pointer to data 10706 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 10707 .else 10708 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 10709 .endif 10710 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 10711 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10712 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 10713 GET_INST_OPCODE(ip) @ extract opcode from rINST 10714 GOTO_OPCODE(ip) @ jump to next instruction 10715 10716 10717/* ------------------------------ */ 10718 .balign 64 10719.L_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */ 10720/* File: armv5te/OP_SGET_OBJECT_VOLATILE_JUMBO.S */ 10721/* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 10722/* File: armv5te/OP_SGET_JUMBO.S */ 10723 /* 10724 * Jumbo 32-bit SGET handler. 10725 * 10726 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 10727 * sget-char/jumbo, sget-short/jumbo 10728 */ 10729 /* exop vBBBB, field@AAAAAAAA */ 10730 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10731 FETCH(r0, 1) @ r0<- aaaa (lo) 10732 FETCH(r1, 2) @ r1<- AAAA (hi) 10733 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10734 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10735 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10736 cmp r0, #0 @ is resolved entry null? 10737 beq .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve 10738.LOP_SGET_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0 10739 ldr r1, [r0, #offStaticField_value] @ r1<- field value 10740 SMP_DMB @ acquiring load 10741 FETCH(r2, 3) @ r2<- BBBB 10742 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10743 SET_VREG(r1, r2) @ fp[BBBB]<- r1 10744 GET_INST_OPCODE(ip) @ extract opcode from rINST 10745 GOTO_OPCODE(ip) @ jump to next instruction 10746 10747 10748 10749/* ------------------------------ */ 10750 .balign 64 10751.L_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */ 10752/* File: armv5te/OP_SPUT_VOLATILE_JUMBO.S */ 10753/* File: armv5te/OP_SPUT_JUMBO.S */ 10754 /* 10755 * Jumbo 32-bit SPUT handler. 10756 * 10757 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 10758 * sput-short/jumbo 10759 */ 10760 /* exop vBBBB, field@AAAAAAAA */ 10761 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10762 FETCH(r0, 1) @ r0<- aaaa (lo) 10763 FETCH(r1, 2) @ r1<- AAAA (hi) 10764 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10765 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10766 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10767 cmp r0, #0 @ is resolved entry null? 10768 beq .LOP_SPUT_VOLATILE_JUMBO_resolve @ yes, do resolve 10769.LOP_SPUT_VOLATILE_JUMBO_finish: @ field ptr in r0 10770 FETCH(r2, 3) @ r2<- BBBB 10771 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10772 GET_VREG(r1, r2) @ r1<- fp[BBBB] 10773 GET_INST_OPCODE(ip) @ extract opcode from rINST 10774 SMP_DMB @ releasing store 10775 str r1, [r0, #offStaticField_value] @ field<- vBBBB 10776 GOTO_OPCODE(ip) @ jump to next instruction 10777 10778 10779/* ------------------------------ */ 10780 .balign 64 10781.L_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */ 10782/* File: armv5te/OP_SPUT_WIDE_VOLATILE_JUMBO.S */ 10783/* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 10784 /* 10785 * Jumbo 64-bit SPUT handler. 10786 */ 10787 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 10788 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 10789 FETCH(r1, 1) @ r1<- aaaa (lo) 10790 FETCH(r2, 2) @ r2<- AAAA (hi) 10791 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 10792 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10793 FETCH(r9, 3) @ r9<- BBBB 10794 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 10795 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 10796 cmp r2, #0 @ is resolved entry null? 10797 beq .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve 10798.LOP_SPUT_WIDE_VOLATILE_JUMBO_finish: @ field ptr in r2, BBBB in r9 10799 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10800 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 10801 GET_INST_OPCODE(r10) @ extract opcode from rINST 10802 .if 1 10803 add r2, r2, #offStaticField_value @ r2<- pointer to data 10804 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 10805 .else 10806 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 10807 .endif 10808 GOTO_OPCODE(r10) @ jump to next instruction 10809 10810 10811/* ------------------------------ */ 10812 .balign 64 10813.L_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */ 10814/* File: armv5te/OP_SPUT_OBJECT_VOLATILE_JUMBO.S */ 10815/* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 10816 /* 10817 * Jumbo 32-bit SPUT handler for objects 10818 */ 10819 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 10820 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10821 FETCH(r0, 1) @ r0<- aaaa (lo) 10822 FETCH(r1, 2) @ r1<- AAAA (hi) 10823 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10824 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10825 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10826 cmp r0, #0 @ is resolved entry null? 10827 bne .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ no, continue 10828 ldr r9, [rSELF, #offThread_method] @ r9<- current method 10829 EXPORT_PC() @ resolve() could throw, so export now 10830 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 10831 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 10832 cmp r0, #0 @ success? 10833 bne .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ yes, finish 10834 b common_exceptionThrown @ no, handle exception 10835 10836 10837/* ------------------------------ */ 10838 .balign 64 10839.L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 10840/* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */ 10841 /* 10842 * Handle a jumbo throw-verification-error instruction. This throws an 10843 * exception for an error discovered during verification. The 10844 * exception is indicated by BBBB, with some detail provided by AAAAAAAA. 10845 */ 10846 /* exop BBBB, Class@AAAAAAAA */ 10847 FETCH(r1, 1) @ r1<- aaaa (lo) 10848 FETCH(r2, 2) @ r2<- AAAA (hi) 10849 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10850 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa 10851 EXPORT_PC() @ export the PC 10852 FETCH(r1, 3) @ r1<- BBBB 10853 bl dvmThrowVerificationError @ always throws 10854 b common_exceptionThrown @ handle exception 10855 10856 .balign 64 10857 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 10858 .global dvmAsmInstructionEnd 10859dvmAsmInstructionEnd: 10860 10861/* 10862 * =========================================================================== 10863 * Sister implementations 10864 * =========================================================================== 10865 */ 10866 .global dvmAsmSisterStart 10867 .type dvmAsmSisterStart, %function 10868 .text 10869 .balign 4 10870dvmAsmSisterStart: 10871 10872/* continuation for OP_CONST_STRING */ 10873 10874 /* 10875 * Continuation if the String has not yet been resolved. 10876 * r1: BBBB (String ref) 10877 * r9: target register 10878 */ 10879.LOP_CONST_STRING_resolve: 10880 EXPORT_PC() 10881 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10882 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10883 bl dvmResolveString @ r0<- String reference 10884 cmp r0, #0 @ failed? 10885 beq common_exceptionThrown @ yup, handle the exception 10886 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10887 GET_INST_OPCODE(ip) @ extract opcode from rINST 10888 SET_VREG(r0, r9) @ vAA<- r0 10889 GOTO_OPCODE(ip) @ jump to next instruction 10890 10891/* continuation for OP_CONST_STRING_JUMBO */ 10892 10893 /* 10894 * Continuation if the String has not yet been resolved. 10895 * r1: BBBBBBBB (String ref) 10896 * r9: target register 10897 */ 10898.LOP_CONST_STRING_JUMBO_resolve: 10899 EXPORT_PC() 10900 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10901 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10902 bl dvmResolveString @ r0<- String reference 10903 cmp r0, #0 @ failed? 10904 beq common_exceptionThrown @ yup, handle the exception 10905 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10906 GET_INST_OPCODE(ip) @ extract opcode from rINST 10907 SET_VREG(r0, r9) @ vAA<- r0 10908 GOTO_OPCODE(ip) @ jump to next instruction 10909 10910/* continuation for OP_CONST_CLASS */ 10911 10912 /* 10913 * Continuation if the Class has not yet been resolved. 10914 * r1: BBBB (Class ref) 10915 * r9: target register 10916 */ 10917.LOP_CONST_CLASS_resolve: 10918 EXPORT_PC() 10919 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10920 mov r2, #1 @ r2<- true 10921 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10922 bl dvmResolveClass @ r0<- Class reference 10923 cmp r0, #0 @ failed? 10924 beq common_exceptionThrown @ yup, handle the exception 10925 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10926 GET_INST_OPCODE(ip) @ extract opcode from rINST 10927 SET_VREG(r0, r9) @ vAA<- r0 10928 GOTO_OPCODE(ip) @ jump to next instruction 10929 10930/* continuation for OP_CHECK_CAST */ 10931 10932 /* 10933 * Trivial test failed, need to perform full check. This is common. 10934 * r0 holds obj->clazz 10935 * r1 holds desired class resolved from BBBB 10936 * r9 holds object 10937 */ 10938.LOP_CHECK_CAST_fullcheck: 10939 mov r10, r1 @ avoid ClassObject getting clobbered 10940 bl dvmInstanceofNonTrivial @ r0<- boolean result 10941 cmp r0, #0 @ failed? 10942 bne .LOP_CHECK_CAST_okay @ no, success 10943 10944 @ A cast has failed. We need to throw a ClassCastException. 10945 EXPORT_PC() @ about to throw 10946 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 10947 mov r1, r10 @ r1<- desired class 10948 bl dvmThrowClassCastException 10949 b common_exceptionThrown 10950 10951 /* 10952 * Resolution required. This is the least-likely path. 10953 * 10954 * r2 holds BBBB 10955 * r9 holds object 10956 */ 10957.LOP_CHECK_CAST_resolve: 10958 EXPORT_PC() @ resolve() could throw 10959 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10960 mov r1, r2 @ r1<- BBBB 10961 mov r2, #0 @ r2<- false 10962 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10963 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10964 cmp r0, #0 @ got null? 10965 beq common_exceptionThrown @ yes, handle exception 10966 mov r1, r0 @ r1<- class resolved from BBB 10967 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 10968 b .LOP_CHECK_CAST_resolved @ pick up where we left off 10969 10970/* continuation for OP_INSTANCE_OF */ 10971 10972 /* 10973 * Trivial test failed, need to perform full check. This is common. 10974 * r0 holds obj->clazz 10975 * r1 holds class resolved from BBBB 10976 * r9 holds A 10977 */ 10978.LOP_INSTANCE_OF_fullcheck: 10979 bl dvmInstanceofNonTrivial @ r0<- boolean result 10980 @ fall through to OP_INSTANCE_OF_store 10981 10982 /* 10983 * r0 holds boolean result 10984 * r9 holds A 10985 */ 10986.LOP_INSTANCE_OF_store: 10987 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10988 SET_VREG(r0, r9) @ vA<- r0 10989 GET_INST_OPCODE(ip) @ extract opcode from rINST 10990 GOTO_OPCODE(ip) @ jump to next instruction 10991 10992 /* 10993 * Trivial test succeeded, save and bail. 10994 * r9 holds A 10995 */ 10996.LOP_INSTANCE_OF_trivial: 10997 mov r0, #1 @ indicate success 10998 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 10999 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11000 SET_VREG(r0, r9) @ vA<- r0 11001 GET_INST_OPCODE(ip) @ extract opcode from rINST 11002 GOTO_OPCODE(ip) @ jump to next instruction 11003 11004 /* 11005 * Resolution required. This is the least-likely path. 11006 * 11007 * r3 holds BBBB 11008 * r9 holds A 11009 */ 11010.LOP_INSTANCE_OF_resolve: 11011 EXPORT_PC() @ resolve() could throw 11012 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 11013 mov r1, r3 @ r1<- BBBB 11014 mov r2, #1 @ r2<- true 11015 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 11016 bl dvmResolveClass @ r0<- resolved ClassObject ptr 11017 cmp r0, #0 @ got null? 11018 beq common_exceptionThrown @ yes, handle exception 11019 mov r1, r0 @ r1<- class resolved from BBB 11020 mov r3, rINST, lsr #12 @ r3<- B 11021 GET_VREG(r0, r3) @ r0<- vB (object) 11022 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 11023 b .LOP_INSTANCE_OF_resolved @ pick up where we left off 11024 11025/* continuation for OP_NEW_INSTANCE */ 11026 11027 .balign 32 @ minimize cache lines 11028.LOP_NEW_INSTANCE_finish: @ r0=new object 11029 mov r3, rINST, lsr #8 @ r3<- AA 11030 cmp r0, #0 @ failed? 11031 beq common_exceptionThrown @ yes, handle the exception 11032 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11033 GET_INST_OPCODE(ip) @ extract opcode from rINST 11034 SET_VREG(r0, r3) @ vAA<- r0 11035 GOTO_OPCODE(ip) @ jump to next instruction 11036 11037 /* 11038 * Class initialization required. 11039 * 11040 * r0 holds class object 11041 */ 11042.LOP_NEW_INSTANCE_needinit: 11043 mov r9, r0 @ save r0 11044 bl dvmInitClass @ initialize class 11045 cmp r0, #0 @ check boolean result 11046 mov r0, r9 @ restore r0 11047 bne .LOP_NEW_INSTANCE_initialized @ success, continue 11048 b common_exceptionThrown @ failed, deal with init exception 11049 11050 /* 11051 * Resolution required. This is the least-likely path. 11052 * 11053 * r1 holds BBBB 11054 */ 11055.LOP_NEW_INSTANCE_resolve: 11056 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11057 mov r2, #0 @ r2<- false 11058 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11059 bl dvmResolveClass @ r0<- resolved ClassObject ptr 11060 cmp r0, #0 @ got null? 11061 bne .LOP_NEW_INSTANCE_resolved @ no, continue 11062 b common_exceptionThrown @ yes, handle exception 11063 11064/* continuation for OP_NEW_ARRAY */ 11065 11066 11067 /* 11068 * Resolve class. (This is an uncommon case.) 11069 * 11070 * r1 holds array length 11071 * r2 holds class ref CCCC 11072 */ 11073.LOP_NEW_ARRAY_resolve: 11074 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11075 mov r9, r1 @ r9<- length (save) 11076 mov r1, r2 @ r1<- CCCC 11077 mov r2, #0 @ r2<- false 11078 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11079 bl dvmResolveClass @ r0<- call(clazz, ref) 11080 cmp r0, #0 @ got null? 11081 mov r1, r9 @ r1<- length (restore) 11082 beq common_exceptionThrown @ yes, handle exception 11083 @ fall through to OP_NEW_ARRAY_finish 11084 11085 /* 11086 * Finish allocation. 11087 * 11088 * r0 holds class 11089 * r1 holds array length 11090 */ 11091.LOP_NEW_ARRAY_finish: 11092 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 11093 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 11094 cmp r0, #0 @ failed? 11095 mov r2, rINST, lsr #8 @ r2<- A+ 11096 beq common_exceptionThrown @ yes, handle the exception 11097 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11098 and r2, r2, #15 @ r2<- A 11099 GET_INST_OPCODE(ip) @ extract opcode from rINST 11100 SET_VREG(r0, r2) @ vA<- r0 11101 GOTO_OPCODE(ip) @ jump to next instruction 11102 11103/* continuation for OP_FILLED_NEW_ARRAY */ 11104 11105 /* 11106 * On entry: 11107 * r0 holds array class 11108 * r10 holds AA or BA 11109 */ 11110.LOP_FILLED_NEW_ARRAY_continue: 11111 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 11112 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 11113 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 11114 .if 0 11115 mov r1, r10 @ r1<- AA (length) 11116 .else 11117 mov r1, r10, lsr #4 @ r1<- B (length) 11118 .endif 11119 cmp rINST, #'I' @ array of ints? 11120 cmpne rINST, #'L' @ array of objects? 11121 cmpne rINST, #'[' @ array of arrays? 11122 mov r9, r1 @ save length in r9 11123 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 11124 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 11125 cmp r0, #0 @ null return? 11126 beq common_exceptionThrown @ alloc failed, handle exception 11127 11128 FETCH(r1, 2) @ r1<- FEDC or CCCC 11129 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 11130 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 11131 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 11132 subs r9, r9, #1 @ length--, check for neg 11133 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 11134 bmi 2f @ was zero, bail 11135 11136 @ copy values from registers into the array 11137 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 11138 .if 0 11139 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 111401: ldr r3, [r2], #4 @ r3<- *r2++ 11141 subs r9, r9, #1 @ count-- 11142 str r3, [r0], #4 @ *contents++ = vX 11143 bpl 1b 11144 @ continue at 2 11145 .else 11146 cmp r9, #4 @ length was initially 5? 11147 and r2, r10, #15 @ r2<- A 11148 bne 1f @ <= 4 args, branch 11149 GET_VREG(r3, r2) @ r3<- vA 11150 sub r9, r9, #1 @ count-- 11151 str r3, [r0, #16] @ contents[4] = vA 111521: and r2, r1, #15 @ r2<- F/E/D/C 11153 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 11154 mov r1, r1, lsr #4 @ r1<- next reg in low 4 11155 subs r9, r9, #1 @ count-- 11156 str r3, [r0], #4 @ *contents++ = vX 11157 bpl 1b 11158 @ continue at 2 11159 .endif 11160 111612: 11162 ldr r0, [rSELF, #offThread_retval] @ r0<- object 11163 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 11164 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11165 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 11166 cmp r1, #'I' @ Is int array? 11167 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 11168 GOTO_OPCODE(ip) @ execute it 11169 11170 /* 11171 * Throw an exception indicating that we have not implemented this 11172 * mode of filled-new-array. 11173 */ 11174.LOP_FILLED_NEW_ARRAY_notimpl: 11175 ldr r0, .L_strFilledNewArrayNotImpl 11176 bl dvmThrowInternalError 11177 b common_exceptionThrown 11178 11179 .if (!0) @ define in one or the other, not both 11180.L_strFilledNewArrayNotImpl: 11181 .word .LstrFilledNewArrayNotImpl 11182 .endif 11183 11184/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 11185 11186 /* 11187 * On entry: 11188 * r0 holds array class 11189 * r10 holds AA or BA 11190 */ 11191.LOP_FILLED_NEW_ARRAY_RANGE_continue: 11192 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 11193 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 11194 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 11195 .if 1 11196 mov r1, r10 @ r1<- AA (length) 11197 .else 11198 mov r1, r10, lsr #4 @ r1<- B (length) 11199 .endif 11200 cmp rINST, #'I' @ array of ints? 11201 cmpne rINST, #'L' @ array of objects? 11202 cmpne rINST, #'[' @ array of arrays? 11203 mov r9, r1 @ save length in r9 11204 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 11205 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 11206 cmp r0, #0 @ null return? 11207 beq common_exceptionThrown @ alloc failed, handle exception 11208 11209 FETCH(r1, 2) @ r1<- FEDC or CCCC 11210 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 11211 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 11212 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 11213 subs r9, r9, #1 @ length--, check for neg 11214 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 11215 bmi 2f @ was zero, bail 11216 11217 @ copy values from registers into the array 11218 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 11219 .if 1 11220 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 112211: ldr r3, [r2], #4 @ r3<- *r2++ 11222 subs r9, r9, #1 @ count-- 11223 str r3, [r0], #4 @ *contents++ = vX 11224 bpl 1b 11225 @ continue at 2 11226 .else 11227 cmp r9, #4 @ length was initially 5? 11228 and r2, r10, #15 @ r2<- A 11229 bne 1f @ <= 4 args, branch 11230 GET_VREG(r3, r2) @ r3<- vA 11231 sub r9, r9, #1 @ count-- 11232 str r3, [r0, #16] @ contents[4] = vA 112331: and r2, r1, #15 @ r2<- F/E/D/C 11234 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 11235 mov r1, r1, lsr #4 @ r1<- next reg in low 4 11236 subs r9, r9, #1 @ count-- 11237 str r3, [r0], #4 @ *contents++ = vX 11238 bpl 1b 11239 @ continue at 2 11240 .endif 11241 112422: 11243 ldr r0, [rSELF, #offThread_retval] @ r0<- object 11244 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 11245 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11246 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 11247 cmp r1, #'I' @ Is int array? 11248 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 11249 GOTO_OPCODE(ip) @ execute it 11250 11251 /* 11252 * Throw an exception indicating that we have not implemented this 11253 * mode of filled-new-array. 11254 */ 11255.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 11256 ldr r0, .L_strFilledNewArrayNotImpl 11257 bl dvmThrowInternalError 11258 b common_exceptionThrown 11259 11260 .if (!1) @ define in one or the other, not both 11261.L_strFilledNewArrayNotImpl: 11262 .word .LstrFilledNewArrayNotImpl 11263 .endif 11264 11265/* continuation for OP_CMPL_FLOAT */ 11266.LOP_CMPL_FLOAT_finish: 11267 SET_VREG(r0, r9) @ vAA<- r0 11268 GOTO_OPCODE(ip) @ jump to next instruction 11269 11270/* continuation for OP_CMPG_FLOAT */ 11271.LOP_CMPG_FLOAT_finish: 11272 SET_VREG(r0, r9) @ vAA<- r0 11273 GOTO_OPCODE(ip) @ jump to next instruction 11274 11275/* continuation for OP_CMPL_DOUBLE */ 11276.LOP_CMPL_DOUBLE_finish: 11277 SET_VREG(r0, r9) @ vAA<- r0 11278 GOTO_OPCODE(ip) @ jump to next instruction 11279 11280/* continuation for OP_CMPG_DOUBLE */ 11281.LOP_CMPG_DOUBLE_finish: 11282 SET_VREG(r0, r9) @ vAA<- r0 11283 GOTO_OPCODE(ip) @ jump to next instruction 11284 11285/* continuation for OP_CMP_LONG */ 11286 11287.LOP_CMP_LONG_less: 11288 mvn r1, #0 @ r1<- -1 11289 @ Want to cond code the next mov so we can avoid branch, but don't see it; 11290 @ instead, we just replicate the tail end. 11291 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11292 SET_VREG(r1, r9) @ vAA<- r1 11293 GET_INST_OPCODE(ip) @ extract opcode from rINST 11294 GOTO_OPCODE(ip) @ jump to next instruction 11295 11296.LOP_CMP_LONG_greater: 11297 mov r1, #1 @ r1<- 1 11298 @ fall through to _finish 11299 11300.LOP_CMP_LONG_finish: 11301 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11302 SET_VREG(r1, r9) @ vAA<- r1 11303 GET_INST_OPCODE(ip) @ extract opcode from rINST 11304 GOTO_OPCODE(ip) @ jump to next instruction 11305 11306/* continuation for OP_AGET_WIDE */ 11307 11308.LOP_AGET_WIDE_finish: 11309 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11310 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11311 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 11312 GET_INST_OPCODE(ip) @ extract opcode from rINST 11313 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 11314 GOTO_OPCODE(ip) @ jump to next instruction 11315 11316/* continuation for OP_APUT_WIDE */ 11317 11318.LOP_APUT_WIDE_finish: 11319 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11320 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 11321 GET_INST_OPCODE(ip) @ extract opcode from rINST 11322 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11323 GOTO_OPCODE(ip) @ jump to next instruction 11324 11325/* continuation for OP_APUT_OBJECT */ 11326 /* 11327 * On entry: 11328 * rINST = vBB (arrayObj) 11329 * r9 = vAA (obj) 11330 * r10 = offset into array (vBB + vCC * width) 11331 */ 11332.LOP_APUT_OBJECT_finish: 11333 cmp r9, #0 @ storing null reference? 11334 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 11335 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 11336 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz 11337 bl dvmCanPutArrayElement @ test object type vs. array type 11338 cmp r0, #0 @ okay? 11339 beq .LOP_APUT_OBJECT_throw @ no 11340 mov r1, rINST @ r1<- arrayObj 11341 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11342 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base 11343 add r10, #offArrayObject_contents @ r0<- pointer to slot 11344 GET_INST_OPCODE(ip) @ extract opcode from rINST 11345 str r9, [r10] @ vBB[vCC]<- vAA 11346 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head 11347 GOTO_OPCODE(ip) @ jump to next instruction 11348.LOP_APUT_OBJECT_skip_check: 11349 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11350 GET_INST_OPCODE(ip) @ extract opcode from rINST 11351 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 11352 GOTO_OPCODE(ip) @ jump to next instruction 11353.LOP_APUT_OBJECT_throw: 11354 @ The types don't match. We need to throw an ArrayStoreException. 11355 ldr r0, [r9, #offObject_clazz] 11356 ldr r1, [rINST, #offObject_clazz] 11357 EXPORT_PC() 11358 bl dvmThrowArrayStoreExceptionIncompatibleElement 11359 b common_exceptionThrown 11360 11361/* continuation for OP_IGET */ 11362 11363 /* 11364 * Currently: 11365 * r0 holds resolved field 11366 * r9 holds object 11367 */ 11368.LOP_IGET_finish: 11369 @bl common_squeak0 11370 cmp r9, #0 @ check object for null 11371 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11372 beq common_errNullObject @ object was null 11373 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11374 @ no-op @ acquiring load 11375 mov r2, rINST, lsr #8 @ r2<- A+ 11376 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11377 and r2, r2, #15 @ r2<- A 11378 GET_INST_OPCODE(ip) @ extract opcode from rINST 11379 SET_VREG(r0, r2) @ fp[A]<- r0 11380 GOTO_OPCODE(ip) @ jump to next instruction 11381 11382/* continuation for OP_IGET_WIDE */ 11383 11384 /* 11385 * Currently: 11386 * r0 holds resolved field 11387 * r9 holds object 11388 */ 11389.LOP_IGET_WIDE_finish: 11390 cmp r9, #0 @ check object for null 11391 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11392 beq common_errNullObject @ object was null 11393 .if 0 11394 add r0, r9, r3 @ r0<- address of field 11395 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 11396 .else 11397 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11398 .endif 11399 mov r2, rINST, lsr #8 @ r2<- A+ 11400 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11401 and r2, r2, #15 @ r2<- A 11402 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11403 GET_INST_OPCODE(ip) @ extract opcode from rINST 11404 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11405 GOTO_OPCODE(ip) @ jump to next instruction 11406 11407/* continuation for OP_IGET_OBJECT */ 11408 11409 /* 11410 * Currently: 11411 * r0 holds resolved field 11412 * r9 holds object 11413 */ 11414.LOP_IGET_OBJECT_finish: 11415 @bl common_squeak0 11416 cmp r9, #0 @ check object for null 11417 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11418 beq common_errNullObject @ object was null 11419 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11420 @ no-op @ acquiring load 11421 mov r2, rINST, lsr #8 @ r2<- A+ 11422 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11423 and r2, r2, #15 @ r2<- A 11424 GET_INST_OPCODE(ip) @ extract opcode from rINST 11425 SET_VREG(r0, r2) @ fp[A]<- r0 11426 GOTO_OPCODE(ip) @ jump to next instruction 11427 11428/* continuation for OP_IGET_BOOLEAN */ 11429 11430 /* 11431 * Currently: 11432 * r0 holds resolved field 11433 * r9 holds object 11434 */ 11435.LOP_IGET_BOOLEAN_finish: 11436 @bl common_squeak1 11437 cmp r9, #0 @ check object for null 11438 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11439 beq common_errNullObject @ object was null 11440 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11441 @ no-op @ acquiring load 11442 mov r2, rINST, lsr #8 @ r2<- A+ 11443 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11444 and r2, r2, #15 @ r2<- A 11445 GET_INST_OPCODE(ip) @ extract opcode from rINST 11446 SET_VREG(r0, r2) @ fp[A]<- r0 11447 GOTO_OPCODE(ip) @ jump to next instruction 11448 11449/* continuation for OP_IGET_BYTE */ 11450 11451 /* 11452 * Currently: 11453 * r0 holds resolved field 11454 * r9 holds object 11455 */ 11456.LOP_IGET_BYTE_finish: 11457 @bl common_squeak2 11458 cmp r9, #0 @ check object for null 11459 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11460 beq common_errNullObject @ object was null 11461 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11462 @ no-op @ acquiring load 11463 mov r2, rINST, lsr #8 @ r2<- A+ 11464 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11465 and r2, r2, #15 @ r2<- A 11466 GET_INST_OPCODE(ip) @ extract opcode from rINST 11467 SET_VREG(r0, r2) @ fp[A]<- r0 11468 GOTO_OPCODE(ip) @ jump to next instruction 11469 11470/* continuation for OP_IGET_CHAR */ 11471 11472 /* 11473 * Currently: 11474 * r0 holds resolved field 11475 * r9 holds object 11476 */ 11477.LOP_IGET_CHAR_finish: 11478 @bl common_squeak3 11479 cmp r9, #0 @ check object for null 11480 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11481 beq common_errNullObject @ object was null 11482 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11483 @ no-op @ acquiring load 11484 mov r2, rINST, lsr #8 @ r2<- A+ 11485 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11486 and r2, r2, #15 @ r2<- A 11487 GET_INST_OPCODE(ip) @ extract opcode from rINST 11488 SET_VREG(r0, r2) @ fp[A]<- r0 11489 GOTO_OPCODE(ip) @ jump to next instruction 11490 11491/* continuation for OP_IGET_SHORT */ 11492 11493 /* 11494 * Currently: 11495 * r0 holds resolved field 11496 * r9 holds object 11497 */ 11498.LOP_IGET_SHORT_finish: 11499 @bl common_squeak4 11500 cmp r9, #0 @ check object for null 11501 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11502 beq common_errNullObject @ object was null 11503 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11504 @ no-op @ acquiring load 11505 mov r2, rINST, lsr #8 @ r2<- A+ 11506 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11507 and r2, r2, #15 @ r2<- A 11508 GET_INST_OPCODE(ip) @ extract opcode from rINST 11509 SET_VREG(r0, r2) @ fp[A]<- r0 11510 GOTO_OPCODE(ip) @ jump to next instruction 11511 11512/* continuation for OP_IPUT */ 11513 11514 /* 11515 * Currently: 11516 * r0 holds resolved field 11517 * r9 holds object 11518 */ 11519.LOP_IPUT_finish: 11520 @bl common_squeak0 11521 mov r1, rINST, lsr #8 @ r1<- A+ 11522 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11523 and r1, r1, #15 @ r1<- A 11524 cmp r9, #0 @ check object for null 11525 GET_VREG(r0, r1) @ r0<- fp[A] 11526 beq common_errNullObject @ object was null 11527 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11528 GET_INST_OPCODE(ip) @ extract opcode from rINST 11529 @ no-op @ releasing store 11530 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11531 GOTO_OPCODE(ip) @ jump to next instruction 11532 11533/* continuation for OP_IPUT_WIDE */ 11534 11535 /* 11536 * Currently: 11537 * r0 holds resolved field 11538 * r9 holds object 11539 */ 11540.LOP_IPUT_WIDE_finish: 11541 mov r2, rINST, lsr #8 @ r2<- A+ 11542 cmp r9, #0 @ check object for null 11543 and r2, r2, #15 @ r2<- A 11544 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11545 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 11546 beq common_errNullObject @ object was null 11547 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11548 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 11549 GET_INST_OPCODE(r10) @ extract opcode from rINST 11550 .if 0 11551 add r2, r9, r3 @ r2<- target address 11552 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 11553 .else 11554 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 11555 .endif 11556 GOTO_OPCODE(r10) @ jump to next instruction 11557 11558/* continuation for OP_IPUT_OBJECT */ 11559 11560 /* 11561 * Currently: 11562 * r0 holds resolved field 11563 * r9 holds object 11564 */ 11565.LOP_IPUT_OBJECT_finish: 11566 @bl common_squeak0 11567 mov r1, rINST, lsr #8 @ r1<- A+ 11568 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11569 and r1, r1, #15 @ r1<- A 11570 cmp r9, #0 @ check object for null 11571 GET_VREG(r0, r1) @ r0<- fp[A] 11572 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11573 beq common_errNullObject @ object was null 11574 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11575 GET_INST_OPCODE(ip) @ extract opcode from rINST 11576 @ no-op @ releasing store 11577 str r0, [r9, r3] @ obj.field (32 bits)<- r0 11578 cmp r0, #0 @ stored a null reference? 11579 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 11580 GOTO_OPCODE(ip) @ jump to next instruction 11581 11582/* continuation for OP_IPUT_BOOLEAN */ 11583 11584 /* 11585 * Currently: 11586 * r0 holds resolved field 11587 * r9 holds object 11588 */ 11589.LOP_IPUT_BOOLEAN_finish: 11590 @bl common_squeak1 11591 mov r1, rINST, lsr #8 @ r1<- A+ 11592 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11593 and r1, r1, #15 @ r1<- A 11594 cmp r9, #0 @ check object for null 11595 GET_VREG(r0, r1) @ r0<- fp[A] 11596 beq common_errNullObject @ object was null 11597 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11598 GET_INST_OPCODE(ip) @ extract opcode from rINST 11599 @ no-op @ releasing store 11600 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11601 GOTO_OPCODE(ip) @ jump to next instruction 11602 11603/* continuation for OP_IPUT_BYTE */ 11604 11605 /* 11606 * Currently: 11607 * r0 holds resolved field 11608 * r9 holds object 11609 */ 11610.LOP_IPUT_BYTE_finish: 11611 @bl common_squeak2 11612 mov r1, rINST, lsr #8 @ r1<- A+ 11613 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11614 and r1, r1, #15 @ r1<- A 11615 cmp r9, #0 @ check object for null 11616 GET_VREG(r0, r1) @ r0<- fp[A] 11617 beq common_errNullObject @ object was null 11618 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11619 GET_INST_OPCODE(ip) @ extract opcode from rINST 11620 @ no-op @ releasing store 11621 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11622 GOTO_OPCODE(ip) @ jump to next instruction 11623 11624/* continuation for OP_IPUT_CHAR */ 11625 11626 /* 11627 * Currently: 11628 * r0 holds resolved field 11629 * r9 holds object 11630 */ 11631.LOP_IPUT_CHAR_finish: 11632 @bl common_squeak3 11633 mov r1, rINST, lsr #8 @ r1<- A+ 11634 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11635 and r1, r1, #15 @ r1<- A 11636 cmp r9, #0 @ check object for null 11637 GET_VREG(r0, r1) @ r0<- fp[A] 11638 beq common_errNullObject @ object was null 11639 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11640 GET_INST_OPCODE(ip) @ extract opcode from rINST 11641 @ no-op @ releasing store 11642 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11643 GOTO_OPCODE(ip) @ jump to next instruction 11644 11645/* continuation for OP_IPUT_SHORT */ 11646 11647 /* 11648 * Currently: 11649 * r0 holds resolved field 11650 * r9 holds object 11651 */ 11652.LOP_IPUT_SHORT_finish: 11653 @bl common_squeak4 11654 mov r1, rINST, lsr #8 @ r1<- A+ 11655 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11656 and r1, r1, #15 @ r1<- A 11657 cmp r9, #0 @ check object for null 11658 GET_VREG(r0, r1) @ r0<- fp[A] 11659 beq common_errNullObject @ object was null 11660 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11661 GET_INST_OPCODE(ip) @ extract opcode from rINST 11662 @ no-op @ releasing store 11663 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11664 GOTO_OPCODE(ip) @ jump to next instruction 11665 11666/* continuation for OP_SGET */ 11667 11668 /* 11669 * Continuation if the field has not yet been resolved. 11670 * r1: BBBB field ref 11671 */ 11672.LOP_SGET_resolve: 11673 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11674 EXPORT_PC() @ resolve() could throw, so export now 11675 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11676 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11677 cmp r0, #0 @ success? 11678 bne .LOP_SGET_finish @ yes, finish 11679 b common_exceptionThrown @ no, handle exception 11680 11681/* continuation for OP_SGET_WIDE */ 11682 11683 /* 11684 * Continuation if the field has not yet been resolved. 11685 * r1: BBBB field ref 11686 * 11687 * Returns StaticField pointer in r0. 11688 */ 11689.LOP_SGET_WIDE_resolve: 11690 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11691 EXPORT_PC() @ resolve() could throw, so export now 11692 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11693 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11694 cmp r0, #0 @ success? 11695 bne .LOP_SGET_WIDE_finish @ yes, finish 11696 b common_exceptionThrown @ no, handle exception 11697 11698/* continuation for OP_SGET_OBJECT */ 11699 11700 /* 11701 * Continuation if the field has not yet been resolved. 11702 * r1: BBBB field ref 11703 */ 11704.LOP_SGET_OBJECT_resolve: 11705 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11706 EXPORT_PC() @ resolve() could throw, so export now 11707 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11708 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11709 cmp r0, #0 @ success? 11710 bne .LOP_SGET_OBJECT_finish @ yes, finish 11711 b common_exceptionThrown @ no, handle exception 11712 11713/* continuation for OP_SGET_BOOLEAN */ 11714 11715 /* 11716 * Continuation if the field has not yet been resolved. 11717 * r1: BBBB field ref 11718 */ 11719.LOP_SGET_BOOLEAN_resolve: 11720 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11721 EXPORT_PC() @ resolve() could throw, so export now 11722 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11723 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11724 cmp r0, #0 @ success? 11725 bne .LOP_SGET_BOOLEAN_finish @ yes, finish 11726 b common_exceptionThrown @ no, handle exception 11727 11728/* continuation for OP_SGET_BYTE */ 11729 11730 /* 11731 * Continuation if the field has not yet been resolved. 11732 * r1: BBBB field ref 11733 */ 11734.LOP_SGET_BYTE_resolve: 11735 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11736 EXPORT_PC() @ resolve() could throw, so export now 11737 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11738 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11739 cmp r0, #0 @ success? 11740 bne .LOP_SGET_BYTE_finish @ yes, finish 11741 b common_exceptionThrown @ no, handle exception 11742 11743/* continuation for OP_SGET_CHAR */ 11744 11745 /* 11746 * Continuation if the field has not yet been resolved. 11747 * r1: BBBB field ref 11748 */ 11749.LOP_SGET_CHAR_resolve: 11750 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11751 EXPORT_PC() @ resolve() could throw, so export now 11752 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11753 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11754 cmp r0, #0 @ success? 11755 bne .LOP_SGET_CHAR_finish @ yes, finish 11756 b common_exceptionThrown @ no, handle exception 11757 11758/* continuation for OP_SGET_SHORT */ 11759 11760 /* 11761 * Continuation if the field has not yet been resolved. 11762 * r1: BBBB field ref 11763 */ 11764.LOP_SGET_SHORT_resolve: 11765 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11766 EXPORT_PC() @ resolve() could throw, so export now 11767 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11768 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11769 cmp r0, #0 @ success? 11770 bne .LOP_SGET_SHORT_finish @ yes, finish 11771 b common_exceptionThrown @ no, handle exception 11772 11773/* continuation for OP_SPUT */ 11774 11775 /* 11776 * Continuation if the field has not yet been resolved. 11777 * r1: BBBB field ref 11778 */ 11779.LOP_SPUT_resolve: 11780 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11781 EXPORT_PC() @ resolve() could throw, so export now 11782 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11783 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11784 cmp r0, #0 @ success? 11785 bne .LOP_SPUT_finish @ yes, finish 11786 b common_exceptionThrown @ no, handle exception 11787 11788/* continuation for OP_SPUT_WIDE */ 11789 11790 /* 11791 * Continuation if the field has not yet been resolved. 11792 * r1: BBBB field ref 11793 * r9: &fp[AA] 11794 * 11795 * Returns StaticField pointer in r2. 11796 */ 11797.LOP_SPUT_WIDE_resolve: 11798 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11799 EXPORT_PC() @ resolve() could throw, so export now 11800 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11801 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11802 cmp r0, #0 @ success? 11803 mov r2, r0 @ copy to r2 11804 bne .LOP_SPUT_WIDE_finish @ yes, finish 11805 b common_exceptionThrown @ no, handle exception 11806 11807/* continuation for OP_SPUT_OBJECT */ 11808.LOP_SPUT_OBJECT_finish: @ field ptr in r0 11809 mov r2, rINST, lsr #8 @ r2<- AA 11810 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11811 GET_VREG(r1, r2) @ r1<- fp[AA] 11812 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11813 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 11814 GET_INST_OPCODE(ip) @ extract opcode from rINST 11815 @ no-op @ releasing store 11816 str r1, [r0, #offStaticField_value] @ field<- vAA 11817 cmp r1, #0 @ stored a null object? 11818 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 11819 GOTO_OPCODE(ip) @ jump to next instruction 11820 11821/* continuation for OP_SPUT_BOOLEAN */ 11822 11823 /* 11824 * Continuation if the field has not yet been resolved. 11825 * r1: BBBB field ref 11826 */ 11827.LOP_SPUT_BOOLEAN_resolve: 11828 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11829 EXPORT_PC() @ resolve() could throw, so export now 11830 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11831 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11832 cmp r0, #0 @ success? 11833 bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 11834 b common_exceptionThrown @ no, handle exception 11835 11836/* continuation for OP_SPUT_BYTE */ 11837 11838 /* 11839 * Continuation if the field has not yet been resolved. 11840 * r1: BBBB field ref 11841 */ 11842.LOP_SPUT_BYTE_resolve: 11843 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11844 EXPORT_PC() @ resolve() could throw, so export now 11845 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11846 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11847 cmp r0, #0 @ success? 11848 bne .LOP_SPUT_BYTE_finish @ yes, finish 11849 b common_exceptionThrown @ no, handle exception 11850 11851/* continuation for OP_SPUT_CHAR */ 11852 11853 /* 11854 * Continuation if the field has not yet been resolved. 11855 * r1: BBBB field ref 11856 */ 11857.LOP_SPUT_CHAR_resolve: 11858 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11859 EXPORT_PC() @ resolve() could throw, so export now 11860 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11861 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11862 cmp r0, #0 @ success? 11863 bne .LOP_SPUT_CHAR_finish @ yes, finish 11864 b common_exceptionThrown @ no, handle exception 11865 11866/* continuation for OP_SPUT_SHORT */ 11867 11868 /* 11869 * Continuation if the field has not yet been resolved. 11870 * r1: BBBB field ref 11871 */ 11872.LOP_SPUT_SHORT_resolve: 11873 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11874 EXPORT_PC() @ resolve() could throw, so export now 11875 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11876 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11877 cmp r0, #0 @ success? 11878 bne .LOP_SPUT_SHORT_finish @ yes, finish 11879 b common_exceptionThrown @ no, handle exception 11880 11881/* continuation for OP_INVOKE_VIRTUAL */ 11882 11883 /* 11884 * At this point: 11885 * r0 = resolved base method 11886 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11887 */ 11888.LOP_INVOKE_VIRTUAL_continue: 11889 GET_VREG(r1, r10) @ r1<- "this" ptr 11890 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11891 cmp r1, #0 @ is "this" null? 11892 beq common_errNullObject @ null "this", throw exception 11893 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11894 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11895 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11896 bl common_invokeMethodNoRange @ continue on 11897 11898/* continuation for OP_INVOKE_SUPER */ 11899 11900 /* 11901 * At this point: 11902 * r0 = resolved base method 11903 * r9 = method->clazz 11904 */ 11905.LOP_INVOKE_SUPER_continue: 11906 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11907 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11908 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11909 EXPORT_PC() @ must export for invoke 11910 cmp r2, r3 @ compare (methodIndex, vtableCount) 11911 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 11912 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11913 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11914 bl common_invokeMethodNoRange @ continue on 11915 11916.LOP_INVOKE_SUPER_resolve: 11917 mov r0, r9 @ r0<- method->clazz 11918 mov r2, #METHOD_VIRTUAL @ resolver method type 11919 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11920 cmp r0, #0 @ got null? 11921 bne .LOP_INVOKE_SUPER_continue @ no, continue 11922 b common_exceptionThrown @ yes, handle exception 11923 11924 /* 11925 * Throw a NoSuchMethodError with the method name as the message. 11926 * r0 = resolved base method 11927 */ 11928.LOP_INVOKE_SUPER_nsm: 11929 ldr r1, [r0, #offMethod_name] @ r1<- method name 11930 b common_errNoSuchMethod 11931 11932/* continuation for OP_INVOKE_DIRECT */ 11933 11934 /* 11935 * On entry: 11936 * r1 = reference (BBBB or CCCC) 11937 * r10 = "this" register 11938 */ 11939.LOP_INVOKE_DIRECT_resolve: 11940 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11941 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11942 mov r2, #METHOD_DIRECT @ resolver method type 11943 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11944 cmp r0, #0 @ got null? 11945 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 11946 bne .LOP_INVOKE_DIRECT_finish @ no, continue 11947 b common_exceptionThrown @ yes, handle exception 11948 11949/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 11950 11951 /* 11952 * At this point: 11953 * r0 = resolved base method 11954 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11955 */ 11956.LOP_INVOKE_VIRTUAL_RANGE_continue: 11957 GET_VREG(r1, r10) @ r1<- "this" ptr 11958 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11959 cmp r1, #0 @ is "this" null? 11960 beq common_errNullObject @ null "this", throw exception 11961 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11962 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11963 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11964 bl common_invokeMethodRange @ continue on 11965 11966/* continuation for OP_INVOKE_SUPER_RANGE */ 11967 11968 /* 11969 * At this point: 11970 * r0 = resolved base method 11971 * r9 = method->clazz 11972 */ 11973.LOP_INVOKE_SUPER_RANGE_continue: 11974 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11975 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11976 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11977 EXPORT_PC() @ must export for invoke 11978 cmp r2, r3 @ compare (methodIndex, vtableCount) 11979 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 11980 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11981 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11982 bl common_invokeMethodRange @ continue on 11983 11984.LOP_INVOKE_SUPER_RANGE_resolve: 11985 mov r0, r9 @ r0<- method->clazz 11986 mov r2, #METHOD_VIRTUAL @ resolver method type 11987 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11988 cmp r0, #0 @ got null? 11989 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 11990 b common_exceptionThrown @ yes, handle exception 11991 11992 /* 11993 * Throw a NoSuchMethodError with the method name as the message. 11994 * r0 = resolved base method 11995 */ 11996.LOP_INVOKE_SUPER_RANGE_nsm: 11997 ldr r1, [r0, #offMethod_name] @ r1<- method name 11998 b common_errNoSuchMethod 11999 12000/* continuation for OP_INVOKE_DIRECT_RANGE */ 12001 12002 /* 12003 * On entry: 12004 * r1 = reference (BBBB or CCCC) 12005 * r10 = "this" register 12006 */ 12007.LOP_INVOKE_DIRECT_RANGE_resolve: 12008 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12009 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12010 mov r2, #METHOD_DIRECT @ resolver method type 12011 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12012 cmp r0, #0 @ got null? 12013 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 12014 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 12015 b common_exceptionThrown @ yes, handle exception 12016 12017/* continuation for OP_FLOAT_TO_LONG */ 12018/* 12019 * Convert the float in r0 to a long in r0/r1. 12020 * 12021 * We have to clip values to long min/max per the specification. The 12022 * expected common case is a "reasonable" value that converts directly 12023 * to modest integer. The EABI convert function isn't doing this for us. 12024 */ 12025f2l_doconv: 12026 stmfd sp!, {r4, lr} 12027 mov r1, #0x5f000000 @ (float)maxlong 12028 mov r4, r0 12029 bl __aeabi_fcmpge @ is arg >= maxlong? 12030 cmp r0, #0 @ nonzero == yes 12031 mvnne r0, #0 @ return maxlong (7fffffff) 12032 mvnne r1, #0x80000000 12033 ldmnefd sp!, {r4, pc} 12034 12035 mov r0, r4 @ recover arg 12036 mov r1, #0xdf000000 @ (float)minlong 12037 bl __aeabi_fcmple @ is arg <= minlong? 12038 cmp r0, #0 @ nonzero == yes 12039 movne r0, #0 @ return minlong (80000000) 12040 movne r1, #0x80000000 12041 ldmnefd sp!, {r4, pc} 12042 12043 mov r0, r4 @ recover arg 12044 mov r1, r4 12045 bl __aeabi_fcmpeq @ is arg == self? 12046 cmp r0, #0 @ zero == no 12047 moveq r1, #0 @ return zero for NaN 12048 ldmeqfd sp!, {r4, pc} 12049 12050 mov r0, r4 @ recover arg 12051 bl __aeabi_f2lz @ convert float to long 12052 ldmfd sp!, {r4, pc} 12053 12054/* continuation for OP_DOUBLE_TO_LONG */ 12055/* 12056 * Convert the double in r0/r1 to a long in r0/r1. 12057 * 12058 * We have to clip values to long min/max per the specification. The 12059 * expected common case is a "reasonable" value that converts directly 12060 * to modest integer. The EABI convert function isn't doing this for us. 12061 */ 12062d2l_doconv: 12063 stmfd sp!, {r4, r5, lr} @ save regs 12064 mov r3, #0x43000000 @ maxlong, as a double (high word) 12065 add r3, #0x00e00000 @ 0x43e00000 12066 mov r2, #0 @ maxlong, as a double (low word) 12067 sub sp, sp, #4 @ align for EABI 12068 mov r4, r0 @ save a copy of r0 12069 mov r5, r1 @ and r1 12070 bl __aeabi_dcmpge @ is arg >= maxlong? 12071 cmp r0, #0 @ nonzero == yes 12072 mvnne r0, #0 @ return maxlong (7fffffffffffffff) 12073 mvnne r1, #0x80000000 12074 bne 1f 12075 12076 mov r0, r4 @ recover arg 12077 mov r1, r5 12078 mov r3, #0xc3000000 @ minlong, as a double (high word) 12079 add r3, #0x00e00000 @ 0xc3e00000 12080 mov r2, #0 @ minlong, as a double (low word) 12081 bl __aeabi_dcmple @ is arg <= minlong? 12082 cmp r0, #0 @ nonzero == yes 12083 movne r0, #0 @ return minlong (8000000000000000) 12084 movne r1, #0x80000000 12085 bne 1f 12086 12087 mov r0, r4 @ recover arg 12088 mov r1, r5 12089 mov r2, r4 @ compare against self 12090 mov r3, r5 12091 bl __aeabi_dcmpeq @ is arg == self? 12092 cmp r0, #0 @ zero == no 12093 moveq r1, #0 @ return zero for NaN 12094 beq 1f 12095 12096 mov r0, r4 @ recover arg 12097 mov r1, r5 12098 bl __aeabi_d2lz @ convert double to long 12099 121001: 12101 add sp, sp, #4 12102 ldmfd sp!, {r4, r5, pc} 12103 12104/* continuation for OP_MUL_LONG */ 12105 12106.LOP_MUL_LONG_finish: 12107 GET_INST_OPCODE(ip) @ extract opcode from rINST 12108 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 12109 GOTO_OPCODE(ip) @ jump to next instruction 12110 12111/* continuation for OP_SHL_LONG */ 12112 12113.LOP_SHL_LONG_finish: 12114 mov r0, r0, asl r2 @ r0<- r0 << r2 12115 GET_INST_OPCODE(ip) @ extract opcode from rINST 12116 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12117 GOTO_OPCODE(ip) @ jump to next instruction 12118 12119/* continuation for OP_SHR_LONG */ 12120 12121.LOP_SHR_LONG_finish: 12122 mov r1, r1, asr r2 @ r1<- r1 >> r2 12123 GET_INST_OPCODE(ip) @ extract opcode from rINST 12124 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12125 GOTO_OPCODE(ip) @ jump to next instruction 12126 12127/* continuation for OP_USHR_LONG */ 12128 12129.LOP_USHR_LONG_finish: 12130 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 12131 GET_INST_OPCODE(ip) @ extract opcode from rINST 12132 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12133 GOTO_OPCODE(ip) @ jump to next instruction 12134 12135/* continuation for OP_SHL_LONG_2ADDR */ 12136 12137.LOP_SHL_LONG_2ADDR_finish: 12138 GET_INST_OPCODE(ip) @ extract opcode from rINST 12139 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12140 GOTO_OPCODE(ip) @ jump to next instruction 12141 12142/* continuation for OP_SHR_LONG_2ADDR */ 12143 12144.LOP_SHR_LONG_2ADDR_finish: 12145 GET_INST_OPCODE(ip) @ extract opcode from rINST 12146 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12147 GOTO_OPCODE(ip) @ jump to next instruction 12148 12149/* continuation for OP_USHR_LONG_2ADDR */ 12150 12151.LOP_USHR_LONG_2ADDR_finish: 12152 GET_INST_OPCODE(ip) @ extract opcode from rINST 12153 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12154 GOTO_OPCODE(ip) @ jump to next instruction 12155 12156/* continuation for OP_IGET_VOLATILE */ 12157 12158 /* 12159 * Currently: 12160 * r0 holds resolved field 12161 * r9 holds object 12162 */ 12163.LOP_IGET_VOLATILE_finish: 12164 @bl common_squeak0 12165 cmp r9, #0 @ check object for null 12166 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12167 beq common_errNullObject @ object was null 12168 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12169 SMP_DMB @ acquiring load 12170 mov r2, rINST, lsr #8 @ r2<- A+ 12171 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12172 and r2, r2, #15 @ r2<- A 12173 GET_INST_OPCODE(ip) @ extract opcode from rINST 12174 SET_VREG(r0, r2) @ fp[A]<- r0 12175 GOTO_OPCODE(ip) @ jump to next instruction 12176 12177/* continuation for OP_IPUT_VOLATILE */ 12178 12179 /* 12180 * Currently: 12181 * r0 holds resolved field 12182 * r9 holds object 12183 */ 12184.LOP_IPUT_VOLATILE_finish: 12185 @bl common_squeak0 12186 mov r1, rINST, lsr #8 @ r1<- A+ 12187 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12188 and r1, r1, #15 @ r1<- A 12189 cmp r9, #0 @ check object for null 12190 GET_VREG(r0, r1) @ r0<- fp[A] 12191 beq common_errNullObject @ object was null 12192 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12193 GET_INST_OPCODE(ip) @ extract opcode from rINST 12194 SMP_DMB @ releasing store 12195 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12196 GOTO_OPCODE(ip) @ jump to next instruction 12197 12198/* continuation for OP_SGET_VOLATILE */ 12199 12200 /* 12201 * Continuation if the field has not yet been resolved. 12202 * r1: BBBB field ref 12203 */ 12204.LOP_SGET_VOLATILE_resolve: 12205 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12206 EXPORT_PC() @ resolve() could throw, so export now 12207 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12208 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12209 cmp r0, #0 @ success? 12210 bne .LOP_SGET_VOLATILE_finish @ yes, finish 12211 b common_exceptionThrown @ no, handle exception 12212 12213/* continuation for OP_SPUT_VOLATILE */ 12214 12215 /* 12216 * Continuation if the field has not yet been resolved. 12217 * r1: BBBB field ref 12218 */ 12219.LOP_SPUT_VOLATILE_resolve: 12220 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12221 EXPORT_PC() @ resolve() could throw, so export now 12222 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12223 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12224 cmp r0, #0 @ success? 12225 bne .LOP_SPUT_VOLATILE_finish @ yes, finish 12226 b common_exceptionThrown @ no, handle exception 12227 12228/* continuation for OP_IGET_OBJECT_VOLATILE */ 12229 12230 /* 12231 * Currently: 12232 * r0 holds resolved field 12233 * r9 holds object 12234 */ 12235.LOP_IGET_OBJECT_VOLATILE_finish: 12236 @bl common_squeak0 12237 cmp r9, #0 @ check object for null 12238 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12239 beq common_errNullObject @ object was null 12240 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12241 SMP_DMB @ acquiring load 12242 mov r2, rINST, lsr #8 @ r2<- A+ 12243 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12244 and r2, r2, #15 @ r2<- A 12245 GET_INST_OPCODE(ip) @ extract opcode from rINST 12246 SET_VREG(r0, r2) @ fp[A]<- r0 12247 GOTO_OPCODE(ip) @ jump to next instruction 12248 12249/* continuation for OP_IGET_WIDE_VOLATILE */ 12250 12251 /* 12252 * Currently: 12253 * r0 holds resolved field 12254 * r9 holds object 12255 */ 12256.LOP_IGET_WIDE_VOLATILE_finish: 12257 cmp r9, #0 @ check object for null 12258 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12259 beq common_errNullObject @ object was null 12260 .if 1 12261 add r0, r9, r3 @ r0<- address of field 12262 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 12263 .else 12264 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12265 .endif 12266 mov r2, rINST, lsr #8 @ r2<- A+ 12267 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12268 and r2, r2, #15 @ r2<- A 12269 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 12270 GET_INST_OPCODE(ip) @ extract opcode from rINST 12271 stmia r3, {r0-r1} @ fp[A]<- r0/r1 12272 GOTO_OPCODE(ip) @ jump to next instruction 12273 12274/* continuation for OP_IPUT_WIDE_VOLATILE */ 12275 12276 /* 12277 * Currently: 12278 * r0 holds resolved field 12279 * r9 holds object 12280 */ 12281.LOP_IPUT_WIDE_VOLATILE_finish: 12282 mov r2, rINST, lsr #8 @ r2<- A+ 12283 cmp r9, #0 @ check object for null 12284 and r2, r2, #15 @ r2<- A 12285 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12286 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 12287 beq common_errNullObject @ object was null 12288 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12289 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 12290 GET_INST_OPCODE(r10) @ extract opcode from rINST 12291 .if 1 12292 add r2, r9, r3 @ r2<- target address 12293 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 12294 .else 12295 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12296 .endif 12297 GOTO_OPCODE(r10) @ jump to next instruction 12298 12299/* continuation for OP_SGET_WIDE_VOLATILE */ 12300 12301 /* 12302 * Continuation if the field has not yet been resolved. 12303 * r1: BBBB field ref 12304 * 12305 * Returns StaticField pointer in r0. 12306 */ 12307.LOP_SGET_WIDE_VOLATILE_resolve: 12308 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12309 EXPORT_PC() @ resolve() could throw, so export now 12310 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12311 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12312 cmp r0, #0 @ success? 12313 bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 12314 b common_exceptionThrown @ no, handle exception 12315 12316/* continuation for OP_SPUT_WIDE_VOLATILE */ 12317 12318 /* 12319 * Continuation if the field has not yet been resolved. 12320 * r1: BBBB field ref 12321 * r9: &fp[AA] 12322 * 12323 * Returns StaticField pointer in r2. 12324 */ 12325.LOP_SPUT_WIDE_VOLATILE_resolve: 12326 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12327 EXPORT_PC() @ resolve() could throw, so export now 12328 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12329 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12330 cmp r0, #0 @ success? 12331 mov r2, r0 @ copy to r2 12332 bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 12333 b common_exceptionThrown @ no, handle exception 12334 12335/* continuation for OP_EXECUTE_INLINE */ 12336 12337 /* 12338 * Extract args, call function. 12339 * r0 = #of args (0-4) 12340 * r10 = call index 12341 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12342 * 12343 * Other ideas: 12344 * - Use a jump table from the main piece to jump directly into the 12345 * AND/LDR pairs. Costs a data load, saves a branch. 12346 * - Have five separate pieces that do the loading, so we can work the 12347 * interleave a little better. Increases code size. 12348 */ 12349.LOP_EXECUTE_INLINE_continue: 12350 rsb r0, r0, #4 @ r0<- 4-r0 12351 FETCH(r9, 2) @ r9<- FEDC 12352 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12353 bl common_abort @ (skipped due to ARM prefetch) 123544: and ip, r9, #0xf000 @ isolate F 12355 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 123563: and ip, r9, #0x0f00 @ isolate E 12357 ldr r2, [rFP, ip, lsr #6] @ r2<- vE 123582: and ip, r9, #0x00f0 @ isolate D 12359 ldr r1, [rFP, ip, lsr #2] @ r1<- vD 123601: and ip, r9, #0x000f @ isolate C 12361 ldr r0, [rFP, ip, lsl #2] @ r0<- vC 123620: 12363 ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 12364 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12365 @ (not reached) 12366 12367.LOP_EXECUTE_INLINE_table: 12368 .word gDvmInlineOpsTable 12369 12370/* continuation for OP_EXECUTE_INLINE_RANGE */ 12371 12372 /* 12373 * Extract args, call function. 12374 * r0 = #of args (0-4) 12375 * r10 = call index 12376 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12377 */ 12378.LOP_EXECUTE_INLINE_RANGE_continue: 12379 rsb r0, r0, #4 @ r0<- 4-r0 12380 FETCH(r9, 2) @ r9<- CCCC 12381 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12382 bl common_abort @ (skipped due to ARM prefetch) 123834: add ip, r9, #3 @ base+3 12384 GET_VREG(r3, ip) @ r3<- vBase[3] 123853: add ip, r9, #2 @ base+2 12386 GET_VREG(r2, ip) @ r2<- vBase[2] 123872: add ip, r9, #1 @ base+1 12388 GET_VREG(r1, ip) @ r1<- vBase[1] 123891: add ip, r9, #0 @ (nop) 12390 GET_VREG(r0, ip) @ r0<- vBase[0] 123910: 12392 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 12393 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12394 @ (not reached) 12395 12396.LOP_EXECUTE_INLINE_RANGE_table: 12397 .word gDvmInlineOpsTable 12398 12399/* continuation for OP_IPUT_OBJECT_VOLATILE */ 12400 12401 /* 12402 * Currently: 12403 * r0 holds resolved field 12404 * r9 holds object 12405 */ 12406.LOP_IPUT_OBJECT_VOLATILE_finish: 12407 @bl common_squeak0 12408 mov r1, rINST, lsr #8 @ r1<- A+ 12409 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12410 and r1, r1, #15 @ r1<- A 12411 cmp r9, #0 @ check object for null 12412 GET_VREG(r0, r1) @ r0<- fp[A] 12413 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12414 beq common_errNullObject @ object was null 12415 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12416 GET_INST_OPCODE(ip) @ extract opcode from rINST 12417 SMP_DMB @ releasing store 12418 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12419 cmp r0, #0 @ stored a null reference? 12420 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12421 GOTO_OPCODE(ip) @ jump to next instruction 12422 12423/* continuation for OP_SGET_OBJECT_VOLATILE */ 12424 12425 /* 12426 * Continuation if the field has not yet been resolved. 12427 * r1: BBBB field ref 12428 */ 12429.LOP_SGET_OBJECT_VOLATILE_resolve: 12430 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12431 EXPORT_PC() @ resolve() could throw, so export now 12432 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12433 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12434 cmp r0, #0 @ success? 12435 bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish 12436 b common_exceptionThrown @ no, handle exception 12437 12438/* continuation for OP_SPUT_OBJECT_VOLATILE */ 12439.LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 12440 mov r2, rINST, lsr #8 @ r2<- AA 12441 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12442 GET_VREG(r1, r2) @ r1<- fp[AA] 12443 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12444 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 12445 GET_INST_OPCODE(ip) @ extract opcode from rINST 12446 SMP_DMB @ releasing store 12447 str r1, [r0, #offStaticField_value] @ field<- vAA 12448 cmp r1, #0 @ stored a null object? 12449 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12450 GOTO_OPCODE(ip) @ jump to next instruction 12451 12452/* continuation for OP_CONST_CLASS_JUMBO */ 12453 12454 /* 12455 * Continuation if the Class has not yet been resolved. 12456 * r1: AAAAAAAA (Class ref) 12457 * r9: target register 12458 */ 12459.LOP_CONST_CLASS_JUMBO_resolve: 12460 EXPORT_PC() 12461 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12462 mov r2, #1 @ r2<- true 12463 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12464 bl dvmResolveClass @ r0<- Class reference 12465 cmp r0, #0 @ failed? 12466 beq common_exceptionThrown @ yup, handle the exception 12467 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12468 GET_INST_OPCODE(ip) @ extract opcode from rINST 12469 SET_VREG(r0, r9) @ vBBBB<- r0 12470 GOTO_OPCODE(ip) @ jump to next instruction 12471 12472/* continuation for OP_CHECK_CAST_JUMBO */ 12473 12474 /* 12475 * Trivial test failed, need to perform full check. This is common. 12476 * r0 holds obj->clazz 12477 * r1 holds desired class resolved from AAAAAAAA 12478 * r9 holds object 12479 */ 12480.LOP_CHECK_CAST_JUMBO_fullcheck: 12481 mov r10, r1 @ avoid ClassObject getting clobbered 12482 bl dvmInstanceofNonTrivial @ r0<- boolean result 12483 cmp r0, #0 @ failed? 12484 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success 12485 12486 @ A cast has failed. We need to throw a ClassCastException. 12487 EXPORT_PC() @ about to throw 12488 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 12489 mov r1, r10 @ r1<- desired class 12490 bl dvmThrowClassCastException 12491 b common_exceptionThrown 12492 12493 /* 12494 * Advance PC and get the next opcode. 12495 */ 12496.LOP_CHECK_CAST_JUMBO_okay: 12497 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12498 GET_INST_OPCODE(ip) @ extract opcode from rINST 12499 GOTO_OPCODE(ip) @ jump to next instruction 12500 12501 /* 12502 * Resolution required. This is the least-likely path. 12503 * 12504 * r2 holds AAAAAAAA 12505 * r9 holds object 12506 */ 12507.LOP_CHECK_CAST_JUMBO_resolve: 12508 EXPORT_PC() @ resolve() could throw 12509 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12510 mov r1, r2 @ r1<- AAAAAAAA 12511 mov r2, #0 @ r2<- false 12512 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12513 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12514 cmp r0, #0 @ got null? 12515 beq common_exceptionThrown @ yes, handle exception 12516 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12517 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 12518 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off 12519 12520/* continuation for OP_INSTANCE_OF_JUMBO */ 12521 12522 /* 12523 * Class resolved, determine type of check necessary. This is common. 12524 * r0 holds obj->clazz 12525 * r1 holds class resolved from AAAAAAAA 12526 * r9 holds BBBB 12527 */ 12528.LOP_INSTANCE_OF_JUMBO_resolved: 12529 cmp r0, r1 @ same class (trivial success)? 12530 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish 12531 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck 12532 12533 /* 12534 * Trivial test failed, need to perform full check. This is common. 12535 * r0 holds obj->clazz 12536 * r1 holds class resolved from AAAAAAAA 12537 * r9 holds BBBB 12538 */ 12539.LOP_INSTANCE_OF_JUMBO_fullcheck: 12540 bl dvmInstanceofNonTrivial @ r0<- boolean result 12541 @ fall through to OP_INSTANCE_OF_JUMBO_store 12542 12543 /* 12544 * r0 holds boolean result 12545 * r9 holds BBBB 12546 */ 12547.LOP_INSTANCE_OF_JUMBO_store: 12548 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12549 SET_VREG(r0, r9) @ vBBBB<- r0 12550 GET_INST_OPCODE(ip) @ extract opcode from rINST 12551 GOTO_OPCODE(ip) @ jump to next instruction 12552 12553 /* 12554 * Trivial test succeeded, save and bail. 12555 * r9 holds BBBB 12556 */ 12557.LOP_INSTANCE_OF_JUMBO_trivial: 12558 mov r0, #1 @ indicate success 12559 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper 12560 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12561 SET_VREG(r0, r9) @ vBBBB<- r0 12562 GET_INST_OPCODE(ip) @ extract opcode from rINST 12563 GOTO_OPCODE(ip) @ jump to next instruction 12564 12565 /* 12566 * Resolution required. This is the least-likely path. 12567 * 12568 * r3 holds AAAAAAAA 12569 * r9 holds BBBB 12570 */ 12571 12572.LOP_INSTANCE_OF_JUMBO_resolve: 12573 EXPORT_PC() @ resolve() could throw 12574 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12575 mov r1, r3 @ r1<- AAAAAAAA 12576 mov r2, #1 @ r2<- true 12577 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12578 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12579 cmp r0, #0 @ got null? 12580 beq common_exceptionThrown @ yes, handle exception 12581 FETCH(r3, 4) @ r3<- vCCCC 12582 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12583 GET_VREG(r0, r3) @ r0<- vCCCC (object) 12584 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 12585 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off 12586 12587/* continuation for OP_NEW_INSTANCE_JUMBO */ 12588 12589 .balign 32 @ minimize cache lines 12590.LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object 12591 FETCH(r3, 3) @ r3<- BBBB 12592 cmp r0, #0 @ failed? 12593 beq common_exceptionThrown @ yes, handle the exception 12594 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12595 GET_INST_OPCODE(ip) @ extract opcode from rINST 12596 SET_VREG(r0, r3) @ vBBBB<- r0 12597 GOTO_OPCODE(ip) @ jump to next instruction 12598 12599 /* 12600 * Class initialization required. 12601 * 12602 * r0 holds class object 12603 */ 12604.LOP_NEW_INSTANCE_JUMBO_needinit: 12605 mov r9, r0 @ save r0 12606 bl dvmInitClass @ initialize class 12607 cmp r0, #0 @ check boolean result 12608 mov r0, r9 @ restore r0 12609 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue 12610 b common_exceptionThrown @ failed, deal with init exception 12611 12612 /* 12613 * Resolution required. This is the least-likely path. 12614 * 12615 * r1 holds AAAAAAAA 12616 */ 12617.LOP_NEW_INSTANCE_JUMBO_resolve: 12618 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12619 mov r2, #0 @ r2<- false 12620 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12621 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12622 cmp r0, #0 @ got null? 12623 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue 12624 b common_exceptionThrown @ yes, handle exception 12625 12626/* continuation for OP_NEW_ARRAY_JUMBO */ 12627 12628 12629 /* 12630 * Resolve class. (This is an uncommon case.) 12631 * 12632 * r1 holds array length 12633 * r2 holds class ref AAAAAAAA 12634 */ 12635.LOP_NEW_ARRAY_JUMBO_resolve: 12636 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12637 mov r9, r1 @ r9<- length (save) 12638 mov r1, r2 @ r1<- AAAAAAAA 12639 mov r2, #0 @ r2<- false 12640 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12641 bl dvmResolveClass @ r0<- call(clazz, ref) 12642 cmp r0, #0 @ got null? 12643 mov r1, r9 @ r1<- length (restore) 12644 beq common_exceptionThrown @ yes, handle exception 12645 @ fall through to OP_NEW_ARRAY_JUMBO_finish 12646 12647 /* 12648 * Finish allocation. 12649 * 12650 * r0 holds class 12651 * r1 holds array length 12652 */ 12653.LOP_NEW_ARRAY_JUMBO_finish: 12654 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 12655 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 12656 cmp r0, #0 @ failed? 12657 FETCH(r2, 3) @ r2<- vBBBB 12658 beq common_exceptionThrown @ yes, handle the exception 12659 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12660 GET_INST_OPCODE(ip) @ extract opcode from rINST 12661 SET_VREG(r0, r2) @ vBBBB<- r0 12662 GOTO_OPCODE(ip) @ jump to next instruction 12663 12664/* continuation for OP_FILLED_NEW_ARRAY_JUMBO */ 12665 12666 /* 12667 * On entry: 12668 * r0 holds array class 12669 */ 12670.LOP_FILLED_NEW_ARRAY_JUMBO_continue: 12671 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 12672 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 12673 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 12674 FETCH(r1, 3) @ r1<- BBBB (length) 12675 cmp rINST, #'I' @ array of ints? 12676 cmpne rINST, #'L' @ array of objects? 12677 cmpne rINST, #'[' @ array of arrays? 12678 mov r9, r1 @ save length in r9 12679 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet 12680 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 12681 cmp r0, #0 @ null return? 12682 beq common_exceptionThrown @ alloc failed, handle exception 12683 12684 FETCH(r1, 4) @ r1<- CCCC 12685 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 12686 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 12687 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 12688 subs r9, r9, #1 @ length--, check for neg 12689 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST 12690 bmi 2f @ was zero, bail 12691 12692 @ copy values from registers into the array 12693 @ r0=array, r1=CCCC, r9=BBBB (length) 12694 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 126951: ldr r3, [r2], #4 @ r3<- *r2++ 12696 subs r9, r9, #1 @ count-- 12697 str r3, [r0], #4 @ *contents++ = vX 12698 bpl 1b 12699 127002: ldr r0, [rSELF, #offThread_retval] @ r0<- object 12701 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 12702 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12703 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 12704 cmp r1, #'I' @ Is int array? 12705 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 12706 GOTO_OPCODE(ip) @ execute it 12707 12708 /* 12709 * Throw an exception indicating that we have not implemented this 12710 * mode of filled-new-array. 12711 */ 12712.LOP_FILLED_NEW_ARRAY_JUMBO_notimpl: 12713 ldr r0, .L_strFilledNewArrayNotImpl 12714 bl dvmThrowInternalError 12715 b common_exceptionThrown 12716 12717/* continuation for OP_IGET_JUMBO */ 12718 12719 /* 12720 * Currently: 12721 * r0 holds resolved field 12722 * r9 holds object 12723 */ 12724.LOP_IGET_JUMBO_resolved: 12725 cmp r0, #0 @ resolution unsuccessful? 12726 beq common_exceptionThrown @ yes, throw exception 12727 @ fall through to OP_IGET_JUMBO_finish 12728 12729 /* 12730 * Currently: 12731 * r0 holds resolved field 12732 * r9 holds object 12733 */ 12734.LOP_IGET_JUMBO_finish: 12735 @bl common_squeak0 12736 cmp r9, #0 @ check object for null 12737 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12738 beq common_errNullObject @ object was null 12739 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12740 @ no-op @ acquiring load 12741 FETCH(r2, 3) @ r2<- BBBB 12742 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12743 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12744 GET_INST_OPCODE(ip) @ extract opcode from rINST 12745 GOTO_OPCODE(ip) @ jump to next instruction 12746 12747/* continuation for OP_IGET_WIDE_JUMBO */ 12748 12749 /* 12750 * Currently: 12751 * r0 holds resolved field 12752 * r9 holds object 12753 */ 12754.LOP_IGET_WIDE_JUMBO_resolved: 12755 cmp r0, #0 @ resolution unsuccessful? 12756 beq common_exceptionThrown @ yes, throw exception 12757 @ fall through to OP_IGET_WIDE_JUMBO_finish 12758 12759 /* 12760 * Currently: 12761 * r0 holds resolved field 12762 * r9 holds object 12763 */ 12764.LOP_IGET_WIDE_JUMBO_finish: 12765 cmp r9, #0 @ check object for null 12766 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12767 beq common_errNullObject @ object was null 12768 .if 0 12769 add r0, r9, r3 @ r0<- address of field 12770 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 12771 .else 12772 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12773 .endif 12774 FETCH(r2, 3) @ r2<- BBBB 12775 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12776 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12777 GET_INST_OPCODE(ip) @ extract opcode from rINST 12778 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 12779 GOTO_OPCODE(ip) @ jump to next instruction 12780 12781/* continuation for OP_IGET_OBJECT_JUMBO */ 12782 12783 /* 12784 * Currently: 12785 * r0 holds resolved field 12786 * r9 holds object 12787 */ 12788.LOP_IGET_OBJECT_JUMBO_resolved: 12789 cmp r0, #0 @ resolution unsuccessful? 12790 beq common_exceptionThrown @ yes, throw exception 12791 @ fall through to OP_IGET_OBJECT_JUMBO_finish 12792 12793 /* 12794 * Currently: 12795 * r0 holds resolved field 12796 * r9 holds object 12797 */ 12798.LOP_IGET_OBJECT_JUMBO_finish: 12799 @bl common_squeak0 12800 cmp r9, #0 @ check object for null 12801 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12802 beq common_errNullObject @ object was null 12803 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12804 @ no-op @ acquiring load 12805 FETCH(r2, 3) @ r2<- BBBB 12806 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12807 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12808 GET_INST_OPCODE(ip) @ extract opcode from rINST 12809 GOTO_OPCODE(ip) @ jump to next instruction 12810 12811/* continuation for OP_IGET_BOOLEAN_JUMBO */ 12812 12813 /* 12814 * Currently: 12815 * r0 holds resolved field 12816 * r9 holds object 12817 */ 12818.LOP_IGET_BOOLEAN_JUMBO_resolved: 12819 cmp r0, #0 @ resolution unsuccessful? 12820 beq common_exceptionThrown @ yes, throw exception 12821 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish 12822 12823 /* 12824 * Currently: 12825 * r0 holds resolved field 12826 * r9 holds object 12827 */ 12828.LOP_IGET_BOOLEAN_JUMBO_finish: 12829 @bl common_squeak1 12830 cmp r9, #0 @ check object for null 12831 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12832 beq common_errNullObject @ object was null 12833 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12834 @ no-op @ acquiring load 12835 FETCH(r2, 3) @ r2<- BBBB 12836 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12837 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12838 GET_INST_OPCODE(ip) @ extract opcode from rINST 12839 GOTO_OPCODE(ip) @ jump to next instruction 12840 12841/* continuation for OP_IGET_BYTE_JUMBO */ 12842 12843 /* 12844 * Currently: 12845 * r0 holds resolved field 12846 * r9 holds object 12847 */ 12848.LOP_IGET_BYTE_JUMBO_resolved: 12849 cmp r0, #0 @ resolution unsuccessful? 12850 beq common_exceptionThrown @ yes, throw exception 12851 @ fall through to OP_IGET_BYTE_JUMBO_finish 12852 12853 /* 12854 * Currently: 12855 * r0 holds resolved field 12856 * r9 holds object 12857 */ 12858.LOP_IGET_BYTE_JUMBO_finish: 12859 @bl common_squeak2 12860 cmp r9, #0 @ check object for null 12861 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12862 beq common_errNullObject @ object was null 12863 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12864 @ no-op @ acquiring load 12865 FETCH(r2, 3) @ r2<- BBBB 12866 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12867 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12868 GET_INST_OPCODE(ip) @ extract opcode from rINST 12869 GOTO_OPCODE(ip) @ jump to next instruction 12870 12871/* continuation for OP_IGET_CHAR_JUMBO */ 12872 12873 /* 12874 * Currently: 12875 * r0 holds resolved field 12876 * r9 holds object 12877 */ 12878.LOP_IGET_CHAR_JUMBO_resolved: 12879 cmp r0, #0 @ resolution unsuccessful? 12880 beq common_exceptionThrown @ yes, throw exception 12881 @ fall through to OP_IGET_CHAR_JUMBO_finish 12882 12883 /* 12884 * Currently: 12885 * r0 holds resolved field 12886 * r9 holds object 12887 */ 12888.LOP_IGET_CHAR_JUMBO_finish: 12889 @bl common_squeak3 12890 cmp r9, #0 @ check object for null 12891 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12892 beq common_errNullObject @ object was null 12893 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12894 @ no-op @ acquiring load 12895 FETCH(r2, 3) @ r2<- BBBB 12896 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12897 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12898 GET_INST_OPCODE(ip) @ extract opcode from rINST 12899 GOTO_OPCODE(ip) @ jump to next instruction 12900 12901/* continuation for OP_IGET_SHORT_JUMBO */ 12902 12903 /* 12904 * Currently: 12905 * r0 holds resolved field 12906 * r9 holds object 12907 */ 12908.LOP_IGET_SHORT_JUMBO_resolved: 12909 cmp r0, #0 @ resolution unsuccessful? 12910 beq common_exceptionThrown @ yes, throw exception 12911 @ fall through to OP_IGET_SHORT_JUMBO_finish 12912 12913 /* 12914 * Currently: 12915 * r0 holds resolved field 12916 * r9 holds object 12917 */ 12918.LOP_IGET_SHORT_JUMBO_finish: 12919 @bl common_squeak4 12920 cmp r9, #0 @ check object for null 12921 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12922 beq common_errNullObject @ object was null 12923 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12924 @ no-op @ acquiring load 12925 FETCH(r2, 3) @ r2<- BBBB 12926 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12927 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12928 GET_INST_OPCODE(ip) @ extract opcode from rINST 12929 GOTO_OPCODE(ip) @ jump to next instruction 12930 12931/* continuation for OP_IPUT_JUMBO */ 12932 12933 /* 12934 * Currently: 12935 * r0 holds resolved field 12936 * r9 holds object 12937 */ 12938.LOP_IPUT_JUMBO_resolved: 12939 cmp r0, #0 @ resolution unsuccessful? 12940 beq common_exceptionThrown @ yes, throw exception 12941 @ fall through to OP_IPUT_JUMBO_finish 12942 12943 /* 12944 * Currently: 12945 * r0 holds resolved field 12946 * r9 holds object 12947 */ 12948.LOP_IPUT_JUMBO_finish: 12949 @bl common_squeak0 12950 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12951 FETCH(r1, 3) @ r1<- BBBB 12952 cmp r9, #0 @ check object for null 12953 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12954 beq common_errNullObject @ object was null 12955 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12956 GET_INST_OPCODE(ip) @ extract opcode from rINST 12957 @ no-op @ releasing store 12958 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12959 GOTO_OPCODE(ip) @ jump to next instruction 12960 12961/* continuation for OP_IPUT_WIDE_JUMBO */ 12962 12963 /* 12964 * Currently: 12965 * r0 holds resolved field 12966 * r9 holds object 12967 */ 12968.LOP_IPUT_WIDE_JUMBO_resolved: 12969 cmp r0, #0 @ resolution unsuccessful? 12970 beq common_exceptionThrown @ yes, throw exception 12971 @ fall through to OP_IPUT_WIDE_JUMBO_finish 12972 12973 /* 12974 * Currently: 12975 * r0 holds resolved field 12976 * r9 holds object 12977 */ 12978.LOP_IPUT_WIDE_JUMBO_finish: 12979 cmp r9, #0 @ check object for null 12980 FETCH(r2, 3) @ r1<- BBBB 12981 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12982 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12983 beq common_errNullObject @ object was null 12984 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12985 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 12986 GET_INST_OPCODE(r10) @ extract opcode from rINST 12987 .if 0 12988 add r2, r9, r3 @ r2<- target address 12989 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 12990 .else 12991 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12992 .endif 12993 GOTO_OPCODE(r10) @ jump to next instruction 12994 12995/* continuation for OP_IPUT_OBJECT_JUMBO */ 12996 12997 /* 12998 * Currently: 12999 * r0 holds resolved field 13000 * r9 holds object 13001 */ 13002.LOP_IPUT_OBJECT_JUMBO_resolved: 13003 cmp r0, #0 @ resolution unsuccessful? 13004 beq common_exceptionThrown @ yes, throw exception 13005 @ fall through to OP_IPUT_OBJECT_JUMBO_finish 13006 13007 /* 13008 * Currently: 13009 * r0 holds resolved field 13010 * r9 holds object 13011 */ 13012.LOP_IPUT_OBJECT_JUMBO_finish: 13013 @bl common_squeak0 13014 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13015 FETCH(r1, 3) @ r1<- BBBB 13016 cmp r9, #0 @ check object for null 13017 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13018 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13019 beq common_errNullObject @ object was null 13020 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13021 GET_INST_OPCODE(ip) @ extract opcode from rINST 13022 @ no-op @ releasing store 13023 str r0, [r9, r3] @ obj.field (32 bits)<- r0 13024 cmp r0, #0 @ stored a null reference? 13025 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 13026 GOTO_OPCODE(ip) @ jump to next instruction 13027 13028/* continuation for OP_IPUT_BOOLEAN_JUMBO */ 13029 13030 /* 13031 * Currently: 13032 * r0 holds resolved field 13033 * r9 holds object 13034 */ 13035.LOP_IPUT_BOOLEAN_JUMBO_resolved: 13036 cmp r0, #0 @ resolution unsuccessful? 13037 beq common_exceptionThrown @ yes, throw exception 13038 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish 13039 13040 /* 13041 * Currently: 13042 * r0 holds resolved field 13043 * r9 holds object 13044 */ 13045.LOP_IPUT_BOOLEAN_JUMBO_finish: 13046 @bl common_squeak1 13047 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13048 FETCH(r1, 3) @ r1<- BBBB 13049 cmp r9, #0 @ check object for null 13050 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13051 beq common_errNullObject @ object was null 13052 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13053 GET_INST_OPCODE(ip) @ extract opcode from rINST 13054 @ no-op @ releasing store 13055 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13056 GOTO_OPCODE(ip) @ jump to next instruction 13057 13058/* continuation for OP_IPUT_BYTE_JUMBO */ 13059 13060 /* 13061 * Currently: 13062 * r0 holds resolved field 13063 * r9 holds object 13064 */ 13065.LOP_IPUT_BYTE_JUMBO_resolved: 13066 cmp r0, #0 @ resolution unsuccessful? 13067 beq common_exceptionThrown @ yes, throw exception 13068 @ fall through to OP_IPUT_BYTE_JUMBO_finish 13069 13070 /* 13071 * Currently: 13072 * r0 holds resolved field 13073 * r9 holds object 13074 */ 13075.LOP_IPUT_BYTE_JUMBO_finish: 13076 @bl common_squeak2 13077 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13078 FETCH(r1, 3) @ r1<- BBBB 13079 cmp r9, #0 @ check object for null 13080 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13081 beq common_errNullObject @ object was null 13082 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13083 GET_INST_OPCODE(ip) @ extract opcode from rINST 13084 @ no-op @ releasing store 13085 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13086 GOTO_OPCODE(ip) @ jump to next instruction 13087 13088/* continuation for OP_IPUT_CHAR_JUMBO */ 13089 13090 /* 13091 * Currently: 13092 * r0 holds resolved field 13093 * r9 holds object 13094 */ 13095.LOP_IPUT_CHAR_JUMBO_resolved: 13096 cmp r0, #0 @ resolution unsuccessful? 13097 beq common_exceptionThrown @ yes, throw exception 13098 @ fall through to OP_IPUT_CHAR_JUMBO_finish 13099 13100 /* 13101 * Currently: 13102 * r0 holds resolved field 13103 * r9 holds object 13104 */ 13105.LOP_IPUT_CHAR_JUMBO_finish: 13106 @bl common_squeak3 13107 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13108 FETCH(r1, 3) @ r1<- BBBB 13109 cmp r9, #0 @ check object for null 13110 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13111 beq common_errNullObject @ object was null 13112 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13113 GET_INST_OPCODE(ip) @ extract opcode from rINST 13114 @ no-op @ releasing store 13115 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13116 GOTO_OPCODE(ip) @ jump to next instruction 13117 13118/* continuation for OP_IPUT_SHORT_JUMBO */ 13119 13120 /* 13121 * Currently: 13122 * r0 holds resolved field 13123 * r9 holds object 13124 */ 13125.LOP_IPUT_SHORT_JUMBO_resolved: 13126 cmp r0, #0 @ resolution unsuccessful? 13127 beq common_exceptionThrown @ yes, throw exception 13128 @ fall through to OP_IPUT_SHORT_JUMBO_finish 13129 13130 /* 13131 * Currently: 13132 * r0 holds resolved field 13133 * r9 holds object 13134 */ 13135.LOP_IPUT_SHORT_JUMBO_finish: 13136 @bl common_squeak4 13137 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13138 FETCH(r1, 3) @ r1<- BBBB 13139 cmp r9, #0 @ check object for null 13140 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13141 beq common_errNullObject @ object was null 13142 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13143 GET_INST_OPCODE(ip) @ extract opcode from rINST 13144 @ no-op @ releasing store 13145 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13146 GOTO_OPCODE(ip) @ jump to next instruction 13147 13148/* continuation for OP_SGET_JUMBO */ 13149 13150 /* 13151 * Continuation if the field has not yet been resolved. 13152 * r1: AAAAAAAA field ref 13153 */ 13154.LOP_SGET_JUMBO_resolve: 13155 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13156 EXPORT_PC() @ resolve() could throw, so export now 13157 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13158 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13159 cmp r0, #0 @ success? 13160 bne .LOP_SGET_JUMBO_finish @ yes, finish 13161 b common_exceptionThrown @ no, handle exception 13162 13163/* continuation for OP_SGET_WIDE_JUMBO */ 13164 13165 /* 13166 * Continuation if the field has not yet been resolved. 13167 * r1: AAAAAAAA field ref 13168 * 13169 * Returns StaticField pointer in r0. 13170 */ 13171.LOP_SGET_WIDE_JUMBO_resolve: 13172 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13173 EXPORT_PC() @ resolve() could throw, so export now 13174 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13175 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13176 cmp r0, #0 @ success? 13177 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish 13178 b common_exceptionThrown @ no, handle exception 13179 13180/* continuation for OP_SGET_OBJECT_JUMBO */ 13181 13182 /* 13183 * Continuation if the field has not yet been resolved. 13184 * r1: AAAAAAAA field ref 13185 */ 13186.LOP_SGET_OBJECT_JUMBO_resolve: 13187 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13188 EXPORT_PC() @ resolve() could throw, so export now 13189 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13190 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13191 cmp r0, #0 @ success? 13192 bne .LOP_SGET_OBJECT_JUMBO_finish @ yes, finish 13193 b common_exceptionThrown @ no, handle exception 13194 13195/* continuation for OP_SGET_BOOLEAN_JUMBO */ 13196 13197 /* 13198 * Continuation if the field has not yet been resolved. 13199 * r1: AAAAAAAA field ref 13200 */ 13201.LOP_SGET_BOOLEAN_JUMBO_resolve: 13202 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13203 EXPORT_PC() @ resolve() could throw, so export now 13204 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13205 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13206 cmp r0, #0 @ success? 13207 bne .LOP_SGET_BOOLEAN_JUMBO_finish @ yes, finish 13208 b common_exceptionThrown @ no, handle exception 13209 13210/* continuation for OP_SGET_BYTE_JUMBO */ 13211 13212 /* 13213 * Continuation if the field has not yet been resolved. 13214 * r1: AAAAAAAA field ref 13215 */ 13216.LOP_SGET_BYTE_JUMBO_resolve: 13217 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13218 EXPORT_PC() @ resolve() could throw, so export now 13219 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13220 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13221 cmp r0, #0 @ success? 13222 bne .LOP_SGET_BYTE_JUMBO_finish @ yes, finish 13223 b common_exceptionThrown @ no, handle exception 13224 13225/* continuation for OP_SGET_CHAR_JUMBO */ 13226 13227 /* 13228 * Continuation if the field has not yet been resolved. 13229 * r1: AAAAAAAA field ref 13230 */ 13231.LOP_SGET_CHAR_JUMBO_resolve: 13232 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13233 EXPORT_PC() @ resolve() could throw, so export now 13234 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13235 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13236 cmp r0, #0 @ success? 13237 bne .LOP_SGET_CHAR_JUMBO_finish @ yes, finish 13238 b common_exceptionThrown @ no, handle exception 13239 13240/* continuation for OP_SGET_SHORT_JUMBO */ 13241 13242 /* 13243 * Continuation if the field has not yet been resolved. 13244 * r1: AAAAAAAA field ref 13245 */ 13246.LOP_SGET_SHORT_JUMBO_resolve: 13247 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13248 EXPORT_PC() @ resolve() could throw, so export now 13249 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13250 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13251 cmp r0, #0 @ success? 13252 bne .LOP_SGET_SHORT_JUMBO_finish @ yes, finish 13253 b common_exceptionThrown @ no, handle exception 13254 13255/* continuation for OP_SPUT_JUMBO */ 13256 13257 /* 13258 * Continuation if the field has not yet been resolved. 13259 * r1: AAAAAAAA field ref 13260 */ 13261.LOP_SPUT_JUMBO_resolve: 13262 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13263 EXPORT_PC() @ resolve() could throw, so export now 13264 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13265 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13266 cmp r0, #0 @ success? 13267 bne .LOP_SPUT_JUMBO_finish @ yes, finish 13268 b common_exceptionThrown @ no, handle exception 13269 13270/* continuation for OP_SPUT_WIDE_JUMBO */ 13271 13272 /* 13273 * Continuation if the field has not yet been resolved. 13274 * r1: AAAAAAAA field ref 13275 * r9: &fp[BBBB] 13276 * 13277 * Returns StaticField pointer in r2. 13278 */ 13279.LOP_SPUT_WIDE_JUMBO_resolve: 13280 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13281 EXPORT_PC() @ resolve() could throw, so export now 13282 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13283 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13284 cmp r0, #0 @ success? 13285 mov r2, r0 @ copy to r2 13286 bne .LOP_SPUT_WIDE_JUMBO_finish @ yes, finish 13287 b common_exceptionThrown @ no, handle exception 13288 13289/* continuation for OP_SPUT_OBJECT_JUMBO */ 13290 13291.LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0 13292 FETCH(r2, 3) @ r2<- BBBB 13293 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 13294 GET_VREG(r1, r2) @ r1<- fp[BBBB] 13295 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13296 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 13297 GET_INST_OPCODE(ip) @ extract opcode from rINST 13298 @ no-op @ releasing store 13299 str r1, [r0, #offStaticField_value] @ field<- vBBBB 13300 cmp r1, #0 @ stored a null object? 13301 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 13302 GOTO_OPCODE(ip) @ jump to next instruction 13303 13304/* continuation for OP_SPUT_BOOLEAN_JUMBO */ 13305 13306 /* 13307 * Continuation if the field has not yet been resolved. 13308 * r1: AAAAAAAA field ref 13309 */ 13310.LOP_SPUT_BOOLEAN_JUMBO_resolve: 13311 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13312 EXPORT_PC() @ resolve() could throw, so export now 13313 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13314 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13315 cmp r0, #0 @ success? 13316 bne .LOP_SPUT_BOOLEAN_JUMBO_finish @ yes, finish 13317 b common_exceptionThrown @ no, handle exception 13318 13319/* continuation for OP_SPUT_BYTE_JUMBO */ 13320 13321 /* 13322 * Continuation if the field has not yet been resolved. 13323 * r1: AAAAAAAA field ref 13324 */ 13325.LOP_SPUT_BYTE_JUMBO_resolve: 13326 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13327 EXPORT_PC() @ resolve() could throw, so export now 13328 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13329 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13330 cmp r0, #0 @ success? 13331 bne .LOP_SPUT_BYTE_JUMBO_finish @ yes, finish 13332 b common_exceptionThrown @ no, handle exception 13333 13334/* continuation for OP_SPUT_CHAR_JUMBO */ 13335 13336 /* 13337 * Continuation if the field has not yet been resolved. 13338 * r1: AAAAAAAA field ref 13339 */ 13340.LOP_SPUT_CHAR_JUMBO_resolve: 13341 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13342 EXPORT_PC() @ resolve() could throw, so export now 13343 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13344 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13345 cmp r0, #0 @ success? 13346 bne .LOP_SPUT_CHAR_JUMBO_finish @ yes, finish 13347 b common_exceptionThrown @ no, handle exception 13348 13349/* continuation for OP_SPUT_SHORT_JUMBO */ 13350 13351 /* 13352 * Continuation if the field has not yet been resolved. 13353 * r1: AAAAAAAA field ref 13354 */ 13355.LOP_SPUT_SHORT_JUMBO_resolve: 13356 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13357 EXPORT_PC() @ resolve() could throw, so export now 13358 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13359 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13360 cmp r0, #0 @ success? 13361 bne .LOP_SPUT_SHORT_JUMBO_finish @ yes, finish 13362 b common_exceptionThrown @ no, handle exception 13363 13364/* continuation for OP_INVOKE_VIRTUAL_JUMBO */ 13365 13366 /* 13367 * At this point: 13368 * r0 = resolved base method 13369 */ 13370.LOP_INVOKE_VIRTUAL_JUMBO_continue: 13371 FETCH(r10, 4) @ r10<- CCCC 13372 GET_VREG(r1, r10) @ r1<- "this" ptr 13373 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13374 cmp r1, #0 @ is "this" null? 13375 beq common_errNullObject @ null "this", throw exception 13376 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 13377 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 13378 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 13379 bl common_invokeMethodJumbo @ continue on 13380 13381/* continuation for OP_INVOKE_SUPER_JUMBO */ 13382 13383 /* 13384 * At this point: 13385 * r0 = resolved base method 13386 * r9 = method->clazz 13387 */ 13388.LOP_INVOKE_SUPER_JUMBO_continue: 13389 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 13390 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13391 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 13392 EXPORT_PC() @ must export for invoke 13393 cmp r2, r3 @ compare (methodIndex, vtableCount) 13394 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass 13395 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 13396 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 13397 bl common_invokeMethodJumbo @ continue on 13398 13399.LOP_INVOKE_SUPER_JUMBO_resolve: 13400 mov r0, r9 @ r0<- method->clazz 13401 mov r2, #METHOD_VIRTUAL @ resolver method type 13402 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13403 cmp r0, #0 @ got null? 13404 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue 13405 b common_exceptionThrown @ yes, handle exception 13406 13407 /* 13408 * Throw a NoSuchMethodError with the method name as the message. 13409 * r0 = resolved base method 13410 */ 13411.LOP_INVOKE_SUPER_JUMBO_nsm: 13412 ldr r1, [r0, #offMethod_name] @ r1<- method name 13413 b common_errNoSuchMethod 13414 13415/* continuation for OP_INVOKE_DIRECT_JUMBO */ 13416 13417 /* 13418 * On entry: 13419 * r1 = reference (CCCC) 13420 * r10 = "this" register 13421 */ 13422.LOP_INVOKE_DIRECT_JUMBO_resolve: 13423 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 13424 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 13425 mov r2, #METHOD_DIRECT @ resolver method type 13426 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13427 cmp r0, #0 @ got null? 13428 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 13429 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue 13430 b common_exceptionThrown @ yes, handle exception 13431 13432/* continuation for OP_IGET_VOLATILE_JUMBO */ 13433 13434 /* 13435 * Currently: 13436 * r0 holds resolved field 13437 * r9 holds object 13438 */ 13439.LOP_IGET_VOLATILE_JUMBO_resolved: 13440 cmp r0, #0 @ resolution unsuccessful? 13441 beq common_exceptionThrown @ yes, throw exception 13442 @ fall through to OP_IGET_VOLATILE_JUMBO_finish 13443 13444 /* 13445 * Currently: 13446 * r0 holds resolved field 13447 * r9 holds object 13448 */ 13449.LOP_IGET_VOLATILE_JUMBO_finish: 13450 @bl common_squeak0 13451 cmp r9, #0 @ check object for null 13452 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13453 beq common_errNullObject @ object was null 13454 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13455 SMP_DMB @ acquiring load 13456 FETCH(r2, 3) @ r2<- BBBB 13457 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13458 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13459 GET_INST_OPCODE(ip) @ extract opcode from rINST 13460 GOTO_OPCODE(ip) @ jump to next instruction 13461 13462/* continuation for OP_IGET_WIDE_VOLATILE_JUMBO */ 13463 13464 /* 13465 * Currently: 13466 * r0 holds resolved field 13467 * r9 holds object 13468 */ 13469.LOP_IGET_WIDE_VOLATILE_JUMBO_resolved: 13470 cmp r0, #0 @ resolution unsuccessful? 13471 beq common_exceptionThrown @ yes, throw exception 13472 @ fall through to OP_IGET_WIDE_VOLATILE_JUMBO_finish 13473 13474 /* 13475 * Currently: 13476 * r0 holds resolved field 13477 * r9 holds object 13478 */ 13479.LOP_IGET_WIDE_VOLATILE_JUMBO_finish: 13480 cmp r9, #0 @ check object for null 13481 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13482 beq common_errNullObject @ object was null 13483 .if 1 13484 add r0, r9, r3 @ r0<- address of field 13485 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 13486 .else 13487 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 13488 .endif 13489 FETCH(r2, 3) @ r2<- BBBB 13490 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13491 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 13492 GET_INST_OPCODE(ip) @ extract opcode from rINST 13493 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 13494 GOTO_OPCODE(ip) @ jump to next instruction 13495 13496/* continuation for OP_IGET_OBJECT_VOLATILE_JUMBO */ 13497 13498 /* 13499 * Currently: 13500 * r0 holds resolved field 13501 * r9 holds object 13502 */ 13503.LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved: 13504 cmp r0, #0 @ resolution unsuccessful? 13505 beq common_exceptionThrown @ yes, throw exception 13506 @ fall through to OP_IGET_OBJECT_VOLATILE_JUMBO_finish 13507 13508 /* 13509 * Currently: 13510 * r0 holds resolved field 13511 * r9 holds object 13512 */ 13513.LOP_IGET_OBJECT_VOLATILE_JUMBO_finish: 13514 @bl common_squeak0 13515 cmp r9, #0 @ check object for null 13516 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13517 beq common_errNullObject @ object was null 13518 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13519 SMP_DMB @ acquiring load 13520 FETCH(r2, 3) @ r2<- BBBB 13521 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13522 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13523 GET_INST_OPCODE(ip) @ extract opcode from rINST 13524 GOTO_OPCODE(ip) @ jump to next instruction 13525 13526/* continuation for OP_IPUT_VOLATILE_JUMBO */ 13527 13528 /* 13529 * Currently: 13530 * r0 holds resolved field 13531 * r9 holds object 13532 */ 13533.LOP_IPUT_VOLATILE_JUMBO_resolved: 13534 cmp r0, #0 @ resolution unsuccessful? 13535 beq common_exceptionThrown @ yes, throw exception 13536 @ fall through to OP_IPUT_VOLATILE_JUMBO_finish 13537 13538 /* 13539 * Currently: 13540 * r0 holds resolved field 13541 * r9 holds object 13542 */ 13543.LOP_IPUT_VOLATILE_JUMBO_finish: 13544 @bl common_squeak0 13545 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13546 FETCH(r1, 3) @ r1<- BBBB 13547 cmp r9, #0 @ check object for null 13548 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13549 beq common_errNullObject @ object was null 13550 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13551 GET_INST_OPCODE(ip) @ extract opcode from rINST 13552 SMP_DMB @ releasing store 13553 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13554 GOTO_OPCODE(ip) @ jump to next instruction 13555 13556/* continuation for OP_IPUT_WIDE_VOLATILE_JUMBO */ 13557 13558 /* 13559 * Currently: 13560 * r0 holds resolved field 13561 * r9 holds object 13562 */ 13563.LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved: 13564 cmp r0, #0 @ resolution unsuccessful? 13565 beq common_exceptionThrown @ yes, throw exception 13566 @ fall through to OP_IPUT_WIDE_VOLATILE_JUMBO_finish 13567 13568 /* 13569 * Currently: 13570 * r0 holds resolved field 13571 * r9 holds object 13572 */ 13573.LOP_IPUT_WIDE_VOLATILE_JUMBO_finish: 13574 cmp r9, #0 @ check object for null 13575 FETCH(r2, 3) @ r1<- BBBB 13576 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13577 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 13578 beq common_errNullObject @ object was null 13579 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13580 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 13581 GET_INST_OPCODE(r10) @ extract opcode from rINST 13582 .if 1 13583 add r2, r9, r3 @ r2<- target address 13584 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 13585 .else 13586 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 13587 .endif 13588 GOTO_OPCODE(r10) @ jump to next instruction 13589 13590/* continuation for OP_IPUT_OBJECT_VOLATILE_JUMBO */ 13591 13592 /* 13593 * Currently: 13594 * r0 holds resolved field 13595 * r9 holds object 13596 */ 13597.LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved: 13598 cmp r0, #0 @ resolution unsuccessful? 13599 beq common_exceptionThrown @ yes, throw exception 13600 @ fall through to OP_IPUT_OBJECT_VOLATILE_JUMBO_finish 13601 13602 /* 13603 * Currently: 13604 * r0 holds resolved field 13605 * r9 holds object 13606 */ 13607.LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish: 13608 @bl common_squeak0 13609 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13610 FETCH(r1, 3) @ r1<- BBBB 13611 cmp r9, #0 @ check object for null 13612 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13613 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13614 beq common_errNullObject @ object was null 13615 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13616 GET_INST_OPCODE(ip) @ extract opcode from rINST 13617 SMP_DMB @ releasing store 13618 str r0, [r9, r3] @ obj.field (32 bits)<- r0 13619 cmp r0, #0 @ stored a null reference? 13620 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 13621 GOTO_OPCODE(ip) @ jump to next instruction 13622 13623/* continuation for OP_SGET_VOLATILE_JUMBO */ 13624 13625 /* 13626 * Continuation if the field has not yet been resolved. 13627 * r1: AAAAAAAA field ref 13628 */ 13629.LOP_SGET_VOLATILE_JUMBO_resolve: 13630 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13631 EXPORT_PC() @ resolve() could throw, so export now 13632 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13633 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13634 cmp r0, #0 @ success? 13635 bne .LOP_SGET_VOLATILE_JUMBO_finish @ yes, finish 13636 b common_exceptionThrown @ no, handle exception 13637 13638/* continuation for OP_SGET_WIDE_VOLATILE_JUMBO */ 13639 13640 /* 13641 * Continuation if the field has not yet been resolved. 13642 * r1: AAAAAAAA field ref 13643 * 13644 * Returns StaticField pointer in r0. 13645 */ 13646.LOP_SGET_WIDE_VOLATILE_JUMBO_resolve: 13647 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13648 EXPORT_PC() @ resolve() could throw, so export now 13649 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13650 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13651 cmp r0, #0 @ success? 13652 bne .LOP_SGET_WIDE_VOLATILE_JUMBO_finish @ yes, finish 13653 b common_exceptionThrown @ no, handle exception 13654 13655/* continuation for OP_SGET_OBJECT_VOLATILE_JUMBO */ 13656 13657 /* 13658 * Continuation if the field has not yet been resolved. 13659 * r1: AAAAAAAA field ref 13660 */ 13661.LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve: 13662 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13663 EXPORT_PC() @ resolve() could throw, so export now 13664 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13665 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13666 cmp r0, #0 @ success? 13667 bne .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish @ yes, finish 13668 b common_exceptionThrown @ no, handle exception 13669 13670/* continuation for OP_SPUT_VOLATILE_JUMBO */ 13671 13672 /* 13673 * Continuation if the field has not yet been resolved. 13674 * r1: AAAAAAAA field ref 13675 */ 13676.LOP_SPUT_VOLATILE_JUMBO_resolve: 13677 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13678 EXPORT_PC() @ resolve() could throw, so export now 13679 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13680 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13681 cmp r0, #0 @ success? 13682 bne .LOP_SPUT_VOLATILE_JUMBO_finish @ yes, finish 13683 b common_exceptionThrown @ no, handle exception 13684 13685/* continuation for OP_SPUT_WIDE_VOLATILE_JUMBO */ 13686 13687 /* 13688 * Continuation if the field has not yet been resolved. 13689 * r1: AAAAAAAA field ref 13690 * r9: &fp[BBBB] 13691 * 13692 * Returns StaticField pointer in r2. 13693 */ 13694.LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve: 13695 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13696 EXPORT_PC() @ resolve() could throw, so export now 13697 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13698 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13699 cmp r0, #0 @ success? 13700 mov r2, r0 @ copy to r2 13701 bne .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish @ yes, finish 13702 b common_exceptionThrown @ no, handle exception 13703 13704/* continuation for OP_SPUT_OBJECT_VOLATILE_JUMBO */ 13705 13706.LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0 13707 FETCH(r2, 3) @ r2<- BBBB 13708 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 13709 GET_VREG(r1, r2) @ r1<- fp[BBBB] 13710 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13711 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 13712 GET_INST_OPCODE(ip) @ extract opcode from rINST 13713 SMP_DMB @ releasing store 13714 str r1, [r0, #offStaticField_value] @ field<- vBBBB 13715 cmp r1, #0 @ stored a null object? 13716 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 13717 GOTO_OPCODE(ip) @ jump to next instruction 13718 13719 .size dvmAsmSisterStart, .-dvmAsmSisterStart 13720 .global dvmAsmSisterEnd 13721dvmAsmSisterEnd: 13722 13723 13724 .global dvmAsmAltInstructionStart 13725 .type dvmAsmAltInstructionStart, %function 13726dvmAsmAltInstructionStart: 13727 .text 13728 13729/* ------------------------------ */ 13730 .balign 64 13731.L_ALT_OP_NOP: /* 0x00 */ 13732/* File: armv5te/alt_stub.S */ 13733/* 13734 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13735 * any interesting requests and then jump to the real instruction 13736 * handler. Note that the call to dvmCheckInst is done as a tail call. 13737 */ 13738 adrl lr, dvmAsmInstructionStart + (0 * 64) 13739 mov r0, rPC @ arg0 13740 mov r1, rSELF @ arg1 13741 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13742 13743/* ------------------------------ */ 13744 .balign 64 13745.L_ALT_OP_MOVE: /* 0x01 */ 13746/* File: armv5te/alt_stub.S */ 13747/* 13748 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13749 * any interesting requests and then jump to the real instruction 13750 * handler. Note that the call to dvmCheckInst is done as a tail call. 13751 */ 13752 adrl lr, dvmAsmInstructionStart + (1 * 64) 13753 mov r0, rPC @ arg0 13754 mov r1, rSELF @ arg1 13755 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13756 13757/* ------------------------------ */ 13758 .balign 64 13759.L_ALT_OP_MOVE_FROM16: /* 0x02 */ 13760/* File: armv5te/alt_stub.S */ 13761/* 13762 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13763 * any interesting requests and then jump to the real instruction 13764 * handler. Note that the call to dvmCheckInst is done as a tail call. 13765 */ 13766 adrl lr, dvmAsmInstructionStart + (2 * 64) 13767 mov r0, rPC @ arg0 13768 mov r1, rSELF @ arg1 13769 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13770 13771/* ------------------------------ */ 13772 .balign 64 13773.L_ALT_OP_MOVE_16: /* 0x03 */ 13774/* File: armv5te/alt_stub.S */ 13775/* 13776 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13777 * any interesting requests and then jump to the real instruction 13778 * handler. Note that the call to dvmCheckInst is done as a tail call. 13779 */ 13780 adrl lr, dvmAsmInstructionStart + (3 * 64) 13781 mov r0, rPC @ arg0 13782 mov r1, rSELF @ arg1 13783 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13784 13785/* ------------------------------ */ 13786 .balign 64 13787.L_ALT_OP_MOVE_WIDE: /* 0x04 */ 13788/* File: armv5te/alt_stub.S */ 13789/* 13790 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13791 * any interesting requests and then jump to the real instruction 13792 * handler. Note that the call to dvmCheckInst is done as a tail call. 13793 */ 13794 adrl lr, dvmAsmInstructionStart + (4 * 64) 13795 mov r0, rPC @ arg0 13796 mov r1, rSELF @ arg1 13797 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13798 13799/* ------------------------------ */ 13800 .balign 64 13801.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */ 13802/* File: armv5te/alt_stub.S */ 13803/* 13804 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13805 * any interesting requests and then jump to the real instruction 13806 * handler. Note that the call to dvmCheckInst is done as a tail call. 13807 */ 13808 adrl lr, dvmAsmInstructionStart + (5 * 64) 13809 mov r0, rPC @ arg0 13810 mov r1, rSELF @ arg1 13811 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13812 13813/* ------------------------------ */ 13814 .balign 64 13815.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */ 13816/* File: armv5te/alt_stub.S */ 13817/* 13818 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13819 * any interesting requests and then jump to the real instruction 13820 * handler. Note that the call to dvmCheckInst is done as a tail call. 13821 */ 13822 adrl lr, dvmAsmInstructionStart + (6 * 64) 13823 mov r0, rPC @ arg0 13824 mov r1, rSELF @ arg1 13825 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13826 13827/* ------------------------------ */ 13828 .balign 64 13829.L_ALT_OP_MOVE_OBJECT: /* 0x07 */ 13830/* File: armv5te/alt_stub.S */ 13831/* 13832 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13833 * any interesting requests and then jump to the real instruction 13834 * handler. Note that the call to dvmCheckInst is done as a tail call. 13835 */ 13836 adrl lr, dvmAsmInstructionStart + (7 * 64) 13837 mov r0, rPC @ arg0 13838 mov r1, rSELF @ arg1 13839 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13840 13841/* ------------------------------ */ 13842 .balign 64 13843.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 13844/* File: armv5te/alt_stub.S */ 13845/* 13846 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13847 * any interesting requests and then jump to the real instruction 13848 * handler. Note that the call to dvmCheckInst is done as a tail call. 13849 */ 13850 adrl lr, dvmAsmInstructionStart + (8 * 64) 13851 mov r0, rPC @ arg0 13852 mov r1, rSELF @ arg1 13853 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13854 13855/* ------------------------------ */ 13856 .balign 64 13857.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */ 13858/* File: armv5te/alt_stub.S */ 13859/* 13860 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13861 * any interesting requests and then jump to the real instruction 13862 * handler. Note that the call to dvmCheckInst is done as a tail call. 13863 */ 13864 adrl lr, dvmAsmInstructionStart + (9 * 64) 13865 mov r0, rPC @ arg0 13866 mov r1, rSELF @ arg1 13867 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13868 13869/* ------------------------------ */ 13870 .balign 64 13871.L_ALT_OP_MOVE_RESULT: /* 0x0a */ 13872/* File: armv5te/alt_stub.S */ 13873/* 13874 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13875 * any interesting requests and then jump to the real instruction 13876 * handler. Note that the call to dvmCheckInst is done as a tail call. 13877 */ 13878 adrl lr, dvmAsmInstructionStart + (10 * 64) 13879 mov r0, rPC @ arg0 13880 mov r1, rSELF @ arg1 13881 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13882 13883/* ------------------------------ */ 13884 .balign 64 13885.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */ 13886/* File: armv5te/alt_stub.S */ 13887/* 13888 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13889 * any interesting requests and then jump to the real instruction 13890 * handler. Note that the call to dvmCheckInst is done as a tail call. 13891 */ 13892 adrl lr, dvmAsmInstructionStart + (11 * 64) 13893 mov r0, rPC @ arg0 13894 mov r1, rSELF @ arg1 13895 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13896 13897/* ------------------------------ */ 13898 .balign 64 13899.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 13900/* File: armv5te/alt_stub.S */ 13901/* 13902 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13903 * any interesting requests and then jump to the real instruction 13904 * handler. Note that the call to dvmCheckInst is done as a tail call. 13905 */ 13906 adrl lr, dvmAsmInstructionStart + (12 * 64) 13907 mov r0, rPC @ arg0 13908 mov r1, rSELF @ arg1 13909 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13910 13911/* ------------------------------ */ 13912 .balign 64 13913.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */ 13914/* File: armv5te/alt_stub.S */ 13915/* 13916 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13917 * any interesting requests and then jump to the real instruction 13918 * handler. Note that the call to dvmCheckInst is done as a tail call. 13919 */ 13920 adrl lr, dvmAsmInstructionStart + (13 * 64) 13921 mov r0, rPC @ arg0 13922 mov r1, rSELF @ arg1 13923 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13924 13925/* ------------------------------ */ 13926 .balign 64 13927.L_ALT_OP_RETURN_VOID: /* 0x0e */ 13928/* File: armv5te/alt_stub.S */ 13929/* 13930 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13931 * any interesting requests and then jump to the real instruction 13932 * handler. Note that the call to dvmCheckInst is done as a tail call. 13933 */ 13934 adrl lr, dvmAsmInstructionStart + (14 * 64) 13935 mov r0, rPC @ arg0 13936 mov r1, rSELF @ arg1 13937 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13938 13939/* ------------------------------ */ 13940 .balign 64 13941.L_ALT_OP_RETURN: /* 0x0f */ 13942/* File: armv5te/alt_stub.S */ 13943/* 13944 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13945 * any interesting requests and then jump to the real instruction 13946 * handler. Note that the call to dvmCheckInst is done as a tail call. 13947 */ 13948 adrl lr, dvmAsmInstructionStart + (15 * 64) 13949 mov r0, rPC @ arg0 13950 mov r1, rSELF @ arg1 13951 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13952 13953/* ------------------------------ */ 13954 .balign 64 13955.L_ALT_OP_RETURN_WIDE: /* 0x10 */ 13956/* File: armv5te/alt_stub.S */ 13957/* 13958 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13959 * any interesting requests and then jump to the real instruction 13960 * handler. Note that the call to dvmCheckInst is done as a tail call. 13961 */ 13962 adrl lr, dvmAsmInstructionStart + (16 * 64) 13963 mov r0, rPC @ arg0 13964 mov r1, rSELF @ arg1 13965 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13966 13967/* ------------------------------ */ 13968 .balign 64 13969.L_ALT_OP_RETURN_OBJECT: /* 0x11 */ 13970/* File: armv5te/alt_stub.S */ 13971/* 13972 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13973 * any interesting requests and then jump to the real instruction 13974 * handler. Note that the call to dvmCheckInst is done as a tail call. 13975 */ 13976 adrl lr, dvmAsmInstructionStart + (17 * 64) 13977 mov r0, rPC @ arg0 13978 mov r1, rSELF @ arg1 13979 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13980 13981/* ------------------------------ */ 13982 .balign 64 13983.L_ALT_OP_CONST_4: /* 0x12 */ 13984/* File: armv5te/alt_stub.S */ 13985/* 13986 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13987 * any interesting requests and then jump to the real instruction 13988 * handler. Note that the call to dvmCheckInst is done as a tail call. 13989 */ 13990 adrl lr, dvmAsmInstructionStart + (18 * 64) 13991 mov r0, rPC @ arg0 13992 mov r1, rSELF @ arg1 13993 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13994 13995/* ------------------------------ */ 13996 .balign 64 13997.L_ALT_OP_CONST_16: /* 0x13 */ 13998/* File: armv5te/alt_stub.S */ 13999/* 14000 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14001 * any interesting requests and then jump to the real instruction 14002 * handler. Note that the call to dvmCheckInst is done as a tail call. 14003 */ 14004 adrl lr, dvmAsmInstructionStart + (19 * 64) 14005 mov r0, rPC @ arg0 14006 mov r1, rSELF @ arg1 14007 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14008 14009/* ------------------------------ */ 14010 .balign 64 14011.L_ALT_OP_CONST: /* 0x14 */ 14012/* File: armv5te/alt_stub.S */ 14013/* 14014 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14015 * any interesting requests and then jump to the real instruction 14016 * handler. Note that the call to dvmCheckInst is done as a tail call. 14017 */ 14018 adrl lr, dvmAsmInstructionStart + (20 * 64) 14019 mov r0, rPC @ arg0 14020 mov r1, rSELF @ arg1 14021 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14022 14023/* ------------------------------ */ 14024 .balign 64 14025.L_ALT_OP_CONST_HIGH16: /* 0x15 */ 14026/* File: armv5te/alt_stub.S */ 14027/* 14028 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14029 * any interesting requests and then jump to the real instruction 14030 * handler. Note that the call to dvmCheckInst is done as a tail call. 14031 */ 14032 adrl lr, dvmAsmInstructionStart + (21 * 64) 14033 mov r0, rPC @ arg0 14034 mov r1, rSELF @ arg1 14035 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14036 14037/* ------------------------------ */ 14038 .balign 64 14039.L_ALT_OP_CONST_WIDE_16: /* 0x16 */ 14040/* File: armv5te/alt_stub.S */ 14041/* 14042 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14043 * any interesting requests and then jump to the real instruction 14044 * handler. Note that the call to dvmCheckInst is done as a tail call. 14045 */ 14046 adrl lr, dvmAsmInstructionStart + (22 * 64) 14047 mov r0, rPC @ arg0 14048 mov r1, rSELF @ arg1 14049 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14050 14051/* ------------------------------ */ 14052 .balign 64 14053.L_ALT_OP_CONST_WIDE_32: /* 0x17 */ 14054/* File: armv5te/alt_stub.S */ 14055/* 14056 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14057 * any interesting requests and then jump to the real instruction 14058 * handler. Note that the call to dvmCheckInst is done as a tail call. 14059 */ 14060 adrl lr, dvmAsmInstructionStart + (23 * 64) 14061 mov r0, rPC @ arg0 14062 mov r1, rSELF @ arg1 14063 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14064 14065/* ------------------------------ */ 14066 .balign 64 14067.L_ALT_OP_CONST_WIDE: /* 0x18 */ 14068/* File: armv5te/alt_stub.S */ 14069/* 14070 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14071 * any interesting requests and then jump to the real instruction 14072 * handler. Note that the call to dvmCheckInst is done as a tail call. 14073 */ 14074 adrl lr, dvmAsmInstructionStart + (24 * 64) 14075 mov r0, rPC @ arg0 14076 mov r1, rSELF @ arg1 14077 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14078 14079/* ------------------------------ */ 14080 .balign 64 14081.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */ 14082/* File: armv5te/alt_stub.S */ 14083/* 14084 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14085 * any interesting requests and then jump to the real instruction 14086 * handler. Note that the call to dvmCheckInst is done as a tail call. 14087 */ 14088 adrl lr, dvmAsmInstructionStart + (25 * 64) 14089 mov r0, rPC @ arg0 14090 mov r1, rSELF @ arg1 14091 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14092 14093/* ------------------------------ */ 14094 .balign 64 14095.L_ALT_OP_CONST_STRING: /* 0x1a */ 14096/* File: armv5te/alt_stub.S */ 14097/* 14098 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14099 * any interesting requests and then jump to the real instruction 14100 * handler. Note that the call to dvmCheckInst is done as a tail call. 14101 */ 14102 adrl lr, dvmAsmInstructionStart + (26 * 64) 14103 mov r0, rPC @ arg0 14104 mov r1, rSELF @ arg1 14105 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14106 14107/* ------------------------------ */ 14108 .balign 64 14109.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */ 14110/* File: armv5te/alt_stub.S */ 14111/* 14112 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14113 * any interesting requests and then jump to the real instruction 14114 * handler. Note that the call to dvmCheckInst is done as a tail call. 14115 */ 14116 adrl lr, dvmAsmInstructionStart + (27 * 64) 14117 mov r0, rPC @ arg0 14118 mov r1, rSELF @ arg1 14119 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14120 14121/* ------------------------------ */ 14122 .balign 64 14123.L_ALT_OP_CONST_CLASS: /* 0x1c */ 14124/* File: armv5te/alt_stub.S */ 14125/* 14126 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14127 * any interesting requests and then jump to the real instruction 14128 * handler. Note that the call to dvmCheckInst is done as a tail call. 14129 */ 14130 adrl lr, dvmAsmInstructionStart + (28 * 64) 14131 mov r0, rPC @ arg0 14132 mov r1, rSELF @ arg1 14133 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14134 14135/* ------------------------------ */ 14136 .balign 64 14137.L_ALT_OP_MONITOR_ENTER: /* 0x1d */ 14138/* File: armv5te/alt_stub.S */ 14139/* 14140 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14141 * any interesting requests and then jump to the real instruction 14142 * handler. Note that the call to dvmCheckInst is done as a tail call. 14143 */ 14144 adrl lr, dvmAsmInstructionStart + (29 * 64) 14145 mov r0, rPC @ arg0 14146 mov r1, rSELF @ arg1 14147 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14148 14149/* ------------------------------ */ 14150 .balign 64 14151.L_ALT_OP_MONITOR_EXIT: /* 0x1e */ 14152/* File: armv5te/alt_stub.S */ 14153/* 14154 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14155 * any interesting requests and then jump to the real instruction 14156 * handler. Note that the call to dvmCheckInst is done as a tail call. 14157 */ 14158 adrl lr, dvmAsmInstructionStart + (30 * 64) 14159 mov r0, rPC @ arg0 14160 mov r1, rSELF @ arg1 14161 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14162 14163/* ------------------------------ */ 14164 .balign 64 14165.L_ALT_OP_CHECK_CAST: /* 0x1f */ 14166/* File: armv5te/alt_stub.S */ 14167/* 14168 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14169 * any interesting requests and then jump to the real instruction 14170 * handler. Note that the call to dvmCheckInst is done as a tail call. 14171 */ 14172 adrl lr, dvmAsmInstructionStart + (31 * 64) 14173 mov r0, rPC @ arg0 14174 mov r1, rSELF @ arg1 14175 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14176 14177/* ------------------------------ */ 14178 .balign 64 14179.L_ALT_OP_INSTANCE_OF: /* 0x20 */ 14180/* File: armv5te/alt_stub.S */ 14181/* 14182 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14183 * any interesting requests and then jump to the real instruction 14184 * handler. Note that the call to dvmCheckInst is done as a tail call. 14185 */ 14186 adrl lr, dvmAsmInstructionStart + (32 * 64) 14187 mov r0, rPC @ arg0 14188 mov r1, rSELF @ arg1 14189 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14190 14191/* ------------------------------ */ 14192 .balign 64 14193.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */ 14194/* File: armv5te/alt_stub.S */ 14195/* 14196 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14197 * any interesting requests and then jump to the real instruction 14198 * handler. Note that the call to dvmCheckInst is done as a tail call. 14199 */ 14200 adrl lr, dvmAsmInstructionStart + (33 * 64) 14201 mov r0, rPC @ arg0 14202 mov r1, rSELF @ arg1 14203 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14204 14205/* ------------------------------ */ 14206 .balign 64 14207.L_ALT_OP_NEW_INSTANCE: /* 0x22 */ 14208/* File: armv5te/alt_stub.S */ 14209/* 14210 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14211 * any interesting requests and then jump to the real instruction 14212 * handler. Note that the call to dvmCheckInst is done as a tail call. 14213 */ 14214 adrl lr, dvmAsmInstructionStart + (34 * 64) 14215 mov r0, rPC @ arg0 14216 mov r1, rSELF @ arg1 14217 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14218 14219/* ------------------------------ */ 14220 .balign 64 14221.L_ALT_OP_NEW_ARRAY: /* 0x23 */ 14222/* File: armv5te/alt_stub.S */ 14223/* 14224 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14225 * any interesting requests and then jump to the real instruction 14226 * handler. Note that the call to dvmCheckInst is done as a tail call. 14227 */ 14228 adrl lr, dvmAsmInstructionStart + (35 * 64) 14229 mov r0, rPC @ arg0 14230 mov r1, rSELF @ arg1 14231 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14232 14233/* ------------------------------ */ 14234 .balign 64 14235.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */ 14236/* File: armv5te/alt_stub.S */ 14237/* 14238 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14239 * any interesting requests and then jump to the real instruction 14240 * handler. Note that the call to dvmCheckInst is done as a tail call. 14241 */ 14242 adrl lr, dvmAsmInstructionStart + (36 * 64) 14243 mov r0, rPC @ arg0 14244 mov r1, rSELF @ arg1 14245 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14246 14247/* ------------------------------ */ 14248 .balign 64 14249.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 14250/* File: armv5te/alt_stub.S */ 14251/* 14252 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14253 * any interesting requests and then jump to the real instruction 14254 * handler. Note that the call to dvmCheckInst is done as a tail call. 14255 */ 14256 adrl lr, dvmAsmInstructionStart + (37 * 64) 14257 mov r0, rPC @ arg0 14258 mov r1, rSELF @ arg1 14259 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14260 14261/* ------------------------------ */ 14262 .balign 64 14263.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */ 14264/* File: armv5te/alt_stub.S */ 14265/* 14266 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14267 * any interesting requests and then jump to the real instruction 14268 * handler. Note that the call to dvmCheckInst is done as a tail call. 14269 */ 14270 adrl lr, dvmAsmInstructionStart + (38 * 64) 14271 mov r0, rPC @ arg0 14272 mov r1, rSELF @ arg1 14273 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14274 14275/* ------------------------------ */ 14276 .balign 64 14277.L_ALT_OP_THROW: /* 0x27 */ 14278/* File: armv5te/alt_stub.S */ 14279/* 14280 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14281 * any interesting requests and then jump to the real instruction 14282 * handler. Note that the call to dvmCheckInst is done as a tail call. 14283 */ 14284 adrl lr, dvmAsmInstructionStart + (39 * 64) 14285 mov r0, rPC @ arg0 14286 mov r1, rSELF @ arg1 14287 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14288 14289/* ------------------------------ */ 14290 .balign 64 14291.L_ALT_OP_GOTO: /* 0x28 */ 14292/* File: armv5te/alt_stub.S */ 14293/* 14294 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14295 * any interesting requests and then jump to the real instruction 14296 * handler. Note that the call to dvmCheckInst is done as a tail call. 14297 */ 14298 adrl lr, dvmAsmInstructionStart + (40 * 64) 14299 mov r0, rPC @ arg0 14300 mov r1, rSELF @ arg1 14301 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14302 14303/* ------------------------------ */ 14304 .balign 64 14305.L_ALT_OP_GOTO_16: /* 0x29 */ 14306/* File: armv5te/alt_stub.S */ 14307/* 14308 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14309 * any interesting requests and then jump to the real instruction 14310 * handler. Note that the call to dvmCheckInst is done as a tail call. 14311 */ 14312 adrl lr, dvmAsmInstructionStart + (41 * 64) 14313 mov r0, rPC @ arg0 14314 mov r1, rSELF @ arg1 14315 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14316 14317/* ------------------------------ */ 14318 .balign 64 14319.L_ALT_OP_GOTO_32: /* 0x2a */ 14320/* File: armv5te/alt_stub.S */ 14321/* 14322 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14323 * any interesting requests and then jump to the real instruction 14324 * handler. Note that the call to dvmCheckInst is done as a tail call. 14325 */ 14326 adrl lr, dvmAsmInstructionStart + (42 * 64) 14327 mov r0, rPC @ arg0 14328 mov r1, rSELF @ arg1 14329 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14330 14331/* ------------------------------ */ 14332 .balign 64 14333.L_ALT_OP_PACKED_SWITCH: /* 0x2b */ 14334/* File: armv5te/alt_stub.S */ 14335/* 14336 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14337 * any interesting requests and then jump to the real instruction 14338 * handler. Note that the call to dvmCheckInst is done as a tail call. 14339 */ 14340 adrl lr, dvmAsmInstructionStart + (43 * 64) 14341 mov r0, rPC @ arg0 14342 mov r1, rSELF @ arg1 14343 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14344 14345/* ------------------------------ */ 14346 .balign 64 14347.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */ 14348/* File: armv5te/alt_stub.S */ 14349/* 14350 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14351 * any interesting requests and then jump to the real instruction 14352 * handler. Note that the call to dvmCheckInst is done as a tail call. 14353 */ 14354 adrl lr, dvmAsmInstructionStart + (44 * 64) 14355 mov r0, rPC @ arg0 14356 mov r1, rSELF @ arg1 14357 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14358 14359/* ------------------------------ */ 14360 .balign 64 14361.L_ALT_OP_CMPL_FLOAT: /* 0x2d */ 14362/* File: armv5te/alt_stub.S */ 14363/* 14364 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14365 * any interesting requests and then jump to the real instruction 14366 * handler. Note that the call to dvmCheckInst is done as a tail call. 14367 */ 14368 adrl lr, dvmAsmInstructionStart + (45 * 64) 14369 mov r0, rPC @ arg0 14370 mov r1, rSELF @ arg1 14371 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14372 14373/* ------------------------------ */ 14374 .balign 64 14375.L_ALT_OP_CMPG_FLOAT: /* 0x2e */ 14376/* File: armv5te/alt_stub.S */ 14377/* 14378 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14379 * any interesting requests and then jump to the real instruction 14380 * handler. Note that the call to dvmCheckInst is done as a tail call. 14381 */ 14382 adrl lr, dvmAsmInstructionStart + (46 * 64) 14383 mov r0, rPC @ arg0 14384 mov r1, rSELF @ arg1 14385 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14386 14387/* ------------------------------ */ 14388 .balign 64 14389.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */ 14390/* File: armv5te/alt_stub.S */ 14391/* 14392 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14393 * any interesting requests and then jump to the real instruction 14394 * handler. Note that the call to dvmCheckInst is done as a tail call. 14395 */ 14396 adrl lr, dvmAsmInstructionStart + (47 * 64) 14397 mov r0, rPC @ arg0 14398 mov r1, rSELF @ arg1 14399 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14400 14401/* ------------------------------ */ 14402 .balign 64 14403.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */ 14404/* File: armv5te/alt_stub.S */ 14405/* 14406 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14407 * any interesting requests and then jump to the real instruction 14408 * handler. Note that the call to dvmCheckInst is done as a tail call. 14409 */ 14410 adrl lr, dvmAsmInstructionStart + (48 * 64) 14411 mov r0, rPC @ arg0 14412 mov r1, rSELF @ arg1 14413 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14414 14415/* ------------------------------ */ 14416 .balign 64 14417.L_ALT_OP_CMP_LONG: /* 0x31 */ 14418/* File: armv5te/alt_stub.S */ 14419/* 14420 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14421 * any interesting requests and then jump to the real instruction 14422 * handler. Note that the call to dvmCheckInst is done as a tail call. 14423 */ 14424 adrl lr, dvmAsmInstructionStart + (49 * 64) 14425 mov r0, rPC @ arg0 14426 mov r1, rSELF @ arg1 14427 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14428 14429/* ------------------------------ */ 14430 .balign 64 14431.L_ALT_OP_IF_EQ: /* 0x32 */ 14432/* File: armv5te/alt_stub.S */ 14433/* 14434 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14435 * any interesting requests and then jump to the real instruction 14436 * handler. Note that the call to dvmCheckInst is done as a tail call. 14437 */ 14438 adrl lr, dvmAsmInstructionStart + (50 * 64) 14439 mov r0, rPC @ arg0 14440 mov r1, rSELF @ arg1 14441 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14442 14443/* ------------------------------ */ 14444 .balign 64 14445.L_ALT_OP_IF_NE: /* 0x33 */ 14446/* File: armv5te/alt_stub.S */ 14447/* 14448 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14449 * any interesting requests and then jump to the real instruction 14450 * handler. Note that the call to dvmCheckInst is done as a tail call. 14451 */ 14452 adrl lr, dvmAsmInstructionStart + (51 * 64) 14453 mov r0, rPC @ arg0 14454 mov r1, rSELF @ arg1 14455 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14456 14457/* ------------------------------ */ 14458 .balign 64 14459.L_ALT_OP_IF_LT: /* 0x34 */ 14460/* File: armv5te/alt_stub.S */ 14461/* 14462 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14463 * any interesting requests and then jump to the real instruction 14464 * handler. Note that the call to dvmCheckInst is done as a tail call. 14465 */ 14466 adrl lr, dvmAsmInstructionStart + (52 * 64) 14467 mov r0, rPC @ arg0 14468 mov r1, rSELF @ arg1 14469 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14470 14471/* ------------------------------ */ 14472 .balign 64 14473.L_ALT_OP_IF_GE: /* 0x35 */ 14474/* File: armv5te/alt_stub.S */ 14475/* 14476 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14477 * any interesting requests and then jump to the real instruction 14478 * handler. Note that the call to dvmCheckInst is done as a tail call. 14479 */ 14480 adrl lr, dvmAsmInstructionStart + (53 * 64) 14481 mov r0, rPC @ arg0 14482 mov r1, rSELF @ arg1 14483 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14484 14485/* ------------------------------ */ 14486 .balign 64 14487.L_ALT_OP_IF_GT: /* 0x36 */ 14488/* File: armv5te/alt_stub.S */ 14489/* 14490 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14491 * any interesting requests and then jump to the real instruction 14492 * handler. Note that the call to dvmCheckInst is done as a tail call. 14493 */ 14494 adrl lr, dvmAsmInstructionStart + (54 * 64) 14495 mov r0, rPC @ arg0 14496 mov r1, rSELF @ arg1 14497 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14498 14499/* ------------------------------ */ 14500 .balign 64 14501.L_ALT_OP_IF_LE: /* 0x37 */ 14502/* File: armv5te/alt_stub.S */ 14503/* 14504 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14505 * any interesting requests and then jump to the real instruction 14506 * handler. Note that the call to dvmCheckInst is done as a tail call. 14507 */ 14508 adrl lr, dvmAsmInstructionStart + (55 * 64) 14509 mov r0, rPC @ arg0 14510 mov r1, rSELF @ arg1 14511 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14512 14513/* ------------------------------ */ 14514 .balign 64 14515.L_ALT_OP_IF_EQZ: /* 0x38 */ 14516/* File: armv5te/alt_stub.S */ 14517/* 14518 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14519 * any interesting requests and then jump to the real instruction 14520 * handler. Note that the call to dvmCheckInst is done as a tail call. 14521 */ 14522 adrl lr, dvmAsmInstructionStart + (56 * 64) 14523 mov r0, rPC @ arg0 14524 mov r1, rSELF @ arg1 14525 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14526 14527/* ------------------------------ */ 14528 .balign 64 14529.L_ALT_OP_IF_NEZ: /* 0x39 */ 14530/* File: armv5te/alt_stub.S */ 14531/* 14532 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14533 * any interesting requests and then jump to the real instruction 14534 * handler. Note that the call to dvmCheckInst is done as a tail call. 14535 */ 14536 adrl lr, dvmAsmInstructionStart + (57 * 64) 14537 mov r0, rPC @ arg0 14538 mov r1, rSELF @ arg1 14539 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14540 14541/* ------------------------------ */ 14542 .balign 64 14543.L_ALT_OP_IF_LTZ: /* 0x3a */ 14544/* File: armv5te/alt_stub.S */ 14545/* 14546 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14547 * any interesting requests and then jump to the real instruction 14548 * handler. Note that the call to dvmCheckInst is done as a tail call. 14549 */ 14550 adrl lr, dvmAsmInstructionStart + (58 * 64) 14551 mov r0, rPC @ arg0 14552 mov r1, rSELF @ arg1 14553 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14554 14555/* ------------------------------ */ 14556 .balign 64 14557.L_ALT_OP_IF_GEZ: /* 0x3b */ 14558/* File: armv5te/alt_stub.S */ 14559/* 14560 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14561 * any interesting requests and then jump to the real instruction 14562 * handler. Note that the call to dvmCheckInst is done as a tail call. 14563 */ 14564 adrl lr, dvmAsmInstructionStart + (59 * 64) 14565 mov r0, rPC @ arg0 14566 mov r1, rSELF @ arg1 14567 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14568 14569/* ------------------------------ */ 14570 .balign 64 14571.L_ALT_OP_IF_GTZ: /* 0x3c */ 14572/* File: armv5te/alt_stub.S */ 14573/* 14574 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14575 * any interesting requests and then jump to the real instruction 14576 * handler. Note that the call to dvmCheckInst is done as a tail call. 14577 */ 14578 adrl lr, dvmAsmInstructionStart + (60 * 64) 14579 mov r0, rPC @ arg0 14580 mov r1, rSELF @ arg1 14581 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14582 14583/* ------------------------------ */ 14584 .balign 64 14585.L_ALT_OP_IF_LEZ: /* 0x3d */ 14586/* File: armv5te/alt_stub.S */ 14587/* 14588 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14589 * any interesting requests and then jump to the real instruction 14590 * handler. Note that the call to dvmCheckInst is done as a tail call. 14591 */ 14592 adrl lr, dvmAsmInstructionStart + (61 * 64) 14593 mov r0, rPC @ arg0 14594 mov r1, rSELF @ arg1 14595 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14596 14597/* ------------------------------ */ 14598 .balign 64 14599.L_ALT_OP_UNUSED_3E: /* 0x3e */ 14600/* File: armv5te/alt_stub.S */ 14601/* 14602 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14603 * any interesting requests and then jump to the real instruction 14604 * handler. Note that the call to dvmCheckInst is done as a tail call. 14605 */ 14606 adrl lr, dvmAsmInstructionStart + (62 * 64) 14607 mov r0, rPC @ arg0 14608 mov r1, rSELF @ arg1 14609 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14610 14611/* ------------------------------ */ 14612 .balign 64 14613.L_ALT_OP_UNUSED_3F: /* 0x3f */ 14614/* File: armv5te/alt_stub.S */ 14615/* 14616 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14617 * any interesting requests and then jump to the real instruction 14618 * handler. Note that the call to dvmCheckInst is done as a tail call. 14619 */ 14620 adrl lr, dvmAsmInstructionStart + (63 * 64) 14621 mov r0, rPC @ arg0 14622 mov r1, rSELF @ arg1 14623 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14624 14625/* ------------------------------ */ 14626 .balign 64 14627.L_ALT_OP_UNUSED_40: /* 0x40 */ 14628/* File: armv5te/alt_stub.S */ 14629/* 14630 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14631 * any interesting requests and then jump to the real instruction 14632 * handler. Note that the call to dvmCheckInst is done as a tail call. 14633 */ 14634 adrl lr, dvmAsmInstructionStart + (64 * 64) 14635 mov r0, rPC @ arg0 14636 mov r1, rSELF @ arg1 14637 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14638 14639/* ------------------------------ */ 14640 .balign 64 14641.L_ALT_OP_UNUSED_41: /* 0x41 */ 14642/* File: armv5te/alt_stub.S */ 14643/* 14644 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14645 * any interesting requests and then jump to the real instruction 14646 * handler. Note that the call to dvmCheckInst is done as a tail call. 14647 */ 14648 adrl lr, dvmAsmInstructionStart + (65 * 64) 14649 mov r0, rPC @ arg0 14650 mov r1, rSELF @ arg1 14651 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14652 14653/* ------------------------------ */ 14654 .balign 64 14655.L_ALT_OP_UNUSED_42: /* 0x42 */ 14656/* File: armv5te/alt_stub.S */ 14657/* 14658 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14659 * any interesting requests and then jump to the real instruction 14660 * handler. Note that the call to dvmCheckInst is done as a tail call. 14661 */ 14662 adrl lr, dvmAsmInstructionStart + (66 * 64) 14663 mov r0, rPC @ arg0 14664 mov r1, rSELF @ arg1 14665 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14666 14667/* ------------------------------ */ 14668 .balign 64 14669.L_ALT_OP_UNUSED_43: /* 0x43 */ 14670/* File: armv5te/alt_stub.S */ 14671/* 14672 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14673 * any interesting requests and then jump to the real instruction 14674 * handler. Note that the call to dvmCheckInst is done as a tail call. 14675 */ 14676 adrl lr, dvmAsmInstructionStart + (67 * 64) 14677 mov r0, rPC @ arg0 14678 mov r1, rSELF @ arg1 14679 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14680 14681/* ------------------------------ */ 14682 .balign 64 14683.L_ALT_OP_AGET: /* 0x44 */ 14684/* File: armv5te/alt_stub.S */ 14685/* 14686 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14687 * any interesting requests and then jump to the real instruction 14688 * handler. Note that the call to dvmCheckInst is done as a tail call. 14689 */ 14690 adrl lr, dvmAsmInstructionStart + (68 * 64) 14691 mov r0, rPC @ arg0 14692 mov r1, rSELF @ arg1 14693 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14694 14695/* ------------------------------ */ 14696 .balign 64 14697.L_ALT_OP_AGET_WIDE: /* 0x45 */ 14698/* File: armv5te/alt_stub.S */ 14699/* 14700 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14701 * any interesting requests and then jump to the real instruction 14702 * handler. Note that the call to dvmCheckInst is done as a tail call. 14703 */ 14704 adrl lr, dvmAsmInstructionStart + (69 * 64) 14705 mov r0, rPC @ arg0 14706 mov r1, rSELF @ arg1 14707 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14708 14709/* ------------------------------ */ 14710 .balign 64 14711.L_ALT_OP_AGET_OBJECT: /* 0x46 */ 14712/* File: armv5te/alt_stub.S */ 14713/* 14714 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14715 * any interesting requests and then jump to the real instruction 14716 * handler. Note that the call to dvmCheckInst is done as a tail call. 14717 */ 14718 adrl lr, dvmAsmInstructionStart + (70 * 64) 14719 mov r0, rPC @ arg0 14720 mov r1, rSELF @ arg1 14721 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14722 14723/* ------------------------------ */ 14724 .balign 64 14725.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */ 14726/* File: armv5te/alt_stub.S */ 14727/* 14728 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14729 * any interesting requests and then jump to the real instruction 14730 * handler. Note that the call to dvmCheckInst is done as a tail call. 14731 */ 14732 adrl lr, dvmAsmInstructionStart + (71 * 64) 14733 mov r0, rPC @ arg0 14734 mov r1, rSELF @ arg1 14735 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14736 14737/* ------------------------------ */ 14738 .balign 64 14739.L_ALT_OP_AGET_BYTE: /* 0x48 */ 14740/* File: armv5te/alt_stub.S */ 14741/* 14742 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14743 * any interesting requests and then jump to the real instruction 14744 * handler. Note that the call to dvmCheckInst is done as a tail call. 14745 */ 14746 adrl lr, dvmAsmInstructionStart + (72 * 64) 14747 mov r0, rPC @ arg0 14748 mov r1, rSELF @ arg1 14749 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14750 14751/* ------------------------------ */ 14752 .balign 64 14753.L_ALT_OP_AGET_CHAR: /* 0x49 */ 14754/* File: armv5te/alt_stub.S */ 14755/* 14756 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14757 * any interesting requests and then jump to the real instruction 14758 * handler. Note that the call to dvmCheckInst is done as a tail call. 14759 */ 14760 adrl lr, dvmAsmInstructionStart + (73 * 64) 14761 mov r0, rPC @ arg0 14762 mov r1, rSELF @ arg1 14763 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14764 14765/* ------------------------------ */ 14766 .balign 64 14767.L_ALT_OP_AGET_SHORT: /* 0x4a */ 14768/* File: armv5te/alt_stub.S */ 14769/* 14770 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14771 * any interesting requests and then jump to the real instruction 14772 * handler. Note that the call to dvmCheckInst is done as a tail call. 14773 */ 14774 adrl lr, dvmAsmInstructionStart + (74 * 64) 14775 mov r0, rPC @ arg0 14776 mov r1, rSELF @ arg1 14777 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14778 14779/* ------------------------------ */ 14780 .balign 64 14781.L_ALT_OP_APUT: /* 0x4b */ 14782/* File: armv5te/alt_stub.S */ 14783/* 14784 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14785 * any interesting requests and then jump to the real instruction 14786 * handler. Note that the call to dvmCheckInst is done as a tail call. 14787 */ 14788 adrl lr, dvmAsmInstructionStart + (75 * 64) 14789 mov r0, rPC @ arg0 14790 mov r1, rSELF @ arg1 14791 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14792 14793/* ------------------------------ */ 14794 .balign 64 14795.L_ALT_OP_APUT_WIDE: /* 0x4c */ 14796/* File: armv5te/alt_stub.S */ 14797/* 14798 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14799 * any interesting requests and then jump to the real instruction 14800 * handler. Note that the call to dvmCheckInst is done as a tail call. 14801 */ 14802 adrl lr, dvmAsmInstructionStart + (76 * 64) 14803 mov r0, rPC @ arg0 14804 mov r1, rSELF @ arg1 14805 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14806 14807/* ------------------------------ */ 14808 .balign 64 14809.L_ALT_OP_APUT_OBJECT: /* 0x4d */ 14810/* File: armv5te/alt_stub.S */ 14811/* 14812 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14813 * any interesting requests and then jump to the real instruction 14814 * handler. Note that the call to dvmCheckInst is done as a tail call. 14815 */ 14816 adrl lr, dvmAsmInstructionStart + (77 * 64) 14817 mov r0, rPC @ arg0 14818 mov r1, rSELF @ arg1 14819 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14820 14821/* ------------------------------ */ 14822 .balign 64 14823.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */ 14824/* File: armv5te/alt_stub.S */ 14825/* 14826 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14827 * any interesting requests and then jump to the real instruction 14828 * handler. Note that the call to dvmCheckInst is done as a tail call. 14829 */ 14830 adrl lr, dvmAsmInstructionStart + (78 * 64) 14831 mov r0, rPC @ arg0 14832 mov r1, rSELF @ arg1 14833 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14834 14835/* ------------------------------ */ 14836 .balign 64 14837.L_ALT_OP_APUT_BYTE: /* 0x4f */ 14838/* File: armv5te/alt_stub.S */ 14839/* 14840 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14841 * any interesting requests and then jump to the real instruction 14842 * handler. Note that the call to dvmCheckInst is done as a tail call. 14843 */ 14844 adrl lr, dvmAsmInstructionStart + (79 * 64) 14845 mov r0, rPC @ arg0 14846 mov r1, rSELF @ arg1 14847 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14848 14849/* ------------------------------ */ 14850 .balign 64 14851.L_ALT_OP_APUT_CHAR: /* 0x50 */ 14852/* File: armv5te/alt_stub.S */ 14853/* 14854 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14855 * any interesting requests and then jump to the real instruction 14856 * handler. Note that the call to dvmCheckInst is done as a tail call. 14857 */ 14858 adrl lr, dvmAsmInstructionStart + (80 * 64) 14859 mov r0, rPC @ arg0 14860 mov r1, rSELF @ arg1 14861 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14862 14863/* ------------------------------ */ 14864 .balign 64 14865.L_ALT_OP_APUT_SHORT: /* 0x51 */ 14866/* File: armv5te/alt_stub.S */ 14867/* 14868 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14869 * any interesting requests and then jump to the real instruction 14870 * handler. Note that the call to dvmCheckInst is done as a tail call. 14871 */ 14872 adrl lr, dvmAsmInstructionStart + (81 * 64) 14873 mov r0, rPC @ arg0 14874 mov r1, rSELF @ arg1 14875 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14876 14877/* ------------------------------ */ 14878 .balign 64 14879.L_ALT_OP_IGET: /* 0x52 */ 14880/* File: armv5te/alt_stub.S */ 14881/* 14882 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14883 * any interesting requests and then jump to the real instruction 14884 * handler. Note that the call to dvmCheckInst is done as a tail call. 14885 */ 14886 adrl lr, dvmAsmInstructionStart + (82 * 64) 14887 mov r0, rPC @ arg0 14888 mov r1, rSELF @ arg1 14889 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14890 14891/* ------------------------------ */ 14892 .balign 64 14893.L_ALT_OP_IGET_WIDE: /* 0x53 */ 14894/* File: armv5te/alt_stub.S */ 14895/* 14896 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14897 * any interesting requests and then jump to the real instruction 14898 * handler. Note that the call to dvmCheckInst is done as a tail call. 14899 */ 14900 adrl lr, dvmAsmInstructionStart + (83 * 64) 14901 mov r0, rPC @ arg0 14902 mov r1, rSELF @ arg1 14903 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14904 14905/* ------------------------------ */ 14906 .balign 64 14907.L_ALT_OP_IGET_OBJECT: /* 0x54 */ 14908/* File: armv5te/alt_stub.S */ 14909/* 14910 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14911 * any interesting requests and then jump to the real instruction 14912 * handler. Note that the call to dvmCheckInst is done as a tail call. 14913 */ 14914 adrl lr, dvmAsmInstructionStart + (84 * 64) 14915 mov r0, rPC @ arg0 14916 mov r1, rSELF @ arg1 14917 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14918 14919/* ------------------------------ */ 14920 .balign 64 14921.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */ 14922/* File: armv5te/alt_stub.S */ 14923/* 14924 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14925 * any interesting requests and then jump to the real instruction 14926 * handler. Note that the call to dvmCheckInst is done as a tail call. 14927 */ 14928 adrl lr, dvmAsmInstructionStart + (85 * 64) 14929 mov r0, rPC @ arg0 14930 mov r1, rSELF @ arg1 14931 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14932 14933/* ------------------------------ */ 14934 .balign 64 14935.L_ALT_OP_IGET_BYTE: /* 0x56 */ 14936/* File: armv5te/alt_stub.S */ 14937/* 14938 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14939 * any interesting requests and then jump to the real instruction 14940 * handler. Note that the call to dvmCheckInst is done as a tail call. 14941 */ 14942 adrl lr, dvmAsmInstructionStart + (86 * 64) 14943 mov r0, rPC @ arg0 14944 mov r1, rSELF @ arg1 14945 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14946 14947/* ------------------------------ */ 14948 .balign 64 14949.L_ALT_OP_IGET_CHAR: /* 0x57 */ 14950/* File: armv5te/alt_stub.S */ 14951/* 14952 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14953 * any interesting requests and then jump to the real instruction 14954 * handler. Note that the call to dvmCheckInst is done as a tail call. 14955 */ 14956 adrl lr, dvmAsmInstructionStart + (87 * 64) 14957 mov r0, rPC @ arg0 14958 mov r1, rSELF @ arg1 14959 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14960 14961/* ------------------------------ */ 14962 .balign 64 14963.L_ALT_OP_IGET_SHORT: /* 0x58 */ 14964/* File: armv5te/alt_stub.S */ 14965/* 14966 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14967 * any interesting requests and then jump to the real instruction 14968 * handler. Note that the call to dvmCheckInst is done as a tail call. 14969 */ 14970 adrl lr, dvmAsmInstructionStart + (88 * 64) 14971 mov r0, rPC @ arg0 14972 mov r1, rSELF @ arg1 14973 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14974 14975/* ------------------------------ */ 14976 .balign 64 14977.L_ALT_OP_IPUT: /* 0x59 */ 14978/* File: armv5te/alt_stub.S */ 14979/* 14980 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14981 * any interesting requests and then jump to the real instruction 14982 * handler. Note that the call to dvmCheckInst is done as a tail call. 14983 */ 14984 adrl lr, dvmAsmInstructionStart + (89 * 64) 14985 mov r0, rPC @ arg0 14986 mov r1, rSELF @ arg1 14987 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14988 14989/* ------------------------------ */ 14990 .balign 64 14991.L_ALT_OP_IPUT_WIDE: /* 0x5a */ 14992/* File: armv5te/alt_stub.S */ 14993/* 14994 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14995 * any interesting requests and then jump to the real instruction 14996 * handler. Note that the call to dvmCheckInst is done as a tail call. 14997 */ 14998 adrl lr, dvmAsmInstructionStart + (90 * 64) 14999 mov r0, rPC @ arg0 15000 mov r1, rSELF @ arg1 15001 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15002 15003/* ------------------------------ */ 15004 .balign 64 15005.L_ALT_OP_IPUT_OBJECT: /* 0x5b */ 15006/* File: armv5te/alt_stub.S */ 15007/* 15008 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15009 * any interesting requests and then jump to the real instruction 15010 * handler. Note that the call to dvmCheckInst is done as a tail call. 15011 */ 15012 adrl lr, dvmAsmInstructionStart + (91 * 64) 15013 mov r0, rPC @ arg0 15014 mov r1, rSELF @ arg1 15015 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15016 15017/* ------------------------------ */ 15018 .balign 64 15019.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */ 15020/* File: armv5te/alt_stub.S */ 15021/* 15022 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15023 * any interesting requests and then jump to the real instruction 15024 * handler. Note that the call to dvmCheckInst is done as a tail call. 15025 */ 15026 adrl lr, dvmAsmInstructionStart + (92 * 64) 15027 mov r0, rPC @ arg0 15028 mov r1, rSELF @ arg1 15029 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15030 15031/* ------------------------------ */ 15032 .balign 64 15033.L_ALT_OP_IPUT_BYTE: /* 0x5d */ 15034/* File: armv5te/alt_stub.S */ 15035/* 15036 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15037 * any interesting requests and then jump to the real instruction 15038 * handler. Note that the call to dvmCheckInst is done as a tail call. 15039 */ 15040 adrl lr, dvmAsmInstructionStart + (93 * 64) 15041 mov r0, rPC @ arg0 15042 mov r1, rSELF @ arg1 15043 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15044 15045/* ------------------------------ */ 15046 .balign 64 15047.L_ALT_OP_IPUT_CHAR: /* 0x5e */ 15048/* File: armv5te/alt_stub.S */ 15049/* 15050 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15051 * any interesting requests and then jump to the real instruction 15052 * handler. Note that the call to dvmCheckInst is done as a tail call. 15053 */ 15054 adrl lr, dvmAsmInstructionStart + (94 * 64) 15055 mov r0, rPC @ arg0 15056 mov r1, rSELF @ arg1 15057 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15058 15059/* ------------------------------ */ 15060 .balign 64 15061.L_ALT_OP_IPUT_SHORT: /* 0x5f */ 15062/* File: armv5te/alt_stub.S */ 15063/* 15064 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15065 * any interesting requests and then jump to the real instruction 15066 * handler. Note that the call to dvmCheckInst is done as a tail call. 15067 */ 15068 adrl lr, dvmAsmInstructionStart + (95 * 64) 15069 mov r0, rPC @ arg0 15070 mov r1, rSELF @ arg1 15071 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15072 15073/* ------------------------------ */ 15074 .balign 64 15075.L_ALT_OP_SGET: /* 0x60 */ 15076/* File: armv5te/alt_stub.S */ 15077/* 15078 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15079 * any interesting requests and then jump to the real instruction 15080 * handler. Note that the call to dvmCheckInst is done as a tail call. 15081 */ 15082 adrl lr, dvmAsmInstructionStart + (96 * 64) 15083 mov r0, rPC @ arg0 15084 mov r1, rSELF @ arg1 15085 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15086 15087/* ------------------------------ */ 15088 .balign 64 15089.L_ALT_OP_SGET_WIDE: /* 0x61 */ 15090/* File: armv5te/alt_stub.S */ 15091/* 15092 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15093 * any interesting requests and then jump to the real instruction 15094 * handler. Note that the call to dvmCheckInst is done as a tail call. 15095 */ 15096 adrl lr, dvmAsmInstructionStart + (97 * 64) 15097 mov r0, rPC @ arg0 15098 mov r1, rSELF @ arg1 15099 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15100 15101/* ------------------------------ */ 15102 .balign 64 15103.L_ALT_OP_SGET_OBJECT: /* 0x62 */ 15104/* File: armv5te/alt_stub.S */ 15105/* 15106 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15107 * any interesting requests and then jump to the real instruction 15108 * handler. Note that the call to dvmCheckInst is done as a tail call. 15109 */ 15110 adrl lr, dvmAsmInstructionStart + (98 * 64) 15111 mov r0, rPC @ arg0 15112 mov r1, rSELF @ arg1 15113 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15114 15115/* ------------------------------ */ 15116 .balign 64 15117.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */ 15118/* File: armv5te/alt_stub.S */ 15119/* 15120 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15121 * any interesting requests and then jump to the real instruction 15122 * handler. Note that the call to dvmCheckInst is done as a tail call. 15123 */ 15124 adrl lr, dvmAsmInstructionStart + (99 * 64) 15125 mov r0, rPC @ arg0 15126 mov r1, rSELF @ arg1 15127 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15128 15129/* ------------------------------ */ 15130 .balign 64 15131.L_ALT_OP_SGET_BYTE: /* 0x64 */ 15132/* File: armv5te/alt_stub.S */ 15133/* 15134 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15135 * any interesting requests and then jump to the real instruction 15136 * handler. Note that the call to dvmCheckInst is done as a tail call. 15137 */ 15138 adrl lr, dvmAsmInstructionStart + (100 * 64) 15139 mov r0, rPC @ arg0 15140 mov r1, rSELF @ arg1 15141 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15142 15143/* ------------------------------ */ 15144 .balign 64 15145.L_ALT_OP_SGET_CHAR: /* 0x65 */ 15146/* File: armv5te/alt_stub.S */ 15147/* 15148 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15149 * any interesting requests and then jump to the real instruction 15150 * handler. Note that the call to dvmCheckInst is done as a tail call. 15151 */ 15152 adrl lr, dvmAsmInstructionStart + (101 * 64) 15153 mov r0, rPC @ arg0 15154 mov r1, rSELF @ arg1 15155 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15156 15157/* ------------------------------ */ 15158 .balign 64 15159.L_ALT_OP_SGET_SHORT: /* 0x66 */ 15160/* File: armv5te/alt_stub.S */ 15161/* 15162 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15163 * any interesting requests and then jump to the real instruction 15164 * handler. Note that the call to dvmCheckInst is done as a tail call. 15165 */ 15166 adrl lr, dvmAsmInstructionStart + (102 * 64) 15167 mov r0, rPC @ arg0 15168 mov r1, rSELF @ arg1 15169 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15170 15171/* ------------------------------ */ 15172 .balign 64 15173.L_ALT_OP_SPUT: /* 0x67 */ 15174/* File: armv5te/alt_stub.S */ 15175/* 15176 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15177 * any interesting requests and then jump to the real instruction 15178 * handler. Note that the call to dvmCheckInst is done as a tail call. 15179 */ 15180 adrl lr, dvmAsmInstructionStart + (103 * 64) 15181 mov r0, rPC @ arg0 15182 mov r1, rSELF @ arg1 15183 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15184 15185/* ------------------------------ */ 15186 .balign 64 15187.L_ALT_OP_SPUT_WIDE: /* 0x68 */ 15188/* File: armv5te/alt_stub.S */ 15189/* 15190 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15191 * any interesting requests and then jump to the real instruction 15192 * handler. Note that the call to dvmCheckInst is done as a tail call. 15193 */ 15194 adrl lr, dvmAsmInstructionStart + (104 * 64) 15195 mov r0, rPC @ arg0 15196 mov r1, rSELF @ arg1 15197 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15198 15199/* ------------------------------ */ 15200 .balign 64 15201.L_ALT_OP_SPUT_OBJECT: /* 0x69 */ 15202/* File: armv5te/alt_stub.S */ 15203/* 15204 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15205 * any interesting requests and then jump to the real instruction 15206 * handler. Note that the call to dvmCheckInst is done as a tail call. 15207 */ 15208 adrl lr, dvmAsmInstructionStart + (105 * 64) 15209 mov r0, rPC @ arg0 15210 mov r1, rSELF @ arg1 15211 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15212 15213/* ------------------------------ */ 15214 .balign 64 15215.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */ 15216/* File: armv5te/alt_stub.S */ 15217/* 15218 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15219 * any interesting requests and then jump to the real instruction 15220 * handler. Note that the call to dvmCheckInst is done as a tail call. 15221 */ 15222 adrl lr, dvmAsmInstructionStart + (106 * 64) 15223 mov r0, rPC @ arg0 15224 mov r1, rSELF @ arg1 15225 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15226 15227/* ------------------------------ */ 15228 .balign 64 15229.L_ALT_OP_SPUT_BYTE: /* 0x6b */ 15230/* File: armv5te/alt_stub.S */ 15231/* 15232 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15233 * any interesting requests and then jump to the real instruction 15234 * handler. Note that the call to dvmCheckInst is done as a tail call. 15235 */ 15236 adrl lr, dvmAsmInstructionStart + (107 * 64) 15237 mov r0, rPC @ arg0 15238 mov r1, rSELF @ arg1 15239 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15240 15241/* ------------------------------ */ 15242 .balign 64 15243.L_ALT_OP_SPUT_CHAR: /* 0x6c */ 15244/* File: armv5te/alt_stub.S */ 15245/* 15246 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15247 * any interesting requests and then jump to the real instruction 15248 * handler. Note that the call to dvmCheckInst is done as a tail call. 15249 */ 15250 adrl lr, dvmAsmInstructionStart + (108 * 64) 15251 mov r0, rPC @ arg0 15252 mov r1, rSELF @ arg1 15253 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15254 15255/* ------------------------------ */ 15256 .balign 64 15257.L_ALT_OP_SPUT_SHORT: /* 0x6d */ 15258/* File: armv5te/alt_stub.S */ 15259/* 15260 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15261 * any interesting requests and then jump to the real instruction 15262 * handler. Note that the call to dvmCheckInst is done as a tail call. 15263 */ 15264 adrl lr, dvmAsmInstructionStart + (109 * 64) 15265 mov r0, rPC @ arg0 15266 mov r1, rSELF @ arg1 15267 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15268 15269/* ------------------------------ */ 15270 .balign 64 15271.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */ 15272/* File: armv5te/alt_stub.S */ 15273/* 15274 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15275 * any interesting requests and then jump to the real instruction 15276 * handler. Note that the call to dvmCheckInst is done as a tail call. 15277 */ 15278 adrl lr, dvmAsmInstructionStart + (110 * 64) 15279 mov r0, rPC @ arg0 15280 mov r1, rSELF @ arg1 15281 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15282 15283/* ------------------------------ */ 15284 .balign 64 15285.L_ALT_OP_INVOKE_SUPER: /* 0x6f */ 15286/* File: armv5te/alt_stub.S */ 15287/* 15288 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15289 * any interesting requests and then jump to the real instruction 15290 * handler. Note that the call to dvmCheckInst is done as a tail call. 15291 */ 15292 adrl lr, dvmAsmInstructionStart + (111 * 64) 15293 mov r0, rPC @ arg0 15294 mov r1, rSELF @ arg1 15295 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15296 15297/* ------------------------------ */ 15298 .balign 64 15299.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */ 15300/* File: armv5te/alt_stub.S */ 15301/* 15302 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15303 * any interesting requests and then jump to the real instruction 15304 * handler. Note that the call to dvmCheckInst is done as a tail call. 15305 */ 15306 adrl lr, dvmAsmInstructionStart + (112 * 64) 15307 mov r0, rPC @ arg0 15308 mov r1, rSELF @ arg1 15309 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15310 15311/* ------------------------------ */ 15312 .balign 64 15313.L_ALT_OP_INVOKE_STATIC: /* 0x71 */ 15314/* File: armv5te/alt_stub.S */ 15315/* 15316 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15317 * any interesting requests and then jump to the real instruction 15318 * handler. Note that the call to dvmCheckInst is done as a tail call. 15319 */ 15320 adrl lr, dvmAsmInstructionStart + (113 * 64) 15321 mov r0, rPC @ arg0 15322 mov r1, rSELF @ arg1 15323 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15324 15325/* ------------------------------ */ 15326 .balign 64 15327.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */ 15328/* File: armv5te/alt_stub.S */ 15329/* 15330 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15331 * any interesting requests and then jump to the real instruction 15332 * handler. Note that the call to dvmCheckInst is done as a tail call. 15333 */ 15334 adrl lr, dvmAsmInstructionStart + (114 * 64) 15335 mov r0, rPC @ arg0 15336 mov r1, rSELF @ arg1 15337 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15338 15339/* ------------------------------ */ 15340 .balign 64 15341.L_ALT_OP_UNUSED_73: /* 0x73 */ 15342/* File: armv5te/alt_stub.S */ 15343/* 15344 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15345 * any interesting requests and then jump to the real instruction 15346 * handler. Note that the call to dvmCheckInst is done as a tail call. 15347 */ 15348 adrl lr, dvmAsmInstructionStart + (115 * 64) 15349 mov r0, rPC @ arg0 15350 mov r1, rSELF @ arg1 15351 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15352 15353/* ------------------------------ */ 15354 .balign 64 15355.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 15356/* File: armv5te/alt_stub.S */ 15357/* 15358 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15359 * any interesting requests and then jump to the real instruction 15360 * handler. Note that the call to dvmCheckInst is done as a tail call. 15361 */ 15362 adrl lr, dvmAsmInstructionStart + (116 * 64) 15363 mov r0, rPC @ arg0 15364 mov r1, rSELF @ arg1 15365 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15366 15367/* ------------------------------ */ 15368 .balign 64 15369.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 15370/* File: armv5te/alt_stub.S */ 15371/* 15372 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15373 * any interesting requests and then jump to the real instruction 15374 * handler. Note that the call to dvmCheckInst is done as a tail call. 15375 */ 15376 adrl lr, dvmAsmInstructionStart + (117 * 64) 15377 mov r0, rPC @ arg0 15378 mov r1, rSELF @ arg1 15379 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15380 15381/* ------------------------------ */ 15382 .balign 64 15383.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 15384/* File: armv5te/alt_stub.S */ 15385/* 15386 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15387 * any interesting requests and then jump to the real instruction 15388 * handler. Note that the call to dvmCheckInst is done as a tail call. 15389 */ 15390 adrl lr, dvmAsmInstructionStart + (118 * 64) 15391 mov r0, rPC @ arg0 15392 mov r1, rSELF @ arg1 15393 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15394 15395/* ------------------------------ */ 15396 .balign 64 15397.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 15398/* File: armv5te/alt_stub.S */ 15399/* 15400 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15401 * any interesting requests and then jump to the real instruction 15402 * handler. Note that the call to dvmCheckInst is done as a tail call. 15403 */ 15404 adrl lr, dvmAsmInstructionStart + (119 * 64) 15405 mov r0, rPC @ arg0 15406 mov r1, rSELF @ arg1 15407 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15408 15409/* ------------------------------ */ 15410 .balign 64 15411.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 15412/* File: armv5te/alt_stub.S */ 15413/* 15414 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15415 * any interesting requests and then jump to the real instruction 15416 * handler. Note that the call to dvmCheckInst is done as a tail call. 15417 */ 15418 adrl lr, dvmAsmInstructionStart + (120 * 64) 15419 mov r0, rPC @ arg0 15420 mov r1, rSELF @ arg1 15421 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15422 15423/* ------------------------------ */ 15424 .balign 64 15425.L_ALT_OP_UNUSED_79: /* 0x79 */ 15426/* File: armv5te/alt_stub.S */ 15427/* 15428 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15429 * any interesting requests and then jump to the real instruction 15430 * handler. Note that the call to dvmCheckInst is done as a tail call. 15431 */ 15432 adrl lr, dvmAsmInstructionStart + (121 * 64) 15433 mov r0, rPC @ arg0 15434 mov r1, rSELF @ arg1 15435 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15436 15437/* ------------------------------ */ 15438 .balign 64 15439.L_ALT_OP_UNUSED_7A: /* 0x7a */ 15440/* File: armv5te/alt_stub.S */ 15441/* 15442 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15443 * any interesting requests and then jump to the real instruction 15444 * handler. Note that the call to dvmCheckInst is done as a tail call. 15445 */ 15446 adrl lr, dvmAsmInstructionStart + (122 * 64) 15447 mov r0, rPC @ arg0 15448 mov r1, rSELF @ arg1 15449 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15450 15451/* ------------------------------ */ 15452 .balign 64 15453.L_ALT_OP_NEG_INT: /* 0x7b */ 15454/* File: armv5te/alt_stub.S */ 15455/* 15456 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15457 * any interesting requests and then jump to the real instruction 15458 * handler. Note that the call to dvmCheckInst is done as a tail call. 15459 */ 15460 adrl lr, dvmAsmInstructionStart + (123 * 64) 15461 mov r0, rPC @ arg0 15462 mov r1, rSELF @ arg1 15463 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15464 15465/* ------------------------------ */ 15466 .balign 64 15467.L_ALT_OP_NOT_INT: /* 0x7c */ 15468/* File: armv5te/alt_stub.S */ 15469/* 15470 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15471 * any interesting requests and then jump to the real instruction 15472 * handler. Note that the call to dvmCheckInst is done as a tail call. 15473 */ 15474 adrl lr, dvmAsmInstructionStart + (124 * 64) 15475 mov r0, rPC @ arg0 15476 mov r1, rSELF @ arg1 15477 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15478 15479/* ------------------------------ */ 15480 .balign 64 15481.L_ALT_OP_NEG_LONG: /* 0x7d */ 15482/* File: armv5te/alt_stub.S */ 15483/* 15484 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15485 * any interesting requests and then jump to the real instruction 15486 * handler. Note that the call to dvmCheckInst is done as a tail call. 15487 */ 15488 adrl lr, dvmAsmInstructionStart + (125 * 64) 15489 mov r0, rPC @ arg0 15490 mov r1, rSELF @ arg1 15491 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15492 15493/* ------------------------------ */ 15494 .balign 64 15495.L_ALT_OP_NOT_LONG: /* 0x7e */ 15496/* File: armv5te/alt_stub.S */ 15497/* 15498 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15499 * any interesting requests and then jump to the real instruction 15500 * handler. Note that the call to dvmCheckInst is done as a tail call. 15501 */ 15502 adrl lr, dvmAsmInstructionStart + (126 * 64) 15503 mov r0, rPC @ arg0 15504 mov r1, rSELF @ arg1 15505 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15506 15507/* ------------------------------ */ 15508 .balign 64 15509.L_ALT_OP_NEG_FLOAT: /* 0x7f */ 15510/* File: armv5te/alt_stub.S */ 15511/* 15512 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15513 * any interesting requests and then jump to the real instruction 15514 * handler. Note that the call to dvmCheckInst is done as a tail call. 15515 */ 15516 adrl lr, dvmAsmInstructionStart + (127 * 64) 15517 mov r0, rPC @ arg0 15518 mov r1, rSELF @ arg1 15519 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15520 15521/* ------------------------------ */ 15522 .balign 64 15523.L_ALT_OP_NEG_DOUBLE: /* 0x80 */ 15524/* File: armv5te/alt_stub.S */ 15525/* 15526 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15527 * any interesting requests and then jump to the real instruction 15528 * handler. Note that the call to dvmCheckInst is done as a tail call. 15529 */ 15530 adrl lr, dvmAsmInstructionStart + (128 * 64) 15531 mov r0, rPC @ arg0 15532 mov r1, rSELF @ arg1 15533 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15534 15535/* ------------------------------ */ 15536 .balign 64 15537.L_ALT_OP_INT_TO_LONG: /* 0x81 */ 15538/* File: armv5te/alt_stub.S */ 15539/* 15540 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15541 * any interesting requests and then jump to the real instruction 15542 * handler. Note that the call to dvmCheckInst is done as a tail call. 15543 */ 15544 adrl lr, dvmAsmInstructionStart + (129 * 64) 15545 mov r0, rPC @ arg0 15546 mov r1, rSELF @ arg1 15547 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15548 15549/* ------------------------------ */ 15550 .balign 64 15551.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */ 15552/* File: armv5te/alt_stub.S */ 15553/* 15554 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15555 * any interesting requests and then jump to the real instruction 15556 * handler. Note that the call to dvmCheckInst is done as a tail call. 15557 */ 15558 adrl lr, dvmAsmInstructionStart + (130 * 64) 15559 mov r0, rPC @ arg0 15560 mov r1, rSELF @ arg1 15561 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15562 15563/* ------------------------------ */ 15564 .balign 64 15565.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */ 15566/* File: armv5te/alt_stub.S */ 15567/* 15568 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15569 * any interesting requests and then jump to the real instruction 15570 * handler. Note that the call to dvmCheckInst is done as a tail call. 15571 */ 15572 adrl lr, dvmAsmInstructionStart + (131 * 64) 15573 mov r0, rPC @ arg0 15574 mov r1, rSELF @ arg1 15575 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15576 15577/* ------------------------------ */ 15578 .balign 64 15579.L_ALT_OP_LONG_TO_INT: /* 0x84 */ 15580/* File: armv5te/alt_stub.S */ 15581/* 15582 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15583 * any interesting requests and then jump to the real instruction 15584 * handler. Note that the call to dvmCheckInst is done as a tail call. 15585 */ 15586 adrl lr, dvmAsmInstructionStart + (132 * 64) 15587 mov r0, rPC @ arg0 15588 mov r1, rSELF @ arg1 15589 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15590 15591/* ------------------------------ */ 15592 .balign 64 15593.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */ 15594/* File: armv5te/alt_stub.S */ 15595/* 15596 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15597 * any interesting requests and then jump to the real instruction 15598 * handler. Note that the call to dvmCheckInst is done as a tail call. 15599 */ 15600 adrl lr, dvmAsmInstructionStart + (133 * 64) 15601 mov r0, rPC @ arg0 15602 mov r1, rSELF @ arg1 15603 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15604 15605/* ------------------------------ */ 15606 .balign 64 15607.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */ 15608/* File: armv5te/alt_stub.S */ 15609/* 15610 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15611 * any interesting requests and then jump to the real instruction 15612 * handler. Note that the call to dvmCheckInst is done as a tail call. 15613 */ 15614 adrl lr, dvmAsmInstructionStart + (134 * 64) 15615 mov r0, rPC @ arg0 15616 mov r1, rSELF @ arg1 15617 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15618 15619/* ------------------------------ */ 15620 .balign 64 15621.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */ 15622/* File: armv5te/alt_stub.S */ 15623/* 15624 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15625 * any interesting requests and then jump to the real instruction 15626 * handler. Note that the call to dvmCheckInst is done as a tail call. 15627 */ 15628 adrl lr, dvmAsmInstructionStart + (135 * 64) 15629 mov r0, rPC @ arg0 15630 mov r1, rSELF @ arg1 15631 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15632 15633/* ------------------------------ */ 15634 .balign 64 15635.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */ 15636/* File: armv5te/alt_stub.S */ 15637/* 15638 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15639 * any interesting requests and then jump to the real instruction 15640 * handler. Note that the call to dvmCheckInst is done as a tail call. 15641 */ 15642 adrl lr, dvmAsmInstructionStart + (136 * 64) 15643 mov r0, rPC @ arg0 15644 mov r1, rSELF @ arg1 15645 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15646 15647/* ------------------------------ */ 15648 .balign 64 15649.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 15650/* File: armv5te/alt_stub.S */ 15651/* 15652 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15653 * any interesting requests and then jump to the real instruction 15654 * handler. Note that the call to dvmCheckInst is done as a tail call. 15655 */ 15656 adrl lr, dvmAsmInstructionStart + (137 * 64) 15657 mov r0, rPC @ arg0 15658 mov r1, rSELF @ arg1 15659 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15660 15661/* ------------------------------ */ 15662 .balign 64 15663.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */ 15664/* File: armv5te/alt_stub.S */ 15665/* 15666 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15667 * any interesting requests and then jump to the real instruction 15668 * handler. Note that the call to dvmCheckInst is done as a tail call. 15669 */ 15670 adrl lr, dvmAsmInstructionStart + (138 * 64) 15671 mov r0, rPC @ arg0 15672 mov r1, rSELF @ arg1 15673 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15674 15675/* ------------------------------ */ 15676 .balign 64 15677.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */ 15678/* File: armv5te/alt_stub.S */ 15679/* 15680 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15681 * any interesting requests and then jump to the real instruction 15682 * handler. Note that the call to dvmCheckInst is done as a tail call. 15683 */ 15684 adrl lr, dvmAsmInstructionStart + (139 * 64) 15685 mov r0, rPC @ arg0 15686 mov r1, rSELF @ arg1 15687 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15688 15689/* ------------------------------ */ 15690 .balign 64 15691.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 15692/* File: armv5te/alt_stub.S */ 15693/* 15694 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15695 * any interesting requests and then jump to the real instruction 15696 * handler. Note that the call to dvmCheckInst is done as a tail call. 15697 */ 15698 adrl lr, dvmAsmInstructionStart + (140 * 64) 15699 mov r0, rPC @ arg0 15700 mov r1, rSELF @ arg1 15701 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15702 15703/* ------------------------------ */ 15704 .balign 64 15705.L_ALT_OP_INT_TO_BYTE: /* 0x8d */ 15706/* File: armv5te/alt_stub.S */ 15707/* 15708 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15709 * any interesting requests and then jump to the real instruction 15710 * handler. Note that the call to dvmCheckInst is done as a tail call. 15711 */ 15712 adrl lr, dvmAsmInstructionStart + (141 * 64) 15713 mov r0, rPC @ arg0 15714 mov r1, rSELF @ arg1 15715 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15716 15717/* ------------------------------ */ 15718 .balign 64 15719.L_ALT_OP_INT_TO_CHAR: /* 0x8e */ 15720/* File: armv5te/alt_stub.S */ 15721/* 15722 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15723 * any interesting requests and then jump to the real instruction 15724 * handler. Note that the call to dvmCheckInst is done as a tail call. 15725 */ 15726 adrl lr, dvmAsmInstructionStart + (142 * 64) 15727 mov r0, rPC @ arg0 15728 mov r1, rSELF @ arg1 15729 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15730 15731/* ------------------------------ */ 15732 .balign 64 15733.L_ALT_OP_INT_TO_SHORT: /* 0x8f */ 15734/* File: armv5te/alt_stub.S */ 15735/* 15736 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15737 * any interesting requests and then jump to the real instruction 15738 * handler. Note that the call to dvmCheckInst is done as a tail call. 15739 */ 15740 adrl lr, dvmAsmInstructionStart + (143 * 64) 15741 mov r0, rPC @ arg0 15742 mov r1, rSELF @ arg1 15743 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15744 15745/* ------------------------------ */ 15746 .balign 64 15747.L_ALT_OP_ADD_INT: /* 0x90 */ 15748/* File: armv5te/alt_stub.S */ 15749/* 15750 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15751 * any interesting requests and then jump to the real instruction 15752 * handler. Note that the call to dvmCheckInst is done as a tail call. 15753 */ 15754 adrl lr, dvmAsmInstructionStart + (144 * 64) 15755 mov r0, rPC @ arg0 15756 mov r1, rSELF @ arg1 15757 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15758 15759/* ------------------------------ */ 15760 .balign 64 15761.L_ALT_OP_SUB_INT: /* 0x91 */ 15762/* File: armv5te/alt_stub.S */ 15763/* 15764 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15765 * any interesting requests and then jump to the real instruction 15766 * handler. Note that the call to dvmCheckInst is done as a tail call. 15767 */ 15768 adrl lr, dvmAsmInstructionStart + (145 * 64) 15769 mov r0, rPC @ arg0 15770 mov r1, rSELF @ arg1 15771 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15772 15773/* ------------------------------ */ 15774 .balign 64 15775.L_ALT_OP_MUL_INT: /* 0x92 */ 15776/* File: armv5te/alt_stub.S */ 15777/* 15778 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15779 * any interesting requests and then jump to the real instruction 15780 * handler. Note that the call to dvmCheckInst is done as a tail call. 15781 */ 15782 adrl lr, dvmAsmInstructionStart + (146 * 64) 15783 mov r0, rPC @ arg0 15784 mov r1, rSELF @ arg1 15785 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15786 15787/* ------------------------------ */ 15788 .balign 64 15789.L_ALT_OP_DIV_INT: /* 0x93 */ 15790/* File: armv5te/alt_stub.S */ 15791/* 15792 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15793 * any interesting requests and then jump to the real instruction 15794 * handler. Note that the call to dvmCheckInst is done as a tail call. 15795 */ 15796 adrl lr, dvmAsmInstructionStart + (147 * 64) 15797 mov r0, rPC @ arg0 15798 mov r1, rSELF @ arg1 15799 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15800 15801/* ------------------------------ */ 15802 .balign 64 15803.L_ALT_OP_REM_INT: /* 0x94 */ 15804/* File: armv5te/alt_stub.S */ 15805/* 15806 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15807 * any interesting requests and then jump to the real instruction 15808 * handler. Note that the call to dvmCheckInst is done as a tail call. 15809 */ 15810 adrl lr, dvmAsmInstructionStart + (148 * 64) 15811 mov r0, rPC @ arg0 15812 mov r1, rSELF @ arg1 15813 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15814 15815/* ------------------------------ */ 15816 .balign 64 15817.L_ALT_OP_AND_INT: /* 0x95 */ 15818/* File: armv5te/alt_stub.S */ 15819/* 15820 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15821 * any interesting requests and then jump to the real instruction 15822 * handler. Note that the call to dvmCheckInst is done as a tail call. 15823 */ 15824 adrl lr, dvmAsmInstructionStart + (149 * 64) 15825 mov r0, rPC @ arg0 15826 mov r1, rSELF @ arg1 15827 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15828 15829/* ------------------------------ */ 15830 .balign 64 15831.L_ALT_OP_OR_INT: /* 0x96 */ 15832/* File: armv5te/alt_stub.S */ 15833/* 15834 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15835 * any interesting requests and then jump to the real instruction 15836 * handler. Note that the call to dvmCheckInst is done as a tail call. 15837 */ 15838 adrl lr, dvmAsmInstructionStart + (150 * 64) 15839 mov r0, rPC @ arg0 15840 mov r1, rSELF @ arg1 15841 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15842 15843/* ------------------------------ */ 15844 .balign 64 15845.L_ALT_OP_XOR_INT: /* 0x97 */ 15846/* File: armv5te/alt_stub.S */ 15847/* 15848 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15849 * any interesting requests and then jump to the real instruction 15850 * handler. Note that the call to dvmCheckInst is done as a tail call. 15851 */ 15852 adrl lr, dvmAsmInstructionStart + (151 * 64) 15853 mov r0, rPC @ arg0 15854 mov r1, rSELF @ arg1 15855 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15856 15857/* ------------------------------ */ 15858 .balign 64 15859.L_ALT_OP_SHL_INT: /* 0x98 */ 15860/* File: armv5te/alt_stub.S */ 15861/* 15862 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15863 * any interesting requests and then jump to the real instruction 15864 * handler. Note that the call to dvmCheckInst is done as a tail call. 15865 */ 15866 adrl lr, dvmAsmInstructionStart + (152 * 64) 15867 mov r0, rPC @ arg0 15868 mov r1, rSELF @ arg1 15869 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15870 15871/* ------------------------------ */ 15872 .balign 64 15873.L_ALT_OP_SHR_INT: /* 0x99 */ 15874/* File: armv5te/alt_stub.S */ 15875/* 15876 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15877 * any interesting requests and then jump to the real instruction 15878 * handler. Note that the call to dvmCheckInst is done as a tail call. 15879 */ 15880 adrl lr, dvmAsmInstructionStart + (153 * 64) 15881 mov r0, rPC @ arg0 15882 mov r1, rSELF @ arg1 15883 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15884 15885/* ------------------------------ */ 15886 .balign 64 15887.L_ALT_OP_USHR_INT: /* 0x9a */ 15888/* File: armv5te/alt_stub.S */ 15889/* 15890 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15891 * any interesting requests and then jump to the real instruction 15892 * handler. Note that the call to dvmCheckInst is done as a tail call. 15893 */ 15894 adrl lr, dvmAsmInstructionStart + (154 * 64) 15895 mov r0, rPC @ arg0 15896 mov r1, rSELF @ arg1 15897 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15898 15899/* ------------------------------ */ 15900 .balign 64 15901.L_ALT_OP_ADD_LONG: /* 0x9b */ 15902/* File: armv5te/alt_stub.S */ 15903/* 15904 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15905 * any interesting requests and then jump to the real instruction 15906 * handler. Note that the call to dvmCheckInst is done as a tail call. 15907 */ 15908 adrl lr, dvmAsmInstructionStart + (155 * 64) 15909 mov r0, rPC @ arg0 15910 mov r1, rSELF @ arg1 15911 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15912 15913/* ------------------------------ */ 15914 .balign 64 15915.L_ALT_OP_SUB_LONG: /* 0x9c */ 15916/* File: armv5te/alt_stub.S */ 15917/* 15918 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15919 * any interesting requests and then jump to the real instruction 15920 * handler. Note that the call to dvmCheckInst is done as a tail call. 15921 */ 15922 adrl lr, dvmAsmInstructionStart + (156 * 64) 15923 mov r0, rPC @ arg0 15924 mov r1, rSELF @ arg1 15925 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15926 15927/* ------------------------------ */ 15928 .balign 64 15929.L_ALT_OP_MUL_LONG: /* 0x9d */ 15930/* File: armv5te/alt_stub.S */ 15931/* 15932 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15933 * any interesting requests and then jump to the real instruction 15934 * handler. Note that the call to dvmCheckInst is done as a tail call. 15935 */ 15936 adrl lr, dvmAsmInstructionStart + (157 * 64) 15937 mov r0, rPC @ arg0 15938 mov r1, rSELF @ arg1 15939 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15940 15941/* ------------------------------ */ 15942 .balign 64 15943.L_ALT_OP_DIV_LONG: /* 0x9e */ 15944/* File: armv5te/alt_stub.S */ 15945/* 15946 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15947 * any interesting requests and then jump to the real instruction 15948 * handler. Note that the call to dvmCheckInst is done as a tail call. 15949 */ 15950 adrl lr, dvmAsmInstructionStart + (158 * 64) 15951 mov r0, rPC @ arg0 15952 mov r1, rSELF @ arg1 15953 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15954 15955/* ------------------------------ */ 15956 .balign 64 15957.L_ALT_OP_REM_LONG: /* 0x9f */ 15958/* File: armv5te/alt_stub.S */ 15959/* 15960 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15961 * any interesting requests and then jump to the real instruction 15962 * handler. Note that the call to dvmCheckInst is done as a tail call. 15963 */ 15964 adrl lr, dvmAsmInstructionStart + (159 * 64) 15965 mov r0, rPC @ arg0 15966 mov r1, rSELF @ arg1 15967 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15968 15969/* ------------------------------ */ 15970 .balign 64 15971.L_ALT_OP_AND_LONG: /* 0xa0 */ 15972/* File: armv5te/alt_stub.S */ 15973/* 15974 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15975 * any interesting requests and then jump to the real instruction 15976 * handler. Note that the call to dvmCheckInst is done as a tail call. 15977 */ 15978 adrl lr, dvmAsmInstructionStart + (160 * 64) 15979 mov r0, rPC @ arg0 15980 mov r1, rSELF @ arg1 15981 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15982 15983/* ------------------------------ */ 15984 .balign 64 15985.L_ALT_OP_OR_LONG: /* 0xa1 */ 15986/* File: armv5te/alt_stub.S */ 15987/* 15988 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15989 * any interesting requests and then jump to the real instruction 15990 * handler. Note that the call to dvmCheckInst is done as a tail call. 15991 */ 15992 adrl lr, dvmAsmInstructionStart + (161 * 64) 15993 mov r0, rPC @ arg0 15994 mov r1, rSELF @ arg1 15995 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15996 15997/* ------------------------------ */ 15998 .balign 64 15999.L_ALT_OP_XOR_LONG: /* 0xa2 */ 16000/* File: armv5te/alt_stub.S */ 16001/* 16002 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16003 * any interesting requests and then jump to the real instruction 16004 * handler. Note that the call to dvmCheckInst is done as a tail call. 16005 */ 16006 adrl lr, dvmAsmInstructionStart + (162 * 64) 16007 mov r0, rPC @ arg0 16008 mov r1, rSELF @ arg1 16009 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16010 16011/* ------------------------------ */ 16012 .balign 64 16013.L_ALT_OP_SHL_LONG: /* 0xa3 */ 16014/* File: armv5te/alt_stub.S */ 16015/* 16016 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16017 * any interesting requests and then jump to the real instruction 16018 * handler. Note that the call to dvmCheckInst is done as a tail call. 16019 */ 16020 adrl lr, dvmAsmInstructionStart + (163 * 64) 16021 mov r0, rPC @ arg0 16022 mov r1, rSELF @ arg1 16023 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16024 16025/* ------------------------------ */ 16026 .balign 64 16027.L_ALT_OP_SHR_LONG: /* 0xa4 */ 16028/* File: armv5te/alt_stub.S */ 16029/* 16030 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16031 * any interesting requests and then jump to the real instruction 16032 * handler. Note that the call to dvmCheckInst is done as a tail call. 16033 */ 16034 adrl lr, dvmAsmInstructionStart + (164 * 64) 16035 mov r0, rPC @ arg0 16036 mov r1, rSELF @ arg1 16037 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16038 16039/* ------------------------------ */ 16040 .balign 64 16041.L_ALT_OP_USHR_LONG: /* 0xa5 */ 16042/* File: armv5te/alt_stub.S */ 16043/* 16044 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16045 * any interesting requests and then jump to the real instruction 16046 * handler. Note that the call to dvmCheckInst is done as a tail call. 16047 */ 16048 adrl lr, dvmAsmInstructionStart + (165 * 64) 16049 mov r0, rPC @ arg0 16050 mov r1, rSELF @ arg1 16051 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16052 16053/* ------------------------------ */ 16054 .balign 64 16055.L_ALT_OP_ADD_FLOAT: /* 0xa6 */ 16056/* File: armv5te/alt_stub.S */ 16057/* 16058 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16059 * any interesting requests and then jump to the real instruction 16060 * handler. Note that the call to dvmCheckInst is done as a tail call. 16061 */ 16062 adrl lr, dvmAsmInstructionStart + (166 * 64) 16063 mov r0, rPC @ arg0 16064 mov r1, rSELF @ arg1 16065 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16066 16067/* ------------------------------ */ 16068 .balign 64 16069.L_ALT_OP_SUB_FLOAT: /* 0xa7 */ 16070/* File: armv5te/alt_stub.S */ 16071/* 16072 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16073 * any interesting requests and then jump to the real instruction 16074 * handler. Note that the call to dvmCheckInst is done as a tail call. 16075 */ 16076 adrl lr, dvmAsmInstructionStart + (167 * 64) 16077 mov r0, rPC @ arg0 16078 mov r1, rSELF @ arg1 16079 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16080 16081/* ------------------------------ */ 16082 .balign 64 16083.L_ALT_OP_MUL_FLOAT: /* 0xa8 */ 16084/* File: armv5te/alt_stub.S */ 16085/* 16086 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16087 * any interesting requests and then jump to the real instruction 16088 * handler. Note that the call to dvmCheckInst is done as a tail call. 16089 */ 16090 adrl lr, dvmAsmInstructionStart + (168 * 64) 16091 mov r0, rPC @ arg0 16092 mov r1, rSELF @ arg1 16093 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16094 16095/* ------------------------------ */ 16096 .balign 64 16097.L_ALT_OP_DIV_FLOAT: /* 0xa9 */ 16098/* File: armv5te/alt_stub.S */ 16099/* 16100 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16101 * any interesting requests and then jump to the real instruction 16102 * handler. Note that the call to dvmCheckInst is done as a tail call. 16103 */ 16104 adrl lr, dvmAsmInstructionStart + (169 * 64) 16105 mov r0, rPC @ arg0 16106 mov r1, rSELF @ arg1 16107 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16108 16109/* ------------------------------ */ 16110 .balign 64 16111.L_ALT_OP_REM_FLOAT: /* 0xaa */ 16112/* File: armv5te/alt_stub.S */ 16113/* 16114 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16115 * any interesting requests and then jump to the real instruction 16116 * handler. Note that the call to dvmCheckInst is done as a tail call. 16117 */ 16118 adrl lr, dvmAsmInstructionStart + (170 * 64) 16119 mov r0, rPC @ arg0 16120 mov r1, rSELF @ arg1 16121 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16122 16123/* ------------------------------ */ 16124 .balign 64 16125.L_ALT_OP_ADD_DOUBLE: /* 0xab */ 16126/* File: armv5te/alt_stub.S */ 16127/* 16128 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16129 * any interesting requests and then jump to the real instruction 16130 * handler. Note that the call to dvmCheckInst is done as a tail call. 16131 */ 16132 adrl lr, dvmAsmInstructionStart + (171 * 64) 16133 mov r0, rPC @ arg0 16134 mov r1, rSELF @ arg1 16135 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16136 16137/* ------------------------------ */ 16138 .balign 64 16139.L_ALT_OP_SUB_DOUBLE: /* 0xac */ 16140/* File: armv5te/alt_stub.S */ 16141/* 16142 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16143 * any interesting requests and then jump to the real instruction 16144 * handler. Note that the call to dvmCheckInst is done as a tail call. 16145 */ 16146 adrl lr, dvmAsmInstructionStart + (172 * 64) 16147 mov r0, rPC @ arg0 16148 mov r1, rSELF @ arg1 16149 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16150 16151/* ------------------------------ */ 16152 .balign 64 16153.L_ALT_OP_MUL_DOUBLE: /* 0xad */ 16154/* File: armv5te/alt_stub.S */ 16155/* 16156 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16157 * any interesting requests and then jump to the real instruction 16158 * handler. Note that the call to dvmCheckInst is done as a tail call. 16159 */ 16160 adrl lr, dvmAsmInstructionStart + (173 * 64) 16161 mov r0, rPC @ arg0 16162 mov r1, rSELF @ arg1 16163 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16164 16165/* ------------------------------ */ 16166 .balign 64 16167.L_ALT_OP_DIV_DOUBLE: /* 0xae */ 16168/* File: armv5te/alt_stub.S */ 16169/* 16170 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16171 * any interesting requests and then jump to the real instruction 16172 * handler. Note that the call to dvmCheckInst is done as a tail call. 16173 */ 16174 adrl lr, dvmAsmInstructionStart + (174 * 64) 16175 mov r0, rPC @ arg0 16176 mov r1, rSELF @ arg1 16177 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16178 16179/* ------------------------------ */ 16180 .balign 64 16181.L_ALT_OP_REM_DOUBLE: /* 0xaf */ 16182/* File: armv5te/alt_stub.S */ 16183/* 16184 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16185 * any interesting requests and then jump to the real instruction 16186 * handler. Note that the call to dvmCheckInst is done as a tail call. 16187 */ 16188 adrl lr, dvmAsmInstructionStart + (175 * 64) 16189 mov r0, rPC @ arg0 16190 mov r1, rSELF @ arg1 16191 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16192 16193/* ------------------------------ */ 16194 .balign 64 16195.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */ 16196/* File: armv5te/alt_stub.S */ 16197/* 16198 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16199 * any interesting requests and then jump to the real instruction 16200 * handler. Note that the call to dvmCheckInst is done as a tail call. 16201 */ 16202 adrl lr, dvmAsmInstructionStart + (176 * 64) 16203 mov r0, rPC @ arg0 16204 mov r1, rSELF @ arg1 16205 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16206 16207/* ------------------------------ */ 16208 .balign 64 16209.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */ 16210/* File: armv5te/alt_stub.S */ 16211/* 16212 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16213 * any interesting requests and then jump to the real instruction 16214 * handler. Note that the call to dvmCheckInst is done as a tail call. 16215 */ 16216 adrl lr, dvmAsmInstructionStart + (177 * 64) 16217 mov r0, rPC @ arg0 16218 mov r1, rSELF @ arg1 16219 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16220 16221/* ------------------------------ */ 16222 .balign 64 16223.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */ 16224/* File: armv5te/alt_stub.S */ 16225/* 16226 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16227 * any interesting requests and then jump to the real instruction 16228 * handler. Note that the call to dvmCheckInst is done as a tail call. 16229 */ 16230 adrl lr, dvmAsmInstructionStart + (178 * 64) 16231 mov r0, rPC @ arg0 16232 mov r1, rSELF @ arg1 16233 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16234 16235/* ------------------------------ */ 16236 .balign 64 16237.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */ 16238/* File: armv5te/alt_stub.S */ 16239/* 16240 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16241 * any interesting requests and then jump to the real instruction 16242 * handler. Note that the call to dvmCheckInst is done as a tail call. 16243 */ 16244 adrl lr, dvmAsmInstructionStart + (179 * 64) 16245 mov r0, rPC @ arg0 16246 mov r1, rSELF @ arg1 16247 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16248 16249/* ------------------------------ */ 16250 .balign 64 16251.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */ 16252/* File: armv5te/alt_stub.S */ 16253/* 16254 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16255 * any interesting requests and then jump to the real instruction 16256 * handler. Note that the call to dvmCheckInst is done as a tail call. 16257 */ 16258 adrl lr, dvmAsmInstructionStart + (180 * 64) 16259 mov r0, rPC @ arg0 16260 mov r1, rSELF @ arg1 16261 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16262 16263/* ------------------------------ */ 16264 .balign 64 16265.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */ 16266/* File: armv5te/alt_stub.S */ 16267/* 16268 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16269 * any interesting requests and then jump to the real instruction 16270 * handler. Note that the call to dvmCheckInst is done as a tail call. 16271 */ 16272 adrl lr, dvmAsmInstructionStart + (181 * 64) 16273 mov r0, rPC @ arg0 16274 mov r1, rSELF @ arg1 16275 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16276 16277/* ------------------------------ */ 16278 .balign 64 16279.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */ 16280/* File: armv5te/alt_stub.S */ 16281/* 16282 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16283 * any interesting requests and then jump to the real instruction 16284 * handler. Note that the call to dvmCheckInst is done as a tail call. 16285 */ 16286 adrl lr, dvmAsmInstructionStart + (182 * 64) 16287 mov r0, rPC @ arg0 16288 mov r1, rSELF @ arg1 16289 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16290 16291/* ------------------------------ */ 16292 .balign 64 16293.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */ 16294/* File: armv5te/alt_stub.S */ 16295/* 16296 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16297 * any interesting requests and then jump to the real instruction 16298 * handler. Note that the call to dvmCheckInst is done as a tail call. 16299 */ 16300 adrl lr, dvmAsmInstructionStart + (183 * 64) 16301 mov r0, rPC @ arg0 16302 mov r1, rSELF @ arg1 16303 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16304 16305/* ------------------------------ */ 16306 .balign 64 16307.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */ 16308/* File: armv5te/alt_stub.S */ 16309/* 16310 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16311 * any interesting requests and then jump to the real instruction 16312 * handler. Note that the call to dvmCheckInst is done as a tail call. 16313 */ 16314 adrl lr, dvmAsmInstructionStart + (184 * 64) 16315 mov r0, rPC @ arg0 16316 mov r1, rSELF @ arg1 16317 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16318 16319/* ------------------------------ */ 16320 .balign 64 16321.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */ 16322/* File: armv5te/alt_stub.S */ 16323/* 16324 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16325 * any interesting requests and then jump to the real instruction 16326 * handler. Note that the call to dvmCheckInst is done as a tail call. 16327 */ 16328 adrl lr, dvmAsmInstructionStart + (185 * 64) 16329 mov r0, rPC @ arg0 16330 mov r1, rSELF @ arg1 16331 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16332 16333/* ------------------------------ */ 16334 .balign 64 16335.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */ 16336/* File: armv5te/alt_stub.S */ 16337/* 16338 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16339 * any interesting requests and then jump to the real instruction 16340 * handler. Note that the call to dvmCheckInst is done as a tail call. 16341 */ 16342 adrl lr, dvmAsmInstructionStart + (186 * 64) 16343 mov r0, rPC @ arg0 16344 mov r1, rSELF @ arg1 16345 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16346 16347/* ------------------------------ */ 16348 .balign 64 16349.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */ 16350/* File: armv5te/alt_stub.S */ 16351/* 16352 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16353 * any interesting requests and then jump to the real instruction 16354 * handler. Note that the call to dvmCheckInst is done as a tail call. 16355 */ 16356 adrl lr, dvmAsmInstructionStart + (187 * 64) 16357 mov r0, rPC @ arg0 16358 mov r1, rSELF @ arg1 16359 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16360 16361/* ------------------------------ */ 16362 .balign 64 16363.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */ 16364/* File: armv5te/alt_stub.S */ 16365/* 16366 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16367 * any interesting requests and then jump to the real instruction 16368 * handler. Note that the call to dvmCheckInst is done as a tail call. 16369 */ 16370 adrl lr, dvmAsmInstructionStart + (188 * 64) 16371 mov r0, rPC @ arg0 16372 mov r1, rSELF @ arg1 16373 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16374 16375/* ------------------------------ */ 16376 .balign 64 16377.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */ 16378/* File: armv5te/alt_stub.S */ 16379/* 16380 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16381 * any interesting requests and then jump to the real instruction 16382 * handler. Note that the call to dvmCheckInst is done as a tail call. 16383 */ 16384 adrl lr, dvmAsmInstructionStart + (189 * 64) 16385 mov r0, rPC @ arg0 16386 mov r1, rSELF @ arg1 16387 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16388 16389/* ------------------------------ */ 16390 .balign 64 16391.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */ 16392/* File: armv5te/alt_stub.S */ 16393/* 16394 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16395 * any interesting requests and then jump to the real instruction 16396 * handler. Note that the call to dvmCheckInst is done as a tail call. 16397 */ 16398 adrl lr, dvmAsmInstructionStart + (190 * 64) 16399 mov r0, rPC @ arg0 16400 mov r1, rSELF @ arg1 16401 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16402 16403/* ------------------------------ */ 16404 .balign 64 16405.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */ 16406/* File: armv5te/alt_stub.S */ 16407/* 16408 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16409 * any interesting requests and then jump to the real instruction 16410 * handler. Note that the call to dvmCheckInst is done as a tail call. 16411 */ 16412 adrl lr, dvmAsmInstructionStart + (191 * 64) 16413 mov r0, rPC @ arg0 16414 mov r1, rSELF @ arg1 16415 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16416 16417/* ------------------------------ */ 16418 .balign 64 16419.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */ 16420/* File: armv5te/alt_stub.S */ 16421/* 16422 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16423 * any interesting requests and then jump to the real instruction 16424 * handler. Note that the call to dvmCheckInst is done as a tail call. 16425 */ 16426 adrl lr, dvmAsmInstructionStart + (192 * 64) 16427 mov r0, rPC @ arg0 16428 mov r1, rSELF @ arg1 16429 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16430 16431/* ------------------------------ */ 16432 .balign 64 16433.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */ 16434/* File: armv5te/alt_stub.S */ 16435/* 16436 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16437 * any interesting requests and then jump to the real instruction 16438 * handler. Note that the call to dvmCheckInst is done as a tail call. 16439 */ 16440 adrl lr, dvmAsmInstructionStart + (193 * 64) 16441 mov r0, rPC @ arg0 16442 mov r1, rSELF @ arg1 16443 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16444 16445/* ------------------------------ */ 16446 .balign 64 16447.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */ 16448/* File: armv5te/alt_stub.S */ 16449/* 16450 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16451 * any interesting requests and then jump to the real instruction 16452 * handler. Note that the call to dvmCheckInst is done as a tail call. 16453 */ 16454 adrl lr, dvmAsmInstructionStart + (194 * 64) 16455 mov r0, rPC @ arg0 16456 mov r1, rSELF @ arg1 16457 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16458 16459/* ------------------------------ */ 16460 .balign 64 16461.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */ 16462/* File: armv5te/alt_stub.S */ 16463/* 16464 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16465 * any interesting requests and then jump to the real instruction 16466 * handler. Note that the call to dvmCheckInst is done as a tail call. 16467 */ 16468 adrl lr, dvmAsmInstructionStart + (195 * 64) 16469 mov r0, rPC @ arg0 16470 mov r1, rSELF @ arg1 16471 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16472 16473/* ------------------------------ */ 16474 .balign 64 16475.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */ 16476/* File: armv5te/alt_stub.S */ 16477/* 16478 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16479 * any interesting requests and then jump to the real instruction 16480 * handler. Note that the call to dvmCheckInst is done as a tail call. 16481 */ 16482 adrl lr, dvmAsmInstructionStart + (196 * 64) 16483 mov r0, rPC @ arg0 16484 mov r1, rSELF @ arg1 16485 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16486 16487/* ------------------------------ */ 16488 .balign 64 16489.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */ 16490/* File: armv5te/alt_stub.S */ 16491/* 16492 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16493 * any interesting requests and then jump to the real instruction 16494 * handler. Note that the call to dvmCheckInst is done as a tail call. 16495 */ 16496 adrl lr, dvmAsmInstructionStart + (197 * 64) 16497 mov r0, rPC @ arg0 16498 mov r1, rSELF @ arg1 16499 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16500 16501/* ------------------------------ */ 16502 .balign 64 16503.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 16504/* File: armv5te/alt_stub.S */ 16505/* 16506 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16507 * any interesting requests and then jump to the real instruction 16508 * handler. Note that the call to dvmCheckInst is done as a tail call. 16509 */ 16510 adrl lr, dvmAsmInstructionStart + (198 * 64) 16511 mov r0, rPC @ arg0 16512 mov r1, rSELF @ arg1 16513 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16514 16515/* ------------------------------ */ 16516 .balign 64 16517.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 16518/* File: armv5te/alt_stub.S */ 16519/* 16520 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16521 * any interesting requests and then jump to the real instruction 16522 * handler. Note that the call to dvmCheckInst is done as a tail call. 16523 */ 16524 adrl lr, dvmAsmInstructionStart + (199 * 64) 16525 mov r0, rPC @ arg0 16526 mov r1, rSELF @ arg1 16527 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16528 16529/* ------------------------------ */ 16530 .balign 64 16531.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 16532/* File: armv5te/alt_stub.S */ 16533/* 16534 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16535 * any interesting requests and then jump to the real instruction 16536 * handler. Note that the call to dvmCheckInst is done as a tail call. 16537 */ 16538 adrl lr, dvmAsmInstructionStart + (200 * 64) 16539 mov r0, rPC @ arg0 16540 mov r1, rSELF @ arg1 16541 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16542 16543/* ------------------------------ */ 16544 .balign 64 16545.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 16546/* File: armv5te/alt_stub.S */ 16547/* 16548 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16549 * any interesting requests and then jump to the real instruction 16550 * handler. Note that the call to dvmCheckInst is done as a tail call. 16551 */ 16552 adrl lr, dvmAsmInstructionStart + (201 * 64) 16553 mov r0, rPC @ arg0 16554 mov r1, rSELF @ arg1 16555 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16556 16557/* ------------------------------ */ 16558 .balign 64 16559.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */ 16560/* File: armv5te/alt_stub.S */ 16561/* 16562 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16563 * any interesting requests and then jump to the real instruction 16564 * handler. Note that the call to dvmCheckInst is done as a tail call. 16565 */ 16566 adrl lr, dvmAsmInstructionStart + (202 * 64) 16567 mov r0, rPC @ arg0 16568 mov r1, rSELF @ arg1 16569 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16570 16571/* ------------------------------ */ 16572 .balign 64 16573.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 16574/* File: armv5te/alt_stub.S */ 16575/* 16576 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16577 * any interesting requests and then jump to the real instruction 16578 * handler. Note that the call to dvmCheckInst is done as a tail call. 16579 */ 16580 adrl lr, dvmAsmInstructionStart + (203 * 64) 16581 mov r0, rPC @ arg0 16582 mov r1, rSELF @ arg1 16583 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16584 16585/* ------------------------------ */ 16586 .balign 64 16587.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 16588/* File: armv5te/alt_stub.S */ 16589/* 16590 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16591 * any interesting requests and then jump to the real instruction 16592 * handler. Note that the call to dvmCheckInst is done as a tail call. 16593 */ 16594 adrl lr, dvmAsmInstructionStart + (204 * 64) 16595 mov r0, rPC @ arg0 16596 mov r1, rSELF @ arg1 16597 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16598 16599/* ------------------------------ */ 16600 .balign 64 16601.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 16602/* File: armv5te/alt_stub.S */ 16603/* 16604 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16605 * any interesting requests and then jump to the real instruction 16606 * handler. Note that the call to dvmCheckInst is done as a tail call. 16607 */ 16608 adrl lr, dvmAsmInstructionStart + (205 * 64) 16609 mov r0, rPC @ arg0 16610 mov r1, rSELF @ arg1 16611 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16612 16613/* ------------------------------ */ 16614 .balign 64 16615.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 16616/* File: armv5te/alt_stub.S */ 16617/* 16618 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16619 * any interesting requests and then jump to the real instruction 16620 * handler. Note that the call to dvmCheckInst is done as a tail call. 16621 */ 16622 adrl lr, dvmAsmInstructionStart + (206 * 64) 16623 mov r0, rPC @ arg0 16624 mov r1, rSELF @ arg1 16625 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16626 16627/* ------------------------------ */ 16628 .balign 64 16629.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 16630/* File: armv5te/alt_stub.S */ 16631/* 16632 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16633 * any interesting requests and then jump to the real instruction 16634 * handler. Note that the call to dvmCheckInst is done as a tail call. 16635 */ 16636 adrl lr, dvmAsmInstructionStart + (207 * 64) 16637 mov r0, rPC @ arg0 16638 mov r1, rSELF @ arg1 16639 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16640 16641/* ------------------------------ */ 16642 .balign 64 16643.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */ 16644/* File: armv5te/alt_stub.S */ 16645/* 16646 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16647 * any interesting requests and then jump to the real instruction 16648 * handler. Note that the call to dvmCheckInst is done as a tail call. 16649 */ 16650 adrl lr, dvmAsmInstructionStart + (208 * 64) 16651 mov r0, rPC @ arg0 16652 mov r1, rSELF @ arg1 16653 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16654 16655/* ------------------------------ */ 16656 .balign 64 16657.L_ALT_OP_RSUB_INT: /* 0xd1 */ 16658/* File: armv5te/alt_stub.S */ 16659/* 16660 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16661 * any interesting requests and then jump to the real instruction 16662 * handler. Note that the call to dvmCheckInst is done as a tail call. 16663 */ 16664 adrl lr, dvmAsmInstructionStart + (209 * 64) 16665 mov r0, rPC @ arg0 16666 mov r1, rSELF @ arg1 16667 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16668 16669/* ------------------------------ */ 16670 .balign 64 16671.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */ 16672/* File: armv5te/alt_stub.S */ 16673/* 16674 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16675 * any interesting requests and then jump to the real instruction 16676 * handler. Note that the call to dvmCheckInst is done as a tail call. 16677 */ 16678 adrl lr, dvmAsmInstructionStart + (210 * 64) 16679 mov r0, rPC @ arg0 16680 mov r1, rSELF @ arg1 16681 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16682 16683/* ------------------------------ */ 16684 .balign 64 16685.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */ 16686/* File: armv5te/alt_stub.S */ 16687/* 16688 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16689 * any interesting requests and then jump to the real instruction 16690 * handler. Note that the call to dvmCheckInst is done as a tail call. 16691 */ 16692 adrl lr, dvmAsmInstructionStart + (211 * 64) 16693 mov r0, rPC @ arg0 16694 mov r1, rSELF @ arg1 16695 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16696 16697/* ------------------------------ */ 16698 .balign 64 16699.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */ 16700/* File: armv5te/alt_stub.S */ 16701/* 16702 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16703 * any interesting requests and then jump to the real instruction 16704 * handler. Note that the call to dvmCheckInst is done as a tail call. 16705 */ 16706 adrl lr, dvmAsmInstructionStart + (212 * 64) 16707 mov r0, rPC @ arg0 16708 mov r1, rSELF @ arg1 16709 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16710 16711/* ------------------------------ */ 16712 .balign 64 16713.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */ 16714/* File: armv5te/alt_stub.S */ 16715/* 16716 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16717 * any interesting requests and then jump to the real instruction 16718 * handler. Note that the call to dvmCheckInst is done as a tail call. 16719 */ 16720 adrl lr, dvmAsmInstructionStart + (213 * 64) 16721 mov r0, rPC @ arg0 16722 mov r1, rSELF @ arg1 16723 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16724 16725/* ------------------------------ */ 16726 .balign 64 16727.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */ 16728/* File: armv5te/alt_stub.S */ 16729/* 16730 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16731 * any interesting requests and then jump to the real instruction 16732 * handler. Note that the call to dvmCheckInst is done as a tail call. 16733 */ 16734 adrl lr, dvmAsmInstructionStart + (214 * 64) 16735 mov r0, rPC @ arg0 16736 mov r1, rSELF @ arg1 16737 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16738 16739/* ------------------------------ */ 16740 .balign 64 16741.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */ 16742/* File: armv5te/alt_stub.S */ 16743/* 16744 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16745 * any interesting requests and then jump to the real instruction 16746 * handler. Note that the call to dvmCheckInst is done as a tail call. 16747 */ 16748 adrl lr, dvmAsmInstructionStart + (215 * 64) 16749 mov r0, rPC @ arg0 16750 mov r1, rSELF @ arg1 16751 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16752 16753/* ------------------------------ */ 16754 .balign 64 16755.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */ 16756/* File: armv5te/alt_stub.S */ 16757/* 16758 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16759 * any interesting requests and then jump to the real instruction 16760 * handler. Note that the call to dvmCheckInst is done as a tail call. 16761 */ 16762 adrl lr, dvmAsmInstructionStart + (216 * 64) 16763 mov r0, rPC @ arg0 16764 mov r1, rSELF @ arg1 16765 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16766 16767/* ------------------------------ */ 16768 .balign 64 16769.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */ 16770/* File: armv5te/alt_stub.S */ 16771/* 16772 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16773 * any interesting requests and then jump to the real instruction 16774 * handler. Note that the call to dvmCheckInst is done as a tail call. 16775 */ 16776 adrl lr, dvmAsmInstructionStart + (217 * 64) 16777 mov r0, rPC @ arg0 16778 mov r1, rSELF @ arg1 16779 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16780 16781/* ------------------------------ */ 16782 .balign 64 16783.L_ALT_OP_MUL_INT_LIT8: /* 0xda */ 16784/* File: armv5te/alt_stub.S */ 16785/* 16786 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16787 * any interesting requests and then jump to the real instruction 16788 * handler. Note that the call to dvmCheckInst is done as a tail call. 16789 */ 16790 adrl lr, dvmAsmInstructionStart + (218 * 64) 16791 mov r0, rPC @ arg0 16792 mov r1, rSELF @ arg1 16793 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16794 16795/* ------------------------------ */ 16796 .balign 64 16797.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */ 16798/* File: armv5te/alt_stub.S */ 16799/* 16800 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16801 * any interesting requests and then jump to the real instruction 16802 * handler. Note that the call to dvmCheckInst is done as a tail call. 16803 */ 16804 adrl lr, dvmAsmInstructionStart + (219 * 64) 16805 mov r0, rPC @ arg0 16806 mov r1, rSELF @ arg1 16807 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16808 16809/* ------------------------------ */ 16810 .balign 64 16811.L_ALT_OP_REM_INT_LIT8: /* 0xdc */ 16812/* File: armv5te/alt_stub.S */ 16813/* 16814 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16815 * any interesting requests and then jump to the real instruction 16816 * handler. Note that the call to dvmCheckInst is done as a tail call. 16817 */ 16818 adrl lr, dvmAsmInstructionStart + (220 * 64) 16819 mov r0, rPC @ arg0 16820 mov r1, rSELF @ arg1 16821 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16822 16823/* ------------------------------ */ 16824 .balign 64 16825.L_ALT_OP_AND_INT_LIT8: /* 0xdd */ 16826/* File: armv5te/alt_stub.S */ 16827/* 16828 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16829 * any interesting requests and then jump to the real instruction 16830 * handler. Note that the call to dvmCheckInst is done as a tail call. 16831 */ 16832 adrl lr, dvmAsmInstructionStart + (221 * 64) 16833 mov r0, rPC @ arg0 16834 mov r1, rSELF @ arg1 16835 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16836 16837/* ------------------------------ */ 16838 .balign 64 16839.L_ALT_OP_OR_INT_LIT8: /* 0xde */ 16840/* File: armv5te/alt_stub.S */ 16841/* 16842 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16843 * any interesting requests and then jump to the real instruction 16844 * handler. Note that the call to dvmCheckInst is done as a tail call. 16845 */ 16846 adrl lr, dvmAsmInstructionStart + (222 * 64) 16847 mov r0, rPC @ arg0 16848 mov r1, rSELF @ arg1 16849 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16850 16851/* ------------------------------ */ 16852 .balign 64 16853.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */ 16854/* File: armv5te/alt_stub.S */ 16855/* 16856 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16857 * any interesting requests and then jump to the real instruction 16858 * handler. Note that the call to dvmCheckInst is done as a tail call. 16859 */ 16860 adrl lr, dvmAsmInstructionStart + (223 * 64) 16861 mov r0, rPC @ arg0 16862 mov r1, rSELF @ arg1 16863 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16864 16865/* ------------------------------ */ 16866 .balign 64 16867.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */ 16868/* File: armv5te/alt_stub.S */ 16869/* 16870 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16871 * any interesting requests and then jump to the real instruction 16872 * handler. Note that the call to dvmCheckInst is done as a tail call. 16873 */ 16874 adrl lr, dvmAsmInstructionStart + (224 * 64) 16875 mov r0, rPC @ arg0 16876 mov r1, rSELF @ arg1 16877 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16878 16879/* ------------------------------ */ 16880 .balign 64 16881.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */ 16882/* File: armv5te/alt_stub.S */ 16883/* 16884 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16885 * any interesting requests and then jump to the real instruction 16886 * handler. Note that the call to dvmCheckInst is done as a tail call. 16887 */ 16888 adrl lr, dvmAsmInstructionStart + (225 * 64) 16889 mov r0, rPC @ arg0 16890 mov r1, rSELF @ arg1 16891 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16892 16893/* ------------------------------ */ 16894 .balign 64 16895.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */ 16896/* File: armv5te/alt_stub.S */ 16897/* 16898 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16899 * any interesting requests and then jump to the real instruction 16900 * handler. Note that the call to dvmCheckInst is done as a tail call. 16901 */ 16902 adrl lr, dvmAsmInstructionStart + (226 * 64) 16903 mov r0, rPC @ arg0 16904 mov r1, rSELF @ arg1 16905 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16906 16907/* ------------------------------ */ 16908 .balign 64 16909.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */ 16910/* File: armv5te/alt_stub.S */ 16911/* 16912 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16913 * any interesting requests and then jump to the real instruction 16914 * handler. Note that the call to dvmCheckInst is done as a tail call. 16915 */ 16916 adrl lr, dvmAsmInstructionStart + (227 * 64) 16917 mov r0, rPC @ arg0 16918 mov r1, rSELF @ arg1 16919 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16920 16921/* ------------------------------ */ 16922 .balign 64 16923.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */ 16924/* File: armv5te/alt_stub.S */ 16925/* 16926 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16927 * any interesting requests and then jump to the real instruction 16928 * handler. Note that the call to dvmCheckInst is done as a tail call. 16929 */ 16930 adrl lr, dvmAsmInstructionStart + (228 * 64) 16931 mov r0, rPC @ arg0 16932 mov r1, rSELF @ arg1 16933 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16934 16935/* ------------------------------ */ 16936 .balign 64 16937.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */ 16938/* File: armv5te/alt_stub.S */ 16939/* 16940 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16941 * any interesting requests and then jump to the real instruction 16942 * handler. Note that the call to dvmCheckInst is done as a tail call. 16943 */ 16944 adrl lr, dvmAsmInstructionStart + (229 * 64) 16945 mov r0, rPC @ arg0 16946 mov r1, rSELF @ arg1 16947 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16948 16949/* ------------------------------ */ 16950 .balign 64 16951.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */ 16952/* File: armv5te/alt_stub.S */ 16953/* 16954 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16955 * any interesting requests and then jump to the real instruction 16956 * handler. Note that the call to dvmCheckInst is done as a tail call. 16957 */ 16958 adrl lr, dvmAsmInstructionStart + (230 * 64) 16959 mov r0, rPC @ arg0 16960 mov r1, rSELF @ arg1 16961 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16962 16963/* ------------------------------ */ 16964 .balign 64 16965.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 16966/* File: armv5te/alt_stub.S */ 16967/* 16968 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16969 * any interesting requests and then jump to the real instruction 16970 * handler. Note that the call to dvmCheckInst is done as a tail call. 16971 */ 16972 adrl lr, dvmAsmInstructionStart + (231 * 64) 16973 mov r0, rPC @ arg0 16974 mov r1, rSELF @ arg1 16975 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16976 16977/* ------------------------------ */ 16978 .balign 64 16979.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 16980/* File: armv5te/alt_stub.S */ 16981/* 16982 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16983 * any interesting requests and then jump to the real instruction 16984 * handler. Note that the call to dvmCheckInst is done as a tail call. 16985 */ 16986 adrl lr, dvmAsmInstructionStart + (232 * 64) 16987 mov r0, rPC @ arg0 16988 mov r1, rSELF @ arg1 16989 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16990 16991/* ------------------------------ */ 16992 .balign 64 16993.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 16994/* File: armv5te/alt_stub.S */ 16995/* 16996 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16997 * any interesting requests and then jump to the real instruction 16998 * handler. Note that the call to dvmCheckInst is done as a tail call. 16999 */ 17000 adrl lr, dvmAsmInstructionStart + (233 * 64) 17001 mov r0, rPC @ arg0 17002 mov r1, rSELF @ arg1 17003 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17004 17005/* ------------------------------ */ 17006 .balign 64 17007.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */ 17008/* File: armv5te/alt_stub.S */ 17009/* 17010 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17011 * any interesting requests and then jump to the real instruction 17012 * handler. Note that the call to dvmCheckInst is done as a tail call. 17013 */ 17014 adrl lr, dvmAsmInstructionStart + (234 * 64) 17015 mov r0, rPC @ arg0 17016 mov r1, rSELF @ arg1 17017 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17018 17019/* ------------------------------ */ 17020 .balign 64 17021.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 17022/* File: armv5te/alt_stub.S */ 17023/* 17024 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17025 * any interesting requests and then jump to the real instruction 17026 * handler. Note that the call to dvmCheckInst is done as a tail call. 17027 */ 17028 adrl lr, dvmAsmInstructionStart + (235 * 64) 17029 mov r0, rPC @ arg0 17030 mov r1, rSELF @ arg1 17031 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17032 17033/* ------------------------------ */ 17034 .balign 64 17035.L_ALT_OP_BREAKPOINT: /* 0xec */ 17036/* File: armv5te/alt_stub.S */ 17037/* 17038 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17039 * any interesting requests and then jump to the real instruction 17040 * handler. Note that the call to dvmCheckInst is done as a tail call. 17041 */ 17042 adrl lr, dvmAsmInstructionStart + (236 * 64) 17043 mov r0, rPC @ arg0 17044 mov r1, rSELF @ arg1 17045 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17046 17047/* ------------------------------ */ 17048 .balign 64 17049.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 17050/* File: armv5te/alt_stub.S */ 17051/* 17052 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17053 * any interesting requests and then jump to the real instruction 17054 * handler. Note that the call to dvmCheckInst is done as a tail call. 17055 */ 17056 adrl lr, dvmAsmInstructionStart + (237 * 64) 17057 mov r0, rPC @ arg0 17058 mov r1, rSELF @ arg1 17059 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17060 17061/* ------------------------------ */ 17062 .balign 64 17063.L_ALT_OP_EXECUTE_INLINE: /* 0xee */ 17064/* File: armv5te/alt_stub.S */ 17065/* 17066 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17067 * any interesting requests and then jump to the real instruction 17068 * handler. Note that the call to dvmCheckInst is done as a tail call. 17069 */ 17070 adrl lr, dvmAsmInstructionStart + (238 * 64) 17071 mov r0, rPC @ arg0 17072 mov r1, rSELF @ arg1 17073 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17074 17075/* ------------------------------ */ 17076 .balign 64 17077.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 17078/* File: armv5te/alt_stub.S */ 17079/* 17080 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17081 * any interesting requests and then jump to the real instruction 17082 * handler. Note that the call to dvmCheckInst is done as a tail call. 17083 */ 17084 adrl lr, dvmAsmInstructionStart + (239 * 64) 17085 mov r0, rPC @ arg0 17086 mov r1, rSELF @ arg1 17087 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17088 17089/* ------------------------------ */ 17090 .balign 64 17091.L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 17092/* File: armv5te/alt_stub.S */ 17093/* 17094 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17095 * any interesting requests and then jump to the real instruction 17096 * handler. Note that the call to dvmCheckInst is done as a tail call. 17097 */ 17098 adrl lr, dvmAsmInstructionStart + (240 * 64) 17099 mov r0, rPC @ arg0 17100 mov r1, rSELF @ arg1 17101 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17102 17103/* ------------------------------ */ 17104 .balign 64 17105.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 17106/* File: armv5te/alt_stub.S */ 17107/* 17108 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17109 * any interesting requests and then jump to the real instruction 17110 * handler. Note that the call to dvmCheckInst is done as a tail call. 17111 */ 17112 adrl lr, dvmAsmInstructionStart + (241 * 64) 17113 mov r0, rPC @ arg0 17114 mov r1, rSELF @ arg1 17115 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17116 17117/* ------------------------------ */ 17118 .balign 64 17119.L_ALT_OP_IGET_QUICK: /* 0xf2 */ 17120/* File: armv5te/alt_stub.S */ 17121/* 17122 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17123 * any interesting requests and then jump to the real instruction 17124 * handler. Note that the call to dvmCheckInst is done as a tail call. 17125 */ 17126 adrl lr, dvmAsmInstructionStart + (242 * 64) 17127 mov r0, rPC @ arg0 17128 mov r1, rSELF @ arg1 17129 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17130 17131/* ------------------------------ */ 17132 .balign 64 17133.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */ 17134/* File: armv5te/alt_stub.S */ 17135/* 17136 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17137 * any interesting requests and then jump to the real instruction 17138 * handler. Note that the call to dvmCheckInst is done as a tail call. 17139 */ 17140 adrl lr, dvmAsmInstructionStart + (243 * 64) 17141 mov r0, rPC @ arg0 17142 mov r1, rSELF @ arg1 17143 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17144 17145/* ------------------------------ */ 17146 .balign 64 17147.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 17148/* File: armv5te/alt_stub.S */ 17149/* 17150 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17151 * any interesting requests and then jump to the real instruction 17152 * handler. Note that the call to dvmCheckInst is done as a tail call. 17153 */ 17154 adrl lr, dvmAsmInstructionStart + (244 * 64) 17155 mov r0, rPC @ arg0 17156 mov r1, rSELF @ arg1 17157 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17158 17159/* ------------------------------ */ 17160 .balign 64 17161.L_ALT_OP_IPUT_QUICK: /* 0xf5 */ 17162/* File: armv5te/alt_stub.S */ 17163/* 17164 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17165 * any interesting requests and then jump to the real instruction 17166 * handler. Note that the call to dvmCheckInst is done as a tail call. 17167 */ 17168 adrl lr, dvmAsmInstructionStart + (245 * 64) 17169 mov r0, rPC @ arg0 17170 mov r1, rSELF @ arg1 17171 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17172 17173/* ------------------------------ */ 17174 .balign 64 17175.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 17176/* File: armv5te/alt_stub.S */ 17177/* 17178 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17179 * any interesting requests and then jump to the real instruction 17180 * handler. Note that the call to dvmCheckInst is done as a tail call. 17181 */ 17182 adrl lr, dvmAsmInstructionStart + (246 * 64) 17183 mov r0, rPC @ arg0 17184 mov r1, rSELF @ arg1 17185 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17186 17187/* ------------------------------ */ 17188 .balign 64 17189.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 17190/* File: armv5te/alt_stub.S */ 17191/* 17192 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17193 * any interesting requests and then jump to the real instruction 17194 * handler. Note that the call to dvmCheckInst is done as a tail call. 17195 */ 17196 adrl lr, dvmAsmInstructionStart + (247 * 64) 17197 mov r0, rPC @ arg0 17198 mov r1, rSELF @ arg1 17199 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17200 17201/* ------------------------------ */ 17202 .balign 64 17203.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 17204/* File: armv5te/alt_stub.S */ 17205/* 17206 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17207 * any interesting requests and then jump to the real instruction 17208 * handler. Note that the call to dvmCheckInst is done as a tail call. 17209 */ 17210 adrl lr, dvmAsmInstructionStart + (248 * 64) 17211 mov r0, rPC @ arg0 17212 mov r1, rSELF @ arg1 17213 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17214 17215/* ------------------------------ */ 17216 .balign 64 17217.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 17218/* File: armv5te/alt_stub.S */ 17219/* 17220 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17221 * any interesting requests and then jump to the real instruction 17222 * handler. Note that the call to dvmCheckInst is done as a tail call. 17223 */ 17224 adrl lr, dvmAsmInstructionStart + (249 * 64) 17225 mov r0, rPC @ arg0 17226 mov r1, rSELF @ arg1 17227 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17228 17229/* ------------------------------ */ 17230 .balign 64 17231.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 17232/* File: armv5te/alt_stub.S */ 17233/* 17234 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17235 * any interesting requests and then jump to the real instruction 17236 * handler. Note that the call to dvmCheckInst is done as a tail call. 17237 */ 17238 adrl lr, dvmAsmInstructionStart + (250 * 64) 17239 mov r0, rPC @ arg0 17240 mov r1, rSELF @ arg1 17241 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17242 17243/* ------------------------------ */ 17244 .balign 64 17245.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 17246/* File: armv5te/alt_stub.S */ 17247/* 17248 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17249 * any interesting requests and then jump to the real instruction 17250 * handler. Note that the call to dvmCheckInst is done as a tail call. 17251 */ 17252 adrl lr, dvmAsmInstructionStart + (251 * 64) 17253 mov r0, rPC @ arg0 17254 mov r1, rSELF @ arg1 17255 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17256 17257/* ------------------------------ */ 17258 .balign 64 17259.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 17260/* File: armv5te/alt_stub.S */ 17261/* 17262 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17263 * any interesting requests and then jump to the real instruction 17264 * handler. Note that the call to dvmCheckInst is done as a tail call. 17265 */ 17266 adrl lr, dvmAsmInstructionStart + (252 * 64) 17267 mov r0, rPC @ arg0 17268 mov r1, rSELF @ arg1 17269 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17270 17271/* ------------------------------ */ 17272 .balign 64 17273.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 17274/* File: armv5te/alt_stub.S */ 17275/* 17276 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17277 * any interesting requests and then jump to the real instruction 17278 * handler. Note that the call to dvmCheckInst is done as a tail call. 17279 */ 17280 adrl lr, dvmAsmInstructionStart + (253 * 64) 17281 mov r0, rPC @ arg0 17282 mov r1, rSELF @ arg1 17283 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17284 17285/* ------------------------------ */ 17286 .balign 64 17287.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 17288/* File: armv5te/alt_stub.S */ 17289/* 17290 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17291 * any interesting requests and then jump to the real instruction 17292 * handler. Note that the call to dvmCheckInst is done as a tail call. 17293 */ 17294 adrl lr, dvmAsmInstructionStart + (254 * 64) 17295 mov r0, rPC @ arg0 17296 mov r1, rSELF @ arg1 17297 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17298 17299/* ------------------------------ */ 17300 .balign 64 17301.L_ALT_OP_DISPATCH_FF: /* 0xff */ 17302/* File: armv5te/alt_stub.S */ 17303/* 17304 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17305 * any interesting requests and then jump to the real instruction 17306 * handler. Note that the call to dvmCheckInst is done as a tail call. 17307 */ 17308 adrl lr, dvmAsmInstructionStart + (255 * 64) 17309 mov r0, rPC @ arg0 17310 mov r1, rSELF @ arg1 17311 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17312 17313/* ------------------------------ */ 17314 .balign 64 17315.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */ 17316/* File: armv5te/alt_stub.S */ 17317/* 17318 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17319 * any interesting requests and then jump to the real instruction 17320 * handler. Note that the call to dvmCheckInst is done as a tail call. 17321 */ 17322 adrl lr, dvmAsmInstructionStart + (256 * 64) 17323 mov r0, rPC @ arg0 17324 mov r1, rSELF @ arg1 17325 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17326 17327/* ------------------------------ */ 17328 .balign 64 17329.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */ 17330/* File: armv5te/alt_stub.S */ 17331/* 17332 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17333 * any interesting requests and then jump to the real instruction 17334 * handler. Note that the call to dvmCheckInst is done as a tail call. 17335 */ 17336 adrl lr, dvmAsmInstructionStart + (257 * 64) 17337 mov r0, rPC @ arg0 17338 mov r1, rSELF @ arg1 17339 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17340 17341/* ------------------------------ */ 17342 .balign 64 17343.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 17344/* File: armv5te/alt_stub.S */ 17345/* 17346 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17347 * any interesting requests and then jump to the real instruction 17348 * handler. Note that the call to dvmCheckInst is done as a tail call. 17349 */ 17350 adrl lr, dvmAsmInstructionStart + (258 * 64) 17351 mov r0, rPC @ arg0 17352 mov r1, rSELF @ arg1 17353 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17354 17355/* ------------------------------ */ 17356 .balign 64 17357.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 17358/* File: armv5te/alt_stub.S */ 17359/* 17360 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17361 * any interesting requests and then jump to the real instruction 17362 * handler. Note that the call to dvmCheckInst is done as a tail call. 17363 */ 17364 adrl lr, dvmAsmInstructionStart + (259 * 64) 17365 mov r0, rPC @ arg0 17366 mov r1, rSELF @ arg1 17367 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17368 17369/* ------------------------------ */ 17370 .balign 64 17371.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 17372/* File: armv5te/alt_stub.S */ 17373/* 17374 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17375 * any interesting requests and then jump to the real instruction 17376 * handler. Note that the call to dvmCheckInst is done as a tail call. 17377 */ 17378 adrl lr, dvmAsmInstructionStart + (260 * 64) 17379 mov r0, rPC @ arg0 17380 mov r1, rSELF @ arg1 17381 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17382 17383/* ------------------------------ */ 17384 .balign 64 17385.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 17386/* File: armv5te/alt_stub.S */ 17387/* 17388 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17389 * any interesting requests and then jump to the real instruction 17390 * handler. Note that the call to dvmCheckInst is done as a tail call. 17391 */ 17392 adrl lr, dvmAsmInstructionStart + (261 * 64) 17393 mov r0, rPC @ arg0 17394 mov r1, rSELF @ arg1 17395 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17396 17397/* ------------------------------ */ 17398 .balign 64 17399.L_ALT_OP_IGET_JUMBO: /* 0x106 */ 17400/* File: armv5te/alt_stub.S */ 17401/* 17402 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17403 * any interesting requests and then jump to the real instruction 17404 * handler. Note that the call to dvmCheckInst is done as a tail call. 17405 */ 17406 adrl lr, dvmAsmInstructionStart + (262 * 64) 17407 mov r0, rPC @ arg0 17408 mov r1, rSELF @ arg1 17409 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17410 17411/* ------------------------------ */ 17412 .balign 64 17413.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */ 17414/* File: armv5te/alt_stub.S */ 17415/* 17416 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17417 * any interesting requests and then jump to the real instruction 17418 * handler. Note that the call to dvmCheckInst is done as a tail call. 17419 */ 17420 adrl lr, dvmAsmInstructionStart + (263 * 64) 17421 mov r0, rPC @ arg0 17422 mov r1, rSELF @ arg1 17423 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17424 17425/* ------------------------------ */ 17426 .balign 64 17427.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 17428/* File: armv5te/alt_stub.S */ 17429/* 17430 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17431 * any interesting requests and then jump to the real instruction 17432 * handler. Note that the call to dvmCheckInst is done as a tail call. 17433 */ 17434 adrl lr, dvmAsmInstructionStart + (264 * 64) 17435 mov r0, rPC @ arg0 17436 mov r1, rSELF @ arg1 17437 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17438 17439/* ------------------------------ */ 17440 .balign 64 17441.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 17442/* File: armv5te/alt_stub.S */ 17443/* 17444 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17445 * any interesting requests and then jump to the real instruction 17446 * handler. Note that the call to dvmCheckInst is done as a tail call. 17447 */ 17448 adrl lr, dvmAsmInstructionStart + (265 * 64) 17449 mov r0, rPC @ arg0 17450 mov r1, rSELF @ arg1 17451 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17452 17453/* ------------------------------ */ 17454 .balign 64 17455.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */ 17456/* File: armv5te/alt_stub.S */ 17457/* 17458 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17459 * any interesting requests and then jump to the real instruction 17460 * handler. Note that the call to dvmCheckInst is done as a tail call. 17461 */ 17462 adrl lr, dvmAsmInstructionStart + (266 * 64) 17463 mov r0, rPC @ arg0 17464 mov r1, rSELF @ arg1 17465 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17466 17467/* ------------------------------ */ 17468 .balign 64 17469.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */ 17470/* File: armv5te/alt_stub.S */ 17471/* 17472 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17473 * any interesting requests and then jump to the real instruction 17474 * handler. Note that the call to dvmCheckInst is done as a tail call. 17475 */ 17476 adrl lr, dvmAsmInstructionStart + (267 * 64) 17477 mov r0, rPC @ arg0 17478 mov r1, rSELF @ arg1 17479 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17480 17481/* ------------------------------ */ 17482 .balign 64 17483.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */ 17484/* File: armv5te/alt_stub.S */ 17485/* 17486 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17487 * any interesting requests and then jump to the real instruction 17488 * handler. Note that the call to dvmCheckInst is done as a tail call. 17489 */ 17490 adrl lr, dvmAsmInstructionStart + (268 * 64) 17491 mov r0, rPC @ arg0 17492 mov r1, rSELF @ arg1 17493 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17494 17495/* ------------------------------ */ 17496 .balign 64 17497.L_ALT_OP_IPUT_JUMBO: /* 0x10d */ 17498/* File: armv5te/alt_stub.S */ 17499/* 17500 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17501 * any interesting requests and then jump to the real instruction 17502 * handler. Note that the call to dvmCheckInst is done as a tail call. 17503 */ 17504 adrl lr, dvmAsmInstructionStart + (269 * 64) 17505 mov r0, rPC @ arg0 17506 mov r1, rSELF @ arg1 17507 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17508 17509/* ------------------------------ */ 17510 .balign 64 17511.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 17512/* File: armv5te/alt_stub.S */ 17513/* 17514 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17515 * any interesting requests and then jump to the real instruction 17516 * handler. Note that the call to dvmCheckInst is done as a tail call. 17517 */ 17518 adrl lr, dvmAsmInstructionStart + (270 * 64) 17519 mov r0, rPC @ arg0 17520 mov r1, rSELF @ arg1 17521 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17522 17523/* ------------------------------ */ 17524 .balign 64 17525.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 17526/* File: armv5te/alt_stub.S */ 17527/* 17528 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17529 * any interesting requests and then jump to the real instruction 17530 * handler. Note that the call to dvmCheckInst is done as a tail call. 17531 */ 17532 adrl lr, dvmAsmInstructionStart + (271 * 64) 17533 mov r0, rPC @ arg0 17534 mov r1, rSELF @ arg1 17535 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17536 17537/* ------------------------------ */ 17538 .balign 64 17539.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 17540/* File: armv5te/alt_stub.S */ 17541/* 17542 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17543 * any interesting requests and then jump to the real instruction 17544 * handler. Note that the call to dvmCheckInst is done as a tail call. 17545 */ 17546 adrl lr, dvmAsmInstructionStart + (272 * 64) 17547 mov r0, rPC @ arg0 17548 mov r1, rSELF @ arg1 17549 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17550 17551/* ------------------------------ */ 17552 .balign 64 17553.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 17554/* File: armv5te/alt_stub.S */ 17555/* 17556 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17557 * any interesting requests and then jump to the real instruction 17558 * handler. Note that the call to dvmCheckInst is done as a tail call. 17559 */ 17560 adrl lr, dvmAsmInstructionStart + (273 * 64) 17561 mov r0, rPC @ arg0 17562 mov r1, rSELF @ arg1 17563 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17564 17565/* ------------------------------ */ 17566 .balign 64 17567.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 17568/* File: armv5te/alt_stub.S */ 17569/* 17570 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17571 * any interesting requests and then jump to the real instruction 17572 * handler. Note that the call to dvmCheckInst is done as a tail call. 17573 */ 17574 adrl lr, dvmAsmInstructionStart + (274 * 64) 17575 mov r0, rPC @ arg0 17576 mov r1, rSELF @ arg1 17577 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17578 17579/* ------------------------------ */ 17580 .balign 64 17581.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 17582/* File: armv5te/alt_stub.S */ 17583/* 17584 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17585 * any interesting requests and then jump to the real instruction 17586 * handler. Note that the call to dvmCheckInst is done as a tail call. 17587 */ 17588 adrl lr, dvmAsmInstructionStart + (275 * 64) 17589 mov r0, rPC @ arg0 17590 mov r1, rSELF @ arg1 17591 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17592 17593/* ------------------------------ */ 17594 .balign 64 17595.L_ALT_OP_SGET_JUMBO: /* 0x114 */ 17596/* File: armv5te/alt_stub.S */ 17597/* 17598 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17599 * any interesting requests and then jump to the real instruction 17600 * handler. Note that the call to dvmCheckInst is done as a tail call. 17601 */ 17602 adrl lr, dvmAsmInstructionStart + (276 * 64) 17603 mov r0, rPC @ arg0 17604 mov r1, rSELF @ arg1 17605 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17606 17607/* ------------------------------ */ 17608 .balign 64 17609.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */ 17610/* File: armv5te/alt_stub.S */ 17611/* 17612 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17613 * any interesting requests and then jump to the real instruction 17614 * handler. Note that the call to dvmCheckInst is done as a tail call. 17615 */ 17616 adrl lr, dvmAsmInstructionStart + (277 * 64) 17617 mov r0, rPC @ arg0 17618 mov r1, rSELF @ arg1 17619 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17620 17621/* ------------------------------ */ 17622 .balign 64 17623.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 17624/* File: armv5te/alt_stub.S */ 17625/* 17626 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17627 * any interesting requests and then jump to the real instruction 17628 * handler. Note that the call to dvmCheckInst is done as a tail call. 17629 */ 17630 adrl lr, dvmAsmInstructionStart + (278 * 64) 17631 mov r0, rPC @ arg0 17632 mov r1, rSELF @ arg1 17633 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17634 17635/* ------------------------------ */ 17636 .balign 64 17637.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 17638/* File: armv5te/alt_stub.S */ 17639/* 17640 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17641 * any interesting requests and then jump to the real instruction 17642 * handler. Note that the call to dvmCheckInst is done as a tail call. 17643 */ 17644 adrl lr, dvmAsmInstructionStart + (279 * 64) 17645 mov r0, rPC @ arg0 17646 mov r1, rSELF @ arg1 17647 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17648 17649/* ------------------------------ */ 17650 .balign 64 17651.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */ 17652/* File: armv5te/alt_stub.S */ 17653/* 17654 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17655 * any interesting requests and then jump to the real instruction 17656 * handler. Note that the call to dvmCheckInst is done as a tail call. 17657 */ 17658 adrl lr, dvmAsmInstructionStart + (280 * 64) 17659 mov r0, rPC @ arg0 17660 mov r1, rSELF @ arg1 17661 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17662 17663/* ------------------------------ */ 17664 .balign 64 17665.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */ 17666/* File: armv5te/alt_stub.S */ 17667/* 17668 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17669 * any interesting requests and then jump to the real instruction 17670 * handler. Note that the call to dvmCheckInst is done as a tail call. 17671 */ 17672 adrl lr, dvmAsmInstructionStart + (281 * 64) 17673 mov r0, rPC @ arg0 17674 mov r1, rSELF @ arg1 17675 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17676 17677/* ------------------------------ */ 17678 .balign 64 17679.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */ 17680/* File: armv5te/alt_stub.S */ 17681/* 17682 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17683 * any interesting requests and then jump to the real instruction 17684 * handler. Note that the call to dvmCheckInst is done as a tail call. 17685 */ 17686 adrl lr, dvmAsmInstructionStart + (282 * 64) 17687 mov r0, rPC @ arg0 17688 mov r1, rSELF @ arg1 17689 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17690 17691/* ------------------------------ */ 17692 .balign 64 17693.L_ALT_OP_SPUT_JUMBO: /* 0x11b */ 17694/* File: armv5te/alt_stub.S */ 17695/* 17696 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17697 * any interesting requests and then jump to the real instruction 17698 * handler. Note that the call to dvmCheckInst is done as a tail call. 17699 */ 17700 adrl lr, dvmAsmInstructionStart + (283 * 64) 17701 mov r0, rPC @ arg0 17702 mov r1, rSELF @ arg1 17703 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17704 17705/* ------------------------------ */ 17706 .balign 64 17707.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 17708/* File: armv5te/alt_stub.S */ 17709/* 17710 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17711 * any interesting requests and then jump to the real instruction 17712 * handler. Note that the call to dvmCheckInst is done as a tail call. 17713 */ 17714 adrl lr, dvmAsmInstructionStart + (284 * 64) 17715 mov r0, rPC @ arg0 17716 mov r1, rSELF @ arg1 17717 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17718 17719/* ------------------------------ */ 17720 .balign 64 17721.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 17722/* File: armv5te/alt_stub.S */ 17723/* 17724 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17725 * any interesting requests and then jump to the real instruction 17726 * handler. Note that the call to dvmCheckInst is done as a tail call. 17727 */ 17728 adrl lr, dvmAsmInstructionStart + (285 * 64) 17729 mov r0, rPC @ arg0 17730 mov r1, rSELF @ arg1 17731 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17732 17733/* ------------------------------ */ 17734 .balign 64 17735.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 17736/* File: armv5te/alt_stub.S */ 17737/* 17738 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17739 * any interesting requests and then jump to the real instruction 17740 * handler. Note that the call to dvmCheckInst is done as a tail call. 17741 */ 17742 adrl lr, dvmAsmInstructionStart + (286 * 64) 17743 mov r0, rPC @ arg0 17744 mov r1, rSELF @ arg1 17745 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17746 17747/* ------------------------------ */ 17748 .balign 64 17749.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 17750/* File: armv5te/alt_stub.S */ 17751/* 17752 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17753 * any interesting requests and then jump to the real instruction 17754 * handler. Note that the call to dvmCheckInst is done as a tail call. 17755 */ 17756 adrl lr, dvmAsmInstructionStart + (287 * 64) 17757 mov r0, rPC @ arg0 17758 mov r1, rSELF @ arg1 17759 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17760 17761/* ------------------------------ */ 17762 .balign 64 17763.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 17764/* File: armv5te/alt_stub.S */ 17765/* 17766 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17767 * any interesting requests and then jump to the real instruction 17768 * handler. Note that the call to dvmCheckInst is done as a tail call. 17769 */ 17770 adrl lr, dvmAsmInstructionStart + (288 * 64) 17771 mov r0, rPC @ arg0 17772 mov r1, rSELF @ arg1 17773 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17774 17775/* ------------------------------ */ 17776 .balign 64 17777.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 17778/* File: armv5te/alt_stub.S */ 17779/* 17780 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17781 * any interesting requests and then jump to the real instruction 17782 * handler. Note that the call to dvmCheckInst is done as a tail call. 17783 */ 17784 adrl lr, dvmAsmInstructionStart + (289 * 64) 17785 mov r0, rPC @ arg0 17786 mov r1, rSELF @ arg1 17787 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17788 17789/* ------------------------------ */ 17790 .balign 64 17791.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 17792/* File: armv5te/alt_stub.S */ 17793/* 17794 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17795 * any interesting requests and then jump to the real instruction 17796 * handler. Note that the call to dvmCheckInst is done as a tail call. 17797 */ 17798 adrl lr, dvmAsmInstructionStart + (290 * 64) 17799 mov r0, rPC @ arg0 17800 mov r1, rSELF @ arg1 17801 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17802 17803/* ------------------------------ */ 17804 .balign 64 17805.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 17806/* File: armv5te/alt_stub.S */ 17807/* 17808 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17809 * any interesting requests and then jump to the real instruction 17810 * handler. Note that the call to dvmCheckInst is done as a tail call. 17811 */ 17812 adrl lr, dvmAsmInstructionStart + (291 * 64) 17813 mov r0, rPC @ arg0 17814 mov r1, rSELF @ arg1 17815 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17816 17817/* ------------------------------ */ 17818 .balign 64 17819.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 17820/* File: armv5te/alt_stub.S */ 17821/* 17822 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17823 * any interesting requests and then jump to the real instruction 17824 * handler. Note that the call to dvmCheckInst is done as a tail call. 17825 */ 17826 adrl lr, dvmAsmInstructionStart + (292 * 64) 17827 mov r0, rPC @ arg0 17828 mov r1, rSELF @ arg1 17829 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17830 17831/* ------------------------------ */ 17832 .balign 64 17833.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 17834/* File: armv5te/alt_stub.S */ 17835/* 17836 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17837 * any interesting requests and then jump to the real instruction 17838 * handler. Note that the call to dvmCheckInst is done as a tail call. 17839 */ 17840 adrl lr, dvmAsmInstructionStart + (293 * 64) 17841 mov r0, rPC @ arg0 17842 mov r1, rSELF @ arg1 17843 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17844 17845/* ------------------------------ */ 17846 .balign 64 17847.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 17848/* File: armv5te/alt_stub.S */ 17849/* 17850 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17851 * any interesting requests and then jump to the real instruction 17852 * handler. Note that the call to dvmCheckInst is done as a tail call. 17853 */ 17854 adrl lr, dvmAsmInstructionStart + (294 * 64) 17855 mov r0, rPC @ arg0 17856 mov r1, rSELF @ arg1 17857 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17858 17859/* ------------------------------ */ 17860 .balign 64 17861.L_ALT_OP_UNUSED_27FF: /* 0x127 */ 17862/* File: armv5te/alt_stub.S */ 17863/* 17864 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17865 * any interesting requests and then jump to the real instruction 17866 * handler. Note that the call to dvmCheckInst is done as a tail call. 17867 */ 17868 adrl lr, dvmAsmInstructionStart + (295 * 64) 17869 mov r0, rPC @ arg0 17870 mov r1, rSELF @ arg1 17871 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17872 17873/* ------------------------------ */ 17874 .balign 64 17875.L_ALT_OP_UNUSED_28FF: /* 0x128 */ 17876/* File: armv5te/alt_stub.S */ 17877/* 17878 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17879 * any interesting requests and then jump to the real instruction 17880 * handler. Note that the call to dvmCheckInst is done as a tail call. 17881 */ 17882 adrl lr, dvmAsmInstructionStart + (296 * 64) 17883 mov r0, rPC @ arg0 17884 mov r1, rSELF @ arg1 17885 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17886 17887/* ------------------------------ */ 17888 .balign 64 17889.L_ALT_OP_UNUSED_29FF: /* 0x129 */ 17890/* File: armv5te/alt_stub.S */ 17891/* 17892 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17893 * any interesting requests and then jump to the real instruction 17894 * handler. Note that the call to dvmCheckInst is done as a tail call. 17895 */ 17896 adrl lr, dvmAsmInstructionStart + (297 * 64) 17897 mov r0, rPC @ arg0 17898 mov r1, rSELF @ arg1 17899 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17900 17901/* ------------------------------ */ 17902 .balign 64 17903.L_ALT_OP_UNUSED_2AFF: /* 0x12a */ 17904/* File: armv5te/alt_stub.S */ 17905/* 17906 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17907 * any interesting requests and then jump to the real instruction 17908 * handler. Note that the call to dvmCheckInst is done as a tail call. 17909 */ 17910 adrl lr, dvmAsmInstructionStart + (298 * 64) 17911 mov r0, rPC @ arg0 17912 mov r1, rSELF @ arg1 17913 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17914 17915/* ------------------------------ */ 17916 .balign 64 17917.L_ALT_OP_UNUSED_2BFF: /* 0x12b */ 17918/* File: armv5te/alt_stub.S */ 17919/* 17920 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17921 * any interesting requests and then jump to the real instruction 17922 * handler. Note that the call to dvmCheckInst is done as a tail call. 17923 */ 17924 adrl lr, dvmAsmInstructionStart + (299 * 64) 17925 mov r0, rPC @ arg0 17926 mov r1, rSELF @ arg1 17927 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17928 17929/* ------------------------------ */ 17930 .balign 64 17931.L_ALT_OP_UNUSED_2CFF: /* 0x12c */ 17932/* File: armv5te/alt_stub.S */ 17933/* 17934 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17935 * any interesting requests and then jump to the real instruction 17936 * handler. Note that the call to dvmCheckInst is done as a tail call. 17937 */ 17938 adrl lr, dvmAsmInstructionStart + (300 * 64) 17939 mov r0, rPC @ arg0 17940 mov r1, rSELF @ arg1 17941 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17942 17943/* ------------------------------ */ 17944 .balign 64 17945.L_ALT_OP_UNUSED_2DFF: /* 0x12d */ 17946/* File: armv5te/alt_stub.S */ 17947/* 17948 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17949 * any interesting requests and then jump to the real instruction 17950 * handler. Note that the call to dvmCheckInst is done as a tail call. 17951 */ 17952 adrl lr, dvmAsmInstructionStart + (301 * 64) 17953 mov r0, rPC @ arg0 17954 mov r1, rSELF @ arg1 17955 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17956 17957/* ------------------------------ */ 17958 .balign 64 17959.L_ALT_OP_UNUSED_2EFF: /* 0x12e */ 17960/* File: armv5te/alt_stub.S */ 17961/* 17962 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17963 * any interesting requests and then jump to the real instruction 17964 * handler. Note that the call to dvmCheckInst is done as a tail call. 17965 */ 17966 adrl lr, dvmAsmInstructionStart + (302 * 64) 17967 mov r0, rPC @ arg0 17968 mov r1, rSELF @ arg1 17969 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17970 17971/* ------------------------------ */ 17972 .balign 64 17973.L_ALT_OP_UNUSED_2FFF: /* 0x12f */ 17974/* File: armv5te/alt_stub.S */ 17975/* 17976 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17977 * any interesting requests and then jump to the real instruction 17978 * handler. Note that the call to dvmCheckInst is done as a tail call. 17979 */ 17980 adrl lr, dvmAsmInstructionStart + (303 * 64) 17981 mov r0, rPC @ arg0 17982 mov r1, rSELF @ arg1 17983 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17984 17985/* ------------------------------ */ 17986 .balign 64 17987.L_ALT_OP_UNUSED_30FF: /* 0x130 */ 17988/* File: armv5te/alt_stub.S */ 17989/* 17990 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17991 * any interesting requests and then jump to the real instruction 17992 * handler. Note that the call to dvmCheckInst is done as a tail call. 17993 */ 17994 adrl lr, dvmAsmInstructionStart + (304 * 64) 17995 mov r0, rPC @ arg0 17996 mov r1, rSELF @ arg1 17997 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17998 17999/* ------------------------------ */ 18000 .balign 64 18001.L_ALT_OP_UNUSED_31FF: /* 0x131 */ 18002/* File: armv5te/alt_stub.S */ 18003/* 18004 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18005 * any interesting requests and then jump to the real instruction 18006 * handler. Note that the call to dvmCheckInst is done as a tail call. 18007 */ 18008 adrl lr, dvmAsmInstructionStart + (305 * 64) 18009 mov r0, rPC @ arg0 18010 mov r1, rSELF @ arg1 18011 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18012 18013/* ------------------------------ */ 18014 .balign 64 18015.L_ALT_OP_UNUSED_32FF: /* 0x132 */ 18016/* File: armv5te/alt_stub.S */ 18017/* 18018 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18019 * any interesting requests and then jump to the real instruction 18020 * handler. Note that the call to dvmCheckInst is done as a tail call. 18021 */ 18022 adrl lr, dvmAsmInstructionStart + (306 * 64) 18023 mov r0, rPC @ arg0 18024 mov r1, rSELF @ arg1 18025 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18026 18027/* ------------------------------ */ 18028 .balign 64 18029.L_ALT_OP_UNUSED_33FF: /* 0x133 */ 18030/* File: armv5te/alt_stub.S */ 18031/* 18032 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18033 * any interesting requests and then jump to the real instruction 18034 * handler. Note that the call to dvmCheckInst is done as a tail call. 18035 */ 18036 adrl lr, dvmAsmInstructionStart + (307 * 64) 18037 mov r0, rPC @ arg0 18038 mov r1, rSELF @ arg1 18039 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18040 18041/* ------------------------------ */ 18042 .balign 64 18043.L_ALT_OP_UNUSED_34FF: /* 0x134 */ 18044/* File: armv5te/alt_stub.S */ 18045/* 18046 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18047 * any interesting requests and then jump to the real instruction 18048 * handler. Note that the call to dvmCheckInst is done as a tail call. 18049 */ 18050 adrl lr, dvmAsmInstructionStart + (308 * 64) 18051 mov r0, rPC @ arg0 18052 mov r1, rSELF @ arg1 18053 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18054 18055/* ------------------------------ */ 18056 .balign 64 18057.L_ALT_OP_UNUSED_35FF: /* 0x135 */ 18058/* File: armv5te/alt_stub.S */ 18059/* 18060 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18061 * any interesting requests and then jump to the real instruction 18062 * handler. Note that the call to dvmCheckInst is done as a tail call. 18063 */ 18064 adrl lr, dvmAsmInstructionStart + (309 * 64) 18065 mov r0, rPC @ arg0 18066 mov r1, rSELF @ arg1 18067 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18068 18069/* ------------------------------ */ 18070 .balign 64 18071.L_ALT_OP_UNUSED_36FF: /* 0x136 */ 18072/* File: armv5te/alt_stub.S */ 18073/* 18074 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18075 * any interesting requests and then jump to the real instruction 18076 * handler. Note that the call to dvmCheckInst is done as a tail call. 18077 */ 18078 adrl lr, dvmAsmInstructionStart + (310 * 64) 18079 mov r0, rPC @ arg0 18080 mov r1, rSELF @ arg1 18081 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18082 18083/* ------------------------------ */ 18084 .balign 64 18085.L_ALT_OP_UNUSED_37FF: /* 0x137 */ 18086/* File: armv5te/alt_stub.S */ 18087/* 18088 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18089 * any interesting requests and then jump to the real instruction 18090 * handler. Note that the call to dvmCheckInst is done as a tail call. 18091 */ 18092 adrl lr, dvmAsmInstructionStart + (311 * 64) 18093 mov r0, rPC @ arg0 18094 mov r1, rSELF @ arg1 18095 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18096 18097/* ------------------------------ */ 18098 .balign 64 18099.L_ALT_OP_UNUSED_38FF: /* 0x138 */ 18100/* File: armv5te/alt_stub.S */ 18101/* 18102 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18103 * any interesting requests and then jump to the real instruction 18104 * handler. Note that the call to dvmCheckInst is done as a tail call. 18105 */ 18106 adrl lr, dvmAsmInstructionStart + (312 * 64) 18107 mov r0, rPC @ arg0 18108 mov r1, rSELF @ arg1 18109 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18110 18111/* ------------------------------ */ 18112 .balign 64 18113.L_ALT_OP_UNUSED_39FF: /* 0x139 */ 18114/* File: armv5te/alt_stub.S */ 18115/* 18116 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18117 * any interesting requests and then jump to the real instruction 18118 * handler. Note that the call to dvmCheckInst is done as a tail call. 18119 */ 18120 adrl lr, dvmAsmInstructionStart + (313 * 64) 18121 mov r0, rPC @ arg0 18122 mov r1, rSELF @ arg1 18123 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18124 18125/* ------------------------------ */ 18126 .balign 64 18127.L_ALT_OP_UNUSED_3AFF: /* 0x13a */ 18128/* File: armv5te/alt_stub.S */ 18129/* 18130 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18131 * any interesting requests and then jump to the real instruction 18132 * handler. Note that the call to dvmCheckInst is done as a tail call. 18133 */ 18134 adrl lr, dvmAsmInstructionStart + (314 * 64) 18135 mov r0, rPC @ arg0 18136 mov r1, rSELF @ arg1 18137 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18138 18139/* ------------------------------ */ 18140 .balign 64 18141.L_ALT_OP_UNUSED_3BFF: /* 0x13b */ 18142/* File: armv5te/alt_stub.S */ 18143/* 18144 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18145 * any interesting requests and then jump to the real instruction 18146 * handler. Note that the call to dvmCheckInst is done as a tail call. 18147 */ 18148 adrl lr, dvmAsmInstructionStart + (315 * 64) 18149 mov r0, rPC @ arg0 18150 mov r1, rSELF @ arg1 18151 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18152 18153/* ------------------------------ */ 18154 .balign 64 18155.L_ALT_OP_UNUSED_3CFF: /* 0x13c */ 18156/* File: armv5te/alt_stub.S */ 18157/* 18158 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18159 * any interesting requests and then jump to the real instruction 18160 * handler. Note that the call to dvmCheckInst is done as a tail call. 18161 */ 18162 adrl lr, dvmAsmInstructionStart + (316 * 64) 18163 mov r0, rPC @ arg0 18164 mov r1, rSELF @ arg1 18165 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18166 18167/* ------------------------------ */ 18168 .balign 64 18169.L_ALT_OP_UNUSED_3DFF: /* 0x13d */ 18170/* File: armv5te/alt_stub.S */ 18171/* 18172 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18173 * any interesting requests and then jump to the real instruction 18174 * handler. Note that the call to dvmCheckInst is done as a tail call. 18175 */ 18176 adrl lr, dvmAsmInstructionStart + (317 * 64) 18177 mov r0, rPC @ arg0 18178 mov r1, rSELF @ arg1 18179 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18180 18181/* ------------------------------ */ 18182 .balign 64 18183.L_ALT_OP_UNUSED_3EFF: /* 0x13e */ 18184/* File: armv5te/alt_stub.S */ 18185/* 18186 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18187 * any interesting requests and then jump to the real instruction 18188 * handler. Note that the call to dvmCheckInst is done as a tail call. 18189 */ 18190 adrl lr, dvmAsmInstructionStart + (318 * 64) 18191 mov r0, rPC @ arg0 18192 mov r1, rSELF @ arg1 18193 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18194 18195/* ------------------------------ */ 18196 .balign 64 18197.L_ALT_OP_UNUSED_3FFF: /* 0x13f */ 18198/* File: armv5te/alt_stub.S */ 18199/* 18200 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18201 * any interesting requests and then jump to the real instruction 18202 * handler. Note that the call to dvmCheckInst is done as a tail call. 18203 */ 18204 adrl lr, dvmAsmInstructionStart + (319 * 64) 18205 mov r0, rPC @ arg0 18206 mov r1, rSELF @ arg1 18207 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18208 18209/* ------------------------------ */ 18210 .balign 64 18211.L_ALT_OP_UNUSED_40FF: /* 0x140 */ 18212/* File: armv5te/alt_stub.S */ 18213/* 18214 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18215 * any interesting requests and then jump to the real instruction 18216 * handler. Note that the call to dvmCheckInst is done as a tail call. 18217 */ 18218 adrl lr, dvmAsmInstructionStart + (320 * 64) 18219 mov r0, rPC @ arg0 18220 mov r1, rSELF @ arg1 18221 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18222 18223/* ------------------------------ */ 18224 .balign 64 18225.L_ALT_OP_UNUSED_41FF: /* 0x141 */ 18226/* File: armv5te/alt_stub.S */ 18227/* 18228 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18229 * any interesting requests and then jump to the real instruction 18230 * handler. Note that the call to dvmCheckInst is done as a tail call. 18231 */ 18232 adrl lr, dvmAsmInstructionStart + (321 * 64) 18233 mov r0, rPC @ arg0 18234 mov r1, rSELF @ arg1 18235 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18236 18237/* ------------------------------ */ 18238 .balign 64 18239.L_ALT_OP_UNUSED_42FF: /* 0x142 */ 18240/* File: armv5te/alt_stub.S */ 18241/* 18242 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18243 * any interesting requests and then jump to the real instruction 18244 * handler. Note that the call to dvmCheckInst is done as a tail call. 18245 */ 18246 adrl lr, dvmAsmInstructionStart + (322 * 64) 18247 mov r0, rPC @ arg0 18248 mov r1, rSELF @ arg1 18249 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18250 18251/* ------------------------------ */ 18252 .balign 64 18253.L_ALT_OP_UNUSED_43FF: /* 0x143 */ 18254/* File: armv5te/alt_stub.S */ 18255/* 18256 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18257 * any interesting requests and then jump to the real instruction 18258 * handler. Note that the call to dvmCheckInst is done as a tail call. 18259 */ 18260 adrl lr, dvmAsmInstructionStart + (323 * 64) 18261 mov r0, rPC @ arg0 18262 mov r1, rSELF @ arg1 18263 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18264 18265/* ------------------------------ */ 18266 .balign 64 18267.L_ALT_OP_UNUSED_44FF: /* 0x144 */ 18268/* File: armv5te/alt_stub.S */ 18269/* 18270 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18271 * any interesting requests and then jump to the real instruction 18272 * handler. Note that the call to dvmCheckInst is done as a tail call. 18273 */ 18274 adrl lr, dvmAsmInstructionStart + (324 * 64) 18275 mov r0, rPC @ arg0 18276 mov r1, rSELF @ arg1 18277 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18278 18279/* ------------------------------ */ 18280 .balign 64 18281.L_ALT_OP_UNUSED_45FF: /* 0x145 */ 18282/* File: armv5te/alt_stub.S */ 18283/* 18284 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18285 * any interesting requests and then jump to the real instruction 18286 * handler. Note that the call to dvmCheckInst is done as a tail call. 18287 */ 18288 adrl lr, dvmAsmInstructionStart + (325 * 64) 18289 mov r0, rPC @ arg0 18290 mov r1, rSELF @ arg1 18291 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18292 18293/* ------------------------------ */ 18294 .balign 64 18295.L_ALT_OP_UNUSED_46FF: /* 0x146 */ 18296/* File: armv5te/alt_stub.S */ 18297/* 18298 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18299 * any interesting requests and then jump to the real instruction 18300 * handler. Note that the call to dvmCheckInst is done as a tail call. 18301 */ 18302 adrl lr, dvmAsmInstructionStart + (326 * 64) 18303 mov r0, rPC @ arg0 18304 mov r1, rSELF @ arg1 18305 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18306 18307/* ------------------------------ */ 18308 .balign 64 18309.L_ALT_OP_UNUSED_47FF: /* 0x147 */ 18310/* File: armv5te/alt_stub.S */ 18311/* 18312 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18313 * any interesting requests and then jump to the real instruction 18314 * handler. Note that the call to dvmCheckInst is done as a tail call. 18315 */ 18316 adrl lr, dvmAsmInstructionStart + (327 * 64) 18317 mov r0, rPC @ arg0 18318 mov r1, rSELF @ arg1 18319 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18320 18321/* ------------------------------ */ 18322 .balign 64 18323.L_ALT_OP_UNUSED_48FF: /* 0x148 */ 18324/* File: armv5te/alt_stub.S */ 18325/* 18326 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18327 * any interesting requests and then jump to the real instruction 18328 * handler. Note that the call to dvmCheckInst is done as a tail call. 18329 */ 18330 adrl lr, dvmAsmInstructionStart + (328 * 64) 18331 mov r0, rPC @ arg0 18332 mov r1, rSELF @ arg1 18333 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18334 18335/* ------------------------------ */ 18336 .balign 64 18337.L_ALT_OP_UNUSED_49FF: /* 0x149 */ 18338/* File: armv5te/alt_stub.S */ 18339/* 18340 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18341 * any interesting requests and then jump to the real instruction 18342 * handler. Note that the call to dvmCheckInst is done as a tail call. 18343 */ 18344 adrl lr, dvmAsmInstructionStart + (329 * 64) 18345 mov r0, rPC @ arg0 18346 mov r1, rSELF @ arg1 18347 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18348 18349/* ------------------------------ */ 18350 .balign 64 18351.L_ALT_OP_UNUSED_4AFF: /* 0x14a */ 18352/* File: armv5te/alt_stub.S */ 18353/* 18354 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18355 * any interesting requests and then jump to the real instruction 18356 * handler. Note that the call to dvmCheckInst is done as a tail call. 18357 */ 18358 adrl lr, dvmAsmInstructionStart + (330 * 64) 18359 mov r0, rPC @ arg0 18360 mov r1, rSELF @ arg1 18361 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18362 18363/* ------------------------------ */ 18364 .balign 64 18365.L_ALT_OP_UNUSED_4BFF: /* 0x14b */ 18366/* File: armv5te/alt_stub.S */ 18367/* 18368 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18369 * any interesting requests and then jump to the real instruction 18370 * handler. Note that the call to dvmCheckInst is done as a tail call. 18371 */ 18372 adrl lr, dvmAsmInstructionStart + (331 * 64) 18373 mov r0, rPC @ arg0 18374 mov r1, rSELF @ arg1 18375 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18376 18377/* ------------------------------ */ 18378 .balign 64 18379.L_ALT_OP_UNUSED_4CFF: /* 0x14c */ 18380/* File: armv5te/alt_stub.S */ 18381/* 18382 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18383 * any interesting requests and then jump to the real instruction 18384 * handler. Note that the call to dvmCheckInst is done as a tail call. 18385 */ 18386 adrl lr, dvmAsmInstructionStart + (332 * 64) 18387 mov r0, rPC @ arg0 18388 mov r1, rSELF @ arg1 18389 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18390 18391/* ------------------------------ */ 18392 .balign 64 18393.L_ALT_OP_UNUSED_4DFF: /* 0x14d */ 18394/* File: armv5te/alt_stub.S */ 18395/* 18396 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18397 * any interesting requests and then jump to the real instruction 18398 * handler. Note that the call to dvmCheckInst is done as a tail call. 18399 */ 18400 adrl lr, dvmAsmInstructionStart + (333 * 64) 18401 mov r0, rPC @ arg0 18402 mov r1, rSELF @ arg1 18403 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18404 18405/* ------------------------------ */ 18406 .balign 64 18407.L_ALT_OP_UNUSED_4EFF: /* 0x14e */ 18408/* File: armv5te/alt_stub.S */ 18409/* 18410 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18411 * any interesting requests and then jump to the real instruction 18412 * handler. Note that the call to dvmCheckInst is done as a tail call. 18413 */ 18414 adrl lr, dvmAsmInstructionStart + (334 * 64) 18415 mov r0, rPC @ arg0 18416 mov r1, rSELF @ arg1 18417 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18418 18419/* ------------------------------ */ 18420 .balign 64 18421.L_ALT_OP_UNUSED_4FFF: /* 0x14f */ 18422/* File: armv5te/alt_stub.S */ 18423/* 18424 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18425 * any interesting requests and then jump to the real instruction 18426 * handler. Note that the call to dvmCheckInst is done as a tail call. 18427 */ 18428 adrl lr, dvmAsmInstructionStart + (335 * 64) 18429 mov r0, rPC @ arg0 18430 mov r1, rSELF @ arg1 18431 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18432 18433/* ------------------------------ */ 18434 .balign 64 18435.L_ALT_OP_UNUSED_50FF: /* 0x150 */ 18436/* File: armv5te/alt_stub.S */ 18437/* 18438 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18439 * any interesting requests and then jump to the real instruction 18440 * handler. Note that the call to dvmCheckInst is done as a tail call. 18441 */ 18442 adrl lr, dvmAsmInstructionStart + (336 * 64) 18443 mov r0, rPC @ arg0 18444 mov r1, rSELF @ arg1 18445 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18446 18447/* ------------------------------ */ 18448 .balign 64 18449.L_ALT_OP_UNUSED_51FF: /* 0x151 */ 18450/* File: armv5te/alt_stub.S */ 18451/* 18452 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18453 * any interesting requests and then jump to the real instruction 18454 * handler. Note that the call to dvmCheckInst is done as a tail call. 18455 */ 18456 adrl lr, dvmAsmInstructionStart + (337 * 64) 18457 mov r0, rPC @ arg0 18458 mov r1, rSELF @ arg1 18459 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18460 18461/* ------------------------------ */ 18462 .balign 64 18463.L_ALT_OP_UNUSED_52FF: /* 0x152 */ 18464/* File: armv5te/alt_stub.S */ 18465/* 18466 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18467 * any interesting requests and then jump to the real instruction 18468 * handler. Note that the call to dvmCheckInst is done as a tail call. 18469 */ 18470 adrl lr, dvmAsmInstructionStart + (338 * 64) 18471 mov r0, rPC @ arg0 18472 mov r1, rSELF @ arg1 18473 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18474 18475/* ------------------------------ */ 18476 .balign 64 18477.L_ALT_OP_UNUSED_53FF: /* 0x153 */ 18478/* File: armv5te/alt_stub.S */ 18479/* 18480 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18481 * any interesting requests and then jump to the real instruction 18482 * handler. Note that the call to dvmCheckInst is done as a tail call. 18483 */ 18484 adrl lr, dvmAsmInstructionStart + (339 * 64) 18485 mov r0, rPC @ arg0 18486 mov r1, rSELF @ arg1 18487 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18488 18489/* ------------------------------ */ 18490 .balign 64 18491.L_ALT_OP_UNUSED_54FF: /* 0x154 */ 18492/* File: armv5te/alt_stub.S */ 18493/* 18494 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18495 * any interesting requests and then jump to the real instruction 18496 * handler. Note that the call to dvmCheckInst is done as a tail call. 18497 */ 18498 adrl lr, dvmAsmInstructionStart + (340 * 64) 18499 mov r0, rPC @ arg0 18500 mov r1, rSELF @ arg1 18501 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18502 18503/* ------------------------------ */ 18504 .balign 64 18505.L_ALT_OP_UNUSED_55FF: /* 0x155 */ 18506/* File: armv5te/alt_stub.S */ 18507/* 18508 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18509 * any interesting requests and then jump to the real instruction 18510 * handler. Note that the call to dvmCheckInst is done as a tail call. 18511 */ 18512 adrl lr, dvmAsmInstructionStart + (341 * 64) 18513 mov r0, rPC @ arg0 18514 mov r1, rSELF @ arg1 18515 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18516 18517/* ------------------------------ */ 18518 .balign 64 18519.L_ALT_OP_UNUSED_56FF: /* 0x156 */ 18520/* File: armv5te/alt_stub.S */ 18521/* 18522 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18523 * any interesting requests and then jump to the real instruction 18524 * handler. Note that the call to dvmCheckInst is done as a tail call. 18525 */ 18526 adrl lr, dvmAsmInstructionStart + (342 * 64) 18527 mov r0, rPC @ arg0 18528 mov r1, rSELF @ arg1 18529 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18530 18531/* ------------------------------ */ 18532 .balign 64 18533.L_ALT_OP_UNUSED_57FF: /* 0x157 */ 18534/* File: armv5te/alt_stub.S */ 18535/* 18536 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18537 * any interesting requests and then jump to the real instruction 18538 * handler. Note that the call to dvmCheckInst is done as a tail call. 18539 */ 18540 adrl lr, dvmAsmInstructionStart + (343 * 64) 18541 mov r0, rPC @ arg0 18542 mov r1, rSELF @ arg1 18543 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18544 18545/* ------------------------------ */ 18546 .balign 64 18547.L_ALT_OP_UNUSED_58FF: /* 0x158 */ 18548/* File: armv5te/alt_stub.S */ 18549/* 18550 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18551 * any interesting requests and then jump to the real instruction 18552 * handler. Note that the call to dvmCheckInst is done as a tail call. 18553 */ 18554 adrl lr, dvmAsmInstructionStart + (344 * 64) 18555 mov r0, rPC @ arg0 18556 mov r1, rSELF @ arg1 18557 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18558 18559/* ------------------------------ */ 18560 .balign 64 18561.L_ALT_OP_UNUSED_59FF: /* 0x159 */ 18562/* File: armv5te/alt_stub.S */ 18563/* 18564 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18565 * any interesting requests and then jump to the real instruction 18566 * handler. Note that the call to dvmCheckInst is done as a tail call. 18567 */ 18568 adrl lr, dvmAsmInstructionStart + (345 * 64) 18569 mov r0, rPC @ arg0 18570 mov r1, rSELF @ arg1 18571 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18572 18573/* ------------------------------ */ 18574 .balign 64 18575.L_ALT_OP_UNUSED_5AFF: /* 0x15a */ 18576/* File: armv5te/alt_stub.S */ 18577/* 18578 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18579 * any interesting requests and then jump to the real instruction 18580 * handler. Note that the call to dvmCheckInst is done as a tail call. 18581 */ 18582 adrl lr, dvmAsmInstructionStart + (346 * 64) 18583 mov r0, rPC @ arg0 18584 mov r1, rSELF @ arg1 18585 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18586 18587/* ------------------------------ */ 18588 .balign 64 18589.L_ALT_OP_UNUSED_5BFF: /* 0x15b */ 18590/* File: armv5te/alt_stub.S */ 18591/* 18592 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18593 * any interesting requests and then jump to the real instruction 18594 * handler. Note that the call to dvmCheckInst is done as a tail call. 18595 */ 18596 adrl lr, dvmAsmInstructionStart + (347 * 64) 18597 mov r0, rPC @ arg0 18598 mov r1, rSELF @ arg1 18599 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18600 18601/* ------------------------------ */ 18602 .balign 64 18603.L_ALT_OP_UNUSED_5CFF: /* 0x15c */ 18604/* File: armv5te/alt_stub.S */ 18605/* 18606 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18607 * any interesting requests and then jump to the real instruction 18608 * handler. Note that the call to dvmCheckInst is done as a tail call. 18609 */ 18610 adrl lr, dvmAsmInstructionStart + (348 * 64) 18611 mov r0, rPC @ arg0 18612 mov r1, rSELF @ arg1 18613 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18614 18615/* ------------------------------ */ 18616 .balign 64 18617.L_ALT_OP_UNUSED_5DFF: /* 0x15d */ 18618/* File: armv5te/alt_stub.S */ 18619/* 18620 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18621 * any interesting requests and then jump to the real instruction 18622 * handler. Note that the call to dvmCheckInst is done as a tail call. 18623 */ 18624 adrl lr, dvmAsmInstructionStart + (349 * 64) 18625 mov r0, rPC @ arg0 18626 mov r1, rSELF @ arg1 18627 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18628 18629/* ------------------------------ */ 18630 .balign 64 18631.L_ALT_OP_UNUSED_5EFF: /* 0x15e */ 18632/* File: armv5te/alt_stub.S */ 18633/* 18634 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18635 * any interesting requests and then jump to the real instruction 18636 * handler. Note that the call to dvmCheckInst is done as a tail call. 18637 */ 18638 adrl lr, dvmAsmInstructionStart + (350 * 64) 18639 mov r0, rPC @ arg0 18640 mov r1, rSELF @ arg1 18641 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18642 18643/* ------------------------------ */ 18644 .balign 64 18645.L_ALT_OP_UNUSED_5FFF: /* 0x15f */ 18646/* File: armv5te/alt_stub.S */ 18647/* 18648 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18649 * any interesting requests and then jump to the real instruction 18650 * handler. Note that the call to dvmCheckInst is done as a tail call. 18651 */ 18652 adrl lr, dvmAsmInstructionStart + (351 * 64) 18653 mov r0, rPC @ arg0 18654 mov r1, rSELF @ arg1 18655 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18656 18657/* ------------------------------ */ 18658 .balign 64 18659.L_ALT_OP_UNUSED_60FF: /* 0x160 */ 18660/* File: armv5te/alt_stub.S */ 18661/* 18662 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18663 * any interesting requests and then jump to the real instruction 18664 * handler. Note that the call to dvmCheckInst is done as a tail call. 18665 */ 18666 adrl lr, dvmAsmInstructionStart + (352 * 64) 18667 mov r0, rPC @ arg0 18668 mov r1, rSELF @ arg1 18669 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18670 18671/* ------------------------------ */ 18672 .balign 64 18673.L_ALT_OP_UNUSED_61FF: /* 0x161 */ 18674/* File: armv5te/alt_stub.S */ 18675/* 18676 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18677 * any interesting requests and then jump to the real instruction 18678 * handler. Note that the call to dvmCheckInst is done as a tail call. 18679 */ 18680 adrl lr, dvmAsmInstructionStart + (353 * 64) 18681 mov r0, rPC @ arg0 18682 mov r1, rSELF @ arg1 18683 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18684 18685/* ------------------------------ */ 18686 .balign 64 18687.L_ALT_OP_UNUSED_62FF: /* 0x162 */ 18688/* File: armv5te/alt_stub.S */ 18689/* 18690 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18691 * any interesting requests and then jump to the real instruction 18692 * handler. Note that the call to dvmCheckInst is done as a tail call. 18693 */ 18694 adrl lr, dvmAsmInstructionStart + (354 * 64) 18695 mov r0, rPC @ arg0 18696 mov r1, rSELF @ arg1 18697 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18698 18699/* ------------------------------ */ 18700 .balign 64 18701.L_ALT_OP_UNUSED_63FF: /* 0x163 */ 18702/* File: armv5te/alt_stub.S */ 18703/* 18704 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18705 * any interesting requests and then jump to the real instruction 18706 * handler. Note that the call to dvmCheckInst is done as a tail call. 18707 */ 18708 adrl lr, dvmAsmInstructionStart + (355 * 64) 18709 mov r0, rPC @ arg0 18710 mov r1, rSELF @ arg1 18711 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18712 18713/* ------------------------------ */ 18714 .balign 64 18715.L_ALT_OP_UNUSED_64FF: /* 0x164 */ 18716/* File: armv5te/alt_stub.S */ 18717/* 18718 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18719 * any interesting requests and then jump to the real instruction 18720 * handler. Note that the call to dvmCheckInst is done as a tail call. 18721 */ 18722 adrl lr, dvmAsmInstructionStart + (356 * 64) 18723 mov r0, rPC @ arg0 18724 mov r1, rSELF @ arg1 18725 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18726 18727/* ------------------------------ */ 18728 .balign 64 18729.L_ALT_OP_UNUSED_65FF: /* 0x165 */ 18730/* File: armv5te/alt_stub.S */ 18731/* 18732 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18733 * any interesting requests and then jump to the real instruction 18734 * handler. Note that the call to dvmCheckInst is done as a tail call. 18735 */ 18736 adrl lr, dvmAsmInstructionStart + (357 * 64) 18737 mov r0, rPC @ arg0 18738 mov r1, rSELF @ arg1 18739 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18740 18741/* ------------------------------ */ 18742 .balign 64 18743.L_ALT_OP_UNUSED_66FF: /* 0x166 */ 18744/* File: armv5te/alt_stub.S */ 18745/* 18746 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18747 * any interesting requests and then jump to the real instruction 18748 * handler. Note that the call to dvmCheckInst is done as a tail call. 18749 */ 18750 adrl lr, dvmAsmInstructionStart + (358 * 64) 18751 mov r0, rPC @ arg0 18752 mov r1, rSELF @ arg1 18753 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18754 18755/* ------------------------------ */ 18756 .balign 64 18757.L_ALT_OP_UNUSED_67FF: /* 0x167 */ 18758/* File: armv5te/alt_stub.S */ 18759/* 18760 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18761 * any interesting requests and then jump to the real instruction 18762 * handler. Note that the call to dvmCheckInst is done as a tail call. 18763 */ 18764 adrl lr, dvmAsmInstructionStart + (359 * 64) 18765 mov r0, rPC @ arg0 18766 mov r1, rSELF @ arg1 18767 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18768 18769/* ------------------------------ */ 18770 .balign 64 18771.L_ALT_OP_UNUSED_68FF: /* 0x168 */ 18772/* File: armv5te/alt_stub.S */ 18773/* 18774 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18775 * any interesting requests and then jump to the real instruction 18776 * handler. Note that the call to dvmCheckInst is done as a tail call. 18777 */ 18778 adrl lr, dvmAsmInstructionStart + (360 * 64) 18779 mov r0, rPC @ arg0 18780 mov r1, rSELF @ arg1 18781 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18782 18783/* ------------------------------ */ 18784 .balign 64 18785.L_ALT_OP_UNUSED_69FF: /* 0x169 */ 18786/* File: armv5te/alt_stub.S */ 18787/* 18788 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18789 * any interesting requests and then jump to the real instruction 18790 * handler. Note that the call to dvmCheckInst is done as a tail call. 18791 */ 18792 adrl lr, dvmAsmInstructionStart + (361 * 64) 18793 mov r0, rPC @ arg0 18794 mov r1, rSELF @ arg1 18795 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18796 18797/* ------------------------------ */ 18798 .balign 64 18799.L_ALT_OP_UNUSED_6AFF: /* 0x16a */ 18800/* File: armv5te/alt_stub.S */ 18801/* 18802 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18803 * any interesting requests and then jump to the real instruction 18804 * handler. Note that the call to dvmCheckInst is done as a tail call. 18805 */ 18806 adrl lr, dvmAsmInstructionStart + (362 * 64) 18807 mov r0, rPC @ arg0 18808 mov r1, rSELF @ arg1 18809 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18810 18811/* ------------------------------ */ 18812 .balign 64 18813.L_ALT_OP_UNUSED_6BFF: /* 0x16b */ 18814/* File: armv5te/alt_stub.S */ 18815/* 18816 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18817 * any interesting requests and then jump to the real instruction 18818 * handler. Note that the call to dvmCheckInst is done as a tail call. 18819 */ 18820 adrl lr, dvmAsmInstructionStart + (363 * 64) 18821 mov r0, rPC @ arg0 18822 mov r1, rSELF @ arg1 18823 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18824 18825/* ------------------------------ */ 18826 .balign 64 18827.L_ALT_OP_UNUSED_6CFF: /* 0x16c */ 18828/* File: armv5te/alt_stub.S */ 18829/* 18830 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18831 * any interesting requests and then jump to the real instruction 18832 * handler. Note that the call to dvmCheckInst is done as a tail call. 18833 */ 18834 adrl lr, dvmAsmInstructionStart + (364 * 64) 18835 mov r0, rPC @ arg0 18836 mov r1, rSELF @ arg1 18837 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18838 18839/* ------------------------------ */ 18840 .balign 64 18841.L_ALT_OP_UNUSED_6DFF: /* 0x16d */ 18842/* File: armv5te/alt_stub.S */ 18843/* 18844 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18845 * any interesting requests and then jump to the real instruction 18846 * handler. Note that the call to dvmCheckInst is done as a tail call. 18847 */ 18848 adrl lr, dvmAsmInstructionStart + (365 * 64) 18849 mov r0, rPC @ arg0 18850 mov r1, rSELF @ arg1 18851 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18852 18853/* ------------------------------ */ 18854 .balign 64 18855.L_ALT_OP_UNUSED_6EFF: /* 0x16e */ 18856/* File: armv5te/alt_stub.S */ 18857/* 18858 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18859 * any interesting requests and then jump to the real instruction 18860 * handler. Note that the call to dvmCheckInst is done as a tail call. 18861 */ 18862 adrl lr, dvmAsmInstructionStart + (366 * 64) 18863 mov r0, rPC @ arg0 18864 mov r1, rSELF @ arg1 18865 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18866 18867/* ------------------------------ */ 18868 .balign 64 18869.L_ALT_OP_UNUSED_6FFF: /* 0x16f */ 18870/* File: armv5te/alt_stub.S */ 18871/* 18872 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18873 * any interesting requests and then jump to the real instruction 18874 * handler. Note that the call to dvmCheckInst is done as a tail call. 18875 */ 18876 adrl lr, dvmAsmInstructionStart + (367 * 64) 18877 mov r0, rPC @ arg0 18878 mov r1, rSELF @ arg1 18879 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18880 18881/* ------------------------------ */ 18882 .balign 64 18883.L_ALT_OP_UNUSED_70FF: /* 0x170 */ 18884/* File: armv5te/alt_stub.S */ 18885/* 18886 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18887 * any interesting requests and then jump to the real instruction 18888 * handler. Note that the call to dvmCheckInst is done as a tail call. 18889 */ 18890 adrl lr, dvmAsmInstructionStart + (368 * 64) 18891 mov r0, rPC @ arg0 18892 mov r1, rSELF @ arg1 18893 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18894 18895/* ------------------------------ */ 18896 .balign 64 18897.L_ALT_OP_UNUSED_71FF: /* 0x171 */ 18898/* File: armv5te/alt_stub.S */ 18899/* 18900 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18901 * any interesting requests and then jump to the real instruction 18902 * handler. Note that the call to dvmCheckInst is done as a tail call. 18903 */ 18904 adrl lr, dvmAsmInstructionStart + (369 * 64) 18905 mov r0, rPC @ arg0 18906 mov r1, rSELF @ arg1 18907 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18908 18909/* ------------------------------ */ 18910 .balign 64 18911.L_ALT_OP_UNUSED_72FF: /* 0x172 */ 18912/* File: armv5te/alt_stub.S */ 18913/* 18914 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18915 * any interesting requests and then jump to the real instruction 18916 * handler. Note that the call to dvmCheckInst is done as a tail call. 18917 */ 18918 adrl lr, dvmAsmInstructionStart + (370 * 64) 18919 mov r0, rPC @ arg0 18920 mov r1, rSELF @ arg1 18921 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18922 18923/* ------------------------------ */ 18924 .balign 64 18925.L_ALT_OP_UNUSED_73FF: /* 0x173 */ 18926/* File: armv5te/alt_stub.S */ 18927/* 18928 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18929 * any interesting requests and then jump to the real instruction 18930 * handler. Note that the call to dvmCheckInst is done as a tail call. 18931 */ 18932 adrl lr, dvmAsmInstructionStart + (371 * 64) 18933 mov r0, rPC @ arg0 18934 mov r1, rSELF @ arg1 18935 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18936 18937/* ------------------------------ */ 18938 .balign 64 18939.L_ALT_OP_UNUSED_74FF: /* 0x174 */ 18940/* File: armv5te/alt_stub.S */ 18941/* 18942 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18943 * any interesting requests and then jump to the real instruction 18944 * handler. Note that the call to dvmCheckInst is done as a tail call. 18945 */ 18946 adrl lr, dvmAsmInstructionStart + (372 * 64) 18947 mov r0, rPC @ arg0 18948 mov r1, rSELF @ arg1 18949 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18950 18951/* ------------------------------ */ 18952 .balign 64 18953.L_ALT_OP_UNUSED_75FF: /* 0x175 */ 18954/* File: armv5te/alt_stub.S */ 18955/* 18956 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18957 * any interesting requests and then jump to the real instruction 18958 * handler. Note that the call to dvmCheckInst is done as a tail call. 18959 */ 18960 adrl lr, dvmAsmInstructionStart + (373 * 64) 18961 mov r0, rPC @ arg0 18962 mov r1, rSELF @ arg1 18963 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18964 18965/* ------------------------------ */ 18966 .balign 64 18967.L_ALT_OP_UNUSED_76FF: /* 0x176 */ 18968/* File: armv5te/alt_stub.S */ 18969/* 18970 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18971 * any interesting requests and then jump to the real instruction 18972 * handler. Note that the call to dvmCheckInst is done as a tail call. 18973 */ 18974 adrl lr, dvmAsmInstructionStart + (374 * 64) 18975 mov r0, rPC @ arg0 18976 mov r1, rSELF @ arg1 18977 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18978 18979/* ------------------------------ */ 18980 .balign 64 18981.L_ALT_OP_UNUSED_77FF: /* 0x177 */ 18982/* File: armv5te/alt_stub.S */ 18983/* 18984 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18985 * any interesting requests and then jump to the real instruction 18986 * handler. Note that the call to dvmCheckInst is done as a tail call. 18987 */ 18988 adrl lr, dvmAsmInstructionStart + (375 * 64) 18989 mov r0, rPC @ arg0 18990 mov r1, rSELF @ arg1 18991 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18992 18993/* ------------------------------ */ 18994 .balign 64 18995.L_ALT_OP_UNUSED_78FF: /* 0x178 */ 18996/* File: armv5te/alt_stub.S */ 18997/* 18998 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18999 * any interesting requests and then jump to the real instruction 19000 * handler. Note that the call to dvmCheckInst is done as a tail call. 19001 */ 19002 adrl lr, dvmAsmInstructionStart + (376 * 64) 19003 mov r0, rPC @ arg0 19004 mov r1, rSELF @ arg1 19005 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19006 19007/* ------------------------------ */ 19008 .balign 64 19009.L_ALT_OP_UNUSED_79FF: /* 0x179 */ 19010/* File: armv5te/alt_stub.S */ 19011/* 19012 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19013 * any interesting requests and then jump to the real instruction 19014 * handler. Note that the call to dvmCheckInst is done as a tail call. 19015 */ 19016 adrl lr, dvmAsmInstructionStart + (377 * 64) 19017 mov r0, rPC @ arg0 19018 mov r1, rSELF @ arg1 19019 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19020 19021/* ------------------------------ */ 19022 .balign 64 19023.L_ALT_OP_UNUSED_7AFF: /* 0x17a */ 19024/* File: armv5te/alt_stub.S */ 19025/* 19026 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19027 * any interesting requests and then jump to the real instruction 19028 * handler. Note that the call to dvmCheckInst is done as a tail call. 19029 */ 19030 adrl lr, dvmAsmInstructionStart + (378 * 64) 19031 mov r0, rPC @ arg0 19032 mov r1, rSELF @ arg1 19033 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19034 19035/* ------------------------------ */ 19036 .balign 64 19037.L_ALT_OP_UNUSED_7BFF: /* 0x17b */ 19038/* File: armv5te/alt_stub.S */ 19039/* 19040 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19041 * any interesting requests and then jump to the real instruction 19042 * handler. Note that the call to dvmCheckInst is done as a tail call. 19043 */ 19044 adrl lr, dvmAsmInstructionStart + (379 * 64) 19045 mov r0, rPC @ arg0 19046 mov r1, rSELF @ arg1 19047 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19048 19049/* ------------------------------ */ 19050 .balign 64 19051.L_ALT_OP_UNUSED_7CFF: /* 0x17c */ 19052/* File: armv5te/alt_stub.S */ 19053/* 19054 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19055 * any interesting requests and then jump to the real instruction 19056 * handler. Note that the call to dvmCheckInst is done as a tail call. 19057 */ 19058 adrl lr, dvmAsmInstructionStart + (380 * 64) 19059 mov r0, rPC @ arg0 19060 mov r1, rSELF @ arg1 19061 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19062 19063/* ------------------------------ */ 19064 .balign 64 19065.L_ALT_OP_UNUSED_7DFF: /* 0x17d */ 19066/* File: armv5te/alt_stub.S */ 19067/* 19068 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19069 * any interesting requests and then jump to the real instruction 19070 * handler. Note that the call to dvmCheckInst is done as a tail call. 19071 */ 19072 adrl lr, dvmAsmInstructionStart + (381 * 64) 19073 mov r0, rPC @ arg0 19074 mov r1, rSELF @ arg1 19075 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19076 19077/* ------------------------------ */ 19078 .balign 64 19079.L_ALT_OP_UNUSED_7EFF: /* 0x17e */ 19080/* File: armv5te/alt_stub.S */ 19081/* 19082 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19083 * any interesting requests and then jump to the real instruction 19084 * handler. Note that the call to dvmCheckInst is done as a tail call. 19085 */ 19086 adrl lr, dvmAsmInstructionStart + (382 * 64) 19087 mov r0, rPC @ arg0 19088 mov r1, rSELF @ arg1 19089 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19090 19091/* ------------------------------ */ 19092 .balign 64 19093.L_ALT_OP_UNUSED_7FFF: /* 0x17f */ 19094/* File: armv5te/alt_stub.S */ 19095/* 19096 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19097 * any interesting requests and then jump to the real instruction 19098 * handler. Note that the call to dvmCheckInst is done as a tail call. 19099 */ 19100 adrl lr, dvmAsmInstructionStart + (383 * 64) 19101 mov r0, rPC @ arg0 19102 mov r1, rSELF @ arg1 19103 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19104 19105/* ------------------------------ */ 19106 .balign 64 19107.L_ALT_OP_UNUSED_80FF: /* 0x180 */ 19108/* File: armv5te/alt_stub.S */ 19109/* 19110 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19111 * any interesting requests and then jump to the real instruction 19112 * handler. Note that the call to dvmCheckInst is done as a tail call. 19113 */ 19114 adrl lr, dvmAsmInstructionStart + (384 * 64) 19115 mov r0, rPC @ arg0 19116 mov r1, rSELF @ arg1 19117 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19118 19119/* ------------------------------ */ 19120 .balign 64 19121.L_ALT_OP_UNUSED_81FF: /* 0x181 */ 19122/* File: armv5te/alt_stub.S */ 19123/* 19124 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19125 * any interesting requests and then jump to the real instruction 19126 * handler. Note that the call to dvmCheckInst is done as a tail call. 19127 */ 19128 adrl lr, dvmAsmInstructionStart + (385 * 64) 19129 mov r0, rPC @ arg0 19130 mov r1, rSELF @ arg1 19131 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19132 19133/* ------------------------------ */ 19134 .balign 64 19135.L_ALT_OP_UNUSED_82FF: /* 0x182 */ 19136/* File: armv5te/alt_stub.S */ 19137/* 19138 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19139 * any interesting requests and then jump to the real instruction 19140 * handler. Note that the call to dvmCheckInst is done as a tail call. 19141 */ 19142 adrl lr, dvmAsmInstructionStart + (386 * 64) 19143 mov r0, rPC @ arg0 19144 mov r1, rSELF @ arg1 19145 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19146 19147/* ------------------------------ */ 19148 .balign 64 19149.L_ALT_OP_UNUSED_83FF: /* 0x183 */ 19150/* File: armv5te/alt_stub.S */ 19151/* 19152 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19153 * any interesting requests and then jump to the real instruction 19154 * handler. Note that the call to dvmCheckInst is done as a tail call. 19155 */ 19156 adrl lr, dvmAsmInstructionStart + (387 * 64) 19157 mov r0, rPC @ arg0 19158 mov r1, rSELF @ arg1 19159 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19160 19161/* ------------------------------ */ 19162 .balign 64 19163.L_ALT_OP_UNUSED_84FF: /* 0x184 */ 19164/* File: armv5te/alt_stub.S */ 19165/* 19166 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19167 * any interesting requests and then jump to the real instruction 19168 * handler. Note that the call to dvmCheckInst is done as a tail call. 19169 */ 19170 adrl lr, dvmAsmInstructionStart + (388 * 64) 19171 mov r0, rPC @ arg0 19172 mov r1, rSELF @ arg1 19173 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19174 19175/* ------------------------------ */ 19176 .balign 64 19177.L_ALT_OP_UNUSED_85FF: /* 0x185 */ 19178/* File: armv5te/alt_stub.S */ 19179/* 19180 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19181 * any interesting requests and then jump to the real instruction 19182 * handler. Note that the call to dvmCheckInst is done as a tail call. 19183 */ 19184 adrl lr, dvmAsmInstructionStart + (389 * 64) 19185 mov r0, rPC @ arg0 19186 mov r1, rSELF @ arg1 19187 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19188 19189/* ------------------------------ */ 19190 .balign 64 19191.L_ALT_OP_UNUSED_86FF: /* 0x186 */ 19192/* File: armv5te/alt_stub.S */ 19193/* 19194 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19195 * any interesting requests and then jump to the real instruction 19196 * handler. Note that the call to dvmCheckInst is done as a tail call. 19197 */ 19198 adrl lr, dvmAsmInstructionStart + (390 * 64) 19199 mov r0, rPC @ arg0 19200 mov r1, rSELF @ arg1 19201 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19202 19203/* ------------------------------ */ 19204 .balign 64 19205.L_ALT_OP_UNUSED_87FF: /* 0x187 */ 19206/* File: armv5te/alt_stub.S */ 19207/* 19208 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19209 * any interesting requests and then jump to the real instruction 19210 * handler. Note that the call to dvmCheckInst is done as a tail call. 19211 */ 19212 adrl lr, dvmAsmInstructionStart + (391 * 64) 19213 mov r0, rPC @ arg0 19214 mov r1, rSELF @ arg1 19215 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19216 19217/* ------------------------------ */ 19218 .balign 64 19219.L_ALT_OP_UNUSED_88FF: /* 0x188 */ 19220/* File: armv5te/alt_stub.S */ 19221/* 19222 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19223 * any interesting requests and then jump to the real instruction 19224 * handler. Note that the call to dvmCheckInst is done as a tail call. 19225 */ 19226 adrl lr, dvmAsmInstructionStart + (392 * 64) 19227 mov r0, rPC @ arg0 19228 mov r1, rSELF @ arg1 19229 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19230 19231/* ------------------------------ */ 19232 .balign 64 19233.L_ALT_OP_UNUSED_89FF: /* 0x189 */ 19234/* File: armv5te/alt_stub.S */ 19235/* 19236 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19237 * any interesting requests and then jump to the real instruction 19238 * handler. Note that the call to dvmCheckInst is done as a tail call. 19239 */ 19240 adrl lr, dvmAsmInstructionStart + (393 * 64) 19241 mov r0, rPC @ arg0 19242 mov r1, rSELF @ arg1 19243 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19244 19245/* ------------------------------ */ 19246 .balign 64 19247.L_ALT_OP_UNUSED_8AFF: /* 0x18a */ 19248/* File: armv5te/alt_stub.S */ 19249/* 19250 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19251 * any interesting requests and then jump to the real instruction 19252 * handler. Note that the call to dvmCheckInst is done as a tail call. 19253 */ 19254 adrl lr, dvmAsmInstructionStart + (394 * 64) 19255 mov r0, rPC @ arg0 19256 mov r1, rSELF @ arg1 19257 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19258 19259/* ------------------------------ */ 19260 .balign 64 19261.L_ALT_OP_UNUSED_8BFF: /* 0x18b */ 19262/* File: armv5te/alt_stub.S */ 19263/* 19264 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19265 * any interesting requests and then jump to the real instruction 19266 * handler. Note that the call to dvmCheckInst is done as a tail call. 19267 */ 19268 adrl lr, dvmAsmInstructionStart + (395 * 64) 19269 mov r0, rPC @ arg0 19270 mov r1, rSELF @ arg1 19271 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19272 19273/* ------------------------------ */ 19274 .balign 64 19275.L_ALT_OP_UNUSED_8CFF: /* 0x18c */ 19276/* File: armv5te/alt_stub.S */ 19277/* 19278 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19279 * any interesting requests and then jump to the real instruction 19280 * handler. Note that the call to dvmCheckInst is done as a tail call. 19281 */ 19282 adrl lr, dvmAsmInstructionStart + (396 * 64) 19283 mov r0, rPC @ arg0 19284 mov r1, rSELF @ arg1 19285 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19286 19287/* ------------------------------ */ 19288 .balign 64 19289.L_ALT_OP_UNUSED_8DFF: /* 0x18d */ 19290/* File: armv5te/alt_stub.S */ 19291/* 19292 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19293 * any interesting requests and then jump to the real instruction 19294 * handler. Note that the call to dvmCheckInst is done as a tail call. 19295 */ 19296 adrl lr, dvmAsmInstructionStart + (397 * 64) 19297 mov r0, rPC @ arg0 19298 mov r1, rSELF @ arg1 19299 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19300 19301/* ------------------------------ */ 19302 .balign 64 19303.L_ALT_OP_UNUSED_8EFF: /* 0x18e */ 19304/* File: armv5te/alt_stub.S */ 19305/* 19306 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19307 * any interesting requests and then jump to the real instruction 19308 * handler. Note that the call to dvmCheckInst is done as a tail call. 19309 */ 19310 adrl lr, dvmAsmInstructionStart + (398 * 64) 19311 mov r0, rPC @ arg0 19312 mov r1, rSELF @ arg1 19313 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19314 19315/* ------------------------------ */ 19316 .balign 64 19317.L_ALT_OP_UNUSED_8FFF: /* 0x18f */ 19318/* File: armv5te/alt_stub.S */ 19319/* 19320 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19321 * any interesting requests and then jump to the real instruction 19322 * handler. Note that the call to dvmCheckInst is done as a tail call. 19323 */ 19324 adrl lr, dvmAsmInstructionStart + (399 * 64) 19325 mov r0, rPC @ arg0 19326 mov r1, rSELF @ arg1 19327 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19328 19329/* ------------------------------ */ 19330 .balign 64 19331.L_ALT_OP_UNUSED_90FF: /* 0x190 */ 19332/* File: armv5te/alt_stub.S */ 19333/* 19334 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19335 * any interesting requests and then jump to the real instruction 19336 * handler. Note that the call to dvmCheckInst is done as a tail call. 19337 */ 19338 adrl lr, dvmAsmInstructionStart + (400 * 64) 19339 mov r0, rPC @ arg0 19340 mov r1, rSELF @ arg1 19341 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19342 19343/* ------------------------------ */ 19344 .balign 64 19345.L_ALT_OP_UNUSED_91FF: /* 0x191 */ 19346/* File: armv5te/alt_stub.S */ 19347/* 19348 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19349 * any interesting requests and then jump to the real instruction 19350 * handler. Note that the call to dvmCheckInst is done as a tail call. 19351 */ 19352 adrl lr, dvmAsmInstructionStart + (401 * 64) 19353 mov r0, rPC @ arg0 19354 mov r1, rSELF @ arg1 19355 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19356 19357/* ------------------------------ */ 19358 .balign 64 19359.L_ALT_OP_UNUSED_92FF: /* 0x192 */ 19360/* File: armv5te/alt_stub.S */ 19361/* 19362 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19363 * any interesting requests and then jump to the real instruction 19364 * handler. Note that the call to dvmCheckInst is done as a tail call. 19365 */ 19366 adrl lr, dvmAsmInstructionStart + (402 * 64) 19367 mov r0, rPC @ arg0 19368 mov r1, rSELF @ arg1 19369 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19370 19371/* ------------------------------ */ 19372 .balign 64 19373.L_ALT_OP_UNUSED_93FF: /* 0x193 */ 19374/* File: armv5te/alt_stub.S */ 19375/* 19376 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19377 * any interesting requests and then jump to the real instruction 19378 * handler. Note that the call to dvmCheckInst is done as a tail call. 19379 */ 19380 adrl lr, dvmAsmInstructionStart + (403 * 64) 19381 mov r0, rPC @ arg0 19382 mov r1, rSELF @ arg1 19383 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19384 19385/* ------------------------------ */ 19386 .balign 64 19387.L_ALT_OP_UNUSED_94FF: /* 0x194 */ 19388/* File: armv5te/alt_stub.S */ 19389/* 19390 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19391 * any interesting requests and then jump to the real instruction 19392 * handler. Note that the call to dvmCheckInst is done as a tail call. 19393 */ 19394 adrl lr, dvmAsmInstructionStart + (404 * 64) 19395 mov r0, rPC @ arg0 19396 mov r1, rSELF @ arg1 19397 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19398 19399/* ------------------------------ */ 19400 .balign 64 19401.L_ALT_OP_UNUSED_95FF: /* 0x195 */ 19402/* File: armv5te/alt_stub.S */ 19403/* 19404 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19405 * any interesting requests and then jump to the real instruction 19406 * handler. Note that the call to dvmCheckInst is done as a tail call. 19407 */ 19408 adrl lr, dvmAsmInstructionStart + (405 * 64) 19409 mov r0, rPC @ arg0 19410 mov r1, rSELF @ arg1 19411 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19412 19413/* ------------------------------ */ 19414 .balign 64 19415.L_ALT_OP_UNUSED_96FF: /* 0x196 */ 19416/* File: armv5te/alt_stub.S */ 19417/* 19418 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19419 * any interesting requests and then jump to the real instruction 19420 * handler. Note that the call to dvmCheckInst is done as a tail call. 19421 */ 19422 adrl lr, dvmAsmInstructionStart + (406 * 64) 19423 mov r0, rPC @ arg0 19424 mov r1, rSELF @ arg1 19425 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19426 19427/* ------------------------------ */ 19428 .balign 64 19429.L_ALT_OP_UNUSED_97FF: /* 0x197 */ 19430/* File: armv5te/alt_stub.S */ 19431/* 19432 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19433 * any interesting requests and then jump to the real instruction 19434 * handler. Note that the call to dvmCheckInst is done as a tail call. 19435 */ 19436 adrl lr, dvmAsmInstructionStart + (407 * 64) 19437 mov r0, rPC @ arg0 19438 mov r1, rSELF @ arg1 19439 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19440 19441/* ------------------------------ */ 19442 .balign 64 19443.L_ALT_OP_UNUSED_98FF: /* 0x198 */ 19444/* File: armv5te/alt_stub.S */ 19445/* 19446 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19447 * any interesting requests and then jump to the real instruction 19448 * handler. Note that the call to dvmCheckInst is done as a tail call. 19449 */ 19450 adrl lr, dvmAsmInstructionStart + (408 * 64) 19451 mov r0, rPC @ arg0 19452 mov r1, rSELF @ arg1 19453 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19454 19455/* ------------------------------ */ 19456 .balign 64 19457.L_ALT_OP_UNUSED_99FF: /* 0x199 */ 19458/* File: armv5te/alt_stub.S */ 19459/* 19460 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19461 * any interesting requests and then jump to the real instruction 19462 * handler. Note that the call to dvmCheckInst is done as a tail call. 19463 */ 19464 adrl lr, dvmAsmInstructionStart + (409 * 64) 19465 mov r0, rPC @ arg0 19466 mov r1, rSELF @ arg1 19467 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19468 19469/* ------------------------------ */ 19470 .balign 64 19471.L_ALT_OP_UNUSED_9AFF: /* 0x19a */ 19472/* File: armv5te/alt_stub.S */ 19473/* 19474 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19475 * any interesting requests and then jump to the real instruction 19476 * handler. Note that the call to dvmCheckInst is done as a tail call. 19477 */ 19478 adrl lr, dvmAsmInstructionStart + (410 * 64) 19479 mov r0, rPC @ arg0 19480 mov r1, rSELF @ arg1 19481 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19482 19483/* ------------------------------ */ 19484 .balign 64 19485.L_ALT_OP_UNUSED_9BFF: /* 0x19b */ 19486/* File: armv5te/alt_stub.S */ 19487/* 19488 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19489 * any interesting requests and then jump to the real instruction 19490 * handler. Note that the call to dvmCheckInst is done as a tail call. 19491 */ 19492 adrl lr, dvmAsmInstructionStart + (411 * 64) 19493 mov r0, rPC @ arg0 19494 mov r1, rSELF @ arg1 19495 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19496 19497/* ------------------------------ */ 19498 .balign 64 19499.L_ALT_OP_UNUSED_9CFF: /* 0x19c */ 19500/* File: armv5te/alt_stub.S */ 19501/* 19502 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19503 * any interesting requests and then jump to the real instruction 19504 * handler. Note that the call to dvmCheckInst is done as a tail call. 19505 */ 19506 adrl lr, dvmAsmInstructionStart + (412 * 64) 19507 mov r0, rPC @ arg0 19508 mov r1, rSELF @ arg1 19509 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19510 19511/* ------------------------------ */ 19512 .balign 64 19513.L_ALT_OP_UNUSED_9DFF: /* 0x19d */ 19514/* File: armv5te/alt_stub.S */ 19515/* 19516 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19517 * any interesting requests and then jump to the real instruction 19518 * handler. Note that the call to dvmCheckInst is done as a tail call. 19519 */ 19520 adrl lr, dvmAsmInstructionStart + (413 * 64) 19521 mov r0, rPC @ arg0 19522 mov r1, rSELF @ arg1 19523 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19524 19525/* ------------------------------ */ 19526 .balign 64 19527.L_ALT_OP_UNUSED_9EFF: /* 0x19e */ 19528/* File: armv5te/alt_stub.S */ 19529/* 19530 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19531 * any interesting requests and then jump to the real instruction 19532 * handler. Note that the call to dvmCheckInst is done as a tail call. 19533 */ 19534 adrl lr, dvmAsmInstructionStart + (414 * 64) 19535 mov r0, rPC @ arg0 19536 mov r1, rSELF @ arg1 19537 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19538 19539/* ------------------------------ */ 19540 .balign 64 19541.L_ALT_OP_UNUSED_9FFF: /* 0x19f */ 19542/* File: armv5te/alt_stub.S */ 19543/* 19544 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19545 * any interesting requests and then jump to the real instruction 19546 * handler. Note that the call to dvmCheckInst is done as a tail call. 19547 */ 19548 adrl lr, dvmAsmInstructionStart + (415 * 64) 19549 mov r0, rPC @ arg0 19550 mov r1, rSELF @ arg1 19551 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19552 19553/* ------------------------------ */ 19554 .balign 64 19555.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */ 19556/* File: armv5te/alt_stub.S */ 19557/* 19558 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19559 * any interesting requests and then jump to the real instruction 19560 * handler. Note that the call to dvmCheckInst is done as a tail call. 19561 */ 19562 adrl lr, dvmAsmInstructionStart + (416 * 64) 19563 mov r0, rPC @ arg0 19564 mov r1, rSELF @ arg1 19565 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19566 19567/* ------------------------------ */ 19568 .balign 64 19569.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */ 19570/* File: armv5te/alt_stub.S */ 19571/* 19572 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19573 * any interesting requests and then jump to the real instruction 19574 * handler. Note that the call to dvmCheckInst is done as a tail call. 19575 */ 19576 adrl lr, dvmAsmInstructionStart + (417 * 64) 19577 mov r0, rPC @ arg0 19578 mov r1, rSELF @ arg1 19579 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19580 19581/* ------------------------------ */ 19582 .balign 64 19583.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */ 19584/* File: armv5te/alt_stub.S */ 19585/* 19586 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19587 * any interesting requests and then jump to the real instruction 19588 * handler. Note that the call to dvmCheckInst is done as a tail call. 19589 */ 19590 adrl lr, dvmAsmInstructionStart + (418 * 64) 19591 mov r0, rPC @ arg0 19592 mov r1, rSELF @ arg1 19593 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19594 19595/* ------------------------------ */ 19596 .balign 64 19597.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */ 19598/* File: armv5te/alt_stub.S */ 19599/* 19600 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19601 * any interesting requests and then jump to the real instruction 19602 * handler. Note that the call to dvmCheckInst is done as a tail call. 19603 */ 19604 adrl lr, dvmAsmInstructionStart + (419 * 64) 19605 mov r0, rPC @ arg0 19606 mov r1, rSELF @ arg1 19607 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19608 19609/* ------------------------------ */ 19610 .balign 64 19611.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */ 19612/* File: armv5te/alt_stub.S */ 19613/* 19614 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19615 * any interesting requests and then jump to the real instruction 19616 * handler. Note that the call to dvmCheckInst is done as a tail call. 19617 */ 19618 adrl lr, dvmAsmInstructionStart + (420 * 64) 19619 mov r0, rPC @ arg0 19620 mov r1, rSELF @ arg1 19621 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19622 19623/* ------------------------------ */ 19624 .balign 64 19625.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */ 19626/* File: armv5te/alt_stub.S */ 19627/* 19628 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19629 * any interesting requests and then jump to the real instruction 19630 * handler. Note that the call to dvmCheckInst is done as a tail call. 19631 */ 19632 adrl lr, dvmAsmInstructionStart + (421 * 64) 19633 mov r0, rPC @ arg0 19634 mov r1, rSELF @ arg1 19635 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19636 19637/* ------------------------------ */ 19638 .balign 64 19639.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */ 19640/* File: armv5te/alt_stub.S */ 19641/* 19642 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19643 * any interesting requests and then jump to the real instruction 19644 * handler. Note that the call to dvmCheckInst is done as a tail call. 19645 */ 19646 adrl lr, dvmAsmInstructionStart + (422 * 64) 19647 mov r0, rPC @ arg0 19648 mov r1, rSELF @ arg1 19649 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19650 19651/* ------------------------------ */ 19652 .balign 64 19653.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */ 19654/* File: armv5te/alt_stub.S */ 19655/* 19656 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19657 * any interesting requests and then jump to the real instruction 19658 * handler. Note that the call to dvmCheckInst is done as a tail call. 19659 */ 19660 adrl lr, dvmAsmInstructionStart + (423 * 64) 19661 mov r0, rPC @ arg0 19662 mov r1, rSELF @ arg1 19663 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19664 19665/* ------------------------------ */ 19666 .balign 64 19667.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */ 19668/* File: armv5te/alt_stub.S */ 19669/* 19670 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19671 * any interesting requests and then jump to the real instruction 19672 * handler. Note that the call to dvmCheckInst is done as a tail call. 19673 */ 19674 adrl lr, dvmAsmInstructionStart + (424 * 64) 19675 mov r0, rPC @ arg0 19676 mov r1, rSELF @ arg1 19677 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19678 19679/* ------------------------------ */ 19680 .balign 64 19681.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */ 19682/* File: armv5te/alt_stub.S */ 19683/* 19684 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19685 * any interesting requests and then jump to the real instruction 19686 * handler. Note that the call to dvmCheckInst is done as a tail call. 19687 */ 19688 adrl lr, dvmAsmInstructionStart + (425 * 64) 19689 mov r0, rPC @ arg0 19690 mov r1, rSELF @ arg1 19691 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19692 19693/* ------------------------------ */ 19694 .balign 64 19695.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */ 19696/* File: armv5te/alt_stub.S */ 19697/* 19698 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19699 * any interesting requests and then jump to the real instruction 19700 * handler. Note that the call to dvmCheckInst is done as a tail call. 19701 */ 19702 adrl lr, dvmAsmInstructionStart + (426 * 64) 19703 mov r0, rPC @ arg0 19704 mov r1, rSELF @ arg1 19705 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19706 19707/* ------------------------------ */ 19708 .balign 64 19709.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */ 19710/* File: armv5te/alt_stub.S */ 19711/* 19712 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19713 * any interesting requests and then jump to the real instruction 19714 * handler. Note that the call to dvmCheckInst is done as a tail call. 19715 */ 19716 adrl lr, dvmAsmInstructionStart + (427 * 64) 19717 mov r0, rPC @ arg0 19718 mov r1, rSELF @ arg1 19719 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19720 19721/* ------------------------------ */ 19722 .balign 64 19723.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */ 19724/* File: armv5te/alt_stub.S */ 19725/* 19726 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19727 * any interesting requests and then jump to the real instruction 19728 * handler. Note that the call to dvmCheckInst is done as a tail call. 19729 */ 19730 adrl lr, dvmAsmInstructionStart + (428 * 64) 19731 mov r0, rPC @ arg0 19732 mov r1, rSELF @ arg1 19733 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19734 19735/* ------------------------------ */ 19736 .balign 64 19737.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */ 19738/* File: armv5te/alt_stub.S */ 19739/* 19740 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19741 * any interesting requests and then jump to the real instruction 19742 * handler. Note that the call to dvmCheckInst is done as a tail call. 19743 */ 19744 adrl lr, dvmAsmInstructionStart + (429 * 64) 19745 mov r0, rPC @ arg0 19746 mov r1, rSELF @ arg1 19747 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19748 19749/* ------------------------------ */ 19750 .balign 64 19751.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */ 19752/* File: armv5te/alt_stub.S */ 19753/* 19754 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19755 * any interesting requests and then jump to the real instruction 19756 * handler. Note that the call to dvmCheckInst is done as a tail call. 19757 */ 19758 adrl lr, dvmAsmInstructionStart + (430 * 64) 19759 mov r0, rPC @ arg0 19760 mov r1, rSELF @ arg1 19761 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19762 19763/* ------------------------------ */ 19764 .balign 64 19765.L_ALT_OP_UNUSED_AFFF: /* 0x1af */ 19766/* File: armv5te/alt_stub.S */ 19767/* 19768 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19769 * any interesting requests and then jump to the real instruction 19770 * handler. Note that the call to dvmCheckInst is done as a tail call. 19771 */ 19772 adrl lr, dvmAsmInstructionStart + (431 * 64) 19773 mov r0, rPC @ arg0 19774 mov r1, rSELF @ arg1 19775 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19776 19777/* ------------------------------ */ 19778 .balign 64 19779.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */ 19780/* File: armv5te/alt_stub.S */ 19781/* 19782 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19783 * any interesting requests and then jump to the real instruction 19784 * handler. Note that the call to dvmCheckInst is done as a tail call. 19785 */ 19786 adrl lr, dvmAsmInstructionStart + (432 * 64) 19787 mov r0, rPC @ arg0 19788 mov r1, rSELF @ arg1 19789 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19790 19791/* ------------------------------ */ 19792 .balign 64 19793.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */ 19794/* File: armv5te/alt_stub.S */ 19795/* 19796 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19797 * any interesting requests and then jump to the real instruction 19798 * handler. Note that the call to dvmCheckInst is done as a tail call. 19799 */ 19800 adrl lr, dvmAsmInstructionStart + (433 * 64) 19801 mov r0, rPC @ arg0 19802 mov r1, rSELF @ arg1 19803 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19804 19805/* ------------------------------ */ 19806 .balign 64 19807.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */ 19808/* File: armv5te/alt_stub.S */ 19809/* 19810 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19811 * any interesting requests and then jump to the real instruction 19812 * handler. Note that the call to dvmCheckInst is done as a tail call. 19813 */ 19814 adrl lr, dvmAsmInstructionStart + (434 * 64) 19815 mov r0, rPC @ arg0 19816 mov r1, rSELF @ arg1 19817 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19818 19819/* ------------------------------ */ 19820 .balign 64 19821.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */ 19822/* File: armv5te/alt_stub.S */ 19823/* 19824 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19825 * any interesting requests and then jump to the real instruction 19826 * handler. Note that the call to dvmCheckInst is done as a tail call. 19827 */ 19828 adrl lr, dvmAsmInstructionStart + (435 * 64) 19829 mov r0, rPC @ arg0 19830 mov r1, rSELF @ arg1 19831 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19832 19833/* ------------------------------ */ 19834 .balign 64 19835.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */ 19836/* File: armv5te/alt_stub.S */ 19837/* 19838 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19839 * any interesting requests and then jump to the real instruction 19840 * handler. Note that the call to dvmCheckInst is done as a tail call. 19841 */ 19842 adrl lr, dvmAsmInstructionStart + (436 * 64) 19843 mov r0, rPC @ arg0 19844 mov r1, rSELF @ arg1 19845 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19846 19847/* ------------------------------ */ 19848 .balign 64 19849.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */ 19850/* File: armv5te/alt_stub.S */ 19851/* 19852 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19853 * any interesting requests and then jump to the real instruction 19854 * handler. Note that the call to dvmCheckInst is done as a tail call. 19855 */ 19856 adrl lr, dvmAsmInstructionStart + (437 * 64) 19857 mov r0, rPC @ arg0 19858 mov r1, rSELF @ arg1 19859 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19860 19861/* ------------------------------ */ 19862 .balign 64 19863.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */ 19864/* File: armv5te/alt_stub.S */ 19865/* 19866 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19867 * any interesting requests and then jump to the real instruction 19868 * handler. Note that the call to dvmCheckInst is done as a tail call. 19869 */ 19870 adrl lr, dvmAsmInstructionStart + (438 * 64) 19871 mov r0, rPC @ arg0 19872 mov r1, rSELF @ arg1 19873 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19874 19875/* ------------------------------ */ 19876 .balign 64 19877.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */ 19878/* File: armv5te/alt_stub.S */ 19879/* 19880 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19881 * any interesting requests and then jump to the real instruction 19882 * handler. Note that the call to dvmCheckInst is done as a tail call. 19883 */ 19884 adrl lr, dvmAsmInstructionStart + (439 * 64) 19885 mov r0, rPC @ arg0 19886 mov r1, rSELF @ arg1 19887 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19888 19889/* ------------------------------ */ 19890 .balign 64 19891.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */ 19892/* File: armv5te/alt_stub.S */ 19893/* 19894 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19895 * any interesting requests and then jump to the real instruction 19896 * handler. Note that the call to dvmCheckInst is done as a tail call. 19897 */ 19898 adrl lr, dvmAsmInstructionStart + (440 * 64) 19899 mov r0, rPC @ arg0 19900 mov r1, rSELF @ arg1 19901 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19902 19903/* ------------------------------ */ 19904 .balign 64 19905.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */ 19906/* File: armv5te/alt_stub.S */ 19907/* 19908 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19909 * any interesting requests and then jump to the real instruction 19910 * handler. Note that the call to dvmCheckInst is done as a tail call. 19911 */ 19912 adrl lr, dvmAsmInstructionStart + (441 * 64) 19913 mov r0, rPC @ arg0 19914 mov r1, rSELF @ arg1 19915 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19916 19917/* ------------------------------ */ 19918 .balign 64 19919.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */ 19920/* File: armv5te/alt_stub.S */ 19921/* 19922 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19923 * any interesting requests and then jump to the real instruction 19924 * handler. Note that the call to dvmCheckInst is done as a tail call. 19925 */ 19926 adrl lr, dvmAsmInstructionStart + (442 * 64) 19927 mov r0, rPC @ arg0 19928 mov r1, rSELF @ arg1 19929 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19930 19931/* ------------------------------ */ 19932 .balign 64 19933.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */ 19934/* File: armv5te/alt_stub.S */ 19935/* 19936 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19937 * any interesting requests and then jump to the real instruction 19938 * handler. Note that the call to dvmCheckInst is done as a tail call. 19939 */ 19940 adrl lr, dvmAsmInstructionStart + (443 * 64) 19941 mov r0, rPC @ arg0 19942 mov r1, rSELF @ arg1 19943 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19944 19945/* ------------------------------ */ 19946 .balign 64 19947.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */ 19948/* File: armv5te/alt_stub.S */ 19949/* 19950 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19951 * any interesting requests and then jump to the real instruction 19952 * handler. Note that the call to dvmCheckInst is done as a tail call. 19953 */ 19954 adrl lr, dvmAsmInstructionStart + (444 * 64) 19955 mov r0, rPC @ arg0 19956 mov r1, rSELF @ arg1 19957 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19958 19959/* ------------------------------ */ 19960 .balign 64 19961.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */ 19962/* File: armv5te/alt_stub.S */ 19963/* 19964 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19965 * any interesting requests and then jump to the real instruction 19966 * handler. Note that the call to dvmCheckInst is done as a tail call. 19967 */ 19968 adrl lr, dvmAsmInstructionStart + (445 * 64) 19969 mov r0, rPC @ arg0 19970 mov r1, rSELF @ arg1 19971 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19972 19973/* ------------------------------ */ 19974 .balign 64 19975.L_ALT_OP_UNUSED_BEFF: /* 0x1be */ 19976/* File: armv5te/alt_stub.S */ 19977/* 19978 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19979 * any interesting requests and then jump to the real instruction 19980 * handler. Note that the call to dvmCheckInst is done as a tail call. 19981 */ 19982 adrl lr, dvmAsmInstructionStart + (446 * 64) 19983 mov r0, rPC @ arg0 19984 mov r1, rSELF @ arg1 19985 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19986 19987/* ------------------------------ */ 19988 .balign 64 19989.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */ 19990/* File: armv5te/alt_stub.S */ 19991/* 19992 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19993 * any interesting requests and then jump to the real instruction 19994 * handler. Note that the call to dvmCheckInst is done as a tail call. 19995 */ 19996 adrl lr, dvmAsmInstructionStart + (447 * 64) 19997 mov r0, rPC @ arg0 19998 mov r1, rSELF @ arg1 19999 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20000 20001/* ------------------------------ */ 20002 .balign 64 20003.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */ 20004/* File: armv5te/alt_stub.S */ 20005/* 20006 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20007 * any interesting requests and then jump to the real instruction 20008 * handler. Note that the call to dvmCheckInst is done as a tail call. 20009 */ 20010 adrl lr, dvmAsmInstructionStart + (448 * 64) 20011 mov r0, rPC @ arg0 20012 mov r1, rSELF @ arg1 20013 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20014 20015/* ------------------------------ */ 20016 .balign 64 20017.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */ 20018/* File: armv5te/alt_stub.S */ 20019/* 20020 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20021 * any interesting requests and then jump to the real instruction 20022 * handler. Note that the call to dvmCheckInst is done as a tail call. 20023 */ 20024 adrl lr, dvmAsmInstructionStart + (449 * 64) 20025 mov r0, rPC @ arg0 20026 mov r1, rSELF @ arg1 20027 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20028 20029/* ------------------------------ */ 20030 .balign 64 20031.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */ 20032/* File: armv5te/alt_stub.S */ 20033/* 20034 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20035 * any interesting requests and then jump to the real instruction 20036 * handler. Note that the call to dvmCheckInst is done as a tail call. 20037 */ 20038 adrl lr, dvmAsmInstructionStart + (450 * 64) 20039 mov r0, rPC @ arg0 20040 mov r1, rSELF @ arg1 20041 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20042 20043/* ------------------------------ */ 20044 .balign 64 20045.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */ 20046/* File: armv5te/alt_stub.S */ 20047/* 20048 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20049 * any interesting requests and then jump to the real instruction 20050 * handler. Note that the call to dvmCheckInst is done as a tail call. 20051 */ 20052 adrl lr, dvmAsmInstructionStart + (451 * 64) 20053 mov r0, rPC @ arg0 20054 mov r1, rSELF @ arg1 20055 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20056 20057/* ------------------------------ */ 20058 .balign 64 20059.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */ 20060/* File: armv5te/alt_stub.S */ 20061/* 20062 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20063 * any interesting requests and then jump to the real instruction 20064 * handler. Note that the call to dvmCheckInst is done as a tail call. 20065 */ 20066 adrl lr, dvmAsmInstructionStart + (452 * 64) 20067 mov r0, rPC @ arg0 20068 mov r1, rSELF @ arg1 20069 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20070 20071/* ------------------------------ */ 20072 .balign 64 20073.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */ 20074/* File: armv5te/alt_stub.S */ 20075/* 20076 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20077 * any interesting requests and then jump to the real instruction 20078 * handler. Note that the call to dvmCheckInst is done as a tail call. 20079 */ 20080 adrl lr, dvmAsmInstructionStart + (453 * 64) 20081 mov r0, rPC @ arg0 20082 mov r1, rSELF @ arg1 20083 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20084 20085/* ------------------------------ */ 20086 .balign 64 20087.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */ 20088/* File: armv5te/alt_stub.S */ 20089/* 20090 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20091 * any interesting requests and then jump to the real instruction 20092 * handler. Note that the call to dvmCheckInst is done as a tail call. 20093 */ 20094 adrl lr, dvmAsmInstructionStart + (454 * 64) 20095 mov r0, rPC @ arg0 20096 mov r1, rSELF @ arg1 20097 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20098 20099/* ------------------------------ */ 20100 .balign 64 20101.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */ 20102/* File: armv5te/alt_stub.S */ 20103/* 20104 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20105 * any interesting requests and then jump to the real instruction 20106 * handler. Note that the call to dvmCheckInst is done as a tail call. 20107 */ 20108 adrl lr, dvmAsmInstructionStart + (455 * 64) 20109 mov r0, rPC @ arg0 20110 mov r1, rSELF @ arg1 20111 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20112 20113/* ------------------------------ */ 20114 .balign 64 20115.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */ 20116/* File: armv5te/alt_stub.S */ 20117/* 20118 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20119 * any interesting requests and then jump to the real instruction 20120 * handler. Note that the call to dvmCheckInst is done as a tail call. 20121 */ 20122 adrl lr, dvmAsmInstructionStart + (456 * 64) 20123 mov r0, rPC @ arg0 20124 mov r1, rSELF @ arg1 20125 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20126 20127/* ------------------------------ */ 20128 .balign 64 20129.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */ 20130/* File: armv5te/alt_stub.S */ 20131/* 20132 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20133 * any interesting requests and then jump to the real instruction 20134 * handler. Note that the call to dvmCheckInst is done as a tail call. 20135 */ 20136 adrl lr, dvmAsmInstructionStart + (457 * 64) 20137 mov r0, rPC @ arg0 20138 mov r1, rSELF @ arg1 20139 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20140 20141/* ------------------------------ */ 20142 .balign 64 20143.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */ 20144/* File: armv5te/alt_stub.S */ 20145/* 20146 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20147 * any interesting requests and then jump to the real instruction 20148 * handler. Note that the call to dvmCheckInst is done as a tail call. 20149 */ 20150 adrl lr, dvmAsmInstructionStart + (458 * 64) 20151 mov r0, rPC @ arg0 20152 mov r1, rSELF @ arg1 20153 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20154 20155/* ------------------------------ */ 20156 .balign 64 20157.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */ 20158/* File: armv5te/alt_stub.S */ 20159/* 20160 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20161 * any interesting requests and then jump to the real instruction 20162 * handler. Note that the call to dvmCheckInst is done as a tail call. 20163 */ 20164 adrl lr, dvmAsmInstructionStart + (459 * 64) 20165 mov r0, rPC @ arg0 20166 mov r1, rSELF @ arg1 20167 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20168 20169/* ------------------------------ */ 20170 .balign 64 20171.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */ 20172/* File: armv5te/alt_stub.S */ 20173/* 20174 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20175 * any interesting requests and then jump to the real instruction 20176 * handler. Note that the call to dvmCheckInst is done as a tail call. 20177 */ 20178 adrl lr, dvmAsmInstructionStart + (460 * 64) 20179 mov r0, rPC @ arg0 20180 mov r1, rSELF @ arg1 20181 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20182 20183/* ------------------------------ */ 20184 .balign 64 20185.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */ 20186/* File: armv5te/alt_stub.S */ 20187/* 20188 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20189 * any interesting requests and then jump to the real instruction 20190 * handler. Note that the call to dvmCheckInst is done as a tail call. 20191 */ 20192 adrl lr, dvmAsmInstructionStart + (461 * 64) 20193 mov r0, rPC @ arg0 20194 mov r1, rSELF @ arg1 20195 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20196 20197/* ------------------------------ */ 20198 .balign 64 20199.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */ 20200/* File: armv5te/alt_stub.S */ 20201/* 20202 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20203 * any interesting requests and then jump to the real instruction 20204 * handler. Note that the call to dvmCheckInst is done as a tail call. 20205 */ 20206 adrl lr, dvmAsmInstructionStart + (462 * 64) 20207 mov r0, rPC @ arg0 20208 mov r1, rSELF @ arg1 20209 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20210 20211/* ------------------------------ */ 20212 .balign 64 20213.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */ 20214/* File: armv5te/alt_stub.S */ 20215/* 20216 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20217 * any interesting requests and then jump to the real instruction 20218 * handler. Note that the call to dvmCheckInst is done as a tail call. 20219 */ 20220 adrl lr, dvmAsmInstructionStart + (463 * 64) 20221 mov r0, rPC @ arg0 20222 mov r1, rSELF @ arg1 20223 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20224 20225/* ------------------------------ */ 20226 .balign 64 20227.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */ 20228/* File: armv5te/alt_stub.S */ 20229/* 20230 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20231 * any interesting requests and then jump to the real instruction 20232 * handler. Note that the call to dvmCheckInst is done as a tail call. 20233 */ 20234 adrl lr, dvmAsmInstructionStart + (464 * 64) 20235 mov r0, rPC @ arg0 20236 mov r1, rSELF @ arg1 20237 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20238 20239/* ------------------------------ */ 20240 .balign 64 20241.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */ 20242/* File: armv5te/alt_stub.S */ 20243/* 20244 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20245 * any interesting requests and then jump to the real instruction 20246 * handler. Note that the call to dvmCheckInst is done as a tail call. 20247 */ 20248 adrl lr, dvmAsmInstructionStart + (465 * 64) 20249 mov r0, rPC @ arg0 20250 mov r1, rSELF @ arg1 20251 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20252 20253/* ------------------------------ */ 20254 .balign 64 20255.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */ 20256/* File: armv5te/alt_stub.S */ 20257/* 20258 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20259 * any interesting requests and then jump to the real instruction 20260 * handler. Note that the call to dvmCheckInst is done as a tail call. 20261 */ 20262 adrl lr, dvmAsmInstructionStart + (466 * 64) 20263 mov r0, rPC @ arg0 20264 mov r1, rSELF @ arg1 20265 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20266 20267/* ------------------------------ */ 20268 .balign 64 20269.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */ 20270/* File: armv5te/alt_stub.S */ 20271/* 20272 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20273 * any interesting requests and then jump to the real instruction 20274 * handler. Note that the call to dvmCheckInst is done as a tail call. 20275 */ 20276 adrl lr, dvmAsmInstructionStart + (467 * 64) 20277 mov r0, rPC @ arg0 20278 mov r1, rSELF @ arg1 20279 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20280 20281/* ------------------------------ */ 20282 .balign 64 20283.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */ 20284/* File: armv5te/alt_stub.S */ 20285/* 20286 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20287 * any interesting requests and then jump to the real instruction 20288 * handler. Note that the call to dvmCheckInst is done as a tail call. 20289 */ 20290 adrl lr, dvmAsmInstructionStart + (468 * 64) 20291 mov r0, rPC @ arg0 20292 mov r1, rSELF @ arg1 20293 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20294 20295/* ------------------------------ */ 20296 .balign 64 20297.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */ 20298/* File: armv5te/alt_stub.S */ 20299/* 20300 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20301 * any interesting requests and then jump to the real instruction 20302 * handler. Note that the call to dvmCheckInst is done as a tail call. 20303 */ 20304 adrl lr, dvmAsmInstructionStart + (469 * 64) 20305 mov r0, rPC @ arg0 20306 mov r1, rSELF @ arg1 20307 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20308 20309/* ------------------------------ */ 20310 .balign 64 20311.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */ 20312/* File: armv5te/alt_stub.S */ 20313/* 20314 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20315 * any interesting requests and then jump to the real instruction 20316 * handler. Note that the call to dvmCheckInst is done as a tail call. 20317 */ 20318 adrl lr, dvmAsmInstructionStart + (470 * 64) 20319 mov r0, rPC @ arg0 20320 mov r1, rSELF @ arg1 20321 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20322 20323/* ------------------------------ */ 20324 .balign 64 20325.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */ 20326/* File: armv5te/alt_stub.S */ 20327/* 20328 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20329 * any interesting requests and then jump to the real instruction 20330 * handler. Note that the call to dvmCheckInst is done as a tail call. 20331 */ 20332 adrl lr, dvmAsmInstructionStart + (471 * 64) 20333 mov r0, rPC @ arg0 20334 mov r1, rSELF @ arg1 20335 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20336 20337/* ------------------------------ */ 20338 .balign 64 20339.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */ 20340/* File: armv5te/alt_stub.S */ 20341/* 20342 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20343 * any interesting requests and then jump to the real instruction 20344 * handler. Note that the call to dvmCheckInst is done as a tail call. 20345 */ 20346 adrl lr, dvmAsmInstructionStart + (472 * 64) 20347 mov r0, rPC @ arg0 20348 mov r1, rSELF @ arg1 20349 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20350 20351/* ------------------------------ */ 20352 .balign 64 20353.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */ 20354/* File: armv5te/alt_stub.S */ 20355/* 20356 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20357 * any interesting requests and then jump to the real instruction 20358 * handler. Note that the call to dvmCheckInst is done as a tail call. 20359 */ 20360 adrl lr, dvmAsmInstructionStart + (473 * 64) 20361 mov r0, rPC @ arg0 20362 mov r1, rSELF @ arg1 20363 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20364 20365/* ------------------------------ */ 20366 .balign 64 20367.L_ALT_OP_UNUSED_DAFF: /* 0x1da */ 20368/* File: armv5te/alt_stub.S */ 20369/* 20370 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20371 * any interesting requests and then jump to the real instruction 20372 * handler. Note that the call to dvmCheckInst is done as a tail call. 20373 */ 20374 adrl lr, dvmAsmInstructionStart + (474 * 64) 20375 mov r0, rPC @ arg0 20376 mov r1, rSELF @ arg1 20377 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20378 20379/* ------------------------------ */ 20380 .balign 64 20381.L_ALT_OP_UNUSED_DBFF: /* 0x1db */ 20382/* File: armv5te/alt_stub.S */ 20383/* 20384 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20385 * any interesting requests and then jump to the real instruction 20386 * handler. Note that the call to dvmCheckInst is done as a tail call. 20387 */ 20388 adrl lr, dvmAsmInstructionStart + (475 * 64) 20389 mov r0, rPC @ arg0 20390 mov r1, rSELF @ arg1 20391 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20392 20393/* ------------------------------ */ 20394 .balign 64 20395.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */ 20396/* File: armv5te/alt_stub.S */ 20397/* 20398 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20399 * any interesting requests and then jump to the real instruction 20400 * handler. Note that the call to dvmCheckInst is done as a tail call. 20401 */ 20402 adrl lr, dvmAsmInstructionStart + (476 * 64) 20403 mov r0, rPC @ arg0 20404 mov r1, rSELF @ arg1 20405 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20406 20407/* ------------------------------ */ 20408 .balign 64 20409.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */ 20410/* File: armv5te/alt_stub.S */ 20411/* 20412 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20413 * any interesting requests and then jump to the real instruction 20414 * handler. Note that the call to dvmCheckInst is done as a tail call. 20415 */ 20416 adrl lr, dvmAsmInstructionStart + (477 * 64) 20417 mov r0, rPC @ arg0 20418 mov r1, rSELF @ arg1 20419 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20420 20421/* ------------------------------ */ 20422 .balign 64 20423.L_ALT_OP_UNUSED_DEFF: /* 0x1de */ 20424/* File: armv5te/alt_stub.S */ 20425/* 20426 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20427 * any interesting requests and then jump to the real instruction 20428 * handler. Note that the call to dvmCheckInst is done as a tail call. 20429 */ 20430 adrl lr, dvmAsmInstructionStart + (478 * 64) 20431 mov r0, rPC @ arg0 20432 mov r1, rSELF @ arg1 20433 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20434 20435/* ------------------------------ */ 20436 .balign 64 20437.L_ALT_OP_UNUSED_DFFF: /* 0x1df */ 20438/* File: armv5te/alt_stub.S */ 20439/* 20440 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20441 * any interesting requests and then jump to the real instruction 20442 * handler. Note that the call to dvmCheckInst is done as a tail call. 20443 */ 20444 adrl lr, dvmAsmInstructionStart + (479 * 64) 20445 mov r0, rPC @ arg0 20446 mov r1, rSELF @ arg1 20447 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20448 20449/* ------------------------------ */ 20450 .balign 64 20451.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */ 20452/* File: armv5te/alt_stub.S */ 20453/* 20454 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20455 * any interesting requests and then jump to the real instruction 20456 * handler. Note that the call to dvmCheckInst is done as a tail call. 20457 */ 20458 adrl lr, dvmAsmInstructionStart + (480 * 64) 20459 mov r0, rPC @ arg0 20460 mov r1, rSELF @ arg1 20461 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20462 20463/* ------------------------------ */ 20464 .balign 64 20465.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */ 20466/* File: armv5te/alt_stub.S */ 20467/* 20468 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20469 * any interesting requests and then jump to the real instruction 20470 * handler. Note that the call to dvmCheckInst is done as a tail call. 20471 */ 20472 adrl lr, dvmAsmInstructionStart + (481 * 64) 20473 mov r0, rPC @ arg0 20474 mov r1, rSELF @ arg1 20475 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20476 20477/* ------------------------------ */ 20478 .balign 64 20479.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */ 20480/* File: armv5te/alt_stub.S */ 20481/* 20482 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20483 * any interesting requests and then jump to the real instruction 20484 * handler. Note that the call to dvmCheckInst is done as a tail call. 20485 */ 20486 adrl lr, dvmAsmInstructionStart + (482 * 64) 20487 mov r0, rPC @ arg0 20488 mov r1, rSELF @ arg1 20489 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20490 20491/* ------------------------------ */ 20492 .balign 64 20493.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */ 20494/* File: armv5te/alt_stub.S */ 20495/* 20496 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20497 * any interesting requests and then jump to the real instruction 20498 * handler. Note that the call to dvmCheckInst is done as a tail call. 20499 */ 20500 adrl lr, dvmAsmInstructionStart + (483 * 64) 20501 mov r0, rPC @ arg0 20502 mov r1, rSELF @ arg1 20503 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20504 20505/* ------------------------------ */ 20506 .balign 64 20507.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */ 20508/* File: armv5te/alt_stub.S */ 20509/* 20510 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20511 * any interesting requests and then jump to the real instruction 20512 * handler. Note that the call to dvmCheckInst is done as a tail call. 20513 */ 20514 adrl lr, dvmAsmInstructionStart + (484 * 64) 20515 mov r0, rPC @ arg0 20516 mov r1, rSELF @ arg1 20517 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20518 20519/* ------------------------------ */ 20520 .balign 64 20521.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */ 20522/* File: armv5te/alt_stub.S */ 20523/* 20524 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20525 * any interesting requests and then jump to the real instruction 20526 * handler. Note that the call to dvmCheckInst is done as a tail call. 20527 */ 20528 adrl lr, dvmAsmInstructionStart + (485 * 64) 20529 mov r0, rPC @ arg0 20530 mov r1, rSELF @ arg1 20531 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20532 20533/* ------------------------------ */ 20534 .balign 64 20535.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */ 20536/* File: armv5te/alt_stub.S */ 20537/* 20538 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20539 * any interesting requests and then jump to the real instruction 20540 * handler. Note that the call to dvmCheckInst is done as a tail call. 20541 */ 20542 adrl lr, dvmAsmInstructionStart + (486 * 64) 20543 mov r0, rPC @ arg0 20544 mov r1, rSELF @ arg1 20545 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20546 20547/* ------------------------------ */ 20548 .balign 64 20549.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */ 20550/* File: armv5te/alt_stub.S */ 20551/* 20552 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20553 * any interesting requests and then jump to the real instruction 20554 * handler. Note that the call to dvmCheckInst is done as a tail call. 20555 */ 20556 adrl lr, dvmAsmInstructionStart + (487 * 64) 20557 mov r0, rPC @ arg0 20558 mov r1, rSELF @ arg1 20559 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20560 20561/* ------------------------------ */ 20562 .balign 64 20563.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */ 20564/* File: armv5te/alt_stub.S */ 20565/* 20566 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20567 * any interesting requests and then jump to the real instruction 20568 * handler. Note that the call to dvmCheckInst is done as a tail call. 20569 */ 20570 adrl lr, dvmAsmInstructionStart + (488 * 64) 20571 mov r0, rPC @ arg0 20572 mov r1, rSELF @ arg1 20573 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20574 20575/* ------------------------------ */ 20576 .balign 64 20577.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */ 20578/* File: armv5te/alt_stub.S */ 20579/* 20580 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20581 * any interesting requests and then jump to the real instruction 20582 * handler. Note that the call to dvmCheckInst is done as a tail call. 20583 */ 20584 adrl lr, dvmAsmInstructionStart + (489 * 64) 20585 mov r0, rPC @ arg0 20586 mov r1, rSELF @ arg1 20587 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20588 20589/* ------------------------------ */ 20590 .balign 64 20591.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */ 20592/* File: armv5te/alt_stub.S */ 20593/* 20594 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20595 * any interesting requests and then jump to the real instruction 20596 * handler. Note that the call to dvmCheckInst is done as a tail call. 20597 */ 20598 adrl lr, dvmAsmInstructionStart + (490 * 64) 20599 mov r0, rPC @ arg0 20600 mov r1, rSELF @ arg1 20601 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20602 20603/* ------------------------------ */ 20604 .balign 64 20605.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */ 20606/* File: armv5te/alt_stub.S */ 20607/* 20608 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20609 * any interesting requests and then jump to the real instruction 20610 * handler. Note that the call to dvmCheckInst is done as a tail call. 20611 */ 20612 adrl lr, dvmAsmInstructionStart + (491 * 64) 20613 mov r0, rPC @ arg0 20614 mov r1, rSELF @ arg1 20615 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20616 20617/* ------------------------------ */ 20618 .balign 64 20619.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */ 20620/* File: armv5te/alt_stub.S */ 20621/* 20622 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20623 * any interesting requests and then jump to the real instruction 20624 * handler. Note that the call to dvmCheckInst is done as a tail call. 20625 */ 20626 adrl lr, dvmAsmInstructionStart + (492 * 64) 20627 mov r0, rPC @ arg0 20628 mov r1, rSELF @ arg1 20629 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20630 20631/* ------------------------------ */ 20632 .balign 64 20633.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */ 20634/* File: armv5te/alt_stub.S */ 20635/* 20636 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20637 * any interesting requests and then jump to the real instruction 20638 * handler. Note that the call to dvmCheckInst is done as a tail call. 20639 */ 20640 adrl lr, dvmAsmInstructionStart + (493 * 64) 20641 mov r0, rPC @ arg0 20642 mov r1, rSELF @ arg1 20643 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20644 20645/* ------------------------------ */ 20646 .balign 64 20647.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */ 20648/* File: armv5te/alt_stub.S */ 20649/* 20650 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20651 * any interesting requests and then jump to the real instruction 20652 * handler. Note that the call to dvmCheckInst is done as a tail call. 20653 */ 20654 adrl lr, dvmAsmInstructionStart + (494 * 64) 20655 mov r0, rPC @ arg0 20656 mov r1, rSELF @ arg1 20657 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20658 20659/* ------------------------------ */ 20660 .balign 64 20661.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */ 20662/* File: armv5te/alt_stub.S */ 20663/* 20664 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20665 * any interesting requests and then jump to the real instruction 20666 * handler. Note that the call to dvmCheckInst is done as a tail call. 20667 */ 20668 adrl lr, dvmAsmInstructionStart + (495 * 64) 20669 mov r0, rPC @ arg0 20670 mov r1, rSELF @ arg1 20671 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20672 20673/* ------------------------------ */ 20674 .balign 64 20675.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */ 20676/* File: armv5te/alt_stub.S */ 20677/* 20678 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20679 * any interesting requests and then jump to the real instruction 20680 * handler. Note that the call to dvmCheckInst is done as a tail call. 20681 */ 20682 adrl lr, dvmAsmInstructionStart + (496 * 64) 20683 mov r0, rPC @ arg0 20684 mov r1, rSELF @ arg1 20685 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20686 20687/* ------------------------------ */ 20688 .balign 64 20689.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */ 20690/* File: armv5te/alt_stub.S */ 20691/* 20692 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20693 * any interesting requests and then jump to the real instruction 20694 * handler. Note that the call to dvmCheckInst is done as a tail call. 20695 */ 20696 adrl lr, dvmAsmInstructionStart + (497 * 64) 20697 mov r0, rPC @ arg0 20698 mov r1, rSELF @ arg1 20699 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20700 20701/* ------------------------------ */ 20702 .balign 64 20703.L_ALT_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */ 20704/* File: armv5te/alt_stub.S */ 20705/* 20706 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20707 * any interesting requests and then jump to the real instruction 20708 * handler. Note that the call to dvmCheckInst is done as a tail call. 20709 */ 20710 adrl lr, dvmAsmInstructionStart + (498 * 64) 20711 mov r0, rPC @ arg0 20712 mov r1, rSELF @ arg1 20713 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20714 20715/* ------------------------------ */ 20716 .balign 64 20717.L_ALT_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */ 20718/* File: armv5te/alt_stub.S */ 20719/* 20720 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20721 * any interesting requests and then jump to the real instruction 20722 * handler. Note that the call to dvmCheckInst is done as a tail call. 20723 */ 20724 adrl lr, dvmAsmInstructionStart + (499 * 64) 20725 mov r0, rPC @ arg0 20726 mov r1, rSELF @ arg1 20727 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20728 20729/* ------------------------------ */ 20730 .balign 64 20731.L_ALT_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */ 20732/* File: armv5te/alt_stub.S */ 20733/* 20734 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20735 * any interesting requests and then jump to the real instruction 20736 * handler. Note that the call to dvmCheckInst is done as a tail call. 20737 */ 20738 adrl lr, dvmAsmInstructionStart + (500 * 64) 20739 mov r0, rPC @ arg0 20740 mov r1, rSELF @ arg1 20741 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20742 20743/* ------------------------------ */ 20744 .balign 64 20745.L_ALT_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */ 20746/* File: armv5te/alt_stub.S */ 20747/* 20748 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20749 * any interesting requests and then jump to the real instruction 20750 * handler. Note that the call to dvmCheckInst is done as a tail call. 20751 */ 20752 adrl lr, dvmAsmInstructionStart + (501 * 64) 20753 mov r0, rPC @ arg0 20754 mov r1, rSELF @ arg1 20755 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20756 20757/* ------------------------------ */ 20758 .balign 64 20759.L_ALT_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */ 20760/* File: armv5te/alt_stub.S */ 20761/* 20762 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20763 * any interesting requests and then jump to the real instruction 20764 * handler. Note that the call to dvmCheckInst is done as a tail call. 20765 */ 20766 adrl lr, dvmAsmInstructionStart + (502 * 64) 20767 mov r0, rPC @ arg0 20768 mov r1, rSELF @ arg1 20769 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20770 20771/* ------------------------------ */ 20772 .balign 64 20773.L_ALT_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */ 20774/* File: armv5te/alt_stub.S */ 20775/* 20776 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20777 * any interesting requests and then jump to the real instruction 20778 * handler. Note that the call to dvmCheckInst is done as a tail call. 20779 */ 20780 adrl lr, dvmAsmInstructionStart + (503 * 64) 20781 mov r0, rPC @ arg0 20782 mov r1, rSELF @ arg1 20783 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20784 20785/* ------------------------------ */ 20786 .balign 64 20787.L_ALT_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */ 20788/* File: armv5te/alt_stub.S */ 20789/* 20790 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20791 * any interesting requests and then jump to the real instruction 20792 * handler. Note that the call to dvmCheckInst is done as a tail call. 20793 */ 20794 adrl lr, dvmAsmInstructionStart + (504 * 64) 20795 mov r0, rPC @ arg0 20796 mov r1, rSELF @ arg1 20797 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20798 20799/* ------------------------------ */ 20800 .balign 64 20801.L_ALT_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */ 20802/* File: armv5te/alt_stub.S */ 20803/* 20804 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20805 * any interesting requests and then jump to the real instruction 20806 * handler. Note that the call to dvmCheckInst is done as a tail call. 20807 */ 20808 adrl lr, dvmAsmInstructionStart + (505 * 64) 20809 mov r0, rPC @ arg0 20810 mov r1, rSELF @ arg1 20811 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20812 20813/* ------------------------------ */ 20814 .balign 64 20815.L_ALT_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */ 20816/* File: armv5te/alt_stub.S */ 20817/* 20818 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20819 * any interesting requests and then jump to the real instruction 20820 * handler. Note that the call to dvmCheckInst is done as a tail call. 20821 */ 20822 adrl lr, dvmAsmInstructionStart + (506 * 64) 20823 mov r0, rPC @ arg0 20824 mov r1, rSELF @ arg1 20825 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20826 20827/* ------------------------------ */ 20828 .balign 64 20829.L_ALT_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */ 20830/* File: armv5te/alt_stub.S */ 20831/* 20832 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20833 * any interesting requests and then jump to the real instruction 20834 * handler. Note that the call to dvmCheckInst is done as a tail call. 20835 */ 20836 adrl lr, dvmAsmInstructionStart + (507 * 64) 20837 mov r0, rPC @ arg0 20838 mov r1, rSELF @ arg1 20839 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20840 20841/* ------------------------------ */ 20842 .balign 64 20843.L_ALT_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */ 20844/* File: armv5te/alt_stub.S */ 20845/* 20846 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20847 * any interesting requests and then jump to the real instruction 20848 * handler. Note that the call to dvmCheckInst is done as a tail call. 20849 */ 20850 adrl lr, dvmAsmInstructionStart + (508 * 64) 20851 mov r0, rPC @ arg0 20852 mov r1, rSELF @ arg1 20853 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20854 20855/* ------------------------------ */ 20856 .balign 64 20857.L_ALT_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */ 20858/* File: armv5te/alt_stub.S */ 20859/* 20860 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20861 * any interesting requests and then jump to the real instruction 20862 * handler. Note that the call to dvmCheckInst is done as a tail call. 20863 */ 20864 adrl lr, dvmAsmInstructionStart + (509 * 64) 20865 mov r0, rPC @ arg0 20866 mov r1, rSELF @ arg1 20867 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20868 20869/* ------------------------------ */ 20870 .balign 64 20871.L_ALT_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */ 20872/* File: armv5te/alt_stub.S */ 20873/* 20874 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20875 * any interesting requests and then jump to the real instruction 20876 * handler. Note that the call to dvmCheckInst is done as a tail call. 20877 */ 20878 adrl lr, dvmAsmInstructionStart + (510 * 64) 20879 mov r0, rPC @ arg0 20880 mov r1, rSELF @ arg1 20881 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20882 20883/* ------------------------------ */ 20884 .balign 64 20885.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 20886/* File: armv5te/alt_stub.S */ 20887/* 20888 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20889 * any interesting requests and then jump to the real instruction 20890 * handler. Note that the call to dvmCheckInst is done as a tail call. 20891 */ 20892 adrl lr, dvmAsmInstructionStart + (511 * 64) 20893 mov r0, rPC @ arg0 20894 mov r1, rSELF @ arg1 20895 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20896 20897 .balign 64 20898 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart 20899 .global dvmAsmAltInstructionEnd 20900dvmAsmAltInstructionEnd: 20901/* File: armv5te/footer.S */ 20902 20903/* 20904 * =========================================================================== 20905 * Common subroutines and data 20906 * =========================================================================== 20907 */ 20908 20909 20910 20911 .text 20912 .align 2 20913 20914#if defined(WITH_JIT) 20915#if defined(WITH_SELF_VERIFICATION) 20916 .global dvmJitToInterpPunt 20917dvmJitToInterpPunt: 20918 mov r2,#kSVSPunt @ r2<- interpreter entry point 20919 mov r3, #0 20920 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20921 b jitSVShadowRunEnd @ doesn't return 20922 20923 .global dvmJitToInterpSingleStep 20924dvmJitToInterpSingleStep: 20925 str lr,[rSELF,#offThread_jitResumeNPC] 20926 str r1,[rSELF,#offThread_jitResumeDPC] 20927 mov r2,#kSVSSingleStep @ r2<- interpreter entry point 20928 b jitSVShadowRunEnd @ doesn't return 20929 20930 .global dvmJitToInterpNoChainNoProfile 20931dvmJitToInterpNoChainNoProfile: 20932 mov r0,rPC @ pass our target PC 20933 mov r2,#kSVSNoProfile @ r2<- interpreter entry point 20934 mov r3, #0 @ 0 means !inJitCodeCache 20935 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 20936 b jitSVShadowRunEnd @ doesn't return 20937 20938 .global dvmJitToInterpTraceSelectNoChain 20939dvmJitToInterpTraceSelectNoChain: 20940 mov r0,rPC @ pass our target PC 20941 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20942 mov r3, #0 @ 0 means !inJitCodeCache 20943 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20944 b jitSVShadowRunEnd @ doesn't return 20945 20946 .global dvmJitToInterpTraceSelect 20947dvmJitToInterpTraceSelect: 20948 ldr r0,[lr, #-1] @ pass our target PC 20949 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20950 mov r3, #0 @ 0 means !inJitCodeCache 20951 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20952 b jitSVShadowRunEnd @ doesn't return 20953 20954 .global dvmJitToInterpBackwardBranch 20955dvmJitToInterpBackwardBranch: 20956 ldr r0,[lr, #-1] @ pass our target PC 20957 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 20958 mov r3, #0 @ 0 means !inJitCodeCache 20959 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20960 b jitSVShadowRunEnd @ doesn't return 20961 20962 .global dvmJitToInterpNormal 20963dvmJitToInterpNormal: 20964 ldr r0,[lr, #-1] @ pass our target PC 20965 mov r2,#kSVSNormal @ r2<- interpreter entry point 20966 mov r3, #0 @ 0 means !inJitCodeCache 20967 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20968 b jitSVShadowRunEnd @ doesn't return 20969 20970 .global dvmJitToInterpNoChain 20971dvmJitToInterpNoChain: 20972 mov r0,rPC @ pass our target PC 20973 mov r2,#kSVSNoChain @ r2<- interpreter entry point 20974 mov r3, #0 @ 0 means !inJitCodeCache 20975 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20976 b jitSVShadowRunEnd @ doesn't return 20977#else 20978/* 20979 * Return from the translation cache to the interpreter when the compiler is 20980 * having issues translating/executing a Dalvik instruction. We have to skip 20981 * the code cache lookup otherwise it is possible to indefinitely bouce 20982 * between the interpreter and the code cache if the instruction that fails 20983 * to be compiled happens to be at a trace start. 20984 */ 20985 .global dvmJitToInterpPunt 20986dvmJitToInterpPunt: 20987 mov rPC, r0 20988#if defined(WITH_JIT_TUNING) 20989 mov r0,lr 20990 bl dvmBumpPunt; 20991#endif 20992 EXPORT_PC() 20993 mov r0, #0 20994 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20995 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20996 FETCH_INST() 20997 GET_INST_OPCODE(ip) 20998 GOTO_OPCODE(ip) 20999 21000/* 21001 * Return to the interpreter to handle a single instruction. 21002 * On entry: 21003 * r0 <= PC 21004 * r1 <= PC of resume instruction 21005 * lr <= resume point in translation 21006 */ 21007 .global dvmJitToInterpSingleStep 21008dvmJitToInterpSingleStep: 21009 str lr,[rSELF,#offThread_jitResumeNPC] 21010 str r1,[rSELF,#offThread_jitResumeDPC] 21011 mov r1,#kInterpEntryInstr 21012 @ enum is 4 byte in aapcs-EABI 21013 str r1, [rSELF, #offThread_entryPoint] 21014 mov rPC,r0 21015 EXPORT_PC() 21016 21017 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21018 mov r2,#kJitSingleStep @ Ask for single step and then revert 21019 str r2,[rSELF,#offThread_jitState] 21020 mov r1,#1 @ set changeInterp to bail to debug interp 21021 b common_gotoBail 21022 21023/* 21024 * Return from the translation cache and immediately request 21025 * a translation for the exit target. Commonly used for callees. 21026 */ 21027 .global dvmJitToInterpTraceSelectNoChain 21028dvmJitToInterpTraceSelectNoChain: 21029#if defined(WITH_JIT_TUNING) 21030 bl dvmBumpNoChain 21031#endif 21032 mov r0,rPC 21033 bl dvmJitGetTraceAddr @ Is there a translation? 21034 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21035 mov r1, rPC @ arg1 of translation may need this 21036 mov lr, #0 @ in case target is HANDLER_INTERPRET 21037 cmp r0,#0 @ !0 means translation exists 21038 bxne r0 @ continue native execution if so 21039 b 2f @ branch over to use the interpreter 21040 21041/* 21042 * Return from the translation cache and immediately request 21043 * a translation for the exit target. Commonly used following 21044 * invokes. 21045 */ 21046 .global dvmJitToInterpTraceSelect 21047dvmJitToInterpTraceSelect: 21048 ldr rPC,[lr, #-1] @ get our target PC 21049 add rINST,lr,#-5 @ save start of chain branch 21050 add rINST, #-4 @ .. which is 9 bytes back 21051 mov r0,rPC 21052 bl dvmJitGetTraceAddr @ Is there a translation? 21053 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21054 cmp r0,#0 21055 beq 2f 21056 mov r1,rINST 21057 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 21058 mov r1, rPC @ arg1 of translation may need this 21059 mov lr, #0 @ in case target is HANDLER_INTERPRET 21060 cmp r0,#0 @ successful chain? 21061 bxne r0 @ continue native execution 21062 b toInterpreter @ didn't chain - resume with interpreter 21063 21064/* No translation, so request one if profiling isn't disabled*/ 210652: 21066 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21067 GET_JIT_PROF_TABLE(r0) 21068 FETCH_INST() 21069 cmp r0, #0 21070 movne r2,#kJitTSelectRequestHot @ ask for trace selection 21071 bne common_selectTrace 21072 GET_INST_OPCODE(ip) 21073 GOTO_OPCODE(ip) 21074 21075/* 21076 * Return from the translation cache to the interpreter. 21077 * The return was done with a BLX from thumb mode, and 21078 * the following 32-bit word contains the target rPC value. 21079 * Note that lr (r14) will have its low-order bit set to denote 21080 * its thumb-mode origin. 21081 * 21082 * We'll need to stash our lr origin away, recover the new 21083 * target and then check to see if there is a translation available 21084 * for our new target. If so, we do a translation chain and 21085 * go back to native execution. Otherwise, it's back to the 21086 * interpreter (after treating this entry as a potential 21087 * trace start). 21088 */ 21089 .global dvmJitToInterpNormal 21090dvmJitToInterpNormal: 21091 ldr rPC,[lr, #-1] @ get our target PC 21092 add rINST,lr,#-5 @ save start of chain branch 21093 add rINST,#-4 @ .. which is 9 bytes back 21094#if defined(WITH_JIT_TUNING) 21095 bl dvmBumpNormal 21096#endif 21097 mov r0,rPC 21098 bl dvmJitGetTraceAddr @ Is there a translation? 21099 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21100 cmp r0,#0 21101 beq toInterpreter @ go if not, otherwise do chain 21102 mov r1,rINST 21103 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 21104 mov r1, rPC @ arg1 of translation may need this 21105 mov lr, #0 @ in case target is HANDLER_INTERPRET 21106 cmp r0,#0 @ successful chain? 21107 bxne r0 @ continue native execution 21108 b toInterpreter @ didn't chain - resume with interpreter 21109 21110/* 21111 * Return from the translation cache to the interpreter to do method invocation. 21112 * Check if translation exists for the callee, but don't chain to it. 21113 */ 21114 .global dvmJitToInterpNoChainNoProfile 21115dvmJitToInterpNoChainNoProfile: 21116#if defined(WITH_JIT_TUNING) 21117 bl dvmBumpNoChain 21118#endif 21119 mov r0,rPC 21120 bl dvmJitGetTraceAddr @ Is there a translation? 21121 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21122 mov r1, rPC @ arg1 of translation may need this 21123 mov lr, #0 @ in case target is HANDLER_INTERPRET 21124 cmp r0,#0 21125 bxne r0 @ continue native execution if so 21126 EXPORT_PC() 21127 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21128 FETCH_INST() 21129 GET_INST_OPCODE(ip) @ extract opcode from rINST 21130 GOTO_OPCODE(ip) @ jump to next instruction 21131 21132/* 21133 * Return from the translation cache to the interpreter to do method invocation. 21134 * Check if translation exists for the callee, but don't chain to it. 21135 */ 21136 .global dvmJitToInterpNoChain 21137dvmJitToInterpNoChain: 21138#if defined(WITH_JIT_TUNING) 21139 bl dvmBumpNoChain 21140#endif 21141 mov r0,rPC 21142 bl dvmJitGetTraceAddr @ Is there a translation? 21143 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21144 mov r1, rPC @ arg1 of translation may need this 21145 mov lr, #0 @ in case target is HANDLER_INTERPRET 21146 cmp r0,#0 21147 bxne r0 @ continue native execution if so 21148#endif 21149 21150/* 21151 * No translation, restore interpreter regs and start interpreting. 21152 * rSELF & rFP were preserved in the translated code, and rPC has 21153 * already been restored by the time we get here. We'll need to set 21154 * up rIBASE & rINST, and load the address of the JitTable into r0. 21155 */ 21156toInterpreter: 21157 EXPORT_PC() 21158 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21159 FETCH_INST() 21160 GET_JIT_PROF_TABLE(r0) 21161 @ NOTE: intended fallthrough 21162 21163/* 21164 * Common code to update potential trace start counter, and initiate 21165 * a trace-build if appropriate. On entry, rPC should point to the 21166 * next instruction to execute, and rINST should be already loaded with 21167 * the next opcode word, and r0 holds a pointer to the jit profile 21168 * table (pJitProfTable). 21169 */ 21170common_testUpdateProfile: 21171 cmp r0,#0 21172 GET_INST_OPCODE(ip) 21173 GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 21174 21175common_updateProfile: 21176 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 21177 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 21178 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 21179 GET_INST_OPCODE(ip) 21180 subs r1,r1,#1 @ decrement counter 21181 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 21182 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 21183 21184/* 21185 * Here, we switch to the debug interpreter to request 21186 * trace selection. First, though, check to see if there 21187 * is already a native translation in place (and, if so, 21188 * jump to it now). 21189 */ 21190 21191 GET_JIT_THRESHOLD(r1) 21192 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 21193 EXPORT_PC() 21194 mov r0,rPC 21195 bl dvmJitGetTraceAddr @ r0<- dvmJitGetTraceAddr(rPC) 21196 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21197 mov r1, rPC @ arg1 of translation may need this 21198 mov lr, #0 @ in case target is HANDLER_INTERPRET 21199 cmp r0,#0 21200#if !defined(WITH_SELF_VERIFICATION) 21201 bxne r0 @ jump to the translation 21202 mov r2,#kJitTSelectRequest @ ask for trace selection 21203 @ fall-through to common_selectTrace 21204#else 21205 moveq r2,#kJitTSelectRequest @ ask for trace selection 21206 beq common_selectTrace 21207 /* 21208 * At this point, we have a target translation. However, if 21209 * that translation is actually the interpret-only pseudo-translation 21210 * we want to treat it the same as no translation. 21211 */ 21212 mov r10, r0 @ save target 21213 bl dvmCompilerGetInterpretTemplate 21214 cmp r0, r10 @ special case? 21215 bne jitSVShadowRunStart @ set up self verification shadow space 21216 @ Need to clear the inJitCodeCache flag 21217 mov r3, #0 @ 0 means not in the JIT code cache 21218 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 21219 GET_INST_OPCODE(ip) 21220 GOTO_OPCODE(ip) 21221 /* no return */ 21222#endif 21223 21224/* 21225 * On entry: 21226 * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 21227 */ 21228common_selectTrace: 21229 21230 str r2,[rSELF,#offThread_jitState] 21231 mov r2,#kInterpEntryInstr @ normal entry reason 21232 str r2,[rSELF,#offThread_entryPoint] 21233 mov r1,#1 @ set changeInterp 21234 b common_gotoBail 21235 21236#if defined(WITH_SELF_VERIFICATION) 21237/* 21238 * Save PC and registers to shadow memory for self verification mode 21239 * before jumping to native translation. 21240 * On entry: 21241 * rPC, rFP, rSELF: the values that they should contain 21242 * r10: the address of the target translation. 21243 */ 21244jitSVShadowRunStart: 21245 mov r0,rPC @ r0<- program counter 21246 mov r1,rFP @ r1<- frame pointer 21247 mov r2,rSELF @ r2<- self (Thread) pointer 21248 mov r3,r10 @ r3<- target translation 21249 bl dvmSelfVerificationSaveState @ save registers to shadow space 21250 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 21251 bx r10 @ jump to the translation 21252 21253/* 21254 * Restore PC, registers, and interpreter state to original values 21255 * before jumping back to the interpreter. 21256 */ 21257jitSVShadowRunEnd: 21258 mov r1,rFP @ pass ending fp 21259 mov r3,rSELF @ pass self ptr for convenience 21260 bl dvmSelfVerificationRestoreState @ restore pc and fp values 21261 ldr rPC,[rSELF,#offThread_pc] @ restore PC 21262 ldr rFP,[rSELF,#offThread_fp] @ restore FP 21263 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 21264 cmp r1,#0 @ check for punt condition 21265 beq 1f 21266 mov r2,#kJitSelfVerification @ ask for self verification 21267 str r2,[rSELF,#offThread_jitState] 21268 mov r2,#kInterpEntryInstr @ normal entry reason 21269 str r2,[rSELF,#offThread_entryPoint] 21270 mov r1,#1 @ set changeInterp 21271 b common_gotoBail 21272 212731: @ exit to interpreter without check 21274 EXPORT_PC() 21275 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21276 FETCH_INST() 21277 GET_INST_OPCODE(ip) 21278 GOTO_OPCODE(ip) 21279#endif 21280 21281#endif 21282 21283/* 21284 * Common code when a backward branch is taken. 21285 * 21286 * TODO: we could avoid a branch by just setting r0 and falling through 21287 * into the common_periodicChecks code, and having a test on r0 at the 21288 * end determine if we should return to the caller or update & branch to 21289 * the next instr. 21290 * 21291 * On entry: 21292 * r9 is PC adjustment *in bytes* 21293 */ 21294common_backwardBranch: 21295 mov r0, #kInterpEntryInstr 21296 bl common_periodicChecks 21297#if defined(WITH_JIT) 21298 GET_JIT_PROF_TABLE(r0) 21299 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 21300 cmp r0,#0 21301 bne common_updateProfile 21302 GET_INST_OPCODE(ip) 21303 GOTO_OPCODE(ip) 21304#else 21305 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 21306 GET_INST_OPCODE(ip) @ extract opcode from rINST 21307 GOTO_OPCODE(ip) @ jump to next instruction 21308#endif 21309 21310 21311/* 21312 * Need to see if the thread needs to be suspended or debugger/profiler 21313 * activity has begun. If so, we suspend the thread or side-exit to 21314 * the debug interpreter as appropriate. 21315 * 21316 * The common case is no activity on any of these, so we want to figure 21317 * that out quickly. If something is up, we can then sort out what. 21318 * 21319 * We want to be fast if the VM was built without debugger or profiler 21320 * support, but we also need to recognize that the system is usually 21321 * shipped with both of these enabled. 21322 * 21323 * TODO: reduce this so we're just checking a single location. 21324 * 21325 * On entry: 21326 * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling) 21327 * r9 is trampoline PC adjustment *in bytes* 21328 */ 21329common_periodicChecks: 21330/* TUNING - make this a direct load when interpBreak moved to Thread */ 21331 ldr r1, [rSELF, #offThread_pInterpBreak] @ r3<- &interpBreak 21332 /* speculatively thread-specific suspend count */ 21333 ldr ip, [rSELF, #offThread_suspendCount] 21334 ldr r1, [r1] @ r1<- interpBreak 21335 cmp r1, #0 @ anything unusual? 21336 bxeq lr @ return if not 21337 /* 21338 * One or more interesting events have happened. Figure out what. 21339 * 21340 * r0 still holds the reentry type. 21341 */ 21342 cmp ip, #0 @ want suspend? 21343 beq 3f @ no, must be something else 21344 21345 stmfd sp!, {r0, lr} @ preserve r0 and lr 21346#if defined(WITH_JIT) 21347 /* 21348 * Refresh the Jit's cached copy of profile table pointer. This pointer 21349 * doubles as the Jit's on/off switch. 21350 */ 21351 ldr r3, [rSELF, #offThread_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 21352 mov r0, rSELF @ r0<- self 21353 ldr r3, [r3] @ r3 <- pJitProfTable 21354 EXPORT_PC() @ need for precise GC 21355 str r3, [rSELF, #offThread_pJitProfTable] @ refresh Jit's on/off switch 21356#else 21357 mov r0, rSELF @ r0<- self 21358 EXPORT_PC() @ need for precise GC 21359#endif 21360 bl dvmCheckSuspendPending @ do full check, suspend if necessary 21361 ldmfd sp!, {r0, lr} @ restore r0 and lr 21362 21363 /* 21364 * Reload the interpBreak flags - they may have changed while we 21365 * were suspended. 21366 */ 21367/* TUNING - direct load when InterpBreak moved to Thread */ 21368 ldr r1, [rSELF, #offThread_pInterpBreak] @ r1<- &interpBreak 21369 ldr r1, [r1] @ r1<- interpBreak 213703: 21371 /* 21372 * TODO: this code is too fragile. Need a general mechanism 21373 * to identify what actions to take by submode. Some profiling modes 21374 * (instruction count) need to single-step, while method tracing 21375 * may not. Debugging with breakpoints can run unfettered, but 21376 * source-level single-stepping requires Dalvik singlestepping. 21377 * GC may require a one-shot action and then full-speed resumption. 21378 */ 21379 ands r1, #(kSubModeDebuggerActive | kSubModeEmulatorTrace | kSubModeInstCounting) 21380 bxeq lr @ nothing to do, return 21381 21382 @ debugger/profiler enabled, bail out; self->entryPoint was set above 21383 str r0, [rSELF, #offThread_entryPoint] @ store r0, need for debug/prof 21384 add rPC, rPC, r9 @ update rPC 21385 mov r1, #1 @ "want switch" = true 21386 b common_gotoBail @ side exit 21387 21388 21389/* 21390 * The equivalent of "goto bail", this calls through the "bail handler". 21391 * 21392 * State registers will be saved to the "thread" area before bailing. 21393 * 21394 * On entry: 21395 * r1 is "bool changeInterp", indicating if we want to switch to the 21396 * other interpreter or just bail all the way out 21397 */ 21398common_gotoBail: 21399 SAVE_PC_FP_TO_SELF() @ export state to "thread" 21400 mov r0, rSELF @ r0<- self ptr 21401 b dvmMterpStdBail @ call(self, changeInterp) 21402 21403 @add r1, r1, #1 @ using (boolean+1) 21404 @add r0, rSELF, #offThread_jmpBuf @ r0<- &self->jmpBuf 21405 @bl _longjmp @ does not return 21406 @bl common_abort 21407 21408 21409/* 21410 * Common code for jumbo method invocation. 21411 * NOTE: this adjusts rPC to account for the difference in instruction width. 21412 * As a result, the savedPc in the stack frame will not be wholly accurate. So 21413 * long as that is only used for source file line number calculations, we're 21414 * okay. 21415 * 21416 * On entry: 21417 * r0 is "Method* methodToCall", the method we're trying to call 21418 */ 21419common_invokeMethodJumbo: 21420.LinvokeNewJumbo: 21421 @ prepare to copy args to "outs" area of current frame 21422 add rPC, rPC, #4 @ adjust pc to make return consistent 21423 FETCH(r2, 1) @ r2<- BBBB (arg count) 21424 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 21425 cmp r2, #0 @ no args? 21426 beq .LinvokeArgsDone @ if no args, skip the rest 21427 FETCH(r1, 2) @ r1<- CCCC 21428 b .LinvokeRangeArgs @ handle args like invoke range 21429 21430/* 21431 * Common code for method invocation with range. 21432 * 21433 * On entry: 21434 * r0 is "Method* methodToCall", the method we're trying to call 21435 */ 21436common_invokeMethodRange: 21437.LinvokeNewRange: 21438 @ prepare to copy args to "outs" area of current frame 21439 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 21440 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 21441 beq .LinvokeArgsDone @ if no args, skip the rest 21442 FETCH(r1, 2) @ r1<- CCCC 21443 21444.LinvokeRangeArgs: 21445 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 21446 @ (very few methods have > 10 args; could unroll for common cases) 21447 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 21448 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 214491: ldr r1, [r3], #4 @ val = *fp++ 21450 subs r2, r2, #1 @ count-- 21451 str r1, [r10], #4 @ *outs++ = val 21452 bne 1b @ ...while count != 0 21453 b .LinvokeArgsDone 21454 21455/* 21456 * Common code for method invocation without range. 21457 * 21458 * On entry: 21459 * r0 is "Method* methodToCall", the method we're trying to call 21460 */ 21461common_invokeMethodNoRange: 21462.LinvokeNewNoRange: 21463 @ prepare to copy args to "outs" area of current frame 21464 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 21465 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 21466 FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 21467 beq .LinvokeArgsDone 21468 21469 @ r0=methodToCall, r1=GFED, r2=count, r10=outs 21470.LinvokeNonRange: 21471 rsb r2, r2, #5 @ r2<- 5-r2 21472 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 21473 bl common_abort @ (skipped due to ARM prefetch) 214745: and ip, rINST, #0x0f00 @ isolate A 21475 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 21476 mov r0, r0 @ nop 21477 str r2, [r10, #-4]! @ *--outs = vA 214784: and ip, r1, #0xf000 @ isolate G 21479 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 21480 mov r0, r0 @ nop 21481 str r2, [r10, #-4]! @ *--outs = vG 214823: and ip, r1, #0x0f00 @ isolate F 21483 ldr r2, [rFP, ip, lsr #6] @ r2<- vF 21484 mov r0, r0 @ nop 21485 str r2, [r10, #-4]! @ *--outs = vF 214862: and ip, r1, #0x00f0 @ isolate E 21487 ldr r2, [rFP, ip, lsr #2] @ r2<- vE 21488 mov r0, r0 @ nop 21489 str r2, [r10, #-4]! @ *--outs = vE 214901: and ip, r1, #0x000f @ isolate D 21491 ldr r2, [rFP, ip, lsl #2] @ r2<- vD 21492 mov r0, r0 @ nop 21493 str r2, [r10, #-4]! @ *--outs = vD 214940: @ fall through to .LinvokeArgsDone 21495 21496.LinvokeArgsDone: @ r0=methodToCall 21497 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 21498 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 21499 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 21500 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 21501 @ find space for the new stack frame, check for overflow 21502 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 21503 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 21504 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 21505@ bl common_dumpRegs 21506 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd 21507 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 21508 cmp r3, r9 @ bottom < interpStackEnd? 21509 ldr lr, [rSELF, #offThread_pInterpBreak] 21510 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 21511 blo .LstackOverflow @ yes, this frame will overflow stack 21512 21513 @ set up newSaveArea 21514 ldr lr, [lr] @ lr<- active submodes 21515#ifdef EASY_GDB 21516 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 21517 str ip, [r10, #offStackSaveArea_prevSave] 21518#endif 21519 str rFP, [r10, #offStackSaveArea_prevFrame] 21520 str rPC, [r10, #offStackSaveArea_savedPc] 21521#if defined(WITH_JIT) 21522 mov r9, #0 21523 str r9, [r10, #offStackSaveArea_returnAddr] 21524#endif 21525 ands lr, #kSubModeMethodTrace @ method tracing? 21526 beq 1f @ skip if not 21527 stmfd sp!, {r0-r3} @ preserve r0-r3 21528 mov r1, rSELF 21529 @ r0=methodToCall, r1=rSELF 21530 bl dvmFastMethodTraceEnter 21531 ldmfd sp!, {r0-r3} @ restore r0-r3 215321: 21533 str r0, [r10, #offStackSaveArea_method] 21534 tst r3, #ACC_NATIVE 21535 bne .LinvokeNative 21536 21537 /* 21538 stmfd sp!, {r0-r3} 21539 bl common_printNewline 21540 mov r0, rFP 21541 mov r1, #0 21542 bl dvmDumpFp 21543 ldmfd sp!, {r0-r3} 21544 stmfd sp!, {r0-r3} 21545 mov r0, r1 21546 mov r1, r10 21547 bl dvmDumpFp 21548 bl common_printNewline 21549 ldmfd sp!, {r0-r3} 21550 */ 21551 21552 ldrh r9, [r2] @ r9 <- load INST from new PC 21553 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 21554 mov rPC, r2 @ publish new rPC 21555 21556 @ Update state values for the new method 21557 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST 21558 str r0, [rSELF, #offThread_method] @ self->method = methodToCall 21559 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ... 21560#if defined(WITH_JIT) 21561 GET_JIT_PROF_TABLE(r0) 21562 mov rFP, r1 @ fp = newFp 21563 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 21564 mov rINST, r9 @ publish new rINST 21565 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21566 cmp r0,#0 21567 bne common_updateProfile 21568 GOTO_OPCODE(ip) @ jump to next instruction 21569#else 21570 mov rFP, r1 @ fp = newFp 21571 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 21572 mov rINST, r9 @ publish new rINST 21573 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21574 GOTO_OPCODE(ip) @ jump to next instruction 21575#endif 21576 21577.LinvokeNative: 21578 @ Prep for the native call 21579 @ r0=methodToCall, r1=newFp, r10=newSaveArea 21580 ldr lr, [rSELF, #offThread_pInterpBreak] 21581 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->... 21582 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21583 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 21584 ldr lr, [lr] @ lr<- active submodes 21585 21586 mov r2, r0 @ r2<- methodToCall 21587 mov r0, r1 @ r0<- newFp (points to args) 21588 add r1, rSELF, #offThread_retval @ r1<- &retval 21589 mov r3, rSELF @ arg3<- self 21590 21591#ifdef ASSIST_DEBUGGER 21592 /* insert fake function header to help gdb find the stack frame */ 21593 b .Lskip 21594 .type dalvik_mterp, %function 21595dalvik_mterp: 21596 .fnstart 21597 MTERP_ENTRY1 21598 MTERP_ENTRY2 21599.Lskip: 21600#endif 21601 21602 ands lr, #kSubModeMethodTrace @ method tracing? 21603 bne 330f @ hop if so 21604 mov lr, pc @ set return addr 21605 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 21606220: 21607#if defined(WITH_JIT) 21608 ldr r3, [rSELF, #offThread_ppJitProfTable] @ Refresh Jit's on/off status 21609#endif 21610 21611 @ native return; r10=newSaveArea 21612 @ equivalent to dvmPopJniLocals 21613 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 21614 ldr r1, [rSELF, #offThread_exception] @ check for exception 21615#if defined(WITH_JIT) 21616 ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 21617#endif 21618 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21619 cmp r1, #0 @ null? 21620 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top 21621#if defined(WITH_JIT) 21622 str r3, [rSELF, #offThread_pJitProfTable] @ refresh cached on/off switch 21623#endif 21624 bne common_exceptionThrown @ no, handle exception 21625 21626 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 21627 GET_INST_OPCODE(ip) @ extract opcode from rINST 21628 GOTO_OPCODE(ip) @ jump to next instruction 21629 21630330: 21631 @ r2=JNIMethod, r6=rSELF 21632 stmfd sp!, {r2,r6} 21633 21634 mov lr, pc @ set return addr 21635 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 21636 21637 @ r0=JNIMethod, r1=rSELF 21638 ldmfd sp!, {r0-r1} 21639 bl dvmFastNativeMethodTraceExit 21640 b 220b 21641 21642.LstackOverflow: @ r0=methodToCall 21643 mov r1, r0 @ r1<- methodToCall 21644 mov r0, rSELF @ r0<- self 21645 bl dvmHandleStackOverflow 21646 b common_exceptionThrown 21647#ifdef ASSIST_DEBUGGER 21648 .fnend 21649 .size dalvik_mterp, .-dalvik_mterp 21650#endif 21651 21652 21653 /* 21654 * Common code for method invocation, calling through "glue code". 21655 * 21656 * TODO: now that we have range and non-range invoke handlers, this 21657 * needs to be split into two. Maybe just create entry points 21658 * that set r9 and jump here? 21659 * 21660 * On entry: 21661 * r0 is "Method* methodToCall", the method we're trying to call 21662 * r9 is "bool methodCallRange", indicating if this is a /range variant 21663 */ 21664 .if 0 21665.LinvokeOld: 21666 sub sp, sp, #8 @ space for args + pad 21667 FETCH(ip, 2) @ ip<- FEDC or CCCC 21668 mov r2, r0 @ A2<- methodToCall 21669 mov r0, rSELF @ A0<- self 21670 SAVE_PC_FP_TO_SELF() @ export state to "self" 21671 mov r1, r9 @ A1<- methodCallRange 21672 mov r3, rINST, lsr #8 @ A3<- AA 21673 str ip, [sp, #0] @ A4<- ip 21674 bl dvmMterp_invokeMethod @ call the C invokeMethod 21675 add sp, sp, #8 @ remove arg area 21676 b common_resumeAfterGlueCall @ continue to next instruction 21677 .endif 21678 21679 21680 21681/* 21682 * Common code for handling a return instruction. 21683 * 21684 * This does not return. 21685 */ 21686common_returnFromMethod: 21687.LreturnNew: 21688 mov r0, #kInterpEntryReturn 21689 mov r9, #0 21690 bl common_periodicChecks 21691 21692 ldr lr, [rSELF, #offThread_pInterpBreak] 21693 SAVEAREA_FROM_FP(r0, rFP) 21694 ldr lr, [lr] @ lr<- active submodes 21695 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 21696 ands lr, #kSubModeMethodTrace @ method tracing? 21697 beq 333f 21698 stmfd sp!, {r0-r3} @ preserve r0-r3 21699 mov r0, rSELF 21700 @ r0=rSELF 21701 bl dvmFastJavaMethodTraceExit 21702 ldmfd sp!, {r0-r3} @ restore r0-r3 21703333: 21704 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 21705 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 21706 @ r2<- method we're returning to 21707 cmp r2, #0 @ is this a break frame? 21708#if defined(WORKAROUND_CORTEX_A9_745320) 21709 /* Don't use conditional loads if the HW defect exists */ 21710 beq 101f 21711 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21712101: 21713#else 21714 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21715#endif 21716 mov r1, #0 @ "want switch" = false 21717 beq common_gotoBail @ break frame, bail out completely 21718 21719 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 21720 str r2, [rSELF, #offThread_method]@ self->method = newSave->method 21721 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 21722 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21723#if defined(WITH_JIT) 21724 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 21725 mov rPC, r9 @ publish new rPC 21726 str r1, [rSELF, #offThread_methodClassDex] 21727 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land 21728 cmp r10, #0 @ caller is compiled code 21729 blxne r10 21730 GET_INST_OPCODE(ip) @ extract opcode from rINST 21731 GOTO_OPCODE(ip) @ jump to next instruction 21732#else 21733 GET_INST_OPCODE(ip) @ extract opcode from rINST 21734 mov rPC, r9 @ publish new rPC 21735 str r1, [rSELF, #offThread_methodClassDex] 21736 GOTO_OPCODE(ip) @ jump to next instruction 21737#endif 21738 21739 /* 21740 * Return handling, calls through "glue code". 21741 */ 21742 .if 0 21743.LreturnOld: 21744 SAVE_PC_FP_TO_SELF() @ export state 21745 mov r0, rSELF @ arg to function 21746 bl dvmMterp_returnFromMethod 21747 b common_resumeAfterGlueCall 21748 .endif 21749 21750 21751/* 21752 * Somebody has thrown an exception. Handle it. 21753 * 21754 * If the exception processing code returns to us (instead of falling 21755 * out of the interpreter), continue with whatever the next instruction 21756 * now happens to be. 21757 * 21758 * This does not return. 21759 */ 21760 .global dvmMterpCommonExceptionThrown 21761dvmMterpCommonExceptionThrown: 21762common_exceptionThrown: 21763.LexceptionNew: 21764 mov r0, #kInterpEntryThrow 21765 mov r9, #0 21766 bl common_periodicChecks 21767 21768 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception 21769 mov r1, rSELF @ r1<- self 21770 mov r0, r9 @ r0<- exception 21771 bl dvmAddTrackedAlloc @ don't let the exception be GCed 21772 mov r3, #0 @ r3<- NULL 21773 str r3, [rSELF, #offThread_exception] @ self->exception = NULL 21774 21775 /* set up args and a local for "&fp" */ 21776 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 21777 str rFP, [sp, #-4]! @ *--sp = fp 21778 mov ip, sp @ ip<- &fp 21779 mov r3, #0 @ r3<- false 21780 str ip, [sp, #-4]! @ *--sp = &fp 21781 ldr r1, [rSELF, #offThread_method] @ r1<- self->method 21782 mov r0, rSELF @ r0<- self 21783 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 21784 mov r2, r9 @ r2<- exception 21785 sub r1, rPC, r1 @ r1<- pc - method->insns 21786 mov r1, r1, asr #1 @ r1<- offset in code units 21787 21788 /* call, r0 gets catchRelPc (a code-unit offset) */ 21789 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 21790 21791 /* fix earlier stack overflow if necessary; may trash rFP */ 21792 ldrb r1, [rSELF, #offThread_stackOverflowed] 21793 cmp r1, #0 @ did we overflow earlier? 21794 beq 1f @ no, skip ahead 21795 mov rFP, r0 @ save relPc result in rFP 21796 mov r0, rSELF @ r0<- self 21797 mov r1, r9 @ r1<- exception 21798 bl dvmCleanupStackOverflow @ call(self) 21799 mov r0, rFP @ restore result 218001: 21801 21802 /* update frame pointer and check result from dvmFindCatchBlock */ 21803 ldr rFP, [sp, #4] @ retrieve the updated rFP 21804 cmp r0, #0 @ is catchRelPc < 0? 21805 add sp, sp, #8 @ restore stack 21806 bmi .LnotCaughtLocally 21807 21808 /* adjust locals to match self->curFrame and updated PC */ 21809 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 21810 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 21811 str r1, [rSELF, #offThread_method] @ self->method = new method 21812 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 21813 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 21814 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 21815 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 21816 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth... 21817 21818 /* release the tracked alloc on the exception */ 21819 mov r0, r9 @ r0<- exception 21820 mov r1, rSELF @ r1<- self 21821 bl dvmReleaseTrackedAlloc @ release the exception 21822 21823 /* restore the exception if the handler wants it */ 21824 FETCH_INST() @ load rINST from rPC 21825 GET_INST_OPCODE(ip) @ extract opcode from rINST 21826 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 21827 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception 21828 GOTO_OPCODE(ip) @ jump to next instruction 21829 21830.LnotCaughtLocally: @ r9=exception 21831 /* fix stack overflow if necessary */ 21832 ldrb r1, [rSELF, #offThread_stackOverflowed] 21833 cmp r1, #0 @ did we overflow earlier? 21834 movne r0, rSELF @ if yes: r0<- self 21835 movne r1, r9 @ if yes: r1<- exception 21836 blne dvmCleanupStackOverflow @ if yes: call(self) 21837 21838 @ may want to show "not caught locally" debug messages here 21839#if DVM_SHOW_EXCEPTION >= 2 21840 /* call __android_log_print(prio, tag, format, ...) */ 21841 /* "Exception %s from %s:%d not caught locally" */ 21842 @ dvmLineNumFromPC(method, pc - method->insns) 21843 ldr r0, [rSELF, #offThread_method] 21844 ldr r1, [r0, #offMethod_insns] 21845 sub r1, rPC, r1 21846 asr r1, r1, #1 21847 bl dvmLineNumFromPC 21848 str r0, [sp, #-4]! 21849 @ dvmGetMethodSourceFile(method) 21850 ldr r0, [rSELF, #offThread_method] 21851 bl dvmGetMethodSourceFile 21852 str r0, [sp, #-4]! 21853 @ exception->clazz->descriptor 21854 ldr r3, [r9, #offObject_clazz] 21855 ldr r3, [r3, #offClassObject_descriptor] 21856 @ 21857 ldr r2, strExceptionNotCaughtLocally 21858 ldr r1, strLogTag 21859 mov r0, #3 @ LOG_DEBUG 21860 bl __android_log_print 21861#endif 21862 str r9, [rSELF, #offThread_exception] @ restore exception 21863 mov r0, r9 @ r0<- exception 21864 mov r1, rSELF @ r1<- self 21865 bl dvmReleaseTrackedAlloc @ release the exception 21866 mov r1, #0 @ "want switch" = false 21867 b common_gotoBail @ bail out 21868 21869 21870 /* 21871 * Exception handling, calls through "glue code". 21872 */ 21873 .if 0 21874.LexceptionOld: 21875 SAVE_PC_FP_TO_SELF() @ export state 21876 mov r0, rSELF @ arg to function 21877 bl dvmMterp_exceptionThrown 21878 b common_resumeAfterGlueCall 21879 .endif 21880 21881 21882/* 21883 * After returning from a "glued" function, pull out the updated 21884 * values and start executing at the next instruction. 21885 */ 21886common_resumeAfterGlueCall: 21887 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread 21888 FETCH_INST() @ load rINST from rPC 21889 GET_INST_OPCODE(ip) @ extract opcode from rINST 21890 GOTO_OPCODE(ip) @ jump to next instruction 21891 21892/* 21893 * Invalid array index. Note that our calling convention is strange; we use r1 21894 * and r3 because those just happen to be the registers all our callers are 21895 * using. We move r3 before calling the C function, but r1 happens to match. 21896 * r1: index 21897 * r3: size 21898 */ 21899common_errArrayIndex: 21900 EXPORT_PC() 21901 mov r0, r3 21902 bl dvmThrowArrayIndexOutOfBoundsException 21903 b common_exceptionThrown 21904 21905/* 21906 * Integer divide or mod by zero. 21907 */ 21908common_errDivideByZero: 21909 EXPORT_PC() 21910 ldr r0, strDivideByZero 21911 bl dvmThrowArithmeticException 21912 b common_exceptionThrown 21913 21914/* 21915 * Attempt to allocate an array with a negative size. 21916 * On entry: length in r1 21917 */ 21918common_errNegativeArraySize: 21919 EXPORT_PC() 21920 mov r0, r1 @ arg0 <- len 21921 bl dvmThrowNegativeArraySizeException @ (len) 21922 b common_exceptionThrown 21923 21924/* 21925 * Invocation of a non-existent method. 21926 * On entry: method name in r1 21927 */ 21928common_errNoSuchMethod: 21929 EXPORT_PC() 21930 mov r0, r1 21931 bl dvmThrowNoSuchMethodError 21932 b common_exceptionThrown 21933 21934/* 21935 * We encountered a null object when we weren't expecting one. We 21936 * export the PC, throw a NullPointerException, and goto the exception 21937 * processing code. 21938 */ 21939common_errNullObject: 21940 EXPORT_PC() 21941 mov r0, #0 21942 bl dvmThrowNullPointerException 21943 b common_exceptionThrown 21944 21945/* 21946 * For debugging, cause an immediate fault. The source address will 21947 * be in lr (use a bl instruction to jump here). 21948 */ 21949common_abort: 21950 ldr pc, .LdeadFood 21951.LdeadFood: 21952 .word 0xdeadf00d 21953 21954/* 21955 * Spit out a "we were here", preserving all registers. (The attempt 21956 * to save ip won't work, but we need to save an even number of 21957 * registers for EABI 64-bit stack alignment.) 21958 */ 21959 .macro SQUEAK num 21960common_squeak\num: 21961 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21962 ldr r0, strSqueak 21963 mov r1, #\num 21964 bl printf 21965 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21966 bx lr 21967 .endm 21968 21969 SQUEAK 0 21970 SQUEAK 1 21971 SQUEAK 2 21972 SQUEAK 3 21973 SQUEAK 4 21974 SQUEAK 5 21975 21976/* 21977 * Spit out the number in r0, preserving registers. 21978 */ 21979common_printNum: 21980 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21981 mov r1, r0 21982 ldr r0, strSqueak 21983 bl printf 21984 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21985 bx lr 21986 21987/* 21988 * Print a newline, preserving registers. 21989 */ 21990common_printNewline: 21991 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21992 ldr r0, strNewline 21993 bl printf 21994 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21995 bx lr 21996 21997 /* 21998 * Print the 32-bit quantity in r0 as a hex value, preserving registers. 21999 */ 22000common_printHex: 22001 stmfd sp!, {r0, r1, r2, r3, ip, lr} 22002 mov r1, r0 22003 ldr r0, strPrintHex 22004 bl printf 22005 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 22006 bx lr 22007 22008/* 22009 * Print the 64-bit quantity in r0-r1, preserving registers. 22010 */ 22011common_printLong: 22012 stmfd sp!, {r0, r1, r2, r3, ip, lr} 22013 mov r3, r1 22014 mov r2, r0 22015 ldr r0, strPrintLong 22016 bl printf 22017 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 22018 bx lr 22019 22020/* 22021 * Print full method info. Pass the Method* in r0. Preserves regs. 22022 */ 22023common_printMethod: 22024 stmfd sp!, {r0, r1, r2, r3, ip, lr} 22025 bl dvmMterpPrintMethod 22026 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 22027 bx lr 22028 22029/* 22030 * Call a C helper function that dumps regs and possibly some 22031 * additional info. Requires the C function to be compiled in. 22032 */ 22033 .if 0 22034common_dumpRegs: 22035 stmfd sp!, {r0, r1, r2, r3, ip, lr} 22036 bl dvmMterpDumpArmRegs 22037 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 22038 bx lr 22039 .endif 22040 22041#if 0 22042/* 22043 * Experiment on VFP mode. 22044 * 22045 * uint32_t setFPSCR(uint32_t val, uint32_t mask) 22046 * 22047 * Updates the bits specified by "mask", setting them to the values in "val". 22048 */ 22049setFPSCR: 22050 and r0, r0, r1 @ make sure no stray bits are set 22051 fmrx r2, fpscr @ get VFP reg 22052 mvn r1, r1 @ bit-invert mask 22053 and r2, r2, r1 @ clear masked bits 22054 orr r2, r2, r0 @ set specified bits 22055 fmxr fpscr, r2 @ set VFP reg 22056 mov r0, r2 @ return new value 22057 bx lr 22058 22059 .align 2 22060 .global dvmConfigureFP 22061 .type dvmConfigureFP, %function 22062dvmConfigureFP: 22063 stmfd sp!, {ip, lr} 22064 /* 0x03000000 sets DN/FZ */ 22065 /* 0x00009f00 clears the six exception enable flags */ 22066 bl common_squeak0 22067 mov r0, #0x03000000 @ r0<- 0x03000000 22068 add r1, r0, #0x9f00 @ r1<- 0x03009f00 22069 bl setFPSCR 22070 ldmfd sp!, {ip, pc} 22071#endif 22072 22073 22074/* 22075 * String references, must be close to the code that uses them. 22076 */ 22077 .align 2 22078strDivideByZero: 22079 .word .LstrDivideByZero 22080strLogTag: 22081 .word .LstrLogTag 22082strExceptionNotCaughtLocally: 22083 .word .LstrExceptionNotCaughtLocally 22084 22085strNewline: 22086 .word .LstrNewline 22087strSqueak: 22088 .word .LstrSqueak 22089strPrintHex: 22090 .word .LstrPrintHex 22091strPrintLong: 22092 .word .LstrPrintLong 22093 22094/* 22095 * Zero-terminated ASCII string data. 22096 * 22097 * On ARM we have two choices: do like gcc does, and LDR from a .word 22098 * with the address, or use an ADR pseudo-op to get the address 22099 * directly. ADR saves 4 bytes and an indirection, but it's using a 22100 * PC-relative addressing mode and hence has a limited range, which 22101 * makes it not work well with mergeable string sections. 22102 */ 22103 .section .rodata.str1.4,"aMS",%progbits,1 22104 22105.LstrBadEntryPoint: 22106 .asciz "Bad entry point %d\n" 22107.LstrFilledNewArrayNotImpl: 22108 .asciz "filled-new-array only implemented for objects and 'int'" 22109.LstrDivideByZero: 22110 .asciz "divide by zero" 22111.LstrLogTag: 22112 .asciz "mterp" 22113.LstrExceptionNotCaughtLocally: 22114 .asciz "Exception %s from %s:%d not caught locally\n" 22115 22116.LstrNewline: 22117 .asciz "\n" 22118.LstrSqueak: 22119 .asciz "<%d>" 22120.LstrPrintHex: 22121 .asciz "<0x%x>" 22122.LstrPrintLong: 22123 .asciz "<%lld>" 22124 22125