InterpAsm-armv5te-vfp.S revision 8cd640b8327e2591c8dd8a69093fa1fc6c901c05
1/* 2 * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: armv5te/header.S */ 8/* 9 * Copyright (C) 2008 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 * ARMv5 definitions and declarations. 26 */ 27 28/* 29ARM EABI general notes: 30 31r0-r3 hold first 4 args to a method; they are not preserved across method calls 32r4-r8 are available for general use 33r9 is given special treatment in some situations, but not for us 34r10 (sl) seems to be generally available 35r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36r12 (ip) is scratch -- not preserved across method calls 37r13 (sp) should be managed carefully in case a signal arrives 38r14 (lr) must be preserved 39r15 (pc) can be tinkered with directly 40 41r0 holds returns of <= 4 bytes 42r0-r1 hold returns of 8 bytes, low word in r0 43 44Callee must save/restore r4+ (except r12) if it modifies them. If VFP 45is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46s0-s15 (d0-d7, q0-a3) do not need to be. 47 48Stack is "full descending". Only the arguments that don't fit in the first 4 49registers are placed on the stack. "sp" points at the first stacked argument 50(i.e. the 5th arg). 51 52VFP: single-precision results in s0, double-precision results in d0. 53 54In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 5564-bit quantities (long long, double) must be 64-bit aligned. 56*/ 57 58/* 59Mterp and ARM notes: 60 61The following registers have fixed assignments: 62 63 reg nick purpose 64 r4 rPC interpreted program counter, used for fetching instructions 65 r5 rFP interpreted frame pointer, used for accessing locals and args 66 r6 rSELF self (Thread) pointer 67 r7 rINST first 16-bit code unit of current instruction 68 r8 rIBASE interpreted instruction base pointer, used for computed goto 69 70Macros are provided for common operations. Each macro MUST emit only 71one instruction to make instruction-counting easier. They MUST NOT alter 72unspecified registers or condition codes. 73*/ 74 75/* single-purpose registers, given names for clarity */ 76#define rPC r4 77#define rFP r5 78#define rSELF r6 79#define rINST r7 80#define rIBASE r8 81 82/* save/restore the PC and/or FP from the thread struct */ 83#define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc] 84#define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc] 85#define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_fp] 86#define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_fp] 87#define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP} 88#define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP} 89 90/* 91 * "export" the PC to the stack frame, f/b/o future exception objects. Must 92 * be done *before* something throws. 93 * 94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96 * 97 * It's okay to do this more than once. 98 */ 99#define EXPORT_PC() \ 100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101 102/* 103 * Given a frame pointer, find the stack save area. 104 * 105 * In C this is "((StackSaveArea*)(_fp) -1)". 106 */ 107#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108 sub _reg, _fpreg, #sizeofStackSaveArea 109 110/* 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112 */ 113#define FETCH_INST() ldrh rINST, [rPC] 114 115/* 116 * Fetch the next instruction from the specified offset. Advances rPC 117 * to point to the next instruction. "_count" is in 16-bit code units. 118 * 119 * Because of the limited size of immediate constants on ARM, this is only 120 * suitable for small forward movements (i.e. don't try to implement "goto" 121 * with this). 122 * 123 * This must come AFTER anything that can throw an exception, or the 124 * exception catch may miss. (This also implies that it must come after 125 * EXPORT_PC().) 126 */ 127#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 128 129/* 130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132 */ 133#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134 ldrh _dreg, [_sreg, #((_count)*2)]! 135 136/* 137 * Fetch the next instruction from an offset specified by _reg. Updates 138 * rPC to point to the next instruction. "_reg" must specify the distance 139 * in bytes, *not* 16-bit code units, and may be a signed value. 140 * 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 142 * bits that hold the shift distance are used for the half/byte/sign flags. 143 * In some cases we can pre-double _reg for free, so we require a byte offset 144 * here. 145 */ 146#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147 148/* 149 * Fetch a half-word code unit from an offset past the current PC. The 150 * "_count" value is in 16-bit code units. Does not advance rPC. 151 * 152 * The "_S" variant works the same but treats the value as signed. 153 */ 154#define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)] 155#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #((_count)*2)] 156 157/* 158 * Fetch one byte from an offset past the current PC. Pass in the same 159 * "_count" as you would for FETCH, and an additional 0/1 indicating which 160 * byte of the halfword you want (lo/hi). 161 */ 162#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #((_count)*2+(_byte))] 163 164/* 165 * Put the instruction's opcode field into the specified register. 166 */ 167#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168 169/* 170 * Put the prefetched instruction's opcode field into the specified register. 171 */ 172#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173 174/* 175 * Begin executing the opcode in _reg. Because this only jumps within the 176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177 */ 178#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 180#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 181 182/* 183 * Get/set the 32-bit value from a Dalvik register. 184 */ 185#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 186#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 187 188#if defined(WITH_JIT) 189#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rSELF,#offThread_pJitProfTable] 190#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rSELF,#offThread_jitThreshold] 191#endif 192 193/* 194 * Convert a virtual register index into an address. 195 */ 196#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 197 add _reg, rFP, _vreg, lsl #2 198 199/* 200 * This is a #include, not a %include, because we want the C pre-processor 201 * to expand the macros into assembler assignment statements. 202 */ 203#include "../common/asm-constants.h" 204 205#if defined(WITH_JIT) 206#include "../common/jit-config.h" 207#endif 208 209/* File: armv5te/platform.S */ 210/* 211 * =========================================================================== 212 * CPU-version-specific defines 213 * =========================================================================== 214 */ 215 216/* 217 * Macro for data memory barrier; not meaningful pre-ARMv6K. 218 */ 219.macro SMP_DMB 220.endm 221 222/* 223 * Macro for data memory barrier; not meaningful pre-ARMv6K. 224 */ 225.macro SMP_DMB_ST 226.endm 227 228/* File: armv5te/entry.S */ 229/* 230 * Copyright (C) 2008 The Android Open Source Project 231 * 232 * Licensed under the Apache License, Version 2.0 (the "License"); 233 * you may not use this file except in compliance with the License. 234 * You may obtain a copy of the License at 235 * 236 * http://www.apache.org/licenses/LICENSE-2.0 237 * 238 * Unless required by applicable law or agreed to in writing, software 239 * distributed under the License is distributed on an "AS IS" BASIS, 240 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 241 * See the License for the specific language governing permissions and 242 * limitations under the License. 243 */ 244/* 245 * Interpreter entry point. 246 */ 247 248/* 249 * We don't have formal stack frames, so gdb scans upward in the code 250 * to find the start of the function (a label with the %function type), 251 * and then looks at the next few instructions to figure out what 252 * got pushed onto the stack. From this it figures out how to restore 253 * the registers, including PC, for the previous stack frame. If gdb 254 * sees a non-function label, it stops scanning, so either we need to 255 * have nothing but assembler-local labels between the entry point and 256 * the break, or we need to fake it out. 257 * 258 * When this is defined, we add some stuff to make gdb less confused. 259 */ 260#define ASSIST_DEBUGGER 1 261 262 .text 263 .align 2 264 .global dvmMterpStdRun 265 .type dvmMterpStdRun, %function 266 267/* 268 * On entry: 269 * r0 Thread* self 270 * 271 * This function returns a boolean "changeInterp" value. The return comes 272 * via a call to dvmMterpStdBail(). 273 */ 274dvmMterpStdRun: 275#define MTERP_ENTRY1 \ 276 .save {r4-r10,fp,lr}; \ 277 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 278#define MTERP_ENTRY2 \ 279 .pad #4; \ 280 sub sp, sp, #4 @ align 64 281 282 .fnstart 283 MTERP_ENTRY1 284 MTERP_ENTRY2 285 286 /* save stack pointer, add magic word for debuggerd */ 287 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return 288 289 /* set up "named" registers, figure out entry point */ 290 mov rSELF, r0 @ set rSELF 291 ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI 292 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread" 293 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE 294 cmp r1, #kInterpEntryInstr @ usual case? 295 bne .Lnot_instr @ no, handle it 296 297#if defined(WITH_JIT) 298.LentryInstr: 299 /* Entry is always a possible trace start */ 300 GET_JIT_PROF_TABLE(r0) 301 FETCH_INST() 302 mov r1, #0 @ prepare the value for the new state 303 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 304 cmp r0,#0 @ is profiling disabled? 305#if !defined(WITH_SELF_VERIFICATION) 306 bne common_updateProfile @ profiling is enabled 307#else 308 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state 309 beq 1f @ profiling is disabled 310 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 311 cmp r3, #kSVSTraceSelect @ hot trace following? 312 moveq r2,#kJitTSelectRequestHot @ ask for trace selection 313 beq common_selectTrace @ go build the trace 314 cmp r3, #kSVSNoProfile @ don't profile the next instruction? 315 beq 1f @ intrepret the next instruction 316 b common_updateProfile @ collect profiles 317#endif 3181: 319 GET_INST_OPCODE(ip) 320 GOTO_OPCODE(ip) 321#else 322 /* start executing the instruction at rPC */ 323 FETCH_INST() @ load rINST from rPC 324 GET_INST_OPCODE(ip) @ extract opcode from rINST 325 GOTO_OPCODE(ip) @ jump to next instruction 326#endif 327 328.Lnot_instr: 329 cmp r1, #kInterpEntryReturn @ were we returning from a method? 330 beq common_returnFromMethod 331 332.Lnot_return: 333 cmp r1, #kInterpEntryThrow @ were we throwing an exception? 334 beq common_exceptionThrown 335 336#if defined(WITH_JIT) 337.Lnot_throw: 338 ldr r10,[rSELF, #offThread_jitResumeNPC] 339 ldr r2,[rSELF, #offThread_jitResumeDPC] 340 cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 341 bne .Lbad_arg 342 cmp rPC,r2 343 bne .LentryInstr @ must have branched, don't resume 344#if defined(WITH_SELF_VERIFICATION) 345 @ self->entryPoint will be set in dvmSelfVerificationSaveState 346 b jitSVShadowRunStart @ re-enter the translation after the 347 @ single-stepped instruction 348 @noreturn 349#endif 350 mov r1, #kInterpEntryInstr 351 str r1, [rSELF, #offThread_entryPoint] 352 bx r10 @ re-enter the translation 353#endif 354 355.Lbad_arg: 356 ldr r0, strBadEntryPoint 357 @ r1 holds value of entryPoint 358 bl printf 359 bl dvmAbort 360 .fnend 361 .size dvmMterpStdRun, .-dvmMterpStdRun 362 363 364 .global dvmMterpStdBail 365 .type dvmMterpStdBail, %function 366 367/* 368 * Restore the stack pointer and PC from the save point established on entry. 369 * This is essentially the same as a longjmp, but should be cheaper. The 370 * last instruction causes us to return to whoever called dvmMterpStdRun. 371 * 372 * We pushed some registers on the stack in dvmMterpStdRun, then saved 373 * SP and LR. Here we restore SP, restore the registers, and then restore 374 * LR to PC. 375 * 376 * On entry: 377 * r0 Thread* self 378 * r1 bool changeInterp 379 */ 380dvmMterpStdBail: 381 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP 382 mov r0, r1 @ return the changeInterp value 383 add sp, sp, #4 @ un-align 64 384 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return 385 386 387/* 388 * String references. 389 */ 390strBadEntryPoint: 391 .word .LstrBadEntryPoint 392 393 394 .global dvmAsmInstructionStart 395 .type dvmAsmInstructionStart, %function 396dvmAsmInstructionStart = .L_OP_NOP 397 .text 398 399/* ------------------------------ */ 400 .balign 64 401.L_OP_NOP: /* 0x00 */ 402/* File: armv5te/OP_NOP.S */ 403 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 404 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 405 GOTO_OPCODE(ip) @ execute it 406 407#ifdef ASSIST_DEBUGGER 408 /* insert fake function header to help gdb find the stack frame */ 409 .type dalvik_inst, %function 410dalvik_inst: 411 .fnstart 412 MTERP_ENTRY1 413 MTERP_ENTRY2 414 .fnend 415#endif 416 417/* ------------------------------ */ 418 .balign 64 419.L_OP_MOVE: /* 0x01 */ 420/* File: armv5te/OP_MOVE.S */ 421 /* for move, move-object, long-to-int */ 422 /* op vA, vB */ 423 mov r1, rINST, lsr #12 @ r1<- B from 15:12 424 mov r0, rINST, lsr #8 @ r0<- A from 11:8 425 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 426 GET_VREG(r2, r1) @ r2<- fp[B] 427 and r0, r0, #15 428 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 429 SET_VREG(r2, r0) @ fp[A]<- r2 430 GOTO_OPCODE(ip) @ execute next instruction 431 432/* ------------------------------ */ 433 .balign 64 434.L_OP_MOVE_FROM16: /* 0x02 */ 435/* File: armv5te/OP_MOVE_FROM16.S */ 436 /* for: move/from16, move-object/from16 */ 437 /* op vAA, vBBBB */ 438 FETCH(r1, 1) @ r1<- BBBB 439 mov r0, rINST, lsr #8 @ r0<- AA 440 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 441 GET_VREG(r2, r1) @ r2<- fp[BBBB] 442 GET_INST_OPCODE(ip) @ extract opcode from rINST 443 SET_VREG(r2, r0) @ fp[AA]<- r2 444 GOTO_OPCODE(ip) @ jump to next instruction 445 446/* ------------------------------ */ 447 .balign 64 448.L_OP_MOVE_16: /* 0x03 */ 449/* File: armv5te/OP_MOVE_16.S */ 450 /* for: move/16, move-object/16 */ 451 /* op vAAAA, vBBBB */ 452 FETCH(r1, 2) @ r1<- BBBB 453 FETCH(r0, 1) @ r0<- AAAA 454 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 455 GET_VREG(r2, r1) @ r2<- fp[BBBB] 456 GET_INST_OPCODE(ip) @ extract opcode from rINST 457 SET_VREG(r2, r0) @ fp[AAAA]<- r2 458 GOTO_OPCODE(ip) @ jump to next instruction 459 460/* ------------------------------ */ 461 .balign 64 462.L_OP_MOVE_WIDE: /* 0x04 */ 463/* File: armv5te/OP_MOVE_WIDE.S */ 464 /* move-wide vA, vB */ 465 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 466 mov r2, rINST, lsr #8 @ r2<- A(+) 467 mov r3, rINST, lsr #12 @ r3<- B 468 and r2, r2, #15 469 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 470 add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 471 ldmia r3, {r0-r1} @ r0/r1<- fp[B] 472 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 473 GET_INST_OPCODE(ip) @ extract opcode from rINST 474 stmia r2, {r0-r1} @ fp[A]<- r0/r1 475 GOTO_OPCODE(ip) @ jump to next instruction 476 477/* ------------------------------ */ 478 .balign 64 479.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 480/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 481 /* move-wide/from16 vAA, vBBBB */ 482 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 483 FETCH(r3, 1) @ r3<- BBBB 484 mov r2, rINST, lsr #8 @ r2<- AA 485 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 486 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 487 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 488 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 489 GET_INST_OPCODE(ip) @ extract opcode from rINST 490 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 491 GOTO_OPCODE(ip) @ jump to next instruction 492 493/* ------------------------------ */ 494 .balign 64 495.L_OP_MOVE_WIDE_16: /* 0x06 */ 496/* File: armv5te/OP_MOVE_WIDE_16.S */ 497 /* move-wide/16 vAAAA, vBBBB */ 498 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 499 FETCH(r3, 2) @ r3<- BBBB 500 FETCH(r2, 1) @ r2<- AAAA 501 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 502 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 503 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 504 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 505 GET_INST_OPCODE(ip) @ extract opcode from rINST 506 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 507 GOTO_OPCODE(ip) @ jump to next instruction 508 509/* ------------------------------ */ 510 .balign 64 511.L_OP_MOVE_OBJECT: /* 0x07 */ 512/* File: armv5te/OP_MOVE_OBJECT.S */ 513/* File: armv5te/OP_MOVE.S */ 514 /* for move, move-object, long-to-int */ 515 /* op vA, vB */ 516 mov r1, rINST, lsr #12 @ r1<- B from 15:12 517 mov r0, rINST, lsr #8 @ r0<- A from 11:8 518 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 519 GET_VREG(r2, r1) @ r2<- fp[B] 520 and r0, r0, #15 521 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 522 SET_VREG(r2, r0) @ fp[A]<- r2 523 GOTO_OPCODE(ip) @ execute next instruction 524 525 526/* ------------------------------ */ 527 .balign 64 528.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 529/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 530/* File: armv5te/OP_MOVE_FROM16.S */ 531 /* for: move/from16, move-object/from16 */ 532 /* op vAA, vBBBB */ 533 FETCH(r1, 1) @ r1<- BBBB 534 mov r0, rINST, lsr #8 @ r0<- AA 535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 536 GET_VREG(r2, r1) @ r2<- fp[BBBB] 537 GET_INST_OPCODE(ip) @ extract opcode from rINST 538 SET_VREG(r2, r0) @ fp[AA]<- r2 539 GOTO_OPCODE(ip) @ jump to next instruction 540 541 542/* ------------------------------ */ 543 .balign 64 544.L_OP_MOVE_OBJECT_16: /* 0x09 */ 545/* File: armv5te/OP_MOVE_OBJECT_16.S */ 546/* File: armv5te/OP_MOVE_16.S */ 547 /* for: move/16, move-object/16 */ 548 /* op vAAAA, vBBBB */ 549 FETCH(r1, 2) @ r1<- BBBB 550 FETCH(r0, 1) @ r0<- AAAA 551 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 552 GET_VREG(r2, r1) @ r2<- fp[BBBB] 553 GET_INST_OPCODE(ip) @ extract opcode from rINST 554 SET_VREG(r2, r0) @ fp[AAAA]<- r2 555 GOTO_OPCODE(ip) @ jump to next instruction 556 557 558/* ------------------------------ */ 559 .balign 64 560.L_OP_MOVE_RESULT: /* 0x0a */ 561/* File: armv5te/OP_MOVE_RESULT.S */ 562 /* for: move-result, move-result-object */ 563 /* op vAA */ 564 mov r2, rINST, lsr #8 @ r2<- AA 565 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 566 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 567 GET_INST_OPCODE(ip) @ extract opcode from rINST 568 SET_VREG(r0, r2) @ fp[AA]<- r0 569 GOTO_OPCODE(ip) @ jump to next instruction 570 571/* ------------------------------ */ 572 .balign 64 573.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 574/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 575 /* move-result-wide vAA */ 576 mov r2, rINST, lsr #8 @ r2<- AA 577 add r3, rSELF, #offThread_retval @ r3<- &self->retval 578 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 579 ldmia r3, {r0-r1} @ r0/r1<- retval.j 580 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 581 GET_INST_OPCODE(ip) @ extract opcode from rINST 582 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 583 GOTO_OPCODE(ip) @ jump to next instruction 584 585/* ------------------------------ */ 586 .balign 64 587.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 588/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 589/* File: armv5te/OP_MOVE_RESULT.S */ 590 /* for: move-result, move-result-object */ 591 /* op vAA */ 592 mov r2, rINST, lsr #8 @ r2<- AA 593 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 594 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 595 GET_INST_OPCODE(ip) @ extract opcode from rINST 596 SET_VREG(r0, r2) @ fp[AA]<- r0 597 GOTO_OPCODE(ip) @ jump to next instruction 598 599 600/* ------------------------------ */ 601 .balign 64 602.L_OP_MOVE_EXCEPTION: /* 0x0d */ 603/* File: armv5te/OP_MOVE_EXCEPTION.S */ 604 /* move-exception vAA */ 605 mov r2, rINST, lsr #8 @ r2<- AA 606 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass 607 mov r1, #0 @ r1<- 0 608 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 609 SET_VREG(r3, r2) @ fp[AA]<- exception obj 610 GET_INST_OPCODE(ip) @ extract opcode from rINST 611 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass 612 GOTO_OPCODE(ip) @ jump to next instruction 613 614/* ------------------------------ */ 615 .balign 64 616.L_OP_RETURN_VOID: /* 0x0e */ 617/* File: armv5te/OP_RETURN_VOID.S */ 618 b common_returnFromMethod 619 620/* ------------------------------ */ 621 .balign 64 622.L_OP_RETURN: /* 0x0f */ 623/* File: armv5te/OP_RETURN.S */ 624 /* 625 * Return a 32-bit value. Copies the return value into the "thread" 626 * structure, then jumps to the return handler. 627 * 628 * for: return, return-object 629 */ 630 /* op vAA */ 631 mov r2, rINST, lsr #8 @ r2<- AA 632 GET_VREG(r0, r2) @ r0<- vAA 633 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 634 b common_returnFromMethod 635 636/* ------------------------------ */ 637 .balign 64 638.L_OP_RETURN_WIDE: /* 0x10 */ 639/* File: armv5te/OP_RETURN_WIDE.S */ 640 /* 641 * Return a 64-bit value. Copies the return value into the "thread" 642 * structure, then jumps to the return handler. 643 */ 644 /* return-wide vAA */ 645 mov r2, rINST, lsr #8 @ r2<- AA 646 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 647 add r3, rSELF, #offThread_retval @ r3<- &self->retval 648 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 649 stmia r3, {r0-r1} @ retval<- r0/r1 650 b common_returnFromMethod 651 652/* ------------------------------ */ 653 .balign 64 654.L_OP_RETURN_OBJECT: /* 0x11 */ 655/* File: armv5te/OP_RETURN_OBJECT.S */ 656/* File: armv5te/OP_RETURN.S */ 657 /* 658 * Return a 32-bit value. Copies the return value into the "thread" 659 * structure, then jumps to the return handler. 660 * 661 * for: return, return-object 662 */ 663 /* op vAA */ 664 mov r2, rINST, lsr #8 @ r2<- AA 665 GET_VREG(r0, r2) @ r0<- vAA 666 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 667 b common_returnFromMethod 668 669 670/* ------------------------------ */ 671 .balign 64 672.L_OP_CONST_4: /* 0x12 */ 673/* File: armv5te/OP_CONST_4.S */ 674 /* const/4 vA, #+B */ 675 mov r1, rINST, lsl #16 @ r1<- Bxxx0000 676 mov r0, rINST, lsr #8 @ r0<- A+ 677 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 678 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 679 and r0, r0, #15 680 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 681 SET_VREG(r1, r0) @ fp[A]<- r1 682 GOTO_OPCODE(ip) @ execute next instruction 683 684/* ------------------------------ */ 685 .balign 64 686.L_OP_CONST_16: /* 0x13 */ 687/* File: armv5te/OP_CONST_16.S */ 688 /* const/16 vAA, #+BBBB */ 689 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 690 mov r3, rINST, lsr #8 @ r3<- AA 691 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 692 SET_VREG(r0, r3) @ vAA<- r0 693 GET_INST_OPCODE(ip) @ extract opcode from rINST 694 GOTO_OPCODE(ip) @ jump to next instruction 695 696/* ------------------------------ */ 697 .balign 64 698.L_OP_CONST: /* 0x14 */ 699/* File: armv5te/OP_CONST.S */ 700 /* const vAA, #+BBBBbbbb */ 701 mov r3, rINST, lsr #8 @ r3<- AA 702 FETCH(r0, 1) @ r0<- bbbb (low) 703 FETCH(r1, 2) @ r1<- BBBB (high) 704 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 705 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 706 GET_INST_OPCODE(ip) @ extract opcode from rINST 707 SET_VREG(r0, r3) @ vAA<- r0 708 GOTO_OPCODE(ip) @ jump to next instruction 709 710/* ------------------------------ */ 711 .balign 64 712.L_OP_CONST_HIGH16: /* 0x15 */ 713/* File: armv5te/OP_CONST_HIGH16.S */ 714 /* const/high16 vAA, #+BBBB0000 */ 715 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 716 mov r3, rINST, lsr #8 @ r3<- AA 717 mov r0, r0, lsl #16 @ r0<- BBBB0000 718 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 719 SET_VREG(r0, r3) @ vAA<- r0 720 GET_INST_OPCODE(ip) @ extract opcode from rINST 721 GOTO_OPCODE(ip) @ jump to next instruction 722 723/* ------------------------------ */ 724 .balign 64 725.L_OP_CONST_WIDE_16: /* 0x16 */ 726/* File: armv5te/OP_CONST_WIDE_16.S */ 727 /* const-wide/16 vAA, #+BBBB */ 728 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 729 mov r3, rINST, lsr #8 @ r3<- AA 730 mov r1, r0, asr #31 @ r1<- ssssssss 731 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 732 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 733 GET_INST_OPCODE(ip) @ extract opcode from rINST 734 stmia r3, {r0-r1} @ vAA<- r0/r1 735 GOTO_OPCODE(ip) @ jump to next instruction 736 737/* ------------------------------ */ 738 .balign 64 739.L_OP_CONST_WIDE_32: /* 0x17 */ 740/* File: armv5te/OP_CONST_WIDE_32.S */ 741 /* const-wide/32 vAA, #+BBBBbbbb */ 742 FETCH(r0, 1) @ r0<- 0000bbbb (low) 743 mov r3, rINST, lsr #8 @ r3<- AA 744 FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 745 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 746 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 747 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 748 mov r1, r0, asr #31 @ r1<- ssssssss 749 GET_INST_OPCODE(ip) @ extract opcode from rINST 750 stmia r3, {r0-r1} @ vAA<- r0/r1 751 GOTO_OPCODE(ip) @ jump to next instruction 752 753/* ------------------------------ */ 754 .balign 64 755.L_OP_CONST_WIDE: /* 0x18 */ 756/* File: armv5te/OP_CONST_WIDE.S */ 757 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 758 FETCH(r0, 1) @ r0<- bbbb (low) 759 FETCH(r1, 2) @ r1<- BBBB (low middle) 760 FETCH(r2, 3) @ r2<- hhhh (high middle) 761 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 762 FETCH(r3, 4) @ r3<- HHHH (high) 763 mov r9, rINST, lsr #8 @ r9<- AA 764 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 765 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 766 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 767 GET_INST_OPCODE(ip) @ extract opcode from rINST 768 stmia r9, {r0-r1} @ vAA<- r0/r1 769 GOTO_OPCODE(ip) @ jump to next instruction 770 771/* ------------------------------ */ 772 .balign 64 773.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 774/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 775 /* const-wide/high16 vAA, #+BBBB000000000000 */ 776 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 777 mov r3, rINST, lsr #8 @ r3<- AA 778 mov r0, #0 @ r0<- 00000000 779 mov r1, r1, lsl #16 @ r1<- BBBB0000 780 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 781 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 782 GET_INST_OPCODE(ip) @ extract opcode from rINST 783 stmia r3, {r0-r1} @ vAA<- r0/r1 784 GOTO_OPCODE(ip) @ jump to next instruction 785 786/* ------------------------------ */ 787 .balign 64 788.L_OP_CONST_STRING: /* 0x1a */ 789/* File: armv5te/OP_CONST_STRING.S */ 790 /* const/string vAA, String@BBBB */ 791 FETCH(r1, 1) @ r1<- BBBB 792 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 793 mov r9, rINST, lsr #8 @ r9<- AA 794 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 795 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 796 cmp r0, #0 @ not yet resolved? 797 beq .LOP_CONST_STRING_resolve 798 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 799 GET_INST_OPCODE(ip) @ extract opcode from rINST 800 SET_VREG(r0, r9) @ vAA<- r0 801 GOTO_OPCODE(ip) @ jump to next instruction 802 803/* ------------------------------ */ 804 .balign 64 805.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 806/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 807 /* const/string vAA, String@BBBBBBBB */ 808 FETCH(r0, 1) @ r0<- bbbb (low) 809 FETCH(r1, 2) @ r1<- BBBB (high) 810 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 811 mov r9, rINST, lsr #8 @ r9<- AA 812 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 813 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 814 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 815 cmp r0, #0 816 beq .LOP_CONST_STRING_JUMBO_resolve 817 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 818 GET_INST_OPCODE(ip) @ extract opcode from rINST 819 SET_VREG(r0, r9) @ vAA<- r0 820 GOTO_OPCODE(ip) @ jump to next instruction 821 822/* ------------------------------ */ 823 .balign 64 824.L_OP_CONST_CLASS: /* 0x1c */ 825/* File: armv5te/OP_CONST_CLASS.S */ 826 /* const/class vAA, Class@BBBB */ 827 FETCH(r1, 1) @ r1<- BBBB 828 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 829 mov r9, rINST, lsr #8 @ r9<- AA 830 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 831 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 832 cmp r0, #0 @ not yet resolved? 833 beq .LOP_CONST_CLASS_resolve 834 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 835 GET_INST_OPCODE(ip) @ extract opcode from rINST 836 SET_VREG(r0, r9) @ vAA<- r0 837 GOTO_OPCODE(ip) @ jump to next instruction 838 839/* ------------------------------ */ 840 .balign 64 841.L_OP_MONITOR_ENTER: /* 0x1d */ 842/* File: armv5te/OP_MONITOR_ENTER.S */ 843 /* 844 * Synchronize on an object. 845 */ 846 /* monitor-enter vAA */ 847 mov r2, rINST, lsr #8 @ r2<- AA 848 GET_VREG(r1, r2) @ r1<- vAA (object) 849 mov r0, rSELF @ r0<- self 850 cmp r1, #0 @ null object? 851 EXPORT_PC() @ need for precise GC 852 beq common_errNullObject @ null object, throw an exception 853 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 854 bl dvmLockObject @ call(self, obj) 855 GET_INST_OPCODE(ip) @ extract opcode from rINST 856 GOTO_OPCODE(ip) @ jump to next instruction 857 858/* ------------------------------ */ 859 .balign 64 860.L_OP_MONITOR_EXIT: /* 0x1e */ 861/* File: armv5te/OP_MONITOR_EXIT.S */ 862 /* 863 * Unlock an object. 864 * 865 * Exceptions that occur when unlocking a monitor need to appear as 866 * if they happened at the following instruction. See the Dalvik 867 * instruction spec. 868 */ 869 /* monitor-exit vAA */ 870 mov r2, rINST, lsr #8 @ r2<- AA 871 EXPORT_PC() @ before fetch: export the PC 872 GET_VREG(r1, r2) @ r1<- vAA (object) 873 cmp r1, #0 @ null object? 874 beq 1f @ yes 875 mov r0, rSELF @ r0<- self 876 bl dvmUnlockObject @ r0<- success for unlock(self, obj) 877 cmp r0, #0 @ failed? 878 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 879 beq common_exceptionThrown @ yes, exception is pending 880 GET_INST_OPCODE(ip) @ extract opcode from rINST 881 GOTO_OPCODE(ip) @ jump to next instruction 8821: 883 FETCH_ADVANCE_INST(1) @ advance before throw 884 b common_errNullObject 885 886/* ------------------------------ */ 887 .balign 64 888.L_OP_CHECK_CAST: /* 0x1f */ 889/* File: armv5te/OP_CHECK_CAST.S */ 890 /* 891 * Check to see if a cast from one class to another is allowed. 892 */ 893 /* check-cast vAA, class@BBBB */ 894 mov r3, rINST, lsr #8 @ r3<- AA 895 FETCH(r2, 1) @ r2<- BBBB 896 GET_VREG(r9, r3) @ r9<- object 897 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 898 cmp r9, #0 @ is object null? 899 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 900 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 901 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 902 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 903 cmp r1, #0 @ have we resolved this before? 904 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 905.LOP_CHECK_CAST_resolved: 906 cmp r0, r1 @ same class (trivial success)? 907 bne .LOP_CHECK_CAST_fullcheck @ no, do full check 908.LOP_CHECK_CAST_okay: 909 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 910 GET_INST_OPCODE(ip) @ extract opcode from rINST 911 GOTO_OPCODE(ip) @ jump to next instruction 912 913/* ------------------------------ */ 914 .balign 64 915.L_OP_INSTANCE_OF: /* 0x20 */ 916/* File: armv5te/OP_INSTANCE_OF.S */ 917 /* 918 * Check to see if an object reference is an instance of a class. 919 * 920 * Most common situation is a non-null object, being compared against 921 * an already-resolved class. 922 */ 923 /* instance-of vA, vB, class@CCCC */ 924 mov r3, rINST, lsr #12 @ r3<- B 925 mov r9, rINST, lsr #8 @ r9<- A+ 926 GET_VREG(r0, r3) @ r0<- vB (object) 927 and r9, r9, #15 @ r9<- A 928 cmp r0, #0 @ is object null? 929 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 930 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 931 FETCH(r3, 1) @ r3<- CCCC 932 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 933 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 934 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 935 cmp r1, #0 @ have we resolved this before? 936 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 937.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 938 cmp r0, r1 @ same class (trivial success)? 939 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 940 b .LOP_INSTANCE_OF_fullcheck @ no, do full check 941 942/* ------------------------------ */ 943 .balign 64 944.L_OP_ARRAY_LENGTH: /* 0x21 */ 945/* File: armv5te/OP_ARRAY_LENGTH.S */ 946 /* 947 * Return the length of an array. 948 */ 949 mov r1, rINST, lsr #12 @ r1<- B 950 mov r2, rINST, lsr #8 @ r2<- A+ 951 GET_VREG(r0, r1) @ r0<- vB (object ref) 952 and r2, r2, #15 @ r2<- A 953 cmp r0, #0 @ is object null? 954 beq common_errNullObject @ yup, fail 955 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 956 ldr r3, [r0, #offArrayObject_length] @ r3<- array length 957 GET_INST_OPCODE(ip) @ extract opcode from rINST 958 SET_VREG(r3, r2) @ vB<- length 959 GOTO_OPCODE(ip) @ jump to next instruction 960 961/* ------------------------------ */ 962 .balign 64 963.L_OP_NEW_INSTANCE: /* 0x22 */ 964/* File: armv5te/OP_NEW_INSTANCE.S */ 965 /* 966 * Create a new instance of a class. 967 */ 968 /* new-instance vAA, class@BBBB */ 969 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 970 FETCH(r1, 1) @ r1<- BBBB 971 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 972 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 973 EXPORT_PC() @ req'd for init, resolve, alloc 974 cmp r0, #0 @ already resolved? 975 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 976.LOP_NEW_INSTANCE_resolved: @ r0=class 977 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 978 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 979 bne .LOP_NEW_INSTANCE_needinit @ no, init class now 980.LOP_NEW_INSTANCE_initialized: @ r0=class 981 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 982 bl dvmAllocObject @ r0<- new object 983 b .LOP_NEW_INSTANCE_finish @ continue 984 985/* ------------------------------ */ 986 .balign 64 987.L_OP_NEW_ARRAY: /* 0x23 */ 988/* File: armv5te/OP_NEW_ARRAY.S */ 989 /* 990 * Allocate an array of objects, specified with the array class 991 * and a count. 992 * 993 * The verifier guarantees that this is an array class, so we don't 994 * check for it here. 995 */ 996 /* new-array vA, vB, class@CCCC */ 997 mov r0, rINST, lsr #12 @ r0<- B 998 FETCH(r2, 1) @ r2<- CCCC 999 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1000 GET_VREG(r1, r0) @ r1<- vB (array length) 1001 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1002 cmp r1, #0 @ check length 1003 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1004 bmi common_errNegativeArraySize @ negative length, bail - len in r1 1005 cmp r0, #0 @ already resolved? 1006 EXPORT_PC() @ req'd for resolve, alloc 1007 bne .LOP_NEW_ARRAY_finish @ resolved, continue 1008 b .LOP_NEW_ARRAY_resolve @ do resolve now 1009 1010/* ------------------------------ */ 1011 .balign 64 1012.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1013/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1014 /* 1015 * Create a new array with elements filled from registers. 1016 * 1017 * for: filled-new-array, filled-new-array/range 1018 */ 1019 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1020 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1021 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1022 FETCH(r1, 1) @ r1<- BBBB 1023 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1024 EXPORT_PC() @ need for resolve and alloc 1025 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1026 mov r10, rINST, lsr #8 @ r10<- AA or BA 1027 cmp r0, #0 @ already resolved? 1028 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 10298: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1030 mov r2, #0 @ r2<- false 1031 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1032 bl dvmResolveClass @ r0<- call(clazz, ref) 1033 cmp r0, #0 @ got null? 1034 beq common_exceptionThrown @ yes, handle exception 1035 b .LOP_FILLED_NEW_ARRAY_continue 1036 1037/* ------------------------------ */ 1038 .balign 64 1039.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1040/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1041/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1042 /* 1043 * Create a new array with elements filled from registers. 1044 * 1045 * for: filled-new-array, filled-new-array/range 1046 */ 1047 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1048 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1049 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1050 FETCH(r1, 1) @ r1<- BBBB 1051 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1052 EXPORT_PC() @ need for resolve and alloc 1053 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1054 mov r10, rINST, lsr #8 @ r10<- AA or BA 1055 cmp r0, #0 @ already resolved? 1056 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 10578: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1058 mov r2, #0 @ r2<- false 1059 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1060 bl dvmResolveClass @ r0<- call(clazz, ref) 1061 cmp r0, #0 @ got null? 1062 beq common_exceptionThrown @ yes, handle exception 1063 b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1064 1065 1066/* ------------------------------ */ 1067 .balign 64 1068.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1069/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1070 /* fill-array-data vAA, +BBBBBBBB */ 1071 FETCH(r0, 1) @ r0<- bbbb (lo) 1072 FETCH(r1, 2) @ r1<- BBBB (hi) 1073 mov r3, rINST, lsr #8 @ r3<- AA 1074 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1075 GET_VREG(r0, r3) @ r0<- vAA (array object) 1076 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1077 EXPORT_PC(); 1078 bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1079 cmp r0, #0 @ 0 means an exception is thrown 1080 beq common_exceptionThrown @ has exception 1081 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1082 GET_INST_OPCODE(ip) @ extract opcode from rINST 1083 GOTO_OPCODE(ip) @ jump to next instruction 1084 1085/* ------------------------------ */ 1086 .balign 64 1087.L_OP_THROW: /* 0x27 */ 1088/* File: armv5te/OP_THROW.S */ 1089 /* 1090 * Throw an exception object in the current thread. 1091 */ 1092 /* throw vAA */ 1093 mov r2, rINST, lsr #8 @ r2<- AA 1094 GET_VREG(r1, r2) @ r1<- vAA (exception object) 1095 EXPORT_PC() @ exception handler can throw 1096 cmp r1, #0 @ null object? 1097 beq common_errNullObject @ yes, throw an NPE instead 1098 @ bypass dvmSetException, just store it 1099 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj 1100 b common_exceptionThrown 1101 1102/* ------------------------------ */ 1103 .balign 64 1104.L_OP_GOTO: /* 0x28 */ 1105/* File: armv5te/OP_GOTO.S */ 1106 /* 1107 * Unconditional branch, 8-bit offset. 1108 * 1109 * The branch distance is a signed code-unit offset, which we need to 1110 * double to get a byte offset. 1111 */ 1112 /* goto +AA */ 1113 mov r0, rINST, lsl #16 @ r0<- AAxx0000 1114 movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1115 mov r9, r9, lsl #1 @ r9<- byte offset 1116 bmi common_backwardBranch @ backward branch, do periodic checks 1117#if defined(WITH_JIT) 1118 GET_JIT_PROF_TABLE(r0) 1119 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1120 cmp r0,#0 1121 bne common_updateProfile 1122 GET_INST_OPCODE(ip) @ extract opcode from rINST 1123 GOTO_OPCODE(ip) @ jump to next instruction 1124#else 1125 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1126 GET_INST_OPCODE(ip) @ extract opcode from rINST 1127 GOTO_OPCODE(ip) @ jump to next instruction 1128#endif 1129 1130/* ------------------------------ */ 1131 .balign 64 1132.L_OP_GOTO_16: /* 0x29 */ 1133/* File: armv5te/OP_GOTO_16.S */ 1134 /* 1135 * Unconditional branch, 16-bit offset. 1136 * 1137 * The branch distance is a signed code-unit offset, which we need to 1138 * double to get a byte offset. 1139 */ 1140 /* goto/16 +AAAA */ 1141 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1142 movs r9, r0, asl #1 @ r9<- byte offset, check sign 1143 bmi common_backwardBranch @ backward branch, do periodic checks 1144#if defined(WITH_JIT) 1145 GET_JIT_PROF_TABLE(r0) 1146 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1147 cmp r0,#0 1148 bne common_updateProfile 1149 GET_INST_OPCODE(ip) @ extract opcode from rINST 1150 GOTO_OPCODE(ip) @ jump to next instruction 1151#else 1152 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1153 GET_INST_OPCODE(ip) @ extract opcode from rINST 1154 GOTO_OPCODE(ip) @ jump to next instruction 1155#endif 1156 1157/* ------------------------------ */ 1158 .balign 64 1159.L_OP_GOTO_32: /* 0x2a */ 1160/* File: armv5te/OP_GOTO_32.S */ 1161 /* 1162 * Unconditional branch, 32-bit offset. 1163 * 1164 * The branch distance is a signed code-unit offset, which we need to 1165 * double to get a byte offset. 1166 * 1167 * Unlike most opcodes, this one is allowed to branch to itself, so 1168 * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1169 * instruction doesn't affect the V flag, so we need to clear it 1170 * explicitly. 1171 */ 1172 /* goto/32 +AAAAAAAA */ 1173 FETCH(r0, 1) @ r0<- aaaa (lo) 1174 FETCH(r1, 2) @ r1<- AAAA (hi) 1175 cmp ip, ip @ (clear V flag during stall) 1176 orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1177 mov r9, r0, asl #1 @ r9<- byte offset 1178 ble common_backwardBranch @ backward branch, do periodic checks 1179#if defined(WITH_JIT) 1180 GET_JIT_PROF_TABLE(r0) 1181 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1182 cmp r0,#0 1183 bne common_updateProfile 1184 GET_INST_OPCODE(ip) @ extract opcode from rINST 1185 GOTO_OPCODE(ip) @ jump to next instruction 1186#else 1187 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1188 GET_INST_OPCODE(ip) @ extract opcode from rINST 1189 GOTO_OPCODE(ip) @ jump to next instruction 1190#endif 1191 1192/* ------------------------------ */ 1193 .balign 64 1194.L_OP_PACKED_SWITCH: /* 0x2b */ 1195/* File: armv5te/OP_PACKED_SWITCH.S */ 1196 /* 1197 * Handle a packed-switch or sparse-switch instruction. In both cases 1198 * we decode it and hand it off to a helper function. 1199 * 1200 * We don't really expect backward branches in a switch statement, but 1201 * they're perfectly legal, so we check for them here. 1202 * 1203 * for: packed-switch, sparse-switch 1204 */ 1205 /* op vAA, +BBBB */ 1206 FETCH(r0, 1) @ r0<- bbbb (lo) 1207 FETCH(r1, 2) @ r1<- BBBB (hi) 1208 mov r3, rINST, lsr #8 @ r3<- AA 1209 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1210 GET_VREG(r1, r3) @ r1<- vAA 1211 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1212 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1213 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1214 bmi common_backwardBranch @ backward branch, do periodic checks 1215 beq common_backwardBranch @ (want to use BLE but V is unknown) 1216#if defined(WITH_JIT) 1217 GET_JIT_PROF_TABLE(r0) 1218 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1219 cmp r0,#0 1220 bne common_updateProfile 1221 GET_INST_OPCODE(ip) @ extract opcode from rINST 1222 GOTO_OPCODE(ip) @ jump to next instruction 1223#else 1224 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1225 GET_INST_OPCODE(ip) @ extract opcode from rINST 1226 GOTO_OPCODE(ip) @ jump to next instruction 1227#endif 1228 1229/* ------------------------------ */ 1230 .balign 64 1231.L_OP_SPARSE_SWITCH: /* 0x2c */ 1232/* File: armv5te/OP_SPARSE_SWITCH.S */ 1233/* File: armv5te/OP_PACKED_SWITCH.S */ 1234 /* 1235 * Handle a packed-switch or sparse-switch instruction. In both cases 1236 * we decode it and hand it off to a helper function. 1237 * 1238 * We don't really expect backward branches in a switch statement, but 1239 * they're perfectly legal, so we check for them here. 1240 * 1241 * for: packed-switch, sparse-switch 1242 */ 1243 /* op vAA, +BBBB */ 1244 FETCH(r0, 1) @ r0<- bbbb (lo) 1245 FETCH(r1, 2) @ r1<- BBBB (hi) 1246 mov r3, rINST, lsr #8 @ r3<- AA 1247 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1248 GET_VREG(r1, r3) @ r1<- vAA 1249 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1250 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1251 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1252 bmi common_backwardBranch @ backward branch, do periodic checks 1253 beq common_backwardBranch @ (want to use BLE but V is unknown) 1254#if defined(WITH_JIT) 1255 GET_JIT_PROF_TABLE(r0) 1256 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1257 cmp r0,#0 1258 bne common_updateProfile 1259 GET_INST_OPCODE(ip) @ extract opcode from rINST 1260 GOTO_OPCODE(ip) @ jump to next instruction 1261#else 1262 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1263 GET_INST_OPCODE(ip) @ extract opcode from rINST 1264 GOTO_OPCODE(ip) @ jump to next instruction 1265#endif 1266 1267 1268/* ------------------------------ */ 1269 .balign 64 1270.L_OP_CMPL_FLOAT: /* 0x2d */ 1271/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1272 /* 1273 * Compare two floating-point values. Puts 0, 1, or -1 into the 1274 * destination register based on the results of the comparison. 1275 * 1276 * int compare(x, y) { 1277 * if (x == y) { 1278 * return 0; 1279 * } else if (x > y) { 1280 * return 1; 1281 * } else if (x < y) { 1282 * return -1; 1283 * } else { 1284 * return -1; 1285 * } 1286 * } 1287 */ 1288 /* op vAA, vBB, vCC */ 1289 FETCH(r0, 1) @ r0<- CCBB 1290 mov r9, rINST, lsr #8 @ r9<- AA 1291 and r2, r0, #255 @ r2<- BB 1292 mov r3, r0, lsr #8 @ r3<- CC 1293 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1294 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1295 flds s0, [r2] @ s0<- vBB 1296 flds s1, [r3] @ s1<- vCC 1297 fcmpes s0, s1 @ compare (vBB, vCC) 1298 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1299 mvn r0, #0 @ r0<- -1 (default) 1300 GET_INST_OPCODE(ip) @ extract opcode from rINST 1301 fmstat @ export status flags 1302 movgt r0, #1 @ (greater than) r1<- 1 1303 moveq r0, #0 @ (equal) r1<- 0 1304 b .LOP_CMPL_FLOAT_finish @ argh 1305 1306 1307/* ------------------------------ */ 1308 .balign 64 1309.L_OP_CMPG_FLOAT: /* 0x2e */ 1310/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1311 /* 1312 * Compare two floating-point values. Puts 0, 1, or -1 into the 1313 * destination register based on the results of the comparison. 1314 * 1315 * int compare(x, y) { 1316 * if (x == y) { 1317 * return 0; 1318 * } else if (x < y) { 1319 * return -1; 1320 * } else if (x > y) { 1321 * return 1; 1322 * } else { 1323 * return 1; 1324 * } 1325 * } 1326 */ 1327 /* op vAA, vBB, vCC */ 1328 FETCH(r0, 1) @ r0<- CCBB 1329 mov r9, rINST, lsr #8 @ r9<- AA 1330 and r2, r0, #255 @ r2<- BB 1331 mov r3, r0, lsr #8 @ r3<- CC 1332 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1333 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1334 flds s0, [r2] @ s0<- vBB 1335 flds s1, [r3] @ s1<- vCC 1336 fcmpes s0, s1 @ compare (vBB, vCC) 1337 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1338 mov r0, #1 @ r0<- 1 (default) 1339 GET_INST_OPCODE(ip) @ extract opcode from rINST 1340 fmstat @ export status flags 1341 mvnmi r0, #0 @ (less than) r1<- -1 1342 moveq r0, #0 @ (equal) r1<- 0 1343 b .LOP_CMPG_FLOAT_finish @ argh 1344 1345 1346/* ------------------------------ */ 1347 .balign 64 1348.L_OP_CMPL_DOUBLE: /* 0x2f */ 1349/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1350 /* 1351 * Compare two floating-point values. Puts 0, 1, or -1 into the 1352 * destination register based on the results of the comparison. 1353 * 1354 * int compare(x, y) { 1355 * if (x == y) { 1356 * return 0; 1357 * } else if (x > y) { 1358 * return 1; 1359 * } else if (x < y) { 1360 * return -1; 1361 * } else { 1362 * return -1; 1363 * } 1364 * } 1365 */ 1366 /* op vAA, vBB, vCC */ 1367 FETCH(r0, 1) @ r0<- CCBB 1368 mov r9, rINST, lsr #8 @ r9<- AA 1369 and r2, r0, #255 @ r2<- BB 1370 mov r3, r0, lsr #8 @ r3<- CC 1371 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1372 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1373 fldd d0, [r2] @ d0<- vBB 1374 fldd d1, [r3] @ d1<- vCC 1375 fcmped d0, d1 @ compare (vBB, vCC) 1376 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1377 mvn r0, #0 @ r0<- -1 (default) 1378 GET_INST_OPCODE(ip) @ extract opcode from rINST 1379 fmstat @ export status flags 1380 movgt r0, #1 @ (greater than) r1<- 1 1381 moveq r0, #0 @ (equal) r1<- 0 1382 b .LOP_CMPL_DOUBLE_finish @ argh 1383 1384 1385/* ------------------------------ */ 1386 .balign 64 1387.L_OP_CMPG_DOUBLE: /* 0x30 */ 1388/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1389 /* 1390 * Compare two floating-point values. Puts 0, 1, or -1 into the 1391 * destination register based on the results of the comparison. 1392 * 1393 * int compare(x, y) { 1394 * if (x == y) { 1395 * return 0; 1396 * } else if (x < y) { 1397 * return -1; 1398 * } else if (x > y) { 1399 * return 1; 1400 * } else { 1401 * return 1; 1402 * } 1403 * } 1404 */ 1405 /* op vAA, vBB, vCC */ 1406 FETCH(r0, 1) @ r0<- CCBB 1407 mov r9, rINST, lsr #8 @ r9<- AA 1408 and r2, r0, #255 @ r2<- BB 1409 mov r3, r0, lsr #8 @ r3<- CC 1410 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1411 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1412 fldd d0, [r2] @ d0<- vBB 1413 fldd d1, [r3] @ d1<- vCC 1414 fcmped d0, d1 @ compare (vBB, vCC) 1415 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1416 mov r0, #1 @ r0<- 1 (default) 1417 GET_INST_OPCODE(ip) @ extract opcode from rINST 1418 fmstat @ export status flags 1419 mvnmi r0, #0 @ (less than) r1<- -1 1420 moveq r0, #0 @ (equal) r1<- 0 1421 b .LOP_CMPG_DOUBLE_finish @ argh 1422 1423 1424/* ------------------------------ */ 1425 .balign 64 1426.L_OP_CMP_LONG: /* 0x31 */ 1427/* File: armv5te/OP_CMP_LONG.S */ 1428 /* 1429 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1430 * register based on the results of the comparison. 1431 * 1432 * We load the full values with LDM, but in practice many values could 1433 * be resolved by only looking at the high word. This could be made 1434 * faster or slower by splitting the LDM into a pair of LDRs. 1435 * 1436 * If we just wanted to set condition flags, we could do this: 1437 * subs ip, r0, r2 1438 * sbcs ip, r1, r3 1439 * subeqs ip, r0, r2 1440 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1441 * integer value, which we can do with 2 conditional mov/mvn instructions 1442 * (set 1, set -1; if they're equal we already have 0 in ip), giving 1443 * us a constant 5-cycle path plus a branch at the end to the 1444 * instruction epilogue code. The multi-compare approach below needs 1445 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1446 * in the worst case (the 64-bit values are equal). 1447 */ 1448 /* cmp-long vAA, vBB, vCC */ 1449 FETCH(r0, 1) @ r0<- CCBB 1450 mov r9, rINST, lsr #8 @ r9<- AA 1451 and r2, r0, #255 @ r2<- BB 1452 mov r3, r0, lsr #8 @ r3<- CC 1453 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1454 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1455 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1456 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1457 cmp r1, r3 @ compare (vBB+1, vCC+1) 1458 blt .LOP_CMP_LONG_less @ signed compare on high part 1459 bgt .LOP_CMP_LONG_greater 1460 subs r1, r0, r2 @ r1<- r0 - r2 1461 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1462 bne .LOP_CMP_LONG_less 1463 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1464 1465/* ------------------------------ */ 1466 .balign 64 1467.L_OP_IF_EQ: /* 0x32 */ 1468/* File: armv5te/OP_IF_EQ.S */ 1469/* File: armv5te/bincmp.S */ 1470 /* 1471 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1472 * fragment that specifies the *reverse* comparison to perform, e.g. 1473 * for "if-le" you would use "gt". 1474 * 1475 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1476 */ 1477 /* if-cmp vA, vB, +CCCC */ 1478 mov r0, rINST, lsr #8 @ r0<- A+ 1479 mov r1, rINST, lsr #12 @ r1<- B 1480 and r0, r0, #15 1481 GET_VREG(r3, r1) @ r3<- vB 1482 GET_VREG(r2, r0) @ r2<- vA 1483 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1484 cmp r2, r3 @ compare (vA, vB) 1485 bne 1f @ branch to 1 if comparison failed 1486 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1487 movs r9, r9, asl #1 @ convert to bytes, check sign 1488 bmi common_backwardBranch @ yes, do periodic checks 14891: 1490#if defined(WITH_JIT) 1491 GET_JIT_PROF_TABLE(r0) 1492 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1493 b common_testUpdateProfile 1494#else 1495 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1496 GET_INST_OPCODE(ip) @ extract opcode from rINST 1497 GOTO_OPCODE(ip) @ jump to next instruction 1498#endif 1499 1500 1501/* ------------------------------ */ 1502 .balign 64 1503.L_OP_IF_NE: /* 0x33 */ 1504/* File: armv5te/OP_IF_NE.S */ 1505/* File: armv5te/bincmp.S */ 1506 /* 1507 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1508 * fragment that specifies the *reverse* comparison to perform, e.g. 1509 * for "if-le" you would use "gt". 1510 * 1511 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1512 */ 1513 /* if-cmp vA, vB, +CCCC */ 1514 mov r0, rINST, lsr #8 @ r0<- A+ 1515 mov r1, rINST, lsr #12 @ r1<- B 1516 and r0, r0, #15 1517 GET_VREG(r3, r1) @ r3<- vB 1518 GET_VREG(r2, r0) @ r2<- vA 1519 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1520 cmp r2, r3 @ compare (vA, vB) 1521 beq 1f @ branch to 1 if comparison failed 1522 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1523 movs r9, r9, asl #1 @ convert to bytes, check sign 1524 bmi common_backwardBranch @ yes, do periodic checks 15251: 1526#if defined(WITH_JIT) 1527 GET_JIT_PROF_TABLE(r0) 1528 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1529 b common_testUpdateProfile 1530#else 1531 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1532 GET_INST_OPCODE(ip) @ extract opcode from rINST 1533 GOTO_OPCODE(ip) @ jump to next instruction 1534#endif 1535 1536 1537/* ------------------------------ */ 1538 .balign 64 1539.L_OP_IF_LT: /* 0x34 */ 1540/* File: armv5te/OP_IF_LT.S */ 1541/* File: armv5te/bincmp.S */ 1542 /* 1543 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1544 * fragment that specifies the *reverse* comparison to perform, e.g. 1545 * for "if-le" you would use "gt". 1546 * 1547 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1548 */ 1549 /* if-cmp vA, vB, +CCCC */ 1550 mov r0, rINST, lsr #8 @ r0<- A+ 1551 mov r1, rINST, lsr #12 @ r1<- B 1552 and r0, r0, #15 1553 GET_VREG(r3, r1) @ r3<- vB 1554 GET_VREG(r2, r0) @ r2<- vA 1555 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1556 cmp r2, r3 @ compare (vA, vB) 1557 bge 1f @ branch to 1 if comparison failed 1558 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1559 movs r9, r9, asl #1 @ convert to bytes, check sign 1560 bmi common_backwardBranch @ yes, do periodic checks 15611: 1562#if defined(WITH_JIT) 1563 GET_JIT_PROF_TABLE(r0) 1564 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1565 b common_testUpdateProfile 1566#else 1567 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1568 GET_INST_OPCODE(ip) @ extract opcode from rINST 1569 GOTO_OPCODE(ip) @ jump to next instruction 1570#endif 1571 1572 1573/* ------------------------------ */ 1574 .balign 64 1575.L_OP_IF_GE: /* 0x35 */ 1576/* File: armv5te/OP_IF_GE.S */ 1577/* File: armv5te/bincmp.S */ 1578 /* 1579 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1580 * fragment that specifies the *reverse* comparison to perform, e.g. 1581 * for "if-le" you would use "gt". 1582 * 1583 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1584 */ 1585 /* if-cmp vA, vB, +CCCC */ 1586 mov r0, rINST, lsr #8 @ r0<- A+ 1587 mov r1, rINST, lsr #12 @ r1<- B 1588 and r0, r0, #15 1589 GET_VREG(r3, r1) @ r3<- vB 1590 GET_VREG(r2, r0) @ r2<- vA 1591 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1592 cmp r2, r3 @ compare (vA, vB) 1593 blt 1f @ branch to 1 if comparison failed 1594 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1595 movs r9, r9, asl #1 @ convert to bytes, check sign 1596 bmi common_backwardBranch @ yes, do periodic checks 15971: 1598#if defined(WITH_JIT) 1599 GET_JIT_PROF_TABLE(r0) 1600 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1601 b common_testUpdateProfile 1602#else 1603 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1604 GET_INST_OPCODE(ip) @ extract opcode from rINST 1605 GOTO_OPCODE(ip) @ jump to next instruction 1606#endif 1607 1608 1609/* ------------------------------ */ 1610 .balign 64 1611.L_OP_IF_GT: /* 0x36 */ 1612/* File: armv5te/OP_IF_GT.S */ 1613/* File: armv5te/bincmp.S */ 1614 /* 1615 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1616 * fragment that specifies the *reverse* comparison to perform, e.g. 1617 * for "if-le" you would use "gt". 1618 * 1619 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1620 */ 1621 /* if-cmp vA, vB, +CCCC */ 1622 mov r0, rINST, lsr #8 @ r0<- A+ 1623 mov r1, rINST, lsr #12 @ r1<- B 1624 and r0, r0, #15 1625 GET_VREG(r3, r1) @ r3<- vB 1626 GET_VREG(r2, r0) @ r2<- vA 1627 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1628 cmp r2, r3 @ compare (vA, vB) 1629 ble 1f @ branch to 1 if comparison failed 1630 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1631 movs r9, r9, asl #1 @ convert to bytes, check sign 1632 bmi common_backwardBranch @ yes, do periodic checks 16331: 1634#if defined(WITH_JIT) 1635 GET_JIT_PROF_TABLE(r0) 1636 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1637 b common_testUpdateProfile 1638#else 1639 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1640 GET_INST_OPCODE(ip) @ extract opcode from rINST 1641 GOTO_OPCODE(ip) @ jump to next instruction 1642#endif 1643 1644 1645/* ------------------------------ */ 1646 .balign 64 1647.L_OP_IF_LE: /* 0x37 */ 1648/* File: armv5te/OP_IF_LE.S */ 1649/* File: armv5te/bincmp.S */ 1650 /* 1651 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1652 * fragment that specifies the *reverse* comparison to perform, e.g. 1653 * for "if-le" you would use "gt". 1654 * 1655 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1656 */ 1657 /* if-cmp vA, vB, +CCCC */ 1658 mov r0, rINST, lsr #8 @ r0<- A+ 1659 mov r1, rINST, lsr #12 @ r1<- B 1660 and r0, r0, #15 1661 GET_VREG(r3, r1) @ r3<- vB 1662 GET_VREG(r2, r0) @ r2<- vA 1663 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1664 cmp r2, r3 @ compare (vA, vB) 1665 bgt 1f @ branch to 1 if comparison failed 1666 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1667 movs r9, r9, asl #1 @ convert to bytes, check sign 1668 bmi common_backwardBranch @ yes, do periodic checks 16691: 1670#if defined(WITH_JIT) 1671 GET_JIT_PROF_TABLE(r0) 1672 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1673 b common_testUpdateProfile 1674#else 1675 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1676 GET_INST_OPCODE(ip) @ extract opcode from rINST 1677 GOTO_OPCODE(ip) @ jump to next instruction 1678#endif 1679 1680 1681/* ------------------------------ */ 1682 .balign 64 1683.L_OP_IF_EQZ: /* 0x38 */ 1684/* File: armv5te/OP_IF_EQZ.S */ 1685/* File: armv5te/zcmp.S */ 1686 /* 1687 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1688 * fragment that specifies the *reverse* comparison to perform, e.g. 1689 * for "if-le" you would use "gt". 1690 * 1691 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1692 */ 1693 /* if-cmp vAA, +BBBB */ 1694 mov r0, rINST, lsr #8 @ r0<- AA 1695 GET_VREG(r2, r0) @ r2<- vAA 1696 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1697 cmp r2, #0 @ compare (vA, 0) 1698 bne 1f @ branch to 1 if comparison failed 1699 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1700 movs r9, r9, asl #1 @ convert to bytes, check sign 1701 bmi common_backwardBranch @ backward branch, do periodic checks 17021: 1703#if defined(WITH_JIT) 1704 GET_JIT_PROF_TABLE(r0) 1705 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1706 cmp r0,#0 1707 bne common_updateProfile 1708 GET_INST_OPCODE(ip) @ extract opcode from rINST 1709 GOTO_OPCODE(ip) @ jump to next instruction 1710#else 1711 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1712 GET_INST_OPCODE(ip) @ extract opcode from rINST 1713 GOTO_OPCODE(ip) @ jump to next instruction 1714#endif 1715 1716 1717/* ------------------------------ */ 1718 .balign 64 1719.L_OP_IF_NEZ: /* 0x39 */ 1720/* File: armv5te/OP_IF_NEZ.S */ 1721/* File: armv5te/zcmp.S */ 1722 /* 1723 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1724 * fragment that specifies the *reverse* comparison to perform, e.g. 1725 * for "if-le" you would use "gt". 1726 * 1727 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1728 */ 1729 /* if-cmp vAA, +BBBB */ 1730 mov r0, rINST, lsr #8 @ r0<- AA 1731 GET_VREG(r2, r0) @ r2<- vAA 1732 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1733 cmp r2, #0 @ compare (vA, 0) 1734 beq 1f @ branch to 1 if comparison failed 1735 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1736 movs r9, r9, asl #1 @ convert to bytes, check sign 1737 bmi common_backwardBranch @ backward branch, do periodic checks 17381: 1739#if defined(WITH_JIT) 1740 GET_JIT_PROF_TABLE(r0) 1741 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1742 cmp r0,#0 1743 bne common_updateProfile 1744 GET_INST_OPCODE(ip) @ extract opcode from rINST 1745 GOTO_OPCODE(ip) @ jump to next instruction 1746#else 1747 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1748 GET_INST_OPCODE(ip) @ extract opcode from rINST 1749 GOTO_OPCODE(ip) @ jump to next instruction 1750#endif 1751 1752 1753/* ------------------------------ */ 1754 .balign 64 1755.L_OP_IF_LTZ: /* 0x3a */ 1756/* File: armv5te/OP_IF_LTZ.S */ 1757/* File: armv5te/zcmp.S */ 1758 /* 1759 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1760 * fragment that specifies the *reverse* comparison to perform, e.g. 1761 * for "if-le" you would use "gt". 1762 * 1763 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1764 */ 1765 /* if-cmp vAA, +BBBB */ 1766 mov r0, rINST, lsr #8 @ r0<- AA 1767 GET_VREG(r2, r0) @ r2<- vAA 1768 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1769 cmp r2, #0 @ compare (vA, 0) 1770 bge 1f @ branch to 1 if comparison failed 1771 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1772 movs r9, r9, asl #1 @ convert to bytes, check sign 1773 bmi common_backwardBranch @ backward branch, do periodic checks 17741: 1775#if defined(WITH_JIT) 1776 GET_JIT_PROF_TABLE(r0) 1777 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1778 cmp r0,#0 1779 bne common_updateProfile 1780 GET_INST_OPCODE(ip) @ extract opcode from rINST 1781 GOTO_OPCODE(ip) @ jump to next instruction 1782#else 1783 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1784 GET_INST_OPCODE(ip) @ extract opcode from rINST 1785 GOTO_OPCODE(ip) @ jump to next instruction 1786#endif 1787 1788 1789/* ------------------------------ */ 1790 .balign 64 1791.L_OP_IF_GEZ: /* 0x3b */ 1792/* File: armv5te/OP_IF_GEZ.S */ 1793/* File: armv5te/zcmp.S */ 1794 /* 1795 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1796 * fragment that specifies the *reverse* comparison to perform, e.g. 1797 * for "if-le" you would use "gt". 1798 * 1799 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1800 */ 1801 /* if-cmp vAA, +BBBB */ 1802 mov r0, rINST, lsr #8 @ r0<- AA 1803 GET_VREG(r2, r0) @ r2<- vAA 1804 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1805 cmp r2, #0 @ compare (vA, 0) 1806 blt 1f @ branch to 1 if comparison failed 1807 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1808 movs r9, r9, asl #1 @ convert to bytes, check sign 1809 bmi common_backwardBranch @ backward branch, do periodic checks 18101: 1811#if defined(WITH_JIT) 1812 GET_JIT_PROF_TABLE(r0) 1813 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1814 cmp r0,#0 1815 bne common_updateProfile 1816 GET_INST_OPCODE(ip) @ extract opcode from rINST 1817 GOTO_OPCODE(ip) @ jump to next instruction 1818#else 1819 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1820 GET_INST_OPCODE(ip) @ extract opcode from rINST 1821 GOTO_OPCODE(ip) @ jump to next instruction 1822#endif 1823 1824 1825/* ------------------------------ */ 1826 .balign 64 1827.L_OP_IF_GTZ: /* 0x3c */ 1828/* File: armv5te/OP_IF_GTZ.S */ 1829/* File: armv5te/zcmp.S */ 1830 /* 1831 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1832 * fragment that specifies the *reverse* comparison to perform, e.g. 1833 * for "if-le" you would use "gt". 1834 * 1835 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1836 */ 1837 /* if-cmp vAA, +BBBB */ 1838 mov r0, rINST, lsr #8 @ r0<- AA 1839 GET_VREG(r2, r0) @ r2<- vAA 1840 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1841 cmp r2, #0 @ compare (vA, 0) 1842 ble 1f @ branch to 1 if comparison failed 1843 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1844 movs r9, r9, asl #1 @ convert to bytes, check sign 1845 bmi common_backwardBranch @ backward branch, do periodic checks 18461: 1847#if defined(WITH_JIT) 1848 GET_JIT_PROF_TABLE(r0) 1849 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1850 cmp r0,#0 1851 bne common_updateProfile 1852 GET_INST_OPCODE(ip) @ extract opcode from rINST 1853 GOTO_OPCODE(ip) @ jump to next instruction 1854#else 1855 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1856 GET_INST_OPCODE(ip) @ extract opcode from rINST 1857 GOTO_OPCODE(ip) @ jump to next instruction 1858#endif 1859 1860 1861/* ------------------------------ */ 1862 .balign 64 1863.L_OP_IF_LEZ: /* 0x3d */ 1864/* File: armv5te/OP_IF_LEZ.S */ 1865/* File: armv5te/zcmp.S */ 1866 /* 1867 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1868 * fragment that specifies the *reverse* comparison to perform, e.g. 1869 * for "if-le" you would use "gt". 1870 * 1871 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1872 */ 1873 /* if-cmp vAA, +BBBB */ 1874 mov r0, rINST, lsr #8 @ r0<- AA 1875 GET_VREG(r2, r0) @ r2<- vAA 1876 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1877 cmp r2, #0 @ compare (vA, 0) 1878 bgt 1f @ branch to 1 if comparison failed 1879 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1880 movs r9, r9, asl #1 @ convert to bytes, check sign 1881 bmi common_backwardBranch @ backward branch, do periodic checks 18821: 1883#if defined(WITH_JIT) 1884 GET_JIT_PROF_TABLE(r0) 1885 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1886 cmp r0,#0 1887 bne common_updateProfile 1888 GET_INST_OPCODE(ip) @ extract opcode from rINST 1889 GOTO_OPCODE(ip) @ jump to next instruction 1890#else 1891 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1892 GET_INST_OPCODE(ip) @ extract opcode from rINST 1893 GOTO_OPCODE(ip) @ jump to next instruction 1894#endif 1895 1896 1897/* ------------------------------ */ 1898 .balign 64 1899.L_OP_UNUSED_3E: /* 0x3e */ 1900/* File: armv5te/OP_UNUSED_3E.S */ 1901/* File: armv5te/unused.S */ 1902 bl common_abort 1903 1904 1905/* ------------------------------ */ 1906 .balign 64 1907.L_OP_UNUSED_3F: /* 0x3f */ 1908/* File: armv5te/OP_UNUSED_3F.S */ 1909/* File: armv5te/unused.S */ 1910 bl common_abort 1911 1912 1913/* ------------------------------ */ 1914 .balign 64 1915.L_OP_UNUSED_40: /* 0x40 */ 1916/* File: armv5te/OP_UNUSED_40.S */ 1917/* File: armv5te/unused.S */ 1918 bl common_abort 1919 1920 1921/* ------------------------------ */ 1922 .balign 64 1923.L_OP_UNUSED_41: /* 0x41 */ 1924/* File: armv5te/OP_UNUSED_41.S */ 1925/* File: armv5te/unused.S */ 1926 bl common_abort 1927 1928 1929/* ------------------------------ */ 1930 .balign 64 1931.L_OP_UNUSED_42: /* 0x42 */ 1932/* File: armv5te/OP_UNUSED_42.S */ 1933/* File: armv5te/unused.S */ 1934 bl common_abort 1935 1936 1937/* ------------------------------ */ 1938 .balign 64 1939.L_OP_UNUSED_43: /* 0x43 */ 1940/* File: armv5te/OP_UNUSED_43.S */ 1941/* File: armv5te/unused.S */ 1942 bl common_abort 1943 1944 1945/* ------------------------------ */ 1946 .balign 64 1947.L_OP_AGET: /* 0x44 */ 1948/* File: armv5te/OP_AGET.S */ 1949 /* 1950 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1951 * 1952 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1953 * instructions. We use a pair of FETCH_Bs instead. 1954 * 1955 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1956 */ 1957 /* op vAA, vBB, vCC */ 1958 FETCH_B(r2, 1, 0) @ r2<- BB 1959 mov r9, rINST, lsr #8 @ r9<- AA 1960 FETCH_B(r3, 1, 1) @ r3<- CC 1961 GET_VREG(r0, r2) @ r0<- vBB (array object) 1962 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1963 cmp r0, #0 @ null array object? 1964 beq common_errNullObject @ yes, bail 1965 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1966 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1967 cmp r1, r3 @ compare unsigned index, length 1968 bcs common_errArrayIndex @ index >= length, bail 1969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1970 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 1971 GET_INST_OPCODE(ip) @ extract opcode from rINST 1972 SET_VREG(r2, r9) @ vAA<- r2 1973 GOTO_OPCODE(ip) @ jump to next instruction 1974 1975/* ------------------------------ */ 1976 .balign 64 1977.L_OP_AGET_WIDE: /* 0x45 */ 1978/* File: armv5te/OP_AGET_WIDE.S */ 1979 /* 1980 * Array get, 64 bits. vAA <- vBB[vCC]. 1981 * 1982 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 1983 */ 1984 /* aget-wide vAA, vBB, vCC */ 1985 FETCH(r0, 1) @ r0<- CCBB 1986 mov r9, rINST, lsr #8 @ r9<- AA 1987 and r2, r0, #255 @ r2<- BB 1988 mov r3, r0, lsr #8 @ r3<- CC 1989 GET_VREG(r0, r2) @ r0<- vBB (array object) 1990 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1991 cmp r0, #0 @ null array object? 1992 beq common_errNullObject @ yes, bail 1993 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1994 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 1995 cmp r1, r3 @ compare unsigned index, length 1996 bcc .LOP_AGET_WIDE_finish @ okay, continue below 1997 b common_errArrayIndex @ index >= length, bail 1998 @ May want to swap the order of these two branches depending on how the 1999 @ branch prediction (if any) handles conditional forward branches vs. 2000 @ unconditional forward branches. 2001 2002/* ------------------------------ */ 2003 .balign 64 2004.L_OP_AGET_OBJECT: /* 0x46 */ 2005/* File: armv5te/OP_AGET_OBJECT.S */ 2006/* File: armv5te/OP_AGET.S */ 2007 /* 2008 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2009 * 2010 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2011 * instructions. We use a pair of FETCH_Bs instead. 2012 * 2013 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2014 */ 2015 /* op vAA, vBB, vCC */ 2016 FETCH_B(r2, 1, 0) @ r2<- BB 2017 mov r9, rINST, lsr #8 @ r9<- AA 2018 FETCH_B(r3, 1, 1) @ r3<- CC 2019 GET_VREG(r0, r2) @ r0<- vBB (array object) 2020 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2021 cmp r0, #0 @ null array object? 2022 beq common_errNullObject @ yes, bail 2023 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2024 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2025 cmp r1, r3 @ compare unsigned index, length 2026 bcs common_errArrayIndex @ index >= length, bail 2027 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2028 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2029 GET_INST_OPCODE(ip) @ extract opcode from rINST 2030 SET_VREG(r2, r9) @ vAA<- r2 2031 GOTO_OPCODE(ip) @ jump to next instruction 2032 2033 2034/* ------------------------------ */ 2035 .balign 64 2036.L_OP_AGET_BOOLEAN: /* 0x47 */ 2037/* File: armv5te/OP_AGET_BOOLEAN.S */ 2038/* File: armv5te/OP_AGET.S */ 2039 /* 2040 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2041 * 2042 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2043 * instructions. We use a pair of FETCH_Bs instead. 2044 * 2045 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2046 */ 2047 /* op vAA, vBB, vCC */ 2048 FETCH_B(r2, 1, 0) @ r2<- BB 2049 mov r9, rINST, lsr #8 @ r9<- AA 2050 FETCH_B(r3, 1, 1) @ r3<- CC 2051 GET_VREG(r0, r2) @ r0<- vBB (array object) 2052 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2053 cmp r0, #0 @ null array object? 2054 beq common_errNullObject @ yes, bail 2055 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2056 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2057 cmp r1, r3 @ compare unsigned index, length 2058 bcs common_errArrayIndex @ index >= length, bail 2059 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2060 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2061 GET_INST_OPCODE(ip) @ extract opcode from rINST 2062 SET_VREG(r2, r9) @ vAA<- r2 2063 GOTO_OPCODE(ip) @ jump to next instruction 2064 2065 2066/* ------------------------------ */ 2067 .balign 64 2068.L_OP_AGET_BYTE: /* 0x48 */ 2069/* File: armv5te/OP_AGET_BYTE.S */ 2070/* File: armv5te/OP_AGET.S */ 2071 /* 2072 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2073 * 2074 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2075 * instructions. We use a pair of FETCH_Bs instead. 2076 * 2077 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2078 */ 2079 /* op vAA, vBB, vCC */ 2080 FETCH_B(r2, 1, 0) @ r2<- BB 2081 mov r9, rINST, lsr #8 @ r9<- AA 2082 FETCH_B(r3, 1, 1) @ r3<- CC 2083 GET_VREG(r0, r2) @ r0<- vBB (array object) 2084 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2085 cmp r0, #0 @ null array object? 2086 beq common_errNullObject @ yes, bail 2087 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2088 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2089 cmp r1, r3 @ compare unsigned index, length 2090 bcs common_errArrayIndex @ index >= length, bail 2091 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2092 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2093 GET_INST_OPCODE(ip) @ extract opcode from rINST 2094 SET_VREG(r2, r9) @ vAA<- r2 2095 GOTO_OPCODE(ip) @ jump to next instruction 2096 2097 2098/* ------------------------------ */ 2099 .balign 64 2100.L_OP_AGET_CHAR: /* 0x49 */ 2101/* File: armv5te/OP_AGET_CHAR.S */ 2102/* File: armv5te/OP_AGET.S */ 2103 /* 2104 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2105 * 2106 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2107 * instructions. We use a pair of FETCH_Bs instead. 2108 * 2109 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2110 */ 2111 /* op vAA, vBB, vCC */ 2112 FETCH_B(r2, 1, 0) @ r2<- BB 2113 mov r9, rINST, lsr #8 @ r9<- AA 2114 FETCH_B(r3, 1, 1) @ r3<- CC 2115 GET_VREG(r0, r2) @ r0<- vBB (array object) 2116 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2117 cmp r0, #0 @ null array object? 2118 beq common_errNullObject @ yes, bail 2119 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2120 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2121 cmp r1, r3 @ compare unsigned index, length 2122 bcs common_errArrayIndex @ index >= length, bail 2123 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2124 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2125 GET_INST_OPCODE(ip) @ extract opcode from rINST 2126 SET_VREG(r2, r9) @ vAA<- r2 2127 GOTO_OPCODE(ip) @ jump to next instruction 2128 2129 2130/* ------------------------------ */ 2131 .balign 64 2132.L_OP_AGET_SHORT: /* 0x4a */ 2133/* File: armv5te/OP_AGET_SHORT.S */ 2134/* File: armv5te/OP_AGET.S */ 2135 /* 2136 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2137 * 2138 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2139 * instructions. We use a pair of FETCH_Bs instead. 2140 * 2141 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2142 */ 2143 /* op vAA, vBB, vCC */ 2144 FETCH_B(r2, 1, 0) @ r2<- BB 2145 mov r9, rINST, lsr #8 @ r9<- AA 2146 FETCH_B(r3, 1, 1) @ r3<- CC 2147 GET_VREG(r0, r2) @ r0<- vBB (array object) 2148 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2149 cmp r0, #0 @ null array object? 2150 beq common_errNullObject @ yes, bail 2151 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2152 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2153 cmp r1, r3 @ compare unsigned index, length 2154 bcs common_errArrayIndex @ index >= length, bail 2155 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2156 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2157 GET_INST_OPCODE(ip) @ extract opcode from rINST 2158 SET_VREG(r2, r9) @ vAA<- r2 2159 GOTO_OPCODE(ip) @ jump to next instruction 2160 2161 2162/* ------------------------------ */ 2163 .balign 64 2164.L_OP_APUT: /* 0x4b */ 2165/* File: armv5te/OP_APUT.S */ 2166 /* 2167 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2168 * 2169 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2170 * instructions. We use a pair of FETCH_Bs instead. 2171 * 2172 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2173 */ 2174 /* op vAA, vBB, vCC */ 2175 FETCH_B(r2, 1, 0) @ r2<- BB 2176 mov r9, rINST, lsr #8 @ r9<- AA 2177 FETCH_B(r3, 1, 1) @ r3<- CC 2178 GET_VREG(r0, r2) @ r0<- vBB (array object) 2179 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2180 cmp r0, #0 @ null array object? 2181 beq common_errNullObject @ yes, bail 2182 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2183 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2184 cmp r1, r3 @ compare unsigned index, length 2185 bcs common_errArrayIndex @ index >= length, bail 2186 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2187 GET_VREG(r2, r9) @ r2<- vAA 2188 GET_INST_OPCODE(ip) @ extract opcode from rINST 2189 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2190 GOTO_OPCODE(ip) @ jump to next instruction 2191 2192/* ------------------------------ */ 2193 .balign 64 2194.L_OP_APUT_WIDE: /* 0x4c */ 2195/* File: armv5te/OP_APUT_WIDE.S */ 2196 /* 2197 * Array put, 64 bits. vBB[vCC] <- vAA. 2198 * 2199 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2200 */ 2201 /* aput-wide vAA, vBB, vCC */ 2202 FETCH(r0, 1) @ r0<- CCBB 2203 mov r9, rINST, lsr #8 @ r9<- AA 2204 and r2, r0, #255 @ r2<- BB 2205 mov r3, r0, lsr #8 @ r3<- CC 2206 GET_VREG(r0, r2) @ r0<- vBB (array object) 2207 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2208 cmp r0, #0 @ null array object? 2209 beq common_errNullObject @ yes, bail 2210 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2211 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2212 cmp r1, r3 @ compare unsigned index, length 2213 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2214 bcc .LOP_APUT_WIDE_finish @ okay, continue below 2215 b common_errArrayIndex @ index >= length, bail 2216 @ May want to swap the order of these two branches depending on how the 2217 @ branch prediction (if any) handles conditional forward branches vs. 2218 @ unconditional forward branches. 2219 2220/* ------------------------------ */ 2221 .balign 64 2222.L_OP_APUT_OBJECT: /* 0x4d */ 2223/* File: armv5te/OP_APUT_OBJECT.S */ 2224 /* 2225 * Store an object into an array. vBB[vCC] <- vAA. 2226 */ 2227 /* op vAA, vBB, vCC */ 2228 FETCH(r0, 1) @ r0<- CCBB 2229 mov r9, rINST, lsr #8 @ r9<- AA 2230 and r2, r0, #255 @ r2<- BB 2231 mov r3, r0, lsr #8 @ r3<- CC 2232 GET_VREG(rINST, r2) @ rINST<- vBB (array object) 2233 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2234 cmp rINST, #0 @ null array object? 2235 GET_VREG(r9, r9) @ r9<- vAA 2236 beq common_errNullObject @ yes, bail 2237 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length 2238 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width 2239 cmp r1, r3 @ compare unsigned index, length 2240 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2241 b common_errArrayIndex @ index >= length, bail 2242 2243 2244/* ------------------------------ */ 2245 .balign 64 2246.L_OP_APUT_BOOLEAN: /* 0x4e */ 2247/* File: armv5te/OP_APUT_BOOLEAN.S */ 2248/* File: armv5te/OP_APUT.S */ 2249 /* 2250 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2251 * 2252 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2253 * instructions. We use a pair of FETCH_Bs instead. 2254 * 2255 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2256 */ 2257 /* op vAA, vBB, vCC */ 2258 FETCH_B(r2, 1, 0) @ r2<- BB 2259 mov r9, rINST, lsr #8 @ r9<- AA 2260 FETCH_B(r3, 1, 1) @ r3<- CC 2261 GET_VREG(r0, r2) @ r0<- vBB (array object) 2262 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2263 cmp r0, #0 @ null array object? 2264 beq common_errNullObject @ yes, bail 2265 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2266 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2267 cmp r1, r3 @ compare unsigned index, length 2268 bcs common_errArrayIndex @ index >= length, bail 2269 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2270 GET_VREG(r2, r9) @ r2<- vAA 2271 GET_INST_OPCODE(ip) @ extract opcode from rINST 2272 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2273 GOTO_OPCODE(ip) @ jump to next instruction 2274 2275 2276/* ------------------------------ */ 2277 .balign 64 2278.L_OP_APUT_BYTE: /* 0x4f */ 2279/* File: armv5te/OP_APUT_BYTE.S */ 2280/* File: armv5te/OP_APUT.S */ 2281 /* 2282 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2283 * 2284 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2285 * instructions. We use a pair of FETCH_Bs instead. 2286 * 2287 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2288 */ 2289 /* op vAA, vBB, vCC */ 2290 FETCH_B(r2, 1, 0) @ r2<- BB 2291 mov r9, rINST, lsr #8 @ r9<- AA 2292 FETCH_B(r3, 1, 1) @ r3<- CC 2293 GET_VREG(r0, r2) @ r0<- vBB (array object) 2294 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2295 cmp r0, #0 @ null array object? 2296 beq common_errNullObject @ yes, bail 2297 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2298 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2299 cmp r1, r3 @ compare unsigned index, length 2300 bcs common_errArrayIndex @ index >= length, bail 2301 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2302 GET_VREG(r2, r9) @ r2<- vAA 2303 GET_INST_OPCODE(ip) @ extract opcode from rINST 2304 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2305 GOTO_OPCODE(ip) @ jump to next instruction 2306 2307 2308/* ------------------------------ */ 2309 .balign 64 2310.L_OP_APUT_CHAR: /* 0x50 */ 2311/* File: armv5te/OP_APUT_CHAR.S */ 2312/* File: armv5te/OP_APUT.S */ 2313 /* 2314 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2315 * 2316 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2317 * instructions. We use a pair of FETCH_Bs instead. 2318 * 2319 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2320 */ 2321 /* op vAA, vBB, vCC */ 2322 FETCH_B(r2, 1, 0) @ r2<- BB 2323 mov r9, rINST, lsr #8 @ r9<- AA 2324 FETCH_B(r3, 1, 1) @ r3<- CC 2325 GET_VREG(r0, r2) @ r0<- vBB (array object) 2326 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2327 cmp r0, #0 @ null array object? 2328 beq common_errNullObject @ yes, bail 2329 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2330 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2331 cmp r1, r3 @ compare unsigned index, length 2332 bcs common_errArrayIndex @ index >= length, bail 2333 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2334 GET_VREG(r2, r9) @ r2<- vAA 2335 GET_INST_OPCODE(ip) @ extract opcode from rINST 2336 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2337 GOTO_OPCODE(ip) @ jump to next instruction 2338 2339 2340/* ------------------------------ */ 2341 .balign 64 2342.L_OP_APUT_SHORT: /* 0x51 */ 2343/* File: armv5te/OP_APUT_SHORT.S */ 2344/* File: armv5te/OP_APUT.S */ 2345 /* 2346 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2347 * 2348 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2349 * instructions. We use a pair of FETCH_Bs instead. 2350 * 2351 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2352 */ 2353 /* op vAA, vBB, vCC */ 2354 FETCH_B(r2, 1, 0) @ r2<- BB 2355 mov r9, rINST, lsr #8 @ r9<- AA 2356 FETCH_B(r3, 1, 1) @ r3<- CC 2357 GET_VREG(r0, r2) @ r0<- vBB (array object) 2358 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2359 cmp r0, #0 @ null array object? 2360 beq common_errNullObject @ yes, bail 2361 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2362 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2363 cmp r1, r3 @ compare unsigned index, length 2364 bcs common_errArrayIndex @ index >= length, bail 2365 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2366 GET_VREG(r2, r9) @ r2<- vAA 2367 GET_INST_OPCODE(ip) @ extract opcode from rINST 2368 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2369 GOTO_OPCODE(ip) @ jump to next instruction 2370 2371 2372/* ------------------------------ */ 2373 .balign 64 2374.L_OP_IGET: /* 0x52 */ 2375/* File: armv5te/OP_IGET.S */ 2376 /* 2377 * General 32-bit instance field get. 2378 * 2379 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2380 */ 2381 /* op vA, vB, field@CCCC */ 2382 mov r0, rINST, lsr #12 @ r0<- B 2383 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2384 FETCH(r1, 1) @ r1<- field ref CCCC 2385 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2386 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2387 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2388 cmp r0, #0 @ is resolved entry null? 2389 bne .LOP_IGET_finish @ no, already resolved 23908: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2391 EXPORT_PC() @ resolve() could throw 2392 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2393 bl dvmResolveInstField @ r0<- resolved InstField ptr 2394 cmp r0, #0 2395 bne .LOP_IGET_finish 2396 b common_exceptionThrown 2397 2398/* ------------------------------ */ 2399 .balign 64 2400.L_OP_IGET_WIDE: /* 0x53 */ 2401/* File: armv5te/OP_IGET_WIDE.S */ 2402 /* 2403 * Wide 32-bit instance field get. 2404 */ 2405 /* iget-wide vA, vB, field@CCCC */ 2406 mov r0, rINST, lsr #12 @ r0<- B 2407 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2408 FETCH(r1, 1) @ r1<- field ref CCCC 2409 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2410 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2411 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2412 cmp r0, #0 @ is resolved entry null? 2413 bne .LOP_IGET_WIDE_finish @ no, already resolved 24148: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2415 EXPORT_PC() @ resolve() could throw 2416 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2417 bl dvmResolveInstField @ r0<- resolved InstField ptr 2418 cmp r0, #0 2419 bne .LOP_IGET_WIDE_finish 2420 b common_exceptionThrown 2421 2422/* ------------------------------ */ 2423 .balign 64 2424.L_OP_IGET_OBJECT: /* 0x54 */ 2425/* File: armv5te/OP_IGET_OBJECT.S */ 2426/* File: armv5te/OP_IGET.S */ 2427 /* 2428 * General 32-bit instance field get. 2429 * 2430 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2431 */ 2432 /* op vA, vB, field@CCCC */ 2433 mov r0, rINST, lsr #12 @ r0<- B 2434 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2435 FETCH(r1, 1) @ r1<- field ref CCCC 2436 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2437 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2438 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2439 cmp r0, #0 @ is resolved entry null? 2440 bne .LOP_IGET_OBJECT_finish @ no, already resolved 24418: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2442 EXPORT_PC() @ resolve() could throw 2443 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2444 bl dvmResolveInstField @ r0<- resolved InstField ptr 2445 cmp r0, #0 2446 bne .LOP_IGET_OBJECT_finish 2447 b common_exceptionThrown 2448 2449 2450/* ------------------------------ */ 2451 .balign 64 2452.L_OP_IGET_BOOLEAN: /* 0x55 */ 2453/* File: armv5te/OP_IGET_BOOLEAN.S */ 2454@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2455/* File: armv5te/OP_IGET.S */ 2456 /* 2457 * General 32-bit instance field get. 2458 * 2459 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2460 */ 2461 /* op vA, vB, field@CCCC */ 2462 mov r0, rINST, lsr #12 @ r0<- B 2463 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2464 FETCH(r1, 1) @ r1<- field ref CCCC 2465 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2466 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2467 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2468 cmp r0, #0 @ is resolved entry null? 2469 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 24708: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2471 EXPORT_PC() @ resolve() could throw 2472 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2473 bl dvmResolveInstField @ r0<- resolved InstField ptr 2474 cmp r0, #0 2475 bne .LOP_IGET_BOOLEAN_finish 2476 b common_exceptionThrown 2477 2478 2479/* ------------------------------ */ 2480 .balign 64 2481.L_OP_IGET_BYTE: /* 0x56 */ 2482/* File: armv5te/OP_IGET_BYTE.S */ 2483@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2484/* File: armv5te/OP_IGET.S */ 2485 /* 2486 * General 32-bit instance field get. 2487 * 2488 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2489 */ 2490 /* op vA, vB, field@CCCC */ 2491 mov r0, rINST, lsr #12 @ r0<- B 2492 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2493 FETCH(r1, 1) @ r1<- field ref CCCC 2494 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2495 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2496 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2497 cmp r0, #0 @ is resolved entry null? 2498 bne .LOP_IGET_BYTE_finish @ no, already resolved 24998: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2500 EXPORT_PC() @ resolve() could throw 2501 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2502 bl dvmResolveInstField @ r0<- resolved InstField ptr 2503 cmp r0, #0 2504 bne .LOP_IGET_BYTE_finish 2505 b common_exceptionThrown 2506 2507 2508/* ------------------------------ */ 2509 .balign 64 2510.L_OP_IGET_CHAR: /* 0x57 */ 2511/* File: armv5te/OP_IGET_CHAR.S */ 2512@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2513/* File: armv5te/OP_IGET.S */ 2514 /* 2515 * General 32-bit instance field get. 2516 * 2517 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2518 */ 2519 /* op vA, vB, field@CCCC */ 2520 mov r0, rINST, lsr #12 @ r0<- B 2521 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2522 FETCH(r1, 1) @ r1<- field ref CCCC 2523 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2524 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2525 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2526 cmp r0, #0 @ is resolved entry null? 2527 bne .LOP_IGET_CHAR_finish @ no, already resolved 25288: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2529 EXPORT_PC() @ resolve() could throw 2530 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2531 bl dvmResolveInstField @ r0<- resolved InstField ptr 2532 cmp r0, #0 2533 bne .LOP_IGET_CHAR_finish 2534 b common_exceptionThrown 2535 2536 2537/* ------------------------------ */ 2538 .balign 64 2539.L_OP_IGET_SHORT: /* 0x58 */ 2540/* File: armv5te/OP_IGET_SHORT.S */ 2541@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2542/* File: armv5te/OP_IGET.S */ 2543 /* 2544 * General 32-bit instance field get. 2545 * 2546 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2547 */ 2548 /* op vA, vB, field@CCCC */ 2549 mov r0, rINST, lsr #12 @ r0<- B 2550 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2551 FETCH(r1, 1) @ r1<- field ref CCCC 2552 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2553 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2554 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2555 cmp r0, #0 @ is resolved entry null? 2556 bne .LOP_IGET_SHORT_finish @ no, already resolved 25578: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2558 EXPORT_PC() @ resolve() could throw 2559 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2560 bl dvmResolveInstField @ r0<- resolved InstField ptr 2561 cmp r0, #0 2562 bne .LOP_IGET_SHORT_finish 2563 b common_exceptionThrown 2564 2565 2566/* ------------------------------ */ 2567 .balign 64 2568.L_OP_IPUT: /* 0x59 */ 2569/* File: armv5te/OP_IPUT.S */ 2570 /* 2571 * General 32-bit instance field put. 2572 * 2573 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2574 */ 2575 /* op vA, vB, field@CCCC */ 2576 mov r0, rINST, lsr #12 @ r0<- B 2577 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2578 FETCH(r1, 1) @ r1<- field ref CCCC 2579 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2580 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2581 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2582 cmp r0, #0 @ is resolved entry null? 2583 bne .LOP_IPUT_finish @ no, already resolved 25848: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2585 EXPORT_PC() @ resolve() could throw 2586 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2587 bl dvmResolveInstField @ r0<- resolved InstField ptr 2588 cmp r0, #0 @ success? 2589 bne .LOP_IPUT_finish @ yes, finish up 2590 b common_exceptionThrown 2591 2592/* ------------------------------ */ 2593 .balign 64 2594.L_OP_IPUT_WIDE: /* 0x5a */ 2595/* File: armv5te/OP_IPUT_WIDE.S */ 2596 /* iput-wide vA, vB, field@CCCC */ 2597 mov r0, rINST, lsr #12 @ r0<- B 2598 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2599 FETCH(r1, 1) @ r1<- field ref CCCC 2600 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2601 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2602 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2603 cmp r0, #0 @ is resolved entry null? 2604 bne .LOP_IPUT_WIDE_finish @ no, already resolved 26058: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2606 EXPORT_PC() @ resolve() could throw 2607 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2608 bl dvmResolveInstField @ r0<- resolved InstField ptr 2609 cmp r0, #0 @ success? 2610 bne .LOP_IPUT_WIDE_finish @ yes, finish up 2611 b common_exceptionThrown 2612 2613/* ------------------------------ */ 2614 .balign 64 2615.L_OP_IPUT_OBJECT: /* 0x5b */ 2616/* File: armv5te/OP_IPUT_OBJECT.S */ 2617 /* 2618 * 32-bit instance field put. 2619 * 2620 * for: iput-object, iput-object-volatile 2621 */ 2622 /* op vA, vB, field@CCCC */ 2623 mov r0, rINST, lsr #12 @ r0<- B 2624 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2625 FETCH(r1, 1) @ r1<- field ref CCCC 2626 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2627 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2628 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2629 cmp r0, #0 @ is resolved entry null? 2630 bne .LOP_IPUT_OBJECT_finish @ no, already resolved 26318: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2632 EXPORT_PC() @ resolve() could throw 2633 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2634 bl dvmResolveInstField @ r0<- resolved InstField ptr 2635 cmp r0, #0 @ success? 2636 bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2637 b common_exceptionThrown 2638 2639/* ------------------------------ */ 2640 .balign 64 2641.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2642/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2643@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2644/* File: armv5te/OP_IPUT.S */ 2645 /* 2646 * General 32-bit instance field put. 2647 * 2648 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2649 */ 2650 /* op vA, vB, field@CCCC */ 2651 mov r0, rINST, lsr #12 @ r0<- B 2652 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2653 FETCH(r1, 1) @ r1<- field ref CCCC 2654 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2655 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2656 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2657 cmp r0, #0 @ is resolved entry null? 2658 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 26598: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2660 EXPORT_PC() @ resolve() could throw 2661 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2662 bl dvmResolveInstField @ r0<- resolved InstField ptr 2663 cmp r0, #0 @ success? 2664 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2665 b common_exceptionThrown 2666 2667 2668/* ------------------------------ */ 2669 .balign 64 2670.L_OP_IPUT_BYTE: /* 0x5d */ 2671/* File: armv5te/OP_IPUT_BYTE.S */ 2672@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2673/* File: armv5te/OP_IPUT.S */ 2674 /* 2675 * General 32-bit instance field put. 2676 * 2677 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2678 */ 2679 /* op vA, vB, field@CCCC */ 2680 mov r0, rINST, lsr #12 @ r0<- B 2681 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2682 FETCH(r1, 1) @ r1<- field ref CCCC 2683 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2684 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2685 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2686 cmp r0, #0 @ is resolved entry null? 2687 bne .LOP_IPUT_BYTE_finish @ no, already resolved 26888: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2689 EXPORT_PC() @ resolve() could throw 2690 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2691 bl dvmResolveInstField @ r0<- resolved InstField ptr 2692 cmp r0, #0 @ success? 2693 bne .LOP_IPUT_BYTE_finish @ yes, finish up 2694 b common_exceptionThrown 2695 2696 2697/* ------------------------------ */ 2698 .balign 64 2699.L_OP_IPUT_CHAR: /* 0x5e */ 2700/* File: armv5te/OP_IPUT_CHAR.S */ 2701@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2702/* File: armv5te/OP_IPUT.S */ 2703 /* 2704 * General 32-bit instance field put. 2705 * 2706 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2707 */ 2708 /* op vA, vB, field@CCCC */ 2709 mov r0, rINST, lsr #12 @ r0<- B 2710 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2711 FETCH(r1, 1) @ r1<- field ref CCCC 2712 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2713 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2714 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2715 cmp r0, #0 @ is resolved entry null? 2716 bne .LOP_IPUT_CHAR_finish @ no, already resolved 27178: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2718 EXPORT_PC() @ resolve() could throw 2719 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2720 bl dvmResolveInstField @ r0<- resolved InstField ptr 2721 cmp r0, #0 @ success? 2722 bne .LOP_IPUT_CHAR_finish @ yes, finish up 2723 b common_exceptionThrown 2724 2725 2726/* ------------------------------ */ 2727 .balign 64 2728.L_OP_IPUT_SHORT: /* 0x5f */ 2729/* File: armv5te/OP_IPUT_SHORT.S */ 2730@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2731/* File: armv5te/OP_IPUT.S */ 2732 /* 2733 * General 32-bit instance field put. 2734 * 2735 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2736 */ 2737 /* op vA, vB, field@CCCC */ 2738 mov r0, rINST, lsr #12 @ r0<- B 2739 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2740 FETCH(r1, 1) @ r1<- field ref CCCC 2741 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2742 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2743 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2744 cmp r0, #0 @ is resolved entry null? 2745 bne .LOP_IPUT_SHORT_finish @ no, already resolved 27468: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2747 EXPORT_PC() @ resolve() could throw 2748 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2749 bl dvmResolveInstField @ r0<- resolved InstField ptr 2750 cmp r0, #0 @ success? 2751 bne .LOP_IPUT_SHORT_finish @ yes, finish up 2752 b common_exceptionThrown 2753 2754 2755/* ------------------------------ */ 2756 .balign 64 2757.L_OP_SGET: /* 0x60 */ 2758/* File: armv5te/OP_SGET.S */ 2759 /* 2760 * General 32-bit SGET handler. 2761 * 2762 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2763 */ 2764 /* op vAA, field@BBBB */ 2765 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2766 FETCH(r1, 1) @ r1<- field ref BBBB 2767 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2768 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2769 cmp r0, #0 @ is resolved entry null? 2770 beq .LOP_SGET_resolve @ yes, do resolve 2771.LOP_SGET_finish: @ field ptr in r0 2772 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2773 @ no-op @ acquiring load 2774 mov r2, rINST, lsr #8 @ r2<- AA 2775 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2776 SET_VREG(r1, r2) @ fp[AA]<- r1 2777 GET_INST_OPCODE(ip) @ extract opcode from rINST 2778 GOTO_OPCODE(ip) @ jump to next instruction 2779 2780/* ------------------------------ */ 2781 .balign 64 2782.L_OP_SGET_WIDE: /* 0x61 */ 2783/* File: armv5te/OP_SGET_WIDE.S */ 2784 /* 2785 * 64-bit SGET handler. 2786 */ 2787 /* sget-wide vAA, field@BBBB */ 2788 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2789 FETCH(r1, 1) @ r1<- field ref BBBB 2790 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2791 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2792 cmp r0, #0 @ is resolved entry null? 2793 beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2794.LOP_SGET_WIDE_finish: 2795 mov r9, rINST, lsr #8 @ r9<- AA 2796 .if 0 2797 add r0, r0, #offStaticField_value @ r0<- pointer to data 2798 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2799 .else 2800 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2801 .endif 2802 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2803 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2804 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2805 GET_INST_OPCODE(ip) @ extract opcode from rINST 2806 GOTO_OPCODE(ip) @ jump to next instruction 2807 2808/* ------------------------------ */ 2809 .balign 64 2810.L_OP_SGET_OBJECT: /* 0x62 */ 2811/* File: armv5te/OP_SGET_OBJECT.S */ 2812/* File: armv5te/OP_SGET.S */ 2813 /* 2814 * General 32-bit SGET handler. 2815 * 2816 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2817 */ 2818 /* op vAA, field@BBBB */ 2819 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2820 FETCH(r1, 1) @ r1<- field ref BBBB 2821 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2822 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2823 cmp r0, #0 @ is resolved entry null? 2824 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2825.LOP_SGET_OBJECT_finish: @ field ptr in r0 2826 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2827 @ no-op @ acquiring load 2828 mov r2, rINST, lsr #8 @ r2<- AA 2829 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2830 SET_VREG(r1, r2) @ fp[AA]<- r1 2831 GET_INST_OPCODE(ip) @ extract opcode from rINST 2832 GOTO_OPCODE(ip) @ jump to next instruction 2833 2834 2835/* ------------------------------ */ 2836 .balign 64 2837.L_OP_SGET_BOOLEAN: /* 0x63 */ 2838/* File: armv5te/OP_SGET_BOOLEAN.S */ 2839/* File: armv5te/OP_SGET.S */ 2840 /* 2841 * General 32-bit SGET handler. 2842 * 2843 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2844 */ 2845 /* op vAA, field@BBBB */ 2846 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2847 FETCH(r1, 1) @ r1<- field ref BBBB 2848 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2849 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2850 cmp r0, #0 @ is resolved entry null? 2851 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2852.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2853 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2854 @ no-op @ acquiring load 2855 mov r2, rINST, lsr #8 @ r2<- AA 2856 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2857 SET_VREG(r1, r2) @ fp[AA]<- r1 2858 GET_INST_OPCODE(ip) @ extract opcode from rINST 2859 GOTO_OPCODE(ip) @ jump to next instruction 2860 2861 2862/* ------------------------------ */ 2863 .balign 64 2864.L_OP_SGET_BYTE: /* 0x64 */ 2865/* File: armv5te/OP_SGET_BYTE.S */ 2866/* File: armv5te/OP_SGET.S */ 2867 /* 2868 * General 32-bit SGET handler. 2869 * 2870 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2871 */ 2872 /* op vAA, field@BBBB */ 2873 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2874 FETCH(r1, 1) @ r1<- field ref BBBB 2875 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2876 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2877 cmp r0, #0 @ is resolved entry null? 2878 beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2879.LOP_SGET_BYTE_finish: @ field ptr in r0 2880 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2881 @ no-op @ acquiring load 2882 mov r2, rINST, lsr #8 @ r2<- AA 2883 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2884 SET_VREG(r1, r2) @ fp[AA]<- r1 2885 GET_INST_OPCODE(ip) @ extract opcode from rINST 2886 GOTO_OPCODE(ip) @ jump to next instruction 2887 2888 2889/* ------------------------------ */ 2890 .balign 64 2891.L_OP_SGET_CHAR: /* 0x65 */ 2892/* File: armv5te/OP_SGET_CHAR.S */ 2893/* File: armv5te/OP_SGET.S */ 2894 /* 2895 * General 32-bit SGET handler. 2896 * 2897 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2898 */ 2899 /* op vAA, field@BBBB */ 2900 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2901 FETCH(r1, 1) @ r1<- field ref BBBB 2902 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2903 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2904 cmp r0, #0 @ is resolved entry null? 2905 beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2906.LOP_SGET_CHAR_finish: @ field ptr in r0 2907 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2908 @ no-op @ acquiring load 2909 mov r2, rINST, lsr #8 @ r2<- AA 2910 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2911 SET_VREG(r1, r2) @ fp[AA]<- r1 2912 GET_INST_OPCODE(ip) @ extract opcode from rINST 2913 GOTO_OPCODE(ip) @ jump to next instruction 2914 2915 2916/* ------------------------------ */ 2917 .balign 64 2918.L_OP_SGET_SHORT: /* 0x66 */ 2919/* File: armv5te/OP_SGET_SHORT.S */ 2920/* File: armv5te/OP_SGET.S */ 2921 /* 2922 * General 32-bit SGET handler. 2923 * 2924 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2925 */ 2926 /* op vAA, field@BBBB */ 2927 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2928 FETCH(r1, 1) @ r1<- field ref BBBB 2929 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2930 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2931 cmp r0, #0 @ is resolved entry null? 2932 beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2933.LOP_SGET_SHORT_finish: @ field ptr in r0 2934 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2935 @ no-op @ acquiring load 2936 mov r2, rINST, lsr #8 @ r2<- AA 2937 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2938 SET_VREG(r1, r2) @ fp[AA]<- r1 2939 GET_INST_OPCODE(ip) @ extract opcode from rINST 2940 GOTO_OPCODE(ip) @ jump to next instruction 2941 2942 2943/* ------------------------------ */ 2944 .balign 64 2945.L_OP_SPUT: /* 0x67 */ 2946/* File: armv5te/OP_SPUT.S */ 2947 /* 2948 * General 32-bit SPUT handler. 2949 * 2950 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2951 */ 2952 /* op vAA, field@BBBB */ 2953 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2954 FETCH(r1, 1) @ r1<- field ref BBBB 2955 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2956 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2957 cmp r0, #0 @ is resolved entry null? 2958 beq .LOP_SPUT_resolve @ yes, do resolve 2959.LOP_SPUT_finish: @ field ptr in r0 2960 mov r2, rINST, lsr #8 @ r2<- AA 2961 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2962 GET_VREG(r1, r2) @ r1<- fp[AA] 2963 GET_INST_OPCODE(ip) @ extract opcode from rINST 2964 @ no-op @ releasing store 2965 str r1, [r0, #offStaticField_value] @ field<- vAA 2966 GOTO_OPCODE(ip) @ jump to next instruction 2967 2968/* ------------------------------ */ 2969 .balign 64 2970.L_OP_SPUT_WIDE: /* 0x68 */ 2971/* File: armv5te/OP_SPUT_WIDE.S */ 2972 /* 2973 * 64-bit SPUT handler. 2974 */ 2975 /* sput-wide vAA, field@BBBB */ 2976 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 2977 FETCH(r1, 1) @ r1<- field ref BBBB 2978 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 2979 mov r9, rINST, lsr #8 @ r9<- AA 2980 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 2981 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2982 cmp r2, #0 @ is resolved entry null? 2983 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 2984.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 2985 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2986 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 2987 GET_INST_OPCODE(r10) @ extract opcode from rINST 2988 .if 0 2989 add r2, r2, #offStaticField_value @ r2<- pointer to data 2990 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 2991 .else 2992 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 2993 .endif 2994 GOTO_OPCODE(r10) @ jump to next instruction 2995 2996/* ------------------------------ */ 2997 .balign 64 2998.L_OP_SPUT_OBJECT: /* 0x69 */ 2999/* File: armv5te/OP_SPUT_OBJECT.S */ 3000 /* 3001 * 32-bit SPUT handler for objects 3002 * 3003 * for: sput-object, sput-object-volatile 3004 */ 3005 /* op vAA, field@BBBB */ 3006 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3007 FETCH(r1, 1) @ r1<- field ref BBBB 3008 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3009 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3010 cmp r0, #0 @ is resolved entry null? 3011 bne .LOP_SPUT_OBJECT_finish @ no, continue 3012 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3013 EXPORT_PC() @ resolve() could throw, so export now 3014 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 3015 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 3016 cmp r0, #0 @ success? 3017 bne .LOP_SPUT_OBJECT_finish @ yes, finish 3018 b common_exceptionThrown @ no, handle exception 3019 3020 3021/* ------------------------------ */ 3022 .balign 64 3023.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3024/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3025/* File: armv5te/OP_SPUT.S */ 3026 /* 3027 * General 32-bit SPUT handler. 3028 * 3029 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3030 */ 3031 /* op vAA, field@BBBB */ 3032 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3033 FETCH(r1, 1) @ r1<- field ref BBBB 3034 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3035 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3036 cmp r0, #0 @ is resolved entry null? 3037 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3038.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3039 mov r2, rINST, lsr #8 @ r2<- AA 3040 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3041 GET_VREG(r1, r2) @ r1<- fp[AA] 3042 GET_INST_OPCODE(ip) @ extract opcode from rINST 3043 @ no-op @ releasing store 3044 str r1, [r0, #offStaticField_value] @ field<- vAA 3045 GOTO_OPCODE(ip) @ jump to next instruction 3046 3047 3048/* ------------------------------ */ 3049 .balign 64 3050.L_OP_SPUT_BYTE: /* 0x6b */ 3051/* File: armv5te/OP_SPUT_BYTE.S */ 3052/* File: armv5te/OP_SPUT.S */ 3053 /* 3054 * General 32-bit SPUT handler. 3055 * 3056 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3057 */ 3058 /* op vAA, field@BBBB */ 3059 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3060 FETCH(r1, 1) @ r1<- field ref BBBB 3061 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3062 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3063 cmp r0, #0 @ is resolved entry null? 3064 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3065.LOP_SPUT_BYTE_finish: @ field ptr in r0 3066 mov r2, rINST, lsr #8 @ r2<- AA 3067 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3068 GET_VREG(r1, r2) @ r1<- fp[AA] 3069 GET_INST_OPCODE(ip) @ extract opcode from rINST 3070 @ no-op @ releasing store 3071 str r1, [r0, #offStaticField_value] @ field<- vAA 3072 GOTO_OPCODE(ip) @ jump to next instruction 3073 3074 3075/* ------------------------------ */ 3076 .balign 64 3077.L_OP_SPUT_CHAR: /* 0x6c */ 3078/* File: armv5te/OP_SPUT_CHAR.S */ 3079/* File: armv5te/OP_SPUT.S */ 3080 /* 3081 * General 32-bit SPUT handler. 3082 * 3083 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3084 */ 3085 /* op vAA, field@BBBB */ 3086 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3087 FETCH(r1, 1) @ r1<- field ref BBBB 3088 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3089 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3090 cmp r0, #0 @ is resolved entry null? 3091 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3092.LOP_SPUT_CHAR_finish: @ field ptr in r0 3093 mov r2, rINST, lsr #8 @ r2<- AA 3094 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3095 GET_VREG(r1, r2) @ r1<- fp[AA] 3096 GET_INST_OPCODE(ip) @ extract opcode from rINST 3097 @ no-op @ releasing store 3098 str r1, [r0, #offStaticField_value] @ field<- vAA 3099 GOTO_OPCODE(ip) @ jump to next instruction 3100 3101 3102/* ------------------------------ */ 3103 .balign 64 3104.L_OP_SPUT_SHORT: /* 0x6d */ 3105/* File: armv5te/OP_SPUT_SHORT.S */ 3106/* File: armv5te/OP_SPUT.S */ 3107 /* 3108 * General 32-bit SPUT handler. 3109 * 3110 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3111 */ 3112 /* op vAA, field@BBBB */ 3113 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3114 FETCH(r1, 1) @ r1<- field ref BBBB 3115 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3116 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3117 cmp r0, #0 @ is resolved entry null? 3118 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3119.LOP_SPUT_SHORT_finish: @ field ptr in r0 3120 mov r2, rINST, lsr #8 @ r2<- AA 3121 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3122 GET_VREG(r1, r2) @ r1<- fp[AA] 3123 GET_INST_OPCODE(ip) @ extract opcode from rINST 3124 @ no-op @ releasing store 3125 str r1, [r0, #offStaticField_value] @ field<- vAA 3126 GOTO_OPCODE(ip) @ jump to next instruction 3127 3128 3129/* ------------------------------ */ 3130 .balign 64 3131.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3132/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3133 /* 3134 * Handle a virtual method call. 3135 * 3136 * for: invoke-virtual, invoke-virtual/range 3137 */ 3138 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3139 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3140 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3141 FETCH(r1, 1) @ r1<- BBBB 3142 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3143 FETCH(r10, 2) @ r10<- GFED or CCCC 3144 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3145 .if (!0) 3146 and r10, r10, #15 @ r10<- D (or stays CCCC) 3147 .endif 3148 cmp r0, #0 @ already resolved? 3149 EXPORT_PC() @ must export for invoke 3150 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3151 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3152 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3153 mov r2, #METHOD_VIRTUAL @ resolver method type 3154 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3155 cmp r0, #0 @ got null? 3156 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3157 b common_exceptionThrown @ yes, handle exception 3158 3159/* ------------------------------ */ 3160 .balign 64 3161.L_OP_INVOKE_SUPER: /* 0x6f */ 3162/* File: armv5te/OP_INVOKE_SUPER.S */ 3163 /* 3164 * Handle a "super" method call. 3165 * 3166 * for: invoke-super, invoke-super/range 3167 */ 3168 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3169 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3170 FETCH(r10, 2) @ r10<- GFED or CCCC 3171 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3172 .if (!0) 3173 and r10, r10, #15 @ r10<- D (or stays CCCC) 3174 .endif 3175 FETCH(r1, 1) @ r1<- BBBB 3176 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3177 GET_VREG(r2, r10) @ r2<- "this" ptr 3178 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3179 cmp r2, #0 @ null "this"? 3180 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3181 beq common_errNullObject @ null "this", throw exception 3182 cmp r0, #0 @ already resolved? 3183 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3184 EXPORT_PC() @ must export for invoke 3185 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3186 b .LOP_INVOKE_SUPER_resolve @ do resolve now 3187 3188/* ------------------------------ */ 3189 .balign 64 3190.L_OP_INVOKE_DIRECT: /* 0x70 */ 3191/* File: armv5te/OP_INVOKE_DIRECT.S */ 3192 /* 3193 * Handle a direct method call. 3194 * 3195 * (We could defer the "is 'this' pointer null" test to the common 3196 * method invocation code, and use a flag to indicate that static 3197 * calls don't count. If we do this as part of copying the arguments 3198 * out we could avoiding loading the first arg twice.) 3199 * 3200 * for: invoke-direct, invoke-direct/range 3201 */ 3202 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3203 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3204 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3205 FETCH(r1, 1) @ r1<- BBBB 3206 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3207 FETCH(r10, 2) @ r10<- GFED or CCCC 3208 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3209 .if (!0) 3210 and r10, r10, #15 @ r10<- D (or stays CCCC) 3211 .endif 3212 cmp r0, #0 @ already resolved? 3213 EXPORT_PC() @ must export for invoke 3214 GET_VREG(r2, r10) @ r2<- "this" ptr 3215 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3216.LOP_INVOKE_DIRECT_finish: 3217 cmp r2, #0 @ null "this" ref? 3218 bne common_invokeMethodNoRange @ no, continue on 3219 b common_errNullObject @ yes, throw exception 3220 3221/* ------------------------------ */ 3222 .balign 64 3223.L_OP_INVOKE_STATIC: /* 0x71 */ 3224/* File: armv5te/OP_INVOKE_STATIC.S */ 3225 /* 3226 * Handle a static method call. 3227 * 3228 * for: invoke-static, invoke-static/range 3229 */ 3230 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3231 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3232 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3233 FETCH(r1, 1) @ r1<- BBBB 3234 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3235 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3236 cmp r0, #0 @ already resolved? 3237 EXPORT_PC() @ must export for invoke 3238 bne common_invokeMethodNoRange @ yes, continue on 32390: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3240 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3241 mov r2, #METHOD_STATIC @ resolver method type 3242 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3243 cmp r0, #0 @ got null? 3244 bne common_invokeMethodNoRange @ no, continue 3245 b common_exceptionThrown @ yes, handle exception 3246 3247/* ------------------------------ */ 3248 .balign 64 3249.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3250/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3251 /* 3252 * Handle an interface method call. 3253 * 3254 * for: invoke-interface, invoke-interface/range 3255 */ 3256 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3257 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3258 FETCH(r2, 2) @ r2<- FEDC or CCCC 3259 FETCH(r1, 1) @ r1<- BBBB 3260 .if (!0) 3261 and r2, r2, #15 @ r2<- C (or stays CCCC) 3262 .endif 3263 EXPORT_PC() @ must export for invoke 3264 GET_VREG(r0, r2) @ r0<- first arg ("this") 3265 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3266 cmp r0, #0 @ null obj? 3267 ldr r2, [rSELF, #offThread_method] @ r2<- method 3268 beq common_errNullObject @ yes, fail 3269 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3270 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3271 cmp r0, #0 @ failed? 3272 beq common_exceptionThrown @ yes, handle exception 3273 b common_invokeMethodNoRange @ jump to common handler 3274 3275/* ------------------------------ */ 3276 .balign 64 3277.L_OP_UNUSED_73: /* 0x73 */ 3278/* File: armv5te/OP_UNUSED_73.S */ 3279/* File: armv5te/unused.S */ 3280 bl common_abort 3281 3282 3283/* ------------------------------ */ 3284 .balign 64 3285.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3286/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3287/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3288 /* 3289 * Handle a virtual method call. 3290 * 3291 * for: invoke-virtual, invoke-virtual/range 3292 */ 3293 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3294 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3295 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3296 FETCH(r1, 1) @ r1<- BBBB 3297 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3298 FETCH(r10, 2) @ r10<- GFED or CCCC 3299 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3300 .if (!1) 3301 and r10, r10, #15 @ r10<- D (or stays CCCC) 3302 .endif 3303 cmp r0, #0 @ already resolved? 3304 EXPORT_PC() @ must export for invoke 3305 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3306 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3307 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3308 mov r2, #METHOD_VIRTUAL @ resolver method type 3309 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3310 cmp r0, #0 @ got null? 3311 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3312 b common_exceptionThrown @ yes, handle exception 3313 3314 3315/* ------------------------------ */ 3316 .balign 64 3317.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3318/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3319/* File: armv5te/OP_INVOKE_SUPER.S */ 3320 /* 3321 * Handle a "super" method call. 3322 * 3323 * for: invoke-super, invoke-super/range 3324 */ 3325 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3326 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3327 FETCH(r10, 2) @ r10<- GFED or CCCC 3328 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3329 .if (!1) 3330 and r10, r10, #15 @ r10<- D (or stays CCCC) 3331 .endif 3332 FETCH(r1, 1) @ r1<- BBBB 3333 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3334 GET_VREG(r2, r10) @ r2<- "this" ptr 3335 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3336 cmp r2, #0 @ null "this"? 3337 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3338 beq common_errNullObject @ null "this", throw exception 3339 cmp r0, #0 @ already resolved? 3340 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3341 EXPORT_PC() @ must export for invoke 3342 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3343 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3344 3345 3346/* ------------------------------ */ 3347 .balign 64 3348.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3349/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3350/* File: armv5te/OP_INVOKE_DIRECT.S */ 3351 /* 3352 * Handle a direct method call. 3353 * 3354 * (We could defer the "is 'this' pointer null" test to the common 3355 * method invocation code, and use a flag to indicate that static 3356 * calls don't count. If we do this as part of copying the arguments 3357 * out we could avoiding loading the first arg twice.) 3358 * 3359 * for: invoke-direct, invoke-direct/range 3360 */ 3361 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3362 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3363 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3364 FETCH(r1, 1) @ r1<- BBBB 3365 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3366 FETCH(r10, 2) @ r10<- GFED or CCCC 3367 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3368 .if (!1) 3369 and r10, r10, #15 @ r10<- D (or stays CCCC) 3370 .endif 3371 cmp r0, #0 @ already resolved? 3372 EXPORT_PC() @ must export for invoke 3373 GET_VREG(r2, r10) @ r2<- "this" ptr 3374 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3375.LOP_INVOKE_DIRECT_RANGE_finish: 3376 cmp r2, #0 @ null "this" ref? 3377 bne common_invokeMethodRange @ no, continue on 3378 b common_errNullObject @ yes, throw exception 3379 3380 3381/* ------------------------------ */ 3382 .balign 64 3383.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3384/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3385/* File: armv5te/OP_INVOKE_STATIC.S */ 3386 /* 3387 * Handle a static method call. 3388 * 3389 * for: invoke-static, invoke-static/range 3390 */ 3391 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3392 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3393 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3394 FETCH(r1, 1) @ r1<- BBBB 3395 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3396 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3397 cmp r0, #0 @ already resolved? 3398 EXPORT_PC() @ must export for invoke 3399 bne common_invokeMethodRange @ yes, continue on 34000: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3401 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3402 mov r2, #METHOD_STATIC @ resolver method type 3403 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3404 cmp r0, #0 @ got null? 3405 bne common_invokeMethodRange @ no, continue 3406 b common_exceptionThrown @ yes, handle exception 3407 3408 3409/* ------------------------------ */ 3410 .balign 64 3411.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3412/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3413/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3414 /* 3415 * Handle an interface method call. 3416 * 3417 * for: invoke-interface, invoke-interface/range 3418 */ 3419 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3420 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3421 FETCH(r2, 2) @ r2<- FEDC or CCCC 3422 FETCH(r1, 1) @ r1<- BBBB 3423 .if (!1) 3424 and r2, r2, #15 @ r2<- C (or stays CCCC) 3425 .endif 3426 EXPORT_PC() @ must export for invoke 3427 GET_VREG(r0, r2) @ r0<- first arg ("this") 3428 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3429 cmp r0, #0 @ null obj? 3430 ldr r2, [rSELF, #offThread_method] @ r2<- method 3431 beq common_errNullObject @ yes, fail 3432 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3433 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3434 cmp r0, #0 @ failed? 3435 beq common_exceptionThrown @ yes, handle exception 3436 b common_invokeMethodRange @ jump to common handler 3437 3438 3439/* ------------------------------ */ 3440 .balign 64 3441.L_OP_UNUSED_79: /* 0x79 */ 3442/* File: armv5te/OP_UNUSED_79.S */ 3443/* File: armv5te/unused.S */ 3444 bl common_abort 3445 3446 3447/* ------------------------------ */ 3448 .balign 64 3449.L_OP_UNUSED_7A: /* 0x7a */ 3450/* File: armv5te/OP_UNUSED_7A.S */ 3451/* File: armv5te/unused.S */ 3452 bl common_abort 3453 3454 3455/* ------------------------------ */ 3456 .balign 64 3457.L_OP_NEG_INT: /* 0x7b */ 3458/* File: armv5te/OP_NEG_INT.S */ 3459/* File: armv5te/unop.S */ 3460 /* 3461 * Generic 32-bit unary operation. Provide an "instr" line that 3462 * specifies an instruction that performs "result = op r0". 3463 * This could be an ARM instruction or a function call. 3464 * 3465 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3466 * int-to-byte, int-to-char, int-to-short 3467 */ 3468 /* unop vA, vB */ 3469 mov r3, rINST, lsr #12 @ r3<- B 3470 mov r9, rINST, lsr #8 @ r9<- A+ 3471 GET_VREG(r0, r3) @ r0<- vB 3472 and r9, r9, #15 3473 @ optional op; may set condition codes 3474 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3475 rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3476 GET_INST_OPCODE(ip) @ extract opcode from rINST 3477 SET_VREG(r0, r9) @ vAA<- r0 3478 GOTO_OPCODE(ip) @ jump to next instruction 3479 /* 9-10 instructions */ 3480 3481 3482/* ------------------------------ */ 3483 .balign 64 3484.L_OP_NOT_INT: /* 0x7c */ 3485/* File: armv5te/OP_NOT_INT.S */ 3486/* File: armv5te/unop.S */ 3487 /* 3488 * Generic 32-bit unary operation. Provide an "instr" line that 3489 * specifies an instruction that performs "result = op r0". 3490 * This could be an ARM instruction or a function call. 3491 * 3492 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3493 * int-to-byte, int-to-char, int-to-short 3494 */ 3495 /* unop vA, vB */ 3496 mov r3, rINST, lsr #12 @ r3<- B 3497 mov r9, rINST, lsr #8 @ r9<- A+ 3498 GET_VREG(r0, r3) @ r0<- vB 3499 and r9, r9, #15 3500 @ optional op; may set condition codes 3501 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3502 mvn r0, r0 @ r0<- op, r0-r3 changed 3503 GET_INST_OPCODE(ip) @ extract opcode from rINST 3504 SET_VREG(r0, r9) @ vAA<- r0 3505 GOTO_OPCODE(ip) @ jump to next instruction 3506 /* 9-10 instructions */ 3507 3508 3509/* ------------------------------ */ 3510 .balign 64 3511.L_OP_NEG_LONG: /* 0x7d */ 3512/* File: armv5te/OP_NEG_LONG.S */ 3513/* File: armv5te/unopWide.S */ 3514 /* 3515 * Generic 64-bit unary operation. Provide an "instr" line that 3516 * specifies an instruction that performs "result = op r0/r1". 3517 * This could be an ARM instruction or a function call. 3518 * 3519 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3520 */ 3521 /* unop vA, vB */ 3522 mov r9, rINST, lsr #8 @ r9<- A+ 3523 mov r3, rINST, lsr #12 @ r3<- B 3524 and r9, r9, #15 3525 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3526 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3527 ldmia r3, {r0-r1} @ r0/r1<- vAA 3528 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3529 rsbs r0, r0, #0 @ optional op; may set condition codes 3530 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3531 GET_INST_OPCODE(ip) @ extract opcode from rINST 3532 stmia r9, {r0-r1} @ vAA<- r0/r1 3533 GOTO_OPCODE(ip) @ jump to next instruction 3534 /* 12-13 instructions */ 3535 3536 3537/* ------------------------------ */ 3538 .balign 64 3539.L_OP_NOT_LONG: /* 0x7e */ 3540/* File: armv5te/OP_NOT_LONG.S */ 3541/* File: armv5te/unopWide.S */ 3542 /* 3543 * Generic 64-bit unary operation. Provide an "instr" line that 3544 * specifies an instruction that performs "result = op r0/r1". 3545 * This could be an ARM instruction or a function call. 3546 * 3547 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3548 */ 3549 /* unop vA, vB */ 3550 mov r9, rINST, lsr #8 @ r9<- A+ 3551 mov r3, rINST, lsr #12 @ r3<- B 3552 and r9, r9, #15 3553 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3554 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3555 ldmia r3, {r0-r1} @ r0/r1<- vAA 3556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3557 mvn r0, r0 @ optional op; may set condition codes 3558 mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3559 GET_INST_OPCODE(ip) @ extract opcode from rINST 3560 stmia r9, {r0-r1} @ vAA<- r0/r1 3561 GOTO_OPCODE(ip) @ jump to next instruction 3562 /* 12-13 instructions */ 3563 3564 3565/* ------------------------------ */ 3566 .balign 64 3567.L_OP_NEG_FLOAT: /* 0x7f */ 3568/* File: armv5te/OP_NEG_FLOAT.S */ 3569/* File: armv5te/unop.S */ 3570 /* 3571 * Generic 32-bit unary operation. Provide an "instr" line that 3572 * specifies an instruction that performs "result = op r0". 3573 * This could be an ARM instruction or a function call. 3574 * 3575 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3576 * int-to-byte, int-to-char, int-to-short 3577 */ 3578 /* unop vA, vB */ 3579 mov r3, rINST, lsr #12 @ r3<- B 3580 mov r9, rINST, lsr #8 @ r9<- A+ 3581 GET_VREG(r0, r3) @ r0<- vB 3582 and r9, r9, #15 3583 @ optional op; may set condition codes 3584 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3585 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3586 GET_INST_OPCODE(ip) @ extract opcode from rINST 3587 SET_VREG(r0, r9) @ vAA<- r0 3588 GOTO_OPCODE(ip) @ jump to next instruction 3589 /* 9-10 instructions */ 3590 3591 3592/* ------------------------------ */ 3593 .balign 64 3594.L_OP_NEG_DOUBLE: /* 0x80 */ 3595/* File: armv5te/OP_NEG_DOUBLE.S */ 3596/* File: armv5te/unopWide.S */ 3597 /* 3598 * Generic 64-bit unary operation. Provide an "instr" line that 3599 * specifies an instruction that performs "result = op r0/r1". 3600 * This could be an ARM instruction or a function call. 3601 * 3602 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3603 */ 3604 /* unop vA, vB */ 3605 mov r9, rINST, lsr #8 @ r9<- A+ 3606 mov r3, rINST, lsr #12 @ r3<- B 3607 and r9, r9, #15 3608 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3609 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3610 ldmia r3, {r0-r1} @ r0/r1<- vAA 3611 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3612 @ optional op; may set condition codes 3613 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3614 GET_INST_OPCODE(ip) @ extract opcode from rINST 3615 stmia r9, {r0-r1} @ vAA<- r0/r1 3616 GOTO_OPCODE(ip) @ jump to next instruction 3617 /* 12-13 instructions */ 3618 3619 3620/* ------------------------------ */ 3621 .balign 64 3622.L_OP_INT_TO_LONG: /* 0x81 */ 3623/* File: armv5te/OP_INT_TO_LONG.S */ 3624/* File: armv5te/unopWider.S */ 3625 /* 3626 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3627 * that specifies an instruction that performs "result = op r0", where 3628 * "result" is a 64-bit quantity in r0/r1. 3629 * 3630 * For: int-to-long, int-to-double, float-to-long, float-to-double 3631 */ 3632 /* unop vA, vB */ 3633 mov r9, rINST, lsr #8 @ r9<- A+ 3634 mov r3, rINST, lsr #12 @ r3<- B 3635 and r9, r9, #15 3636 GET_VREG(r0, r3) @ r0<- vB 3637 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3638 @ optional op; may set condition codes 3639 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3640 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3641 GET_INST_OPCODE(ip) @ extract opcode from rINST 3642 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3643 GOTO_OPCODE(ip) @ jump to next instruction 3644 /* 10-11 instructions */ 3645 3646 3647/* ------------------------------ */ 3648 .balign 64 3649.L_OP_INT_TO_FLOAT: /* 0x82 */ 3650/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3651/* File: arm-vfp/funop.S */ 3652 /* 3653 * Generic 32-bit unary floating-point operation. Provide an "instr" 3654 * line that specifies an instruction that performs "s1 = op s0". 3655 * 3656 * for: int-to-float, float-to-int 3657 */ 3658 /* unop vA, vB */ 3659 mov r3, rINST, lsr #12 @ r3<- B 3660 mov r9, rINST, lsr #8 @ r9<- A+ 3661 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3662 flds s0, [r3] @ s0<- vB 3663 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3664 and r9, r9, #15 @ r9<- A 3665 fsitos s1, s0 @ s1<- op 3666 GET_INST_OPCODE(ip) @ extract opcode from rINST 3667 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3668 fsts s1, [r9] @ vA<- s1 3669 GOTO_OPCODE(ip) @ jump to next instruction 3670 3671 3672/* ------------------------------ */ 3673 .balign 64 3674.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3675/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3676/* File: arm-vfp/funopWider.S */ 3677 /* 3678 * Generic 32bit-to-64bit floating point unary operation. Provide an 3679 * "instr" line that specifies an instruction that performs "d0 = op s0". 3680 * 3681 * For: int-to-double, float-to-double 3682 */ 3683 /* unop vA, vB */ 3684 mov r3, rINST, lsr #12 @ r3<- B 3685 mov r9, rINST, lsr #8 @ r9<- A+ 3686 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3687 flds s0, [r3] @ s0<- vB 3688 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3689 and r9, r9, #15 @ r9<- A 3690 fsitod d0, s0 @ d0<- op 3691 GET_INST_OPCODE(ip) @ extract opcode from rINST 3692 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3693 fstd d0, [r9] @ vA<- d0 3694 GOTO_OPCODE(ip) @ jump to next instruction 3695 3696 3697/* ------------------------------ */ 3698 .balign 64 3699.L_OP_LONG_TO_INT: /* 0x84 */ 3700/* File: armv5te/OP_LONG_TO_INT.S */ 3701/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3702/* File: armv5te/OP_MOVE.S */ 3703 /* for move, move-object, long-to-int */ 3704 /* op vA, vB */ 3705 mov r1, rINST, lsr #12 @ r1<- B from 15:12 3706 mov r0, rINST, lsr #8 @ r0<- A from 11:8 3707 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3708 GET_VREG(r2, r1) @ r2<- fp[B] 3709 and r0, r0, #15 3710 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3711 SET_VREG(r2, r0) @ fp[A]<- r2 3712 GOTO_OPCODE(ip) @ execute next instruction 3713 3714 3715/* ------------------------------ */ 3716 .balign 64 3717.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3718/* File: armv5te/OP_LONG_TO_FLOAT.S */ 3719/* File: armv5te/unopNarrower.S */ 3720 /* 3721 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3722 * that specifies an instruction that performs "result = op r0/r1", where 3723 * "result" is a 32-bit quantity in r0. 3724 * 3725 * For: long-to-float, double-to-int, double-to-float 3726 * 3727 * (This would work for long-to-int, but that instruction is actually 3728 * an exact match for OP_MOVE.) 3729 */ 3730 /* unop vA, vB */ 3731 mov r3, rINST, lsr #12 @ r3<- B 3732 mov r9, rINST, lsr #8 @ r9<- A+ 3733 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3734 and r9, r9, #15 3735 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3736 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3737 @ optional op; may set condition codes 3738 bl __aeabi_l2f @ r0<- op, r0-r3 changed 3739 GET_INST_OPCODE(ip) @ extract opcode from rINST 3740 SET_VREG(r0, r9) @ vA<- r0 3741 GOTO_OPCODE(ip) @ jump to next instruction 3742 /* 10-11 instructions */ 3743 3744 3745/* ------------------------------ */ 3746 .balign 64 3747.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3748/* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3749/* File: armv5te/unopWide.S */ 3750 /* 3751 * Generic 64-bit unary operation. Provide an "instr" line that 3752 * specifies an instruction that performs "result = op r0/r1". 3753 * This could be an ARM instruction or a function call. 3754 * 3755 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3756 */ 3757 /* unop vA, vB */ 3758 mov r9, rINST, lsr #8 @ r9<- A+ 3759 mov r3, rINST, lsr #12 @ r3<- B 3760 and r9, r9, #15 3761 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3762 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3763 ldmia r3, {r0-r1} @ r0/r1<- vAA 3764 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3765 @ optional op; may set condition codes 3766 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3767 GET_INST_OPCODE(ip) @ extract opcode from rINST 3768 stmia r9, {r0-r1} @ vAA<- r0/r1 3769 GOTO_OPCODE(ip) @ jump to next instruction 3770 /* 12-13 instructions */ 3771 3772 3773/* ------------------------------ */ 3774 .balign 64 3775.L_OP_FLOAT_TO_INT: /* 0x87 */ 3776/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3777/* File: arm-vfp/funop.S */ 3778 /* 3779 * Generic 32-bit unary floating-point operation. Provide an "instr" 3780 * line that specifies an instruction that performs "s1 = op s0". 3781 * 3782 * for: int-to-float, float-to-int 3783 */ 3784 /* unop vA, vB */ 3785 mov r3, rINST, lsr #12 @ r3<- B 3786 mov r9, rINST, lsr #8 @ r9<- A+ 3787 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3788 flds s0, [r3] @ s0<- vB 3789 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3790 and r9, r9, #15 @ r9<- A 3791 ftosizs s1, s0 @ s1<- op 3792 GET_INST_OPCODE(ip) @ extract opcode from rINST 3793 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3794 fsts s1, [r9] @ vA<- s1 3795 GOTO_OPCODE(ip) @ jump to next instruction 3796 3797 3798/* ------------------------------ */ 3799 .balign 64 3800.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3801/* File: armv5te/OP_FLOAT_TO_LONG.S */ 3802@include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3803/* File: armv5te/unopWider.S */ 3804 /* 3805 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3806 * that specifies an instruction that performs "result = op r0", where 3807 * "result" is a 64-bit quantity in r0/r1. 3808 * 3809 * For: int-to-long, int-to-double, float-to-long, float-to-double 3810 */ 3811 /* unop vA, vB */ 3812 mov r9, rINST, lsr #8 @ r9<- A+ 3813 mov r3, rINST, lsr #12 @ r3<- B 3814 and r9, r9, #15 3815 GET_VREG(r0, r3) @ r0<- vB 3816 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3817 @ optional op; may set condition codes 3818 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3819 bl f2l_doconv @ r0<- op, r0-r3 changed 3820 GET_INST_OPCODE(ip) @ extract opcode from rINST 3821 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3822 GOTO_OPCODE(ip) @ jump to next instruction 3823 /* 10-11 instructions */ 3824 3825 3826 3827/* ------------------------------ */ 3828 .balign 64 3829.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3830/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3831/* File: arm-vfp/funopWider.S */ 3832 /* 3833 * Generic 32bit-to-64bit floating point unary operation. Provide an 3834 * "instr" line that specifies an instruction that performs "d0 = op s0". 3835 * 3836 * For: int-to-double, float-to-double 3837 */ 3838 /* unop vA, vB */ 3839 mov r3, rINST, lsr #12 @ r3<- B 3840 mov r9, rINST, lsr #8 @ r9<- A+ 3841 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3842 flds s0, [r3] @ s0<- vB 3843 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3844 and r9, r9, #15 @ r9<- A 3845 fcvtds d0, s0 @ d0<- op 3846 GET_INST_OPCODE(ip) @ extract opcode from rINST 3847 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3848 fstd d0, [r9] @ vA<- d0 3849 GOTO_OPCODE(ip) @ jump to next instruction 3850 3851 3852/* ------------------------------ */ 3853 .balign 64 3854.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3855/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3856/* File: arm-vfp/funopNarrower.S */ 3857 /* 3858 * Generic 64bit-to-32bit unary floating point operation. Provide an 3859 * "instr" line that specifies an instruction that performs "s0 = op d0". 3860 * 3861 * For: double-to-int, double-to-float 3862 */ 3863 /* unop vA, vB */ 3864 mov r3, rINST, lsr #12 @ r3<- B 3865 mov r9, rINST, lsr #8 @ r9<- A+ 3866 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3867 fldd d0, [r3] @ d0<- vB 3868 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3869 and r9, r9, #15 @ r9<- A 3870 ftosizd s0, d0 @ s0<- op 3871 GET_INST_OPCODE(ip) @ extract opcode from rINST 3872 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3873 fsts s0, [r9] @ vA<- s0 3874 GOTO_OPCODE(ip) @ jump to next instruction 3875 3876 3877/* ------------------------------ */ 3878 .balign 64 3879.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3880/* File: armv5te/OP_DOUBLE_TO_LONG.S */ 3881@include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3882/* File: armv5te/unopWide.S */ 3883 /* 3884 * Generic 64-bit unary operation. Provide an "instr" line that 3885 * specifies an instruction that performs "result = op r0/r1". 3886 * This could be an ARM instruction or a function call. 3887 * 3888 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3889 */ 3890 /* unop vA, vB */ 3891 mov r9, rINST, lsr #8 @ r9<- A+ 3892 mov r3, rINST, lsr #12 @ r3<- B 3893 and r9, r9, #15 3894 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3895 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3896 ldmia r3, {r0-r1} @ r0/r1<- vAA 3897 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3898 @ optional op; may set condition codes 3899 bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3900 GET_INST_OPCODE(ip) @ extract opcode from rINST 3901 stmia r9, {r0-r1} @ vAA<- r0/r1 3902 GOTO_OPCODE(ip) @ jump to next instruction 3903 /* 12-13 instructions */ 3904 3905 3906 3907/* ------------------------------ */ 3908 .balign 64 3909.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3910/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3911/* File: arm-vfp/funopNarrower.S */ 3912 /* 3913 * Generic 64bit-to-32bit unary floating point operation. Provide an 3914 * "instr" line that specifies an instruction that performs "s0 = op d0". 3915 * 3916 * For: double-to-int, double-to-float 3917 */ 3918 /* unop vA, vB */ 3919 mov r3, rINST, lsr #12 @ r3<- B 3920 mov r9, rINST, lsr #8 @ r9<- A+ 3921 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3922 fldd d0, [r3] @ d0<- vB 3923 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3924 and r9, r9, #15 @ r9<- A 3925 fcvtsd s0, d0 @ s0<- op 3926 GET_INST_OPCODE(ip) @ extract opcode from rINST 3927 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3928 fsts s0, [r9] @ vA<- s0 3929 GOTO_OPCODE(ip) @ jump to next instruction 3930 3931 3932/* ------------------------------ */ 3933 .balign 64 3934.L_OP_INT_TO_BYTE: /* 0x8d */ 3935/* File: armv5te/OP_INT_TO_BYTE.S */ 3936/* File: armv5te/unop.S */ 3937 /* 3938 * Generic 32-bit unary operation. Provide an "instr" line that 3939 * specifies an instruction that performs "result = op r0". 3940 * This could be an ARM instruction or a function call. 3941 * 3942 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3943 * int-to-byte, int-to-char, int-to-short 3944 */ 3945 /* unop vA, vB */ 3946 mov r3, rINST, lsr #12 @ r3<- B 3947 mov r9, rINST, lsr #8 @ r9<- A+ 3948 GET_VREG(r0, r3) @ r0<- vB 3949 and r9, r9, #15 3950 mov r0, r0, asl #24 @ optional op; may set condition codes 3951 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3952 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 3953 GET_INST_OPCODE(ip) @ extract opcode from rINST 3954 SET_VREG(r0, r9) @ vAA<- r0 3955 GOTO_OPCODE(ip) @ jump to next instruction 3956 /* 9-10 instructions */ 3957 3958 3959/* ------------------------------ */ 3960 .balign 64 3961.L_OP_INT_TO_CHAR: /* 0x8e */ 3962/* File: armv5te/OP_INT_TO_CHAR.S */ 3963/* File: armv5te/unop.S */ 3964 /* 3965 * Generic 32-bit unary operation. Provide an "instr" line that 3966 * specifies an instruction that performs "result = op r0". 3967 * This could be an ARM instruction or a function call. 3968 * 3969 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3970 * int-to-byte, int-to-char, int-to-short 3971 */ 3972 /* unop vA, vB */ 3973 mov r3, rINST, lsr #12 @ r3<- B 3974 mov r9, rINST, lsr #8 @ r9<- A+ 3975 GET_VREG(r0, r3) @ r0<- vB 3976 and r9, r9, #15 3977 mov r0, r0, asl #16 @ optional op; may set condition codes 3978 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3979 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 3980 GET_INST_OPCODE(ip) @ extract opcode from rINST 3981 SET_VREG(r0, r9) @ vAA<- r0 3982 GOTO_OPCODE(ip) @ jump to next instruction 3983 /* 9-10 instructions */ 3984 3985 3986/* ------------------------------ */ 3987 .balign 64 3988.L_OP_INT_TO_SHORT: /* 0x8f */ 3989/* File: armv5te/OP_INT_TO_SHORT.S */ 3990/* File: armv5te/unop.S */ 3991 /* 3992 * Generic 32-bit unary operation. Provide an "instr" line that 3993 * specifies an instruction that performs "result = op r0". 3994 * This could be an ARM instruction or a function call. 3995 * 3996 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3997 * int-to-byte, int-to-char, int-to-short 3998 */ 3999 /* unop vA, vB */ 4000 mov r3, rINST, lsr #12 @ r3<- B 4001 mov r9, rINST, lsr #8 @ r9<- A+ 4002 GET_VREG(r0, r3) @ r0<- vB 4003 and r9, r9, #15 4004 mov r0, r0, asl #16 @ optional op; may set condition codes 4005 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4006 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 4007 GET_INST_OPCODE(ip) @ extract opcode from rINST 4008 SET_VREG(r0, r9) @ vAA<- r0 4009 GOTO_OPCODE(ip) @ jump to next instruction 4010 /* 9-10 instructions */ 4011 4012 4013/* ------------------------------ */ 4014 .balign 64 4015.L_OP_ADD_INT: /* 0x90 */ 4016/* File: armv5te/OP_ADD_INT.S */ 4017/* File: armv5te/binop.S */ 4018 /* 4019 * Generic 32-bit binary operation. Provide an "instr" line that 4020 * specifies an instruction that performs "result = r0 op r1". 4021 * This could be an ARM instruction or a function call. (If the result 4022 * comes back in a register other than r0, you can override "result".) 4023 * 4024 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4025 * vCC (r1). Useful for integer division and modulus. Note that we 4026 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4027 * handles it correctly. 4028 * 4029 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4030 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4031 * mul-float, div-float, rem-float 4032 */ 4033 /* binop vAA, vBB, vCC */ 4034 FETCH(r0, 1) @ r0<- CCBB 4035 mov r9, rINST, lsr #8 @ r9<- AA 4036 mov r3, r0, lsr #8 @ r3<- CC 4037 and r2, r0, #255 @ r2<- BB 4038 GET_VREG(r1, r3) @ r1<- vCC 4039 GET_VREG(r0, r2) @ r0<- vBB 4040 .if 0 4041 cmp r1, #0 @ is second operand zero? 4042 beq common_errDivideByZero 4043 .endif 4044 4045 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4046 @ optional op; may set condition codes 4047 add r0, r0, r1 @ r0<- op, r0-r3 changed 4048 GET_INST_OPCODE(ip) @ extract opcode from rINST 4049 SET_VREG(r0, r9) @ vAA<- r0 4050 GOTO_OPCODE(ip) @ jump to next instruction 4051 /* 11-14 instructions */ 4052 4053 4054/* ------------------------------ */ 4055 .balign 64 4056.L_OP_SUB_INT: /* 0x91 */ 4057/* File: armv5te/OP_SUB_INT.S */ 4058/* File: armv5te/binop.S */ 4059 /* 4060 * Generic 32-bit binary operation. Provide an "instr" line that 4061 * specifies an instruction that performs "result = r0 op r1". 4062 * This could be an ARM instruction or a function call. (If the result 4063 * comes back in a register other than r0, you can override "result".) 4064 * 4065 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4066 * vCC (r1). Useful for integer division and modulus. Note that we 4067 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4068 * handles it correctly. 4069 * 4070 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4071 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4072 * mul-float, div-float, rem-float 4073 */ 4074 /* binop vAA, vBB, vCC */ 4075 FETCH(r0, 1) @ r0<- CCBB 4076 mov r9, rINST, lsr #8 @ r9<- AA 4077 mov r3, r0, lsr #8 @ r3<- CC 4078 and r2, r0, #255 @ r2<- BB 4079 GET_VREG(r1, r3) @ r1<- vCC 4080 GET_VREG(r0, r2) @ r0<- vBB 4081 .if 0 4082 cmp r1, #0 @ is second operand zero? 4083 beq common_errDivideByZero 4084 .endif 4085 4086 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4087 @ optional op; may set condition codes 4088 sub r0, r0, r1 @ r0<- op, r0-r3 changed 4089 GET_INST_OPCODE(ip) @ extract opcode from rINST 4090 SET_VREG(r0, r9) @ vAA<- r0 4091 GOTO_OPCODE(ip) @ jump to next instruction 4092 /* 11-14 instructions */ 4093 4094 4095/* ------------------------------ */ 4096 .balign 64 4097.L_OP_MUL_INT: /* 0x92 */ 4098/* File: armv5te/OP_MUL_INT.S */ 4099/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4100/* File: armv5te/binop.S */ 4101 /* 4102 * Generic 32-bit binary operation. Provide an "instr" line that 4103 * specifies an instruction that performs "result = r0 op r1". 4104 * This could be an ARM instruction or a function call. (If the result 4105 * comes back in a register other than r0, you can override "result".) 4106 * 4107 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4108 * vCC (r1). Useful for integer division and modulus. Note that we 4109 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4110 * handles it correctly. 4111 * 4112 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4113 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4114 * mul-float, div-float, rem-float 4115 */ 4116 /* binop vAA, vBB, vCC */ 4117 FETCH(r0, 1) @ r0<- CCBB 4118 mov r9, rINST, lsr #8 @ r9<- AA 4119 mov r3, r0, lsr #8 @ r3<- CC 4120 and r2, r0, #255 @ r2<- BB 4121 GET_VREG(r1, r3) @ r1<- vCC 4122 GET_VREG(r0, r2) @ r0<- vBB 4123 .if 0 4124 cmp r1, #0 @ is second operand zero? 4125 beq common_errDivideByZero 4126 .endif 4127 4128 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4129 @ optional op; may set condition codes 4130 mul r0, r1, r0 @ r0<- op, r0-r3 changed 4131 GET_INST_OPCODE(ip) @ extract opcode from rINST 4132 SET_VREG(r0, r9) @ vAA<- r0 4133 GOTO_OPCODE(ip) @ jump to next instruction 4134 /* 11-14 instructions */ 4135 4136 4137/* ------------------------------ */ 4138 .balign 64 4139.L_OP_DIV_INT: /* 0x93 */ 4140/* File: armv5te/OP_DIV_INT.S */ 4141/* File: armv5te/binop.S */ 4142 /* 4143 * Generic 32-bit binary operation. Provide an "instr" line that 4144 * specifies an instruction that performs "result = r0 op r1". 4145 * This could be an ARM instruction or a function call. (If the result 4146 * comes back in a register other than r0, you can override "result".) 4147 * 4148 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4149 * vCC (r1). Useful for integer division and modulus. Note that we 4150 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4151 * handles it correctly. 4152 * 4153 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4154 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4155 * mul-float, div-float, rem-float 4156 */ 4157 /* binop vAA, vBB, vCC */ 4158 FETCH(r0, 1) @ r0<- CCBB 4159 mov r9, rINST, lsr #8 @ r9<- AA 4160 mov r3, r0, lsr #8 @ r3<- CC 4161 and r2, r0, #255 @ r2<- BB 4162 GET_VREG(r1, r3) @ r1<- vCC 4163 GET_VREG(r0, r2) @ r0<- vBB 4164 .if 1 4165 cmp r1, #0 @ is second operand zero? 4166 beq common_errDivideByZero 4167 .endif 4168 4169 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4170 @ optional op; may set condition codes 4171 bl __aeabi_idiv @ r0<- op, r0-r3 changed 4172 GET_INST_OPCODE(ip) @ extract opcode from rINST 4173 SET_VREG(r0, r9) @ vAA<- r0 4174 GOTO_OPCODE(ip) @ jump to next instruction 4175 /* 11-14 instructions */ 4176 4177 4178/* ------------------------------ */ 4179 .balign 64 4180.L_OP_REM_INT: /* 0x94 */ 4181/* File: armv5te/OP_REM_INT.S */ 4182/* idivmod returns quotient in r0 and remainder in r1 */ 4183/* File: armv5te/binop.S */ 4184 /* 4185 * Generic 32-bit binary operation. Provide an "instr" line that 4186 * specifies an instruction that performs "result = r0 op r1". 4187 * This could be an ARM instruction or a function call. (If the result 4188 * comes back in a register other than r0, you can override "result".) 4189 * 4190 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4191 * vCC (r1). Useful for integer division and modulus. Note that we 4192 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4193 * handles it correctly. 4194 * 4195 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4196 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4197 * mul-float, div-float, rem-float 4198 */ 4199 /* binop vAA, vBB, vCC */ 4200 FETCH(r0, 1) @ r0<- CCBB 4201 mov r9, rINST, lsr #8 @ r9<- AA 4202 mov r3, r0, lsr #8 @ r3<- CC 4203 and r2, r0, #255 @ r2<- BB 4204 GET_VREG(r1, r3) @ r1<- vCC 4205 GET_VREG(r0, r2) @ r0<- vBB 4206 .if 1 4207 cmp r1, #0 @ is second operand zero? 4208 beq common_errDivideByZero 4209 .endif 4210 4211 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4212 @ optional op; may set condition codes 4213 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4214 GET_INST_OPCODE(ip) @ extract opcode from rINST 4215 SET_VREG(r1, r9) @ vAA<- r1 4216 GOTO_OPCODE(ip) @ jump to next instruction 4217 /* 11-14 instructions */ 4218 4219 4220/* ------------------------------ */ 4221 .balign 64 4222.L_OP_AND_INT: /* 0x95 */ 4223/* File: armv5te/OP_AND_INT.S */ 4224/* File: armv5te/binop.S */ 4225 /* 4226 * Generic 32-bit binary operation. Provide an "instr" line that 4227 * specifies an instruction that performs "result = r0 op r1". 4228 * This could be an ARM instruction or a function call. (If the result 4229 * comes back in a register other than r0, you can override "result".) 4230 * 4231 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4232 * vCC (r1). Useful for integer division and modulus. Note that we 4233 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4234 * handles it correctly. 4235 * 4236 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4237 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4238 * mul-float, div-float, rem-float 4239 */ 4240 /* binop vAA, vBB, vCC */ 4241 FETCH(r0, 1) @ r0<- CCBB 4242 mov r9, rINST, lsr #8 @ r9<- AA 4243 mov r3, r0, lsr #8 @ r3<- CC 4244 and r2, r0, #255 @ r2<- BB 4245 GET_VREG(r1, r3) @ r1<- vCC 4246 GET_VREG(r0, r2) @ r0<- vBB 4247 .if 0 4248 cmp r1, #0 @ is second operand zero? 4249 beq common_errDivideByZero 4250 .endif 4251 4252 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4253 @ optional op; may set condition codes 4254 and r0, r0, r1 @ r0<- op, r0-r3 changed 4255 GET_INST_OPCODE(ip) @ extract opcode from rINST 4256 SET_VREG(r0, r9) @ vAA<- r0 4257 GOTO_OPCODE(ip) @ jump to next instruction 4258 /* 11-14 instructions */ 4259 4260 4261/* ------------------------------ */ 4262 .balign 64 4263.L_OP_OR_INT: /* 0x96 */ 4264/* File: armv5te/OP_OR_INT.S */ 4265/* File: armv5te/binop.S */ 4266 /* 4267 * Generic 32-bit binary operation. Provide an "instr" line that 4268 * specifies an instruction that performs "result = r0 op r1". 4269 * This could be an ARM instruction or a function call. (If the result 4270 * comes back in a register other than r0, you can override "result".) 4271 * 4272 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4273 * vCC (r1). Useful for integer division and modulus. Note that we 4274 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4275 * handles it correctly. 4276 * 4277 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4278 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4279 * mul-float, div-float, rem-float 4280 */ 4281 /* binop vAA, vBB, vCC */ 4282 FETCH(r0, 1) @ r0<- CCBB 4283 mov r9, rINST, lsr #8 @ r9<- AA 4284 mov r3, r0, lsr #8 @ r3<- CC 4285 and r2, r0, #255 @ r2<- BB 4286 GET_VREG(r1, r3) @ r1<- vCC 4287 GET_VREG(r0, r2) @ r0<- vBB 4288 .if 0 4289 cmp r1, #0 @ is second operand zero? 4290 beq common_errDivideByZero 4291 .endif 4292 4293 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4294 @ optional op; may set condition codes 4295 orr r0, r0, r1 @ r0<- op, r0-r3 changed 4296 GET_INST_OPCODE(ip) @ extract opcode from rINST 4297 SET_VREG(r0, r9) @ vAA<- r0 4298 GOTO_OPCODE(ip) @ jump to next instruction 4299 /* 11-14 instructions */ 4300 4301 4302/* ------------------------------ */ 4303 .balign 64 4304.L_OP_XOR_INT: /* 0x97 */ 4305/* File: armv5te/OP_XOR_INT.S */ 4306/* File: armv5te/binop.S */ 4307 /* 4308 * Generic 32-bit binary operation. Provide an "instr" line that 4309 * specifies an instruction that performs "result = r0 op r1". 4310 * This could be an ARM instruction or a function call. (If the result 4311 * comes back in a register other than r0, you can override "result".) 4312 * 4313 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4314 * vCC (r1). Useful for integer division and modulus. Note that we 4315 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4316 * handles it correctly. 4317 * 4318 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4319 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4320 * mul-float, div-float, rem-float 4321 */ 4322 /* binop vAA, vBB, vCC */ 4323 FETCH(r0, 1) @ r0<- CCBB 4324 mov r9, rINST, lsr #8 @ r9<- AA 4325 mov r3, r0, lsr #8 @ r3<- CC 4326 and r2, r0, #255 @ r2<- BB 4327 GET_VREG(r1, r3) @ r1<- vCC 4328 GET_VREG(r0, r2) @ r0<- vBB 4329 .if 0 4330 cmp r1, #0 @ is second operand zero? 4331 beq common_errDivideByZero 4332 .endif 4333 4334 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4335 @ optional op; may set condition codes 4336 eor r0, r0, r1 @ r0<- op, r0-r3 changed 4337 GET_INST_OPCODE(ip) @ extract opcode from rINST 4338 SET_VREG(r0, r9) @ vAA<- r0 4339 GOTO_OPCODE(ip) @ jump to next instruction 4340 /* 11-14 instructions */ 4341 4342 4343/* ------------------------------ */ 4344 .balign 64 4345.L_OP_SHL_INT: /* 0x98 */ 4346/* File: armv5te/OP_SHL_INT.S */ 4347/* File: armv5te/binop.S */ 4348 /* 4349 * Generic 32-bit binary operation. Provide an "instr" line that 4350 * specifies an instruction that performs "result = r0 op r1". 4351 * This could be an ARM instruction or a function call. (If the result 4352 * comes back in a register other than r0, you can override "result".) 4353 * 4354 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4355 * vCC (r1). Useful for integer division and modulus. Note that we 4356 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4357 * handles it correctly. 4358 * 4359 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4360 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4361 * mul-float, div-float, rem-float 4362 */ 4363 /* binop vAA, vBB, vCC */ 4364 FETCH(r0, 1) @ r0<- CCBB 4365 mov r9, rINST, lsr #8 @ r9<- AA 4366 mov r3, r0, lsr #8 @ r3<- CC 4367 and r2, r0, #255 @ r2<- BB 4368 GET_VREG(r1, r3) @ r1<- vCC 4369 GET_VREG(r0, r2) @ r0<- vBB 4370 .if 0 4371 cmp r1, #0 @ is second operand zero? 4372 beq common_errDivideByZero 4373 .endif 4374 4375 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4376 and r1, r1, #31 @ optional op; may set condition codes 4377 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4378 GET_INST_OPCODE(ip) @ extract opcode from rINST 4379 SET_VREG(r0, r9) @ vAA<- r0 4380 GOTO_OPCODE(ip) @ jump to next instruction 4381 /* 11-14 instructions */ 4382 4383 4384/* ------------------------------ */ 4385 .balign 64 4386.L_OP_SHR_INT: /* 0x99 */ 4387/* File: armv5te/OP_SHR_INT.S */ 4388/* File: armv5te/binop.S */ 4389 /* 4390 * Generic 32-bit binary operation. Provide an "instr" line that 4391 * specifies an instruction that performs "result = r0 op r1". 4392 * This could be an ARM instruction or a function call. (If the result 4393 * comes back in a register other than r0, you can override "result".) 4394 * 4395 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4396 * vCC (r1). Useful for integer division and modulus. Note that we 4397 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4398 * handles it correctly. 4399 * 4400 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4401 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4402 * mul-float, div-float, rem-float 4403 */ 4404 /* binop vAA, vBB, vCC */ 4405 FETCH(r0, 1) @ r0<- CCBB 4406 mov r9, rINST, lsr #8 @ r9<- AA 4407 mov r3, r0, lsr #8 @ r3<- CC 4408 and r2, r0, #255 @ r2<- BB 4409 GET_VREG(r1, r3) @ r1<- vCC 4410 GET_VREG(r0, r2) @ r0<- vBB 4411 .if 0 4412 cmp r1, #0 @ is second operand zero? 4413 beq common_errDivideByZero 4414 .endif 4415 4416 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4417 and r1, r1, #31 @ optional op; may set condition codes 4418 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4419 GET_INST_OPCODE(ip) @ extract opcode from rINST 4420 SET_VREG(r0, r9) @ vAA<- r0 4421 GOTO_OPCODE(ip) @ jump to next instruction 4422 /* 11-14 instructions */ 4423 4424 4425/* ------------------------------ */ 4426 .balign 64 4427.L_OP_USHR_INT: /* 0x9a */ 4428/* File: armv5te/OP_USHR_INT.S */ 4429/* File: armv5te/binop.S */ 4430 /* 4431 * Generic 32-bit binary operation. Provide an "instr" line that 4432 * specifies an instruction that performs "result = r0 op r1". 4433 * This could be an ARM instruction or a function call. (If the result 4434 * comes back in a register other than r0, you can override "result".) 4435 * 4436 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4437 * vCC (r1). Useful for integer division and modulus. Note that we 4438 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4439 * handles it correctly. 4440 * 4441 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4442 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4443 * mul-float, div-float, rem-float 4444 */ 4445 /* binop vAA, vBB, vCC */ 4446 FETCH(r0, 1) @ r0<- CCBB 4447 mov r9, rINST, lsr #8 @ r9<- AA 4448 mov r3, r0, lsr #8 @ r3<- CC 4449 and r2, r0, #255 @ r2<- BB 4450 GET_VREG(r1, r3) @ r1<- vCC 4451 GET_VREG(r0, r2) @ r0<- vBB 4452 .if 0 4453 cmp r1, #0 @ is second operand zero? 4454 beq common_errDivideByZero 4455 .endif 4456 4457 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4458 and r1, r1, #31 @ optional op; may set condition codes 4459 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4460 GET_INST_OPCODE(ip) @ extract opcode from rINST 4461 SET_VREG(r0, r9) @ vAA<- r0 4462 GOTO_OPCODE(ip) @ jump to next instruction 4463 /* 11-14 instructions */ 4464 4465 4466/* ------------------------------ */ 4467 .balign 64 4468.L_OP_ADD_LONG: /* 0x9b */ 4469/* File: armv5te/OP_ADD_LONG.S */ 4470/* File: armv5te/binopWide.S */ 4471 /* 4472 * Generic 64-bit binary operation. Provide an "instr" line that 4473 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4474 * This could be an ARM instruction or a function call. (If the result 4475 * comes back in a register other than r0, you can override "result".) 4476 * 4477 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4478 * vCC (r1). Useful for integer division and modulus. 4479 * 4480 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4481 * xor-long, add-double, sub-double, mul-double, div-double, 4482 * rem-double 4483 * 4484 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4485 */ 4486 /* binop vAA, vBB, vCC */ 4487 FETCH(r0, 1) @ r0<- CCBB 4488 mov r9, rINST, lsr #8 @ r9<- AA 4489 and r2, r0, #255 @ r2<- BB 4490 mov r3, r0, lsr #8 @ r3<- CC 4491 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4492 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4493 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4494 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4495 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4496 .if 0 4497 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4498 beq common_errDivideByZero 4499 .endif 4500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4501 4502 adds r0, r0, r2 @ optional op; may set condition codes 4503 adc r1, r1, r3 @ result<- op, r0-r3 changed 4504 GET_INST_OPCODE(ip) @ extract opcode from rINST 4505 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4506 GOTO_OPCODE(ip) @ jump to next instruction 4507 /* 14-17 instructions */ 4508 4509 4510/* ------------------------------ */ 4511 .balign 64 4512.L_OP_SUB_LONG: /* 0x9c */ 4513/* File: armv5te/OP_SUB_LONG.S */ 4514/* File: armv5te/binopWide.S */ 4515 /* 4516 * Generic 64-bit binary operation. Provide an "instr" line that 4517 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4518 * This could be an ARM instruction or a function call. (If the result 4519 * comes back in a register other than r0, you can override "result".) 4520 * 4521 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4522 * vCC (r1). Useful for integer division and modulus. 4523 * 4524 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4525 * xor-long, add-double, sub-double, mul-double, div-double, 4526 * rem-double 4527 * 4528 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4529 */ 4530 /* binop vAA, vBB, vCC */ 4531 FETCH(r0, 1) @ r0<- CCBB 4532 mov r9, rINST, lsr #8 @ r9<- AA 4533 and r2, r0, #255 @ r2<- BB 4534 mov r3, r0, lsr #8 @ r3<- CC 4535 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4536 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4537 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4538 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4539 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4540 .if 0 4541 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4542 beq common_errDivideByZero 4543 .endif 4544 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4545 4546 subs r0, r0, r2 @ optional op; may set condition codes 4547 sbc r1, r1, r3 @ result<- op, r0-r3 changed 4548 GET_INST_OPCODE(ip) @ extract opcode from rINST 4549 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4550 GOTO_OPCODE(ip) @ jump to next instruction 4551 /* 14-17 instructions */ 4552 4553 4554/* ------------------------------ */ 4555 .balign 64 4556.L_OP_MUL_LONG: /* 0x9d */ 4557/* File: armv5te/OP_MUL_LONG.S */ 4558 /* 4559 * Signed 64-bit integer multiply. 4560 * 4561 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4562 * WX 4563 * x YZ 4564 * -------- 4565 * ZW ZX 4566 * YW YX 4567 * 4568 * The low word of the result holds ZX, the high word holds 4569 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4570 * it doesn't fit in the low 64 bits. 4571 * 4572 * Unlike most ARM math operations, multiply instructions have 4573 * restrictions on using the same register more than once (Rd and Rm 4574 * cannot be the same). 4575 */ 4576 /* mul-long vAA, vBB, vCC */ 4577 FETCH(r0, 1) @ r0<- CCBB 4578 and r2, r0, #255 @ r2<- BB 4579 mov r3, r0, lsr #8 @ r3<- CC 4580 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4581 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4582 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4583 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4584 mul ip, r2, r1 @ ip<- ZxW 4585 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4586 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4587 mov r0, rINST, lsr #8 @ r0<- AA 4588 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4589 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4590 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4591 b .LOP_MUL_LONG_finish 4592 4593/* ------------------------------ */ 4594 .balign 64 4595.L_OP_DIV_LONG: /* 0x9e */ 4596/* File: armv5te/OP_DIV_LONG.S */ 4597/* File: armv5te/binopWide.S */ 4598 /* 4599 * Generic 64-bit binary operation. Provide an "instr" line that 4600 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4601 * This could be an ARM instruction or a function call. (If the result 4602 * comes back in a register other than r0, you can override "result".) 4603 * 4604 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4605 * vCC (r1). Useful for integer division and modulus. 4606 * 4607 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4608 * xor-long, add-double, sub-double, mul-double, div-double, 4609 * rem-double 4610 * 4611 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4612 */ 4613 /* binop vAA, vBB, vCC */ 4614 FETCH(r0, 1) @ r0<- CCBB 4615 mov r9, rINST, lsr #8 @ r9<- AA 4616 and r2, r0, #255 @ r2<- BB 4617 mov r3, r0, lsr #8 @ r3<- CC 4618 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4619 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4620 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4621 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4622 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4623 .if 1 4624 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4625 beq common_errDivideByZero 4626 .endif 4627 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4628 4629 @ optional op; may set condition codes 4630 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4631 GET_INST_OPCODE(ip) @ extract opcode from rINST 4632 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4633 GOTO_OPCODE(ip) @ jump to next instruction 4634 /* 14-17 instructions */ 4635 4636 4637/* ------------------------------ */ 4638 .balign 64 4639.L_OP_REM_LONG: /* 0x9f */ 4640/* File: armv5te/OP_REM_LONG.S */ 4641/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4642/* File: armv5te/binopWide.S */ 4643 /* 4644 * Generic 64-bit binary operation. Provide an "instr" line that 4645 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4646 * This could be an ARM instruction or a function call. (If the result 4647 * comes back in a register other than r0, you can override "result".) 4648 * 4649 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4650 * vCC (r1). Useful for integer division and modulus. 4651 * 4652 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4653 * xor-long, add-double, sub-double, mul-double, div-double, 4654 * rem-double 4655 * 4656 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4657 */ 4658 /* binop vAA, vBB, vCC */ 4659 FETCH(r0, 1) @ r0<- CCBB 4660 mov r9, rINST, lsr #8 @ r9<- AA 4661 and r2, r0, #255 @ r2<- BB 4662 mov r3, r0, lsr #8 @ r3<- CC 4663 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4664 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4665 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4666 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4667 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4668 .if 1 4669 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4670 beq common_errDivideByZero 4671 .endif 4672 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4673 4674 @ optional op; may set condition codes 4675 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4676 GET_INST_OPCODE(ip) @ extract opcode from rINST 4677 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4678 GOTO_OPCODE(ip) @ jump to next instruction 4679 /* 14-17 instructions */ 4680 4681 4682/* ------------------------------ */ 4683 .balign 64 4684.L_OP_AND_LONG: /* 0xa0 */ 4685/* File: armv5te/OP_AND_LONG.S */ 4686/* File: armv5te/binopWide.S */ 4687 /* 4688 * Generic 64-bit binary operation. Provide an "instr" line that 4689 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4690 * This could be an ARM instruction or a function call. (If the result 4691 * comes back in a register other than r0, you can override "result".) 4692 * 4693 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4694 * vCC (r1). Useful for integer division and modulus. 4695 * 4696 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4697 * xor-long, add-double, sub-double, mul-double, div-double, 4698 * rem-double 4699 * 4700 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4701 */ 4702 /* binop vAA, vBB, vCC */ 4703 FETCH(r0, 1) @ r0<- CCBB 4704 mov r9, rINST, lsr #8 @ r9<- AA 4705 and r2, r0, #255 @ r2<- BB 4706 mov r3, r0, lsr #8 @ r3<- CC 4707 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4708 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4709 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4710 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4711 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4712 .if 0 4713 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4714 beq common_errDivideByZero 4715 .endif 4716 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4717 4718 and r0, r0, r2 @ optional op; may set condition codes 4719 and r1, r1, r3 @ result<- op, r0-r3 changed 4720 GET_INST_OPCODE(ip) @ extract opcode from rINST 4721 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4722 GOTO_OPCODE(ip) @ jump to next instruction 4723 /* 14-17 instructions */ 4724 4725 4726/* ------------------------------ */ 4727 .balign 64 4728.L_OP_OR_LONG: /* 0xa1 */ 4729/* File: armv5te/OP_OR_LONG.S */ 4730/* File: armv5te/binopWide.S */ 4731 /* 4732 * Generic 64-bit binary operation. Provide an "instr" line that 4733 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4734 * This could be an ARM instruction or a function call. (If the result 4735 * comes back in a register other than r0, you can override "result".) 4736 * 4737 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4738 * vCC (r1). Useful for integer division and modulus. 4739 * 4740 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4741 * xor-long, add-double, sub-double, mul-double, div-double, 4742 * rem-double 4743 * 4744 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4745 */ 4746 /* binop vAA, vBB, vCC */ 4747 FETCH(r0, 1) @ r0<- CCBB 4748 mov r9, rINST, lsr #8 @ r9<- AA 4749 and r2, r0, #255 @ r2<- BB 4750 mov r3, r0, lsr #8 @ r3<- CC 4751 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4752 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4753 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4754 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4755 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4756 .if 0 4757 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4758 beq common_errDivideByZero 4759 .endif 4760 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4761 4762 orr r0, r0, r2 @ optional op; may set condition codes 4763 orr r1, r1, r3 @ result<- op, r0-r3 changed 4764 GET_INST_OPCODE(ip) @ extract opcode from rINST 4765 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4766 GOTO_OPCODE(ip) @ jump to next instruction 4767 /* 14-17 instructions */ 4768 4769 4770/* ------------------------------ */ 4771 .balign 64 4772.L_OP_XOR_LONG: /* 0xa2 */ 4773/* File: armv5te/OP_XOR_LONG.S */ 4774/* File: armv5te/binopWide.S */ 4775 /* 4776 * Generic 64-bit binary operation. Provide an "instr" line that 4777 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4778 * This could be an ARM instruction or a function call. (If the result 4779 * comes back in a register other than r0, you can override "result".) 4780 * 4781 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4782 * vCC (r1). Useful for integer division and modulus. 4783 * 4784 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4785 * xor-long, add-double, sub-double, mul-double, div-double, 4786 * rem-double 4787 * 4788 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4789 */ 4790 /* binop vAA, vBB, vCC */ 4791 FETCH(r0, 1) @ r0<- CCBB 4792 mov r9, rINST, lsr #8 @ r9<- AA 4793 and r2, r0, #255 @ r2<- BB 4794 mov r3, r0, lsr #8 @ r3<- CC 4795 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4796 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4797 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4798 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4799 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4800 .if 0 4801 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4802 beq common_errDivideByZero 4803 .endif 4804 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4805 4806 eor r0, r0, r2 @ optional op; may set condition codes 4807 eor r1, r1, r3 @ result<- op, r0-r3 changed 4808 GET_INST_OPCODE(ip) @ extract opcode from rINST 4809 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4810 GOTO_OPCODE(ip) @ jump to next instruction 4811 /* 14-17 instructions */ 4812 4813 4814/* ------------------------------ */ 4815 .balign 64 4816.L_OP_SHL_LONG: /* 0xa3 */ 4817/* File: armv5te/OP_SHL_LONG.S */ 4818 /* 4819 * Long integer shift. This is different from the generic 32/64-bit 4820 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4821 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4822 * 6 bits of the shift distance. 4823 */ 4824 /* shl-long vAA, vBB, vCC */ 4825 FETCH(r0, 1) @ r0<- CCBB 4826 mov r9, rINST, lsr #8 @ r9<- AA 4827 and r3, r0, #255 @ r3<- BB 4828 mov r0, r0, lsr #8 @ r0<- CC 4829 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4830 GET_VREG(r2, r0) @ r2<- vCC 4831 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4832 and r2, r2, #63 @ r2<- r2 & 0x3f 4833 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4834 4835 mov r1, r1, asl r2 @ r1<- r1 << r2 4836 rsb r3, r2, #32 @ r3<- 32 - r2 4837 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4838 subs ip, r2, #32 @ ip<- r2 - 32 4839 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4840 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4841 b .LOP_SHL_LONG_finish 4842 4843/* ------------------------------ */ 4844 .balign 64 4845.L_OP_SHR_LONG: /* 0xa4 */ 4846/* File: armv5te/OP_SHR_LONG.S */ 4847 /* 4848 * Long integer shift. This is different from the generic 32/64-bit 4849 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4850 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4851 * 6 bits of the shift distance. 4852 */ 4853 /* shr-long vAA, vBB, vCC */ 4854 FETCH(r0, 1) @ r0<- CCBB 4855 mov r9, rINST, lsr #8 @ r9<- AA 4856 and r3, r0, #255 @ r3<- BB 4857 mov r0, r0, lsr #8 @ r0<- CC 4858 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4859 GET_VREG(r2, r0) @ r2<- vCC 4860 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4861 and r2, r2, #63 @ r0<- r0 & 0x3f 4862 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4863 4864 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4865 rsb r3, r2, #32 @ r3<- 32 - r2 4866 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4867 subs ip, r2, #32 @ ip<- r2 - 32 4868 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4869 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4870 b .LOP_SHR_LONG_finish 4871 4872/* ------------------------------ */ 4873 .balign 64 4874.L_OP_USHR_LONG: /* 0xa5 */ 4875/* File: armv5te/OP_USHR_LONG.S */ 4876 /* 4877 * Long integer shift. This is different from the generic 32/64-bit 4878 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4879 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4880 * 6 bits of the shift distance. 4881 */ 4882 /* ushr-long vAA, vBB, vCC */ 4883 FETCH(r0, 1) @ r0<- CCBB 4884 mov r9, rINST, lsr #8 @ r9<- AA 4885 and r3, r0, #255 @ r3<- BB 4886 mov r0, r0, lsr #8 @ r0<- CC 4887 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4888 GET_VREG(r2, r0) @ r2<- vCC 4889 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4890 and r2, r2, #63 @ r0<- r0 & 0x3f 4891 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4892 4893 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4894 rsb r3, r2, #32 @ r3<- 32 - r2 4895 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4896 subs ip, r2, #32 @ ip<- r2 - 32 4897 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4898 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4899 b .LOP_USHR_LONG_finish 4900 4901/* ------------------------------ */ 4902 .balign 64 4903.L_OP_ADD_FLOAT: /* 0xa6 */ 4904/* File: arm-vfp/OP_ADD_FLOAT.S */ 4905/* File: arm-vfp/fbinop.S */ 4906 /* 4907 * Generic 32-bit floating-point operation. Provide an "instr" line that 4908 * specifies an instruction that performs "s2 = s0 op s1". Because we 4909 * use the "softfp" ABI, this must be an instruction, not a function call. 4910 * 4911 * For: add-float, sub-float, mul-float, div-float 4912 */ 4913 /* floatop vAA, vBB, vCC */ 4914 FETCH(r0, 1) @ r0<- CCBB 4915 mov r9, rINST, lsr #8 @ r9<- AA 4916 mov r3, r0, lsr #8 @ r3<- CC 4917 and r2, r0, #255 @ r2<- BB 4918 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4919 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4920 flds s1, [r3] @ s1<- vCC 4921 flds s0, [r2] @ s0<- vBB 4922 4923 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4924 fadds s2, s0, s1 @ s2<- op 4925 GET_INST_OPCODE(ip) @ extract opcode from rINST 4926 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4927 fsts s2, [r9] @ vAA<- s2 4928 GOTO_OPCODE(ip) @ jump to next instruction 4929 4930 4931/* ------------------------------ */ 4932 .balign 64 4933.L_OP_SUB_FLOAT: /* 0xa7 */ 4934/* File: arm-vfp/OP_SUB_FLOAT.S */ 4935/* File: arm-vfp/fbinop.S */ 4936 /* 4937 * Generic 32-bit floating-point operation. Provide an "instr" line that 4938 * specifies an instruction that performs "s2 = s0 op s1". Because we 4939 * use the "softfp" ABI, this must be an instruction, not a function call. 4940 * 4941 * For: add-float, sub-float, mul-float, div-float 4942 */ 4943 /* floatop vAA, vBB, vCC */ 4944 FETCH(r0, 1) @ r0<- CCBB 4945 mov r9, rINST, lsr #8 @ r9<- AA 4946 mov r3, r0, lsr #8 @ r3<- CC 4947 and r2, r0, #255 @ r2<- BB 4948 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4949 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4950 flds s1, [r3] @ s1<- vCC 4951 flds s0, [r2] @ s0<- vBB 4952 4953 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4954 fsubs s2, s0, s1 @ s2<- op 4955 GET_INST_OPCODE(ip) @ extract opcode from rINST 4956 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4957 fsts s2, [r9] @ vAA<- s2 4958 GOTO_OPCODE(ip) @ jump to next instruction 4959 4960 4961/* ------------------------------ */ 4962 .balign 64 4963.L_OP_MUL_FLOAT: /* 0xa8 */ 4964/* File: arm-vfp/OP_MUL_FLOAT.S */ 4965/* File: arm-vfp/fbinop.S */ 4966 /* 4967 * Generic 32-bit floating-point operation. Provide an "instr" line that 4968 * specifies an instruction that performs "s2 = s0 op s1". Because we 4969 * use the "softfp" ABI, this must be an instruction, not a function call. 4970 * 4971 * For: add-float, sub-float, mul-float, div-float 4972 */ 4973 /* floatop vAA, vBB, vCC */ 4974 FETCH(r0, 1) @ r0<- CCBB 4975 mov r9, rINST, lsr #8 @ r9<- AA 4976 mov r3, r0, lsr #8 @ r3<- CC 4977 and r2, r0, #255 @ r2<- BB 4978 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4979 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4980 flds s1, [r3] @ s1<- vCC 4981 flds s0, [r2] @ s0<- vBB 4982 4983 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4984 fmuls s2, s0, s1 @ s2<- op 4985 GET_INST_OPCODE(ip) @ extract opcode from rINST 4986 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4987 fsts s2, [r9] @ vAA<- s2 4988 GOTO_OPCODE(ip) @ jump to next instruction 4989 4990 4991/* ------------------------------ */ 4992 .balign 64 4993.L_OP_DIV_FLOAT: /* 0xa9 */ 4994/* File: arm-vfp/OP_DIV_FLOAT.S */ 4995/* File: arm-vfp/fbinop.S */ 4996 /* 4997 * Generic 32-bit floating-point operation. Provide an "instr" line that 4998 * specifies an instruction that performs "s2 = s0 op s1". Because we 4999 * use the "softfp" ABI, this must be an instruction, not a function call. 5000 * 5001 * For: add-float, sub-float, mul-float, div-float 5002 */ 5003 /* floatop vAA, vBB, vCC */ 5004 FETCH(r0, 1) @ r0<- CCBB 5005 mov r9, rINST, lsr #8 @ r9<- AA 5006 mov r3, r0, lsr #8 @ r3<- CC 5007 and r2, r0, #255 @ r2<- BB 5008 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5009 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5010 flds s1, [r3] @ s1<- vCC 5011 flds s0, [r2] @ s0<- vBB 5012 5013 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5014 fdivs s2, s0, s1 @ s2<- op 5015 GET_INST_OPCODE(ip) @ extract opcode from rINST 5016 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5017 fsts s2, [r9] @ vAA<- s2 5018 GOTO_OPCODE(ip) @ jump to next instruction 5019 5020 5021/* ------------------------------ */ 5022 .balign 64 5023.L_OP_REM_FLOAT: /* 0xaa */ 5024/* File: armv5te/OP_REM_FLOAT.S */ 5025/* EABI doesn't define a float remainder function, but libm does */ 5026/* File: armv5te/binop.S */ 5027 /* 5028 * Generic 32-bit binary operation. Provide an "instr" line that 5029 * specifies an instruction that performs "result = r0 op r1". 5030 * This could be an ARM instruction or a function call. (If the result 5031 * comes back in a register other than r0, you can override "result".) 5032 * 5033 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5034 * vCC (r1). Useful for integer division and modulus. Note that we 5035 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5036 * handles it correctly. 5037 * 5038 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5039 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5040 * mul-float, div-float, rem-float 5041 */ 5042 /* binop vAA, vBB, vCC */ 5043 FETCH(r0, 1) @ r0<- CCBB 5044 mov r9, rINST, lsr #8 @ r9<- AA 5045 mov r3, r0, lsr #8 @ r3<- CC 5046 and r2, r0, #255 @ r2<- BB 5047 GET_VREG(r1, r3) @ r1<- vCC 5048 GET_VREG(r0, r2) @ r0<- vBB 5049 .if 0 5050 cmp r1, #0 @ is second operand zero? 5051 beq common_errDivideByZero 5052 .endif 5053 5054 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5055 @ optional op; may set condition codes 5056 bl fmodf @ r0<- op, r0-r3 changed 5057 GET_INST_OPCODE(ip) @ extract opcode from rINST 5058 SET_VREG(r0, r9) @ vAA<- r0 5059 GOTO_OPCODE(ip) @ jump to next instruction 5060 /* 11-14 instructions */ 5061 5062 5063/* ------------------------------ */ 5064 .balign 64 5065.L_OP_ADD_DOUBLE: /* 0xab */ 5066/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5067/* File: arm-vfp/fbinopWide.S */ 5068 /* 5069 * Generic 64-bit double-precision floating point binary operation. 5070 * Provide an "instr" line that specifies an instruction that performs 5071 * "d2 = d0 op d1". 5072 * 5073 * for: add-double, sub-double, mul-double, div-double 5074 */ 5075 /* doubleop vAA, vBB, vCC */ 5076 FETCH(r0, 1) @ r0<- CCBB 5077 mov r9, rINST, lsr #8 @ r9<- AA 5078 mov r3, r0, lsr #8 @ r3<- CC 5079 and r2, r0, #255 @ r2<- BB 5080 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5081 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5082 fldd d1, [r3] @ d1<- vCC 5083 fldd d0, [r2] @ d0<- vBB 5084 5085 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5086 faddd d2, d0, d1 @ s2<- op 5087 GET_INST_OPCODE(ip) @ extract opcode from rINST 5088 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5089 fstd d2, [r9] @ vAA<- d2 5090 GOTO_OPCODE(ip) @ jump to next instruction 5091 5092 5093/* ------------------------------ */ 5094 .balign 64 5095.L_OP_SUB_DOUBLE: /* 0xac */ 5096/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5097/* File: arm-vfp/fbinopWide.S */ 5098 /* 5099 * Generic 64-bit double-precision floating point binary operation. 5100 * Provide an "instr" line that specifies an instruction that performs 5101 * "d2 = d0 op d1". 5102 * 5103 * for: add-double, sub-double, mul-double, div-double 5104 */ 5105 /* doubleop vAA, vBB, vCC */ 5106 FETCH(r0, 1) @ r0<- CCBB 5107 mov r9, rINST, lsr #8 @ r9<- AA 5108 mov r3, r0, lsr #8 @ r3<- CC 5109 and r2, r0, #255 @ r2<- BB 5110 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5111 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5112 fldd d1, [r3] @ d1<- vCC 5113 fldd d0, [r2] @ d0<- vBB 5114 5115 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5116 fsubd d2, d0, d1 @ s2<- op 5117 GET_INST_OPCODE(ip) @ extract opcode from rINST 5118 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5119 fstd d2, [r9] @ vAA<- d2 5120 GOTO_OPCODE(ip) @ jump to next instruction 5121 5122 5123/* ------------------------------ */ 5124 .balign 64 5125.L_OP_MUL_DOUBLE: /* 0xad */ 5126/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5127/* File: arm-vfp/fbinopWide.S */ 5128 /* 5129 * Generic 64-bit double-precision floating point binary operation. 5130 * Provide an "instr" line that specifies an instruction that performs 5131 * "d2 = d0 op d1". 5132 * 5133 * for: add-double, sub-double, mul-double, div-double 5134 */ 5135 /* doubleop vAA, vBB, vCC */ 5136 FETCH(r0, 1) @ r0<- CCBB 5137 mov r9, rINST, lsr #8 @ r9<- AA 5138 mov r3, r0, lsr #8 @ r3<- CC 5139 and r2, r0, #255 @ r2<- BB 5140 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5141 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5142 fldd d1, [r3] @ d1<- vCC 5143 fldd d0, [r2] @ d0<- vBB 5144 5145 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5146 fmuld d2, d0, d1 @ s2<- op 5147 GET_INST_OPCODE(ip) @ extract opcode from rINST 5148 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5149 fstd d2, [r9] @ vAA<- d2 5150 GOTO_OPCODE(ip) @ jump to next instruction 5151 5152 5153/* ------------------------------ */ 5154 .balign 64 5155.L_OP_DIV_DOUBLE: /* 0xae */ 5156/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5157/* File: arm-vfp/fbinopWide.S */ 5158 /* 5159 * Generic 64-bit double-precision floating point binary operation. 5160 * Provide an "instr" line that specifies an instruction that performs 5161 * "d2 = d0 op d1". 5162 * 5163 * for: add-double, sub-double, mul-double, div-double 5164 */ 5165 /* doubleop vAA, vBB, vCC */ 5166 FETCH(r0, 1) @ r0<- CCBB 5167 mov r9, rINST, lsr #8 @ r9<- AA 5168 mov r3, r0, lsr #8 @ r3<- CC 5169 and r2, r0, #255 @ r2<- BB 5170 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5171 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5172 fldd d1, [r3] @ d1<- vCC 5173 fldd d0, [r2] @ d0<- vBB 5174 5175 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5176 fdivd d2, d0, d1 @ s2<- op 5177 GET_INST_OPCODE(ip) @ extract opcode from rINST 5178 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5179 fstd d2, [r9] @ vAA<- d2 5180 GOTO_OPCODE(ip) @ jump to next instruction 5181 5182 5183/* ------------------------------ */ 5184 .balign 64 5185.L_OP_REM_DOUBLE: /* 0xaf */ 5186/* File: armv5te/OP_REM_DOUBLE.S */ 5187/* EABI doesn't define a double remainder function, but libm does */ 5188/* File: armv5te/binopWide.S */ 5189 /* 5190 * Generic 64-bit binary operation. Provide an "instr" line that 5191 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5192 * This could be an ARM instruction or a function call. (If the result 5193 * comes back in a register other than r0, you can override "result".) 5194 * 5195 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5196 * vCC (r1). Useful for integer division and modulus. 5197 * 5198 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5199 * xor-long, add-double, sub-double, mul-double, div-double, 5200 * rem-double 5201 * 5202 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5203 */ 5204 /* binop vAA, vBB, vCC */ 5205 FETCH(r0, 1) @ r0<- CCBB 5206 mov r9, rINST, lsr #8 @ r9<- AA 5207 and r2, r0, #255 @ r2<- BB 5208 mov r3, r0, lsr #8 @ r3<- CC 5209 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5210 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5211 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5212 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5213 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5214 .if 0 5215 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5216 beq common_errDivideByZero 5217 .endif 5218 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5219 5220 @ optional op; may set condition codes 5221 bl fmod @ result<- op, r0-r3 changed 5222 GET_INST_OPCODE(ip) @ extract opcode from rINST 5223 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5224 GOTO_OPCODE(ip) @ jump to next instruction 5225 /* 14-17 instructions */ 5226 5227 5228/* ------------------------------ */ 5229 .balign 64 5230.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5231/* File: armv5te/OP_ADD_INT_2ADDR.S */ 5232/* File: armv5te/binop2addr.S */ 5233 /* 5234 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5235 * that specifies an instruction that performs "result = r0 op r1". 5236 * This could be an ARM instruction or a function call. (If the result 5237 * comes back in a register other than r0, you can override "result".) 5238 * 5239 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5240 * vCC (r1). Useful for integer division and modulus. 5241 * 5242 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5243 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5244 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5245 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5246 */ 5247 /* binop/2addr vA, vB */ 5248 mov r9, rINST, lsr #8 @ r9<- A+ 5249 mov r3, rINST, lsr #12 @ r3<- B 5250 and r9, r9, #15 5251 GET_VREG(r1, r3) @ r1<- vB 5252 GET_VREG(r0, r9) @ r0<- vA 5253 .if 0 5254 cmp r1, #0 @ is second operand zero? 5255 beq common_errDivideByZero 5256 .endif 5257 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5258 5259 @ optional op; may set condition codes 5260 add r0, r0, r1 @ r0<- op, r0-r3 changed 5261 GET_INST_OPCODE(ip) @ extract opcode from rINST 5262 SET_VREG(r0, r9) @ vAA<- r0 5263 GOTO_OPCODE(ip) @ jump to next instruction 5264 /* 10-13 instructions */ 5265 5266 5267/* ------------------------------ */ 5268 .balign 64 5269.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5270/* File: armv5te/OP_SUB_INT_2ADDR.S */ 5271/* File: armv5te/binop2addr.S */ 5272 /* 5273 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5274 * that specifies an instruction that performs "result = r0 op r1". 5275 * This could be an ARM instruction or a function call. (If the result 5276 * comes back in a register other than r0, you can override "result".) 5277 * 5278 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5279 * vCC (r1). Useful for integer division and modulus. 5280 * 5281 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5282 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5283 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5284 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5285 */ 5286 /* binop/2addr vA, vB */ 5287 mov r9, rINST, lsr #8 @ r9<- A+ 5288 mov r3, rINST, lsr #12 @ r3<- B 5289 and r9, r9, #15 5290 GET_VREG(r1, r3) @ r1<- vB 5291 GET_VREG(r0, r9) @ r0<- vA 5292 .if 0 5293 cmp r1, #0 @ is second operand zero? 5294 beq common_errDivideByZero 5295 .endif 5296 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5297 5298 @ optional op; may set condition codes 5299 sub r0, r0, r1 @ r0<- op, r0-r3 changed 5300 GET_INST_OPCODE(ip) @ extract opcode from rINST 5301 SET_VREG(r0, r9) @ vAA<- r0 5302 GOTO_OPCODE(ip) @ jump to next instruction 5303 /* 10-13 instructions */ 5304 5305 5306/* ------------------------------ */ 5307 .balign 64 5308.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5309/* File: armv5te/OP_MUL_INT_2ADDR.S */ 5310/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5311/* File: armv5te/binop2addr.S */ 5312 /* 5313 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5314 * that specifies an instruction that performs "result = r0 op r1". 5315 * This could be an ARM instruction or a function call. (If the result 5316 * comes back in a register other than r0, you can override "result".) 5317 * 5318 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5319 * vCC (r1). Useful for integer division and modulus. 5320 * 5321 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5322 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5323 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5324 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5325 */ 5326 /* binop/2addr vA, vB */ 5327 mov r9, rINST, lsr #8 @ r9<- A+ 5328 mov r3, rINST, lsr #12 @ r3<- B 5329 and r9, r9, #15 5330 GET_VREG(r1, r3) @ r1<- vB 5331 GET_VREG(r0, r9) @ r0<- vA 5332 .if 0 5333 cmp r1, #0 @ is second operand zero? 5334 beq common_errDivideByZero 5335 .endif 5336 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5337 5338 @ optional op; may set condition codes 5339 mul r0, r1, r0 @ r0<- op, r0-r3 changed 5340 GET_INST_OPCODE(ip) @ extract opcode from rINST 5341 SET_VREG(r0, r9) @ vAA<- r0 5342 GOTO_OPCODE(ip) @ jump to next instruction 5343 /* 10-13 instructions */ 5344 5345 5346/* ------------------------------ */ 5347 .balign 64 5348.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5349/* File: armv5te/OP_DIV_INT_2ADDR.S */ 5350/* File: armv5te/binop2addr.S */ 5351 /* 5352 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5353 * that specifies an instruction that performs "result = r0 op r1". 5354 * This could be an ARM instruction or a function call. (If the result 5355 * comes back in a register other than r0, you can override "result".) 5356 * 5357 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5358 * vCC (r1). Useful for integer division and modulus. 5359 * 5360 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5361 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5362 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5363 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5364 */ 5365 /* binop/2addr vA, vB */ 5366 mov r9, rINST, lsr #8 @ r9<- A+ 5367 mov r3, rINST, lsr #12 @ r3<- B 5368 and r9, r9, #15 5369 GET_VREG(r1, r3) @ r1<- vB 5370 GET_VREG(r0, r9) @ r0<- vA 5371 .if 1 5372 cmp r1, #0 @ is second operand zero? 5373 beq common_errDivideByZero 5374 .endif 5375 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5376 5377 @ optional op; may set condition codes 5378 bl __aeabi_idiv @ r0<- op, r0-r3 changed 5379 GET_INST_OPCODE(ip) @ extract opcode from rINST 5380 SET_VREG(r0, r9) @ vAA<- r0 5381 GOTO_OPCODE(ip) @ jump to next instruction 5382 /* 10-13 instructions */ 5383 5384 5385/* ------------------------------ */ 5386 .balign 64 5387.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5388/* File: armv5te/OP_REM_INT_2ADDR.S */ 5389/* idivmod returns quotient in r0 and remainder in r1 */ 5390/* File: armv5te/binop2addr.S */ 5391 /* 5392 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5393 * that specifies an instruction that performs "result = r0 op r1". 5394 * This could be an ARM instruction or a function call. (If the result 5395 * comes back in a register other than r0, you can override "result".) 5396 * 5397 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5398 * vCC (r1). Useful for integer division and modulus. 5399 * 5400 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5401 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5402 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5403 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5404 */ 5405 /* binop/2addr vA, vB */ 5406 mov r9, rINST, lsr #8 @ r9<- A+ 5407 mov r3, rINST, lsr #12 @ r3<- B 5408 and r9, r9, #15 5409 GET_VREG(r1, r3) @ r1<- vB 5410 GET_VREG(r0, r9) @ r0<- vA 5411 .if 1 5412 cmp r1, #0 @ is second operand zero? 5413 beq common_errDivideByZero 5414 .endif 5415 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5416 5417 @ optional op; may set condition codes 5418 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5419 GET_INST_OPCODE(ip) @ extract opcode from rINST 5420 SET_VREG(r1, r9) @ vAA<- r1 5421 GOTO_OPCODE(ip) @ jump to next instruction 5422 /* 10-13 instructions */ 5423 5424 5425/* ------------------------------ */ 5426 .balign 64 5427.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5428/* File: armv5te/OP_AND_INT_2ADDR.S */ 5429/* File: armv5te/binop2addr.S */ 5430 /* 5431 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5432 * that specifies an instruction that performs "result = r0 op r1". 5433 * This could be an ARM instruction or a function call. (If the result 5434 * comes back in a register other than r0, you can override "result".) 5435 * 5436 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5437 * vCC (r1). Useful for integer division and modulus. 5438 * 5439 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5440 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5441 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5442 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5443 */ 5444 /* binop/2addr vA, vB */ 5445 mov r9, rINST, lsr #8 @ r9<- A+ 5446 mov r3, rINST, lsr #12 @ r3<- B 5447 and r9, r9, #15 5448 GET_VREG(r1, r3) @ r1<- vB 5449 GET_VREG(r0, r9) @ r0<- vA 5450 .if 0 5451 cmp r1, #0 @ is second operand zero? 5452 beq common_errDivideByZero 5453 .endif 5454 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5455 5456 @ optional op; may set condition codes 5457 and r0, r0, r1 @ r0<- op, r0-r3 changed 5458 GET_INST_OPCODE(ip) @ extract opcode from rINST 5459 SET_VREG(r0, r9) @ vAA<- r0 5460 GOTO_OPCODE(ip) @ jump to next instruction 5461 /* 10-13 instructions */ 5462 5463 5464/* ------------------------------ */ 5465 .balign 64 5466.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5467/* File: armv5te/OP_OR_INT_2ADDR.S */ 5468/* File: armv5te/binop2addr.S */ 5469 /* 5470 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5471 * that specifies an instruction that performs "result = r0 op r1". 5472 * This could be an ARM instruction or a function call. (If the result 5473 * comes back in a register other than r0, you can override "result".) 5474 * 5475 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5476 * vCC (r1). Useful for integer division and modulus. 5477 * 5478 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5479 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5480 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5481 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5482 */ 5483 /* binop/2addr vA, vB */ 5484 mov r9, rINST, lsr #8 @ r9<- A+ 5485 mov r3, rINST, lsr #12 @ r3<- B 5486 and r9, r9, #15 5487 GET_VREG(r1, r3) @ r1<- vB 5488 GET_VREG(r0, r9) @ r0<- vA 5489 .if 0 5490 cmp r1, #0 @ is second operand zero? 5491 beq common_errDivideByZero 5492 .endif 5493 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5494 5495 @ optional op; may set condition codes 5496 orr r0, r0, r1 @ r0<- op, r0-r3 changed 5497 GET_INST_OPCODE(ip) @ extract opcode from rINST 5498 SET_VREG(r0, r9) @ vAA<- r0 5499 GOTO_OPCODE(ip) @ jump to next instruction 5500 /* 10-13 instructions */ 5501 5502 5503/* ------------------------------ */ 5504 .balign 64 5505.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5506/* File: armv5te/OP_XOR_INT_2ADDR.S */ 5507/* File: armv5te/binop2addr.S */ 5508 /* 5509 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5510 * that specifies an instruction that performs "result = r0 op r1". 5511 * This could be an ARM instruction or a function call. (If the result 5512 * comes back in a register other than r0, you can override "result".) 5513 * 5514 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5515 * vCC (r1). Useful for integer division and modulus. 5516 * 5517 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5518 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5519 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5520 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5521 */ 5522 /* binop/2addr vA, vB */ 5523 mov r9, rINST, lsr #8 @ r9<- A+ 5524 mov r3, rINST, lsr #12 @ r3<- B 5525 and r9, r9, #15 5526 GET_VREG(r1, r3) @ r1<- vB 5527 GET_VREG(r0, r9) @ r0<- vA 5528 .if 0 5529 cmp r1, #0 @ is second operand zero? 5530 beq common_errDivideByZero 5531 .endif 5532 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5533 5534 @ optional op; may set condition codes 5535 eor r0, r0, r1 @ r0<- op, r0-r3 changed 5536 GET_INST_OPCODE(ip) @ extract opcode from rINST 5537 SET_VREG(r0, r9) @ vAA<- r0 5538 GOTO_OPCODE(ip) @ jump to next instruction 5539 /* 10-13 instructions */ 5540 5541 5542/* ------------------------------ */ 5543 .balign 64 5544.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5545/* File: armv5te/OP_SHL_INT_2ADDR.S */ 5546/* File: armv5te/binop2addr.S */ 5547 /* 5548 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5549 * that specifies an instruction that performs "result = r0 op r1". 5550 * This could be an ARM instruction or a function call. (If the result 5551 * comes back in a register other than r0, you can override "result".) 5552 * 5553 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5554 * vCC (r1). Useful for integer division and modulus. 5555 * 5556 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5557 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5558 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5559 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5560 */ 5561 /* binop/2addr vA, vB */ 5562 mov r9, rINST, lsr #8 @ r9<- A+ 5563 mov r3, rINST, lsr #12 @ r3<- B 5564 and r9, r9, #15 5565 GET_VREG(r1, r3) @ r1<- vB 5566 GET_VREG(r0, r9) @ r0<- vA 5567 .if 0 5568 cmp r1, #0 @ is second operand zero? 5569 beq common_errDivideByZero 5570 .endif 5571 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5572 5573 and r1, r1, #31 @ optional op; may set condition codes 5574 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5575 GET_INST_OPCODE(ip) @ extract opcode from rINST 5576 SET_VREG(r0, r9) @ vAA<- r0 5577 GOTO_OPCODE(ip) @ jump to next instruction 5578 /* 10-13 instructions */ 5579 5580 5581/* ------------------------------ */ 5582 .balign 64 5583.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5584/* File: armv5te/OP_SHR_INT_2ADDR.S */ 5585/* File: armv5te/binop2addr.S */ 5586 /* 5587 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5588 * that specifies an instruction that performs "result = r0 op r1". 5589 * This could be an ARM instruction or a function call. (If the result 5590 * comes back in a register other than r0, you can override "result".) 5591 * 5592 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5593 * vCC (r1). Useful for integer division and modulus. 5594 * 5595 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5596 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5597 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5598 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5599 */ 5600 /* binop/2addr vA, vB */ 5601 mov r9, rINST, lsr #8 @ r9<- A+ 5602 mov r3, rINST, lsr #12 @ r3<- B 5603 and r9, r9, #15 5604 GET_VREG(r1, r3) @ r1<- vB 5605 GET_VREG(r0, r9) @ r0<- vA 5606 .if 0 5607 cmp r1, #0 @ is second operand zero? 5608 beq common_errDivideByZero 5609 .endif 5610 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5611 5612 and r1, r1, #31 @ optional op; may set condition codes 5613 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5614 GET_INST_OPCODE(ip) @ extract opcode from rINST 5615 SET_VREG(r0, r9) @ vAA<- r0 5616 GOTO_OPCODE(ip) @ jump to next instruction 5617 /* 10-13 instructions */ 5618 5619 5620/* ------------------------------ */ 5621 .balign 64 5622.L_OP_USHR_INT_2ADDR: /* 0xba */ 5623/* File: armv5te/OP_USHR_INT_2ADDR.S */ 5624/* File: armv5te/binop2addr.S */ 5625 /* 5626 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5627 * that specifies an instruction that performs "result = r0 op r1". 5628 * This could be an ARM instruction or a function call. (If the result 5629 * comes back in a register other than r0, you can override "result".) 5630 * 5631 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5632 * vCC (r1). Useful for integer division and modulus. 5633 * 5634 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5635 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5636 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5637 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5638 */ 5639 /* binop/2addr vA, vB */ 5640 mov r9, rINST, lsr #8 @ r9<- A+ 5641 mov r3, rINST, lsr #12 @ r3<- B 5642 and r9, r9, #15 5643 GET_VREG(r1, r3) @ r1<- vB 5644 GET_VREG(r0, r9) @ r0<- vA 5645 .if 0 5646 cmp r1, #0 @ is second operand zero? 5647 beq common_errDivideByZero 5648 .endif 5649 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5650 5651 and r1, r1, #31 @ optional op; may set condition codes 5652 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5653 GET_INST_OPCODE(ip) @ extract opcode from rINST 5654 SET_VREG(r0, r9) @ vAA<- r0 5655 GOTO_OPCODE(ip) @ jump to next instruction 5656 /* 10-13 instructions */ 5657 5658 5659/* ------------------------------ */ 5660 .balign 64 5661.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5662/* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5663/* File: armv5te/binopWide2addr.S */ 5664 /* 5665 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5666 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5667 * This could be an ARM instruction or a function call. (If the result 5668 * comes back in a register other than r0, you can override "result".) 5669 * 5670 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5671 * vCC (r1). Useful for integer division and modulus. 5672 * 5673 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5674 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5675 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5676 * rem-double/2addr 5677 */ 5678 /* binop/2addr vA, vB */ 5679 mov r9, rINST, lsr #8 @ r9<- A+ 5680 mov r1, rINST, lsr #12 @ r1<- B 5681 and r9, r9, #15 5682 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5683 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5684 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5685 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5686 .if 0 5687 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5688 beq common_errDivideByZero 5689 .endif 5690 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5691 5692 adds r0, r0, r2 @ optional op; may set condition codes 5693 adc r1, r1, r3 @ result<- op, r0-r3 changed 5694 GET_INST_OPCODE(ip) @ extract opcode from rINST 5695 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5696 GOTO_OPCODE(ip) @ jump to next instruction 5697 /* 12-15 instructions */ 5698 5699 5700/* ------------------------------ */ 5701 .balign 64 5702.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5703/* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5704/* File: armv5te/binopWide2addr.S */ 5705 /* 5706 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5707 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5708 * This could be an ARM instruction or a function call. (If the result 5709 * comes back in a register other than r0, you can override "result".) 5710 * 5711 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5712 * vCC (r1). Useful for integer division and modulus. 5713 * 5714 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5715 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5716 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5717 * rem-double/2addr 5718 */ 5719 /* binop/2addr vA, vB */ 5720 mov r9, rINST, lsr #8 @ r9<- A+ 5721 mov r1, rINST, lsr #12 @ r1<- B 5722 and r9, r9, #15 5723 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5724 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5725 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5726 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5727 .if 0 5728 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5729 beq common_errDivideByZero 5730 .endif 5731 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5732 5733 subs r0, r0, r2 @ optional op; may set condition codes 5734 sbc r1, r1, r3 @ result<- op, r0-r3 changed 5735 GET_INST_OPCODE(ip) @ extract opcode from rINST 5736 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5737 GOTO_OPCODE(ip) @ jump to next instruction 5738 /* 12-15 instructions */ 5739 5740 5741/* ------------------------------ */ 5742 .balign 64 5743.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5744/* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5745 /* 5746 * Signed 64-bit integer multiply, "/2addr" version. 5747 * 5748 * See OP_MUL_LONG for an explanation. 5749 * 5750 * We get a little tight on registers, so to avoid looking up &fp[A] 5751 * again we stuff it into rINST. 5752 */ 5753 /* mul-long/2addr vA, vB */ 5754 mov r9, rINST, lsr #8 @ r9<- A+ 5755 mov r1, rINST, lsr #12 @ r1<- B 5756 and r9, r9, #15 5757 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5758 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5759 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5760 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5761 mul ip, r2, r1 @ ip<- ZxW 5762 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5763 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5764 mov r0, rINST @ r0<- &fp[A] (free up rINST) 5765 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5766 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5767 GET_INST_OPCODE(ip) @ extract opcode from rINST 5768 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5769 GOTO_OPCODE(ip) @ jump to next instruction 5770 5771/* ------------------------------ */ 5772 .balign 64 5773.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5774/* File: armv5te/OP_DIV_LONG_2ADDR.S */ 5775/* File: armv5te/binopWide2addr.S */ 5776 /* 5777 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5778 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5779 * This could be an ARM instruction or a function call. (If the result 5780 * comes back in a register other than r0, you can override "result".) 5781 * 5782 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5783 * vCC (r1). Useful for integer division and modulus. 5784 * 5785 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5786 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5787 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5788 * rem-double/2addr 5789 */ 5790 /* binop/2addr vA, vB */ 5791 mov r9, rINST, lsr #8 @ r9<- A+ 5792 mov r1, rINST, lsr #12 @ r1<- B 5793 and r9, r9, #15 5794 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5795 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5796 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5797 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5798 .if 1 5799 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5800 beq common_errDivideByZero 5801 .endif 5802 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5803 5804 @ optional op; may set condition codes 5805 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5806 GET_INST_OPCODE(ip) @ extract opcode from rINST 5807 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5808 GOTO_OPCODE(ip) @ jump to next instruction 5809 /* 12-15 instructions */ 5810 5811 5812/* ------------------------------ */ 5813 .balign 64 5814.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5815/* File: armv5te/OP_REM_LONG_2ADDR.S */ 5816/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5817/* File: armv5te/binopWide2addr.S */ 5818 /* 5819 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5820 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5821 * This could be an ARM instruction or a function call. (If the result 5822 * comes back in a register other than r0, you can override "result".) 5823 * 5824 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5825 * vCC (r1). Useful for integer division and modulus. 5826 * 5827 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5828 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5829 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5830 * rem-double/2addr 5831 */ 5832 /* binop/2addr vA, vB */ 5833 mov r9, rINST, lsr #8 @ r9<- A+ 5834 mov r1, rINST, lsr #12 @ r1<- B 5835 and r9, r9, #15 5836 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5837 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5838 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5839 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5840 .if 1 5841 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5842 beq common_errDivideByZero 5843 .endif 5844 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5845 5846 @ optional op; may set condition codes 5847 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5848 GET_INST_OPCODE(ip) @ extract opcode from rINST 5849 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5850 GOTO_OPCODE(ip) @ jump to next instruction 5851 /* 12-15 instructions */ 5852 5853 5854/* ------------------------------ */ 5855 .balign 64 5856.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5857/* File: armv5te/OP_AND_LONG_2ADDR.S */ 5858/* File: armv5te/binopWide2addr.S */ 5859 /* 5860 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5861 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5862 * This could be an ARM instruction or a function call. (If the result 5863 * comes back in a register other than r0, you can override "result".) 5864 * 5865 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5866 * vCC (r1). Useful for integer division and modulus. 5867 * 5868 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5869 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5870 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5871 * rem-double/2addr 5872 */ 5873 /* binop/2addr vA, vB */ 5874 mov r9, rINST, lsr #8 @ r9<- A+ 5875 mov r1, rINST, lsr #12 @ r1<- B 5876 and r9, r9, #15 5877 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5878 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5879 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5880 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5881 .if 0 5882 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5883 beq common_errDivideByZero 5884 .endif 5885 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5886 5887 and r0, r0, r2 @ optional op; may set condition codes 5888 and r1, r1, r3 @ result<- op, r0-r3 changed 5889 GET_INST_OPCODE(ip) @ extract opcode from rINST 5890 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5891 GOTO_OPCODE(ip) @ jump to next instruction 5892 /* 12-15 instructions */ 5893 5894 5895/* ------------------------------ */ 5896 .balign 64 5897.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5898/* File: armv5te/OP_OR_LONG_2ADDR.S */ 5899/* File: armv5te/binopWide2addr.S */ 5900 /* 5901 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5902 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5903 * This could be an ARM instruction or a function call. (If the result 5904 * comes back in a register other than r0, you can override "result".) 5905 * 5906 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5907 * vCC (r1). Useful for integer division and modulus. 5908 * 5909 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5910 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5911 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5912 * rem-double/2addr 5913 */ 5914 /* binop/2addr vA, vB */ 5915 mov r9, rINST, lsr #8 @ r9<- A+ 5916 mov r1, rINST, lsr #12 @ r1<- B 5917 and r9, r9, #15 5918 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5919 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5920 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5921 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5922 .if 0 5923 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5924 beq common_errDivideByZero 5925 .endif 5926 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5927 5928 orr r0, r0, r2 @ optional op; may set condition codes 5929 orr r1, r1, r3 @ result<- op, r0-r3 changed 5930 GET_INST_OPCODE(ip) @ extract opcode from rINST 5931 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5932 GOTO_OPCODE(ip) @ jump to next instruction 5933 /* 12-15 instructions */ 5934 5935 5936/* ------------------------------ */ 5937 .balign 64 5938.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5939/* File: armv5te/OP_XOR_LONG_2ADDR.S */ 5940/* File: armv5te/binopWide2addr.S */ 5941 /* 5942 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5943 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5944 * This could be an ARM instruction or a function call. (If the result 5945 * comes back in a register other than r0, you can override "result".) 5946 * 5947 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5948 * vCC (r1). Useful for integer division and modulus. 5949 * 5950 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5951 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5952 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5953 * rem-double/2addr 5954 */ 5955 /* binop/2addr vA, vB */ 5956 mov r9, rINST, lsr #8 @ r9<- A+ 5957 mov r1, rINST, lsr #12 @ r1<- B 5958 and r9, r9, #15 5959 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5960 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5961 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5962 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5963 .if 0 5964 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5965 beq common_errDivideByZero 5966 .endif 5967 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5968 5969 eor r0, r0, r2 @ optional op; may set condition codes 5970 eor r1, r1, r3 @ result<- op, r0-r3 changed 5971 GET_INST_OPCODE(ip) @ extract opcode from rINST 5972 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5973 GOTO_OPCODE(ip) @ jump to next instruction 5974 /* 12-15 instructions */ 5975 5976 5977/* ------------------------------ */ 5978 .balign 64 5979.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 5980/* File: armv5te/OP_SHL_LONG_2ADDR.S */ 5981 /* 5982 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5983 * 32-bit shift distance. 5984 */ 5985 /* shl-long/2addr vA, vB */ 5986 mov r9, rINST, lsr #8 @ r9<- A+ 5987 mov r3, rINST, lsr #12 @ r3<- B 5988 and r9, r9, #15 5989 GET_VREG(r2, r3) @ r2<- vB 5990 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5991 and r2, r2, #63 @ r2<- r2 & 0x3f 5992 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5993 5994 mov r1, r1, asl r2 @ r1<- r1 << r2 5995 rsb r3, r2, #32 @ r3<- 32 - r2 5996 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 5997 subs ip, r2, #32 @ ip<- r2 - 32 5998 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5999 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6000 mov r0, r0, asl r2 @ r0<- r0 << r2 6001 b .LOP_SHL_LONG_2ADDR_finish 6002 6003/* ------------------------------ */ 6004 .balign 64 6005.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6006/* File: armv5te/OP_SHR_LONG_2ADDR.S */ 6007 /* 6008 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6009 * 32-bit shift distance. 6010 */ 6011 /* shr-long/2addr vA, vB */ 6012 mov r9, rINST, lsr #8 @ r9<- A+ 6013 mov r3, rINST, lsr #12 @ r3<- B 6014 and r9, r9, #15 6015 GET_VREG(r2, r3) @ r2<- vB 6016 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6017 and r2, r2, #63 @ r2<- r2 & 0x3f 6018 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6019 6020 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6021 rsb r3, r2, #32 @ r3<- 32 - r2 6022 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6023 subs ip, r2, #32 @ ip<- r2 - 32 6024 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6025 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6026 mov r1, r1, asr r2 @ r1<- r1 >> r2 6027 b .LOP_SHR_LONG_2ADDR_finish 6028 6029/* ------------------------------ */ 6030 .balign 64 6031.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6032/* File: armv5te/OP_USHR_LONG_2ADDR.S */ 6033 /* 6034 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6035 * 32-bit shift distance. 6036 */ 6037 /* ushr-long/2addr vA, vB */ 6038 mov r9, rINST, lsr #8 @ r9<- A+ 6039 mov r3, rINST, lsr #12 @ r3<- B 6040 and r9, r9, #15 6041 GET_VREG(r2, r3) @ r2<- vB 6042 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6043 and r2, r2, #63 @ r2<- r2 & 0x3f 6044 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6045 6046 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6047 rsb r3, r2, #32 @ r3<- 32 - r2 6048 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6049 subs ip, r2, #32 @ ip<- r2 - 32 6050 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6051 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6052 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6053 b .LOP_USHR_LONG_2ADDR_finish 6054 6055/* ------------------------------ */ 6056 .balign 64 6057.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6058/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6059/* File: arm-vfp/fbinop2addr.S */ 6060 /* 6061 * Generic 32-bit floating point "/2addr" binary operation. Provide 6062 * an "instr" line that specifies an instruction that performs 6063 * "s2 = s0 op s1". 6064 * 6065 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6066 */ 6067 /* binop/2addr vA, vB */ 6068 mov r3, rINST, lsr #12 @ r3<- B 6069 mov r9, rINST, lsr #8 @ r9<- A+ 6070 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6071 and r9, r9, #15 @ r9<- A 6072 flds s1, [r3] @ s1<- vB 6073 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6074 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6075 flds s0, [r9] @ s0<- vA 6076 6077 fadds s2, s0, s1 @ s2<- op 6078 GET_INST_OPCODE(ip) @ extract opcode from rINST 6079 fsts s2, [r9] @ vAA<- s2 6080 GOTO_OPCODE(ip) @ jump to next instruction 6081 6082 6083/* ------------------------------ */ 6084 .balign 64 6085.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6086/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6087/* File: arm-vfp/fbinop2addr.S */ 6088 /* 6089 * Generic 32-bit floating point "/2addr" binary operation. Provide 6090 * an "instr" line that specifies an instruction that performs 6091 * "s2 = s0 op s1". 6092 * 6093 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6094 */ 6095 /* binop/2addr vA, vB */ 6096 mov r3, rINST, lsr #12 @ r3<- B 6097 mov r9, rINST, lsr #8 @ r9<- A+ 6098 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6099 and r9, r9, #15 @ r9<- A 6100 flds s1, [r3] @ s1<- vB 6101 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6102 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6103 flds s0, [r9] @ s0<- vA 6104 6105 fsubs s2, s0, s1 @ s2<- op 6106 GET_INST_OPCODE(ip) @ extract opcode from rINST 6107 fsts s2, [r9] @ vAA<- s2 6108 GOTO_OPCODE(ip) @ jump to next instruction 6109 6110 6111/* ------------------------------ */ 6112 .balign 64 6113.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6114/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6115/* File: arm-vfp/fbinop2addr.S */ 6116 /* 6117 * Generic 32-bit floating point "/2addr" binary operation. Provide 6118 * an "instr" line that specifies an instruction that performs 6119 * "s2 = s0 op s1". 6120 * 6121 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6122 */ 6123 /* binop/2addr vA, vB */ 6124 mov r3, rINST, lsr #12 @ r3<- B 6125 mov r9, rINST, lsr #8 @ r9<- A+ 6126 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6127 and r9, r9, #15 @ r9<- A 6128 flds s1, [r3] @ s1<- vB 6129 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6130 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6131 flds s0, [r9] @ s0<- vA 6132 6133 fmuls s2, s0, s1 @ s2<- op 6134 GET_INST_OPCODE(ip) @ extract opcode from rINST 6135 fsts s2, [r9] @ vAA<- s2 6136 GOTO_OPCODE(ip) @ jump to next instruction 6137 6138 6139/* ------------------------------ */ 6140 .balign 64 6141.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6142/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6143/* File: arm-vfp/fbinop2addr.S */ 6144 /* 6145 * Generic 32-bit floating point "/2addr" binary operation. Provide 6146 * an "instr" line that specifies an instruction that performs 6147 * "s2 = s0 op s1". 6148 * 6149 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6150 */ 6151 /* binop/2addr vA, vB */ 6152 mov r3, rINST, lsr #12 @ r3<- B 6153 mov r9, rINST, lsr #8 @ r9<- A+ 6154 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6155 and r9, r9, #15 @ r9<- A 6156 flds s1, [r3] @ s1<- vB 6157 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6158 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6159 flds s0, [r9] @ s0<- vA 6160 6161 fdivs s2, s0, s1 @ s2<- op 6162 GET_INST_OPCODE(ip) @ extract opcode from rINST 6163 fsts s2, [r9] @ vAA<- s2 6164 GOTO_OPCODE(ip) @ jump to next instruction 6165 6166 6167/* ------------------------------ */ 6168 .balign 64 6169.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6170/* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6171/* EABI doesn't define a float remainder function, but libm does */ 6172/* File: armv5te/binop2addr.S */ 6173 /* 6174 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6175 * that specifies an instruction that performs "result = r0 op r1". 6176 * This could be an ARM instruction or a function call. (If the result 6177 * comes back in a register other than r0, you can override "result".) 6178 * 6179 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6180 * vCC (r1). Useful for integer division and modulus. 6181 * 6182 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6183 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6184 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6185 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6186 */ 6187 /* binop/2addr vA, vB */ 6188 mov r9, rINST, lsr #8 @ r9<- A+ 6189 mov r3, rINST, lsr #12 @ r3<- B 6190 and r9, r9, #15 6191 GET_VREG(r1, r3) @ r1<- vB 6192 GET_VREG(r0, r9) @ r0<- vA 6193 .if 0 6194 cmp r1, #0 @ is second operand zero? 6195 beq common_errDivideByZero 6196 .endif 6197 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6198 6199 @ optional op; may set condition codes 6200 bl fmodf @ r0<- op, r0-r3 changed 6201 GET_INST_OPCODE(ip) @ extract opcode from rINST 6202 SET_VREG(r0, r9) @ vAA<- r0 6203 GOTO_OPCODE(ip) @ jump to next instruction 6204 /* 10-13 instructions */ 6205 6206 6207/* ------------------------------ */ 6208 .balign 64 6209.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6210/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6211/* File: arm-vfp/fbinopWide2addr.S */ 6212 /* 6213 * Generic 64-bit floating point "/2addr" binary operation. Provide 6214 * an "instr" line that specifies an instruction that performs 6215 * "d2 = d0 op d1". 6216 * 6217 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6218 * div-double/2addr 6219 */ 6220 /* binop/2addr vA, vB */ 6221 mov r3, rINST, lsr #12 @ r3<- B 6222 mov r9, rINST, lsr #8 @ r9<- A+ 6223 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6224 and r9, r9, #15 @ r9<- A 6225 fldd d1, [r3] @ d1<- vB 6226 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6227 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6228 fldd d0, [r9] @ d0<- vA 6229 6230 faddd d2, d0, d1 @ d2<- op 6231 GET_INST_OPCODE(ip) @ extract opcode from rINST 6232 fstd d2, [r9] @ vAA<- d2 6233 GOTO_OPCODE(ip) @ jump to next instruction 6234 6235 6236/* ------------------------------ */ 6237 .balign 64 6238.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6239/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6240/* File: arm-vfp/fbinopWide2addr.S */ 6241 /* 6242 * Generic 64-bit floating point "/2addr" binary operation. Provide 6243 * an "instr" line that specifies an instruction that performs 6244 * "d2 = d0 op d1". 6245 * 6246 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6247 * div-double/2addr 6248 */ 6249 /* binop/2addr vA, vB */ 6250 mov r3, rINST, lsr #12 @ r3<- B 6251 mov r9, rINST, lsr #8 @ r9<- A+ 6252 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6253 and r9, r9, #15 @ r9<- A 6254 fldd d1, [r3] @ d1<- vB 6255 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6256 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6257 fldd d0, [r9] @ d0<- vA 6258 6259 fsubd d2, d0, d1 @ d2<- op 6260 GET_INST_OPCODE(ip) @ extract opcode from rINST 6261 fstd d2, [r9] @ vAA<- d2 6262 GOTO_OPCODE(ip) @ jump to next instruction 6263 6264 6265/* ------------------------------ */ 6266 .balign 64 6267.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6268/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6269/* File: arm-vfp/fbinopWide2addr.S */ 6270 /* 6271 * Generic 64-bit floating point "/2addr" binary operation. Provide 6272 * an "instr" line that specifies an instruction that performs 6273 * "d2 = d0 op d1". 6274 * 6275 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6276 * div-double/2addr 6277 */ 6278 /* binop/2addr vA, vB */ 6279 mov r3, rINST, lsr #12 @ r3<- B 6280 mov r9, rINST, lsr #8 @ r9<- A+ 6281 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6282 and r9, r9, #15 @ r9<- A 6283 fldd d1, [r3] @ d1<- vB 6284 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6285 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6286 fldd d0, [r9] @ d0<- vA 6287 6288 fmuld d2, d0, d1 @ d2<- op 6289 GET_INST_OPCODE(ip) @ extract opcode from rINST 6290 fstd d2, [r9] @ vAA<- d2 6291 GOTO_OPCODE(ip) @ jump to next instruction 6292 6293 6294/* ------------------------------ */ 6295 .balign 64 6296.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6297/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6298/* File: arm-vfp/fbinopWide2addr.S */ 6299 /* 6300 * Generic 64-bit floating point "/2addr" binary operation. Provide 6301 * an "instr" line that specifies an instruction that performs 6302 * "d2 = d0 op d1". 6303 * 6304 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6305 * div-double/2addr 6306 */ 6307 /* binop/2addr vA, vB */ 6308 mov r3, rINST, lsr #12 @ r3<- B 6309 mov r9, rINST, lsr #8 @ r9<- A+ 6310 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6311 and r9, r9, #15 @ r9<- A 6312 fldd d1, [r3] @ d1<- vB 6313 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6314 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6315 fldd d0, [r9] @ d0<- vA 6316 6317 fdivd d2, d0, d1 @ d2<- op 6318 GET_INST_OPCODE(ip) @ extract opcode from rINST 6319 fstd d2, [r9] @ vAA<- d2 6320 GOTO_OPCODE(ip) @ jump to next instruction 6321 6322 6323/* ------------------------------ */ 6324 .balign 64 6325.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6326/* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6327/* EABI doesn't define a double remainder function, but libm does */ 6328/* File: armv5te/binopWide2addr.S */ 6329 /* 6330 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6331 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6332 * This could be an ARM instruction or a function call. (If the result 6333 * comes back in a register other than r0, you can override "result".) 6334 * 6335 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6336 * vCC (r1). Useful for integer division and modulus. 6337 * 6338 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6339 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6340 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6341 * rem-double/2addr 6342 */ 6343 /* binop/2addr vA, vB */ 6344 mov r9, rINST, lsr #8 @ r9<- A+ 6345 mov r1, rINST, lsr #12 @ r1<- B 6346 and r9, r9, #15 6347 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6348 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6349 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6350 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6351 .if 0 6352 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6353 beq common_errDivideByZero 6354 .endif 6355 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6356 6357 @ optional op; may set condition codes 6358 bl fmod @ result<- op, r0-r3 changed 6359 GET_INST_OPCODE(ip) @ extract opcode from rINST 6360 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6361 GOTO_OPCODE(ip) @ jump to next instruction 6362 /* 12-15 instructions */ 6363 6364 6365/* ------------------------------ */ 6366 .balign 64 6367.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6368/* File: armv5te/OP_ADD_INT_LIT16.S */ 6369/* File: armv5te/binopLit16.S */ 6370 /* 6371 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6372 * that specifies an instruction that performs "result = r0 op r1". 6373 * This could be an ARM instruction or a function call. (If the result 6374 * comes back in a register other than r0, you can override "result".) 6375 * 6376 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6377 * vCC (r1). Useful for integer division and modulus. 6378 * 6379 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6380 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6381 */ 6382 /* binop/lit16 vA, vB, #+CCCC */ 6383 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6384 mov r2, rINST, lsr #12 @ r2<- B 6385 mov r9, rINST, lsr #8 @ r9<- A+ 6386 GET_VREG(r0, r2) @ r0<- vB 6387 and r9, r9, #15 6388 .if 0 6389 cmp r1, #0 @ is second operand zero? 6390 beq common_errDivideByZero 6391 .endif 6392 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6393 6394 add r0, r0, r1 @ r0<- op, r0-r3 changed 6395 GET_INST_OPCODE(ip) @ extract opcode from rINST 6396 SET_VREG(r0, r9) @ vAA<- r0 6397 GOTO_OPCODE(ip) @ jump to next instruction 6398 /* 10-13 instructions */ 6399 6400 6401/* ------------------------------ */ 6402 .balign 64 6403.L_OP_RSUB_INT: /* 0xd1 */ 6404/* File: armv5te/OP_RSUB_INT.S */ 6405/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6406/* File: armv5te/binopLit16.S */ 6407 /* 6408 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6409 * that specifies an instruction that performs "result = r0 op r1". 6410 * This could be an ARM instruction or a function call. (If the result 6411 * comes back in a register other than r0, you can override "result".) 6412 * 6413 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6414 * vCC (r1). Useful for integer division and modulus. 6415 * 6416 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6417 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6418 */ 6419 /* binop/lit16 vA, vB, #+CCCC */ 6420 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6421 mov r2, rINST, lsr #12 @ r2<- B 6422 mov r9, rINST, lsr #8 @ r9<- A+ 6423 GET_VREG(r0, r2) @ r0<- vB 6424 and r9, r9, #15 6425 .if 0 6426 cmp r1, #0 @ is second operand zero? 6427 beq common_errDivideByZero 6428 .endif 6429 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6430 6431 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6432 GET_INST_OPCODE(ip) @ extract opcode from rINST 6433 SET_VREG(r0, r9) @ vAA<- r0 6434 GOTO_OPCODE(ip) @ jump to next instruction 6435 /* 10-13 instructions */ 6436 6437 6438/* ------------------------------ */ 6439 .balign 64 6440.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6441/* File: armv5te/OP_MUL_INT_LIT16.S */ 6442/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6443/* File: armv5te/binopLit16.S */ 6444 /* 6445 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6446 * that specifies an instruction that performs "result = r0 op r1". 6447 * This could be an ARM instruction or a function call. (If the result 6448 * comes back in a register other than r0, you can override "result".) 6449 * 6450 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6451 * vCC (r1). Useful for integer division and modulus. 6452 * 6453 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6454 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6455 */ 6456 /* binop/lit16 vA, vB, #+CCCC */ 6457 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6458 mov r2, rINST, lsr #12 @ r2<- B 6459 mov r9, rINST, lsr #8 @ r9<- A+ 6460 GET_VREG(r0, r2) @ r0<- vB 6461 and r9, r9, #15 6462 .if 0 6463 cmp r1, #0 @ is second operand zero? 6464 beq common_errDivideByZero 6465 .endif 6466 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6467 6468 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6469 GET_INST_OPCODE(ip) @ extract opcode from rINST 6470 SET_VREG(r0, r9) @ vAA<- r0 6471 GOTO_OPCODE(ip) @ jump to next instruction 6472 /* 10-13 instructions */ 6473 6474 6475/* ------------------------------ */ 6476 .balign 64 6477.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6478/* File: armv5te/OP_DIV_INT_LIT16.S */ 6479/* File: armv5te/binopLit16.S */ 6480 /* 6481 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6482 * that specifies an instruction that performs "result = r0 op r1". 6483 * This could be an ARM instruction or a function call. (If the result 6484 * comes back in a register other than r0, you can override "result".) 6485 * 6486 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6487 * vCC (r1). Useful for integer division and modulus. 6488 * 6489 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6490 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6491 */ 6492 /* binop/lit16 vA, vB, #+CCCC */ 6493 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6494 mov r2, rINST, lsr #12 @ r2<- B 6495 mov r9, rINST, lsr #8 @ r9<- A+ 6496 GET_VREG(r0, r2) @ r0<- vB 6497 and r9, r9, #15 6498 .if 1 6499 cmp r1, #0 @ is second operand zero? 6500 beq common_errDivideByZero 6501 .endif 6502 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6503 6504 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6505 GET_INST_OPCODE(ip) @ extract opcode from rINST 6506 SET_VREG(r0, r9) @ vAA<- r0 6507 GOTO_OPCODE(ip) @ jump to next instruction 6508 /* 10-13 instructions */ 6509 6510 6511/* ------------------------------ */ 6512 .balign 64 6513.L_OP_REM_INT_LIT16: /* 0xd4 */ 6514/* File: armv5te/OP_REM_INT_LIT16.S */ 6515/* idivmod returns quotient in r0 and remainder in r1 */ 6516/* File: armv5te/binopLit16.S */ 6517 /* 6518 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6519 * that specifies an instruction that performs "result = r0 op r1". 6520 * This could be an ARM instruction or a function call. (If the result 6521 * comes back in a register other than r0, you can override "result".) 6522 * 6523 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6524 * vCC (r1). Useful for integer division and modulus. 6525 * 6526 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6527 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6528 */ 6529 /* binop/lit16 vA, vB, #+CCCC */ 6530 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6531 mov r2, rINST, lsr #12 @ r2<- B 6532 mov r9, rINST, lsr #8 @ r9<- A+ 6533 GET_VREG(r0, r2) @ r0<- vB 6534 and r9, r9, #15 6535 .if 1 6536 cmp r1, #0 @ is second operand zero? 6537 beq common_errDivideByZero 6538 .endif 6539 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6540 6541 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6542 GET_INST_OPCODE(ip) @ extract opcode from rINST 6543 SET_VREG(r1, r9) @ vAA<- r1 6544 GOTO_OPCODE(ip) @ jump to next instruction 6545 /* 10-13 instructions */ 6546 6547 6548/* ------------------------------ */ 6549 .balign 64 6550.L_OP_AND_INT_LIT16: /* 0xd5 */ 6551/* File: armv5te/OP_AND_INT_LIT16.S */ 6552/* File: armv5te/binopLit16.S */ 6553 /* 6554 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6555 * that specifies an instruction that performs "result = r0 op r1". 6556 * This could be an ARM instruction or a function call. (If the result 6557 * comes back in a register other than r0, you can override "result".) 6558 * 6559 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6560 * vCC (r1). Useful for integer division and modulus. 6561 * 6562 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6563 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6564 */ 6565 /* binop/lit16 vA, vB, #+CCCC */ 6566 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6567 mov r2, rINST, lsr #12 @ r2<- B 6568 mov r9, rINST, lsr #8 @ r9<- A+ 6569 GET_VREG(r0, r2) @ r0<- vB 6570 and r9, r9, #15 6571 .if 0 6572 cmp r1, #0 @ is second operand zero? 6573 beq common_errDivideByZero 6574 .endif 6575 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6576 6577 and r0, r0, r1 @ r0<- op, r0-r3 changed 6578 GET_INST_OPCODE(ip) @ extract opcode from rINST 6579 SET_VREG(r0, r9) @ vAA<- r0 6580 GOTO_OPCODE(ip) @ jump to next instruction 6581 /* 10-13 instructions */ 6582 6583 6584/* ------------------------------ */ 6585 .balign 64 6586.L_OP_OR_INT_LIT16: /* 0xd6 */ 6587/* File: armv5te/OP_OR_INT_LIT16.S */ 6588/* File: armv5te/binopLit16.S */ 6589 /* 6590 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6591 * that specifies an instruction that performs "result = r0 op r1". 6592 * This could be an ARM instruction or a function call. (If the result 6593 * comes back in a register other than r0, you can override "result".) 6594 * 6595 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6596 * vCC (r1). Useful for integer division and modulus. 6597 * 6598 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6599 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6600 */ 6601 /* binop/lit16 vA, vB, #+CCCC */ 6602 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6603 mov r2, rINST, lsr #12 @ r2<- B 6604 mov r9, rINST, lsr #8 @ r9<- A+ 6605 GET_VREG(r0, r2) @ r0<- vB 6606 and r9, r9, #15 6607 .if 0 6608 cmp r1, #0 @ is second operand zero? 6609 beq common_errDivideByZero 6610 .endif 6611 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6612 6613 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6614 GET_INST_OPCODE(ip) @ extract opcode from rINST 6615 SET_VREG(r0, r9) @ vAA<- r0 6616 GOTO_OPCODE(ip) @ jump to next instruction 6617 /* 10-13 instructions */ 6618 6619 6620/* ------------------------------ */ 6621 .balign 64 6622.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6623/* File: armv5te/OP_XOR_INT_LIT16.S */ 6624/* File: armv5te/binopLit16.S */ 6625 /* 6626 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6627 * that specifies an instruction that performs "result = r0 op r1". 6628 * This could be an ARM instruction or a function call. (If the result 6629 * comes back in a register other than r0, you can override "result".) 6630 * 6631 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6632 * vCC (r1). Useful for integer division and modulus. 6633 * 6634 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6635 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6636 */ 6637 /* binop/lit16 vA, vB, #+CCCC */ 6638 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6639 mov r2, rINST, lsr #12 @ r2<- B 6640 mov r9, rINST, lsr #8 @ r9<- A+ 6641 GET_VREG(r0, r2) @ r0<- vB 6642 and r9, r9, #15 6643 .if 0 6644 cmp r1, #0 @ is second operand zero? 6645 beq common_errDivideByZero 6646 .endif 6647 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6648 6649 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6650 GET_INST_OPCODE(ip) @ extract opcode from rINST 6651 SET_VREG(r0, r9) @ vAA<- r0 6652 GOTO_OPCODE(ip) @ jump to next instruction 6653 /* 10-13 instructions */ 6654 6655 6656/* ------------------------------ */ 6657 .balign 64 6658.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6659/* File: armv5te/OP_ADD_INT_LIT8.S */ 6660/* File: armv5te/binopLit8.S */ 6661 /* 6662 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6663 * that specifies an instruction that performs "result = r0 op r1". 6664 * This could be an ARM instruction or a function call. (If the result 6665 * comes back in a register other than r0, you can override "result".) 6666 * 6667 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6668 * vCC (r1). Useful for integer division and modulus. 6669 * 6670 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6671 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6672 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6673 */ 6674 /* binop/lit8 vAA, vBB, #+CC */ 6675 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6676 mov r9, rINST, lsr #8 @ r9<- AA 6677 and r2, r3, #255 @ r2<- BB 6678 GET_VREG(r0, r2) @ r0<- vBB 6679 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6680 .if 0 6681 @cmp r1, #0 @ is second operand zero? 6682 beq common_errDivideByZero 6683 .endif 6684 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6685 6686 @ optional op; may set condition codes 6687 add r0, r0, r1 @ r0<- op, r0-r3 changed 6688 GET_INST_OPCODE(ip) @ extract opcode from rINST 6689 SET_VREG(r0, r9) @ vAA<- r0 6690 GOTO_OPCODE(ip) @ jump to next instruction 6691 /* 10-12 instructions */ 6692 6693 6694/* ------------------------------ */ 6695 .balign 64 6696.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6697/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6698/* File: armv5te/binopLit8.S */ 6699 /* 6700 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6701 * that specifies an instruction that performs "result = r0 op r1". 6702 * This could be an ARM instruction or a function call. (If the result 6703 * comes back in a register other than r0, you can override "result".) 6704 * 6705 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6706 * vCC (r1). Useful for integer division and modulus. 6707 * 6708 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6709 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6710 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6711 */ 6712 /* binop/lit8 vAA, vBB, #+CC */ 6713 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6714 mov r9, rINST, lsr #8 @ r9<- AA 6715 and r2, r3, #255 @ r2<- BB 6716 GET_VREG(r0, r2) @ r0<- vBB 6717 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6718 .if 0 6719 @cmp r1, #0 @ is second operand zero? 6720 beq common_errDivideByZero 6721 .endif 6722 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6723 6724 @ optional op; may set condition codes 6725 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6726 GET_INST_OPCODE(ip) @ extract opcode from rINST 6727 SET_VREG(r0, r9) @ vAA<- r0 6728 GOTO_OPCODE(ip) @ jump to next instruction 6729 /* 10-12 instructions */ 6730 6731 6732/* ------------------------------ */ 6733 .balign 64 6734.L_OP_MUL_INT_LIT8: /* 0xda */ 6735/* File: armv5te/OP_MUL_INT_LIT8.S */ 6736/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6737/* File: armv5te/binopLit8.S */ 6738 /* 6739 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6740 * that specifies an instruction that performs "result = r0 op r1". 6741 * This could be an ARM instruction or a function call. (If the result 6742 * comes back in a register other than r0, you can override "result".) 6743 * 6744 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6745 * vCC (r1). Useful for integer division and modulus. 6746 * 6747 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6748 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6749 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6750 */ 6751 /* binop/lit8 vAA, vBB, #+CC */ 6752 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6753 mov r9, rINST, lsr #8 @ r9<- AA 6754 and r2, r3, #255 @ r2<- BB 6755 GET_VREG(r0, r2) @ r0<- vBB 6756 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6757 .if 0 6758 @cmp r1, #0 @ is second operand zero? 6759 beq common_errDivideByZero 6760 .endif 6761 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6762 6763 @ optional op; may set condition codes 6764 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6765 GET_INST_OPCODE(ip) @ extract opcode from rINST 6766 SET_VREG(r0, r9) @ vAA<- r0 6767 GOTO_OPCODE(ip) @ jump to next instruction 6768 /* 10-12 instructions */ 6769 6770 6771/* ------------------------------ */ 6772 .balign 64 6773.L_OP_DIV_INT_LIT8: /* 0xdb */ 6774/* File: armv5te/OP_DIV_INT_LIT8.S */ 6775/* File: armv5te/binopLit8.S */ 6776 /* 6777 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6778 * that specifies an instruction that performs "result = r0 op r1". 6779 * This could be an ARM instruction or a function call. (If the result 6780 * comes back in a register other than r0, you can override "result".) 6781 * 6782 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6783 * vCC (r1). Useful for integer division and modulus. 6784 * 6785 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6786 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6787 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6788 */ 6789 /* binop/lit8 vAA, vBB, #+CC */ 6790 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6791 mov r9, rINST, lsr #8 @ r9<- AA 6792 and r2, r3, #255 @ r2<- BB 6793 GET_VREG(r0, r2) @ r0<- vBB 6794 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6795 .if 1 6796 @cmp r1, #0 @ is second operand zero? 6797 beq common_errDivideByZero 6798 .endif 6799 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6800 6801 @ optional op; may set condition codes 6802 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6803 GET_INST_OPCODE(ip) @ extract opcode from rINST 6804 SET_VREG(r0, r9) @ vAA<- r0 6805 GOTO_OPCODE(ip) @ jump to next instruction 6806 /* 10-12 instructions */ 6807 6808 6809/* ------------------------------ */ 6810 .balign 64 6811.L_OP_REM_INT_LIT8: /* 0xdc */ 6812/* File: armv5te/OP_REM_INT_LIT8.S */ 6813/* idivmod returns quotient in r0 and remainder in r1 */ 6814/* File: armv5te/binopLit8.S */ 6815 /* 6816 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6817 * that specifies an instruction that performs "result = r0 op r1". 6818 * This could be an ARM instruction or a function call. (If the result 6819 * comes back in a register other than r0, you can override "result".) 6820 * 6821 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6822 * vCC (r1). Useful for integer division and modulus. 6823 * 6824 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6825 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6826 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6827 */ 6828 /* binop/lit8 vAA, vBB, #+CC */ 6829 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6830 mov r9, rINST, lsr #8 @ r9<- AA 6831 and r2, r3, #255 @ r2<- BB 6832 GET_VREG(r0, r2) @ r0<- vBB 6833 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6834 .if 1 6835 @cmp r1, #0 @ is second operand zero? 6836 beq common_errDivideByZero 6837 .endif 6838 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6839 6840 @ optional op; may set condition codes 6841 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6842 GET_INST_OPCODE(ip) @ extract opcode from rINST 6843 SET_VREG(r1, r9) @ vAA<- r1 6844 GOTO_OPCODE(ip) @ jump to next instruction 6845 /* 10-12 instructions */ 6846 6847 6848/* ------------------------------ */ 6849 .balign 64 6850.L_OP_AND_INT_LIT8: /* 0xdd */ 6851/* File: armv5te/OP_AND_INT_LIT8.S */ 6852/* File: armv5te/binopLit8.S */ 6853 /* 6854 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6855 * that specifies an instruction that performs "result = r0 op r1". 6856 * This could be an ARM instruction or a function call. (If the result 6857 * comes back in a register other than r0, you can override "result".) 6858 * 6859 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6860 * vCC (r1). Useful for integer division and modulus. 6861 * 6862 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6863 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6864 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6865 */ 6866 /* binop/lit8 vAA, vBB, #+CC */ 6867 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6868 mov r9, rINST, lsr #8 @ r9<- AA 6869 and r2, r3, #255 @ r2<- BB 6870 GET_VREG(r0, r2) @ r0<- vBB 6871 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6872 .if 0 6873 @cmp r1, #0 @ is second operand zero? 6874 beq common_errDivideByZero 6875 .endif 6876 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6877 6878 @ optional op; may set condition codes 6879 and r0, r0, r1 @ r0<- op, r0-r3 changed 6880 GET_INST_OPCODE(ip) @ extract opcode from rINST 6881 SET_VREG(r0, r9) @ vAA<- r0 6882 GOTO_OPCODE(ip) @ jump to next instruction 6883 /* 10-12 instructions */ 6884 6885 6886/* ------------------------------ */ 6887 .balign 64 6888.L_OP_OR_INT_LIT8: /* 0xde */ 6889/* File: armv5te/OP_OR_INT_LIT8.S */ 6890/* File: armv5te/binopLit8.S */ 6891 /* 6892 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6893 * that specifies an instruction that performs "result = r0 op r1". 6894 * This could be an ARM instruction or a function call. (If the result 6895 * comes back in a register other than r0, you can override "result".) 6896 * 6897 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6898 * vCC (r1). Useful for integer division and modulus. 6899 * 6900 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6901 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6902 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6903 */ 6904 /* binop/lit8 vAA, vBB, #+CC */ 6905 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6906 mov r9, rINST, lsr #8 @ r9<- AA 6907 and r2, r3, #255 @ r2<- BB 6908 GET_VREG(r0, r2) @ r0<- vBB 6909 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6910 .if 0 6911 @cmp r1, #0 @ is second operand zero? 6912 beq common_errDivideByZero 6913 .endif 6914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6915 6916 @ optional op; may set condition codes 6917 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6918 GET_INST_OPCODE(ip) @ extract opcode from rINST 6919 SET_VREG(r0, r9) @ vAA<- r0 6920 GOTO_OPCODE(ip) @ jump to next instruction 6921 /* 10-12 instructions */ 6922 6923 6924/* ------------------------------ */ 6925 .balign 64 6926.L_OP_XOR_INT_LIT8: /* 0xdf */ 6927/* File: armv5te/OP_XOR_INT_LIT8.S */ 6928/* File: armv5te/binopLit8.S */ 6929 /* 6930 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6931 * that specifies an instruction that performs "result = r0 op r1". 6932 * This could be an ARM instruction or a function call. (If the result 6933 * comes back in a register other than r0, you can override "result".) 6934 * 6935 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6936 * vCC (r1). Useful for integer division and modulus. 6937 * 6938 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6939 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6940 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6941 */ 6942 /* binop/lit8 vAA, vBB, #+CC */ 6943 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6944 mov r9, rINST, lsr #8 @ r9<- AA 6945 and r2, r3, #255 @ r2<- BB 6946 GET_VREG(r0, r2) @ r0<- vBB 6947 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6948 .if 0 6949 @cmp r1, #0 @ is second operand zero? 6950 beq common_errDivideByZero 6951 .endif 6952 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6953 6954 @ optional op; may set condition codes 6955 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6956 GET_INST_OPCODE(ip) @ extract opcode from rINST 6957 SET_VREG(r0, r9) @ vAA<- r0 6958 GOTO_OPCODE(ip) @ jump to next instruction 6959 /* 10-12 instructions */ 6960 6961 6962/* ------------------------------ */ 6963 .balign 64 6964.L_OP_SHL_INT_LIT8: /* 0xe0 */ 6965/* File: armv5te/OP_SHL_INT_LIT8.S */ 6966/* File: armv5te/binopLit8.S */ 6967 /* 6968 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6969 * that specifies an instruction that performs "result = r0 op r1". 6970 * This could be an ARM instruction or a function call. (If the result 6971 * comes back in a register other than r0, you can override "result".) 6972 * 6973 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6974 * vCC (r1). Useful for integer division and modulus. 6975 * 6976 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6977 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6978 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6979 */ 6980 /* binop/lit8 vAA, vBB, #+CC */ 6981 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6982 mov r9, rINST, lsr #8 @ r9<- AA 6983 and r2, r3, #255 @ r2<- BB 6984 GET_VREG(r0, r2) @ r0<- vBB 6985 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6986 .if 0 6987 @cmp r1, #0 @ is second operand zero? 6988 beq common_errDivideByZero 6989 .endif 6990 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6991 6992 and r1, r1, #31 @ optional op; may set condition codes 6993 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 6994 GET_INST_OPCODE(ip) @ extract opcode from rINST 6995 SET_VREG(r0, r9) @ vAA<- r0 6996 GOTO_OPCODE(ip) @ jump to next instruction 6997 /* 10-12 instructions */ 6998 6999 7000/* ------------------------------ */ 7001 .balign 64 7002.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7003/* File: armv5te/OP_SHR_INT_LIT8.S */ 7004/* File: armv5te/binopLit8.S */ 7005 /* 7006 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7007 * that specifies an instruction that performs "result = r0 op r1". 7008 * This could be an ARM instruction or a function call. (If the result 7009 * comes back in a register other than r0, you can override "result".) 7010 * 7011 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7012 * vCC (r1). Useful for integer division and modulus. 7013 * 7014 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7015 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7016 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7017 */ 7018 /* binop/lit8 vAA, vBB, #+CC */ 7019 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7020 mov r9, rINST, lsr #8 @ r9<- AA 7021 and r2, r3, #255 @ r2<- BB 7022 GET_VREG(r0, r2) @ r0<- vBB 7023 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7024 .if 0 7025 @cmp r1, #0 @ is second operand zero? 7026 beq common_errDivideByZero 7027 .endif 7028 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7029 7030 and r1, r1, #31 @ optional op; may set condition codes 7031 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7032 GET_INST_OPCODE(ip) @ extract opcode from rINST 7033 SET_VREG(r0, r9) @ vAA<- r0 7034 GOTO_OPCODE(ip) @ jump to next instruction 7035 /* 10-12 instructions */ 7036 7037 7038/* ------------------------------ */ 7039 .balign 64 7040.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7041/* File: armv5te/OP_USHR_INT_LIT8.S */ 7042/* File: armv5te/binopLit8.S */ 7043 /* 7044 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7045 * that specifies an instruction that performs "result = r0 op r1". 7046 * This could be an ARM instruction or a function call. (If the result 7047 * comes back in a register other than r0, you can override "result".) 7048 * 7049 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7050 * vCC (r1). Useful for integer division and modulus. 7051 * 7052 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7053 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7054 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7055 */ 7056 /* binop/lit8 vAA, vBB, #+CC */ 7057 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7058 mov r9, rINST, lsr #8 @ r9<- AA 7059 and r2, r3, #255 @ r2<- BB 7060 GET_VREG(r0, r2) @ r0<- vBB 7061 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7062 .if 0 7063 @cmp r1, #0 @ is second operand zero? 7064 beq common_errDivideByZero 7065 .endif 7066 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7067 7068 and r1, r1, #31 @ optional op; may set condition codes 7069 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7070 GET_INST_OPCODE(ip) @ extract opcode from rINST 7071 SET_VREG(r0, r9) @ vAA<- r0 7072 GOTO_OPCODE(ip) @ jump to next instruction 7073 /* 10-12 instructions */ 7074 7075 7076/* ------------------------------ */ 7077 .balign 64 7078.L_OP_IGET_VOLATILE: /* 0xe3 */ 7079/* File: armv5te/OP_IGET_VOLATILE.S */ 7080/* File: armv5te/OP_IGET.S */ 7081 /* 7082 * General 32-bit instance field get. 7083 * 7084 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7085 */ 7086 /* op vA, vB, field@CCCC */ 7087 mov r0, rINST, lsr #12 @ r0<- B 7088 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7089 FETCH(r1, 1) @ r1<- field ref CCCC 7090 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7091 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7092 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7093 cmp r0, #0 @ is resolved entry null? 7094 bne .LOP_IGET_VOLATILE_finish @ no, already resolved 70958: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7096 EXPORT_PC() @ resolve() could throw 7097 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7098 bl dvmResolveInstField @ r0<- resolved InstField ptr 7099 cmp r0, #0 7100 bne .LOP_IGET_VOLATILE_finish 7101 b common_exceptionThrown 7102 7103 7104/* ------------------------------ */ 7105 .balign 64 7106.L_OP_IPUT_VOLATILE: /* 0xe4 */ 7107/* File: armv5te/OP_IPUT_VOLATILE.S */ 7108/* File: armv5te/OP_IPUT.S */ 7109 /* 7110 * General 32-bit instance field put. 7111 * 7112 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7113 */ 7114 /* op vA, vB, field@CCCC */ 7115 mov r0, rINST, lsr #12 @ r0<- B 7116 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7117 FETCH(r1, 1) @ r1<- field ref CCCC 7118 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7119 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7120 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7121 cmp r0, #0 @ is resolved entry null? 7122 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 71238: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7124 EXPORT_PC() @ resolve() could throw 7125 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7126 bl dvmResolveInstField @ r0<- resolved InstField ptr 7127 cmp r0, #0 @ success? 7128 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7129 b common_exceptionThrown 7130 7131 7132/* ------------------------------ */ 7133 .balign 64 7134.L_OP_SGET_VOLATILE: /* 0xe5 */ 7135/* File: armv5te/OP_SGET_VOLATILE.S */ 7136/* File: armv5te/OP_SGET.S */ 7137 /* 7138 * General 32-bit SGET handler. 7139 * 7140 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7141 */ 7142 /* op vAA, field@BBBB */ 7143 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7144 FETCH(r1, 1) @ r1<- field ref BBBB 7145 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7146 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7147 cmp r0, #0 @ is resolved entry null? 7148 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7149.LOP_SGET_VOLATILE_finish: @ field ptr in r0 7150 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7151 SMP_DMB @ acquiring load 7152 mov r2, rINST, lsr #8 @ r2<- AA 7153 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7154 SET_VREG(r1, r2) @ fp[AA]<- r1 7155 GET_INST_OPCODE(ip) @ extract opcode from rINST 7156 GOTO_OPCODE(ip) @ jump to next instruction 7157 7158 7159/* ------------------------------ */ 7160 .balign 64 7161.L_OP_SPUT_VOLATILE: /* 0xe6 */ 7162/* File: armv5te/OP_SPUT_VOLATILE.S */ 7163/* File: armv5te/OP_SPUT.S */ 7164 /* 7165 * General 32-bit SPUT handler. 7166 * 7167 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7168 */ 7169 /* op vAA, field@BBBB */ 7170 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7171 FETCH(r1, 1) @ r1<- field ref BBBB 7172 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7173 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7174 cmp r0, #0 @ is resolved entry null? 7175 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7176.LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7177 mov r2, rINST, lsr #8 @ r2<- AA 7178 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7179 GET_VREG(r1, r2) @ r1<- fp[AA] 7180 GET_INST_OPCODE(ip) @ extract opcode from rINST 7181 SMP_DMB @ releasing store 7182 str r1, [r0, #offStaticField_value] @ field<- vAA 7183 GOTO_OPCODE(ip) @ jump to next instruction 7184 7185 7186/* ------------------------------ */ 7187 .balign 64 7188.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7189/* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7190/* File: armv5te/OP_IGET.S */ 7191 /* 7192 * General 32-bit instance field get. 7193 * 7194 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7195 */ 7196 /* op vA, vB, field@CCCC */ 7197 mov r0, rINST, lsr #12 @ r0<- B 7198 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7199 FETCH(r1, 1) @ r1<- field ref CCCC 7200 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7201 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7202 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7203 cmp r0, #0 @ is resolved entry null? 7204 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 72058: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7206 EXPORT_PC() @ resolve() could throw 7207 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7208 bl dvmResolveInstField @ r0<- resolved InstField ptr 7209 cmp r0, #0 7210 bne .LOP_IGET_OBJECT_VOLATILE_finish 7211 b common_exceptionThrown 7212 7213 7214/* ------------------------------ */ 7215 .balign 64 7216.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 7217/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 7218/* File: armv5te/OP_IGET_WIDE.S */ 7219 /* 7220 * Wide 32-bit instance field get. 7221 */ 7222 /* iget-wide vA, vB, field@CCCC */ 7223 mov r0, rINST, lsr #12 @ r0<- B 7224 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7225 FETCH(r1, 1) @ r1<- field ref CCCC 7226 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7227 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7228 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7229 cmp r0, #0 @ is resolved entry null? 7230 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 72318: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7232 EXPORT_PC() @ resolve() could throw 7233 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7234 bl dvmResolveInstField @ r0<- resolved InstField ptr 7235 cmp r0, #0 7236 bne .LOP_IGET_WIDE_VOLATILE_finish 7237 b common_exceptionThrown 7238 7239 7240/* ------------------------------ */ 7241 .balign 64 7242.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 7243/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 7244/* File: armv5te/OP_IPUT_WIDE.S */ 7245 /* iput-wide vA, vB, field@CCCC */ 7246 mov r0, rINST, lsr #12 @ r0<- B 7247 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7248 FETCH(r1, 1) @ r1<- field ref CCCC 7249 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7250 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7251 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7252 cmp r0, #0 @ is resolved entry null? 7253 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 72548: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7255 EXPORT_PC() @ resolve() could throw 7256 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7257 bl dvmResolveInstField @ r0<- resolved InstField ptr 7258 cmp r0, #0 @ success? 7259 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 7260 b common_exceptionThrown 7261 7262 7263/* ------------------------------ */ 7264 .balign 64 7265.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 7266/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 7267/* File: armv5te/OP_SGET_WIDE.S */ 7268 /* 7269 * 64-bit SGET handler. 7270 */ 7271 /* sget-wide vAA, field@BBBB */ 7272 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7273 FETCH(r1, 1) @ r1<- field ref BBBB 7274 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7275 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7276 cmp r0, #0 @ is resolved entry null? 7277 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 7278.LOP_SGET_WIDE_VOLATILE_finish: 7279 mov r9, rINST, lsr #8 @ r9<- AA 7280 .if 1 7281 add r0, r0, #offStaticField_value @ r0<- pointer to data 7282 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7283 .else 7284 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7285 .endif 7286 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7287 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7288 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 7289 GET_INST_OPCODE(ip) @ extract opcode from rINST 7290 GOTO_OPCODE(ip) @ jump to next instruction 7291 7292 7293/* ------------------------------ */ 7294 .balign 64 7295.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 7296/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 7297/* File: armv5te/OP_SPUT_WIDE.S */ 7298 /* 7299 * 64-bit SPUT handler. 7300 */ 7301 /* sput-wide vAA, field@BBBB */ 7302 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 7303 FETCH(r1, 1) @ r1<- field ref BBBB 7304 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 7305 mov r9, rINST, lsr #8 @ r9<- AA 7306 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 7307 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7308 cmp r2, #0 @ is resolved entry null? 7309 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7310.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 7311 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7312 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7313 GET_INST_OPCODE(r10) @ extract opcode from rINST 7314 .if 1 7315 add r2, r2, #offStaticField_value @ r2<- pointer to data 7316 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 7317 .else 7318 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7319 .endif 7320 GOTO_OPCODE(r10) @ jump to next instruction 7321 7322 7323/* ------------------------------ */ 7324 .balign 64 7325.L_OP_BREAKPOINT: /* 0xec */ 7326/* File: armv5te/OP_BREAKPOINT.S */ 7327/* File: armv5te/unused.S */ 7328 bl common_abort 7329 7330 7331/* ------------------------------ */ 7332 .balign 64 7333.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7334/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7335 /* 7336 * Handle a throw-verification-error instruction. This throws an 7337 * exception for an error discovered during verification. The 7338 * exception is indicated by AA, with some detail provided by BBBB. 7339 */ 7340 /* op AA, ref@BBBB */ 7341 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 7342 FETCH(r2, 1) @ r2<- BBBB 7343 EXPORT_PC() @ export the PC 7344 mov r1, rINST, lsr #8 @ r1<- AA 7345 bl dvmThrowVerificationError @ always throws 7346 b common_exceptionThrown @ handle exception 7347 7348/* ------------------------------ */ 7349 .balign 64 7350.L_OP_EXECUTE_INLINE: /* 0xee */ 7351/* File: armv5te/OP_EXECUTE_INLINE.S */ 7352 /* 7353 * Execute a "native inline" instruction. 7354 * 7355 * We need to call an InlineOp4Func: 7356 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7357 * 7358 * The first four args are in r0-r3, pointer to return value storage 7359 * is on the stack. The function's return value is a flag that tells 7360 * us if an exception was thrown. 7361 */ 7362 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7363 FETCH(r10, 1) @ r10<- BBBB 7364 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7365 EXPORT_PC() @ can throw 7366 sub sp, sp, #8 @ make room for arg, +64 bit align 7367 mov r0, rINST, lsr #12 @ r0<- B 7368 str r1, [sp] @ push &self->retval 7369 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7370 add sp, sp, #8 @ pop stack 7371 cmp r0, #0 @ test boolean result of inline 7372 beq common_exceptionThrown @ returned false, handle exception 7373 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7374 GET_INST_OPCODE(ip) @ extract opcode from rINST 7375 GOTO_OPCODE(ip) @ jump to next instruction 7376 7377/* ------------------------------ */ 7378 .balign 64 7379.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7380/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7381 /* 7382 * Execute a "native inline" instruction, using "/range" semantics. 7383 * Same idea as execute-inline, but we get the args differently. 7384 * 7385 * We need to call an InlineOp4Func: 7386 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7387 * 7388 * The first four args are in r0-r3, pointer to return value storage 7389 * is on the stack. The function's return value is a flag that tells 7390 * us if an exception was thrown. 7391 */ 7392 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7393 FETCH(r10, 1) @ r10<- BBBB 7394 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7395 EXPORT_PC() @ can throw 7396 sub sp, sp, #8 @ make room for arg, +64 bit align 7397 mov r0, rINST, lsr #8 @ r0<- AA 7398 str r1, [sp] @ push &self->retval 7399 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7400 add sp, sp, #8 @ pop stack 7401 cmp r0, #0 @ test boolean result of inline 7402 beq common_exceptionThrown @ returned false, handle exception 7403 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7404 GET_INST_OPCODE(ip) @ extract opcode from rINST 7405 GOTO_OPCODE(ip) @ jump to next instruction 7406 7407/* ------------------------------ */ 7408 .balign 64 7409.L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 7410/* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */ 7411 /* 7412 * Invoke Object.<init> on an object. In practice we know that 7413 * Object's nullary constructor doesn't do anything, so we just 7414 * skip it (we know a debugger isn't active). 7415 */ 7416 FETCH(r1, 2) @ r1<- CCCC 7417 GET_VREG(r0, r1) @ r0<- "this" ptr 7418 cmp r0, #0 @ check for NULL 7419 beq common_errNullObject @ export PC and throw NPE 7420 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 7421 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 7422 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 7423 beq 1f @ nope, done 7424 EXPORT_PC() @ can throw 7425 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 7426 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception 7427 cmp r0, #0 @ exception pending? 7428 bne common_exceptionThrown @ yes, handle it 74291: FETCH_ADVANCE_INST(2+1) @ advance to next instr, load rINST 7430 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7431 GOTO_OPCODE(ip) @ execute it 7432 7433/* ------------------------------ */ 7434 .balign 64 7435.L_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 7436/* File: armv5te/OP_RETURN_VOID_BARRIER.S */ 7437 SMP_DMB_ST 7438 b common_returnFromMethod 7439 7440/* ------------------------------ */ 7441 .balign 64 7442.L_OP_IGET_QUICK: /* 0xf2 */ 7443/* File: armv5te/OP_IGET_QUICK.S */ 7444 /* For: iget-quick, iget-object-quick */ 7445 /* op vA, vB, offset@CCCC */ 7446 mov r2, rINST, lsr #12 @ r2<- B 7447 GET_VREG(r3, r2) @ r3<- object we're operating on 7448 FETCH(r1, 1) @ r1<- field byte offset 7449 cmp r3, #0 @ check object for null 7450 mov r2, rINST, lsr #8 @ r2<- A(+) 7451 beq common_errNullObject @ object was null 7452 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7453 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7454 and r2, r2, #15 7455 GET_INST_OPCODE(ip) @ extract opcode from rINST 7456 SET_VREG(r0, r2) @ fp[A]<- r0 7457 GOTO_OPCODE(ip) @ jump to next instruction 7458 7459/* ------------------------------ */ 7460 .balign 64 7461.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7462/* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7463 /* iget-wide-quick vA, vB, offset@CCCC */ 7464 mov r2, rINST, lsr #12 @ r2<- B 7465 GET_VREG(r3, r2) @ r3<- object we're operating on 7466 FETCH(ip, 1) @ ip<- field byte offset 7467 cmp r3, #0 @ check object for null 7468 mov r2, rINST, lsr #8 @ r2<- A(+) 7469 beq common_errNullObject @ object was null 7470 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7471 and r2, r2, #15 7472 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7473 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7474 GET_INST_OPCODE(ip) @ extract opcode from rINST 7475 stmia r3, {r0-r1} @ fp[A]<- r0/r1 7476 GOTO_OPCODE(ip) @ jump to next instruction 7477 7478/* ------------------------------ */ 7479 .balign 64 7480.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7481/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7482/* File: armv5te/OP_IGET_QUICK.S */ 7483 /* For: iget-quick, iget-object-quick */ 7484 /* op vA, vB, offset@CCCC */ 7485 mov r2, rINST, lsr #12 @ r2<- B 7486 GET_VREG(r3, r2) @ r3<- object we're operating on 7487 FETCH(r1, 1) @ r1<- field byte offset 7488 cmp r3, #0 @ check object for null 7489 mov r2, rINST, lsr #8 @ r2<- A(+) 7490 beq common_errNullObject @ object was null 7491 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7492 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7493 and r2, r2, #15 7494 GET_INST_OPCODE(ip) @ extract opcode from rINST 7495 SET_VREG(r0, r2) @ fp[A]<- r0 7496 GOTO_OPCODE(ip) @ jump to next instruction 7497 7498 7499/* ------------------------------ */ 7500 .balign 64 7501.L_OP_IPUT_QUICK: /* 0xf5 */ 7502/* File: armv5te/OP_IPUT_QUICK.S */ 7503 /* For: iput-quick */ 7504 /* op vA, vB, offset@CCCC */ 7505 mov r2, rINST, lsr #12 @ r2<- B 7506 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7507 FETCH(r1, 1) @ r1<- field byte offset 7508 cmp r3, #0 @ check object for null 7509 mov r2, rINST, lsr #8 @ r2<- A(+) 7510 beq common_errNullObject @ object was null 7511 and r2, r2, #15 7512 GET_VREG(r0, r2) @ r0<- fp[A] 7513 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7514 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7515 GET_INST_OPCODE(ip) @ extract opcode from rINST 7516 GOTO_OPCODE(ip) @ jump to next instruction 7517 7518/* ------------------------------ */ 7519 .balign 64 7520.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7521/* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7522 /* iput-wide-quick vA, vB, offset@CCCC */ 7523 mov r0, rINST, lsr #8 @ r0<- A(+) 7524 mov r1, rINST, lsr #12 @ r1<- B 7525 and r0, r0, #15 7526 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7527 add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7528 cmp r2, #0 @ check object for null 7529 ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7530 beq common_errNullObject @ object was null 7531 FETCH(r3, 1) @ r3<- field byte offset 7532 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7533 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7534 GET_INST_OPCODE(ip) @ extract opcode from rINST 7535 GOTO_OPCODE(ip) @ jump to next instruction 7536 7537/* ------------------------------ */ 7538 .balign 64 7539.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7540/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7541 /* For: iput-object-quick */ 7542 /* op vA, vB, offset@CCCC */ 7543 mov r2, rINST, lsr #12 @ r2<- B 7544 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7545 FETCH(r1, 1) @ r1<- field byte offset 7546 cmp r3, #0 @ check object for null 7547 mov r2, rINST, lsr #8 @ r2<- A(+) 7548 beq common_errNullObject @ object was null 7549 and r2, r2, #15 7550 GET_VREG(r0, r2) @ r0<- fp[A] 7551 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 7552 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7553 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7554 cmp r0, #0 7555 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head 7556 GET_INST_OPCODE(ip) @ extract opcode from rINST 7557 GOTO_OPCODE(ip) @ jump to next instruction 7558 7559/* ------------------------------ */ 7560 .balign 64 7561.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7562/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7563 /* 7564 * Handle an optimized virtual method call. 7565 * 7566 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7567 */ 7568 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7569 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7570 FETCH(r3, 2) @ r3<- FEDC or CCCC 7571 FETCH(r1, 1) @ r1<- BBBB 7572 .if (!0) 7573 and r3, r3, #15 @ r3<- C (or stays CCCC) 7574 .endif 7575 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7576 cmp r2, #0 @ is "this" null? 7577 beq common_errNullObject @ null "this", throw exception 7578 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7579 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7580 EXPORT_PC() @ invoke must export 7581 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7582 bl common_invokeMethodNoRange @ continue on 7583 7584/* ------------------------------ */ 7585 .balign 64 7586.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7587/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7588/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7589 /* 7590 * Handle an optimized virtual method call. 7591 * 7592 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7593 */ 7594 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7595 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7596 FETCH(r3, 2) @ r3<- FEDC or CCCC 7597 FETCH(r1, 1) @ r1<- BBBB 7598 .if (!1) 7599 and r3, r3, #15 @ r3<- C (or stays CCCC) 7600 .endif 7601 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7602 cmp r2, #0 @ is "this" null? 7603 beq common_errNullObject @ null "this", throw exception 7604 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7605 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7606 EXPORT_PC() @ invoke must export 7607 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7608 bl common_invokeMethodRange @ continue on 7609 7610 7611/* ------------------------------ */ 7612 .balign 64 7613.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7614/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7615 /* 7616 * Handle an optimized "super" method call. 7617 * 7618 * for: [opt] invoke-super-quick, invoke-super-quick/range 7619 */ 7620 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7621 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7622 FETCH(r10, 2) @ r10<- GFED or CCCC 7623 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7624 .if (!0) 7625 and r10, r10, #15 @ r10<- D (or stays CCCC) 7626 .endif 7627 FETCH(r1, 1) @ r1<- BBBB 7628 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7629 EXPORT_PC() @ must export for invoke 7630 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7631 GET_VREG(r3, r10) @ r3<- "this" 7632 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7633 cmp r3, #0 @ null "this" ref? 7634 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7635 beq common_errNullObject @ "this" is null, throw exception 7636 bl common_invokeMethodNoRange @ continue on 7637 7638/* ------------------------------ */ 7639 .balign 64 7640.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7641/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7642/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7643 /* 7644 * Handle an optimized "super" method call. 7645 * 7646 * for: [opt] invoke-super-quick, invoke-super-quick/range 7647 */ 7648 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7649 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7650 FETCH(r10, 2) @ r10<- GFED or CCCC 7651 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7652 .if (!1) 7653 and r10, r10, #15 @ r10<- D (or stays CCCC) 7654 .endif 7655 FETCH(r1, 1) @ r1<- BBBB 7656 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7657 EXPORT_PC() @ must export for invoke 7658 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7659 GET_VREG(r3, r10) @ r3<- "this" 7660 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7661 cmp r3, #0 @ null "this" ref? 7662 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7663 beq common_errNullObject @ "this" is null, throw exception 7664 bl common_invokeMethodRange @ continue on 7665 7666 7667/* ------------------------------ */ 7668 .balign 64 7669.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7670/* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7671/* File: armv5te/OP_IPUT_OBJECT.S */ 7672 /* 7673 * 32-bit instance field put. 7674 * 7675 * for: iput-object, iput-object-volatile 7676 */ 7677 /* op vA, vB, field@CCCC */ 7678 mov r0, rINST, lsr #12 @ r0<- B 7679 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7680 FETCH(r1, 1) @ r1<- field ref CCCC 7681 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7682 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7683 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7684 cmp r0, #0 @ is resolved entry null? 7685 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 76868: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7687 EXPORT_PC() @ resolve() could throw 7688 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7689 bl dvmResolveInstField @ r0<- resolved InstField ptr 7690 cmp r0, #0 @ success? 7691 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 7692 b common_exceptionThrown 7693 7694 7695/* ------------------------------ */ 7696 .balign 64 7697.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 7698/* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 7699/* File: armv5te/OP_SGET.S */ 7700 /* 7701 * General 32-bit SGET handler. 7702 * 7703 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7704 */ 7705 /* op vAA, field@BBBB */ 7706 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7707 FETCH(r1, 1) @ r1<- field ref BBBB 7708 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7709 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7710 cmp r0, #0 @ is resolved entry null? 7711 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 7712.LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 7713 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7714 SMP_DMB @ acquiring load 7715 mov r2, rINST, lsr #8 @ r2<- AA 7716 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7717 SET_VREG(r1, r2) @ fp[AA]<- r1 7718 GET_INST_OPCODE(ip) @ extract opcode from rINST 7719 GOTO_OPCODE(ip) @ jump to next instruction 7720 7721 7722/* ------------------------------ */ 7723 .balign 64 7724.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 7725/* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 7726/* File: armv5te/OP_SPUT_OBJECT.S */ 7727 /* 7728 * 32-bit SPUT handler for objects 7729 * 7730 * for: sput-object, sput-object-volatile 7731 */ 7732 /* op vAA, field@BBBB */ 7733 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7734 FETCH(r1, 1) @ r1<- field ref BBBB 7735 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7736 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7737 cmp r0, #0 @ is resolved entry null? 7738 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue 7739 ldr r9, [rSELF, #offThread_method] @ r9<- current method 7740 EXPORT_PC() @ resolve() could throw, so export now 7741 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 7742 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 7743 cmp r0, #0 @ success? 7744 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish 7745 b common_exceptionThrown @ no, handle exception 7746 7747 7748 7749/* ------------------------------ */ 7750 .balign 64 7751.L_OP_DISPATCH_FF: /* 0xff */ 7752/* File: armv5te/OP_DISPATCH_FF.S */ 7753 mov ip, rINST, lsr #8 @ ip<- extended opcode 7754 add ip, ip, #256 @ add offset for extended opcodes 7755 GOTO_OPCODE(ip) @ go to proper extended handler 7756 7757 7758/* ------------------------------ */ 7759 .balign 64 7760.L_OP_CONST_CLASS_JUMBO: /* 0x100 */ 7761/* File: armv5te/OP_CONST_CLASS_JUMBO.S */ 7762 /* const-class/jumbo vBBBB, Class@AAAAAAAA */ 7763 FETCH(r0, 1) @ r0<- aaaa (lo) 7764 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex 7765 FETCH(r1, 2) @ r1<- AAAA (hi) 7766 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 7767 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7768 FETCH(r9, 3) @ r9<- BBBB 7769 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa] 7770 cmp r0, #0 @ not yet resolved? 7771 beq .LOP_CONST_CLASS_JUMBO_resolve 7772 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 7773 GET_INST_OPCODE(ip) @ extract opcode from rINST 7774 SET_VREG(r0, r9) @ vBBBB<- r0 7775 GOTO_OPCODE(ip) @ jump to next instruction 7776 7777/* ------------------------------ */ 7778 .balign 64 7779.L_OP_CHECK_CAST_JUMBO: /* 0x101 */ 7780/* File: armv5te/OP_CHECK_CAST_JUMBO.S */ 7781 /* 7782 * Check to see if a cast from one class to another is allowed. 7783 */ 7784 /* check-cast/jumbo vBBBB, class@AAAAAAAA */ 7785 FETCH(r0, 1) @ r0<- aaaa (lo) 7786 FETCH(r2, 2) @ r2<- AAAA (hi) 7787 FETCH(r3, 3) @ r3<- BBBB 7788 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa 7789 GET_VREG(r9, r3) @ r9<- object 7790 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 7791 cmp r9, #0 @ is object null? 7792 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 7793 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds 7794 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 7795 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7796 cmp r1, #0 @ have we resolved this before? 7797 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now 7798.LOP_CHECK_CAST_JUMBO_resolved: 7799 cmp r0, r1 @ same class (trivial success)? 7800 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check 7801 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up 7802 7803/* ------------------------------ */ 7804 .balign 64 7805.L_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 7806/* File: armv5te/OP_INSTANCE_OF_JUMBO.S */ 7807 /* 7808 * Check to see if an object reference is an instance of a class. 7809 * 7810 * Most common situation is a non-null object, being compared against 7811 * an already-resolved class. 7812 * 7813 * TODO: convert most of this into a common subroutine, shared with 7814 * OP_INSTANCE_OF.S. 7815 */ 7816 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7817 FETCH(r3, 4) @ r3<- vCCCC 7818 FETCH(r9, 3) @ r9<- vBBBB 7819 GET_VREG(r0, r3) @ r0<- vCCCC (object) 7820 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 7821 cmp r0, #0 @ is object null? 7822 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0 7823 FETCH(r1, 1) @ r1<- aaaa (lo) 7824 FETCH(r3, 2) @ r3<- AAAA (hi) 7825 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 7826 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa 7827 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 7828 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7829 cmp r1, #0 @ have we resolved this before? 7830 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now 7831 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue 7832 7833/* ------------------------------ */ 7834 .balign 64 7835.L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 7836/* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */ 7837 /* 7838 * Create a new instance of a class. 7839 */ 7840 /* new-instance/jumbo vBBBB, class@AAAAAAAA */ 7841 FETCH(r0, 1) @ r0<- aaaa (lo) 7842 FETCH(r1, 2) @ r1<- AAAA (hi) 7843 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7844 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7845 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7846 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7847 EXPORT_PC() @ req'd for init, resolve, alloc 7848 cmp r0, #0 @ already resolved? 7849 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now 7850.LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class 7851 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 7852 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 7853 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now 7854.LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class 7855 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 7856 bl dvmAllocObject @ r0<- new object 7857 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue 7858 7859/* ------------------------------ */ 7860 .balign 64 7861.L_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 7862/* File: armv5te/OP_NEW_ARRAY_JUMBO.S */ 7863 /* 7864 * Allocate an array of objects, specified with the array class 7865 * and a count. 7866 * 7867 * The verifier guarantees that this is an array class, so we don't 7868 * check for it here. 7869 */ 7870 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7871 FETCH(r2, 1) @ r2<- aaaa (lo) 7872 FETCH(r3, 2) @ r3<- AAAA (hi) 7873 FETCH(r0, 4) @ r0<- vCCCC 7874 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa 7875 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7876 GET_VREG(r1, r0) @ r1<- vCCCC (array length) 7877 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7878 cmp r1, #0 @ check length 7879 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 7880 bmi common_errNegativeArraySize @ negative length, bail - len in r1 7881 cmp r0, #0 @ already resolved? 7882 EXPORT_PC() @ req'd for resolve, alloc 7883 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue 7884 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now 7885 7886/* ------------------------------ */ 7887 .balign 64 7888.L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 7889/* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */ 7890 /* 7891 * Create a new array with elements filled from registers. 7892 * 7893 * TODO: convert most of this into a common subroutine, shared with 7894 * OP_FILLED_NEW_ARRAY.S. 7895 */ 7896 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */ 7897 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7898 FETCH(r0, 1) @ r0<- aaaa (lo) 7899 FETCH(r1, 2) @ r1<- AAAA (hi) 7900 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7901 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7902 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7903 EXPORT_PC() @ need for resolve and alloc 7904 cmp r0, #0 @ already resolved? 7905 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on 79068: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 7907 mov r2, #0 @ r2<- false 7908 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7909 bl dvmResolveClass @ r0<- call(clazz, ref) 7910 cmp r0, #0 @ got null? 7911 beq common_exceptionThrown @ yes, handle exception 7912 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue 7913 7914/* ------------------------------ */ 7915 .balign 64 7916.L_OP_IGET_JUMBO: /* 0x106 */ 7917/* File: armv5te/OP_IGET_JUMBO.S */ 7918 /* 7919 * Jumbo 32-bit instance field get. 7920 * 7921 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7922 * iget-char/jumbo, iget-short/jumbo 7923 */ 7924 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7925 FETCH(r1, 1) @ r1<- aaaa (lo) 7926 FETCH(r2, 2) @ r2<- AAAA (hi) 7927 FETCH(r0, 4) @ r0<- CCCC 7928 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7929 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7930 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7931 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7932 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7933 cmp r0, #0 @ is resolved entry null? 7934 bne .LOP_IGET_JUMBO_finish @ no, already resolved 79358: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7936 EXPORT_PC() @ resolve() could throw 7937 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7938 bl dvmResolveInstField @ r0<- resolved InstField ptr 7939 b .LOP_IGET_JUMBO_resolved @ resolved, continue 7940 7941/* ------------------------------ */ 7942 .balign 64 7943.L_OP_IGET_WIDE_JUMBO: /* 0x107 */ 7944/* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 7945 /* 7946 * Jumbo 64-bit instance field get. 7947 */ 7948 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 7949 FETCH(r1, 1) @ r1<- aaaa (lo) 7950 FETCH(r2, 2) @ r2<- AAAA (hi) 7951 FETCH(r0, 4) @ r0<- CCCC 7952 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7953 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7954 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7955 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7956 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7957 cmp r0, #0 @ is resolved entry null? 7958 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved 7959 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7960 EXPORT_PC() @ resolve() could throw 7961 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7962 bl dvmResolveInstField @ r0<- resolved InstField ptr 7963 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue 7964 7965/* ------------------------------ */ 7966 .balign 64 7967.L_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 7968/* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 7969/* File: armv5te/OP_IGET_JUMBO.S */ 7970 /* 7971 * Jumbo 32-bit instance field get. 7972 * 7973 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7974 * iget-char/jumbo, iget-short/jumbo 7975 */ 7976 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7977 FETCH(r1, 1) @ r1<- aaaa (lo) 7978 FETCH(r2, 2) @ r2<- AAAA (hi) 7979 FETCH(r0, 4) @ r0<- CCCC 7980 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7981 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7982 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7983 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7984 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7985 cmp r0, #0 @ is resolved entry null? 7986 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved 79878: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7988 EXPORT_PC() @ resolve() could throw 7989 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7990 bl dvmResolveInstField @ r0<- resolved InstField ptr 7991 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue 7992 7993 7994/* ------------------------------ */ 7995 .balign 64 7996.L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 7997/* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */ 7998@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" } 7999/* File: armv5te/OP_IGET_JUMBO.S */ 8000 /* 8001 * Jumbo 32-bit instance field get. 8002 * 8003 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8004 * iget-char/jumbo, iget-short/jumbo 8005 */ 8006 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8007 FETCH(r1, 1) @ r1<- aaaa (lo) 8008 FETCH(r2, 2) @ r2<- AAAA (hi) 8009 FETCH(r0, 4) @ r0<- CCCC 8010 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8011 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8012 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8013 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8014 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8015 cmp r0, #0 @ is resolved entry null? 8016 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved 80178: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8018 EXPORT_PC() @ resolve() could throw 8019 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8020 bl dvmResolveInstField @ r0<- resolved InstField ptr 8021 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue 8022 8023 8024/* ------------------------------ */ 8025 .balign 64 8026.L_OP_IGET_BYTE_JUMBO: /* 0x10a */ 8027/* File: armv5te/OP_IGET_BYTE_JUMBO.S */ 8028@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" } 8029/* File: armv5te/OP_IGET_JUMBO.S */ 8030 /* 8031 * Jumbo 32-bit instance field get. 8032 * 8033 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8034 * iget-char/jumbo, iget-short/jumbo 8035 */ 8036 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8037 FETCH(r1, 1) @ r1<- aaaa (lo) 8038 FETCH(r2, 2) @ r2<- AAAA (hi) 8039 FETCH(r0, 4) @ r0<- CCCC 8040 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8041 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8042 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8043 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8044 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8045 cmp r0, #0 @ is resolved entry null? 8046 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved 80478: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8048 EXPORT_PC() @ resolve() could throw 8049 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8050 bl dvmResolveInstField @ r0<- resolved InstField ptr 8051 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue 8052 8053 8054/* ------------------------------ */ 8055 .balign 64 8056.L_OP_IGET_CHAR_JUMBO: /* 0x10b */ 8057/* File: armv5te/OP_IGET_CHAR_JUMBO.S */ 8058@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" } 8059/* File: armv5te/OP_IGET_JUMBO.S */ 8060 /* 8061 * Jumbo 32-bit instance field get. 8062 * 8063 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8064 * iget-char/jumbo, iget-short/jumbo 8065 */ 8066 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8067 FETCH(r1, 1) @ r1<- aaaa (lo) 8068 FETCH(r2, 2) @ r2<- AAAA (hi) 8069 FETCH(r0, 4) @ r0<- CCCC 8070 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8071 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8072 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8073 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8074 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8075 cmp r0, #0 @ is resolved entry null? 8076 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved 80778: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8078 EXPORT_PC() @ resolve() could throw 8079 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8080 bl dvmResolveInstField @ r0<- resolved InstField ptr 8081 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue 8082 8083 8084/* ------------------------------ */ 8085 .balign 64 8086.L_OP_IGET_SHORT_JUMBO: /* 0x10c */ 8087/* File: armv5te/OP_IGET_SHORT_JUMBO.S */ 8088@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" } 8089/* File: armv5te/OP_IGET_JUMBO.S */ 8090 /* 8091 * Jumbo 32-bit instance field get. 8092 * 8093 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8094 * iget-char/jumbo, iget-short/jumbo 8095 */ 8096 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8097 FETCH(r1, 1) @ r1<- aaaa (lo) 8098 FETCH(r2, 2) @ r2<- AAAA (hi) 8099 FETCH(r0, 4) @ r0<- CCCC 8100 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8101 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8102 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8103 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8104 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8105 cmp r0, #0 @ is resolved entry null? 8106 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved 81078: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8108 EXPORT_PC() @ resolve() could throw 8109 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8110 bl dvmResolveInstField @ r0<- resolved InstField ptr 8111 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue 8112 8113 8114/* ------------------------------ */ 8115 .balign 64 8116.L_OP_IPUT_JUMBO: /* 0x10d */ 8117/* File: armv5te/OP_IPUT_JUMBO.S */ 8118 /* 8119 * Jumbo 32-bit instance field put. 8120 * 8121 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8122 * iput-short/jumbo 8123 */ 8124 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8125 FETCH(r1, 1) @ r1<- aaaa (lo) 8126 FETCH(r2, 2) @ r2<- AAAA (hi) 8127 FETCH(r0, 4) @ r0<- CCCC 8128 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8129 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8130 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8131 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8132 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8133 cmp r0, #0 @ is resolved entry null? 8134 bne .LOP_IPUT_JUMBO_finish @ no, already resolved 81358: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8136 EXPORT_PC() @ resolve() could throw 8137 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8138 bl dvmResolveInstField @ r0<- resolved InstField ptr 8139 b .LOP_IPUT_JUMBO_resolved @ resolved, continue 8140 8141/* ------------------------------ */ 8142 .balign 64 8143.L_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 8144/* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 8145 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8146 FETCH(r1, 1) @ r1<- aaaa (lo) 8147 FETCH(r2, 2) @ r2<- AAAA (hi) 8148 FETCH(r0, 4) @ r0<- CCCC 8149 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8150 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8151 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 8152 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 8153 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8154 cmp r0, #0 @ is resolved entry null? 8155 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved 81568: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8157 EXPORT_PC() @ resolve() could throw 8158 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8159 bl dvmResolveInstField @ r0<- resolved InstField ptr 8160 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue 8161 8162/* ------------------------------ */ 8163 .balign 64 8164.L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 8165/* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 8166 /* 8167 * Jumbo 32-bit instance field put. 8168 */ 8169 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8170 FETCH(r1, 1) @ r1<- aaaa (lo) 8171 FETCH(r2, 2) @ r2<- AAAA (hi) 8172 FETCH(r0, 4) @ r0<- CCCC 8173 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8174 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8175 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8176 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8177 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8178 cmp r0, #0 @ is resolved entry null? 8179 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved 81808: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8181 EXPORT_PC() @ resolve() could throw 8182 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8183 bl dvmResolveInstField @ r0<- resolved InstField ptr 8184 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue 8185 8186/* ------------------------------ */ 8187 .balign 64 8188.L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 8189/* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */ 8190@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" } 8191/* File: armv5te/OP_IPUT_JUMBO.S */ 8192 /* 8193 * Jumbo 32-bit instance field put. 8194 * 8195 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8196 * iput-short/jumbo 8197 */ 8198 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8199 FETCH(r1, 1) @ r1<- aaaa (lo) 8200 FETCH(r2, 2) @ r2<- AAAA (hi) 8201 FETCH(r0, 4) @ r0<- CCCC 8202 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8203 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8204 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8205 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8206 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8207 cmp r0, #0 @ is resolved entry null? 8208 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved 82098: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8210 EXPORT_PC() @ resolve() could throw 8211 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8212 bl dvmResolveInstField @ r0<- resolved InstField ptr 8213 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue 8214 8215 8216/* ------------------------------ */ 8217 .balign 64 8218.L_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 8219/* File: armv5te/OP_IPUT_BYTE_JUMBO.S */ 8220@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" } 8221/* File: armv5te/OP_IPUT_JUMBO.S */ 8222 /* 8223 * Jumbo 32-bit instance field put. 8224 * 8225 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8226 * iput-short/jumbo 8227 */ 8228 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8229 FETCH(r1, 1) @ r1<- aaaa (lo) 8230 FETCH(r2, 2) @ r2<- AAAA (hi) 8231 FETCH(r0, 4) @ r0<- CCCC 8232 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8233 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8234 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8235 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8236 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8237 cmp r0, #0 @ is resolved entry null? 8238 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved 82398: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8240 EXPORT_PC() @ resolve() could throw 8241 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8242 bl dvmResolveInstField @ r0<- resolved InstField ptr 8243 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue 8244 8245 8246/* ------------------------------ */ 8247 .balign 64 8248.L_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 8249/* File: armv5te/OP_IPUT_CHAR_JUMBO.S */ 8250@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" } 8251/* File: armv5te/OP_IPUT_JUMBO.S */ 8252 /* 8253 * Jumbo 32-bit instance field put. 8254 * 8255 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8256 * iput-short/jumbo 8257 */ 8258 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8259 FETCH(r1, 1) @ r1<- aaaa (lo) 8260 FETCH(r2, 2) @ r2<- AAAA (hi) 8261 FETCH(r0, 4) @ r0<- CCCC 8262 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8263 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8264 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8265 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8266 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8267 cmp r0, #0 @ is resolved entry null? 8268 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved 82698: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8270 EXPORT_PC() @ resolve() could throw 8271 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8272 bl dvmResolveInstField @ r0<- resolved InstField ptr 8273 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue 8274 8275 8276/* ------------------------------ */ 8277 .balign 64 8278.L_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 8279/* File: armv5te/OP_IPUT_SHORT_JUMBO.S */ 8280@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" } 8281/* File: armv5te/OP_IPUT_JUMBO.S */ 8282 /* 8283 * Jumbo 32-bit instance field put. 8284 * 8285 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8286 * iput-short/jumbo 8287 */ 8288 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8289 FETCH(r1, 1) @ r1<- aaaa (lo) 8290 FETCH(r2, 2) @ r2<- AAAA (hi) 8291 FETCH(r0, 4) @ r0<- CCCC 8292 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8293 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8294 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8295 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8296 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8297 cmp r0, #0 @ is resolved entry null? 8298 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved 82998: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8300 EXPORT_PC() @ resolve() could throw 8301 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8302 bl dvmResolveInstField @ r0<- resolved InstField ptr 8303 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue 8304 8305 8306/* ------------------------------ */ 8307 .balign 64 8308.L_OP_SGET_JUMBO: /* 0x114 */ 8309/* File: armv5te/OP_SGET_JUMBO.S */ 8310 /* 8311 * Jumbo 32-bit SGET handler. 8312 * 8313 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8314 * sget-char/jumbo, sget-short/jumbo 8315 */ 8316 /* exop vBBBB, field@AAAAAAAA */ 8317 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8318 FETCH(r0, 1) @ r0<- aaaa (lo) 8319 FETCH(r1, 2) @ r1<- AAAA (hi) 8320 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8321 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8322 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8323 cmp r0, #0 @ is resolved entry null? 8324 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve 8325.LOP_SGET_JUMBO_finish: @ field ptr in r0 8326 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8327 @ no-op @ acquiring load 8328 FETCH(r2, 3) @ r2<- BBBB 8329 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8330 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8331 GET_INST_OPCODE(ip) @ extract opcode from rINST 8332 GOTO_OPCODE(ip) @ jump to next instruction 8333 8334/* ------------------------------ */ 8335 .balign 64 8336.L_OP_SGET_WIDE_JUMBO: /* 0x115 */ 8337/* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 8338 /* 8339 * Jumbo 64-bit SGET handler. 8340 */ 8341 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 8342 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8343 FETCH(r0, 1) @ r0<- aaaa (lo) 8344 FETCH(r1, 2) @ r1<- AAAA (hi) 8345 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8346 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8347 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8348 cmp r0, #0 @ is resolved entry null? 8349 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve 8350.LOP_SGET_WIDE_JUMBO_finish: 8351 FETCH(r9, 3) @ r9<- BBBB 8352 .if 0 8353 add r0, r0, #offStaticField_value @ r0<- pointer to data 8354 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 8355 .else 8356 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 8357 .endif 8358 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8359 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8360 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 8361 GET_INST_OPCODE(ip) @ extract opcode from rINST 8362 GOTO_OPCODE(ip) @ jump to next instruction 8363 8364/* ------------------------------ */ 8365 .balign 64 8366.L_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 8367/* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 8368/* File: armv5te/OP_SGET_JUMBO.S */ 8369 /* 8370 * Jumbo 32-bit SGET handler. 8371 * 8372 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8373 * sget-char/jumbo, sget-short/jumbo 8374 */ 8375 /* exop vBBBB, field@AAAAAAAA */ 8376 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8377 FETCH(r0, 1) @ r0<- aaaa (lo) 8378 FETCH(r1, 2) @ r1<- AAAA (hi) 8379 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8380 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8381 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8382 cmp r0, #0 @ is resolved entry null? 8383 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve 8384.LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0 8385 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8386 @ no-op @ acquiring load 8387 FETCH(r2, 3) @ r2<- BBBB 8388 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8389 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8390 GET_INST_OPCODE(ip) @ extract opcode from rINST 8391 GOTO_OPCODE(ip) @ jump to next instruction 8392 8393 8394/* ------------------------------ */ 8395 .balign 64 8396.L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 8397/* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */ 8398/* File: armv5te/OP_SGET_JUMBO.S */ 8399 /* 8400 * Jumbo 32-bit SGET handler. 8401 * 8402 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8403 * sget-char/jumbo, sget-short/jumbo 8404 */ 8405 /* exop vBBBB, field@AAAAAAAA */ 8406 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8407 FETCH(r0, 1) @ r0<- aaaa (lo) 8408 FETCH(r1, 2) @ r1<- AAAA (hi) 8409 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8410 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8411 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8412 cmp r0, #0 @ is resolved entry null? 8413 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve 8414.LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0 8415 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8416 @ no-op @ acquiring load 8417 FETCH(r2, 3) @ r2<- BBBB 8418 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8419 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8420 GET_INST_OPCODE(ip) @ extract opcode from rINST 8421 GOTO_OPCODE(ip) @ jump to next instruction 8422 8423 8424/* ------------------------------ */ 8425 .balign 64 8426.L_OP_SGET_BYTE_JUMBO: /* 0x118 */ 8427/* File: armv5te/OP_SGET_BYTE_JUMBO.S */ 8428/* File: armv5te/OP_SGET_JUMBO.S */ 8429 /* 8430 * Jumbo 32-bit SGET handler. 8431 * 8432 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8433 * sget-char/jumbo, sget-short/jumbo 8434 */ 8435 /* exop vBBBB, field@AAAAAAAA */ 8436 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8437 FETCH(r0, 1) @ r0<- aaaa (lo) 8438 FETCH(r1, 2) @ r1<- AAAA (hi) 8439 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8440 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8441 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8442 cmp r0, #0 @ is resolved entry null? 8443 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve 8444.LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0 8445 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8446 @ no-op @ acquiring load 8447 FETCH(r2, 3) @ r2<- BBBB 8448 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8449 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8450 GET_INST_OPCODE(ip) @ extract opcode from rINST 8451 GOTO_OPCODE(ip) @ jump to next instruction 8452 8453 8454/* ------------------------------ */ 8455 .balign 64 8456.L_OP_SGET_CHAR_JUMBO: /* 0x119 */ 8457/* File: armv5te/OP_SGET_CHAR_JUMBO.S */ 8458/* File: armv5te/OP_SGET_JUMBO.S */ 8459 /* 8460 * Jumbo 32-bit SGET handler. 8461 * 8462 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8463 * sget-char/jumbo, sget-short/jumbo 8464 */ 8465 /* exop vBBBB, field@AAAAAAAA */ 8466 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8467 FETCH(r0, 1) @ r0<- aaaa (lo) 8468 FETCH(r1, 2) @ r1<- AAAA (hi) 8469 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8470 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8471 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8472 cmp r0, #0 @ is resolved entry null? 8473 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve 8474.LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0 8475 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8476 @ no-op @ acquiring load 8477 FETCH(r2, 3) @ r2<- BBBB 8478 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8479 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8480 GET_INST_OPCODE(ip) @ extract opcode from rINST 8481 GOTO_OPCODE(ip) @ jump to next instruction 8482 8483 8484/* ------------------------------ */ 8485 .balign 64 8486.L_OP_SGET_SHORT_JUMBO: /* 0x11a */ 8487/* File: armv5te/OP_SGET_SHORT_JUMBO.S */ 8488/* File: armv5te/OP_SGET_JUMBO.S */ 8489 /* 8490 * Jumbo 32-bit SGET handler. 8491 * 8492 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8493 * sget-char/jumbo, sget-short/jumbo 8494 */ 8495 /* exop vBBBB, field@AAAAAAAA */ 8496 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8497 FETCH(r0, 1) @ r0<- aaaa (lo) 8498 FETCH(r1, 2) @ r1<- AAAA (hi) 8499 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8500 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8501 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8502 cmp r0, #0 @ is resolved entry null? 8503 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve 8504.LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0 8505 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8506 @ no-op @ acquiring load 8507 FETCH(r2, 3) @ r2<- BBBB 8508 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8509 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8510 GET_INST_OPCODE(ip) @ extract opcode from rINST 8511 GOTO_OPCODE(ip) @ jump to next instruction 8512 8513 8514/* ------------------------------ */ 8515 .balign 64 8516.L_OP_SPUT_JUMBO: /* 0x11b */ 8517/* File: armv5te/OP_SPUT_JUMBO.S */ 8518 /* 8519 * Jumbo 32-bit SPUT handler. 8520 * 8521 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8522 * sput-short/jumbo 8523 */ 8524 /* exop vBBBB, field@AAAAAAAA */ 8525 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8526 FETCH(r0, 1) @ r0<- aaaa (lo) 8527 FETCH(r1, 2) @ r1<- AAAA (hi) 8528 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8529 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8530 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8531 cmp r0, #0 @ is resolved entry null? 8532 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve 8533.LOP_SPUT_JUMBO_finish: @ field ptr in r0 8534 FETCH(r2, 3) @ r2<- BBBB 8535 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8536 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8537 GET_INST_OPCODE(ip) @ extract opcode from rINST 8538 @ no-op @ releasing store 8539 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8540 GOTO_OPCODE(ip) @ jump to next instruction 8541 8542/* ------------------------------ */ 8543 .balign 64 8544.L_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 8545/* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 8546 /* 8547 * Jumbo 64-bit SPUT handler. 8548 */ 8549 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 8550 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 8551 FETCH(r1, 1) @ r1<- aaaa (lo) 8552 FETCH(r2, 2) @ r2<- AAAA (hi) 8553 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 8554 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8555 FETCH(r9, 3) @ r9<- BBBB 8556 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 8557 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8558 cmp r2, #0 @ is resolved entry null? 8559 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve 8560.LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9 8561 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8562 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 8563 GET_INST_OPCODE(r10) @ extract opcode from rINST 8564 .if 0 8565 add r2, r2, #offStaticField_value @ r2<- pointer to data 8566 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 8567 .else 8568 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 8569 .endif 8570 GOTO_OPCODE(r10) @ jump to next instruction 8571 8572/* ------------------------------ */ 8573 .balign 64 8574.L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 8575/* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 8576 /* 8577 * Jumbo 32-bit SPUT handler for objects 8578 */ 8579 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 8580 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8581 FETCH(r0, 1) @ r0<- aaaa (lo) 8582 FETCH(r1, 2) @ r1<- AAAA (hi) 8583 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8584 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8585 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8586 cmp r0, #0 @ is resolved entry null? 8587 bne .LOP_SPUT_OBJECT_JUMBO_finish @ no, continue 8588 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8589 EXPORT_PC() @ resolve() could throw, so export now 8590 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 8591 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8592 cmp r0, #0 @ success? 8593 bne .LOP_SPUT_OBJECT_JUMBO_finish @ yes, finish 8594 b common_exceptionThrown @ no, handle exception 8595 8596/* ------------------------------ */ 8597 .balign 64 8598.L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 8599/* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */ 8600/* File: armv5te/OP_SPUT_JUMBO.S */ 8601 /* 8602 * Jumbo 32-bit SPUT handler. 8603 * 8604 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8605 * sput-short/jumbo 8606 */ 8607 /* exop vBBBB, field@AAAAAAAA */ 8608 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8609 FETCH(r0, 1) @ r0<- aaaa (lo) 8610 FETCH(r1, 2) @ r1<- AAAA (hi) 8611 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8612 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8613 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8614 cmp r0, #0 @ is resolved entry null? 8615 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve 8616.LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0 8617 FETCH(r2, 3) @ r2<- BBBB 8618 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8619 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8620 GET_INST_OPCODE(ip) @ extract opcode from rINST 8621 @ no-op @ releasing store 8622 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8623 GOTO_OPCODE(ip) @ jump to next instruction 8624 8625 8626/* ------------------------------ */ 8627 .balign 64 8628.L_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 8629/* File: armv5te/OP_SPUT_BYTE_JUMBO.S */ 8630/* File: armv5te/OP_SPUT_JUMBO.S */ 8631 /* 8632 * Jumbo 32-bit SPUT handler. 8633 * 8634 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8635 * sput-short/jumbo 8636 */ 8637 /* exop vBBBB, field@AAAAAAAA */ 8638 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8639 FETCH(r0, 1) @ r0<- aaaa (lo) 8640 FETCH(r1, 2) @ r1<- AAAA (hi) 8641 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8642 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8643 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8644 cmp r0, #0 @ is resolved entry null? 8645 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve 8646.LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0 8647 FETCH(r2, 3) @ r2<- BBBB 8648 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8649 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8650 GET_INST_OPCODE(ip) @ extract opcode from rINST 8651 @ no-op @ releasing store 8652 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8653 GOTO_OPCODE(ip) @ jump to next instruction 8654 8655 8656/* ------------------------------ */ 8657 .balign 64 8658.L_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 8659/* File: armv5te/OP_SPUT_CHAR_JUMBO.S */ 8660/* File: armv5te/OP_SPUT_JUMBO.S */ 8661 /* 8662 * Jumbo 32-bit SPUT handler. 8663 * 8664 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8665 * sput-short/jumbo 8666 */ 8667 /* exop vBBBB, field@AAAAAAAA */ 8668 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8669 FETCH(r0, 1) @ r0<- aaaa (lo) 8670 FETCH(r1, 2) @ r1<- AAAA (hi) 8671 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8672 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8673 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8674 cmp r0, #0 @ is resolved entry null? 8675 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve 8676.LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0 8677 FETCH(r2, 3) @ r2<- BBBB 8678 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8679 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8680 GET_INST_OPCODE(ip) @ extract opcode from rINST 8681 @ no-op @ releasing store 8682 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8683 GOTO_OPCODE(ip) @ jump to next instruction 8684 8685 8686/* ------------------------------ */ 8687 .balign 64 8688.L_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 8689/* File: armv5te/OP_SPUT_SHORT_JUMBO.S */ 8690/* File: armv5te/OP_SPUT_JUMBO.S */ 8691 /* 8692 * Jumbo 32-bit SPUT handler. 8693 * 8694 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8695 * sput-short/jumbo 8696 */ 8697 /* exop vBBBB, field@AAAAAAAA */ 8698 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8699 FETCH(r0, 1) @ r0<- aaaa (lo) 8700 FETCH(r1, 2) @ r1<- AAAA (hi) 8701 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8702 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8703 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8704 cmp r0, #0 @ is resolved entry null? 8705 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve 8706.LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0 8707 FETCH(r2, 3) @ r2<- BBBB 8708 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8709 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8710 GET_INST_OPCODE(ip) @ extract opcode from rINST 8711 @ no-op @ releasing store 8712 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8713 GOTO_OPCODE(ip) @ jump to next instruction 8714 8715 8716/* ------------------------------ */ 8717 .balign 64 8718.L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 8719/* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */ 8720 /* 8721 * Handle a virtual method call. 8722 */ 8723 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8724 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8725 FETCH(r0, 1) @ r1<- aaaa (lo) 8726 FETCH(r1, 2) @ r1<- AAAA (hi) 8727 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8728 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8729 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8730 cmp r0, #0 @ already resolved? 8731 EXPORT_PC() @ must export for invoke 8732 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on 8733 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8734 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8735 mov r2, #METHOD_VIRTUAL @ resolver method type 8736 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8737 cmp r0, #0 @ got null? 8738 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue 8739 b common_exceptionThrown @ yes, handle exception 8740 8741/* ------------------------------ */ 8742 .balign 64 8743.L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 8744/* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */ 8745 /* 8746 * Handle a "super" method call. 8747 */ 8748 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8749 FETCH(r10, 4) @ r10<- CCCC 8750 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8751 FETCH(r0, 1) @ r1<- aaaa (lo) 8752 FETCH(r1, 2) @ r1<- AAAA (hi) 8753 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8754 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8755 GET_VREG(r2, r10) @ r2<- "this" ptr 8756 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8757 cmp r2, #0 @ null "this"? 8758 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8759 beq common_errNullObject @ null "this", throw exception 8760 cmp r0, #0 @ already resolved? 8761 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 8762 EXPORT_PC() @ must export for invoke 8763 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on 8764 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now 8765 8766/* ------------------------------ */ 8767 .balign 64 8768.L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 8769/* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */ 8770 /* 8771 * Handle a direct method call. 8772 * 8773 * (We could defer the "is 'this' pointer null" test to the common 8774 * method invocation code, and use a flag to indicate that static 8775 * calls don't count. If we do this as part of copying the arguments 8776 * out we could avoiding loading the first arg twice.) 8777 * 8778 */ 8779 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8780 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8781 FETCH(r0, 1) @ r1<- aaaa (lo) 8782 FETCH(r1, 2) @ r1<- AAAA (hi) 8783 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8784 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8785 FETCH(r10, 4) @ r10<- CCCC 8786 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8787 cmp r0, #0 @ already resolved? 8788 EXPORT_PC() @ must export for invoke 8789 GET_VREG(r2, r10) @ r2<- "this" ptr 8790 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now 8791.LOP_INVOKE_DIRECT_JUMBO_finish: 8792 cmp r2, #0 @ null "this" ref? 8793 bne common_invokeMethodJumbo @ no, continue on 8794 b common_errNullObject @ yes, throw exception 8795 8796/* ------------------------------ */ 8797 .balign 64 8798.L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 8799/* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */ 8800 /* 8801 * Handle a static method call. 8802 */ 8803 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8804 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8805 FETCH(r0, 1) @ r1<- aaaa (lo) 8806 FETCH(r1, 2) @ r1<- AAAA (hi) 8807 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8808 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8809 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8810 cmp r0, #0 @ already resolved? 8811 EXPORT_PC() @ must export for invoke 8812 bne common_invokeMethodJumbo @ yes, continue on 88130: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8814 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8815 mov r2, #METHOD_STATIC @ resolver method type 8816 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8817 cmp r0, #0 @ got null? 8818 bne common_invokeMethodJumbo @ no, continue 8819 b common_exceptionThrown @ yes, handle exception 8820 8821/* ------------------------------ */ 8822 .balign 64 8823.L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 8824/* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */ 8825 /* 8826 * Handle an interface method call. 8827 */ 8828 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8829 FETCH(r2, 4) @ r2<- CCCC 8830 FETCH(r0, 1) @ r0<- aaaa (lo) 8831 FETCH(r1, 2) @ r1<- AAAA (hi) 8832 EXPORT_PC() @ must export for invoke 8833 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8834 GET_VREG(r0, r2) @ r0<- first arg ("this") 8835 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 8836 cmp r0, #0 @ null obj? 8837 ldr r2, [rSELF, #offThread_method] @ r2<- method 8838 beq common_errNullObject @ yes, fail 8839 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 8840 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 8841 cmp r0, #0 @ failed? 8842 beq common_exceptionThrown @ yes, handle exception 8843 b common_invokeMethodJumbo @ jump to common handler 8844 8845/* ------------------------------ */ 8846 .balign 64 8847.L_OP_UNUSED_27FF: /* 0x127 */ 8848/* File: armv5te/OP_UNUSED_27FF.S */ 8849/* File: armv5te/unused.S */ 8850 bl common_abort 8851 8852 8853/* ------------------------------ */ 8854 .balign 64 8855.L_OP_UNUSED_28FF: /* 0x128 */ 8856/* File: armv5te/OP_UNUSED_28FF.S */ 8857/* File: armv5te/unused.S */ 8858 bl common_abort 8859 8860 8861/* ------------------------------ */ 8862 .balign 64 8863.L_OP_UNUSED_29FF: /* 0x129 */ 8864/* File: armv5te/OP_UNUSED_29FF.S */ 8865/* File: armv5te/unused.S */ 8866 bl common_abort 8867 8868 8869/* ------------------------------ */ 8870 .balign 64 8871.L_OP_UNUSED_2AFF: /* 0x12a */ 8872/* File: armv5te/OP_UNUSED_2AFF.S */ 8873/* File: armv5te/unused.S */ 8874 bl common_abort 8875 8876 8877/* ------------------------------ */ 8878 .balign 64 8879.L_OP_UNUSED_2BFF: /* 0x12b */ 8880/* File: armv5te/OP_UNUSED_2BFF.S */ 8881/* File: armv5te/unused.S */ 8882 bl common_abort 8883 8884 8885/* ------------------------------ */ 8886 .balign 64 8887.L_OP_UNUSED_2CFF: /* 0x12c */ 8888/* File: armv5te/OP_UNUSED_2CFF.S */ 8889/* File: armv5te/unused.S */ 8890 bl common_abort 8891 8892 8893/* ------------------------------ */ 8894 .balign 64 8895.L_OP_UNUSED_2DFF: /* 0x12d */ 8896/* File: armv5te/OP_UNUSED_2DFF.S */ 8897/* File: armv5te/unused.S */ 8898 bl common_abort 8899 8900 8901/* ------------------------------ */ 8902 .balign 64 8903.L_OP_UNUSED_2EFF: /* 0x12e */ 8904/* File: armv5te/OP_UNUSED_2EFF.S */ 8905/* File: armv5te/unused.S */ 8906 bl common_abort 8907 8908 8909/* ------------------------------ */ 8910 .balign 64 8911.L_OP_UNUSED_2FFF: /* 0x12f */ 8912/* File: armv5te/OP_UNUSED_2FFF.S */ 8913/* File: armv5te/unused.S */ 8914 bl common_abort 8915 8916 8917/* ------------------------------ */ 8918 .balign 64 8919.L_OP_UNUSED_30FF: /* 0x130 */ 8920/* File: armv5te/OP_UNUSED_30FF.S */ 8921/* File: armv5te/unused.S */ 8922 bl common_abort 8923 8924 8925/* ------------------------------ */ 8926 .balign 64 8927.L_OP_UNUSED_31FF: /* 0x131 */ 8928/* File: armv5te/OP_UNUSED_31FF.S */ 8929/* File: armv5te/unused.S */ 8930 bl common_abort 8931 8932 8933/* ------------------------------ */ 8934 .balign 64 8935.L_OP_UNUSED_32FF: /* 0x132 */ 8936/* File: armv5te/OP_UNUSED_32FF.S */ 8937/* File: armv5te/unused.S */ 8938 bl common_abort 8939 8940 8941/* ------------------------------ */ 8942 .balign 64 8943.L_OP_UNUSED_33FF: /* 0x133 */ 8944/* File: armv5te/OP_UNUSED_33FF.S */ 8945/* File: armv5te/unused.S */ 8946 bl common_abort 8947 8948 8949/* ------------------------------ */ 8950 .balign 64 8951.L_OP_UNUSED_34FF: /* 0x134 */ 8952/* File: armv5te/OP_UNUSED_34FF.S */ 8953/* File: armv5te/unused.S */ 8954 bl common_abort 8955 8956 8957/* ------------------------------ */ 8958 .balign 64 8959.L_OP_UNUSED_35FF: /* 0x135 */ 8960/* File: armv5te/OP_UNUSED_35FF.S */ 8961/* File: armv5te/unused.S */ 8962 bl common_abort 8963 8964 8965/* ------------------------------ */ 8966 .balign 64 8967.L_OP_UNUSED_36FF: /* 0x136 */ 8968/* File: armv5te/OP_UNUSED_36FF.S */ 8969/* File: armv5te/unused.S */ 8970 bl common_abort 8971 8972 8973/* ------------------------------ */ 8974 .balign 64 8975.L_OP_UNUSED_37FF: /* 0x137 */ 8976/* File: armv5te/OP_UNUSED_37FF.S */ 8977/* File: armv5te/unused.S */ 8978 bl common_abort 8979 8980 8981/* ------------------------------ */ 8982 .balign 64 8983.L_OP_UNUSED_38FF: /* 0x138 */ 8984/* File: armv5te/OP_UNUSED_38FF.S */ 8985/* File: armv5te/unused.S */ 8986 bl common_abort 8987 8988 8989/* ------------------------------ */ 8990 .balign 64 8991.L_OP_UNUSED_39FF: /* 0x139 */ 8992/* File: armv5te/OP_UNUSED_39FF.S */ 8993/* File: armv5te/unused.S */ 8994 bl common_abort 8995 8996 8997/* ------------------------------ */ 8998 .balign 64 8999.L_OP_UNUSED_3AFF: /* 0x13a */ 9000/* File: armv5te/OP_UNUSED_3AFF.S */ 9001/* File: armv5te/unused.S */ 9002 bl common_abort 9003 9004 9005/* ------------------------------ */ 9006 .balign 64 9007.L_OP_UNUSED_3BFF: /* 0x13b */ 9008/* File: armv5te/OP_UNUSED_3BFF.S */ 9009/* File: armv5te/unused.S */ 9010 bl common_abort 9011 9012 9013/* ------------------------------ */ 9014 .balign 64 9015.L_OP_UNUSED_3CFF: /* 0x13c */ 9016/* File: armv5te/OP_UNUSED_3CFF.S */ 9017/* File: armv5te/unused.S */ 9018 bl common_abort 9019 9020 9021/* ------------------------------ */ 9022 .balign 64 9023.L_OP_UNUSED_3DFF: /* 0x13d */ 9024/* File: armv5te/OP_UNUSED_3DFF.S */ 9025/* File: armv5te/unused.S */ 9026 bl common_abort 9027 9028 9029/* ------------------------------ */ 9030 .balign 64 9031.L_OP_UNUSED_3EFF: /* 0x13e */ 9032/* File: armv5te/OP_UNUSED_3EFF.S */ 9033/* File: armv5te/unused.S */ 9034 bl common_abort 9035 9036 9037/* ------------------------------ */ 9038 .balign 64 9039.L_OP_UNUSED_3FFF: /* 0x13f */ 9040/* File: armv5te/OP_UNUSED_3FFF.S */ 9041/* File: armv5te/unused.S */ 9042 bl common_abort 9043 9044 9045/* ------------------------------ */ 9046 .balign 64 9047.L_OP_UNUSED_40FF: /* 0x140 */ 9048/* File: armv5te/OP_UNUSED_40FF.S */ 9049/* File: armv5te/unused.S */ 9050 bl common_abort 9051 9052 9053/* ------------------------------ */ 9054 .balign 64 9055.L_OP_UNUSED_41FF: /* 0x141 */ 9056/* File: armv5te/OP_UNUSED_41FF.S */ 9057/* File: armv5te/unused.S */ 9058 bl common_abort 9059 9060 9061/* ------------------------------ */ 9062 .balign 64 9063.L_OP_UNUSED_42FF: /* 0x142 */ 9064/* File: armv5te/OP_UNUSED_42FF.S */ 9065/* File: armv5te/unused.S */ 9066 bl common_abort 9067 9068 9069/* ------------------------------ */ 9070 .balign 64 9071.L_OP_UNUSED_43FF: /* 0x143 */ 9072/* File: armv5te/OP_UNUSED_43FF.S */ 9073/* File: armv5te/unused.S */ 9074 bl common_abort 9075 9076 9077/* ------------------------------ */ 9078 .balign 64 9079.L_OP_UNUSED_44FF: /* 0x144 */ 9080/* File: armv5te/OP_UNUSED_44FF.S */ 9081/* File: armv5te/unused.S */ 9082 bl common_abort 9083 9084 9085/* ------------------------------ */ 9086 .balign 64 9087.L_OP_UNUSED_45FF: /* 0x145 */ 9088/* File: armv5te/OP_UNUSED_45FF.S */ 9089/* File: armv5te/unused.S */ 9090 bl common_abort 9091 9092 9093/* ------------------------------ */ 9094 .balign 64 9095.L_OP_UNUSED_46FF: /* 0x146 */ 9096/* File: armv5te/OP_UNUSED_46FF.S */ 9097/* File: armv5te/unused.S */ 9098 bl common_abort 9099 9100 9101/* ------------------------------ */ 9102 .balign 64 9103.L_OP_UNUSED_47FF: /* 0x147 */ 9104/* File: armv5te/OP_UNUSED_47FF.S */ 9105/* File: armv5te/unused.S */ 9106 bl common_abort 9107 9108 9109/* ------------------------------ */ 9110 .balign 64 9111.L_OP_UNUSED_48FF: /* 0x148 */ 9112/* File: armv5te/OP_UNUSED_48FF.S */ 9113/* File: armv5te/unused.S */ 9114 bl common_abort 9115 9116 9117/* ------------------------------ */ 9118 .balign 64 9119.L_OP_UNUSED_49FF: /* 0x149 */ 9120/* File: armv5te/OP_UNUSED_49FF.S */ 9121/* File: armv5te/unused.S */ 9122 bl common_abort 9123 9124 9125/* ------------------------------ */ 9126 .balign 64 9127.L_OP_UNUSED_4AFF: /* 0x14a */ 9128/* File: armv5te/OP_UNUSED_4AFF.S */ 9129/* File: armv5te/unused.S */ 9130 bl common_abort 9131 9132 9133/* ------------------------------ */ 9134 .balign 64 9135.L_OP_UNUSED_4BFF: /* 0x14b */ 9136/* File: armv5te/OP_UNUSED_4BFF.S */ 9137/* File: armv5te/unused.S */ 9138 bl common_abort 9139 9140 9141/* ------------------------------ */ 9142 .balign 64 9143.L_OP_UNUSED_4CFF: /* 0x14c */ 9144/* File: armv5te/OP_UNUSED_4CFF.S */ 9145/* File: armv5te/unused.S */ 9146 bl common_abort 9147 9148 9149/* ------------------------------ */ 9150 .balign 64 9151.L_OP_UNUSED_4DFF: /* 0x14d */ 9152/* File: armv5te/OP_UNUSED_4DFF.S */ 9153/* File: armv5te/unused.S */ 9154 bl common_abort 9155 9156 9157/* ------------------------------ */ 9158 .balign 64 9159.L_OP_UNUSED_4EFF: /* 0x14e */ 9160/* File: armv5te/OP_UNUSED_4EFF.S */ 9161/* File: armv5te/unused.S */ 9162 bl common_abort 9163 9164 9165/* ------------------------------ */ 9166 .balign 64 9167.L_OP_UNUSED_4FFF: /* 0x14f */ 9168/* File: armv5te/OP_UNUSED_4FFF.S */ 9169/* File: armv5te/unused.S */ 9170 bl common_abort 9171 9172 9173/* ------------------------------ */ 9174 .balign 64 9175.L_OP_UNUSED_50FF: /* 0x150 */ 9176/* File: armv5te/OP_UNUSED_50FF.S */ 9177/* File: armv5te/unused.S */ 9178 bl common_abort 9179 9180 9181/* ------------------------------ */ 9182 .balign 64 9183.L_OP_UNUSED_51FF: /* 0x151 */ 9184/* File: armv5te/OP_UNUSED_51FF.S */ 9185/* File: armv5te/unused.S */ 9186 bl common_abort 9187 9188 9189/* ------------------------------ */ 9190 .balign 64 9191.L_OP_UNUSED_52FF: /* 0x152 */ 9192/* File: armv5te/OP_UNUSED_52FF.S */ 9193/* File: armv5te/unused.S */ 9194 bl common_abort 9195 9196 9197/* ------------------------------ */ 9198 .balign 64 9199.L_OP_UNUSED_53FF: /* 0x153 */ 9200/* File: armv5te/OP_UNUSED_53FF.S */ 9201/* File: armv5te/unused.S */ 9202 bl common_abort 9203 9204 9205/* ------------------------------ */ 9206 .balign 64 9207.L_OP_UNUSED_54FF: /* 0x154 */ 9208/* File: armv5te/OP_UNUSED_54FF.S */ 9209/* File: armv5te/unused.S */ 9210 bl common_abort 9211 9212 9213/* ------------------------------ */ 9214 .balign 64 9215.L_OP_UNUSED_55FF: /* 0x155 */ 9216/* File: armv5te/OP_UNUSED_55FF.S */ 9217/* File: armv5te/unused.S */ 9218 bl common_abort 9219 9220 9221/* ------------------------------ */ 9222 .balign 64 9223.L_OP_UNUSED_56FF: /* 0x156 */ 9224/* File: armv5te/OP_UNUSED_56FF.S */ 9225/* File: armv5te/unused.S */ 9226 bl common_abort 9227 9228 9229/* ------------------------------ */ 9230 .balign 64 9231.L_OP_UNUSED_57FF: /* 0x157 */ 9232/* File: armv5te/OP_UNUSED_57FF.S */ 9233/* File: armv5te/unused.S */ 9234 bl common_abort 9235 9236 9237/* ------------------------------ */ 9238 .balign 64 9239.L_OP_UNUSED_58FF: /* 0x158 */ 9240/* File: armv5te/OP_UNUSED_58FF.S */ 9241/* File: armv5te/unused.S */ 9242 bl common_abort 9243 9244 9245/* ------------------------------ */ 9246 .balign 64 9247.L_OP_UNUSED_59FF: /* 0x159 */ 9248/* File: armv5te/OP_UNUSED_59FF.S */ 9249/* File: armv5te/unused.S */ 9250 bl common_abort 9251 9252 9253/* ------------------------------ */ 9254 .balign 64 9255.L_OP_UNUSED_5AFF: /* 0x15a */ 9256/* File: armv5te/OP_UNUSED_5AFF.S */ 9257/* File: armv5te/unused.S */ 9258 bl common_abort 9259 9260 9261/* ------------------------------ */ 9262 .balign 64 9263.L_OP_UNUSED_5BFF: /* 0x15b */ 9264/* File: armv5te/OP_UNUSED_5BFF.S */ 9265/* File: armv5te/unused.S */ 9266 bl common_abort 9267 9268 9269/* ------------------------------ */ 9270 .balign 64 9271.L_OP_UNUSED_5CFF: /* 0x15c */ 9272/* File: armv5te/OP_UNUSED_5CFF.S */ 9273/* File: armv5te/unused.S */ 9274 bl common_abort 9275 9276 9277/* ------------------------------ */ 9278 .balign 64 9279.L_OP_UNUSED_5DFF: /* 0x15d */ 9280/* File: armv5te/OP_UNUSED_5DFF.S */ 9281/* File: armv5te/unused.S */ 9282 bl common_abort 9283 9284 9285/* ------------------------------ */ 9286 .balign 64 9287.L_OP_UNUSED_5EFF: /* 0x15e */ 9288/* File: armv5te/OP_UNUSED_5EFF.S */ 9289/* File: armv5te/unused.S */ 9290 bl common_abort 9291 9292 9293/* ------------------------------ */ 9294 .balign 64 9295.L_OP_UNUSED_5FFF: /* 0x15f */ 9296/* File: armv5te/OP_UNUSED_5FFF.S */ 9297/* File: armv5te/unused.S */ 9298 bl common_abort 9299 9300 9301/* ------------------------------ */ 9302 .balign 64 9303.L_OP_UNUSED_60FF: /* 0x160 */ 9304/* File: armv5te/OP_UNUSED_60FF.S */ 9305/* File: armv5te/unused.S */ 9306 bl common_abort 9307 9308 9309/* ------------------------------ */ 9310 .balign 64 9311.L_OP_UNUSED_61FF: /* 0x161 */ 9312/* File: armv5te/OP_UNUSED_61FF.S */ 9313/* File: armv5te/unused.S */ 9314 bl common_abort 9315 9316 9317/* ------------------------------ */ 9318 .balign 64 9319.L_OP_UNUSED_62FF: /* 0x162 */ 9320/* File: armv5te/OP_UNUSED_62FF.S */ 9321/* File: armv5te/unused.S */ 9322 bl common_abort 9323 9324 9325/* ------------------------------ */ 9326 .balign 64 9327.L_OP_UNUSED_63FF: /* 0x163 */ 9328/* File: armv5te/OP_UNUSED_63FF.S */ 9329/* File: armv5te/unused.S */ 9330 bl common_abort 9331 9332 9333/* ------------------------------ */ 9334 .balign 64 9335.L_OP_UNUSED_64FF: /* 0x164 */ 9336/* File: armv5te/OP_UNUSED_64FF.S */ 9337/* File: armv5te/unused.S */ 9338 bl common_abort 9339 9340 9341/* ------------------------------ */ 9342 .balign 64 9343.L_OP_UNUSED_65FF: /* 0x165 */ 9344/* File: armv5te/OP_UNUSED_65FF.S */ 9345/* File: armv5te/unused.S */ 9346 bl common_abort 9347 9348 9349/* ------------------------------ */ 9350 .balign 64 9351.L_OP_UNUSED_66FF: /* 0x166 */ 9352/* File: armv5te/OP_UNUSED_66FF.S */ 9353/* File: armv5te/unused.S */ 9354 bl common_abort 9355 9356 9357/* ------------------------------ */ 9358 .balign 64 9359.L_OP_UNUSED_67FF: /* 0x167 */ 9360/* File: armv5te/OP_UNUSED_67FF.S */ 9361/* File: armv5te/unused.S */ 9362 bl common_abort 9363 9364 9365/* ------------------------------ */ 9366 .balign 64 9367.L_OP_UNUSED_68FF: /* 0x168 */ 9368/* File: armv5te/OP_UNUSED_68FF.S */ 9369/* File: armv5te/unused.S */ 9370 bl common_abort 9371 9372 9373/* ------------------------------ */ 9374 .balign 64 9375.L_OP_UNUSED_69FF: /* 0x169 */ 9376/* File: armv5te/OP_UNUSED_69FF.S */ 9377/* File: armv5te/unused.S */ 9378 bl common_abort 9379 9380 9381/* ------------------------------ */ 9382 .balign 64 9383.L_OP_UNUSED_6AFF: /* 0x16a */ 9384/* File: armv5te/OP_UNUSED_6AFF.S */ 9385/* File: armv5te/unused.S */ 9386 bl common_abort 9387 9388 9389/* ------------------------------ */ 9390 .balign 64 9391.L_OP_UNUSED_6BFF: /* 0x16b */ 9392/* File: armv5te/OP_UNUSED_6BFF.S */ 9393/* File: armv5te/unused.S */ 9394 bl common_abort 9395 9396 9397/* ------------------------------ */ 9398 .balign 64 9399.L_OP_UNUSED_6CFF: /* 0x16c */ 9400/* File: armv5te/OP_UNUSED_6CFF.S */ 9401/* File: armv5te/unused.S */ 9402 bl common_abort 9403 9404 9405/* ------------------------------ */ 9406 .balign 64 9407.L_OP_UNUSED_6DFF: /* 0x16d */ 9408/* File: armv5te/OP_UNUSED_6DFF.S */ 9409/* File: armv5te/unused.S */ 9410 bl common_abort 9411 9412 9413/* ------------------------------ */ 9414 .balign 64 9415.L_OP_UNUSED_6EFF: /* 0x16e */ 9416/* File: armv5te/OP_UNUSED_6EFF.S */ 9417/* File: armv5te/unused.S */ 9418 bl common_abort 9419 9420 9421/* ------------------------------ */ 9422 .balign 64 9423.L_OP_UNUSED_6FFF: /* 0x16f */ 9424/* File: armv5te/OP_UNUSED_6FFF.S */ 9425/* File: armv5te/unused.S */ 9426 bl common_abort 9427 9428 9429/* ------------------------------ */ 9430 .balign 64 9431.L_OP_UNUSED_70FF: /* 0x170 */ 9432/* File: armv5te/OP_UNUSED_70FF.S */ 9433/* File: armv5te/unused.S */ 9434 bl common_abort 9435 9436 9437/* ------------------------------ */ 9438 .balign 64 9439.L_OP_UNUSED_71FF: /* 0x171 */ 9440/* File: armv5te/OP_UNUSED_71FF.S */ 9441/* File: armv5te/unused.S */ 9442 bl common_abort 9443 9444 9445/* ------------------------------ */ 9446 .balign 64 9447.L_OP_UNUSED_72FF: /* 0x172 */ 9448/* File: armv5te/OP_UNUSED_72FF.S */ 9449/* File: armv5te/unused.S */ 9450 bl common_abort 9451 9452 9453/* ------------------------------ */ 9454 .balign 64 9455.L_OP_UNUSED_73FF: /* 0x173 */ 9456/* File: armv5te/OP_UNUSED_73FF.S */ 9457/* File: armv5te/unused.S */ 9458 bl common_abort 9459 9460 9461/* ------------------------------ */ 9462 .balign 64 9463.L_OP_UNUSED_74FF: /* 0x174 */ 9464/* File: armv5te/OP_UNUSED_74FF.S */ 9465/* File: armv5te/unused.S */ 9466 bl common_abort 9467 9468 9469/* ------------------------------ */ 9470 .balign 64 9471.L_OP_UNUSED_75FF: /* 0x175 */ 9472/* File: armv5te/OP_UNUSED_75FF.S */ 9473/* File: armv5te/unused.S */ 9474 bl common_abort 9475 9476 9477/* ------------------------------ */ 9478 .balign 64 9479.L_OP_UNUSED_76FF: /* 0x176 */ 9480/* File: armv5te/OP_UNUSED_76FF.S */ 9481/* File: armv5te/unused.S */ 9482 bl common_abort 9483 9484 9485/* ------------------------------ */ 9486 .balign 64 9487.L_OP_UNUSED_77FF: /* 0x177 */ 9488/* File: armv5te/OP_UNUSED_77FF.S */ 9489/* File: armv5te/unused.S */ 9490 bl common_abort 9491 9492 9493/* ------------------------------ */ 9494 .balign 64 9495.L_OP_UNUSED_78FF: /* 0x178 */ 9496/* File: armv5te/OP_UNUSED_78FF.S */ 9497/* File: armv5te/unused.S */ 9498 bl common_abort 9499 9500 9501/* ------------------------------ */ 9502 .balign 64 9503.L_OP_UNUSED_79FF: /* 0x179 */ 9504/* File: armv5te/OP_UNUSED_79FF.S */ 9505/* File: armv5te/unused.S */ 9506 bl common_abort 9507 9508 9509/* ------------------------------ */ 9510 .balign 64 9511.L_OP_UNUSED_7AFF: /* 0x17a */ 9512/* File: armv5te/OP_UNUSED_7AFF.S */ 9513/* File: armv5te/unused.S */ 9514 bl common_abort 9515 9516 9517/* ------------------------------ */ 9518 .balign 64 9519.L_OP_UNUSED_7BFF: /* 0x17b */ 9520/* File: armv5te/OP_UNUSED_7BFF.S */ 9521/* File: armv5te/unused.S */ 9522 bl common_abort 9523 9524 9525/* ------------------------------ */ 9526 .balign 64 9527.L_OP_UNUSED_7CFF: /* 0x17c */ 9528/* File: armv5te/OP_UNUSED_7CFF.S */ 9529/* File: armv5te/unused.S */ 9530 bl common_abort 9531 9532 9533/* ------------------------------ */ 9534 .balign 64 9535.L_OP_UNUSED_7DFF: /* 0x17d */ 9536/* File: armv5te/OP_UNUSED_7DFF.S */ 9537/* File: armv5te/unused.S */ 9538 bl common_abort 9539 9540 9541/* ------------------------------ */ 9542 .balign 64 9543.L_OP_UNUSED_7EFF: /* 0x17e */ 9544/* File: armv5te/OP_UNUSED_7EFF.S */ 9545/* File: armv5te/unused.S */ 9546 bl common_abort 9547 9548 9549/* ------------------------------ */ 9550 .balign 64 9551.L_OP_UNUSED_7FFF: /* 0x17f */ 9552/* File: armv5te/OP_UNUSED_7FFF.S */ 9553/* File: armv5te/unused.S */ 9554 bl common_abort 9555 9556 9557/* ------------------------------ */ 9558 .balign 64 9559.L_OP_UNUSED_80FF: /* 0x180 */ 9560/* File: armv5te/OP_UNUSED_80FF.S */ 9561/* File: armv5te/unused.S */ 9562 bl common_abort 9563 9564 9565/* ------------------------------ */ 9566 .balign 64 9567.L_OP_UNUSED_81FF: /* 0x181 */ 9568/* File: armv5te/OP_UNUSED_81FF.S */ 9569/* File: armv5te/unused.S */ 9570 bl common_abort 9571 9572 9573/* ------------------------------ */ 9574 .balign 64 9575.L_OP_UNUSED_82FF: /* 0x182 */ 9576/* File: armv5te/OP_UNUSED_82FF.S */ 9577/* File: armv5te/unused.S */ 9578 bl common_abort 9579 9580 9581/* ------------------------------ */ 9582 .balign 64 9583.L_OP_UNUSED_83FF: /* 0x183 */ 9584/* File: armv5te/OP_UNUSED_83FF.S */ 9585/* File: armv5te/unused.S */ 9586 bl common_abort 9587 9588 9589/* ------------------------------ */ 9590 .balign 64 9591.L_OP_UNUSED_84FF: /* 0x184 */ 9592/* File: armv5te/OP_UNUSED_84FF.S */ 9593/* File: armv5te/unused.S */ 9594 bl common_abort 9595 9596 9597/* ------------------------------ */ 9598 .balign 64 9599.L_OP_UNUSED_85FF: /* 0x185 */ 9600/* File: armv5te/OP_UNUSED_85FF.S */ 9601/* File: armv5te/unused.S */ 9602 bl common_abort 9603 9604 9605/* ------------------------------ */ 9606 .balign 64 9607.L_OP_UNUSED_86FF: /* 0x186 */ 9608/* File: armv5te/OP_UNUSED_86FF.S */ 9609/* File: armv5te/unused.S */ 9610 bl common_abort 9611 9612 9613/* ------------------------------ */ 9614 .balign 64 9615.L_OP_UNUSED_87FF: /* 0x187 */ 9616/* File: armv5te/OP_UNUSED_87FF.S */ 9617/* File: armv5te/unused.S */ 9618 bl common_abort 9619 9620 9621/* ------------------------------ */ 9622 .balign 64 9623.L_OP_UNUSED_88FF: /* 0x188 */ 9624/* File: armv5te/OP_UNUSED_88FF.S */ 9625/* File: armv5te/unused.S */ 9626 bl common_abort 9627 9628 9629/* ------------------------------ */ 9630 .balign 64 9631.L_OP_UNUSED_89FF: /* 0x189 */ 9632/* File: armv5te/OP_UNUSED_89FF.S */ 9633/* File: armv5te/unused.S */ 9634 bl common_abort 9635 9636 9637/* ------------------------------ */ 9638 .balign 64 9639.L_OP_UNUSED_8AFF: /* 0x18a */ 9640/* File: armv5te/OP_UNUSED_8AFF.S */ 9641/* File: armv5te/unused.S */ 9642 bl common_abort 9643 9644 9645/* ------------------------------ */ 9646 .balign 64 9647.L_OP_UNUSED_8BFF: /* 0x18b */ 9648/* File: armv5te/OP_UNUSED_8BFF.S */ 9649/* File: armv5te/unused.S */ 9650 bl common_abort 9651 9652 9653/* ------------------------------ */ 9654 .balign 64 9655.L_OP_UNUSED_8CFF: /* 0x18c */ 9656/* File: armv5te/OP_UNUSED_8CFF.S */ 9657/* File: armv5te/unused.S */ 9658 bl common_abort 9659 9660 9661/* ------------------------------ */ 9662 .balign 64 9663.L_OP_UNUSED_8DFF: /* 0x18d */ 9664/* File: armv5te/OP_UNUSED_8DFF.S */ 9665/* File: armv5te/unused.S */ 9666 bl common_abort 9667 9668 9669/* ------------------------------ */ 9670 .balign 64 9671.L_OP_UNUSED_8EFF: /* 0x18e */ 9672/* File: armv5te/OP_UNUSED_8EFF.S */ 9673/* File: armv5te/unused.S */ 9674 bl common_abort 9675 9676 9677/* ------------------------------ */ 9678 .balign 64 9679.L_OP_UNUSED_8FFF: /* 0x18f */ 9680/* File: armv5te/OP_UNUSED_8FFF.S */ 9681/* File: armv5te/unused.S */ 9682 bl common_abort 9683 9684 9685/* ------------------------------ */ 9686 .balign 64 9687.L_OP_UNUSED_90FF: /* 0x190 */ 9688/* File: armv5te/OP_UNUSED_90FF.S */ 9689/* File: armv5te/unused.S */ 9690 bl common_abort 9691 9692 9693/* ------------------------------ */ 9694 .balign 64 9695.L_OP_UNUSED_91FF: /* 0x191 */ 9696/* File: armv5te/OP_UNUSED_91FF.S */ 9697/* File: armv5te/unused.S */ 9698 bl common_abort 9699 9700 9701/* ------------------------------ */ 9702 .balign 64 9703.L_OP_UNUSED_92FF: /* 0x192 */ 9704/* File: armv5te/OP_UNUSED_92FF.S */ 9705/* File: armv5te/unused.S */ 9706 bl common_abort 9707 9708 9709/* ------------------------------ */ 9710 .balign 64 9711.L_OP_UNUSED_93FF: /* 0x193 */ 9712/* File: armv5te/OP_UNUSED_93FF.S */ 9713/* File: armv5te/unused.S */ 9714 bl common_abort 9715 9716 9717/* ------------------------------ */ 9718 .balign 64 9719.L_OP_UNUSED_94FF: /* 0x194 */ 9720/* File: armv5te/OP_UNUSED_94FF.S */ 9721/* File: armv5te/unused.S */ 9722 bl common_abort 9723 9724 9725/* ------------------------------ */ 9726 .balign 64 9727.L_OP_UNUSED_95FF: /* 0x195 */ 9728/* File: armv5te/OP_UNUSED_95FF.S */ 9729/* File: armv5te/unused.S */ 9730 bl common_abort 9731 9732 9733/* ------------------------------ */ 9734 .balign 64 9735.L_OP_UNUSED_96FF: /* 0x196 */ 9736/* File: armv5te/OP_UNUSED_96FF.S */ 9737/* File: armv5te/unused.S */ 9738 bl common_abort 9739 9740 9741/* ------------------------------ */ 9742 .balign 64 9743.L_OP_UNUSED_97FF: /* 0x197 */ 9744/* File: armv5te/OP_UNUSED_97FF.S */ 9745/* File: armv5te/unused.S */ 9746 bl common_abort 9747 9748 9749/* ------------------------------ */ 9750 .balign 64 9751.L_OP_UNUSED_98FF: /* 0x198 */ 9752/* File: armv5te/OP_UNUSED_98FF.S */ 9753/* File: armv5te/unused.S */ 9754 bl common_abort 9755 9756 9757/* ------------------------------ */ 9758 .balign 64 9759.L_OP_UNUSED_99FF: /* 0x199 */ 9760/* File: armv5te/OP_UNUSED_99FF.S */ 9761/* File: armv5te/unused.S */ 9762 bl common_abort 9763 9764 9765/* ------------------------------ */ 9766 .balign 64 9767.L_OP_UNUSED_9AFF: /* 0x19a */ 9768/* File: armv5te/OP_UNUSED_9AFF.S */ 9769/* File: armv5te/unused.S */ 9770 bl common_abort 9771 9772 9773/* ------------------------------ */ 9774 .balign 64 9775.L_OP_UNUSED_9BFF: /* 0x19b */ 9776/* File: armv5te/OP_UNUSED_9BFF.S */ 9777/* File: armv5te/unused.S */ 9778 bl common_abort 9779 9780 9781/* ------------------------------ */ 9782 .balign 64 9783.L_OP_UNUSED_9CFF: /* 0x19c */ 9784/* File: armv5te/OP_UNUSED_9CFF.S */ 9785/* File: armv5te/unused.S */ 9786 bl common_abort 9787 9788 9789/* ------------------------------ */ 9790 .balign 64 9791.L_OP_UNUSED_9DFF: /* 0x19d */ 9792/* File: armv5te/OP_UNUSED_9DFF.S */ 9793/* File: armv5te/unused.S */ 9794 bl common_abort 9795 9796 9797/* ------------------------------ */ 9798 .balign 64 9799.L_OP_UNUSED_9EFF: /* 0x19e */ 9800/* File: armv5te/OP_UNUSED_9EFF.S */ 9801/* File: armv5te/unused.S */ 9802 bl common_abort 9803 9804 9805/* ------------------------------ */ 9806 .balign 64 9807.L_OP_UNUSED_9FFF: /* 0x19f */ 9808/* File: armv5te/OP_UNUSED_9FFF.S */ 9809/* File: armv5te/unused.S */ 9810 bl common_abort 9811 9812 9813/* ------------------------------ */ 9814 .balign 64 9815.L_OP_UNUSED_A0FF: /* 0x1a0 */ 9816/* File: armv5te/OP_UNUSED_A0FF.S */ 9817/* File: armv5te/unused.S */ 9818 bl common_abort 9819 9820 9821/* ------------------------------ */ 9822 .balign 64 9823.L_OP_UNUSED_A1FF: /* 0x1a1 */ 9824/* File: armv5te/OP_UNUSED_A1FF.S */ 9825/* File: armv5te/unused.S */ 9826 bl common_abort 9827 9828 9829/* ------------------------------ */ 9830 .balign 64 9831.L_OP_UNUSED_A2FF: /* 0x1a2 */ 9832/* File: armv5te/OP_UNUSED_A2FF.S */ 9833/* File: armv5te/unused.S */ 9834 bl common_abort 9835 9836 9837/* ------------------------------ */ 9838 .balign 64 9839.L_OP_UNUSED_A3FF: /* 0x1a3 */ 9840/* File: armv5te/OP_UNUSED_A3FF.S */ 9841/* File: armv5te/unused.S */ 9842 bl common_abort 9843 9844 9845/* ------------------------------ */ 9846 .balign 64 9847.L_OP_UNUSED_A4FF: /* 0x1a4 */ 9848/* File: armv5te/OP_UNUSED_A4FF.S */ 9849/* File: armv5te/unused.S */ 9850 bl common_abort 9851 9852 9853/* ------------------------------ */ 9854 .balign 64 9855.L_OP_UNUSED_A5FF: /* 0x1a5 */ 9856/* File: armv5te/OP_UNUSED_A5FF.S */ 9857/* File: armv5te/unused.S */ 9858 bl common_abort 9859 9860 9861/* ------------------------------ */ 9862 .balign 64 9863.L_OP_UNUSED_A6FF: /* 0x1a6 */ 9864/* File: armv5te/OP_UNUSED_A6FF.S */ 9865/* File: armv5te/unused.S */ 9866 bl common_abort 9867 9868 9869/* ------------------------------ */ 9870 .balign 64 9871.L_OP_UNUSED_A7FF: /* 0x1a7 */ 9872/* File: armv5te/OP_UNUSED_A7FF.S */ 9873/* File: armv5te/unused.S */ 9874 bl common_abort 9875 9876 9877/* ------------------------------ */ 9878 .balign 64 9879.L_OP_UNUSED_A8FF: /* 0x1a8 */ 9880/* File: armv5te/OP_UNUSED_A8FF.S */ 9881/* File: armv5te/unused.S */ 9882 bl common_abort 9883 9884 9885/* ------------------------------ */ 9886 .balign 64 9887.L_OP_UNUSED_A9FF: /* 0x1a9 */ 9888/* File: armv5te/OP_UNUSED_A9FF.S */ 9889/* File: armv5te/unused.S */ 9890 bl common_abort 9891 9892 9893/* ------------------------------ */ 9894 .balign 64 9895.L_OP_UNUSED_AAFF: /* 0x1aa */ 9896/* File: armv5te/OP_UNUSED_AAFF.S */ 9897/* File: armv5te/unused.S */ 9898 bl common_abort 9899 9900 9901/* ------------------------------ */ 9902 .balign 64 9903.L_OP_UNUSED_ABFF: /* 0x1ab */ 9904/* File: armv5te/OP_UNUSED_ABFF.S */ 9905/* File: armv5te/unused.S */ 9906 bl common_abort 9907 9908 9909/* ------------------------------ */ 9910 .balign 64 9911.L_OP_UNUSED_ACFF: /* 0x1ac */ 9912/* File: armv5te/OP_UNUSED_ACFF.S */ 9913/* File: armv5te/unused.S */ 9914 bl common_abort 9915 9916 9917/* ------------------------------ */ 9918 .balign 64 9919.L_OP_UNUSED_ADFF: /* 0x1ad */ 9920/* File: armv5te/OP_UNUSED_ADFF.S */ 9921/* File: armv5te/unused.S */ 9922 bl common_abort 9923 9924 9925/* ------------------------------ */ 9926 .balign 64 9927.L_OP_UNUSED_AEFF: /* 0x1ae */ 9928/* File: armv5te/OP_UNUSED_AEFF.S */ 9929/* File: armv5te/unused.S */ 9930 bl common_abort 9931 9932 9933/* ------------------------------ */ 9934 .balign 64 9935.L_OP_UNUSED_AFFF: /* 0x1af */ 9936/* File: armv5te/OP_UNUSED_AFFF.S */ 9937/* File: armv5te/unused.S */ 9938 bl common_abort 9939 9940 9941/* ------------------------------ */ 9942 .balign 64 9943.L_OP_UNUSED_B0FF: /* 0x1b0 */ 9944/* File: armv5te/OP_UNUSED_B0FF.S */ 9945/* File: armv5te/unused.S */ 9946 bl common_abort 9947 9948 9949/* ------------------------------ */ 9950 .balign 64 9951.L_OP_UNUSED_B1FF: /* 0x1b1 */ 9952/* File: armv5te/OP_UNUSED_B1FF.S */ 9953/* File: armv5te/unused.S */ 9954 bl common_abort 9955 9956 9957/* ------------------------------ */ 9958 .balign 64 9959.L_OP_UNUSED_B2FF: /* 0x1b2 */ 9960/* File: armv5te/OP_UNUSED_B2FF.S */ 9961/* File: armv5te/unused.S */ 9962 bl common_abort 9963 9964 9965/* ------------------------------ */ 9966 .balign 64 9967.L_OP_UNUSED_B3FF: /* 0x1b3 */ 9968/* File: armv5te/OP_UNUSED_B3FF.S */ 9969/* File: armv5te/unused.S */ 9970 bl common_abort 9971 9972 9973/* ------------------------------ */ 9974 .balign 64 9975.L_OP_UNUSED_B4FF: /* 0x1b4 */ 9976/* File: armv5te/OP_UNUSED_B4FF.S */ 9977/* File: armv5te/unused.S */ 9978 bl common_abort 9979 9980 9981/* ------------------------------ */ 9982 .balign 64 9983.L_OP_UNUSED_B5FF: /* 0x1b5 */ 9984/* File: armv5te/OP_UNUSED_B5FF.S */ 9985/* File: armv5te/unused.S */ 9986 bl common_abort 9987 9988 9989/* ------------------------------ */ 9990 .balign 64 9991.L_OP_UNUSED_B6FF: /* 0x1b6 */ 9992/* File: armv5te/OP_UNUSED_B6FF.S */ 9993/* File: armv5te/unused.S */ 9994 bl common_abort 9995 9996 9997/* ------------------------------ */ 9998 .balign 64 9999.L_OP_UNUSED_B7FF: /* 0x1b7 */ 10000/* File: armv5te/OP_UNUSED_B7FF.S */ 10001/* File: armv5te/unused.S */ 10002 bl common_abort 10003 10004 10005/* ------------------------------ */ 10006 .balign 64 10007.L_OP_UNUSED_B8FF: /* 0x1b8 */ 10008/* File: armv5te/OP_UNUSED_B8FF.S */ 10009/* File: armv5te/unused.S */ 10010 bl common_abort 10011 10012 10013/* ------------------------------ */ 10014 .balign 64 10015.L_OP_UNUSED_B9FF: /* 0x1b9 */ 10016/* File: armv5te/OP_UNUSED_B9FF.S */ 10017/* File: armv5te/unused.S */ 10018 bl common_abort 10019 10020 10021/* ------------------------------ */ 10022 .balign 64 10023.L_OP_UNUSED_BAFF: /* 0x1ba */ 10024/* File: armv5te/OP_UNUSED_BAFF.S */ 10025/* File: armv5te/unused.S */ 10026 bl common_abort 10027 10028 10029/* ------------------------------ */ 10030 .balign 64 10031.L_OP_UNUSED_BBFF: /* 0x1bb */ 10032/* File: armv5te/OP_UNUSED_BBFF.S */ 10033/* File: armv5te/unused.S */ 10034 bl common_abort 10035 10036 10037/* ------------------------------ */ 10038 .balign 64 10039.L_OP_UNUSED_BCFF: /* 0x1bc */ 10040/* File: armv5te/OP_UNUSED_BCFF.S */ 10041/* File: armv5te/unused.S */ 10042 bl common_abort 10043 10044 10045/* ------------------------------ */ 10046 .balign 64 10047.L_OP_UNUSED_BDFF: /* 0x1bd */ 10048/* File: armv5te/OP_UNUSED_BDFF.S */ 10049/* File: armv5te/unused.S */ 10050 bl common_abort 10051 10052 10053/* ------------------------------ */ 10054 .balign 64 10055.L_OP_UNUSED_BEFF: /* 0x1be */ 10056/* File: armv5te/OP_UNUSED_BEFF.S */ 10057/* File: armv5te/unused.S */ 10058 bl common_abort 10059 10060 10061/* ------------------------------ */ 10062 .balign 64 10063.L_OP_UNUSED_BFFF: /* 0x1bf */ 10064/* File: armv5te/OP_UNUSED_BFFF.S */ 10065/* File: armv5te/unused.S */ 10066 bl common_abort 10067 10068 10069/* ------------------------------ */ 10070 .balign 64 10071.L_OP_UNUSED_C0FF: /* 0x1c0 */ 10072/* File: armv5te/OP_UNUSED_C0FF.S */ 10073/* File: armv5te/unused.S */ 10074 bl common_abort 10075 10076 10077/* ------------------------------ */ 10078 .balign 64 10079.L_OP_UNUSED_C1FF: /* 0x1c1 */ 10080/* File: armv5te/OP_UNUSED_C1FF.S */ 10081/* File: armv5te/unused.S */ 10082 bl common_abort 10083 10084 10085/* ------------------------------ */ 10086 .balign 64 10087.L_OP_UNUSED_C2FF: /* 0x1c2 */ 10088/* File: armv5te/OP_UNUSED_C2FF.S */ 10089/* File: armv5te/unused.S */ 10090 bl common_abort 10091 10092 10093/* ------------------------------ */ 10094 .balign 64 10095.L_OP_UNUSED_C3FF: /* 0x1c3 */ 10096/* File: armv5te/OP_UNUSED_C3FF.S */ 10097/* File: armv5te/unused.S */ 10098 bl common_abort 10099 10100 10101/* ------------------------------ */ 10102 .balign 64 10103.L_OP_UNUSED_C4FF: /* 0x1c4 */ 10104/* File: armv5te/OP_UNUSED_C4FF.S */ 10105/* File: armv5te/unused.S */ 10106 bl common_abort 10107 10108 10109/* ------------------------------ */ 10110 .balign 64 10111.L_OP_UNUSED_C5FF: /* 0x1c5 */ 10112/* File: armv5te/OP_UNUSED_C5FF.S */ 10113/* File: armv5te/unused.S */ 10114 bl common_abort 10115 10116 10117/* ------------------------------ */ 10118 .balign 64 10119.L_OP_UNUSED_C6FF: /* 0x1c6 */ 10120/* File: armv5te/OP_UNUSED_C6FF.S */ 10121/* File: armv5te/unused.S */ 10122 bl common_abort 10123 10124 10125/* ------------------------------ */ 10126 .balign 64 10127.L_OP_UNUSED_C7FF: /* 0x1c7 */ 10128/* File: armv5te/OP_UNUSED_C7FF.S */ 10129/* File: armv5te/unused.S */ 10130 bl common_abort 10131 10132 10133/* ------------------------------ */ 10134 .balign 64 10135.L_OP_UNUSED_C8FF: /* 0x1c8 */ 10136/* File: armv5te/OP_UNUSED_C8FF.S */ 10137/* File: armv5te/unused.S */ 10138 bl common_abort 10139 10140 10141/* ------------------------------ */ 10142 .balign 64 10143.L_OP_UNUSED_C9FF: /* 0x1c9 */ 10144/* File: armv5te/OP_UNUSED_C9FF.S */ 10145/* File: armv5te/unused.S */ 10146 bl common_abort 10147 10148 10149/* ------------------------------ */ 10150 .balign 64 10151.L_OP_UNUSED_CAFF: /* 0x1ca */ 10152/* File: armv5te/OP_UNUSED_CAFF.S */ 10153/* File: armv5te/unused.S */ 10154 bl common_abort 10155 10156 10157/* ------------------------------ */ 10158 .balign 64 10159.L_OP_UNUSED_CBFF: /* 0x1cb */ 10160/* File: armv5te/OP_UNUSED_CBFF.S */ 10161/* File: armv5te/unused.S */ 10162 bl common_abort 10163 10164 10165/* ------------------------------ */ 10166 .balign 64 10167.L_OP_UNUSED_CCFF: /* 0x1cc */ 10168/* File: armv5te/OP_UNUSED_CCFF.S */ 10169/* File: armv5te/unused.S */ 10170 bl common_abort 10171 10172 10173/* ------------------------------ */ 10174 .balign 64 10175.L_OP_UNUSED_CDFF: /* 0x1cd */ 10176/* File: armv5te/OP_UNUSED_CDFF.S */ 10177/* File: armv5te/unused.S */ 10178 bl common_abort 10179 10180 10181/* ------------------------------ */ 10182 .balign 64 10183.L_OP_UNUSED_CEFF: /* 0x1ce */ 10184/* File: armv5te/OP_UNUSED_CEFF.S */ 10185/* File: armv5te/unused.S */ 10186 bl common_abort 10187 10188 10189/* ------------------------------ */ 10190 .balign 64 10191.L_OP_UNUSED_CFFF: /* 0x1cf */ 10192/* File: armv5te/OP_UNUSED_CFFF.S */ 10193/* File: armv5te/unused.S */ 10194 bl common_abort 10195 10196 10197/* ------------------------------ */ 10198 .balign 64 10199.L_OP_UNUSED_D0FF: /* 0x1d0 */ 10200/* File: armv5te/OP_UNUSED_D0FF.S */ 10201/* File: armv5te/unused.S */ 10202 bl common_abort 10203 10204 10205/* ------------------------------ */ 10206 .balign 64 10207.L_OP_UNUSED_D1FF: /* 0x1d1 */ 10208/* File: armv5te/OP_UNUSED_D1FF.S */ 10209/* File: armv5te/unused.S */ 10210 bl common_abort 10211 10212 10213/* ------------------------------ */ 10214 .balign 64 10215.L_OP_UNUSED_D2FF: /* 0x1d2 */ 10216/* File: armv5te/OP_UNUSED_D2FF.S */ 10217/* File: armv5te/unused.S */ 10218 bl common_abort 10219 10220 10221/* ------------------------------ */ 10222 .balign 64 10223.L_OP_UNUSED_D3FF: /* 0x1d3 */ 10224/* File: armv5te/OP_UNUSED_D3FF.S */ 10225/* File: armv5te/unused.S */ 10226 bl common_abort 10227 10228 10229/* ------------------------------ */ 10230 .balign 64 10231.L_OP_UNUSED_D4FF: /* 0x1d4 */ 10232/* File: armv5te/OP_UNUSED_D4FF.S */ 10233/* File: armv5te/unused.S */ 10234 bl common_abort 10235 10236 10237/* ------------------------------ */ 10238 .balign 64 10239.L_OP_UNUSED_D5FF: /* 0x1d5 */ 10240/* File: armv5te/OP_UNUSED_D5FF.S */ 10241/* File: armv5te/unused.S */ 10242 bl common_abort 10243 10244 10245/* ------------------------------ */ 10246 .balign 64 10247.L_OP_UNUSED_D6FF: /* 0x1d6 */ 10248/* File: armv5te/OP_UNUSED_D6FF.S */ 10249/* File: armv5te/unused.S */ 10250 bl common_abort 10251 10252 10253/* ------------------------------ */ 10254 .balign 64 10255.L_OP_UNUSED_D7FF: /* 0x1d7 */ 10256/* File: armv5te/OP_UNUSED_D7FF.S */ 10257/* File: armv5te/unused.S */ 10258 bl common_abort 10259 10260 10261/* ------------------------------ */ 10262 .balign 64 10263.L_OP_UNUSED_D8FF: /* 0x1d8 */ 10264/* File: armv5te/OP_UNUSED_D8FF.S */ 10265/* File: armv5te/unused.S */ 10266 bl common_abort 10267 10268 10269/* ------------------------------ */ 10270 .balign 64 10271.L_OP_UNUSED_D9FF: /* 0x1d9 */ 10272/* File: armv5te/OP_UNUSED_D9FF.S */ 10273/* File: armv5te/unused.S */ 10274 bl common_abort 10275 10276 10277/* ------------------------------ */ 10278 .balign 64 10279.L_OP_UNUSED_DAFF: /* 0x1da */ 10280/* File: armv5te/OP_UNUSED_DAFF.S */ 10281/* File: armv5te/unused.S */ 10282 bl common_abort 10283 10284 10285/* ------------------------------ */ 10286 .balign 64 10287.L_OP_UNUSED_DBFF: /* 0x1db */ 10288/* File: armv5te/OP_UNUSED_DBFF.S */ 10289/* File: armv5te/unused.S */ 10290 bl common_abort 10291 10292 10293/* ------------------------------ */ 10294 .balign 64 10295.L_OP_UNUSED_DCFF: /* 0x1dc */ 10296/* File: armv5te/OP_UNUSED_DCFF.S */ 10297/* File: armv5te/unused.S */ 10298 bl common_abort 10299 10300 10301/* ------------------------------ */ 10302 .balign 64 10303.L_OP_UNUSED_DDFF: /* 0x1dd */ 10304/* File: armv5te/OP_UNUSED_DDFF.S */ 10305/* File: armv5te/unused.S */ 10306 bl common_abort 10307 10308 10309/* ------------------------------ */ 10310 .balign 64 10311.L_OP_UNUSED_DEFF: /* 0x1de */ 10312/* File: armv5te/OP_UNUSED_DEFF.S */ 10313/* File: armv5te/unused.S */ 10314 bl common_abort 10315 10316 10317/* ------------------------------ */ 10318 .balign 64 10319.L_OP_UNUSED_DFFF: /* 0x1df */ 10320/* File: armv5te/OP_UNUSED_DFFF.S */ 10321/* File: armv5te/unused.S */ 10322 bl common_abort 10323 10324 10325/* ------------------------------ */ 10326 .balign 64 10327.L_OP_UNUSED_E0FF: /* 0x1e0 */ 10328/* File: armv5te/OP_UNUSED_E0FF.S */ 10329/* File: armv5te/unused.S */ 10330 bl common_abort 10331 10332 10333/* ------------------------------ */ 10334 .balign 64 10335.L_OP_UNUSED_E1FF: /* 0x1e1 */ 10336/* File: armv5te/OP_UNUSED_E1FF.S */ 10337/* File: armv5te/unused.S */ 10338 bl common_abort 10339 10340 10341/* ------------------------------ */ 10342 .balign 64 10343.L_OP_UNUSED_E2FF: /* 0x1e2 */ 10344/* File: armv5te/OP_UNUSED_E2FF.S */ 10345/* File: armv5te/unused.S */ 10346 bl common_abort 10347 10348 10349/* ------------------------------ */ 10350 .balign 64 10351.L_OP_UNUSED_E3FF: /* 0x1e3 */ 10352/* File: armv5te/OP_UNUSED_E3FF.S */ 10353/* File: armv5te/unused.S */ 10354 bl common_abort 10355 10356 10357/* ------------------------------ */ 10358 .balign 64 10359.L_OP_UNUSED_E4FF: /* 0x1e4 */ 10360/* File: armv5te/OP_UNUSED_E4FF.S */ 10361/* File: armv5te/unused.S */ 10362 bl common_abort 10363 10364 10365/* ------------------------------ */ 10366 .balign 64 10367.L_OP_UNUSED_E5FF: /* 0x1e5 */ 10368/* File: armv5te/OP_UNUSED_E5FF.S */ 10369/* File: armv5te/unused.S */ 10370 bl common_abort 10371 10372 10373/* ------------------------------ */ 10374 .balign 64 10375.L_OP_UNUSED_E6FF: /* 0x1e6 */ 10376/* File: armv5te/OP_UNUSED_E6FF.S */ 10377/* File: armv5te/unused.S */ 10378 bl common_abort 10379 10380 10381/* ------------------------------ */ 10382 .balign 64 10383.L_OP_UNUSED_E7FF: /* 0x1e7 */ 10384/* File: armv5te/OP_UNUSED_E7FF.S */ 10385/* File: armv5te/unused.S */ 10386 bl common_abort 10387 10388 10389/* ------------------------------ */ 10390 .balign 64 10391.L_OP_UNUSED_E8FF: /* 0x1e8 */ 10392/* File: armv5te/OP_UNUSED_E8FF.S */ 10393/* File: armv5te/unused.S */ 10394 bl common_abort 10395 10396 10397/* ------------------------------ */ 10398 .balign 64 10399.L_OP_UNUSED_E9FF: /* 0x1e9 */ 10400/* File: armv5te/OP_UNUSED_E9FF.S */ 10401/* File: armv5te/unused.S */ 10402 bl common_abort 10403 10404 10405/* ------------------------------ */ 10406 .balign 64 10407.L_OP_UNUSED_EAFF: /* 0x1ea */ 10408/* File: armv5te/OP_UNUSED_EAFF.S */ 10409/* File: armv5te/unused.S */ 10410 bl common_abort 10411 10412 10413/* ------------------------------ */ 10414 .balign 64 10415.L_OP_UNUSED_EBFF: /* 0x1eb */ 10416/* File: armv5te/OP_UNUSED_EBFF.S */ 10417/* File: armv5te/unused.S */ 10418 bl common_abort 10419 10420 10421/* ------------------------------ */ 10422 .balign 64 10423.L_OP_UNUSED_ECFF: /* 0x1ec */ 10424/* File: armv5te/OP_UNUSED_ECFF.S */ 10425/* File: armv5te/unused.S */ 10426 bl common_abort 10427 10428 10429/* ------------------------------ */ 10430 .balign 64 10431.L_OP_UNUSED_EDFF: /* 0x1ed */ 10432/* File: armv5te/OP_UNUSED_EDFF.S */ 10433/* File: armv5te/unused.S */ 10434 bl common_abort 10435 10436 10437/* ------------------------------ */ 10438 .balign 64 10439.L_OP_UNUSED_EEFF: /* 0x1ee */ 10440/* File: armv5te/OP_UNUSED_EEFF.S */ 10441/* File: armv5te/unused.S */ 10442 bl common_abort 10443 10444 10445/* ------------------------------ */ 10446 .balign 64 10447.L_OP_UNUSED_EFFF: /* 0x1ef */ 10448/* File: armv5te/OP_UNUSED_EFFF.S */ 10449/* File: armv5te/unused.S */ 10450 bl common_abort 10451 10452 10453/* ------------------------------ */ 10454 .balign 64 10455.L_OP_UNUSED_F0FF: /* 0x1f0 */ 10456/* File: armv5te/OP_UNUSED_F0FF.S */ 10457/* File: armv5te/unused.S */ 10458 bl common_abort 10459 10460 10461/* ------------------------------ */ 10462 .balign 64 10463.L_OP_UNUSED_F1FF: /* 0x1f1 */ 10464/* File: armv5te/OP_UNUSED_F1FF.S */ 10465/* File: armv5te/unused.S */ 10466 bl common_abort 10467 10468 10469/* ------------------------------ */ 10470 .balign 64 10471.L_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */ 10472/* File: armv5te/OP_INVOKE_OBJECT_INIT_JUMBO.S */ 10473/* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */ 10474 /* 10475 * Invoke Object.<init> on an object. In practice we know that 10476 * Object's nullary constructor doesn't do anything, so we just 10477 * skip it (we know a debugger isn't active). 10478 */ 10479 FETCH(r1, 4) @ r1<- CCCC 10480 GET_VREG(r0, r1) @ r0<- "this" ptr 10481 cmp r0, #0 @ check for NULL 10482 beq common_errNullObject @ export PC and throw NPE 10483 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 10484 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 10485 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 10486 beq 1f @ nope, done 10487 EXPORT_PC() @ can throw 10488 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 10489 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception 10490 cmp r0, #0 @ exception pending? 10491 bne common_exceptionThrown @ yes, handle it 104921: FETCH_ADVANCE_INST(4+1) @ advance to next instr, load rINST 10493 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 10494 GOTO_OPCODE(ip) @ execute it 10495 10496 10497/* ------------------------------ */ 10498 .balign 64 10499.L_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */ 10500/* File: armv5te/OP_IGET_VOLATILE_JUMBO.S */ 10501/* File: armv5te/OP_IGET_JUMBO.S */ 10502 /* 10503 * Jumbo 32-bit instance field get. 10504 * 10505 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 10506 * iget-char/jumbo, iget-short/jumbo 10507 */ 10508 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 10509 FETCH(r1, 1) @ r1<- aaaa (lo) 10510 FETCH(r2, 2) @ r2<- AAAA (hi) 10511 FETCH(r0, 4) @ r0<- CCCC 10512 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10513 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10514 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10515 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10516 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10517 cmp r0, #0 @ is resolved entry null? 10518 bne .LOP_IGET_VOLATILE_JUMBO_finish @ no, already resolved 105198: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10520 EXPORT_PC() @ resolve() could throw 10521 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10522 bl dvmResolveInstField @ r0<- resolved InstField ptr 10523 b .LOP_IGET_VOLATILE_JUMBO_resolved @ resolved, continue 10524 10525 10526/* ------------------------------ */ 10527 .balign 64 10528.L_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */ 10529/* File: armv5te/OP_IGET_WIDE_VOLATILE_JUMBO.S */ 10530/* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 10531 /* 10532 * Jumbo 64-bit instance field get. 10533 */ 10534 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 10535 FETCH(r1, 1) @ r1<- aaaa (lo) 10536 FETCH(r2, 2) @ r2<- AAAA (hi) 10537 FETCH(r0, 4) @ r0<- CCCC 10538 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10539 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10540 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 10541 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10542 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10543 cmp r0, #0 @ is resolved entry null? 10544 bne .LOP_IGET_WIDE_VOLATILE_JUMBO_finish @ no, already resolved 10545 ldr r2, [rSELF, #offThread_method] @ r2<- current method 10546 EXPORT_PC() @ resolve() could throw 10547 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10548 bl dvmResolveInstField @ r0<- resolved InstField ptr 10549 b .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue 10550 10551 10552/* ------------------------------ */ 10553 .balign 64 10554.L_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */ 10555/* File: armv5te/OP_IGET_OBJECT_VOLATILE_JUMBO.S */ 10556/* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 10557/* File: armv5te/OP_IGET_JUMBO.S */ 10558 /* 10559 * Jumbo 32-bit instance field get. 10560 * 10561 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 10562 * iget-char/jumbo, iget-short/jumbo 10563 */ 10564 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 10565 FETCH(r1, 1) @ r1<- aaaa (lo) 10566 FETCH(r2, 2) @ r2<- AAAA (hi) 10567 FETCH(r0, 4) @ r0<- CCCC 10568 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10569 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10570 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10571 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10572 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10573 cmp r0, #0 @ is resolved entry null? 10574 bne .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved 105758: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10576 EXPORT_PC() @ resolve() could throw 10577 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10578 bl dvmResolveInstField @ r0<- resolved InstField ptr 10579 b .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue 10580 10581 10582 10583/* ------------------------------ */ 10584 .balign 64 10585.L_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */ 10586/* File: armv5te/OP_IPUT_VOLATILE_JUMBO.S */ 10587/* File: armv5te/OP_IPUT_JUMBO.S */ 10588 /* 10589 * Jumbo 32-bit instance field put. 10590 * 10591 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 10592 * iput-short/jumbo 10593 */ 10594 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 10595 FETCH(r1, 1) @ r1<- aaaa (lo) 10596 FETCH(r2, 2) @ r2<- AAAA (hi) 10597 FETCH(r0, 4) @ r0<- CCCC 10598 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10599 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10600 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10601 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10602 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10603 cmp r0, #0 @ is resolved entry null? 10604 bne .LOP_IPUT_VOLATILE_JUMBO_finish @ no, already resolved 106058: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10606 EXPORT_PC() @ resolve() could throw 10607 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10608 bl dvmResolveInstField @ r0<- resolved InstField ptr 10609 b .LOP_IPUT_VOLATILE_JUMBO_resolved @ resolved, continue 10610 10611 10612/* ------------------------------ */ 10613 .balign 64 10614.L_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */ 10615/* File: armv5te/OP_IPUT_WIDE_VOLATILE_JUMBO.S */ 10616/* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 10617 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 10618 FETCH(r1, 1) @ r1<- aaaa (lo) 10619 FETCH(r2, 2) @ r2<- AAAA (hi) 10620 FETCH(r0, 4) @ r0<- CCCC 10621 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10622 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10623 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 10624 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 10625 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10626 cmp r0, #0 @ is resolved entry null? 10627 bne .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish @ no, already resolved 106288: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10629 EXPORT_PC() @ resolve() could throw 10630 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10631 bl dvmResolveInstField @ r0<- resolved InstField ptr 10632 b .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue 10633 10634 10635/* ------------------------------ */ 10636 .balign 64 10637.L_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */ 10638/* File: armv5te/OP_IPUT_OBJECT_VOLATILE_JUMBO.S */ 10639/* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 10640 /* 10641 * Jumbo 32-bit instance field put. 10642 */ 10643 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 10644 FETCH(r1, 1) @ r1<- aaaa (lo) 10645 FETCH(r2, 2) @ r2<- AAAA (hi) 10646 FETCH(r0, 4) @ r0<- CCCC 10647 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10648 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10649 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10650 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10651 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10652 cmp r0, #0 @ is resolved entry null? 10653 bne .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved 106548: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10655 EXPORT_PC() @ resolve() could throw 10656 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10657 bl dvmResolveInstField @ r0<- resolved InstField ptr 10658 b .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue 10659 10660 10661/* ------------------------------ */ 10662 .balign 64 10663.L_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */ 10664/* File: armv5te/OP_SGET_VOLATILE_JUMBO.S */ 10665/* File: armv5te/OP_SGET_JUMBO.S */ 10666 /* 10667 * Jumbo 32-bit SGET handler. 10668 * 10669 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 10670 * sget-char/jumbo, sget-short/jumbo 10671 */ 10672 /* exop vBBBB, field@AAAAAAAA */ 10673 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10674 FETCH(r0, 1) @ r0<- aaaa (lo) 10675 FETCH(r1, 2) @ r1<- AAAA (hi) 10676 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10677 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10678 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10679 cmp r0, #0 @ is resolved entry null? 10680 beq .LOP_SGET_VOLATILE_JUMBO_resolve @ yes, do resolve 10681.LOP_SGET_VOLATILE_JUMBO_finish: @ field ptr in r0 10682 ldr r1, [r0, #offStaticField_value] @ r1<- field value 10683 SMP_DMB @ acquiring load 10684 FETCH(r2, 3) @ r2<- BBBB 10685 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10686 SET_VREG(r1, r2) @ fp[BBBB]<- r1 10687 GET_INST_OPCODE(ip) @ extract opcode from rINST 10688 GOTO_OPCODE(ip) @ jump to next instruction 10689 10690 10691/* ------------------------------ */ 10692 .balign 64 10693.L_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */ 10694/* File: armv5te/OP_SGET_WIDE_VOLATILE_JUMBO.S */ 10695/* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 10696 /* 10697 * Jumbo 64-bit SGET handler. 10698 */ 10699 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 10700 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10701 FETCH(r0, 1) @ r0<- aaaa (lo) 10702 FETCH(r1, 2) @ r1<- AAAA (hi) 10703 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10704 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10705 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10706 cmp r0, #0 @ is resolved entry null? 10707 beq .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve 10708.LOP_SGET_WIDE_VOLATILE_JUMBO_finish: 10709 FETCH(r9, 3) @ r9<- BBBB 10710 .if 1 10711 add r0, r0, #offStaticField_value @ r0<- pointer to data 10712 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 10713 .else 10714 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 10715 .endif 10716 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 10717 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10718 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 10719 GET_INST_OPCODE(ip) @ extract opcode from rINST 10720 GOTO_OPCODE(ip) @ jump to next instruction 10721 10722 10723/* ------------------------------ */ 10724 .balign 64 10725.L_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */ 10726/* File: armv5te/OP_SGET_OBJECT_VOLATILE_JUMBO.S */ 10727/* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 10728/* File: armv5te/OP_SGET_JUMBO.S */ 10729 /* 10730 * Jumbo 32-bit SGET handler. 10731 * 10732 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 10733 * sget-char/jumbo, sget-short/jumbo 10734 */ 10735 /* exop vBBBB, field@AAAAAAAA */ 10736 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10737 FETCH(r0, 1) @ r0<- aaaa (lo) 10738 FETCH(r1, 2) @ r1<- AAAA (hi) 10739 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10740 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10741 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10742 cmp r0, #0 @ is resolved entry null? 10743 beq .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve 10744.LOP_SGET_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0 10745 ldr r1, [r0, #offStaticField_value] @ r1<- field value 10746 SMP_DMB @ acquiring load 10747 FETCH(r2, 3) @ r2<- BBBB 10748 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10749 SET_VREG(r1, r2) @ fp[BBBB]<- r1 10750 GET_INST_OPCODE(ip) @ extract opcode from rINST 10751 GOTO_OPCODE(ip) @ jump to next instruction 10752 10753 10754 10755/* ------------------------------ */ 10756 .balign 64 10757.L_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */ 10758/* File: armv5te/OP_SPUT_VOLATILE_JUMBO.S */ 10759/* File: armv5te/OP_SPUT_JUMBO.S */ 10760 /* 10761 * Jumbo 32-bit SPUT handler. 10762 * 10763 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 10764 * sput-short/jumbo 10765 */ 10766 /* exop vBBBB, field@AAAAAAAA */ 10767 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10768 FETCH(r0, 1) @ r0<- aaaa (lo) 10769 FETCH(r1, 2) @ r1<- AAAA (hi) 10770 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10771 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10772 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10773 cmp r0, #0 @ is resolved entry null? 10774 beq .LOP_SPUT_VOLATILE_JUMBO_resolve @ yes, do resolve 10775.LOP_SPUT_VOLATILE_JUMBO_finish: @ field ptr in r0 10776 FETCH(r2, 3) @ r2<- BBBB 10777 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10778 GET_VREG(r1, r2) @ r1<- fp[BBBB] 10779 GET_INST_OPCODE(ip) @ extract opcode from rINST 10780 SMP_DMB @ releasing store 10781 str r1, [r0, #offStaticField_value] @ field<- vBBBB 10782 GOTO_OPCODE(ip) @ jump to next instruction 10783 10784 10785/* ------------------------------ */ 10786 .balign 64 10787.L_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */ 10788/* File: armv5te/OP_SPUT_WIDE_VOLATILE_JUMBO.S */ 10789/* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 10790 /* 10791 * Jumbo 64-bit SPUT handler. 10792 */ 10793 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 10794 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 10795 FETCH(r1, 1) @ r1<- aaaa (lo) 10796 FETCH(r2, 2) @ r2<- AAAA (hi) 10797 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 10798 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10799 FETCH(r9, 3) @ r9<- BBBB 10800 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 10801 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 10802 cmp r2, #0 @ is resolved entry null? 10803 beq .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve 10804.LOP_SPUT_WIDE_VOLATILE_JUMBO_finish: @ field ptr in r2, BBBB in r9 10805 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10806 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 10807 GET_INST_OPCODE(r10) @ extract opcode from rINST 10808 .if 1 10809 add r2, r2, #offStaticField_value @ r2<- pointer to data 10810 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 10811 .else 10812 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 10813 .endif 10814 GOTO_OPCODE(r10) @ jump to next instruction 10815 10816 10817/* ------------------------------ */ 10818 .balign 64 10819.L_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */ 10820/* File: armv5te/OP_SPUT_OBJECT_VOLATILE_JUMBO.S */ 10821/* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 10822 /* 10823 * Jumbo 32-bit SPUT handler for objects 10824 */ 10825 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 10826 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10827 FETCH(r0, 1) @ r0<- aaaa (lo) 10828 FETCH(r1, 2) @ r1<- AAAA (hi) 10829 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10830 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10831 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10832 cmp r0, #0 @ is resolved entry null? 10833 bne .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ no, continue 10834 ldr r9, [rSELF, #offThread_method] @ r9<- current method 10835 EXPORT_PC() @ resolve() could throw, so export now 10836 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 10837 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 10838 cmp r0, #0 @ success? 10839 bne .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ yes, finish 10840 b common_exceptionThrown @ no, handle exception 10841 10842 10843/* ------------------------------ */ 10844 .balign 64 10845.L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 10846/* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */ 10847 /* 10848 * Handle a jumbo throw-verification-error instruction. This throws an 10849 * exception for an error discovered during verification. The 10850 * exception is indicated by BBBB, with some detail provided by AAAAAAAA. 10851 */ 10852 /* exop BBBB, Class@AAAAAAAA */ 10853 FETCH(r1, 1) @ r1<- aaaa (lo) 10854 FETCH(r2, 2) @ r2<- AAAA (hi) 10855 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10856 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa 10857 EXPORT_PC() @ export the PC 10858 FETCH(r1, 3) @ r1<- BBBB 10859 bl dvmThrowVerificationError @ always throws 10860 b common_exceptionThrown @ handle exception 10861 10862 .balign 64 10863 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 10864 .global dvmAsmInstructionEnd 10865dvmAsmInstructionEnd: 10866 10867/* 10868 * =========================================================================== 10869 * Sister implementations 10870 * =========================================================================== 10871 */ 10872 .global dvmAsmSisterStart 10873 .type dvmAsmSisterStart, %function 10874 .text 10875 .balign 4 10876dvmAsmSisterStart: 10877 10878/* continuation for OP_CONST_STRING */ 10879 10880 /* 10881 * Continuation if the String has not yet been resolved. 10882 * r1: BBBB (String ref) 10883 * r9: target register 10884 */ 10885.LOP_CONST_STRING_resolve: 10886 EXPORT_PC() 10887 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10888 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10889 bl dvmResolveString @ r0<- String reference 10890 cmp r0, #0 @ failed? 10891 beq common_exceptionThrown @ yup, handle the exception 10892 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10893 GET_INST_OPCODE(ip) @ extract opcode from rINST 10894 SET_VREG(r0, r9) @ vAA<- r0 10895 GOTO_OPCODE(ip) @ jump to next instruction 10896 10897/* continuation for OP_CONST_STRING_JUMBO */ 10898 10899 /* 10900 * Continuation if the String has not yet been resolved. 10901 * r1: BBBBBBBB (String ref) 10902 * r9: target register 10903 */ 10904.LOP_CONST_STRING_JUMBO_resolve: 10905 EXPORT_PC() 10906 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10907 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10908 bl dvmResolveString @ r0<- String reference 10909 cmp r0, #0 @ failed? 10910 beq common_exceptionThrown @ yup, handle the exception 10911 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10912 GET_INST_OPCODE(ip) @ extract opcode from rINST 10913 SET_VREG(r0, r9) @ vAA<- r0 10914 GOTO_OPCODE(ip) @ jump to next instruction 10915 10916/* continuation for OP_CONST_CLASS */ 10917 10918 /* 10919 * Continuation if the Class has not yet been resolved. 10920 * r1: BBBB (Class ref) 10921 * r9: target register 10922 */ 10923.LOP_CONST_CLASS_resolve: 10924 EXPORT_PC() 10925 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10926 mov r2, #1 @ r2<- true 10927 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10928 bl dvmResolveClass @ r0<- Class reference 10929 cmp r0, #0 @ failed? 10930 beq common_exceptionThrown @ yup, handle the exception 10931 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10932 GET_INST_OPCODE(ip) @ extract opcode from rINST 10933 SET_VREG(r0, r9) @ vAA<- r0 10934 GOTO_OPCODE(ip) @ jump to next instruction 10935 10936/* continuation for OP_CHECK_CAST */ 10937 10938 /* 10939 * Trivial test failed, need to perform full check. This is common. 10940 * r0 holds obj->clazz 10941 * r1 holds desired class resolved from BBBB 10942 * r9 holds object 10943 */ 10944.LOP_CHECK_CAST_fullcheck: 10945 mov r10, r1 @ avoid ClassObject getting clobbered 10946 bl dvmInstanceofNonTrivial @ r0<- boolean result 10947 cmp r0, #0 @ failed? 10948 bne .LOP_CHECK_CAST_okay @ no, success 10949 10950 @ A cast has failed. We need to throw a ClassCastException. 10951 EXPORT_PC() @ about to throw 10952 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 10953 mov r1, r10 @ r1<- desired class 10954 bl dvmThrowClassCastException 10955 b common_exceptionThrown 10956 10957 /* 10958 * Resolution required. This is the least-likely path. 10959 * 10960 * r2 holds BBBB 10961 * r9 holds object 10962 */ 10963.LOP_CHECK_CAST_resolve: 10964 EXPORT_PC() @ resolve() could throw 10965 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10966 mov r1, r2 @ r1<- BBBB 10967 mov r2, #0 @ r2<- false 10968 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10969 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10970 cmp r0, #0 @ got null? 10971 beq common_exceptionThrown @ yes, handle exception 10972 mov r1, r0 @ r1<- class resolved from BBB 10973 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 10974 b .LOP_CHECK_CAST_resolved @ pick up where we left off 10975 10976/* continuation for OP_INSTANCE_OF */ 10977 10978 /* 10979 * Trivial test failed, need to perform full check. This is common. 10980 * r0 holds obj->clazz 10981 * r1 holds class resolved from BBBB 10982 * r9 holds A 10983 */ 10984.LOP_INSTANCE_OF_fullcheck: 10985 bl dvmInstanceofNonTrivial @ r0<- boolean result 10986 @ fall through to OP_INSTANCE_OF_store 10987 10988 /* 10989 * r0 holds boolean result 10990 * r9 holds A 10991 */ 10992.LOP_INSTANCE_OF_store: 10993 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10994 SET_VREG(r0, r9) @ vA<- r0 10995 GET_INST_OPCODE(ip) @ extract opcode from rINST 10996 GOTO_OPCODE(ip) @ jump to next instruction 10997 10998 /* 10999 * Trivial test succeeded, save and bail. 11000 * r9 holds A 11001 */ 11002.LOP_INSTANCE_OF_trivial: 11003 mov r0, #1 @ indicate success 11004 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 11005 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11006 SET_VREG(r0, r9) @ vA<- r0 11007 GET_INST_OPCODE(ip) @ extract opcode from rINST 11008 GOTO_OPCODE(ip) @ jump to next instruction 11009 11010 /* 11011 * Resolution required. This is the least-likely path. 11012 * 11013 * r3 holds BBBB 11014 * r9 holds A 11015 */ 11016.LOP_INSTANCE_OF_resolve: 11017 EXPORT_PC() @ resolve() could throw 11018 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 11019 mov r1, r3 @ r1<- BBBB 11020 mov r2, #1 @ r2<- true 11021 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 11022 bl dvmResolveClass @ r0<- resolved ClassObject ptr 11023 cmp r0, #0 @ got null? 11024 beq common_exceptionThrown @ yes, handle exception 11025 mov r1, r0 @ r1<- class resolved from BBB 11026 mov r3, rINST, lsr #12 @ r3<- B 11027 GET_VREG(r0, r3) @ r0<- vB (object) 11028 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 11029 b .LOP_INSTANCE_OF_resolved @ pick up where we left off 11030 11031/* continuation for OP_NEW_INSTANCE */ 11032 11033 .balign 32 @ minimize cache lines 11034.LOP_NEW_INSTANCE_finish: @ r0=new object 11035 mov r3, rINST, lsr #8 @ r3<- AA 11036 cmp r0, #0 @ failed? 11037 beq common_exceptionThrown @ yes, handle the exception 11038 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11039 GET_INST_OPCODE(ip) @ extract opcode from rINST 11040 SET_VREG(r0, r3) @ vAA<- r0 11041 GOTO_OPCODE(ip) @ jump to next instruction 11042 11043 /* 11044 * Class initialization required. 11045 * 11046 * r0 holds class object 11047 */ 11048.LOP_NEW_INSTANCE_needinit: 11049 mov r9, r0 @ save r0 11050 bl dvmInitClass @ initialize class 11051 cmp r0, #0 @ check boolean result 11052 mov r0, r9 @ restore r0 11053 bne .LOP_NEW_INSTANCE_initialized @ success, continue 11054 b common_exceptionThrown @ failed, deal with init exception 11055 11056 /* 11057 * Resolution required. This is the least-likely path. 11058 * 11059 * r1 holds BBBB 11060 */ 11061.LOP_NEW_INSTANCE_resolve: 11062 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11063 mov r2, #0 @ r2<- false 11064 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11065 bl dvmResolveClass @ r0<- resolved ClassObject ptr 11066 cmp r0, #0 @ got null? 11067 bne .LOP_NEW_INSTANCE_resolved @ no, continue 11068 b common_exceptionThrown @ yes, handle exception 11069 11070/* continuation for OP_NEW_ARRAY */ 11071 11072 11073 /* 11074 * Resolve class. (This is an uncommon case.) 11075 * 11076 * r1 holds array length 11077 * r2 holds class ref CCCC 11078 */ 11079.LOP_NEW_ARRAY_resolve: 11080 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11081 mov r9, r1 @ r9<- length (save) 11082 mov r1, r2 @ r1<- CCCC 11083 mov r2, #0 @ r2<- false 11084 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11085 bl dvmResolveClass @ r0<- call(clazz, ref) 11086 cmp r0, #0 @ got null? 11087 mov r1, r9 @ r1<- length (restore) 11088 beq common_exceptionThrown @ yes, handle exception 11089 @ fall through to OP_NEW_ARRAY_finish 11090 11091 /* 11092 * Finish allocation. 11093 * 11094 * r0 holds class 11095 * r1 holds array length 11096 */ 11097.LOP_NEW_ARRAY_finish: 11098 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 11099 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 11100 cmp r0, #0 @ failed? 11101 mov r2, rINST, lsr #8 @ r2<- A+ 11102 beq common_exceptionThrown @ yes, handle the exception 11103 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11104 and r2, r2, #15 @ r2<- A 11105 GET_INST_OPCODE(ip) @ extract opcode from rINST 11106 SET_VREG(r0, r2) @ vA<- r0 11107 GOTO_OPCODE(ip) @ jump to next instruction 11108 11109/* continuation for OP_FILLED_NEW_ARRAY */ 11110 11111 /* 11112 * On entry: 11113 * r0 holds array class 11114 * r10 holds AA or BA 11115 */ 11116.LOP_FILLED_NEW_ARRAY_continue: 11117 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 11118 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 11119 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 11120 .if 0 11121 mov r1, r10 @ r1<- AA (length) 11122 .else 11123 mov r1, r10, lsr #4 @ r1<- B (length) 11124 .endif 11125 cmp rINST, #'I' @ array of ints? 11126 cmpne rINST, #'L' @ array of objects? 11127 cmpne rINST, #'[' @ array of arrays? 11128 mov r9, r1 @ save length in r9 11129 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 11130 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 11131 cmp r0, #0 @ null return? 11132 beq common_exceptionThrown @ alloc failed, handle exception 11133 11134 FETCH(r1, 2) @ r1<- FEDC or CCCC 11135 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 11136 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 11137 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 11138 subs r9, r9, #1 @ length--, check for neg 11139 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 11140 bmi 2f @ was zero, bail 11141 11142 @ copy values from registers into the array 11143 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 11144 .if 0 11145 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 111461: ldr r3, [r2], #4 @ r3<- *r2++ 11147 subs r9, r9, #1 @ count-- 11148 str r3, [r0], #4 @ *contents++ = vX 11149 bpl 1b 11150 @ continue at 2 11151 .else 11152 cmp r9, #4 @ length was initially 5? 11153 and r2, r10, #15 @ r2<- A 11154 bne 1f @ <= 4 args, branch 11155 GET_VREG(r3, r2) @ r3<- vA 11156 sub r9, r9, #1 @ count-- 11157 str r3, [r0, #16] @ contents[4] = vA 111581: and r2, r1, #15 @ r2<- F/E/D/C 11159 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 11160 mov r1, r1, lsr #4 @ r1<- next reg in low 4 11161 subs r9, r9, #1 @ count-- 11162 str r3, [r0], #4 @ *contents++ = vX 11163 bpl 1b 11164 @ continue at 2 11165 .endif 11166 111672: 11168 ldr r0, [rSELF, #offThread_retval] @ r0<- object 11169 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 11170 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11171 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 11172 cmp r1, #'I' @ Is int array? 11173 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 11174 GOTO_OPCODE(ip) @ execute it 11175 11176 /* 11177 * Throw an exception indicating that we have not implemented this 11178 * mode of filled-new-array. 11179 */ 11180.LOP_FILLED_NEW_ARRAY_notimpl: 11181 ldr r0, .L_strFilledNewArrayNotImpl 11182 bl dvmThrowInternalError 11183 b common_exceptionThrown 11184 11185 .if (!0) @ define in one or the other, not both 11186.L_strFilledNewArrayNotImpl: 11187 .word .LstrFilledNewArrayNotImpl 11188 .endif 11189 11190/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 11191 11192 /* 11193 * On entry: 11194 * r0 holds array class 11195 * r10 holds AA or BA 11196 */ 11197.LOP_FILLED_NEW_ARRAY_RANGE_continue: 11198 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 11199 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 11200 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 11201 .if 1 11202 mov r1, r10 @ r1<- AA (length) 11203 .else 11204 mov r1, r10, lsr #4 @ r1<- B (length) 11205 .endif 11206 cmp rINST, #'I' @ array of ints? 11207 cmpne rINST, #'L' @ array of objects? 11208 cmpne rINST, #'[' @ array of arrays? 11209 mov r9, r1 @ save length in r9 11210 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 11211 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 11212 cmp r0, #0 @ null return? 11213 beq common_exceptionThrown @ alloc failed, handle exception 11214 11215 FETCH(r1, 2) @ r1<- FEDC or CCCC 11216 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 11217 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 11218 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 11219 subs r9, r9, #1 @ length--, check for neg 11220 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 11221 bmi 2f @ was zero, bail 11222 11223 @ copy values from registers into the array 11224 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 11225 .if 1 11226 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 112271: ldr r3, [r2], #4 @ r3<- *r2++ 11228 subs r9, r9, #1 @ count-- 11229 str r3, [r0], #4 @ *contents++ = vX 11230 bpl 1b 11231 @ continue at 2 11232 .else 11233 cmp r9, #4 @ length was initially 5? 11234 and r2, r10, #15 @ r2<- A 11235 bne 1f @ <= 4 args, branch 11236 GET_VREG(r3, r2) @ r3<- vA 11237 sub r9, r9, #1 @ count-- 11238 str r3, [r0, #16] @ contents[4] = vA 112391: and r2, r1, #15 @ r2<- F/E/D/C 11240 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 11241 mov r1, r1, lsr #4 @ r1<- next reg in low 4 11242 subs r9, r9, #1 @ count-- 11243 str r3, [r0], #4 @ *contents++ = vX 11244 bpl 1b 11245 @ continue at 2 11246 .endif 11247 112482: 11249 ldr r0, [rSELF, #offThread_retval] @ r0<- object 11250 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 11251 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11252 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 11253 cmp r1, #'I' @ Is int array? 11254 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 11255 GOTO_OPCODE(ip) @ execute it 11256 11257 /* 11258 * Throw an exception indicating that we have not implemented this 11259 * mode of filled-new-array. 11260 */ 11261.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 11262 ldr r0, .L_strFilledNewArrayNotImpl 11263 bl dvmThrowInternalError 11264 b common_exceptionThrown 11265 11266 .if (!1) @ define in one or the other, not both 11267.L_strFilledNewArrayNotImpl: 11268 .word .LstrFilledNewArrayNotImpl 11269 .endif 11270 11271/* continuation for OP_CMPL_FLOAT */ 11272.LOP_CMPL_FLOAT_finish: 11273 SET_VREG(r0, r9) @ vAA<- r0 11274 GOTO_OPCODE(ip) @ jump to next instruction 11275 11276/* continuation for OP_CMPG_FLOAT */ 11277.LOP_CMPG_FLOAT_finish: 11278 SET_VREG(r0, r9) @ vAA<- r0 11279 GOTO_OPCODE(ip) @ jump to next instruction 11280 11281/* continuation for OP_CMPL_DOUBLE */ 11282.LOP_CMPL_DOUBLE_finish: 11283 SET_VREG(r0, r9) @ vAA<- r0 11284 GOTO_OPCODE(ip) @ jump to next instruction 11285 11286/* continuation for OP_CMPG_DOUBLE */ 11287.LOP_CMPG_DOUBLE_finish: 11288 SET_VREG(r0, r9) @ vAA<- r0 11289 GOTO_OPCODE(ip) @ jump to next instruction 11290 11291/* continuation for OP_CMP_LONG */ 11292 11293.LOP_CMP_LONG_less: 11294 mvn r1, #0 @ r1<- -1 11295 @ Want to cond code the next mov so we can avoid branch, but don't see it; 11296 @ instead, we just replicate the tail end. 11297 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11298 SET_VREG(r1, r9) @ vAA<- r1 11299 GET_INST_OPCODE(ip) @ extract opcode from rINST 11300 GOTO_OPCODE(ip) @ jump to next instruction 11301 11302.LOP_CMP_LONG_greater: 11303 mov r1, #1 @ r1<- 1 11304 @ fall through to _finish 11305 11306.LOP_CMP_LONG_finish: 11307 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11308 SET_VREG(r1, r9) @ vAA<- r1 11309 GET_INST_OPCODE(ip) @ extract opcode from rINST 11310 GOTO_OPCODE(ip) @ jump to next instruction 11311 11312/* continuation for OP_AGET_WIDE */ 11313 11314.LOP_AGET_WIDE_finish: 11315 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11316 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11317 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 11318 GET_INST_OPCODE(ip) @ extract opcode from rINST 11319 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 11320 GOTO_OPCODE(ip) @ jump to next instruction 11321 11322/* continuation for OP_APUT_WIDE */ 11323 11324.LOP_APUT_WIDE_finish: 11325 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11326 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 11327 GET_INST_OPCODE(ip) @ extract opcode from rINST 11328 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11329 GOTO_OPCODE(ip) @ jump to next instruction 11330 11331/* continuation for OP_APUT_OBJECT */ 11332 /* 11333 * On entry: 11334 * rINST = vBB (arrayObj) 11335 * r9 = vAA (obj) 11336 * r10 = offset into array (vBB + vCC * width) 11337 */ 11338.LOP_APUT_OBJECT_finish: 11339 cmp r9, #0 @ storing null reference? 11340 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 11341 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 11342 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz 11343 bl dvmCanPutArrayElement @ test object type vs. array type 11344 cmp r0, #0 @ okay? 11345 beq .LOP_APUT_OBJECT_throw @ no 11346 mov r1, rINST @ r1<- arrayObj 11347 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11348 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base 11349 add r10, #offArrayObject_contents @ r0<- pointer to slot 11350 GET_INST_OPCODE(ip) @ extract opcode from rINST 11351 str r9, [r10] @ vBB[vCC]<- vAA 11352 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head 11353 GOTO_OPCODE(ip) @ jump to next instruction 11354.LOP_APUT_OBJECT_skip_check: 11355 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11356 GET_INST_OPCODE(ip) @ extract opcode from rINST 11357 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 11358 GOTO_OPCODE(ip) @ jump to next instruction 11359.LOP_APUT_OBJECT_throw: 11360 @ The types don't match. We need to throw an ArrayStoreException. 11361 ldr r0, [r9, #offObject_clazz] 11362 ldr r1, [rINST, #offObject_clazz] 11363 EXPORT_PC() 11364 bl dvmThrowArrayStoreExceptionIncompatibleElement 11365 b common_exceptionThrown 11366 11367/* continuation for OP_IGET */ 11368 11369 /* 11370 * Currently: 11371 * r0 holds resolved field 11372 * r9 holds object 11373 */ 11374.LOP_IGET_finish: 11375 @bl common_squeak0 11376 cmp r9, #0 @ check object for null 11377 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11378 beq common_errNullObject @ object was null 11379 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11380 @ no-op @ acquiring load 11381 mov r2, rINST, lsr #8 @ r2<- A+ 11382 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11383 and r2, r2, #15 @ r2<- A 11384 GET_INST_OPCODE(ip) @ extract opcode from rINST 11385 SET_VREG(r0, r2) @ fp[A]<- r0 11386 GOTO_OPCODE(ip) @ jump to next instruction 11387 11388/* continuation for OP_IGET_WIDE */ 11389 11390 /* 11391 * Currently: 11392 * r0 holds resolved field 11393 * r9 holds object 11394 */ 11395.LOP_IGET_WIDE_finish: 11396 cmp r9, #0 @ check object for null 11397 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11398 beq common_errNullObject @ object was null 11399 .if 0 11400 add r0, r9, r3 @ r0<- address of field 11401 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 11402 .else 11403 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11404 .endif 11405 mov r2, rINST, lsr #8 @ r2<- A+ 11406 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11407 and r2, r2, #15 @ r2<- A 11408 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11409 GET_INST_OPCODE(ip) @ extract opcode from rINST 11410 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11411 GOTO_OPCODE(ip) @ jump to next instruction 11412 11413/* continuation for OP_IGET_OBJECT */ 11414 11415 /* 11416 * Currently: 11417 * r0 holds resolved field 11418 * r9 holds object 11419 */ 11420.LOP_IGET_OBJECT_finish: 11421 @bl common_squeak0 11422 cmp r9, #0 @ check object for null 11423 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11424 beq common_errNullObject @ object was null 11425 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11426 @ no-op @ acquiring load 11427 mov r2, rINST, lsr #8 @ r2<- A+ 11428 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11429 and r2, r2, #15 @ r2<- A 11430 GET_INST_OPCODE(ip) @ extract opcode from rINST 11431 SET_VREG(r0, r2) @ fp[A]<- r0 11432 GOTO_OPCODE(ip) @ jump to next instruction 11433 11434/* continuation for OP_IGET_BOOLEAN */ 11435 11436 /* 11437 * Currently: 11438 * r0 holds resolved field 11439 * r9 holds object 11440 */ 11441.LOP_IGET_BOOLEAN_finish: 11442 @bl common_squeak1 11443 cmp r9, #0 @ check object for null 11444 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11445 beq common_errNullObject @ object was null 11446 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11447 @ no-op @ acquiring load 11448 mov r2, rINST, lsr #8 @ r2<- A+ 11449 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11450 and r2, r2, #15 @ r2<- A 11451 GET_INST_OPCODE(ip) @ extract opcode from rINST 11452 SET_VREG(r0, r2) @ fp[A]<- r0 11453 GOTO_OPCODE(ip) @ jump to next instruction 11454 11455/* continuation for OP_IGET_BYTE */ 11456 11457 /* 11458 * Currently: 11459 * r0 holds resolved field 11460 * r9 holds object 11461 */ 11462.LOP_IGET_BYTE_finish: 11463 @bl common_squeak2 11464 cmp r9, #0 @ check object for null 11465 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11466 beq common_errNullObject @ object was null 11467 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11468 @ no-op @ acquiring load 11469 mov r2, rINST, lsr #8 @ r2<- A+ 11470 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11471 and r2, r2, #15 @ r2<- A 11472 GET_INST_OPCODE(ip) @ extract opcode from rINST 11473 SET_VREG(r0, r2) @ fp[A]<- r0 11474 GOTO_OPCODE(ip) @ jump to next instruction 11475 11476/* continuation for OP_IGET_CHAR */ 11477 11478 /* 11479 * Currently: 11480 * r0 holds resolved field 11481 * r9 holds object 11482 */ 11483.LOP_IGET_CHAR_finish: 11484 @bl common_squeak3 11485 cmp r9, #0 @ check object for null 11486 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11487 beq common_errNullObject @ object was null 11488 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11489 @ no-op @ acquiring load 11490 mov r2, rINST, lsr #8 @ r2<- A+ 11491 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11492 and r2, r2, #15 @ r2<- A 11493 GET_INST_OPCODE(ip) @ extract opcode from rINST 11494 SET_VREG(r0, r2) @ fp[A]<- r0 11495 GOTO_OPCODE(ip) @ jump to next instruction 11496 11497/* continuation for OP_IGET_SHORT */ 11498 11499 /* 11500 * Currently: 11501 * r0 holds resolved field 11502 * r9 holds object 11503 */ 11504.LOP_IGET_SHORT_finish: 11505 @bl common_squeak4 11506 cmp r9, #0 @ check object for null 11507 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11508 beq common_errNullObject @ object was null 11509 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11510 @ no-op @ acquiring load 11511 mov r2, rINST, lsr #8 @ r2<- A+ 11512 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11513 and r2, r2, #15 @ r2<- A 11514 GET_INST_OPCODE(ip) @ extract opcode from rINST 11515 SET_VREG(r0, r2) @ fp[A]<- r0 11516 GOTO_OPCODE(ip) @ jump to next instruction 11517 11518/* continuation for OP_IPUT */ 11519 11520 /* 11521 * Currently: 11522 * r0 holds resolved field 11523 * r9 holds object 11524 */ 11525.LOP_IPUT_finish: 11526 @bl common_squeak0 11527 mov r1, rINST, lsr #8 @ r1<- A+ 11528 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11529 and r1, r1, #15 @ r1<- A 11530 cmp r9, #0 @ check object for null 11531 GET_VREG(r0, r1) @ r0<- fp[A] 11532 beq common_errNullObject @ object was null 11533 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11534 GET_INST_OPCODE(ip) @ extract opcode from rINST 11535 @ no-op @ releasing store 11536 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11537 GOTO_OPCODE(ip) @ jump to next instruction 11538 11539/* continuation for OP_IPUT_WIDE */ 11540 11541 /* 11542 * Currently: 11543 * r0 holds resolved field 11544 * r9 holds object 11545 */ 11546.LOP_IPUT_WIDE_finish: 11547 mov r2, rINST, lsr #8 @ r2<- A+ 11548 cmp r9, #0 @ check object for null 11549 and r2, r2, #15 @ r2<- A 11550 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11551 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 11552 beq common_errNullObject @ object was null 11553 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11554 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 11555 GET_INST_OPCODE(r10) @ extract opcode from rINST 11556 .if 0 11557 add r2, r9, r3 @ r2<- target address 11558 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 11559 .else 11560 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 11561 .endif 11562 GOTO_OPCODE(r10) @ jump to next instruction 11563 11564/* continuation for OP_IPUT_OBJECT */ 11565 11566 /* 11567 * Currently: 11568 * r0 holds resolved field 11569 * r9 holds object 11570 */ 11571.LOP_IPUT_OBJECT_finish: 11572 @bl common_squeak0 11573 mov r1, rINST, lsr #8 @ r1<- A+ 11574 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11575 and r1, r1, #15 @ r1<- A 11576 cmp r9, #0 @ check object for null 11577 GET_VREG(r0, r1) @ r0<- fp[A] 11578 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11579 beq common_errNullObject @ object was null 11580 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11581 GET_INST_OPCODE(ip) @ extract opcode from rINST 11582 @ no-op @ releasing store 11583 str r0, [r9, r3] @ obj.field (32 bits)<- r0 11584 cmp r0, #0 @ stored a null reference? 11585 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 11586 GOTO_OPCODE(ip) @ jump to next instruction 11587 11588/* continuation for OP_IPUT_BOOLEAN */ 11589 11590 /* 11591 * Currently: 11592 * r0 holds resolved field 11593 * r9 holds object 11594 */ 11595.LOP_IPUT_BOOLEAN_finish: 11596 @bl common_squeak1 11597 mov r1, rINST, lsr #8 @ r1<- A+ 11598 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11599 and r1, r1, #15 @ r1<- A 11600 cmp r9, #0 @ check object for null 11601 GET_VREG(r0, r1) @ r0<- fp[A] 11602 beq common_errNullObject @ object was null 11603 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11604 GET_INST_OPCODE(ip) @ extract opcode from rINST 11605 @ no-op @ releasing store 11606 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11607 GOTO_OPCODE(ip) @ jump to next instruction 11608 11609/* continuation for OP_IPUT_BYTE */ 11610 11611 /* 11612 * Currently: 11613 * r0 holds resolved field 11614 * r9 holds object 11615 */ 11616.LOP_IPUT_BYTE_finish: 11617 @bl common_squeak2 11618 mov r1, rINST, lsr #8 @ r1<- A+ 11619 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11620 and r1, r1, #15 @ r1<- A 11621 cmp r9, #0 @ check object for null 11622 GET_VREG(r0, r1) @ r0<- fp[A] 11623 beq common_errNullObject @ object was null 11624 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11625 GET_INST_OPCODE(ip) @ extract opcode from rINST 11626 @ no-op @ releasing store 11627 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11628 GOTO_OPCODE(ip) @ jump to next instruction 11629 11630/* continuation for OP_IPUT_CHAR */ 11631 11632 /* 11633 * Currently: 11634 * r0 holds resolved field 11635 * r9 holds object 11636 */ 11637.LOP_IPUT_CHAR_finish: 11638 @bl common_squeak3 11639 mov r1, rINST, lsr #8 @ r1<- A+ 11640 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11641 and r1, r1, #15 @ r1<- A 11642 cmp r9, #0 @ check object for null 11643 GET_VREG(r0, r1) @ r0<- fp[A] 11644 beq common_errNullObject @ object was null 11645 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11646 GET_INST_OPCODE(ip) @ extract opcode from rINST 11647 @ no-op @ releasing store 11648 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11649 GOTO_OPCODE(ip) @ jump to next instruction 11650 11651/* continuation for OP_IPUT_SHORT */ 11652 11653 /* 11654 * Currently: 11655 * r0 holds resolved field 11656 * r9 holds object 11657 */ 11658.LOP_IPUT_SHORT_finish: 11659 @bl common_squeak4 11660 mov r1, rINST, lsr #8 @ r1<- A+ 11661 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11662 and r1, r1, #15 @ r1<- A 11663 cmp r9, #0 @ check object for null 11664 GET_VREG(r0, r1) @ r0<- fp[A] 11665 beq common_errNullObject @ object was null 11666 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11667 GET_INST_OPCODE(ip) @ extract opcode from rINST 11668 @ no-op @ releasing store 11669 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11670 GOTO_OPCODE(ip) @ jump to next instruction 11671 11672/* continuation for OP_SGET */ 11673 11674 /* 11675 * Continuation if the field has not yet been resolved. 11676 * r1: BBBB field ref 11677 */ 11678.LOP_SGET_resolve: 11679 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11680 EXPORT_PC() @ resolve() could throw, so export now 11681 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11682 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11683 cmp r0, #0 @ success? 11684 bne .LOP_SGET_finish @ yes, finish 11685 b common_exceptionThrown @ no, handle exception 11686 11687/* continuation for OP_SGET_WIDE */ 11688 11689 /* 11690 * Continuation if the field has not yet been resolved. 11691 * r1: BBBB field ref 11692 * 11693 * Returns StaticField pointer in r0. 11694 */ 11695.LOP_SGET_WIDE_resolve: 11696 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11697 EXPORT_PC() @ resolve() could throw, so export now 11698 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11699 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11700 cmp r0, #0 @ success? 11701 bne .LOP_SGET_WIDE_finish @ yes, finish 11702 b common_exceptionThrown @ no, handle exception 11703 11704/* continuation for OP_SGET_OBJECT */ 11705 11706 /* 11707 * Continuation if the field has not yet been resolved. 11708 * r1: BBBB field ref 11709 */ 11710.LOP_SGET_OBJECT_resolve: 11711 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11712 EXPORT_PC() @ resolve() could throw, so export now 11713 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11714 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11715 cmp r0, #0 @ success? 11716 bne .LOP_SGET_OBJECT_finish @ yes, finish 11717 b common_exceptionThrown @ no, handle exception 11718 11719/* continuation for OP_SGET_BOOLEAN */ 11720 11721 /* 11722 * Continuation if the field has not yet been resolved. 11723 * r1: BBBB field ref 11724 */ 11725.LOP_SGET_BOOLEAN_resolve: 11726 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11727 EXPORT_PC() @ resolve() could throw, so export now 11728 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11729 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11730 cmp r0, #0 @ success? 11731 bne .LOP_SGET_BOOLEAN_finish @ yes, finish 11732 b common_exceptionThrown @ no, handle exception 11733 11734/* continuation for OP_SGET_BYTE */ 11735 11736 /* 11737 * Continuation if the field has not yet been resolved. 11738 * r1: BBBB field ref 11739 */ 11740.LOP_SGET_BYTE_resolve: 11741 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11742 EXPORT_PC() @ resolve() could throw, so export now 11743 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11744 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11745 cmp r0, #0 @ success? 11746 bne .LOP_SGET_BYTE_finish @ yes, finish 11747 b common_exceptionThrown @ no, handle exception 11748 11749/* continuation for OP_SGET_CHAR */ 11750 11751 /* 11752 * Continuation if the field has not yet been resolved. 11753 * r1: BBBB field ref 11754 */ 11755.LOP_SGET_CHAR_resolve: 11756 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11757 EXPORT_PC() @ resolve() could throw, so export now 11758 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11759 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11760 cmp r0, #0 @ success? 11761 bne .LOP_SGET_CHAR_finish @ yes, finish 11762 b common_exceptionThrown @ no, handle exception 11763 11764/* continuation for OP_SGET_SHORT */ 11765 11766 /* 11767 * Continuation if the field has not yet been resolved. 11768 * r1: BBBB field ref 11769 */ 11770.LOP_SGET_SHORT_resolve: 11771 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11772 EXPORT_PC() @ resolve() could throw, so export now 11773 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11774 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11775 cmp r0, #0 @ success? 11776 bne .LOP_SGET_SHORT_finish @ yes, finish 11777 b common_exceptionThrown @ no, handle exception 11778 11779/* continuation for OP_SPUT */ 11780 11781 /* 11782 * Continuation if the field has not yet been resolved. 11783 * r1: BBBB field ref 11784 */ 11785.LOP_SPUT_resolve: 11786 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11787 EXPORT_PC() @ resolve() could throw, so export now 11788 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11789 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11790 cmp r0, #0 @ success? 11791 bne .LOP_SPUT_finish @ yes, finish 11792 b common_exceptionThrown @ no, handle exception 11793 11794/* continuation for OP_SPUT_WIDE */ 11795 11796 /* 11797 * Continuation if the field has not yet been resolved. 11798 * r1: BBBB field ref 11799 * r9: &fp[AA] 11800 * 11801 * Returns StaticField pointer in r2. 11802 */ 11803.LOP_SPUT_WIDE_resolve: 11804 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11805 EXPORT_PC() @ resolve() could throw, so export now 11806 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11807 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11808 cmp r0, #0 @ success? 11809 mov r2, r0 @ copy to r2 11810 bne .LOP_SPUT_WIDE_finish @ yes, finish 11811 b common_exceptionThrown @ no, handle exception 11812 11813/* continuation for OP_SPUT_OBJECT */ 11814.LOP_SPUT_OBJECT_finish: @ field ptr in r0 11815 mov r2, rINST, lsr #8 @ r2<- AA 11816 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11817 GET_VREG(r1, r2) @ r1<- fp[AA] 11818 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11819 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 11820 GET_INST_OPCODE(ip) @ extract opcode from rINST 11821 @ no-op @ releasing store 11822 str r1, [r0, #offStaticField_value] @ field<- vAA 11823 cmp r1, #0 @ stored a null object? 11824 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 11825 GOTO_OPCODE(ip) @ jump to next instruction 11826 11827/* continuation for OP_SPUT_BOOLEAN */ 11828 11829 /* 11830 * Continuation if the field has not yet been resolved. 11831 * r1: BBBB field ref 11832 */ 11833.LOP_SPUT_BOOLEAN_resolve: 11834 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11835 EXPORT_PC() @ resolve() could throw, so export now 11836 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11837 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11838 cmp r0, #0 @ success? 11839 bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 11840 b common_exceptionThrown @ no, handle exception 11841 11842/* continuation for OP_SPUT_BYTE */ 11843 11844 /* 11845 * Continuation if the field has not yet been resolved. 11846 * r1: BBBB field ref 11847 */ 11848.LOP_SPUT_BYTE_resolve: 11849 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11850 EXPORT_PC() @ resolve() could throw, so export now 11851 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11852 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11853 cmp r0, #0 @ success? 11854 bne .LOP_SPUT_BYTE_finish @ yes, finish 11855 b common_exceptionThrown @ no, handle exception 11856 11857/* continuation for OP_SPUT_CHAR */ 11858 11859 /* 11860 * Continuation if the field has not yet been resolved. 11861 * r1: BBBB field ref 11862 */ 11863.LOP_SPUT_CHAR_resolve: 11864 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11865 EXPORT_PC() @ resolve() could throw, so export now 11866 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11867 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11868 cmp r0, #0 @ success? 11869 bne .LOP_SPUT_CHAR_finish @ yes, finish 11870 b common_exceptionThrown @ no, handle exception 11871 11872/* continuation for OP_SPUT_SHORT */ 11873 11874 /* 11875 * Continuation if the field has not yet been resolved. 11876 * r1: BBBB field ref 11877 */ 11878.LOP_SPUT_SHORT_resolve: 11879 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11880 EXPORT_PC() @ resolve() could throw, so export now 11881 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11882 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11883 cmp r0, #0 @ success? 11884 bne .LOP_SPUT_SHORT_finish @ yes, finish 11885 b common_exceptionThrown @ no, handle exception 11886 11887/* continuation for OP_INVOKE_VIRTUAL */ 11888 11889 /* 11890 * At this point: 11891 * r0 = resolved base method 11892 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11893 */ 11894.LOP_INVOKE_VIRTUAL_continue: 11895 GET_VREG(r1, r10) @ r1<- "this" ptr 11896 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11897 cmp r1, #0 @ is "this" null? 11898 beq common_errNullObject @ null "this", throw exception 11899 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11900 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11901 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11902 bl common_invokeMethodNoRange @ continue on 11903 11904/* continuation for OP_INVOKE_SUPER */ 11905 11906 /* 11907 * At this point: 11908 * r0 = resolved base method 11909 * r9 = method->clazz 11910 */ 11911.LOP_INVOKE_SUPER_continue: 11912 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11913 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11914 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11915 EXPORT_PC() @ must export for invoke 11916 cmp r2, r3 @ compare (methodIndex, vtableCount) 11917 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 11918 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11919 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11920 bl common_invokeMethodNoRange @ continue on 11921 11922.LOP_INVOKE_SUPER_resolve: 11923 mov r0, r9 @ r0<- method->clazz 11924 mov r2, #METHOD_VIRTUAL @ resolver method type 11925 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11926 cmp r0, #0 @ got null? 11927 bne .LOP_INVOKE_SUPER_continue @ no, continue 11928 b common_exceptionThrown @ yes, handle exception 11929 11930 /* 11931 * Throw a NoSuchMethodError with the method name as the message. 11932 * r0 = resolved base method 11933 */ 11934.LOP_INVOKE_SUPER_nsm: 11935 ldr r1, [r0, #offMethod_name] @ r1<- method name 11936 b common_errNoSuchMethod 11937 11938/* continuation for OP_INVOKE_DIRECT */ 11939 11940 /* 11941 * On entry: 11942 * r1 = reference (BBBB or CCCC) 11943 * r10 = "this" register 11944 */ 11945.LOP_INVOKE_DIRECT_resolve: 11946 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11947 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11948 mov r2, #METHOD_DIRECT @ resolver method type 11949 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11950 cmp r0, #0 @ got null? 11951 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 11952 bne .LOP_INVOKE_DIRECT_finish @ no, continue 11953 b common_exceptionThrown @ yes, handle exception 11954 11955/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 11956 11957 /* 11958 * At this point: 11959 * r0 = resolved base method 11960 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11961 */ 11962.LOP_INVOKE_VIRTUAL_RANGE_continue: 11963 GET_VREG(r1, r10) @ r1<- "this" ptr 11964 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11965 cmp r1, #0 @ is "this" null? 11966 beq common_errNullObject @ null "this", throw exception 11967 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11968 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11969 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11970 bl common_invokeMethodRange @ continue on 11971 11972/* continuation for OP_INVOKE_SUPER_RANGE */ 11973 11974 /* 11975 * At this point: 11976 * r0 = resolved base method 11977 * r9 = method->clazz 11978 */ 11979.LOP_INVOKE_SUPER_RANGE_continue: 11980 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11981 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11982 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11983 EXPORT_PC() @ must export for invoke 11984 cmp r2, r3 @ compare (methodIndex, vtableCount) 11985 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 11986 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11987 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11988 bl common_invokeMethodRange @ continue on 11989 11990.LOP_INVOKE_SUPER_RANGE_resolve: 11991 mov r0, r9 @ r0<- method->clazz 11992 mov r2, #METHOD_VIRTUAL @ resolver method type 11993 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11994 cmp r0, #0 @ got null? 11995 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 11996 b common_exceptionThrown @ yes, handle exception 11997 11998 /* 11999 * Throw a NoSuchMethodError with the method name as the message. 12000 * r0 = resolved base method 12001 */ 12002.LOP_INVOKE_SUPER_RANGE_nsm: 12003 ldr r1, [r0, #offMethod_name] @ r1<- method name 12004 b common_errNoSuchMethod 12005 12006/* continuation for OP_INVOKE_DIRECT_RANGE */ 12007 12008 /* 12009 * On entry: 12010 * r1 = reference (BBBB or CCCC) 12011 * r10 = "this" register 12012 */ 12013.LOP_INVOKE_DIRECT_RANGE_resolve: 12014 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12015 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12016 mov r2, #METHOD_DIRECT @ resolver method type 12017 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12018 cmp r0, #0 @ got null? 12019 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 12020 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 12021 b common_exceptionThrown @ yes, handle exception 12022 12023/* continuation for OP_FLOAT_TO_LONG */ 12024/* 12025 * Convert the float in r0 to a long in r0/r1. 12026 * 12027 * We have to clip values to long min/max per the specification. The 12028 * expected common case is a "reasonable" value that converts directly 12029 * to modest integer. The EABI convert function isn't doing this for us. 12030 */ 12031f2l_doconv: 12032 stmfd sp!, {r4, lr} 12033 mov r1, #0x5f000000 @ (float)maxlong 12034 mov r4, r0 12035 bl __aeabi_fcmpge @ is arg >= maxlong? 12036 cmp r0, #0 @ nonzero == yes 12037 mvnne r0, #0 @ return maxlong (7fffffff) 12038 mvnne r1, #0x80000000 12039 ldmnefd sp!, {r4, pc} 12040 12041 mov r0, r4 @ recover arg 12042 mov r1, #0xdf000000 @ (float)minlong 12043 bl __aeabi_fcmple @ is arg <= minlong? 12044 cmp r0, #0 @ nonzero == yes 12045 movne r0, #0 @ return minlong (80000000) 12046 movne r1, #0x80000000 12047 ldmnefd sp!, {r4, pc} 12048 12049 mov r0, r4 @ recover arg 12050 mov r1, r4 12051 bl __aeabi_fcmpeq @ is arg == self? 12052 cmp r0, #0 @ zero == no 12053 moveq r1, #0 @ return zero for NaN 12054 ldmeqfd sp!, {r4, pc} 12055 12056 mov r0, r4 @ recover arg 12057 bl __aeabi_f2lz @ convert float to long 12058 ldmfd sp!, {r4, pc} 12059 12060/* continuation for OP_DOUBLE_TO_LONG */ 12061/* 12062 * Convert the double in r0/r1 to a long in r0/r1. 12063 * 12064 * We have to clip values to long min/max per the specification. The 12065 * expected common case is a "reasonable" value that converts directly 12066 * to modest integer. The EABI convert function isn't doing this for us. 12067 */ 12068d2l_doconv: 12069 stmfd sp!, {r4, r5, lr} @ save regs 12070 mov r3, #0x43000000 @ maxlong, as a double (high word) 12071 add r3, #0x00e00000 @ 0x43e00000 12072 mov r2, #0 @ maxlong, as a double (low word) 12073 sub sp, sp, #4 @ align for EABI 12074 mov r4, r0 @ save a copy of r0 12075 mov r5, r1 @ and r1 12076 bl __aeabi_dcmpge @ is arg >= maxlong? 12077 cmp r0, #0 @ nonzero == yes 12078 mvnne r0, #0 @ return maxlong (7fffffffffffffff) 12079 mvnne r1, #0x80000000 12080 bne 1f 12081 12082 mov r0, r4 @ recover arg 12083 mov r1, r5 12084 mov r3, #0xc3000000 @ minlong, as a double (high word) 12085 add r3, #0x00e00000 @ 0xc3e00000 12086 mov r2, #0 @ minlong, as a double (low word) 12087 bl __aeabi_dcmple @ is arg <= minlong? 12088 cmp r0, #0 @ nonzero == yes 12089 movne r0, #0 @ return minlong (8000000000000000) 12090 movne r1, #0x80000000 12091 bne 1f 12092 12093 mov r0, r4 @ recover arg 12094 mov r1, r5 12095 mov r2, r4 @ compare against self 12096 mov r3, r5 12097 bl __aeabi_dcmpeq @ is arg == self? 12098 cmp r0, #0 @ zero == no 12099 moveq r1, #0 @ return zero for NaN 12100 beq 1f 12101 12102 mov r0, r4 @ recover arg 12103 mov r1, r5 12104 bl __aeabi_d2lz @ convert double to long 12105 121061: 12107 add sp, sp, #4 12108 ldmfd sp!, {r4, r5, pc} 12109 12110/* continuation for OP_MUL_LONG */ 12111 12112.LOP_MUL_LONG_finish: 12113 GET_INST_OPCODE(ip) @ extract opcode from rINST 12114 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 12115 GOTO_OPCODE(ip) @ jump to next instruction 12116 12117/* continuation for OP_SHL_LONG */ 12118 12119.LOP_SHL_LONG_finish: 12120 mov r0, r0, asl r2 @ r0<- r0 << r2 12121 GET_INST_OPCODE(ip) @ extract opcode from rINST 12122 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12123 GOTO_OPCODE(ip) @ jump to next instruction 12124 12125/* continuation for OP_SHR_LONG */ 12126 12127.LOP_SHR_LONG_finish: 12128 mov r1, r1, asr r2 @ r1<- r1 >> r2 12129 GET_INST_OPCODE(ip) @ extract opcode from rINST 12130 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12131 GOTO_OPCODE(ip) @ jump to next instruction 12132 12133/* continuation for OP_USHR_LONG */ 12134 12135.LOP_USHR_LONG_finish: 12136 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 12137 GET_INST_OPCODE(ip) @ extract opcode from rINST 12138 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12139 GOTO_OPCODE(ip) @ jump to next instruction 12140 12141/* continuation for OP_SHL_LONG_2ADDR */ 12142 12143.LOP_SHL_LONG_2ADDR_finish: 12144 GET_INST_OPCODE(ip) @ extract opcode from rINST 12145 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12146 GOTO_OPCODE(ip) @ jump to next instruction 12147 12148/* continuation for OP_SHR_LONG_2ADDR */ 12149 12150.LOP_SHR_LONG_2ADDR_finish: 12151 GET_INST_OPCODE(ip) @ extract opcode from rINST 12152 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12153 GOTO_OPCODE(ip) @ jump to next instruction 12154 12155/* continuation for OP_USHR_LONG_2ADDR */ 12156 12157.LOP_USHR_LONG_2ADDR_finish: 12158 GET_INST_OPCODE(ip) @ extract opcode from rINST 12159 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12160 GOTO_OPCODE(ip) @ jump to next instruction 12161 12162/* continuation for OP_IGET_VOLATILE */ 12163 12164 /* 12165 * Currently: 12166 * r0 holds resolved field 12167 * r9 holds object 12168 */ 12169.LOP_IGET_VOLATILE_finish: 12170 @bl common_squeak0 12171 cmp r9, #0 @ check object for null 12172 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12173 beq common_errNullObject @ object was null 12174 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12175 SMP_DMB @ acquiring load 12176 mov r2, rINST, lsr #8 @ r2<- A+ 12177 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12178 and r2, r2, #15 @ r2<- A 12179 GET_INST_OPCODE(ip) @ extract opcode from rINST 12180 SET_VREG(r0, r2) @ fp[A]<- r0 12181 GOTO_OPCODE(ip) @ jump to next instruction 12182 12183/* continuation for OP_IPUT_VOLATILE */ 12184 12185 /* 12186 * Currently: 12187 * r0 holds resolved field 12188 * r9 holds object 12189 */ 12190.LOP_IPUT_VOLATILE_finish: 12191 @bl common_squeak0 12192 mov r1, rINST, lsr #8 @ r1<- A+ 12193 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12194 and r1, r1, #15 @ r1<- A 12195 cmp r9, #0 @ check object for null 12196 GET_VREG(r0, r1) @ r0<- fp[A] 12197 beq common_errNullObject @ object was null 12198 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12199 GET_INST_OPCODE(ip) @ extract opcode from rINST 12200 SMP_DMB @ releasing store 12201 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12202 GOTO_OPCODE(ip) @ jump to next instruction 12203 12204/* continuation for OP_SGET_VOLATILE */ 12205 12206 /* 12207 * Continuation if the field has not yet been resolved. 12208 * r1: BBBB field ref 12209 */ 12210.LOP_SGET_VOLATILE_resolve: 12211 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12212 EXPORT_PC() @ resolve() could throw, so export now 12213 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12214 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12215 cmp r0, #0 @ success? 12216 bne .LOP_SGET_VOLATILE_finish @ yes, finish 12217 b common_exceptionThrown @ no, handle exception 12218 12219/* continuation for OP_SPUT_VOLATILE */ 12220 12221 /* 12222 * Continuation if the field has not yet been resolved. 12223 * r1: BBBB field ref 12224 */ 12225.LOP_SPUT_VOLATILE_resolve: 12226 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12227 EXPORT_PC() @ resolve() could throw, so export now 12228 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12229 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12230 cmp r0, #0 @ success? 12231 bne .LOP_SPUT_VOLATILE_finish @ yes, finish 12232 b common_exceptionThrown @ no, handle exception 12233 12234/* continuation for OP_IGET_OBJECT_VOLATILE */ 12235 12236 /* 12237 * Currently: 12238 * r0 holds resolved field 12239 * r9 holds object 12240 */ 12241.LOP_IGET_OBJECT_VOLATILE_finish: 12242 @bl common_squeak0 12243 cmp r9, #0 @ check object for null 12244 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12245 beq common_errNullObject @ object was null 12246 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12247 SMP_DMB @ acquiring load 12248 mov r2, rINST, lsr #8 @ r2<- A+ 12249 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12250 and r2, r2, #15 @ r2<- A 12251 GET_INST_OPCODE(ip) @ extract opcode from rINST 12252 SET_VREG(r0, r2) @ fp[A]<- r0 12253 GOTO_OPCODE(ip) @ jump to next instruction 12254 12255/* continuation for OP_IGET_WIDE_VOLATILE */ 12256 12257 /* 12258 * Currently: 12259 * r0 holds resolved field 12260 * r9 holds object 12261 */ 12262.LOP_IGET_WIDE_VOLATILE_finish: 12263 cmp r9, #0 @ check object for null 12264 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12265 beq common_errNullObject @ object was null 12266 .if 1 12267 add r0, r9, r3 @ r0<- address of field 12268 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 12269 .else 12270 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12271 .endif 12272 mov r2, rINST, lsr #8 @ r2<- A+ 12273 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12274 and r2, r2, #15 @ r2<- A 12275 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 12276 GET_INST_OPCODE(ip) @ extract opcode from rINST 12277 stmia r3, {r0-r1} @ fp[A]<- r0/r1 12278 GOTO_OPCODE(ip) @ jump to next instruction 12279 12280/* continuation for OP_IPUT_WIDE_VOLATILE */ 12281 12282 /* 12283 * Currently: 12284 * r0 holds resolved field 12285 * r9 holds object 12286 */ 12287.LOP_IPUT_WIDE_VOLATILE_finish: 12288 mov r2, rINST, lsr #8 @ r2<- A+ 12289 cmp r9, #0 @ check object for null 12290 and r2, r2, #15 @ r2<- A 12291 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12292 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 12293 beq common_errNullObject @ object was null 12294 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12295 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 12296 GET_INST_OPCODE(r10) @ extract opcode from rINST 12297 .if 1 12298 add r2, r9, r3 @ r2<- target address 12299 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 12300 .else 12301 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12302 .endif 12303 GOTO_OPCODE(r10) @ jump to next instruction 12304 12305/* continuation for OP_SGET_WIDE_VOLATILE */ 12306 12307 /* 12308 * Continuation if the field has not yet been resolved. 12309 * r1: BBBB field ref 12310 * 12311 * Returns StaticField pointer in r0. 12312 */ 12313.LOP_SGET_WIDE_VOLATILE_resolve: 12314 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12315 EXPORT_PC() @ resolve() could throw, so export now 12316 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12317 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12318 cmp r0, #0 @ success? 12319 bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 12320 b common_exceptionThrown @ no, handle exception 12321 12322/* continuation for OP_SPUT_WIDE_VOLATILE */ 12323 12324 /* 12325 * Continuation if the field has not yet been resolved. 12326 * r1: BBBB field ref 12327 * r9: &fp[AA] 12328 * 12329 * Returns StaticField pointer in r2. 12330 */ 12331.LOP_SPUT_WIDE_VOLATILE_resolve: 12332 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12333 EXPORT_PC() @ resolve() could throw, so export now 12334 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12335 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12336 cmp r0, #0 @ success? 12337 mov r2, r0 @ copy to r2 12338 bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 12339 b common_exceptionThrown @ no, handle exception 12340 12341/* continuation for OP_EXECUTE_INLINE */ 12342 12343 /* 12344 * Extract args, call function. 12345 * r0 = #of args (0-4) 12346 * r10 = call index 12347 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12348 * 12349 * Other ideas: 12350 * - Use a jump table from the main piece to jump directly into the 12351 * AND/LDR pairs. Costs a data load, saves a branch. 12352 * - Have five separate pieces that do the loading, so we can work the 12353 * interleave a little better. Increases code size. 12354 */ 12355.LOP_EXECUTE_INLINE_continue: 12356 rsb r0, r0, #4 @ r0<- 4-r0 12357 FETCH(r9, 2) @ r9<- FEDC 12358 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12359 bl common_abort @ (skipped due to ARM prefetch) 123604: and ip, r9, #0xf000 @ isolate F 12361 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 123623: and ip, r9, #0x0f00 @ isolate E 12363 ldr r2, [rFP, ip, lsr #6] @ r2<- vE 123642: and ip, r9, #0x00f0 @ isolate D 12365 ldr r1, [rFP, ip, lsr #2] @ r1<- vD 123661: and ip, r9, #0x000f @ isolate C 12367 ldr r0, [rFP, ip, lsl #2] @ r0<- vC 123680: 12369 ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 12370 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12371 @ (not reached) 12372 12373.LOP_EXECUTE_INLINE_table: 12374 .word gDvmInlineOpsTable 12375 12376/* continuation for OP_EXECUTE_INLINE_RANGE */ 12377 12378 /* 12379 * Extract args, call function. 12380 * r0 = #of args (0-4) 12381 * r10 = call index 12382 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12383 */ 12384.LOP_EXECUTE_INLINE_RANGE_continue: 12385 rsb r0, r0, #4 @ r0<- 4-r0 12386 FETCH(r9, 2) @ r9<- CCCC 12387 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12388 bl common_abort @ (skipped due to ARM prefetch) 123894: add ip, r9, #3 @ base+3 12390 GET_VREG(r3, ip) @ r3<- vBase[3] 123913: add ip, r9, #2 @ base+2 12392 GET_VREG(r2, ip) @ r2<- vBase[2] 123932: add ip, r9, #1 @ base+1 12394 GET_VREG(r1, ip) @ r1<- vBase[1] 123951: add ip, r9, #0 @ (nop) 12396 GET_VREG(r0, ip) @ r0<- vBase[0] 123970: 12398 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 12399 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12400 @ (not reached) 12401 12402.LOP_EXECUTE_INLINE_RANGE_table: 12403 .word gDvmInlineOpsTable 12404 12405/* continuation for OP_IPUT_OBJECT_VOLATILE */ 12406 12407 /* 12408 * Currently: 12409 * r0 holds resolved field 12410 * r9 holds object 12411 */ 12412.LOP_IPUT_OBJECT_VOLATILE_finish: 12413 @bl common_squeak0 12414 mov r1, rINST, lsr #8 @ r1<- A+ 12415 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12416 and r1, r1, #15 @ r1<- A 12417 cmp r9, #0 @ check object for null 12418 GET_VREG(r0, r1) @ r0<- fp[A] 12419 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12420 beq common_errNullObject @ object was null 12421 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12422 GET_INST_OPCODE(ip) @ extract opcode from rINST 12423 SMP_DMB @ releasing store 12424 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12425 cmp r0, #0 @ stored a null reference? 12426 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12427 GOTO_OPCODE(ip) @ jump to next instruction 12428 12429/* continuation for OP_SGET_OBJECT_VOLATILE */ 12430 12431 /* 12432 * Continuation if the field has not yet been resolved. 12433 * r1: BBBB field ref 12434 */ 12435.LOP_SGET_OBJECT_VOLATILE_resolve: 12436 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12437 EXPORT_PC() @ resolve() could throw, so export now 12438 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12439 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12440 cmp r0, #0 @ success? 12441 bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish 12442 b common_exceptionThrown @ no, handle exception 12443 12444/* continuation for OP_SPUT_OBJECT_VOLATILE */ 12445.LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 12446 mov r2, rINST, lsr #8 @ r2<- AA 12447 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12448 GET_VREG(r1, r2) @ r1<- fp[AA] 12449 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12450 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 12451 GET_INST_OPCODE(ip) @ extract opcode from rINST 12452 SMP_DMB @ releasing store 12453 str r1, [r0, #offStaticField_value] @ field<- vAA 12454 cmp r1, #0 @ stored a null object? 12455 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12456 GOTO_OPCODE(ip) @ jump to next instruction 12457 12458/* continuation for OP_CONST_CLASS_JUMBO */ 12459 12460 /* 12461 * Continuation if the Class has not yet been resolved. 12462 * r1: AAAAAAAA (Class ref) 12463 * r9: target register 12464 */ 12465.LOP_CONST_CLASS_JUMBO_resolve: 12466 EXPORT_PC() 12467 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12468 mov r2, #1 @ r2<- true 12469 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12470 bl dvmResolveClass @ r0<- Class reference 12471 cmp r0, #0 @ failed? 12472 beq common_exceptionThrown @ yup, handle the exception 12473 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12474 GET_INST_OPCODE(ip) @ extract opcode from rINST 12475 SET_VREG(r0, r9) @ vBBBB<- r0 12476 GOTO_OPCODE(ip) @ jump to next instruction 12477 12478/* continuation for OP_CHECK_CAST_JUMBO */ 12479 12480 /* 12481 * Trivial test failed, need to perform full check. This is common. 12482 * r0 holds obj->clazz 12483 * r1 holds desired class resolved from AAAAAAAA 12484 * r9 holds object 12485 */ 12486.LOP_CHECK_CAST_JUMBO_fullcheck: 12487 mov r10, r1 @ avoid ClassObject getting clobbered 12488 bl dvmInstanceofNonTrivial @ r0<- boolean result 12489 cmp r0, #0 @ failed? 12490 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success 12491 12492 @ A cast has failed. We need to throw a ClassCastException. 12493 EXPORT_PC() @ about to throw 12494 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 12495 mov r1, r10 @ r1<- desired class 12496 bl dvmThrowClassCastException 12497 b common_exceptionThrown 12498 12499 /* 12500 * Advance PC and get the next opcode. 12501 */ 12502.LOP_CHECK_CAST_JUMBO_okay: 12503 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12504 GET_INST_OPCODE(ip) @ extract opcode from rINST 12505 GOTO_OPCODE(ip) @ jump to next instruction 12506 12507 /* 12508 * Resolution required. This is the least-likely path. 12509 * 12510 * r2 holds AAAAAAAA 12511 * r9 holds object 12512 */ 12513.LOP_CHECK_CAST_JUMBO_resolve: 12514 EXPORT_PC() @ resolve() could throw 12515 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12516 mov r1, r2 @ r1<- AAAAAAAA 12517 mov r2, #0 @ r2<- false 12518 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12519 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12520 cmp r0, #0 @ got null? 12521 beq common_exceptionThrown @ yes, handle exception 12522 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12523 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 12524 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off 12525 12526/* continuation for OP_INSTANCE_OF_JUMBO */ 12527 12528 /* 12529 * Class resolved, determine type of check necessary. This is common. 12530 * r0 holds obj->clazz 12531 * r1 holds class resolved from AAAAAAAA 12532 * r9 holds BBBB 12533 */ 12534.LOP_INSTANCE_OF_JUMBO_resolved: 12535 cmp r0, r1 @ same class (trivial success)? 12536 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish 12537 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck 12538 12539 /* 12540 * Trivial test failed, need to perform full check. This is common. 12541 * r0 holds obj->clazz 12542 * r1 holds class resolved from AAAAAAAA 12543 * r9 holds BBBB 12544 */ 12545.LOP_INSTANCE_OF_JUMBO_fullcheck: 12546 bl dvmInstanceofNonTrivial @ r0<- boolean result 12547 @ fall through to OP_INSTANCE_OF_JUMBO_store 12548 12549 /* 12550 * r0 holds boolean result 12551 * r9 holds BBBB 12552 */ 12553.LOP_INSTANCE_OF_JUMBO_store: 12554 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12555 SET_VREG(r0, r9) @ vBBBB<- r0 12556 GET_INST_OPCODE(ip) @ extract opcode from rINST 12557 GOTO_OPCODE(ip) @ jump to next instruction 12558 12559 /* 12560 * Trivial test succeeded, save and bail. 12561 * r9 holds BBBB 12562 */ 12563.LOP_INSTANCE_OF_JUMBO_trivial: 12564 mov r0, #1 @ indicate success 12565 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper 12566 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12567 SET_VREG(r0, r9) @ vBBBB<- r0 12568 GET_INST_OPCODE(ip) @ extract opcode from rINST 12569 GOTO_OPCODE(ip) @ jump to next instruction 12570 12571 /* 12572 * Resolution required. This is the least-likely path. 12573 * 12574 * r3 holds AAAAAAAA 12575 * r9 holds BBBB 12576 */ 12577 12578.LOP_INSTANCE_OF_JUMBO_resolve: 12579 EXPORT_PC() @ resolve() could throw 12580 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12581 mov r1, r3 @ r1<- AAAAAAAA 12582 mov r2, #1 @ r2<- true 12583 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12584 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12585 cmp r0, #0 @ got null? 12586 beq common_exceptionThrown @ yes, handle exception 12587 FETCH(r3, 4) @ r3<- vCCCC 12588 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12589 GET_VREG(r0, r3) @ r0<- vCCCC (object) 12590 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 12591 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off 12592 12593/* continuation for OP_NEW_INSTANCE_JUMBO */ 12594 12595 .balign 32 @ minimize cache lines 12596.LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object 12597 FETCH(r3, 3) @ r3<- BBBB 12598 cmp r0, #0 @ failed? 12599 beq common_exceptionThrown @ yes, handle the exception 12600 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12601 GET_INST_OPCODE(ip) @ extract opcode from rINST 12602 SET_VREG(r0, r3) @ vBBBB<- r0 12603 GOTO_OPCODE(ip) @ jump to next instruction 12604 12605 /* 12606 * Class initialization required. 12607 * 12608 * r0 holds class object 12609 */ 12610.LOP_NEW_INSTANCE_JUMBO_needinit: 12611 mov r9, r0 @ save r0 12612 bl dvmInitClass @ initialize class 12613 cmp r0, #0 @ check boolean result 12614 mov r0, r9 @ restore r0 12615 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue 12616 b common_exceptionThrown @ failed, deal with init exception 12617 12618 /* 12619 * Resolution required. This is the least-likely path. 12620 * 12621 * r1 holds AAAAAAAA 12622 */ 12623.LOP_NEW_INSTANCE_JUMBO_resolve: 12624 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12625 mov r2, #0 @ r2<- false 12626 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12627 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12628 cmp r0, #0 @ got null? 12629 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue 12630 b common_exceptionThrown @ yes, handle exception 12631 12632/* continuation for OP_NEW_ARRAY_JUMBO */ 12633 12634 12635 /* 12636 * Resolve class. (This is an uncommon case.) 12637 * 12638 * r1 holds array length 12639 * r2 holds class ref AAAAAAAA 12640 */ 12641.LOP_NEW_ARRAY_JUMBO_resolve: 12642 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12643 mov r9, r1 @ r9<- length (save) 12644 mov r1, r2 @ r1<- AAAAAAAA 12645 mov r2, #0 @ r2<- false 12646 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12647 bl dvmResolveClass @ r0<- call(clazz, ref) 12648 cmp r0, #0 @ got null? 12649 mov r1, r9 @ r1<- length (restore) 12650 beq common_exceptionThrown @ yes, handle exception 12651 @ fall through to OP_NEW_ARRAY_JUMBO_finish 12652 12653 /* 12654 * Finish allocation. 12655 * 12656 * r0 holds class 12657 * r1 holds array length 12658 */ 12659.LOP_NEW_ARRAY_JUMBO_finish: 12660 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 12661 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 12662 cmp r0, #0 @ failed? 12663 FETCH(r2, 3) @ r2<- vBBBB 12664 beq common_exceptionThrown @ yes, handle the exception 12665 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12666 GET_INST_OPCODE(ip) @ extract opcode from rINST 12667 SET_VREG(r0, r2) @ vBBBB<- r0 12668 GOTO_OPCODE(ip) @ jump to next instruction 12669 12670/* continuation for OP_FILLED_NEW_ARRAY_JUMBO */ 12671 12672 /* 12673 * On entry: 12674 * r0 holds array class 12675 */ 12676.LOP_FILLED_NEW_ARRAY_JUMBO_continue: 12677 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 12678 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 12679 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 12680 FETCH(r1, 3) @ r1<- BBBB (length) 12681 cmp rINST, #'I' @ array of ints? 12682 cmpne rINST, #'L' @ array of objects? 12683 cmpne rINST, #'[' @ array of arrays? 12684 mov r9, r1 @ save length in r9 12685 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet 12686 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 12687 cmp r0, #0 @ null return? 12688 beq common_exceptionThrown @ alloc failed, handle exception 12689 12690 FETCH(r1, 4) @ r1<- CCCC 12691 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 12692 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 12693 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 12694 subs r9, r9, #1 @ length--, check for neg 12695 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST 12696 bmi 2f @ was zero, bail 12697 12698 @ copy values from registers into the array 12699 @ r0=array, r1=CCCC, r9=BBBB (length) 12700 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 127011: ldr r3, [r2], #4 @ r3<- *r2++ 12702 subs r9, r9, #1 @ count-- 12703 str r3, [r0], #4 @ *contents++ = vX 12704 bpl 1b 12705 127062: ldr r0, [rSELF, #offThread_retval] @ r0<- object 12707 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 12708 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12709 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 12710 cmp r1, #'I' @ Is int array? 12711 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 12712 GOTO_OPCODE(ip) @ execute it 12713 12714 /* 12715 * Throw an exception indicating that we have not implemented this 12716 * mode of filled-new-array. 12717 */ 12718.LOP_FILLED_NEW_ARRAY_JUMBO_notimpl: 12719 ldr r0, .L_strFilledNewArrayNotImpl 12720 bl dvmThrowInternalError 12721 b common_exceptionThrown 12722 12723/* continuation for OP_IGET_JUMBO */ 12724 12725 /* 12726 * Currently: 12727 * r0 holds resolved field 12728 * r9 holds object 12729 */ 12730.LOP_IGET_JUMBO_resolved: 12731 cmp r0, #0 @ resolution unsuccessful? 12732 beq common_exceptionThrown @ yes, throw exception 12733 @ fall through to OP_IGET_JUMBO_finish 12734 12735 /* 12736 * Currently: 12737 * r0 holds resolved field 12738 * r9 holds object 12739 */ 12740.LOP_IGET_JUMBO_finish: 12741 @bl common_squeak0 12742 cmp r9, #0 @ check object for null 12743 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12744 beq common_errNullObject @ object was null 12745 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12746 @ no-op @ acquiring load 12747 FETCH(r2, 3) @ r2<- BBBB 12748 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12749 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12750 GET_INST_OPCODE(ip) @ extract opcode from rINST 12751 GOTO_OPCODE(ip) @ jump to next instruction 12752 12753/* continuation for OP_IGET_WIDE_JUMBO */ 12754 12755 /* 12756 * Currently: 12757 * r0 holds resolved field 12758 * r9 holds object 12759 */ 12760.LOP_IGET_WIDE_JUMBO_resolved: 12761 cmp r0, #0 @ resolution unsuccessful? 12762 beq common_exceptionThrown @ yes, throw exception 12763 @ fall through to OP_IGET_WIDE_JUMBO_finish 12764 12765 /* 12766 * Currently: 12767 * r0 holds resolved field 12768 * r9 holds object 12769 */ 12770.LOP_IGET_WIDE_JUMBO_finish: 12771 cmp r9, #0 @ check object for null 12772 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12773 beq common_errNullObject @ object was null 12774 .if 0 12775 add r0, r9, r3 @ r0<- address of field 12776 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 12777 .else 12778 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12779 .endif 12780 FETCH(r2, 3) @ r2<- BBBB 12781 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12782 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12783 GET_INST_OPCODE(ip) @ extract opcode from rINST 12784 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 12785 GOTO_OPCODE(ip) @ jump to next instruction 12786 12787/* continuation for OP_IGET_OBJECT_JUMBO */ 12788 12789 /* 12790 * Currently: 12791 * r0 holds resolved field 12792 * r9 holds object 12793 */ 12794.LOP_IGET_OBJECT_JUMBO_resolved: 12795 cmp r0, #0 @ resolution unsuccessful? 12796 beq common_exceptionThrown @ yes, throw exception 12797 @ fall through to OP_IGET_OBJECT_JUMBO_finish 12798 12799 /* 12800 * Currently: 12801 * r0 holds resolved field 12802 * r9 holds object 12803 */ 12804.LOP_IGET_OBJECT_JUMBO_finish: 12805 @bl common_squeak0 12806 cmp r9, #0 @ check object for null 12807 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12808 beq common_errNullObject @ object was null 12809 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12810 @ no-op @ acquiring load 12811 FETCH(r2, 3) @ r2<- BBBB 12812 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12813 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12814 GET_INST_OPCODE(ip) @ extract opcode from rINST 12815 GOTO_OPCODE(ip) @ jump to next instruction 12816 12817/* continuation for OP_IGET_BOOLEAN_JUMBO */ 12818 12819 /* 12820 * Currently: 12821 * r0 holds resolved field 12822 * r9 holds object 12823 */ 12824.LOP_IGET_BOOLEAN_JUMBO_resolved: 12825 cmp r0, #0 @ resolution unsuccessful? 12826 beq common_exceptionThrown @ yes, throw exception 12827 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish 12828 12829 /* 12830 * Currently: 12831 * r0 holds resolved field 12832 * r9 holds object 12833 */ 12834.LOP_IGET_BOOLEAN_JUMBO_finish: 12835 @bl common_squeak1 12836 cmp r9, #0 @ check object for null 12837 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12838 beq common_errNullObject @ object was null 12839 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12840 @ no-op @ acquiring load 12841 FETCH(r2, 3) @ r2<- BBBB 12842 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12843 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12844 GET_INST_OPCODE(ip) @ extract opcode from rINST 12845 GOTO_OPCODE(ip) @ jump to next instruction 12846 12847/* continuation for OP_IGET_BYTE_JUMBO */ 12848 12849 /* 12850 * Currently: 12851 * r0 holds resolved field 12852 * r9 holds object 12853 */ 12854.LOP_IGET_BYTE_JUMBO_resolved: 12855 cmp r0, #0 @ resolution unsuccessful? 12856 beq common_exceptionThrown @ yes, throw exception 12857 @ fall through to OP_IGET_BYTE_JUMBO_finish 12858 12859 /* 12860 * Currently: 12861 * r0 holds resolved field 12862 * r9 holds object 12863 */ 12864.LOP_IGET_BYTE_JUMBO_finish: 12865 @bl common_squeak2 12866 cmp r9, #0 @ check object for null 12867 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12868 beq common_errNullObject @ object was null 12869 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12870 @ no-op @ acquiring load 12871 FETCH(r2, 3) @ r2<- BBBB 12872 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12873 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12874 GET_INST_OPCODE(ip) @ extract opcode from rINST 12875 GOTO_OPCODE(ip) @ jump to next instruction 12876 12877/* continuation for OP_IGET_CHAR_JUMBO */ 12878 12879 /* 12880 * Currently: 12881 * r0 holds resolved field 12882 * r9 holds object 12883 */ 12884.LOP_IGET_CHAR_JUMBO_resolved: 12885 cmp r0, #0 @ resolution unsuccessful? 12886 beq common_exceptionThrown @ yes, throw exception 12887 @ fall through to OP_IGET_CHAR_JUMBO_finish 12888 12889 /* 12890 * Currently: 12891 * r0 holds resolved field 12892 * r9 holds object 12893 */ 12894.LOP_IGET_CHAR_JUMBO_finish: 12895 @bl common_squeak3 12896 cmp r9, #0 @ check object for null 12897 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12898 beq common_errNullObject @ object was null 12899 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12900 @ no-op @ acquiring load 12901 FETCH(r2, 3) @ r2<- BBBB 12902 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12903 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12904 GET_INST_OPCODE(ip) @ extract opcode from rINST 12905 GOTO_OPCODE(ip) @ jump to next instruction 12906 12907/* continuation for OP_IGET_SHORT_JUMBO */ 12908 12909 /* 12910 * Currently: 12911 * r0 holds resolved field 12912 * r9 holds object 12913 */ 12914.LOP_IGET_SHORT_JUMBO_resolved: 12915 cmp r0, #0 @ resolution unsuccessful? 12916 beq common_exceptionThrown @ yes, throw exception 12917 @ fall through to OP_IGET_SHORT_JUMBO_finish 12918 12919 /* 12920 * Currently: 12921 * r0 holds resolved field 12922 * r9 holds object 12923 */ 12924.LOP_IGET_SHORT_JUMBO_finish: 12925 @bl common_squeak4 12926 cmp r9, #0 @ check object for null 12927 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12928 beq common_errNullObject @ object was null 12929 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12930 @ no-op @ acquiring load 12931 FETCH(r2, 3) @ r2<- BBBB 12932 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12933 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12934 GET_INST_OPCODE(ip) @ extract opcode from rINST 12935 GOTO_OPCODE(ip) @ jump to next instruction 12936 12937/* continuation for OP_IPUT_JUMBO */ 12938 12939 /* 12940 * Currently: 12941 * r0 holds resolved field 12942 * r9 holds object 12943 */ 12944.LOP_IPUT_JUMBO_resolved: 12945 cmp r0, #0 @ resolution unsuccessful? 12946 beq common_exceptionThrown @ yes, throw exception 12947 @ fall through to OP_IPUT_JUMBO_finish 12948 12949 /* 12950 * Currently: 12951 * r0 holds resolved field 12952 * r9 holds object 12953 */ 12954.LOP_IPUT_JUMBO_finish: 12955 @bl common_squeak0 12956 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12957 FETCH(r1, 3) @ r1<- BBBB 12958 cmp r9, #0 @ check object for null 12959 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12960 beq common_errNullObject @ object was null 12961 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12962 GET_INST_OPCODE(ip) @ extract opcode from rINST 12963 @ no-op @ releasing store 12964 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12965 GOTO_OPCODE(ip) @ jump to next instruction 12966 12967/* continuation for OP_IPUT_WIDE_JUMBO */ 12968 12969 /* 12970 * Currently: 12971 * r0 holds resolved field 12972 * r9 holds object 12973 */ 12974.LOP_IPUT_WIDE_JUMBO_resolved: 12975 cmp r0, #0 @ resolution unsuccessful? 12976 beq common_exceptionThrown @ yes, throw exception 12977 @ fall through to OP_IPUT_WIDE_JUMBO_finish 12978 12979 /* 12980 * Currently: 12981 * r0 holds resolved field 12982 * r9 holds object 12983 */ 12984.LOP_IPUT_WIDE_JUMBO_finish: 12985 cmp r9, #0 @ check object for null 12986 FETCH(r2, 3) @ r1<- BBBB 12987 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12988 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12989 beq common_errNullObject @ object was null 12990 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12991 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 12992 GET_INST_OPCODE(r10) @ extract opcode from rINST 12993 .if 0 12994 add r2, r9, r3 @ r2<- target address 12995 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 12996 .else 12997 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12998 .endif 12999 GOTO_OPCODE(r10) @ jump to next instruction 13000 13001/* continuation for OP_IPUT_OBJECT_JUMBO */ 13002 13003 /* 13004 * Currently: 13005 * r0 holds resolved field 13006 * r9 holds object 13007 */ 13008.LOP_IPUT_OBJECT_JUMBO_resolved: 13009 cmp r0, #0 @ resolution unsuccessful? 13010 beq common_exceptionThrown @ yes, throw exception 13011 @ fall through to OP_IPUT_OBJECT_JUMBO_finish 13012 13013 /* 13014 * Currently: 13015 * r0 holds resolved field 13016 * r9 holds object 13017 */ 13018.LOP_IPUT_OBJECT_JUMBO_finish: 13019 @bl common_squeak0 13020 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13021 FETCH(r1, 3) @ r1<- BBBB 13022 cmp r9, #0 @ check object for null 13023 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13024 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13025 beq common_errNullObject @ object was null 13026 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13027 GET_INST_OPCODE(ip) @ extract opcode from rINST 13028 @ no-op @ releasing store 13029 str r0, [r9, r3] @ obj.field (32 bits)<- r0 13030 cmp r0, #0 @ stored a null reference? 13031 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 13032 GOTO_OPCODE(ip) @ jump to next instruction 13033 13034/* continuation for OP_IPUT_BOOLEAN_JUMBO */ 13035 13036 /* 13037 * Currently: 13038 * r0 holds resolved field 13039 * r9 holds object 13040 */ 13041.LOP_IPUT_BOOLEAN_JUMBO_resolved: 13042 cmp r0, #0 @ resolution unsuccessful? 13043 beq common_exceptionThrown @ yes, throw exception 13044 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish 13045 13046 /* 13047 * Currently: 13048 * r0 holds resolved field 13049 * r9 holds object 13050 */ 13051.LOP_IPUT_BOOLEAN_JUMBO_finish: 13052 @bl common_squeak1 13053 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13054 FETCH(r1, 3) @ r1<- BBBB 13055 cmp r9, #0 @ check object for null 13056 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13057 beq common_errNullObject @ object was null 13058 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13059 GET_INST_OPCODE(ip) @ extract opcode from rINST 13060 @ no-op @ releasing store 13061 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13062 GOTO_OPCODE(ip) @ jump to next instruction 13063 13064/* continuation for OP_IPUT_BYTE_JUMBO */ 13065 13066 /* 13067 * Currently: 13068 * r0 holds resolved field 13069 * r9 holds object 13070 */ 13071.LOP_IPUT_BYTE_JUMBO_resolved: 13072 cmp r0, #0 @ resolution unsuccessful? 13073 beq common_exceptionThrown @ yes, throw exception 13074 @ fall through to OP_IPUT_BYTE_JUMBO_finish 13075 13076 /* 13077 * Currently: 13078 * r0 holds resolved field 13079 * r9 holds object 13080 */ 13081.LOP_IPUT_BYTE_JUMBO_finish: 13082 @bl common_squeak2 13083 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13084 FETCH(r1, 3) @ r1<- BBBB 13085 cmp r9, #0 @ check object for null 13086 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13087 beq common_errNullObject @ object was null 13088 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13089 GET_INST_OPCODE(ip) @ extract opcode from rINST 13090 @ no-op @ releasing store 13091 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13092 GOTO_OPCODE(ip) @ jump to next instruction 13093 13094/* continuation for OP_IPUT_CHAR_JUMBO */ 13095 13096 /* 13097 * Currently: 13098 * r0 holds resolved field 13099 * r9 holds object 13100 */ 13101.LOP_IPUT_CHAR_JUMBO_resolved: 13102 cmp r0, #0 @ resolution unsuccessful? 13103 beq common_exceptionThrown @ yes, throw exception 13104 @ fall through to OP_IPUT_CHAR_JUMBO_finish 13105 13106 /* 13107 * Currently: 13108 * r0 holds resolved field 13109 * r9 holds object 13110 */ 13111.LOP_IPUT_CHAR_JUMBO_finish: 13112 @bl common_squeak3 13113 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13114 FETCH(r1, 3) @ r1<- BBBB 13115 cmp r9, #0 @ check object for null 13116 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13117 beq common_errNullObject @ object was null 13118 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13119 GET_INST_OPCODE(ip) @ extract opcode from rINST 13120 @ no-op @ releasing store 13121 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13122 GOTO_OPCODE(ip) @ jump to next instruction 13123 13124/* continuation for OP_IPUT_SHORT_JUMBO */ 13125 13126 /* 13127 * Currently: 13128 * r0 holds resolved field 13129 * r9 holds object 13130 */ 13131.LOP_IPUT_SHORT_JUMBO_resolved: 13132 cmp r0, #0 @ resolution unsuccessful? 13133 beq common_exceptionThrown @ yes, throw exception 13134 @ fall through to OP_IPUT_SHORT_JUMBO_finish 13135 13136 /* 13137 * Currently: 13138 * r0 holds resolved field 13139 * r9 holds object 13140 */ 13141.LOP_IPUT_SHORT_JUMBO_finish: 13142 @bl common_squeak4 13143 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13144 FETCH(r1, 3) @ r1<- BBBB 13145 cmp r9, #0 @ check object for null 13146 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13147 beq common_errNullObject @ object was null 13148 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13149 GET_INST_OPCODE(ip) @ extract opcode from rINST 13150 @ no-op @ releasing store 13151 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13152 GOTO_OPCODE(ip) @ jump to next instruction 13153 13154/* continuation for OP_SGET_JUMBO */ 13155 13156 /* 13157 * Continuation if the field has not yet been resolved. 13158 * r1: AAAAAAAA field ref 13159 */ 13160.LOP_SGET_JUMBO_resolve: 13161 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13162 EXPORT_PC() @ resolve() could throw, so export now 13163 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13164 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13165 cmp r0, #0 @ success? 13166 bne .LOP_SGET_JUMBO_finish @ yes, finish 13167 b common_exceptionThrown @ no, handle exception 13168 13169/* continuation for OP_SGET_WIDE_JUMBO */ 13170 13171 /* 13172 * Continuation if the field has not yet been resolved. 13173 * r1: AAAAAAAA field ref 13174 * 13175 * Returns StaticField pointer in r0. 13176 */ 13177.LOP_SGET_WIDE_JUMBO_resolve: 13178 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13179 EXPORT_PC() @ resolve() could throw, so export now 13180 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13181 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13182 cmp r0, #0 @ success? 13183 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish 13184 b common_exceptionThrown @ no, handle exception 13185 13186/* continuation for OP_SGET_OBJECT_JUMBO */ 13187 13188 /* 13189 * Continuation if the field has not yet been resolved. 13190 * r1: AAAAAAAA field ref 13191 */ 13192.LOP_SGET_OBJECT_JUMBO_resolve: 13193 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13194 EXPORT_PC() @ resolve() could throw, so export now 13195 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13196 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13197 cmp r0, #0 @ success? 13198 bne .LOP_SGET_OBJECT_JUMBO_finish @ yes, finish 13199 b common_exceptionThrown @ no, handle exception 13200 13201/* continuation for OP_SGET_BOOLEAN_JUMBO */ 13202 13203 /* 13204 * Continuation if the field has not yet been resolved. 13205 * r1: AAAAAAAA field ref 13206 */ 13207.LOP_SGET_BOOLEAN_JUMBO_resolve: 13208 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13209 EXPORT_PC() @ resolve() could throw, so export now 13210 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13211 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13212 cmp r0, #0 @ success? 13213 bne .LOP_SGET_BOOLEAN_JUMBO_finish @ yes, finish 13214 b common_exceptionThrown @ no, handle exception 13215 13216/* continuation for OP_SGET_BYTE_JUMBO */ 13217 13218 /* 13219 * Continuation if the field has not yet been resolved. 13220 * r1: AAAAAAAA field ref 13221 */ 13222.LOP_SGET_BYTE_JUMBO_resolve: 13223 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13224 EXPORT_PC() @ resolve() could throw, so export now 13225 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13226 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13227 cmp r0, #0 @ success? 13228 bne .LOP_SGET_BYTE_JUMBO_finish @ yes, finish 13229 b common_exceptionThrown @ no, handle exception 13230 13231/* continuation for OP_SGET_CHAR_JUMBO */ 13232 13233 /* 13234 * Continuation if the field has not yet been resolved. 13235 * r1: AAAAAAAA field ref 13236 */ 13237.LOP_SGET_CHAR_JUMBO_resolve: 13238 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13239 EXPORT_PC() @ resolve() could throw, so export now 13240 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13241 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13242 cmp r0, #0 @ success? 13243 bne .LOP_SGET_CHAR_JUMBO_finish @ yes, finish 13244 b common_exceptionThrown @ no, handle exception 13245 13246/* continuation for OP_SGET_SHORT_JUMBO */ 13247 13248 /* 13249 * Continuation if the field has not yet been resolved. 13250 * r1: AAAAAAAA field ref 13251 */ 13252.LOP_SGET_SHORT_JUMBO_resolve: 13253 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13254 EXPORT_PC() @ resolve() could throw, so export now 13255 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13256 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13257 cmp r0, #0 @ success? 13258 bne .LOP_SGET_SHORT_JUMBO_finish @ yes, finish 13259 b common_exceptionThrown @ no, handle exception 13260 13261/* continuation for OP_SPUT_JUMBO */ 13262 13263 /* 13264 * Continuation if the field has not yet been resolved. 13265 * r1: AAAAAAAA field ref 13266 */ 13267.LOP_SPUT_JUMBO_resolve: 13268 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13269 EXPORT_PC() @ resolve() could throw, so export now 13270 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13271 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13272 cmp r0, #0 @ success? 13273 bne .LOP_SPUT_JUMBO_finish @ yes, finish 13274 b common_exceptionThrown @ no, handle exception 13275 13276/* continuation for OP_SPUT_WIDE_JUMBO */ 13277 13278 /* 13279 * Continuation if the field has not yet been resolved. 13280 * r1: AAAAAAAA field ref 13281 * r9: &fp[BBBB] 13282 * 13283 * Returns StaticField pointer in r2. 13284 */ 13285.LOP_SPUT_WIDE_JUMBO_resolve: 13286 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13287 EXPORT_PC() @ resolve() could throw, so export now 13288 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13289 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13290 cmp r0, #0 @ success? 13291 mov r2, r0 @ copy to r2 13292 bne .LOP_SPUT_WIDE_JUMBO_finish @ yes, finish 13293 b common_exceptionThrown @ no, handle exception 13294 13295/* continuation for OP_SPUT_OBJECT_JUMBO */ 13296 13297.LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0 13298 FETCH(r2, 3) @ r2<- BBBB 13299 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 13300 GET_VREG(r1, r2) @ r1<- fp[BBBB] 13301 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13302 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 13303 GET_INST_OPCODE(ip) @ extract opcode from rINST 13304 @ no-op @ releasing store 13305 str r1, [r0, #offStaticField_value] @ field<- vBBBB 13306 cmp r1, #0 @ stored a null object? 13307 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 13308 GOTO_OPCODE(ip) @ jump to next instruction 13309 13310/* continuation for OP_SPUT_BOOLEAN_JUMBO */ 13311 13312 /* 13313 * Continuation if the field has not yet been resolved. 13314 * r1: AAAAAAAA field ref 13315 */ 13316.LOP_SPUT_BOOLEAN_JUMBO_resolve: 13317 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13318 EXPORT_PC() @ resolve() could throw, so export now 13319 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13320 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13321 cmp r0, #0 @ success? 13322 bne .LOP_SPUT_BOOLEAN_JUMBO_finish @ yes, finish 13323 b common_exceptionThrown @ no, handle exception 13324 13325/* continuation for OP_SPUT_BYTE_JUMBO */ 13326 13327 /* 13328 * Continuation if the field has not yet been resolved. 13329 * r1: AAAAAAAA field ref 13330 */ 13331.LOP_SPUT_BYTE_JUMBO_resolve: 13332 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13333 EXPORT_PC() @ resolve() could throw, so export now 13334 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13335 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13336 cmp r0, #0 @ success? 13337 bne .LOP_SPUT_BYTE_JUMBO_finish @ yes, finish 13338 b common_exceptionThrown @ no, handle exception 13339 13340/* continuation for OP_SPUT_CHAR_JUMBO */ 13341 13342 /* 13343 * Continuation if the field has not yet been resolved. 13344 * r1: AAAAAAAA field ref 13345 */ 13346.LOP_SPUT_CHAR_JUMBO_resolve: 13347 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13348 EXPORT_PC() @ resolve() could throw, so export now 13349 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13350 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13351 cmp r0, #0 @ success? 13352 bne .LOP_SPUT_CHAR_JUMBO_finish @ yes, finish 13353 b common_exceptionThrown @ no, handle exception 13354 13355/* continuation for OP_SPUT_SHORT_JUMBO */ 13356 13357 /* 13358 * Continuation if the field has not yet been resolved. 13359 * r1: AAAAAAAA field ref 13360 */ 13361.LOP_SPUT_SHORT_JUMBO_resolve: 13362 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13363 EXPORT_PC() @ resolve() could throw, so export now 13364 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13365 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13366 cmp r0, #0 @ success? 13367 bne .LOP_SPUT_SHORT_JUMBO_finish @ yes, finish 13368 b common_exceptionThrown @ no, handle exception 13369 13370/* continuation for OP_INVOKE_VIRTUAL_JUMBO */ 13371 13372 /* 13373 * At this point: 13374 * r0 = resolved base method 13375 */ 13376.LOP_INVOKE_VIRTUAL_JUMBO_continue: 13377 FETCH(r10, 4) @ r10<- CCCC 13378 GET_VREG(r1, r10) @ r1<- "this" ptr 13379 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13380 cmp r1, #0 @ is "this" null? 13381 beq common_errNullObject @ null "this", throw exception 13382 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 13383 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 13384 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 13385 bl common_invokeMethodJumbo @ continue on 13386 13387/* continuation for OP_INVOKE_SUPER_JUMBO */ 13388 13389 /* 13390 * At this point: 13391 * r0 = resolved base method 13392 * r9 = method->clazz 13393 */ 13394.LOP_INVOKE_SUPER_JUMBO_continue: 13395 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 13396 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13397 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 13398 EXPORT_PC() @ must export for invoke 13399 cmp r2, r3 @ compare (methodIndex, vtableCount) 13400 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass 13401 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 13402 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 13403 bl common_invokeMethodJumbo @ continue on 13404 13405.LOP_INVOKE_SUPER_JUMBO_resolve: 13406 mov r0, r9 @ r0<- method->clazz 13407 mov r2, #METHOD_VIRTUAL @ resolver method type 13408 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13409 cmp r0, #0 @ got null? 13410 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue 13411 b common_exceptionThrown @ yes, handle exception 13412 13413 /* 13414 * Throw a NoSuchMethodError with the method name as the message. 13415 * r0 = resolved base method 13416 */ 13417.LOP_INVOKE_SUPER_JUMBO_nsm: 13418 ldr r1, [r0, #offMethod_name] @ r1<- method name 13419 b common_errNoSuchMethod 13420 13421/* continuation for OP_INVOKE_DIRECT_JUMBO */ 13422 13423 /* 13424 * On entry: 13425 * r1 = reference (CCCC) 13426 * r10 = "this" register 13427 */ 13428.LOP_INVOKE_DIRECT_JUMBO_resolve: 13429 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 13430 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 13431 mov r2, #METHOD_DIRECT @ resolver method type 13432 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13433 cmp r0, #0 @ got null? 13434 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 13435 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue 13436 b common_exceptionThrown @ yes, handle exception 13437 13438/* continuation for OP_IGET_VOLATILE_JUMBO */ 13439 13440 /* 13441 * Currently: 13442 * r0 holds resolved field 13443 * r9 holds object 13444 */ 13445.LOP_IGET_VOLATILE_JUMBO_resolved: 13446 cmp r0, #0 @ resolution unsuccessful? 13447 beq common_exceptionThrown @ yes, throw exception 13448 @ fall through to OP_IGET_VOLATILE_JUMBO_finish 13449 13450 /* 13451 * Currently: 13452 * r0 holds resolved field 13453 * r9 holds object 13454 */ 13455.LOP_IGET_VOLATILE_JUMBO_finish: 13456 @bl common_squeak0 13457 cmp r9, #0 @ check object for null 13458 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13459 beq common_errNullObject @ object was null 13460 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13461 SMP_DMB @ acquiring load 13462 FETCH(r2, 3) @ r2<- BBBB 13463 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13464 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13465 GET_INST_OPCODE(ip) @ extract opcode from rINST 13466 GOTO_OPCODE(ip) @ jump to next instruction 13467 13468/* continuation for OP_IGET_WIDE_VOLATILE_JUMBO */ 13469 13470 /* 13471 * Currently: 13472 * r0 holds resolved field 13473 * r9 holds object 13474 */ 13475.LOP_IGET_WIDE_VOLATILE_JUMBO_resolved: 13476 cmp r0, #0 @ resolution unsuccessful? 13477 beq common_exceptionThrown @ yes, throw exception 13478 @ fall through to OP_IGET_WIDE_VOLATILE_JUMBO_finish 13479 13480 /* 13481 * Currently: 13482 * r0 holds resolved field 13483 * r9 holds object 13484 */ 13485.LOP_IGET_WIDE_VOLATILE_JUMBO_finish: 13486 cmp r9, #0 @ check object for null 13487 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13488 beq common_errNullObject @ object was null 13489 .if 1 13490 add r0, r9, r3 @ r0<- address of field 13491 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 13492 .else 13493 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 13494 .endif 13495 FETCH(r2, 3) @ r2<- BBBB 13496 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13497 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 13498 GET_INST_OPCODE(ip) @ extract opcode from rINST 13499 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 13500 GOTO_OPCODE(ip) @ jump to next instruction 13501 13502/* continuation for OP_IGET_OBJECT_VOLATILE_JUMBO */ 13503 13504 /* 13505 * Currently: 13506 * r0 holds resolved field 13507 * r9 holds object 13508 */ 13509.LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved: 13510 cmp r0, #0 @ resolution unsuccessful? 13511 beq common_exceptionThrown @ yes, throw exception 13512 @ fall through to OP_IGET_OBJECT_VOLATILE_JUMBO_finish 13513 13514 /* 13515 * Currently: 13516 * r0 holds resolved field 13517 * r9 holds object 13518 */ 13519.LOP_IGET_OBJECT_VOLATILE_JUMBO_finish: 13520 @bl common_squeak0 13521 cmp r9, #0 @ check object for null 13522 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13523 beq common_errNullObject @ object was null 13524 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13525 SMP_DMB @ acquiring load 13526 FETCH(r2, 3) @ r2<- BBBB 13527 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13528 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13529 GET_INST_OPCODE(ip) @ extract opcode from rINST 13530 GOTO_OPCODE(ip) @ jump to next instruction 13531 13532/* continuation for OP_IPUT_VOLATILE_JUMBO */ 13533 13534 /* 13535 * Currently: 13536 * r0 holds resolved field 13537 * r9 holds object 13538 */ 13539.LOP_IPUT_VOLATILE_JUMBO_resolved: 13540 cmp r0, #0 @ resolution unsuccessful? 13541 beq common_exceptionThrown @ yes, throw exception 13542 @ fall through to OP_IPUT_VOLATILE_JUMBO_finish 13543 13544 /* 13545 * Currently: 13546 * r0 holds resolved field 13547 * r9 holds object 13548 */ 13549.LOP_IPUT_VOLATILE_JUMBO_finish: 13550 @bl common_squeak0 13551 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13552 FETCH(r1, 3) @ r1<- BBBB 13553 cmp r9, #0 @ check object for null 13554 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13555 beq common_errNullObject @ object was null 13556 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13557 GET_INST_OPCODE(ip) @ extract opcode from rINST 13558 SMP_DMB @ releasing store 13559 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13560 GOTO_OPCODE(ip) @ jump to next instruction 13561 13562/* continuation for OP_IPUT_WIDE_VOLATILE_JUMBO */ 13563 13564 /* 13565 * Currently: 13566 * r0 holds resolved field 13567 * r9 holds object 13568 */ 13569.LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved: 13570 cmp r0, #0 @ resolution unsuccessful? 13571 beq common_exceptionThrown @ yes, throw exception 13572 @ fall through to OP_IPUT_WIDE_VOLATILE_JUMBO_finish 13573 13574 /* 13575 * Currently: 13576 * r0 holds resolved field 13577 * r9 holds object 13578 */ 13579.LOP_IPUT_WIDE_VOLATILE_JUMBO_finish: 13580 cmp r9, #0 @ check object for null 13581 FETCH(r2, 3) @ r1<- BBBB 13582 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13583 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 13584 beq common_errNullObject @ object was null 13585 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13586 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 13587 GET_INST_OPCODE(r10) @ extract opcode from rINST 13588 .if 1 13589 add r2, r9, r3 @ r2<- target address 13590 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 13591 .else 13592 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 13593 .endif 13594 GOTO_OPCODE(r10) @ jump to next instruction 13595 13596/* continuation for OP_IPUT_OBJECT_VOLATILE_JUMBO */ 13597 13598 /* 13599 * Currently: 13600 * r0 holds resolved field 13601 * r9 holds object 13602 */ 13603.LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved: 13604 cmp r0, #0 @ resolution unsuccessful? 13605 beq common_exceptionThrown @ yes, throw exception 13606 @ fall through to OP_IPUT_OBJECT_VOLATILE_JUMBO_finish 13607 13608 /* 13609 * Currently: 13610 * r0 holds resolved field 13611 * r9 holds object 13612 */ 13613.LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish: 13614 @bl common_squeak0 13615 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13616 FETCH(r1, 3) @ r1<- BBBB 13617 cmp r9, #0 @ check object for null 13618 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13619 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13620 beq common_errNullObject @ object was null 13621 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13622 GET_INST_OPCODE(ip) @ extract opcode from rINST 13623 SMP_DMB @ releasing store 13624 str r0, [r9, r3] @ obj.field (32 bits)<- r0 13625 cmp r0, #0 @ stored a null reference? 13626 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 13627 GOTO_OPCODE(ip) @ jump to next instruction 13628 13629/* continuation for OP_SGET_VOLATILE_JUMBO */ 13630 13631 /* 13632 * Continuation if the field has not yet been resolved. 13633 * r1: AAAAAAAA field ref 13634 */ 13635.LOP_SGET_VOLATILE_JUMBO_resolve: 13636 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13637 EXPORT_PC() @ resolve() could throw, so export now 13638 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13639 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13640 cmp r0, #0 @ success? 13641 bne .LOP_SGET_VOLATILE_JUMBO_finish @ yes, finish 13642 b common_exceptionThrown @ no, handle exception 13643 13644/* continuation for OP_SGET_WIDE_VOLATILE_JUMBO */ 13645 13646 /* 13647 * Continuation if the field has not yet been resolved. 13648 * r1: AAAAAAAA field ref 13649 * 13650 * Returns StaticField pointer in r0. 13651 */ 13652.LOP_SGET_WIDE_VOLATILE_JUMBO_resolve: 13653 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13654 EXPORT_PC() @ resolve() could throw, so export now 13655 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13656 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13657 cmp r0, #0 @ success? 13658 bne .LOP_SGET_WIDE_VOLATILE_JUMBO_finish @ yes, finish 13659 b common_exceptionThrown @ no, handle exception 13660 13661/* continuation for OP_SGET_OBJECT_VOLATILE_JUMBO */ 13662 13663 /* 13664 * Continuation if the field has not yet been resolved. 13665 * r1: AAAAAAAA field ref 13666 */ 13667.LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve: 13668 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13669 EXPORT_PC() @ resolve() could throw, so export now 13670 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13671 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13672 cmp r0, #0 @ success? 13673 bne .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish @ yes, finish 13674 b common_exceptionThrown @ no, handle exception 13675 13676/* continuation for OP_SPUT_VOLATILE_JUMBO */ 13677 13678 /* 13679 * Continuation if the field has not yet been resolved. 13680 * r1: AAAAAAAA field ref 13681 */ 13682.LOP_SPUT_VOLATILE_JUMBO_resolve: 13683 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13684 EXPORT_PC() @ resolve() could throw, so export now 13685 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13686 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13687 cmp r0, #0 @ success? 13688 bne .LOP_SPUT_VOLATILE_JUMBO_finish @ yes, finish 13689 b common_exceptionThrown @ no, handle exception 13690 13691/* continuation for OP_SPUT_WIDE_VOLATILE_JUMBO */ 13692 13693 /* 13694 * Continuation if the field has not yet been resolved. 13695 * r1: AAAAAAAA field ref 13696 * r9: &fp[BBBB] 13697 * 13698 * Returns StaticField pointer in r2. 13699 */ 13700.LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve: 13701 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13702 EXPORT_PC() @ resolve() could throw, so export now 13703 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13704 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13705 cmp r0, #0 @ success? 13706 mov r2, r0 @ copy to r2 13707 bne .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish @ yes, finish 13708 b common_exceptionThrown @ no, handle exception 13709 13710/* continuation for OP_SPUT_OBJECT_VOLATILE_JUMBO */ 13711 13712.LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0 13713 FETCH(r2, 3) @ r2<- BBBB 13714 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 13715 GET_VREG(r1, r2) @ r1<- fp[BBBB] 13716 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13717 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 13718 GET_INST_OPCODE(ip) @ extract opcode from rINST 13719 SMP_DMB @ releasing store 13720 str r1, [r0, #offStaticField_value] @ field<- vBBBB 13721 cmp r1, #0 @ stored a null object? 13722 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 13723 GOTO_OPCODE(ip) @ jump to next instruction 13724 13725 .size dvmAsmSisterStart, .-dvmAsmSisterStart 13726 .global dvmAsmSisterEnd 13727dvmAsmSisterEnd: 13728 13729 13730 .global dvmAsmAltInstructionStart 13731 .type dvmAsmAltInstructionStart, %function 13732dvmAsmAltInstructionStart: 13733 .text 13734 13735/* ------------------------------ */ 13736 .balign 64 13737.L_ALT_OP_NOP: /* 0x00 */ 13738/* File: armv5te/alt_stub.S */ 13739/* 13740 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13741 * any interesting requests and then jump to the real instruction 13742 * handler. Note that the call to dvmCheckInst is done as a tail call. 13743 */ 13744 adrl lr, dvmAsmInstructionStart + (0 * 64) 13745 mov r0, rPC @ arg0 13746 mov r1, rSELF @ arg1 13747 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13748 13749/* ------------------------------ */ 13750 .balign 64 13751.L_ALT_OP_MOVE: /* 0x01 */ 13752/* File: armv5te/alt_stub.S */ 13753/* 13754 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13755 * any interesting requests and then jump to the real instruction 13756 * handler. Note that the call to dvmCheckInst is done as a tail call. 13757 */ 13758 adrl lr, dvmAsmInstructionStart + (1 * 64) 13759 mov r0, rPC @ arg0 13760 mov r1, rSELF @ arg1 13761 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13762 13763/* ------------------------------ */ 13764 .balign 64 13765.L_ALT_OP_MOVE_FROM16: /* 0x02 */ 13766/* File: armv5te/alt_stub.S */ 13767/* 13768 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13769 * any interesting requests and then jump to the real instruction 13770 * handler. Note that the call to dvmCheckInst is done as a tail call. 13771 */ 13772 adrl lr, dvmAsmInstructionStart + (2 * 64) 13773 mov r0, rPC @ arg0 13774 mov r1, rSELF @ arg1 13775 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13776 13777/* ------------------------------ */ 13778 .balign 64 13779.L_ALT_OP_MOVE_16: /* 0x03 */ 13780/* File: armv5te/alt_stub.S */ 13781/* 13782 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13783 * any interesting requests and then jump to the real instruction 13784 * handler. Note that the call to dvmCheckInst is done as a tail call. 13785 */ 13786 adrl lr, dvmAsmInstructionStart + (3 * 64) 13787 mov r0, rPC @ arg0 13788 mov r1, rSELF @ arg1 13789 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13790 13791/* ------------------------------ */ 13792 .balign 64 13793.L_ALT_OP_MOVE_WIDE: /* 0x04 */ 13794/* File: armv5te/alt_stub.S */ 13795/* 13796 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13797 * any interesting requests and then jump to the real instruction 13798 * handler. Note that the call to dvmCheckInst is done as a tail call. 13799 */ 13800 adrl lr, dvmAsmInstructionStart + (4 * 64) 13801 mov r0, rPC @ arg0 13802 mov r1, rSELF @ arg1 13803 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13804 13805/* ------------------------------ */ 13806 .balign 64 13807.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */ 13808/* File: armv5te/alt_stub.S */ 13809/* 13810 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13811 * any interesting requests and then jump to the real instruction 13812 * handler. Note that the call to dvmCheckInst is done as a tail call. 13813 */ 13814 adrl lr, dvmAsmInstructionStart + (5 * 64) 13815 mov r0, rPC @ arg0 13816 mov r1, rSELF @ arg1 13817 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13818 13819/* ------------------------------ */ 13820 .balign 64 13821.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */ 13822/* File: armv5te/alt_stub.S */ 13823/* 13824 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13825 * any interesting requests and then jump to the real instruction 13826 * handler. Note that the call to dvmCheckInst is done as a tail call. 13827 */ 13828 adrl lr, dvmAsmInstructionStart + (6 * 64) 13829 mov r0, rPC @ arg0 13830 mov r1, rSELF @ arg1 13831 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13832 13833/* ------------------------------ */ 13834 .balign 64 13835.L_ALT_OP_MOVE_OBJECT: /* 0x07 */ 13836/* File: armv5te/alt_stub.S */ 13837/* 13838 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13839 * any interesting requests and then jump to the real instruction 13840 * handler. Note that the call to dvmCheckInst is done as a tail call. 13841 */ 13842 adrl lr, dvmAsmInstructionStart + (7 * 64) 13843 mov r0, rPC @ arg0 13844 mov r1, rSELF @ arg1 13845 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13846 13847/* ------------------------------ */ 13848 .balign 64 13849.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 13850/* File: armv5te/alt_stub.S */ 13851/* 13852 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13853 * any interesting requests and then jump to the real instruction 13854 * handler. Note that the call to dvmCheckInst is done as a tail call. 13855 */ 13856 adrl lr, dvmAsmInstructionStart + (8 * 64) 13857 mov r0, rPC @ arg0 13858 mov r1, rSELF @ arg1 13859 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13860 13861/* ------------------------------ */ 13862 .balign 64 13863.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */ 13864/* File: armv5te/alt_stub.S */ 13865/* 13866 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13867 * any interesting requests and then jump to the real instruction 13868 * handler. Note that the call to dvmCheckInst is done as a tail call. 13869 */ 13870 adrl lr, dvmAsmInstructionStart + (9 * 64) 13871 mov r0, rPC @ arg0 13872 mov r1, rSELF @ arg1 13873 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13874 13875/* ------------------------------ */ 13876 .balign 64 13877.L_ALT_OP_MOVE_RESULT: /* 0x0a */ 13878/* File: armv5te/alt_stub.S */ 13879/* 13880 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13881 * any interesting requests and then jump to the real instruction 13882 * handler. Note that the call to dvmCheckInst is done as a tail call. 13883 */ 13884 adrl lr, dvmAsmInstructionStart + (10 * 64) 13885 mov r0, rPC @ arg0 13886 mov r1, rSELF @ arg1 13887 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13888 13889/* ------------------------------ */ 13890 .balign 64 13891.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */ 13892/* File: armv5te/alt_stub.S */ 13893/* 13894 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13895 * any interesting requests and then jump to the real instruction 13896 * handler. Note that the call to dvmCheckInst is done as a tail call. 13897 */ 13898 adrl lr, dvmAsmInstructionStart + (11 * 64) 13899 mov r0, rPC @ arg0 13900 mov r1, rSELF @ arg1 13901 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13902 13903/* ------------------------------ */ 13904 .balign 64 13905.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 13906/* File: armv5te/alt_stub.S */ 13907/* 13908 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13909 * any interesting requests and then jump to the real instruction 13910 * handler. Note that the call to dvmCheckInst is done as a tail call. 13911 */ 13912 adrl lr, dvmAsmInstructionStart + (12 * 64) 13913 mov r0, rPC @ arg0 13914 mov r1, rSELF @ arg1 13915 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13916 13917/* ------------------------------ */ 13918 .balign 64 13919.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */ 13920/* File: armv5te/alt_stub.S */ 13921/* 13922 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13923 * any interesting requests and then jump to the real instruction 13924 * handler. Note that the call to dvmCheckInst is done as a tail call. 13925 */ 13926 adrl lr, dvmAsmInstructionStart + (13 * 64) 13927 mov r0, rPC @ arg0 13928 mov r1, rSELF @ arg1 13929 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13930 13931/* ------------------------------ */ 13932 .balign 64 13933.L_ALT_OP_RETURN_VOID: /* 0x0e */ 13934/* File: armv5te/alt_stub.S */ 13935/* 13936 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13937 * any interesting requests and then jump to the real instruction 13938 * handler. Note that the call to dvmCheckInst is done as a tail call. 13939 */ 13940 adrl lr, dvmAsmInstructionStart + (14 * 64) 13941 mov r0, rPC @ arg0 13942 mov r1, rSELF @ arg1 13943 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13944 13945/* ------------------------------ */ 13946 .balign 64 13947.L_ALT_OP_RETURN: /* 0x0f */ 13948/* File: armv5te/alt_stub.S */ 13949/* 13950 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13951 * any interesting requests and then jump to the real instruction 13952 * handler. Note that the call to dvmCheckInst is done as a tail call. 13953 */ 13954 adrl lr, dvmAsmInstructionStart + (15 * 64) 13955 mov r0, rPC @ arg0 13956 mov r1, rSELF @ arg1 13957 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13958 13959/* ------------------------------ */ 13960 .balign 64 13961.L_ALT_OP_RETURN_WIDE: /* 0x10 */ 13962/* File: armv5te/alt_stub.S */ 13963/* 13964 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13965 * any interesting requests and then jump to the real instruction 13966 * handler. Note that the call to dvmCheckInst is done as a tail call. 13967 */ 13968 adrl lr, dvmAsmInstructionStart + (16 * 64) 13969 mov r0, rPC @ arg0 13970 mov r1, rSELF @ arg1 13971 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13972 13973/* ------------------------------ */ 13974 .balign 64 13975.L_ALT_OP_RETURN_OBJECT: /* 0x11 */ 13976/* File: armv5te/alt_stub.S */ 13977/* 13978 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13979 * any interesting requests and then jump to the real instruction 13980 * handler. Note that the call to dvmCheckInst is done as a tail call. 13981 */ 13982 adrl lr, dvmAsmInstructionStart + (17 * 64) 13983 mov r0, rPC @ arg0 13984 mov r1, rSELF @ arg1 13985 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13986 13987/* ------------------------------ */ 13988 .balign 64 13989.L_ALT_OP_CONST_4: /* 0x12 */ 13990/* File: armv5te/alt_stub.S */ 13991/* 13992 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13993 * any interesting requests and then jump to the real instruction 13994 * handler. Note that the call to dvmCheckInst is done as a tail call. 13995 */ 13996 adrl lr, dvmAsmInstructionStart + (18 * 64) 13997 mov r0, rPC @ arg0 13998 mov r1, rSELF @ arg1 13999 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14000 14001/* ------------------------------ */ 14002 .balign 64 14003.L_ALT_OP_CONST_16: /* 0x13 */ 14004/* File: armv5te/alt_stub.S */ 14005/* 14006 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14007 * any interesting requests and then jump to the real instruction 14008 * handler. Note that the call to dvmCheckInst is done as a tail call. 14009 */ 14010 adrl lr, dvmAsmInstructionStart + (19 * 64) 14011 mov r0, rPC @ arg0 14012 mov r1, rSELF @ arg1 14013 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14014 14015/* ------------------------------ */ 14016 .balign 64 14017.L_ALT_OP_CONST: /* 0x14 */ 14018/* File: armv5te/alt_stub.S */ 14019/* 14020 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14021 * any interesting requests and then jump to the real instruction 14022 * handler. Note that the call to dvmCheckInst is done as a tail call. 14023 */ 14024 adrl lr, dvmAsmInstructionStart + (20 * 64) 14025 mov r0, rPC @ arg0 14026 mov r1, rSELF @ arg1 14027 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14028 14029/* ------------------------------ */ 14030 .balign 64 14031.L_ALT_OP_CONST_HIGH16: /* 0x15 */ 14032/* File: armv5te/alt_stub.S */ 14033/* 14034 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14035 * any interesting requests and then jump to the real instruction 14036 * handler. Note that the call to dvmCheckInst is done as a tail call. 14037 */ 14038 adrl lr, dvmAsmInstructionStart + (21 * 64) 14039 mov r0, rPC @ arg0 14040 mov r1, rSELF @ arg1 14041 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14042 14043/* ------------------------------ */ 14044 .balign 64 14045.L_ALT_OP_CONST_WIDE_16: /* 0x16 */ 14046/* File: armv5te/alt_stub.S */ 14047/* 14048 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14049 * any interesting requests and then jump to the real instruction 14050 * handler. Note that the call to dvmCheckInst is done as a tail call. 14051 */ 14052 adrl lr, dvmAsmInstructionStart + (22 * 64) 14053 mov r0, rPC @ arg0 14054 mov r1, rSELF @ arg1 14055 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14056 14057/* ------------------------------ */ 14058 .balign 64 14059.L_ALT_OP_CONST_WIDE_32: /* 0x17 */ 14060/* File: armv5te/alt_stub.S */ 14061/* 14062 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14063 * any interesting requests and then jump to the real instruction 14064 * handler. Note that the call to dvmCheckInst is done as a tail call. 14065 */ 14066 adrl lr, dvmAsmInstructionStart + (23 * 64) 14067 mov r0, rPC @ arg0 14068 mov r1, rSELF @ arg1 14069 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14070 14071/* ------------------------------ */ 14072 .balign 64 14073.L_ALT_OP_CONST_WIDE: /* 0x18 */ 14074/* File: armv5te/alt_stub.S */ 14075/* 14076 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14077 * any interesting requests and then jump to the real instruction 14078 * handler. Note that the call to dvmCheckInst is done as a tail call. 14079 */ 14080 adrl lr, dvmAsmInstructionStart + (24 * 64) 14081 mov r0, rPC @ arg0 14082 mov r1, rSELF @ arg1 14083 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14084 14085/* ------------------------------ */ 14086 .balign 64 14087.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */ 14088/* File: armv5te/alt_stub.S */ 14089/* 14090 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14091 * any interesting requests and then jump to the real instruction 14092 * handler. Note that the call to dvmCheckInst is done as a tail call. 14093 */ 14094 adrl lr, dvmAsmInstructionStart + (25 * 64) 14095 mov r0, rPC @ arg0 14096 mov r1, rSELF @ arg1 14097 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14098 14099/* ------------------------------ */ 14100 .balign 64 14101.L_ALT_OP_CONST_STRING: /* 0x1a */ 14102/* File: armv5te/alt_stub.S */ 14103/* 14104 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14105 * any interesting requests and then jump to the real instruction 14106 * handler. Note that the call to dvmCheckInst is done as a tail call. 14107 */ 14108 adrl lr, dvmAsmInstructionStart + (26 * 64) 14109 mov r0, rPC @ arg0 14110 mov r1, rSELF @ arg1 14111 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14112 14113/* ------------------------------ */ 14114 .balign 64 14115.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */ 14116/* File: armv5te/alt_stub.S */ 14117/* 14118 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14119 * any interesting requests and then jump to the real instruction 14120 * handler. Note that the call to dvmCheckInst is done as a tail call. 14121 */ 14122 adrl lr, dvmAsmInstructionStart + (27 * 64) 14123 mov r0, rPC @ arg0 14124 mov r1, rSELF @ arg1 14125 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14126 14127/* ------------------------------ */ 14128 .balign 64 14129.L_ALT_OP_CONST_CLASS: /* 0x1c */ 14130/* File: armv5te/alt_stub.S */ 14131/* 14132 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14133 * any interesting requests and then jump to the real instruction 14134 * handler. Note that the call to dvmCheckInst is done as a tail call. 14135 */ 14136 adrl lr, dvmAsmInstructionStart + (28 * 64) 14137 mov r0, rPC @ arg0 14138 mov r1, rSELF @ arg1 14139 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14140 14141/* ------------------------------ */ 14142 .balign 64 14143.L_ALT_OP_MONITOR_ENTER: /* 0x1d */ 14144/* File: armv5te/alt_stub.S */ 14145/* 14146 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14147 * any interesting requests and then jump to the real instruction 14148 * handler. Note that the call to dvmCheckInst is done as a tail call. 14149 */ 14150 adrl lr, dvmAsmInstructionStart + (29 * 64) 14151 mov r0, rPC @ arg0 14152 mov r1, rSELF @ arg1 14153 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14154 14155/* ------------------------------ */ 14156 .balign 64 14157.L_ALT_OP_MONITOR_EXIT: /* 0x1e */ 14158/* File: armv5te/alt_stub.S */ 14159/* 14160 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14161 * any interesting requests and then jump to the real instruction 14162 * handler. Note that the call to dvmCheckInst is done as a tail call. 14163 */ 14164 adrl lr, dvmAsmInstructionStart + (30 * 64) 14165 mov r0, rPC @ arg0 14166 mov r1, rSELF @ arg1 14167 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14168 14169/* ------------------------------ */ 14170 .balign 64 14171.L_ALT_OP_CHECK_CAST: /* 0x1f */ 14172/* File: armv5te/alt_stub.S */ 14173/* 14174 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14175 * any interesting requests and then jump to the real instruction 14176 * handler. Note that the call to dvmCheckInst is done as a tail call. 14177 */ 14178 adrl lr, dvmAsmInstructionStart + (31 * 64) 14179 mov r0, rPC @ arg0 14180 mov r1, rSELF @ arg1 14181 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14182 14183/* ------------------------------ */ 14184 .balign 64 14185.L_ALT_OP_INSTANCE_OF: /* 0x20 */ 14186/* File: armv5te/alt_stub.S */ 14187/* 14188 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14189 * any interesting requests and then jump to the real instruction 14190 * handler. Note that the call to dvmCheckInst is done as a tail call. 14191 */ 14192 adrl lr, dvmAsmInstructionStart + (32 * 64) 14193 mov r0, rPC @ arg0 14194 mov r1, rSELF @ arg1 14195 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14196 14197/* ------------------------------ */ 14198 .balign 64 14199.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */ 14200/* File: armv5te/alt_stub.S */ 14201/* 14202 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14203 * any interesting requests and then jump to the real instruction 14204 * handler. Note that the call to dvmCheckInst is done as a tail call. 14205 */ 14206 adrl lr, dvmAsmInstructionStart + (33 * 64) 14207 mov r0, rPC @ arg0 14208 mov r1, rSELF @ arg1 14209 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14210 14211/* ------------------------------ */ 14212 .balign 64 14213.L_ALT_OP_NEW_INSTANCE: /* 0x22 */ 14214/* File: armv5te/alt_stub.S */ 14215/* 14216 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14217 * any interesting requests and then jump to the real instruction 14218 * handler. Note that the call to dvmCheckInst is done as a tail call. 14219 */ 14220 adrl lr, dvmAsmInstructionStart + (34 * 64) 14221 mov r0, rPC @ arg0 14222 mov r1, rSELF @ arg1 14223 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14224 14225/* ------------------------------ */ 14226 .balign 64 14227.L_ALT_OP_NEW_ARRAY: /* 0x23 */ 14228/* File: armv5te/alt_stub.S */ 14229/* 14230 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14231 * any interesting requests and then jump to the real instruction 14232 * handler. Note that the call to dvmCheckInst is done as a tail call. 14233 */ 14234 adrl lr, dvmAsmInstructionStart + (35 * 64) 14235 mov r0, rPC @ arg0 14236 mov r1, rSELF @ arg1 14237 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14238 14239/* ------------------------------ */ 14240 .balign 64 14241.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */ 14242/* File: armv5te/alt_stub.S */ 14243/* 14244 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14245 * any interesting requests and then jump to the real instruction 14246 * handler. Note that the call to dvmCheckInst is done as a tail call. 14247 */ 14248 adrl lr, dvmAsmInstructionStart + (36 * 64) 14249 mov r0, rPC @ arg0 14250 mov r1, rSELF @ arg1 14251 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14252 14253/* ------------------------------ */ 14254 .balign 64 14255.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 14256/* File: armv5te/alt_stub.S */ 14257/* 14258 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14259 * any interesting requests and then jump to the real instruction 14260 * handler. Note that the call to dvmCheckInst is done as a tail call. 14261 */ 14262 adrl lr, dvmAsmInstructionStart + (37 * 64) 14263 mov r0, rPC @ arg0 14264 mov r1, rSELF @ arg1 14265 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14266 14267/* ------------------------------ */ 14268 .balign 64 14269.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */ 14270/* File: armv5te/alt_stub.S */ 14271/* 14272 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14273 * any interesting requests and then jump to the real instruction 14274 * handler. Note that the call to dvmCheckInst is done as a tail call. 14275 */ 14276 adrl lr, dvmAsmInstructionStart + (38 * 64) 14277 mov r0, rPC @ arg0 14278 mov r1, rSELF @ arg1 14279 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14280 14281/* ------------------------------ */ 14282 .balign 64 14283.L_ALT_OP_THROW: /* 0x27 */ 14284/* File: armv5te/alt_stub.S */ 14285/* 14286 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14287 * any interesting requests and then jump to the real instruction 14288 * handler. Note that the call to dvmCheckInst is done as a tail call. 14289 */ 14290 adrl lr, dvmAsmInstructionStart + (39 * 64) 14291 mov r0, rPC @ arg0 14292 mov r1, rSELF @ arg1 14293 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14294 14295/* ------------------------------ */ 14296 .balign 64 14297.L_ALT_OP_GOTO: /* 0x28 */ 14298/* File: armv5te/alt_stub.S */ 14299/* 14300 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14301 * any interesting requests and then jump to the real instruction 14302 * handler. Note that the call to dvmCheckInst is done as a tail call. 14303 */ 14304 adrl lr, dvmAsmInstructionStart + (40 * 64) 14305 mov r0, rPC @ arg0 14306 mov r1, rSELF @ arg1 14307 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14308 14309/* ------------------------------ */ 14310 .balign 64 14311.L_ALT_OP_GOTO_16: /* 0x29 */ 14312/* File: armv5te/alt_stub.S */ 14313/* 14314 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14315 * any interesting requests and then jump to the real instruction 14316 * handler. Note that the call to dvmCheckInst is done as a tail call. 14317 */ 14318 adrl lr, dvmAsmInstructionStart + (41 * 64) 14319 mov r0, rPC @ arg0 14320 mov r1, rSELF @ arg1 14321 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14322 14323/* ------------------------------ */ 14324 .balign 64 14325.L_ALT_OP_GOTO_32: /* 0x2a */ 14326/* File: armv5te/alt_stub.S */ 14327/* 14328 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14329 * any interesting requests and then jump to the real instruction 14330 * handler. Note that the call to dvmCheckInst is done as a tail call. 14331 */ 14332 adrl lr, dvmAsmInstructionStart + (42 * 64) 14333 mov r0, rPC @ arg0 14334 mov r1, rSELF @ arg1 14335 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14336 14337/* ------------------------------ */ 14338 .balign 64 14339.L_ALT_OP_PACKED_SWITCH: /* 0x2b */ 14340/* File: armv5te/alt_stub.S */ 14341/* 14342 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14343 * any interesting requests and then jump to the real instruction 14344 * handler. Note that the call to dvmCheckInst is done as a tail call. 14345 */ 14346 adrl lr, dvmAsmInstructionStart + (43 * 64) 14347 mov r0, rPC @ arg0 14348 mov r1, rSELF @ arg1 14349 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14350 14351/* ------------------------------ */ 14352 .balign 64 14353.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */ 14354/* File: armv5te/alt_stub.S */ 14355/* 14356 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14357 * any interesting requests and then jump to the real instruction 14358 * handler. Note that the call to dvmCheckInst is done as a tail call. 14359 */ 14360 adrl lr, dvmAsmInstructionStart + (44 * 64) 14361 mov r0, rPC @ arg0 14362 mov r1, rSELF @ arg1 14363 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14364 14365/* ------------------------------ */ 14366 .balign 64 14367.L_ALT_OP_CMPL_FLOAT: /* 0x2d */ 14368/* File: armv5te/alt_stub.S */ 14369/* 14370 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14371 * any interesting requests and then jump to the real instruction 14372 * handler. Note that the call to dvmCheckInst is done as a tail call. 14373 */ 14374 adrl lr, dvmAsmInstructionStart + (45 * 64) 14375 mov r0, rPC @ arg0 14376 mov r1, rSELF @ arg1 14377 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14378 14379/* ------------------------------ */ 14380 .balign 64 14381.L_ALT_OP_CMPG_FLOAT: /* 0x2e */ 14382/* File: armv5te/alt_stub.S */ 14383/* 14384 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14385 * any interesting requests and then jump to the real instruction 14386 * handler. Note that the call to dvmCheckInst is done as a tail call. 14387 */ 14388 adrl lr, dvmAsmInstructionStart + (46 * 64) 14389 mov r0, rPC @ arg0 14390 mov r1, rSELF @ arg1 14391 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14392 14393/* ------------------------------ */ 14394 .balign 64 14395.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */ 14396/* File: armv5te/alt_stub.S */ 14397/* 14398 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14399 * any interesting requests and then jump to the real instruction 14400 * handler. Note that the call to dvmCheckInst is done as a tail call. 14401 */ 14402 adrl lr, dvmAsmInstructionStart + (47 * 64) 14403 mov r0, rPC @ arg0 14404 mov r1, rSELF @ arg1 14405 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14406 14407/* ------------------------------ */ 14408 .balign 64 14409.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */ 14410/* File: armv5te/alt_stub.S */ 14411/* 14412 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14413 * any interesting requests and then jump to the real instruction 14414 * handler. Note that the call to dvmCheckInst is done as a tail call. 14415 */ 14416 adrl lr, dvmAsmInstructionStart + (48 * 64) 14417 mov r0, rPC @ arg0 14418 mov r1, rSELF @ arg1 14419 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14420 14421/* ------------------------------ */ 14422 .balign 64 14423.L_ALT_OP_CMP_LONG: /* 0x31 */ 14424/* File: armv5te/alt_stub.S */ 14425/* 14426 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14427 * any interesting requests and then jump to the real instruction 14428 * handler. Note that the call to dvmCheckInst is done as a tail call. 14429 */ 14430 adrl lr, dvmAsmInstructionStart + (49 * 64) 14431 mov r0, rPC @ arg0 14432 mov r1, rSELF @ arg1 14433 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14434 14435/* ------------------------------ */ 14436 .balign 64 14437.L_ALT_OP_IF_EQ: /* 0x32 */ 14438/* File: armv5te/alt_stub.S */ 14439/* 14440 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14441 * any interesting requests and then jump to the real instruction 14442 * handler. Note that the call to dvmCheckInst is done as a tail call. 14443 */ 14444 adrl lr, dvmAsmInstructionStart + (50 * 64) 14445 mov r0, rPC @ arg0 14446 mov r1, rSELF @ arg1 14447 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14448 14449/* ------------------------------ */ 14450 .balign 64 14451.L_ALT_OP_IF_NE: /* 0x33 */ 14452/* File: armv5te/alt_stub.S */ 14453/* 14454 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14455 * any interesting requests and then jump to the real instruction 14456 * handler. Note that the call to dvmCheckInst is done as a tail call. 14457 */ 14458 adrl lr, dvmAsmInstructionStart + (51 * 64) 14459 mov r0, rPC @ arg0 14460 mov r1, rSELF @ arg1 14461 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14462 14463/* ------------------------------ */ 14464 .balign 64 14465.L_ALT_OP_IF_LT: /* 0x34 */ 14466/* File: armv5te/alt_stub.S */ 14467/* 14468 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14469 * any interesting requests and then jump to the real instruction 14470 * handler. Note that the call to dvmCheckInst is done as a tail call. 14471 */ 14472 adrl lr, dvmAsmInstructionStart + (52 * 64) 14473 mov r0, rPC @ arg0 14474 mov r1, rSELF @ arg1 14475 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14476 14477/* ------------------------------ */ 14478 .balign 64 14479.L_ALT_OP_IF_GE: /* 0x35 */ 14480/* File: armv5te/alt_stub.S */ 14481/* 14482 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14483 * any interesting requests and then jump to the real instruction 14484 * handler. Note that the call to dvmCheckInst is done as a tail call. 14485 */ 14486 adrl lr, dvmAsmInstructionStart + (53 * 64) 14487 mov r0, rPC @ arg0 14488 mov r1, rSELF @ arg1 14489 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14490 14491/* ------------------------------ */ 14492 .balign 64 14493.L_ALT_OP_IF_GT: /* 0x36 */ 14494/* File: armv5te/alt_stub.S */ 14495/* 14496 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14497 * any interesting requests and then jump to the real instruction 14498 * handler. Note that the call to dvmCheckInst is done as a tail call. 14499 */ 14500 adrl lr, dvmAsmInstructionStart + (54 * 64) 14501 mov r0, rPC @ arg0 14502 mov r1, rSELF @ arg1 14503 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14504 14505/* ------------------------------ */ 14506 .balign 64 14507.L_ALT_OP_IF_LE: /* 0x37 */ 14508/* File: armv5te/alt_stub.S */ 14509/* 14510 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14511 * any interesting requests and then jump to the real instruction 14512 * handler. Note that the call to dvmCheckInst is done as a tail call. 14513 */ 14514 adrl lr, dvmAsmInstructionStart + (55 * 64) 14515 mov r0, rPC @ arg0 14516 mov r1, rSELF @ arg1 14517 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14518 14519/* ------------------------------ */ 14520 .balign 64 14521.L_ALT_OP_IF_EQZ: /* 0x38 */ 14522/* File: armv5te/alt_stub.S */ 14523/* 14524 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14525 * any interesting requests and then jump to the real instruction 14526 * handler. Note that the call to dvmCheckInst is done as a tail call. 14527 */ 14528 adrl lr, dvmAsmInstructionStart + (56 * 64) 14529 mov r0, rPC @ arg0 14530 mov r1, rSELF @ arg1 14531 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14532 14533/* ------------------------------ */ 14534 .balign 64 14535.L_ALT_OP_IF_NEZ: /* 0x39 */ 14536/* File: armv5te/alt_stub.S */ 14537/* 14538 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14539 * any interesting requests and then jump to the real instruction 14540 * handler. Note that the call to dvmCheckInst is done as a tail call. 14541 */ 14542 adrl lr, dvmAsmInstructionStart + (57 * 64) 14543 mov r0, rPC @ arg0 14544 mov r1, rSELF @ arg1 14545 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14546 14547/* ------------------------------ */ 14548 .balign 64 14549.L_ALT_OP_IF_LTZ: /* 0x3a */ 14550/* File: armv5te/alt_stub.S */ 14551/* 14552 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14553 * any interesting requests and then jump to the real instruction 14554 * handler. Note that the call to dvmCheckInst is done as a tail call. 14555 */ 14556 adrl lr, dvmAsmInstructionStart + (58 * 64) 14557 mov r0, rPC @ arg0 14558 mov r1, rSELF @ arg1 14559 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14560 14561/* ------------------------------ */ 14562 .balign 64 14563.L_ALT_OP_IF_GEZ: /* 0x3b */ 14564/* File: armv5te/alt_stub.S */ 14565/* 14566 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14567 * any interesting requests and then jump to the real instruction 14568 * handler. Note that the call to dvmCheckInst is done as a tail call. 14569 */ 14570 adrl lr, dvmAsmInstructionStart + (59 * 64) 14571 mov r0, rPC @ arg0 14572 mov r1, rSELF @ arg1 14573 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14574 14575/* ------------------------------ */ 14576 .balign 64 14577.L_ALT_OP_IF_GTZ: /* 0x3c */ 14578/* File: armv5te/alt_stub.S */ 14579/* 14580 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14581 * any interesting requests and then jump to the real instruction 14582 * handler. Note that the call to dvmCheckInst is done as a tail call. 14583 */ 14584 adrl lr, dvmAsmInstructionStart + (60 * 64) 14585 mov r0, rPC @ arg0 14586 mov r1, rSELF @ arg1 14587 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14588 14589/* ------------------------------ */ 14590 .balign 64 14591.L_ALT_OP_IF_LEZ: /* 0x3d */ 14592/* File: armv5te/alt_stub.S */ 14593/* 14594 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14595 * any interesting requests and then jump to the real instruction 14596 * handler. Note that the call to dvmCheckInst is done as a tail call. 14597 */ 14598 adrl lr, dvmAsmInstructionStart + (61 * 64) 14599 mov r0, rPC @ arg0 14600 mov r1, rSELF @ arg1 14601 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14602 14603/* ------------------------------ */ 14604 .balign 64 14605.L_ALT_OP_UNUSED_3E: /* 0x3e */ 14606/* File: armv5te/alt_stub.S */ 14607/* 14608 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14609 * any interesting requests and then jump to the real instruction 14610 * handler. Note that the call to dvmCheckInst is done as a tail call. 14611 */ 14612 adrl lr, dvmAsmInstructionStart + (62 * 64) 14613 mov r0, rPC @ arg0 14614 mov r1, rSELF @ arg1 14615 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14616 14617/* ------------------------------ */ 14618 .balign 64 14619.L_ALT_OP_UNUSED_3F: /* 0x3f */ 14620/* File: armv5te/alt_stub.S */ 14621/* 14622 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14623 * any interesting requests and then jump to the real instruction 14624 * handler. Note that the call to dvmCheckInst is done as a tail call. 14625 */ 14626 adrl lr, dvmAsmInstructionStart + (63 * 64) 14627 mov r0, rPC @ arg0 14628 mov r1, rSELF @ arg1 14629 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14630 14631/* ------------------------------ */ 14632 .balign 64 14633.L_ALT_OP_UNUSED_40: /* 0x40 */ 14634/* File: armv5te/alt_stub.S */ 14635/* 14636 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14637 * any interesting requests and then jump to the real instruction 14638 * handler. Note that the call to dvmCheckInst is done as a tail call. 14639 */ 14640 adrl lr, dvmAsmInstructionStart + (64 * 64) 14641 mov r0, rPC @ arg0 14642 mov r1, rSELF @ arg1 14643 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14644 14645/* ------------------------------ */ 14646 .balign 64 14647.L_ALT_OP_UNUSED_41: /* 0x41 */ 14648/* File: armv5te/alt_stub.S */ 14649/* 14650 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14651 * any interesting requests and then jump to the real instruction 14652 * handler. Note that the call to dvmCheckInst is done as a tail call. 14653 */ 14654 adrl lr, dvmAsmInstructionStart + (65 * 64) 14655 mov r0, rPC @ arg0 14656 mov r1, rSELF @ arg1 14657 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14658 14659/* ------------------------------ */ 14660 .balign 64 14661.L_ALT_OP_UNUSED_42: /* 0x42 */ 14662/* File: armv5te/alt_stub.S */ 14663/* 14664 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14665 * any interesting requests and then jump to the real instruction 14666 * handler. Note that the call to dvmCheckInst is done as a tail call. 14667 */ 14668 adrl lr, dvmAsmInstructionStart + (66 * 64) 14669 mov r0, rPC @ arg0 14670 mov r1, rSELF @ arg1 14671 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14672 14673/* ------------------------------ */ 14674 .balign 64 14675.L_ALT_OP_UNUSED_43: /* 0x43 */ 14676/* File: armv5te/alt_stub.S */ 14677/* 14678 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14679 * any interesting requests and then jump to the real instruction 14680 * handler. Note that the call to dvmCheckInst is done as a tail call. 14681 */ 14682 adrl lr, dvmAsmInstructionStart + (67 * 64) 14683 mov r0, rPC @ arg0 14684 mov r1, rSELF @ arg1 14685 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14686 14687/* ------------------------------ */ 14688 .balign 64 14689.L_ALT_OP_AGET: /* 0x44 */ 14690/* File: armv5te/alt_stub.S */ 14691/* 14692 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14693 * any interesting requests and then jump to the real instruction 14694 * handler. Note that the call to dvmCheckInst is done as a tail call. 14695 */ 14696 adrl lr, dvmAsmInstructionStart + (68 * 64) 14697 mov r0, rPC @ arg0 14698 mov r1, rSELF @ arg1 14699 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14700 14701/* ------------------------------ */ 14702 .balign 64 14703.L_ALT_OP_AGET_WIDE: /* 0x45 */ 14704/* File: armv5te/alt_stub.S */ 14705/* 14706 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14707 * any interesting requests and then jump to the real instruction 14708 * handler. Note that the call to dvmCheckInst is done as a tail call. 14709 */ 14710 adrl lr, dvmAsmInstructionStart + (69 * 64) 14711 mov r0, rPC @ arg0 14712 mov r1, rSELF @ arg1 14713 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14714 14715/* ------------------------------ */ 14716 .balign 64 14717.L_ALT_OP_AGET_OBJECT: /* 0x46 */ 14718/* File: armv5te/alt_stub.S */ 14719/* 14720 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14721 * any interesting requests and then jump to the real instruction 14722 * handler. Note that the call to dvmCheckInst is done as a tail call. 14723 */ 14724 adrl lr, dvmAsmInstructionStart + (70 * 64) 14725 mov r0, rPC @ arg0 14726 mov r1, rSELF @ arg1 14727 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14728 14729/* ------------------------------ */ 14730 .balign 64 14731.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */ 14732/* File: armv5te/alt_stub.S */ 14733/* 14734 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14735 * any interesting requests and then jump to the real instruction 14736 * handler. Note that the call to dvmCheckInst is done as a tail call. 14737 */ 14738 adrl lr, dvmAsmInstructionStart + (71 * 64) 14739 mov r0, rPC @ arg0 14740 mov r1, rSELF @ arg1 14741 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14742 14743/* ------------------------------ */ 14744 .balign 64 14745.L_ALT_OP_AGET_BYTE: /* 0x48 */ 14746/* File: armv5te/alt_stub.S */ 14747/* 14748 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14749 * any interesting requests and then jump to the real instruction 14750 * handler. Note that the call to dvmCheckInst is done as a tail call. 14751 */ 14752 adrl lr, dvmAsmInstructionStart + (72 * 64) 14753 mov r0, rPC @ arg0 14754 mov r1, rSELF @ arg1 14755 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14756 14757/* ------------------------------ */ 14758 .balign 64 14759.L_ALT_OP_AGET_CHAR: /* 0x49 */ 14760/* File: armv5te/alt_stub.S */ 14761/* 14762 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14763 * any interesting requests and then jump to the real instruction 14764 * handler. Note that the call to dvmCheckInst is done as a tail call. 14765 */ 14766 adrl lr, dvmAsmInstructionStart + (73 * 64) 14767 mov r0, rPC @ arg0 14768 mov r1, rSELF @ arg1 14769 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14770 14771/* ------------------------------ */ 14772 .balign 64 14773.L_ALT_OP_AGET_SHORT: /* 0x4a */ 14774/* File: armv5te/alt_stub.S */ 14775/* 14776 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14777 * any interesting requests and then jump to the real instruction 14778 * handler. Note that the call to dvmCheckInst is done as a tail call. 14779 */ 14780 adrl lr, dvmAsmInstructionStart + (74 * 64) 14781 mov r0, rPC @ arg0 14782 mov r1, rSELF @ arg1 14783 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14784 14785/* ------------------------------ */ 14786 .balign 64 14787.L_ALT_OP_APUT: /* 0x4b */ 14788/* File: armv5te/alt_stub.S */ 14789/* 14790 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14791 * any interesting requests and then jump to the real instruction 14792 * handler. Note that the call to dvmCheckInst is done as a tail call. 14793 */ 14794 adrl lr, dvmAsmInstructionStart + (75 * 64) 14795 mov r0, rPC @ arg0 14796 mov r1, rSELF @ arg1 14797 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14798 14799/* ------------------------------ */ 14800 .balign 64 14801.L_ALT_OP_APUT_WIDE: /* 0x4c */ 14802/* File: armv5te/alt_stub.S */ 14803/* 14804 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14805 * any interesting requests and then jump to the real instruction 14806 * handler. Note that the call to dvmCheckInst is done as a tail call. 14807 */ 14808 adrl lr, dvmAsmInstructionStart + (76 * 64) 14809 mov r0, rPC @ arg0 14810 mov r1, rSELF @ arg1 14811 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14812 14813/* ------------------------------ */ 14814 .balign 64 14815.L_ALT_OP_APUT_OBJECT: /* 0x4d */ 14816/* File: armv5te/alt_stub.S */ 14817/* 14818 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14819 * any interesting requests and then jump to the real instruction 14820 * handler. Note that the call to dvmCheckInst is done as a tail call. 14821 */ 14822 adrl lr, dvmAsmInstructionStart + (77 * 64) 14823 mov r0, rPC @ arg0 14824 mov r1, rSELF @ arg1 14825 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14826 14827/* ------------------------------ */ 14828 .balign 64 14829.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */ 14830/* File: armv5te/alt_stub.S */ 14831/* 14832 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14833 * any interesting requests and then jump to the real instruction 14834 * handler. Note that the call to dvmCheckInst is done as a tail call. 14835 */ 14836 adrl lr, dvmAsmInstructionStart + (78 * 64) 14837 mov r0, rPC @ arg0 14838 mov r1, rSELF @ arg1 14839 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14840 14841/* ------------------------------ */ 14842 .balign 64 14843.L_ALT_OP_APUT_BYTE: /* 0x4f */ 14844/* File: armv5te/alt_stub.S */ 14845/* 14846 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14847 * any interesting requests and then jump to the real instruction 14848 * handler. Note that the call to dvmCheckInst is done as a tail call. 14849 */ 14850 adrl lr, dvmAsmInstructionStart + (79 * 64) 14851 mov r0, rPC @ arg0 14852 mov r1, rSELF @ arg1 14853 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14854 14855/* ------------------------------ */ 14856 .balign 64 14857.L_ALT_OP_APUT_CHAR: /* 0x50 */ 14858/* File: armv5te/alt_stub.S */ 14859/* 14860 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14861 * any interesting requests and then jump to the real instruction 14862 * handler. Note that the call to dvmCheckInst is done as a tail call. 14863 */ 14864 adrl lr, dvmAsmInstructionStart + (80 * 64) 14865 mov r0, rPC @ arg0 14866 mov r1, rSELF @ arg1 14867 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14868 14869/* ------------------------------ */ 14870 .balign 64 14871.L_ALT_OP_APUT_SHORT: /* 0x51 */ 14872/* File: armv5te/alt_stub.S */ 14873/* 14874 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14875 * any interesting requests and then jump to the real instruction 14876 * handler. Note that the call to dvmCheckInst is done as a tail call. 14877 */ 14878 adrl lr, dvmAsmInstructionStart + (81 * 64) 14879 mov r0, rPC @ arg0 14880 mov r1, rSELF @ arg1 14881 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14882 14883/* ------------------------------ */ 14884 .balign 64 14885.L_ALT_OP_IGET: /* 0x52 */ 14886/* File: armv5te/alt_stub.S */ 14887/* 14888 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14889 * any interesting requests and then jump to the real instruction 14890 * handler. Note that the call to dvmCheckInst is done as a tail call. 14891 */ 14892 adrl lr, dvmAsmInstructionStart + (82 * 64) 14893 mov r0, rPC @ arg0 14894 mov r1, rSELF @ arg1 14895 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14896 14897/* ------------------------------ */ 14898 .balign 64 14899.L_ALT_OP_IGET_WIDE: /* 0x53 */ 14900/* File: armv5te/alt_stub.S */ 14901/* 14902 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14903 * any interesting requests and then jump to the real instruction 14904 * handler. Note that the call to dvmCheckInst is done as a tail call. 14905 */ 14906 adrl lr, dvmAsmInstructionStart + (83 * 64) 14907 mov r0, rPC @ arg0 14908 mov r1, rSELF @ arg1 14909 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14910 14911/* ------------------------------ */ 14912 .balign 64 14913.L_ALT_OP_IGET_OBJECT: /* 0x54 */ 14914/* File: armv5te/alt_stub.S */ 14915/* 14916 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14917 * any interesting requests and then jump to the real instruction 14918 * handler. Note that the call to dvmCheckInst is done as a tail call. 14919 */ 14920 adrl lr, dvmAsmInstructionStart + (84 * 64) 14921 mov r0, rPC @ arg0 14922 mov r1, rSELF @ arg1 14923 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14924 14925/* ------------------------------ */ 14926 .balign 64 14927.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */ 14928/* File: armv5te/alt_stub.S */ 14929/* 14930 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14931 * any interesting requests and then jump to the real instruction 14932 * handler. Note that the call to dvmCheckInst is done as a tail call. 14933 */ 14934 adrl lr, dvmAsmInstructionStart + (85 * 64) 14935 mov r0, rPC @ arg0 14936 mov r1, rSELF @ arg1 14937 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14938 14939/* ------------------------------ */ 14940 .balign 64 14941.L_ALT_OP_IGET_BYTE: /* 0x56 */ 14942/* File: armv5te/alt_stub.S */ 14943/* 14944 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14945 * any interesting requests and then jump to the real instruction 14946 * handler. Note that the call to dvmCheckInst is done as a tail call. 14947 */ 14948 adrl lr, dvmAsmInstructionStart + (86 * 64) 14949 mov r0, rPC @ arg0 14950 mov r1, rSELF @ arg1 14951 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14952 14953/* ------------------------------ */ 14954 .balign 64 14955.L_ALT_OP_IGET_CHAR: /* 0x57 */ 14956/* File: armv5te/alt_stub.S */ 14957/* 14958 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14959 * any interesting requests and then jump to the real instruction 14960 * handler. Note that the call to dvmCheckInst is done as a tail call. 14961 */ 14962 adrl lr, dvmAsmInstructionStart + (87 * 64) 14963 mov r0, rPC @ arg0 14964 mov r1, rSELF @ arg1 14965 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14966 14967/* ------------------------------ */ 14968 .balign 64 14969.L_ALT_OP_IGET_SHORT: /* 0x58 */ 14970/* File: armv5te/alt_stub.S */ 14971/* 14972 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14973 * any interesting requests and then jump to the real instruction 14974 * handler. Note that the call to dvmCheckInst is done as a tail call. 14975 */ 14976 adrl lr, dvmAsmInstructionStart + (88 * 64) 14977 mov r0, rPC @ arg0 14978 mov r1, rSELF @ arg1 14979 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14980 14981/* ------------------------------ */ 14982 .balign 64 14983.L_ALT_OP_IPUT: /* 0x59 */ 14984/* File: armv5te/alt_stub.S */ 14985/* 14986 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14987 * any interesting requests and then jump to the real instruction 14988 * handler. Note that the call to dvmCheckInst is done as a tail call. 14989 */ 14990 adrl lr, dvmAsmInstructionStart + (89 * 64) 14991 mov r0, rPC @ arg0 14992 mov r1, rSELF @ arg1 14993 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14994 14995/* ------------------------------ */ 14996 .balign 64 14997.L_ALT_OP_IPUT_WIDE: /* 0x5a */ 14998/* File: armv5te/alt_stub.S */ 14999/* 15000 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15001 * any interesting requests and then jump to the real instruction 15002 * handler. Note that the call to dvmCheckInst is done as a tail call. 15003 */ 15004 adrl lr, dvmAsmInstructionStart + (90 * 64) 15005 mov r0, rPC @ arg0 15006 mov r1, rSELF @ arg1 15007 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15008 15009/* ------------------------------ */ 15010 .balign 64 15011.L_ALT_OP_IPUT_OBJECT: /* 0x5b */ 15012/* File: armv5te/alt_stub.S */ 15013/* 15014 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15015 * any interesting requests and then jump to the real instruction 15016 * handler. Note that the call to dvmCheckInst is done as a tail call. 15017 */ 15018 adrl lr, dvmAsmInstructionStart + (91 * 64) 15019 mov r0, rPC @ arg0 15020 mov r1, rSELF @ arg1 15021 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15022 15023/* ------------------------------ */ 15024 .balign 64 15025.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */ 15026/* File: armv5te/alt_stub.S */ 15027/* 15028 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15029 * any interesting requests and then jump to the real instruction 15030 * handler. Note that the call to dvmCheckInst is done as a tail call. 15031 */ 15032 adrl lr, dvmAsmInstructionStart + (92 * 64) 15033 mov r0, rPC @ arg0 15034 mov r1, rSELF @ arg1 15035 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15036 15037/* ------------------------------ */ 15038 .balign 64 15039.L_ALT_OP_IPUT_BYTE: /* 0x5d */ 15040/* File: armv5te/alt_stub.S */ 15041/* 15042 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15043 * any interesting requests and then jump to the real instruction 15044 * handler. Note that the call to dvmCheckInst is done as a tail call. 15045 */ 15046 adrl lr, dvmAsmInstructionStart + (93 * 64) 15047 mov r0, rPC @ arg0 15048 mov r1, rSELF @ arg1 15049 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15050 15051/* ------------------------------ */ 15052 .balign 64 15053.L_ALT_OP_IPUT_CHAR: /* 0x5e */ 15054/* File: armv5te/alt_stub.S */ 15055/* 15056 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15057 * any interesting requests and then jump to the real instruction 15058 * handler. Note that the call to dvmCheckInst is done as a tail call. 15059 */ 15060 adrl lr, dvmAsmInstructionStart + (94 * 64) 15061 mov r0, rPC @ arg0 15062 mov r1, rSELF @ arg1 15063 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15064 15065/* ------------------------------ */ 15066 .balign 64 15067.L_ALT_OP_IPUT_SHORT: /* 0x5f */ 15068/* File: armv5te/alt_stub.S */ 15069/* 15070 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15071 * any interesting requests and then jump to the real instruction 15072 * handler. Note that the call to dvmCheckInst is done as a tail call. 15073 */ 15074 adrl lr, dvmAsmInstructionStart + (95 * 64) 15075 mov r0, rPC @ arg0 15076 mov r1, rSELF @ arg1 15077 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15078 15079/* ------------------------------ */ 15080 .balign 64 15081.L_ALT_OP_SGET: /* 0x60 */ 15082/* File: armv5te/alt_stub.S */ 15083/* 15084 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15085 * any interesting requests and then jump to the real instruction 15086 * handler. Note that the call to dvmCheckInst is done as a tail call. 15087 */ 15088 adrl lr, dvmAsmInstructionStart + (96 * 64) 15089 mov r0, rPC @ arg0 15090 mov r1, rSELF @ arg1 15091 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15092 15093/* ------------------------------ */ 15094 .balign 64 15095.L_ALT_OP_SGET_WIDE: /* 0x61 */ 15096/* File: armv5te/alt_stub.S */ 15097/* 15098 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15099 * any interesting requests and then jump to the real instruction 15100 * handler. Note that the call to dvmCheckInst is done as a tail call. 15101 */ 15102 adrl lr, dvmAsmInstructionStart + (97 * 64) 15103 mov r0, rPC @ arg0 15104 mov r1, rSELF @ arg1 15105 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15106 15107/* ------------------------------ */ 15108 .balign 64 15109.L_ALT_OP_SGET_OBJECT: /* 0x62 */ 15110/* File: armv5te/alt_stub.S */ 15111/* 15112 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15113 * any interesting requests and then jump to the real instruction 15114 * handler. Note that the call to dvmCheckInst is done as a tail call. 15115 */ 15116 adrl lr, dvmAsmInstructionStart + (98 * 64) 15117 mov r0, rPC @ arg0 15118 mov r1, rSELF @ arg1 15119 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15120 15121/* ------------------------------ */ 15122 .balign 64 15123.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */ 15124/* File: armv5te/alt_stub.S */ 15125/* 15126 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15127 * any interesting requests and then jump to the real instruction 15128 * handler. Note that the call to dvmCheckInst is done as a tail call. 15129 */ 15130 adrl lr, dvmAsmInstructionStart + (99 * 64) 15131 mov r0, rPC @ arg0 15132 mov r1, rSELF @ arg1 15133 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15134 15135/* ------------------------------ */ 15136 .balign 64 15137.L_ALT_OP_SGET_BYTE: /* 0x64 */ 15138/* File: armv5te/alt_stub.S */ 15139/* 15140 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15141 * any interesting requests and then jump to the real instruction 15142 * handler. Note that the call to dvmCheckInst is done as a tail call. 15143 */ 15144 adrl lr, dvmAsmInstructionStart + (100 * 64) 15145 mov r0, rPC @ arg0 15146 mov r1, rSELF @ arg1 15147 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15148 15149/* ------------------------------ */ 15150 .balign 64 15151.L_ALT_OP_SGET_CHAR: /* 0x65 */ 15152/* File: armv5te/alt_stub.S */ 15153/* 15154 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15155 * any interesting requests and then jump to the real instruction 15156 * handler. Note that the call to dvmCheckInst is done as a tail call. 15157 */ 15158 adrl lr, dvmAsmInstructionStart + (101 * 64) 15159 mov r0, rPC @ arg0 15160 mov r1, rSELF @ arg1 15161 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15162 15163/* ------------------------------ */ 15164 .balign 64 15165.L_ALT_OP_SGET_SHORT: /* 0x66 */ 15166/* File: armv5te/alt_stub.S */ 15167/* 15168 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15169 * any interesting requests and then jump to the real instruction 15170 * handler. Note that the call to dvmCheckInst is done as a tail call. 15171 */ 15172 adrl lr, dvmAsmInstructionStart + (102 * 64) 15173 mov r0, rPC @ arg0 15174 mov r1, rSELF @ arg1 15175 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15176 15177/* ------------------------------ */ 15178 .balign 64 15179.L_ALT_OP_SPUT: /* 0x67 */ 15180/* File: armv5te/alt_stub.S */ 15181/* 15182 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15183 * any interesting requests and then jump to the real instruction 15184 * handler. Note that the call to dvmCheckInst is done as a tail call. 15185 */ 15186 adrl lr, dvmAsmInstructionStart + (103 * 64) 15187 mov r0, rPC @ arg0 15188 mov r1, rSELF @ arg1 15189 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15190 15191/* ------------------------------ */ 15192 .balign 64 15193.L_ALT_OP_SPUT_WIDE: /* 0x68 */ 15194/* File: armv5te/alt_stub.S */ 15195/* 15196 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15197 * any interesting requests and then jump to the real instruction 15198 * handler. Note that the call to dvmCheckInst is done as a tail call. 15199 */ 15200 adrl lr, dvmAsmInstructionStart + (104 * 64) 15201 mov r0, rPC @ arg0 15202 mov r1, rSELF @ arg1 15203 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15204 15205/* ------------------------------ */ 15206 .balign 64 15207.L_ALT_OP_SPUT_OBJECT: /* 0x69 */ 15208/* File: armv5te/alt_stub.S */ 15209/* 15210 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15211 * any interesting requests and then jump to the real instruction 15212 * handler. Note that the call to dvmCheckInst is done as a tail call. 15213 */ 15214 adrl lr, dvmAsmInstructionStart + (105 * 64) 15215 mov r0, rPC @ arg0 15216 mov r1, rSELF @ arg1 15217 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15218 15219/* ------------------------------ */ 15220 .balign 64 15221.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */ 15222/* File: armv5te/alt_stub.S */ 15223/* 15224 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15225 * any interesting requests and then jump to the real instruction 15226 * handler. Note that the call to dvmCheckInst is done as a tail call. 15227 */ 15228 adrl lr, dvmAsmInstructionStart + (106 * 64) 15229 mov r0, rPC @ arg0 15230 mov r1, rSELF @ arg1 15231 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15232 15233/* ------------------------------ */ 15234 .balign 64 15235.L_ALT_OP_SPUT_BYTE: /* 0x6b */ 15236/* File: armv5te/alt_stub.S */ 15237/* 15238 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15239 * any interesting requests and then jump to the real instruction 15240 * handler. Note that the call to dvmCheckInst is done as a tail call. 15241 */ 15242 adrl lr, dvmAsmInstructionStart + (107 * 64) 15243 mov r0, rPC @ arg0 15244 mov r1, rSELF @ arg1 15245 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15246 15247/* ------------------------------ */ 15248 .balign 64 15249.L_ALT_OP_SPUT_CHAR: /* 0x6c */ 15250/* File: armv5te/alt_stub.S */ 15251/* 15252 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15253 * any interesting requests and then jump to the real instruction 15254 * handler. Note that the call to dvmCheckInst is done as a tail call. 15255 */ 15256 adrl lr, dvmAsmInstructionStart + (108 * 64) 15257 mov r0, rPC @ arg0 15258 mov r1, rSELF @ arg1 15259 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15260 15261/* ------------------------------ */ 15262 .balign 64 15263.L_ALT_OP_SPUT_SHORT: /* 0x6d */ 15264/* File: armv5te/alt_stub.S */ 15265/* 15266 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15267 * any interesting requests and then jump to the real instruction 15268 * handler. Note that the call to dvmCheckInst is done as a tail call. 15269 */ 15270 adrl lr, dvmAsmInstructionStart + (109 * 64) 15271 mov r0, rPC @ arg0 15272 mov r1, rSELF @ arg1 15273 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15274 15275/* ------------------------------ */ 15276 .balign 64 15277.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */ 15278/* File: armv5te/alt_stub.S */ 15279/* 15280 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15281 * any interesting requests and then jump to the real instruction 15282 * handler. Note that the call to dvmCheckInst is done as a tail call. 15283 */ 15284 adrl lr, dvmAsmInstructionStart + (110 * 64) 15285 mov r0, rPC @ arg0 15286 mov r1, rSELF @ arg1 15287 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15288 15289/* ------------------------------ */ 15290 .balign 64 15291.L_ALT_OP_INVOKE_SUPER: /* 0x6f */ 15292/* File: armv5te/alt_stub.S */ 15293/* 15294 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15295 * any interesting requests and then jump to the real instruction 15296 * handler. Note that the call to dvmCheckInst is done as a tail call. 15297 */ 15298 adrl lr, dvmAsmInstructionStart + (111 * 64) 15299 mov r0, rPC @ arg0 15300 mov r1, rSELF @ arg1 15301 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15302 15303/* ------------------------------ */ 15304 .balign 64 15305.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */ 15306/* File: armv5te/alt_stub.S */ 15307/* 15308 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15309 * any interesting requests and then jump to the real instruction 15310 * handler. Note that the call to dvmCheckInst is done as a tail call. 15311 */ 15312 adrl lr, dvmAsmInstructionStart + (112 * 64) 15313 mov r0, rPC @ arg0 15314 mov r1, rSELF @ arg1 15315 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15316 15317/* ------------------------------ */ 15318 .balign 64 15319.L_ALT_OP_INVOKE_STATIC: /* 0x71 */ 15320/* File: armv5te/alt_stub.S */ 15321/* 15322 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15323 * any interesting requests and then jump to the real instruction 15324 * handler. Note that the call to dvmCheckInst is done as a tail call. 15325 */ 15326 adrl lr, dvmAsmInstructionStart + (113 * 64) 15327 mov r0, rPC @ arg0 15328 mov r1, rSELF @ arg1 15329 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15330 15331/* ------------------------------ */ 15332 .balign 64 15333.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */ 15334/* File: armv5te/alt_stub.S */ 15335/* 15336 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15337 * any interesting requests and then jump to the real instruction 15338 * handler. Note that the call to dvmCheckInst is done as a tail call. 15339 */ 15340 adrl lr, dvmAsmInstructionStart + (114 * 64) 15341 mov r0, rPC @ arg0 15342 mov r1, rSELF @ arg1 15343 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15344 15345/* ------------------------------ */ 15346 .balign 64 15347.L_ALT_OP_UNUSED_73: /* 0x73 */ 15348/* File: armv5te/alt_stub.S */ 15349/* 15350 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15351 * any interesting requests and then jump to the real instruction 15352 * handler. Note that the call to dvmCheckInst is done as a tail call. 15353 */ 15354 adrl lr, dvmAsmInstructionStart + (115 * 64) 15355 mov r0, rPC @ arg0 15356 mov r1, rSELF @ arg1 15357 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15358 15359/* ------------------------------ */ 15360 .balign 64 15361.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 15362/* File: armv5te/alt_stub.S */ 15363/* 15364 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15365 * any interesting requests and then jump to the real instruction 15366 * handler. Note that the call to dvmCheckInst is done as a tail call. 15367 */ 15368 adrl lr, dvmAsmInstructionStart + (116 * 64) 15369 mov r0, rPC @ arg0 15370 mov r1, rSELF @ arg1 15371 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15372 15373/* ------------------------------ */ 15374 .balign 64 15375.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 15376/* File: armv5te/alt_stub.S */ 15377/* 15378 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15379 * any interesting requests and then jump to the real instruction 15380 * handler. Note that the call to dvmCheckInst is done as a tail call. 15381 */ 15382 adrl lr, dvmAsmInstructionStart + (117 * 64) 15383 mov r0, rPC @ arg0 15384 mov r1, rSELF @ arg1 15385 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15386 15387/* ------------------------------ */ 15388 .balign 64 15389.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 15390/* File: armv5te/alt_stub.S */ 15391/* 15392 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15393 * any interesting requests and then jump to the real instruction 15394 * handler. Note that the call to dvmCheckInst is done as a tail call. 15395 */ 15396 adrl lr, dvmAsmInstructionStart + (118 * 64) 15397 mov r0, rPC @ arg0 15398 mov r1, rSELF @ arg1 15399 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15400 15401/* ------------------------------ */ 15402 .balign 64 15403.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 15404/* File: armv5te/alt_stub.S */ 15405/* 15406 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15407 * any interesting requests and then jump to the real instruction 15408 * handler. Note that the call to dvmCheckInst is done as a tail call. 15409 */ 15410 adrl lr, dvmAsmInstructionStart + (119 * 64) 15411 mov r0, rPC @ arg0 15412 mov r1, rSELF @ arg1 15413 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15414 15415/* ------------------------------ */ 15416 .balign 64 15417.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 15418/* File: armv5te/alt_stub.S */ 15419/* 15420 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15421 * any interesting requests and then jump to the real instruction 15422 * handler. Note that the call to dvmCheckInst is done as a tail call. 15423 */ 15424 adrl lr, dvmAsmInstructionStart + (120 * 64) 15425 mov r0, rPC @ arg0 15426 mov r1, rSELF @ arg1 15427 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15428 15429/* ------------------------------ */ 15430 .balign 64 15431.L_ALT_OP_UNUSED_79: /* 0x79 */ 15432/* File: armv5te/alt_stub.S */ 15433/* 15434 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15435 * any interesting requests and then jump to the real instruction 15436 * handler. Note that the call to dvmCheckInst is done as a tail call. 15437 */ 15438 adrl lr, dvmAsmInstructionStart + (121 * 64) 15439 mov r0, rPC @ arg0 15440 mov r1, rSELF @ arg1 15441 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15442 15443/* ------------------------------ */ 15444 .balign 64 15445.L_ALT_OP_UNUSED_7A: /* 0x7a */ 15446/* File: armv5te/alt_stub.S */ 15447/* 15448 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15449 * any interesting requests and then jump to the real instruction 15450 * handler. Note that the call to dvmCheckInst is done as a tail call. 15451 */ 15452 adrl lr, dvmAsmInstructionStart + (122 * 64) 15453 mov r0, rPC @ arg0 15454 mov r1, rSELF @ arg1 15455 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15456 15457/* ------------------------------ */ 15458 .balign 64 15459.L_ALT_OP_NEG_INT: /* 0x7b */ 15460/* File: armv5te/alt_stub.S */ 15461/* 15462 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15463 * any interesting requests and then jump to the real instruction 15464 * handler. Note that the call to dvmCheckInst is done as a tail call. 15465 */ 15466 adrl lr, dvmAsmInstructionStart + (123 * 64) 15467 mov r0, rPC @ arg0 15468 mov r1, rSELF @ arg1 15469 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15470 15471/* ------------------------------ */ 15472 .balign 64 15473.L_ALT_OP_NOT_INT: /* 0x7c */ 15474/* File: armv5te/alt_stub.S */ 15475/* 15476 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15477 * any interesting requests and then jump to the real instruction 15478 * handler. Note that the call to dvmCheckInst is done as a tail call. 15479 */ 15480 adrl lr, dvmAsmInstructionStart + (124 * 64) 15481 mov r0, rPC @ arg0 15482 mov r1, rSELF @ arg1 15483 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15484 15485/* ------------------------------ */ 15486 .balign 64 15487.L_ALT_OP_NEG_LONG: /* 0x7d */ 15488/* File: armv5te/alt_stub.S */ 15489/* 15490 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15491 * any interesting requests and then jump to the real instruction 15492 * handler. Note that the call to dvmCheckInst is done as a tail call. 15493 */ 15494 adrl lr, dvmAsmInstructionStart + (125 * 64) 15495 mov r0, rPC @ arg0 15496 mov r1, rSELF @ arg1 15497 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15498 15499/* ------------------------------ */ 15500 .balign 64 15501.L_ALT_OP_NOT_LONG: /* 0x7e */ 15502/* File: armv5te/alt_stub.S */ 15503/* 15504 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15505 * any interesting requests and then jump to the real instruction 15506 * handler. Note that the call to dvmCheckInst is done as a tail call. 15507 */ 15508 adrl lr, dvmAsmInstructionStart + (126 * 64) 15509 mov r0, rPC @ arg0 15510 mov r1, rSELF @ arg1 15511 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15512 15513/* ------------------------------ */ 15514 .balign 64 15515.L_ALT_OP_NEG_FLOAT: /* 0x7f */ 15516/* File: armv5te/alt_stub.S */ 15517/* 15518 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15519 * any interesting requests and then jump to the real instruction 15520 * handler. Note that the call to dvmCheckInst is done as a tail call. 15521 */ 15522 adrl lr, dvmAsmInstructionStart + (127 * 64) 15523 mov r0, rPC @ arg0 15524 mov r1, rSELF @ arg1 15525 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15526 15527/* ------------------------------ */ 15528 .balign 64 15529.L_ALT_OP_NEG_DOUBLE: /* 0x80 */ 15530/* File: armv5te/alt_stub.S */ 15531/* 15532 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15533 * any interesting requests and then jump to the real instruction 15534 * handler. Note that the call to dvmCheckInst is done as a tail call. 15535 */ 15536 adrl lr, dvmAsmInstructionStart + (128 * 64) 15537 mov r0, rPC @ arg0 15538 mov r1, rSELF @ arg1 15539 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15540 15541/* ------------------------------ */ 15542 .balign 64 15543.L_ALT_OP_INT_TO_LONG: /* 0x81 */ 15544/* File: armv5te/alt_stub.S */ 15545/* 15546 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15547 * any interesting requests and then jump to the real instruction 15548 * handler. Note that the call to dvmCheckInst is done as a tail call. 15549 */ 15550 adrl lr, dvmAsmInstructionStart + (129 * 64) 15551 mov r0, rPC @ arg0 15552 mov r1, rSELF @ arg1 15553 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15554 15555/* ------------------------------ */ 15556 .balign 64 15557.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */ 15558/* File: armv5te/alt_stub.S */ 15559/* 15560 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15561 * any interesting requests and then jump to the real instruction 15562 * handler. Note that the call to dvmCheckInst is done as a tail call. 15563 */ 15564 adrl lr, dvmAsmInstructionStart + (130 * 64) 15565 mov r0, rPC @ arg0 15566 mov r1, rSELF @ arg1 15567 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15568 15569/* ------------------------------ */ 15570 .balign 64 15571.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */ 15572/* File: armv5te/alt_stub.S */ 15573/* 15574 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15575 * any interesting requests and then jump to the real instruction 15576 * handler. Note that the call to dvmCheckInst is done as a tail call. 15577 */ 15578 adrl lr, dvmAsmInstructionStart + (131 * 64) 15579 mov r0, rPC @ arg0 15580 mov r1, rSELF @ arg1 15581 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15582 15583/* ------------------------------ */ 15584 .balign 64 15585.L_ALT_OP_LONG_TO_INT: /* 0x84 */ 15586/* File: armv5te/alt_stub.S */ 15587/* 15588 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15589 * any interesting requests and then jump to the real instruction 15590 * handler. Note that the call to dvmCheckInst is done as a tail call. 15591 */ 15592 adrl lr, dvmAsmInstructionStart + (132 * 64) 15593 mov r0, rPC @ arg0 15594 mov r1, rSELF @ arg1 15595 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15596 15597/* ------------------------------ */ 15598 .balign 64 15599.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */ 15600/* File: armv5te/alt_stub.S */ 15601/* 15602 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15603 * any interesting requests and then jump to the real instruction 15604 * handler. Note that the call to dvmCheckInst is done as a tail call. 15605 */ 15606 adrl lr, dvmAsmInstructionStart + (133 * 64) 15607 mov r0, rPC @ arg0 15608 mov r1, rSELF @ arg1 15609 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15610 15611/* ------------------------------ */ 15612 .balign 64 15613.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */ 15614/* File: armv5te/alt_stub.S */ 15615/* 15616 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15617 * any interesting requests and then jump to the real instruction 15618 * handler. Note that the call to dvmCheckInst is done as a tail call. 15619 */ 15620 adrl lr, dvmAsmInstructionStart + (134 * 64) 15621 mov r0, rPC @ arg0 15622 mov r1, rSELF @ arg1 15623 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15624 15625/* ------------------------------ */ 15626 .balign 64 15627.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */ 15628/* File: armv5te/alt_stub.S */ 15629/* 15630 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15631 * any interesting requests and then jump to the real instruction 15632 * handler. Note that the call to dvmCheckInst is done as a tail call. 15633 */ 15634 adrl lr, dvmAsmInstructionStart + (135 * 64) 15635 mov r0, rPC @ arg0 15636 mov r1, rSELF @ arg1 15637 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15638 15639/* ------------------------------ */ 15640 .balign 64 15641.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */ 15642/* File: armv5te/alt_stub.S */ 15643/* 15644 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15645 * any interesting requests and then jump to the real instruction 15646 * handler. Note that the call to dvmCheckInst is done as a tail call. 15647 */ 15648 adrl lr, dvmAsmInstructionStart + (136 * 64) 15649 mov r0, rPC @ arg0 15650 mov r1, rSELF @ arg1 15651 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15652 15653/* ------------------------------ */ 15654 .balign 64 15655.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 15656/* File: armv5te/alt_stub.S */ 15657/* 15658 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15659 * any interesting requests and then jump to the real instruction 15660 * handler. Note that the call to dvmCheckInst is done as a tail call. 15661 */ 15662 adrl lr, dvmAsmInstructionStart + (137 * 64) 15663 mov r0, rPC @ arg0 15664 mov r1, rSELF @ arg1 15665 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15666 15667/* ------------------------------ */ 15668 .balign 64 15669.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */ 15670/* File: armv5te/alt_stub.S */ 15671/* 15672 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15673 * any interesting requests and then jump to the real instruction 15674 * handler. Note that the call to dvmCheckInst is done as a tail call. 15675 */ 15676 adrl lr, dvmAsmInstructionStart + (138 * 64) 15677 mov r0, rPC @ arg0 15678 mov r1, rSELF @ arg1 15679 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15680 15681/* ------------------------------ */ 15682 .balign 64 15683.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */ 15684/* File: armv5te/alt_stub.S */ 15685/* 15686 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15687 * any interesting requests and then jump to the real instruction 15688 * handler. Note that the call to dvmCheckInst is done as a tail call. 15689 */ 15690 adrl lr, dvmAsmInstructionStart + (139 * 64) 15691 mov r0, rPC @ arg0 15692 mov r1, rSELF @ arg1 15693 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15694 15695/* ------------------------------ */ 15696 .balign 64 15697.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 15698/* File: armv5te/alt_stub.S */ 15699/* 15700 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15701 * any interesting requests and then jump to the real instruction 15702 * handler. Note that the call to dvmCheckInst is done as a tail call. 15703 */ 15704 adrl lr, dvmAsmInstructionStart + (140 * 64) 15705 mov r0, rPC @ arg0 15706 mov r1, rSELF @ arg1 15707 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15708 15709/* ------------------------------ */ 15710 .balign 64 15711.L_ALT_OP_INT_TO_BYTE: /* 0x8d */ 15712/* File: armv5te/alt_stub.S */ 15713/* 15714 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15715 * any interesting requests and then jump to the real instruction 15716 * handler. Note that the call to dvmCheckInst is done as a tail call. 15717 */ 15718 adrl lr, dvmAsmInstructionStart + (141 * 64) 15719 mov r0, rPC @ arg0 15720 mov r1, rSELF @ arg1 15721 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15722 15723/* ------------------------------ */ 15724 .balign 64 15725.L_ALT_OP_INT_TO_CHAR: /* 0x8e */ 15726/* File: armv5te/alt_stub.S */ 15727/* 15728 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15729 * any interesting requests and then jump to the real instruction 15730 * handler. Note that the call to dvmCheckInst is done as a tail call. 15731 */ 15732 adrl lr, dvmAsmInstructionStart + (142 * 64) 15733 mov r0, rPC @ arg0 15734 mov r1, rSELF @ arg1 15735 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15736 15737/* ------------------------------ */ 15738 .balign 64 15739.L_ALT_OP_INT_TO_SHORT: /* 0x8f */ 15740/* File: armv5te/alt_stub.S */ 15741/* 15742 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15743 * any interesting requests and then jump to the real instruction 15744 * handler. Note that the call to dvmCheckInst is done as a tail call. 15745 */ 15746 adrl lr, dvmAsmInstructionStart + (143 * 64) 15747 mov r0, rPC @ arg0 15748 mov r1, rSELF @ arg1 15749 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15750 15751/* ------------------------------ */ 15752 .balign 64 15753.L_ALT_OP_ADD_INT: /* 0x90 */ 15754/* File: armv5te/alt_stub.S */ 15755/* 15756 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15757 * any interesting requests and then jump to the real instruction 15758 * handler. Note that the call to dvmCheckInst is done as a tail call. 15759 */ 15760 adrl lr, dvmAsmInstructionStart + (144 * 64) 15761 mov r0, rPC @ arg0 15762 mov r1, rSELF @ arg1 15763 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15764 15765/* ------------------------------ */ 15766 .balign 64 15767.L_ALT_OP_SUB_INT: /* 0x91 */ 15768/* File: armv5te/alt_stub.S */ 15769/* 15770 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15771 * any interesting requests and then jump to the real instruction 15772 * handler. Note that the call to dvmCheckInst is done as a tail call. 15773 */ 15774 adrl lr, dvmAsmInstructionStart + (145 * 64) 15775 mov r0, rPC @ arg0 15776 mov r1, rSELF @ arg1 15777 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15778 15779/* ------------------------------ */ 15780 .balign 64 15781.L_ALT_OP_MUL_INT: /* 0x92 */ 15782/* File: armv5te/alt_stub.S */ 15783/* 15784 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15785 * any interesting requests and then jump to the real instruction 15786 * handler. Note that the call to dvmCheckInst is done as a tail call. 15787 */ 15788 adrl lr, dvmAsmInstructionStart + (146 * 64) 15789 mov r0, rPC @ arg0 15790 mov r1, rSELF @ arg1 15791 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15792 15793/* ------------------------------ */ 15794 .balign 64 15795.L_ALT_OP_DIV_INT: /* 0x93 */ 15796/* File: armv5te/alt_stub.S */ 15797/* 15798 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15799 * any interesting requests and then jump to the real instruction 15800 * handler. Note that the call to dvmCheckInst is done as a tail call. 15801 */ 15802 adrl lr, dvmAsmInstructionStart + (147 * 64) 15803 mov r0, rPC @ arg0 15804 mov r1, rSELF @ arg1 15805 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15806 15807/* ------------------------------ */ 15808 .balign 64 15809.L_ALT_OP_REM_INT: /* 0x94 */ 15810/* File: armv5te/alt_stub.S */ 15811/* 15812 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15813 * any interesting requests and then jump to the real instruction 15814 * handler. Note that the call to dvmCheckInst is done as a tail call. 15815 */ 15816 adrl lr, dvmAsmInstructionStart + (148 * 64) 15817 mov r0, rPC @ arg0 15818 mov r1, rSELF @ arg1 15819 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15820 15821/* ------------------------------ */ 15822 .balign 64 15823.L_ALT_OP_AND_INT: /* 0x95 */ 15824/* File: armv5te/alt_stub.S */ 15825/* 15826 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15827 * any interesting requests and then jump to the real instruction 15828 * handler. Note that the call to dvmCheckInst is done as a tail call. 15829 */ 15830 adrl lr, dvmAsmInstructionStart + (149 * 64) 15831 mov r0, rPC @ arg0 15832 mov r1, rSELF @ arg1 15833 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15834 15835/* ------------------------------ */ 15836 .balign 64 15837.L_ALT_OP_OR_INT: /* 0x96 */ 15838/* File: armv5te/alt_stub.S */ 15839/* 15840 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15841 * any interesting requests and then jump to the real instruction 15842 * handler. Note that the call to dvmCheckInst is done as a tail call. 15843 */ 15844 adrl lr, dvmAsmInstructionStart + (150 * 64) 15845 mov r0, rPC @ arg0 15846 mov r1, rSELF @ arg1 15847 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15848 15849/* ------------------------------ */ 15850 .balign 64 15851.L_ALT_OP_XOR_INT: /* 0x97 */ 15852/* File: armv5te/alt_stub.S */ 15853/* 15854 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15855 * any interesting requests and then jump to the real instruction 15856 * handler. Note that the call to dvmCheckInst is done as a tail call. 15857 */ 15858 adrl lr, dvmAsmInstructionStart + (151 * 64) 15859 mov r0, rPC @ arg0 15860 mov r1, rSELF @ arg1 15861 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15862 15863/* ------------------------------ */ 15864 .balign 64 15865.L_ALT_OP_SHL_INT: /* 0x98 */ 15866/* File: armv5te/alt_stub.S */ 15867/* 15868 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15869 * any interesting requests and then jump to the real instruction 15870 * handler. Note that the call to dvmCheckInst is done as a tail call. 15871 */ 15872 adrl lr, dvmAsmInstructionStart + (152 * 64) 15873 mov r0, rPC @ arg0 15874 mov r1, rSELF @ arg1 15875 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15876 15877/* ------------------------------ */ 15878 .balign 64 15879.L_ALT_OP_SHR_INT: /* 0x99 */ 15880/* File: armv5te/alt_stub.S */ 15881/* 15882 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15883 * any interesting requests and then jump to the real instruction 15884 * handler. Note that the call to dvmCheckInst is done as a tail call. 15885 */ 15886 adrl lr, dvmAsmInstructionStart + (153 * 64) 15887 mov r0, rPC @ arg0 15888 mov r1, rSELF @ arg1 15889 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15890 15891/* ------------------------------ */ 15892 .balign 64 15893.L_ALT_OP_USHR_INT: /* 0x9a */ 15894/* File: armv5te/alt_stub.S */ 15895/* 15896 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15897 * any interesting requests and then jump to the real instruction 15898 * handler. Note that the call to dvmCheckInst is done as a tail call. 15899 */ 15900 adrl lr, dvmAsmInstructionStart + (154 * 64) 15901 mov r0, rPC @ arg0 15902 mov r1, rSELF @ arg1 15903 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15904 15905/* ------------------------------ */ 15906 .balign 64 15907.L_ALT_OP_ADD_LONG: /* 0x9b */ 15908/* File: armv5te/alt_stub.S */ 15909/* 15910 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15911 * any interesting requests and then jump to the real instruction 15912 * handler. Note that the call to dvmCheckInst is done as a tail call. 15913 */ 15914 adrl lr, dvmAsmInstructionStart + (155 * 64) 15915 mov r0, rPC @ arg0 15916 mov r1, rSELF @ arg1 15917 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15918 15919/* ------------------------------ */ 15920 .balign 64 15921.L_ALT_OP_SUB_LONG: /* 0x9c */ 15922/* File: armv5te/alt_stub.S */ 15923/* 15924 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15925 * any interesting requests and then jump to the real instruction 15926 * handler. Note that the call to dvmCheckInst is done as a tail call. 15927 */ 15928 adrl lr, dvmAsmInstructionStart + (156 * 64) 15929 mov r0, rPC @ arg0 15930 mov r1, rSELF @ arg1 15931 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15932 15933/* ------------------------------ */ 15934 .balign 64 15935.L_ALT_OP_MUL_LONG: /* 0x9d */ 15936/* File: armv5te/alt_stub.S */ 15937/* 15938 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15939 * any interesting requests and then jump to the real instruction 15940 * handler. Note that the call to dvmCheckInst is done as a tail call. 15941 */ 15942 adrl lr, dvmAsmInstructionStart + (157 * 64) 15943 mov r0, rPC @ arg0 15944 mov r1, rSELF @ arg1 15945 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15946 15947/* ------------------------------ */ 15948 .balign 64 15949.L_ALT_OP_DIV_LONG: /* 0x9e */ 15950/* File: armv5te/alt_stub.S */ 15951/* 15952 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15953 * any interesting requests and then jump to the real instruction 15954 * handler. Note that the call to dvmCheckInst is done as a tail call. 15955 */ 15956 adrl lr, dvmAsmInstructionStart + (158 * 64) 15957 mov r0, rPC @ arg0 15958 mov r1, rSELF @ arg1 15959 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15960 15961/* ------------------------------ */ 15962 .balign 64 15963.L_ALT_OP_REM_LONG: /* 0x9f */ 15964/* File: armv5te/alt_stub.S */ 15965/* 15966 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15967 * any interesting requests and then jump to the real instruction 15968 * handler. Note that the call to dvmCheckInst is done as a tail call. 15969 */ 15970 adrl lr, dvmAsmInstructionStart + (159 * 64) 15971 mov r0, rPC @ arg0 15972 mov r1, rSELF @ arg1 15973 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15974 15975/* ------------------------------ */ 15976 .balign 64 15977.L_ALT_OP_AND_LONG: /* 0xa0 */ 15978/* File: armv5te/alt_stub.S */ 15979/* 15980 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15981 * any interesting requests and then jump to the real instruction 15982 * handler. Note that the call to dvmCheckInst is done as a tail call. 15983 */ 15984 adrl lr, dvmAsmInstructionStart + (160 * 64) 15985 mov r0, rPC @ arg0 15986 mov r1, rSELF @ arg1 15987 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15988 15989/* ------------------------------ */ 15990 .balign 64 15991.L_ALT_OP_OR_LONG: /* 0xa1 */ 15992/* File: armv5te/alt_stub.S */ 15993/* 15994 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15995 * any interesting requests and then jump to the real instruction 15996 * handler. Note that the call to dvmCheckInst is done as a tail call. 15997 */ 15998 adrl lr, dvmAsmInstructionStart + (161 * 64) 15999 mov r0, rPC @ arg0 16000 mov r1, rSELF @ arg1 16001 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16002 16003/* ------------------------------ */ 16004 .balign 64 16005.L_ALT_OP_XOR_LONG: /* 0xa2 */ 16006/* File: armv5te/alt_stub.S */ 16007/* 16008 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16009 * any interesting requests and then jump to the real instruction 16010 * handler. Note that the call to dvmCheckInst is done as a tail call. 16011 */ 16012 adrl lr, dvmAsmInstructionStart + (162 * 64) 16013 mov r0, rPC @ arg0 16014 mov r1, rSELF @ arg1 16015 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16016 16017/* ------------------------------ */ 16018 .balign 64 16019.L_ALT_OP_SHL_LONG: /* 0xa3 */ 16020/* File: armv5te/alt_stub.S */ 16021/* 16022 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16023 * any interesting requests and then jump to the real instruction 16024 * handler. Note that the call to dvmCheckInst is done as a tail call. 16025 */ 16026 adrl lr, dvmAsmInstructionStart + (163 * 64) 16027 mov r0, rPC @ arg0 16028 mov r1, rSELF @ arg1 16029 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16030 16031/* ------------------------------ */ 16032 .balign 64 16033.L_ALT_OP_SHR_LONG: /* 0xa4 */ 16034/* File: armv5te/alt_stub.S */ 16035/* 16036 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16037 * any interesting requests and then jump to the real instruction 16038 * handler. Note that the call to dvmCheckInst is done as a tail call. 16039 */ 16040 adrl lr, dvmAsmInstructionStart + (164 * 64) 16041 mov r0, rPC @ arg0 16042 mov r1, rSELF @ arg1 16043 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16044 16045/* ------------------------------ */ 16046 .balign 64 16047.L_ALT_OP_USHR_LONG: /* 0xa5 */ 16048/* File: armv5te/alt_stub.S */ 16049/* 16050 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16051 * any interesting requests and then jump to the real instruction 16052 * handler. Note that the call to dvmCheckInst is done as a tail call. 16053 */ 16054 adrl lr, dvmAsmInstructionStart + (165 * 64) 16055 mov r0, rPC @ arg0 16056 mov r1, rSELF @ arg1 16057 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16058 16059/* ------------------------------ */ 16060 .balign 64 16061.L_ALT_OP_ADD_FLOAT: /* 0xa6 */ 16062/* File: armv5te/alt_stub.S */ 16063/* 16064 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16065 * any interesting requests and then jump to the real instruction 16066 * handler. Note that the call to dvmCheckInst is done as a tail call. 16067 */ 16068 adrl lr, dvmAsmInstructionStart + (166 * 64) 16069 mov r0, rPC @ arg0 16070 mov r1, rSELF @ arg1 16071 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16072 16073/* ------------------------------ */ 16074 .balign 64 16075.L_ALT_OP_SUB_FLOAT: /* 0xa7 */ 16076/* File: armv5te/alt_stub.S */ 16077/* 16078 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16079 * any interesting requests and then jump to the real instruction 16080 * handler. Note that the call to dvmCheckInst is done as a tail call. 16081 */ 16082 adrl lr, dvmAsmInstructionStart + (167 * 64) 16083 mov r0, rPC @ arg0 16084 mov r1, rSELF @ arg1 16085 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16086 16087/* ------------------------------ */ 16088 .balign 64 16089.L_ALT_OP_MUL_FLOAT: /* 0xa8 */ 16090/* File: armv5te/alt_stub.S */ 16091/* 16092 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16093 * any interesting requests and then jump to the real instruction 16094 * handler. Note that the call to dvmCheckInst is done as a tail call. 16095 */ 16096 adrl lr, dvmAsmInstructionStart + (168 * 64) 16097 mov r0, rPC @ arg0 16098 mov r1, rSELF @ arg1 16099 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16100 16101/* ------------------------------ */ 16102 .balign 64 16103.L_ALT_OP_DIV_FLOAT: /* 0xa9 */ 16104/* File: armv5te/alt_stub.S */ 16105/* 16106 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16107 * any interesting requests and then jump to the real instruction 16108 * handler. Note that the call to dvmCheckInst is done as a tail call. 16109 */ 16110 adrl lr, dvmAsmInstructionStart + (169 * 64) 16111 mov r0, rPC @ arg0 16112 mov r1, rSELF @ arg1 16113 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16114 16115/* ------------------------------ */ 16116 .balign 64 16117.L_ALT_OP_REM_FLOAT: /* 0xaa */ 16118/* File: armv5te/alt_stub.S */ 16119/* 16120 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16121 * any interesting requests and then jump to the real instruction 16122 * handler. Note that the call to dvmCheckInst is done as a tail call. 16123 */ 16124 adrl lr, dvmAsmInstructionStart + (170 * 64) 16125 mov r0, rPC @ arg0 16126 mov r1, rSELF @ arg1 16127 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16128 16129/* ------------------------------ */ 16130 .balign 64 16131.L_ALT_OP_ADD_DOUBLE: /* 0xab */ 16132/* File: armv5te/alt_stub.S */ 16133/* 16134 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16135 * any interesting requests and then jump to the real instruction 16136 * handler. Note that the call to dvmCheckInst is done as a tail call. 16137 */ 16138 adrl lr, dvmAsmInstructionStart + (171 * 64) 16139 mov r0, rPC @ arg0 16140 mov r1, rSELF @ arg1 16141 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16142 16143/* ------------------------------ */ 16144 .balign 64 16145.L_ALT_OP_SUB_DOUBLE: /* 0xac */ 16146/* File: armv5te/alt_stub.S */ 16147/* 16148 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16149 * any interesting requests and then jump to the real instruction 16150 * handler. Note that the call to dvmCheckInst is done as a tail call. 16151 */ 16152 adrl lr, dvmAsmInstructionStart + (172 * 64) 16153 mov r0, rPC @ arg0 16154 mov r1, rSELF @ arg1 16155 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16156 16157/* ------------------------------ */ 16158 .balign 64 16159.L_ALT_OP_MUL_DOUBLE: /* 0xad */ 16160/* File: armv5te/alt_stub.S */ 16161/* 16162 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16163 * any interesting requests and then jump to the real instruction 16164 * handler. Note that the call to dvmCheckInst is done as a tail call. 16165 */ 16166 adrl lr, dvmAsmInstructionStart + (173 * 64) 16167 mov r0, rPC @ arg0 16168 mov r1, rSELF @ arg1 16169 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16170 16171/* ------------------------------ */ 16172 .balign 64 16173.L_ALT_OP_DIV_DOUBLE: /* 0xae */ 16174/* File: armv5te/alt_stub.S */ 16175/* 16176 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16177 * any interesting requests and then jump to the real instruction 16178 * handler. Note that the call to dvmCheckInst is done as a tail call. 16179 */ 16180 adrl lr, dvmAsmInstructionStart + (174 * 64) 16181 mov r0, rPC @ arg0 16182 mov r1, rSELF @ arg1 16183 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16184 16185/* ------------------------------ */ 16186 .balign 64 16187.L_ALT_OP_REM_DOUBLE: /* 0xaf */ 16188/* File: armv5te/alt_stub.S */ 16189/* 16190 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16191 * any interesting requests and then jump to the real instruction 16192 * handler. Note that the call to dvmCheckInst is done as a tail call. 16193 */ 16194 adrl lr, dvmAsmInstructionStart + (175 * 64) 16195 mov r0, rPC @ arg0 16196 mov r1, rSELF @ arg1 16197 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16198 16199/* ------------------------------ */ 16200 .balign 64 16201.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */ 16202/* File: armv5te/alt_stub.S */ 16203/* 16204 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16205 * any interesting requests and then jump to the real instruction 16206 * handler. Note that the call to dvmCheckInst is done as a tail call. 16207 */ 16208 adrl lr, dvmAsmInstructionStart + (176 * 64) 16209 mov r0, rPC @ arg0 16210 mov r1, rSELF @ arg1 16211 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16212 16213/* ------------------------------ */ 16214 .balign 64 16215.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */ 16216/* File: armv5te/alt_stub.S */ 16217/* 16218 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16219 * any interesting requests and then jump to the real instruction 16220 * handler. Note that the call to dvmCheckInst is done as a tail call. 16221 */ 16222 adrl lr, dvmAsmInstructionStart + (177 * 64) 16223 mov r0, rPC @ arg0 16224 mov r1, rSELF @ arg1 16225 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16226 16227/* ------------------------------ */ 16228 .balign 64 16229.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */ 16230/* File: armv5te/alt_stub.S */ 16231/* 16232 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16233 * any interesting requests and then jump to the real instruction 16234 * handler. Note that the call to dvmCheckInst is done as a tail call. 16235 */ 16236 adrl lr, dvmAsmInstructionStart + (178 * 64) 16237 mov r0, rPC @ arg0 16238 mov r1, rSELF @ arg1 16239 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16240 16241/* ------------------------------ */ 16242 .balign 64 16243.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */ 16244/* File: armv5te/alt_stub.S */ 16245/* 16246 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16247 * any interesting requests and then jump to the real instruction 16248 * handler. Note that the call to dvmCheckInst is done as a tail call. 16249 */ 16250 adrl lr, dvmAsmInstructionStart + (179 * 64) 16251 mov r0, rPC @ arg0 16252 mov r1, rSELF @ arg1 16253 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16254 16255/* ------------------------------ */ 16256 .balign 64 16257.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */ 16258/* File: armv5te/alt_stub.S */ 16259/* 16260 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16261 * any interesting requests and then jump to the real instruction 16262 * handler. Note that the call to dvmCheckInst is done as a tail call. 16263 */ 16264 adrl lr, dvmAsmInstructionStart + (180 * 64) 16265 mov r0, rPC @ arg0 16266 mov r1, rSELF @ arg1 16267 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16268 16269/* ------------------------------ */ 16270 .balign 64 16271.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */ 16272/* File: armv5te/alt_stub.S */ 16273/* 16274 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16275 * any interesting requests and then jump to the real instruction 16276 * handler. Note that the call to dvmCheckInst is done as a tail call. 16277 */ 16278 adrl lr, dvmAsmInstructionStart + (181 * 64) 16279 mov r0, rPC @ arg0 16280 mov r1, rSELF @ arg1 16281 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16282 16283/* ------------------------------ */ 16284 .balign 64 16285.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */ 16286/* File: armv5te/alt_stub.S */ 16287/* 16288 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16289 * any interesting requests and then jump to the real instruction 16290 * handler. Note that the call to dvmCheckInst is done as a tail call. 16291 */ 16292 adrl lr, dvmAsmInstructionStart + (182 * 64) 16293 mov r0, rPC @ arg0 16294 mov r1, rSELF @ arg1 16295 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16296 16297/* ------------------------------ */ 16298 .balign 64 16299.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */ 16300/* File: armv5te/alt_stub.S */ 16301/* 16302 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16303 * any interesting requests and then jump to the real instruction 16304 * handler. Note that the call to dvmCheckInst is done as a tail call. 16305 */ 16306 adrl lr, dvmAsmInstructionStart + (183 * 64) 16307 mov r0, rPC @ arg0 16308 mov r1, rSELF @ arg1 16309 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16310 16311/* ------------------------------ */ 16312 .balign 64 16313.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */ 16314/* File: armv5te/alt_stub.S */ 16315/* 16316 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16317 * any interesting requests and then jump to the real instruction 16318 * handler. Note that the call to dvmCheckInst is done as a tail call. 16319 */ 16320 adrl lr, dvmAsmInstructionStart + (184 * 64) 16321 mov r0, rPC @ arg0 16322 mov r1, rSELF @ arg1 16323 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16324 16325/* ------------------------------ */ 16326 .balign 64 16327.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */ 16328/* File: armv5te/alt_stub.S */ 16329/* 16330 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16331 * any interesting requests and then jump to the real instruction 16332 * handler. Note that the call to dvmCheckInst is done as a tail call. 16333 */ 16334 adrl lr, dvmAsmInstructionStart + (185 * 64) 16335 mov r0, rPC @ arg0 16336 mov r1, rSELF @ arg1 16337 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16338 16339/* ------------------------------ */ 16340 .balign 64 16341.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */ 16342/* File: armv5te/alt_stub.S */ 16343/* 16344 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16345 * any interesting requests and then jump to the real instruction 16346 * handler. Note that the call to dvmCheckInst is done as a tail call. 16347 */ 16348 adrl lr, dvmAsmInstructionStart + (186 * 64) 16349 mov r0, rPC @ arg0 16350 mov r1, rSELF @ arg1 16351 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16352 16353/* ------------------------------ */ 16354 .balign 64 16355.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */ 16356/* File: armv5te/alt_stub.S */ 16357/* 16358 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16359 * any interesting requests and then jump to the real instruction 16360 * handler. Note that the call to dvmCheckInst is done as a tail call. 16361 */ 16362 adrl lr, dvmAsmInstructionStart + (187 * 64) 16363 mov r0, rPC @ arg0 16364 mov r1, rSELF @ arg1 16365 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16366 16367/* ------------------------------ */ 16368 .balign 64 16369.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */ 16370/* File: armv5te/alt_stub.S */ 16371/* 16372 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16373 * any interesting requests and then jump to the real instruction 16374 * handler. Note that the call to dvmCheckInst is done as a tail call. 16375 */ 16376 adrl lr, dvmAsmInstructionStart + (188 * 64) 16377 mov r0, rPC @ arg0 16378 mov r1, rSELF @ arg1 16379 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16380 16381/* ------------------------------ */ 16382 .balign 64 16383.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */ 16384/* File: armv5te/alt_stub.S */ 16385/* 16386 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16387 * any interesting requests and then jump to the real instruction 16388 * handler. Note that the call to dvmCheckInst is done as a tail call. 16389 */ 16390 adrl lr, dvmAsmInstructionStart + (189 * 64) 16391 mov r0, rPC @ arg0 16392 mov r1, rSELF @ arg1 16393 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16394 16395/* ------------------------------ */ 16396 .balign 64 16397.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */ 16398/* File: armv5te/alt_stub.S */ 16399/* 16400 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16401 * any interesting requests and then jump to the real instruction 16402 * handler. Note that the call to dvmCheckInst is done as a tail call. 16403 */ 16404 adrl lr, dvmAsmInstructionStart + (190 * 64) 16405 mov r0, rPC @ arg0 16406 mov r1, rSELF @ arg1 16407 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16408 16409/* ------------------------------ */ 16410 .balign 64 16411.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */ 16412/* File: armv5te/alt_stub.S */ 16413/* 16414 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16415 * any interesting requests and then jump to the real instruction 16416 * handler. Note that the call to dvmCheckInst is done as a tail call. 16417 */ 16418 adrl lr, dvmAsmInstructionStart + (191 * 64) 16419 mov r0, rPC @ arg0 16420 mov r1, rSELF @ arg1 16421 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16422 16423/* ------------------------------ */ 16424 .balign 64 16425.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */ 16426/* File: armv5te/alt_stub.S */ 16427/* 16428 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16429 * any interesting requests and then jump to the real instruction 16430 * handler. Note that the call to dvmCheckInst is done as a tail call. 16431 */ 16432 adrl lr, dvmAsmInstructionStart + (192 * 64) 16433 mov r0, rPC @ arg0 16434 mov r1, rSELF @ arg1 16435 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16436 16437/* ------------------------------ */ 16438 .balign 64 16439.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */ 16440/* File: armv5te/alt_stub.S */ 16441/* 16442 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16443 * any interesting requests and then jump to the real instruction 16444 * handler. Note that the call to dvmCheckInst is done as a tail call. 16445 */ 16446 adrl lr, dvmAsmInstructionStart + (193 * 64) 16447 mov r0, rPC @ arg0 16448 mov r1, rSELF @ arg1 16449 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16450 16451/* ------------------------------ */ 16452 .balign 64 16453.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */ 16454/* File: armv5te/alt_stub.S */ 16455/* 16456 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16457 * any interesting requests and then jump to the real instruction 16458 * handler. Note that the call to dvmCheckInst is done as a tail call. 16459 */ 16460 adrl lr, dvmAsmInstructionStart + (194 * 64) 16461 mov r0, rPC @ arg0 16462 mov r1, rSELF @ arg1 16463 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16464 16465/* ------------------------------ */ 16466 .balign 64 16467.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */ 16468/* File: armv5te/alt_stub.S */ 16469/* 16470 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16471 * any interesting requests and then jump to the real instruction 16472 * handler. Note that the call to dvmCheckInst is done as a tail call. 16473 */ 16474 adrl lr, dvmAsmInstructionStart + (195 * 64) 16475 mov r0, rPC @ arg0 16476 mov r1, rSELF @ arg1 16477 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16478 16479/* ------------------------------ */ 16480 .balign 64 16481.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */ 16482/* File: armv5te/alt_stub.S */ 16483/* 16484 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16485 * any interesting requests and then jump to the real instruction 16486 * handler. Note that the call to dvmCheckInst is done as a tail call. 16487 */ 16488 adrl lr, dvmAsmInstructionStart + (196 * 64) 16489 mov r0, rPC @ arg0 16490 mov r1, rSELF @ arg1 16491 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16492 16493/* ------------------------------ */ 16494 .balign 64 16495.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */ 16496/* File: armv5te/alt_stub.S */ 16497/* 16498 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16499 * any interesting requests and then jump to the real instruction 16500 * handler. Note that the call to dvmCheckInst is done as a tail call. 16501 */ 16502 adrl lr, dvmAsmInstructionStart + (197 * 64) 16503 mov r0, rPC @ arg0 16504 mov r1, rSELF @ arg1 16505 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16506 16507/* ------------------------------ */ 16508 .balign 64 16509.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 16510/* File: armv5te/alt_stub.S */ 16511/* 16512 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16513 * any interesting requests and then jump to the real instruction 16514 * handler. Note that the call to dvmCheckInst is done as a tail call. 16515 */ 16516 adrl lr, dvmAsmInstructionStart + (198 * 64) 16517 mov r0, rPC @ arg0 16518 mov r1, rSELF @ arg1 16519 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16520 16521/* ------------------------------ */ 16522 .balign 64 16523.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 16524/* File: armv5te/alt_stub.S */ 16525/* 16526 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16527 * any interesting requests and then jump to the real instruction 16528 * handler. Note that the call to dvmCheckInst is done as a tail call. 16529 */ 16530 adrl lr, dvmAsmInstructionStart + (199 * 64) 16531 mov r0, rPC @ arg0 16532 mov r1, rSELF @ arg1 16533 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16534 16535/* ------------------------------ */ 16536 .balign 64 16537.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 16538/* File: armv5te/alt_stub.S */ 16539/* 16540 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16541 * any interesting requests and then jump to the real instruction 16542 * handler. Note that the call to dvmCheckInst is done as a tail call. 16543 */ 16544 adrl lr, dvmAsmInstructionStart + (200 * 64) 16545 mov r0, rPC @ arg0 16546 mov r1, rSELF @ arg1 16547 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16548 16549/* ------------------------------ */ 16550 .balign 64 16551.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 16552/* File: armv5te/alt_stub.S */ 16553/* 16554 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16555 * any interesting requests and then jump to the real instruction 16556 * handler. Note that the call to dvmCheckInst is done as a tail call. 16557 */ 16558 adrl lr, dvmAsmInstructionStart + (201 * 64) 16559 mov r0, rPC @ arg0 16560 mov r1, rSELF @ arg1 16561 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16562 16563/* ------------------------------ */ 16564 .balign 64 16565.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */ 16566/* File: armv5te/alt_stub.S */ 16567/* 16568 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16569 * any interesting requests and then jump to the real instruction 16570 * handler. Note that the call to dvmCheckInst is done as a tail call. 16571 */ 16572 adrl lr, dvmAsmInstructionStart + (202 * 64) 16573 mov r0, rPC @ arg0 16574 mov r1, rSELF @ arg1 16575 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16576 16577/* ------------------------------ */ 16578 .balign 64 16579.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 16580/* File: armv5te/alt_stub.S */ 16581/* 16582 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16583 * any interesting requests and then jump to the real instruction 16584 * handler. Note that the call to dvmCheckInst is done as a tail call. 16585 */ 16586 adrl lr, dvmAsmInstructionStart + (203 * 64) 16587 mov r0, rPC @ arg0 16588 mov r1, rSELF @ arg1 16589 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16590 16591/* ------------------------------ */ 16592 .balign 64 16593.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 16594/* File: armv5te/alt_stub.S */ 16595/* 16596 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16597 * any interesting requests and then jump to the real instruction 16598 * handler. Note that the call to dvmCheckInst is done as a tail call. 16599 */ 16600 adrl lr, dvmAsmInstructionStart + (204 * 64) 16601 mov r0, rPC @ arg0 16602 mov r1, rSELF @ arg1 16603 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16604 16605/* ------------------------------ */ 16606 .balign 64 16607.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 16608/* File: armv5te/alt_stub.S */ 16609/* 16610 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16611 * any interesting requests and then jump to the real instruction 16612 * handler. Note that the call to dvmCheckInst is done as a tail call. 16613 */ 16614 adrl lr, dvmAsmInstructionStart + (205 * 64) 16615 mov r0, rPC @ arg0 16616 mov r1, rSELF @ arg1 16617 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16618 16619/* ------------------------------ */ 16620 .balign 64 16621.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 16622/* File: armv5te/alt_stub.S */ 16623/* 16624 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16625 * any interesting requests and then jump to the real instruction 16626 * handler. Note that the call to dvmCheckInst is done as a tail call. 16627 */ 16628 adrl lr, dvmAsmInstructionStart + (206 * 64) 16629 mov r0, rPC @ arg0 16630 mov r1, rSELF @ arg1 16631 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16632 16633/* ------------------------------ */ 16634 .balign 64 16635.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 16636/* File: armv5te/alt_stub.S */ 16637/* 16638 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16639 * any interesting requests and then jump to the real instruction 16640 * handler. Note that the call to dvmCheckInst is done as a tail call. 16641 */ 16642 adrl lr, dvmAsmInstructionStart + (207 * 64) 16643 mov r0, rPC @ arg0 16644 mov r1, rSELF @ arg1 16645 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16646 16647/* ------------------------------ */ 16648 .balign 64 16649.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */ 16650/* File: armv5te/alt_stub.S */ 16651/* 16652 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16653 * any interesting requests and then jump to the real instruction 16654 * handler. Note that the call to dvmCheckInst is done as a tail call. 16655 */ 16656 adrl lr, dvmAsmInstructionStart + (208 * 64) 16657 mov r0, rPC @ arg0 16658 mov r1, rSELF @ arg1 16659 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16660 16661/* ------------------------------ */ 16662 .balign 64 16663.L_ALT_OP_RSUB_INT: /* 0xd1 */ 16664/* File: armv5te/alt_stub.S */ 16665/* 16666 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16667 * any interesting requests and then jump to the real instruction 16668 * handler. Note that the call to dvmCheckInst is done as a tail call. 16669 */ 16670 adrl lr, dvmAsmInstructionStart + (209 * 64) 16671 mov r0, rPC @ arg0 16672 mov r1, rSELF @ arg1 16673 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16674 16675/* ------------------------------ */ 16676 .balign 64 16677.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */ 16678/* File: armv5te/alt_stub.S */ 16679/* 16680 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16681 * any interesting requests and then jump to the real instruction 16682 * handler. Note that the call to dvmCheckInst is done as a tail call. 16683 */ 16684 adrl lr, dvmAsmInstructionStart + (210 * 64) 16685 mov r0, rPC @ arg0 16686 mov r1, rSELF @ arg1 16687 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16688 16689/* ------------------------------ */ 16690 .balign 64 16691.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */ 16692/* File: armv5te/alt_stub.S */ 16693/* 16694 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16695 * any interesting requests and then jump to the real instruction 16696 * handler. Note that the call to dvmCheckInst is done as a tail call. 16697 */ 16698 adrl lr, dvmAsmInstructionStart + (211 * 64) 16699 mov r0, rPC @ arg0 16700 mov r1, rSELF @ arg1 16701 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16702 16703/* ------------------------------ */ 16704 .balign 64 16705.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */ 16706/* File: armv5te/alt_stub.S */ 16707/* 16708 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16709 * any interesting requests and then jump to the real instruction 16710 * handler. Note that the call to dvmCheckInst is done as a tail call. 16711 */ 16712 adrl lr, dvmAsmInstructionStart + (212 * 64) 16713 mov r0, rPC @ arg0 16714 mov r1, rSELF @ arg1 16715 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16716 16717/* ------------------------------ */ 16718 .balign 64 16719.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */ 16720/* File: armv5te/alt_stub.S */ 16721/* 16722 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16723 * any interesting requests and then jump to the real instruction 16724 * handler. Note that the call to dvmCheckInst is done as a tail call. 16725 */ 16726 adrl lr, dvmAsmInstructionStart + (213 * 64) 16727 mov r0, rPC @ arg0 16728 mov r1, rSELF @ arg1 16729 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16730 16731/* ------------------------------ */ 16732 .balign 64 16733.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */ 16734/* File: armv5te/alt_stub.S */ 16735/* 16736 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16737 * any interesting requests and then jump to the real instruction 16738 * handler. Note that the call to dvmCheckInst is done as a tail call. 16739 */ 16740 adrl lr, dvmAsmInstructionStart + (214 * 64) 16741 mov r0, rPC @ arg0 16742 mov r1, rSELF @ arg1 16743 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16744 16745/* ------------------------------ */ 16746 .balign 64 16747.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */ 16748/* File: armv5te/alt_stub.S */ 16749/* 16750 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16751 * any interesting requests and then jump to the real instruction 16752 * handler. Note that the call to dvmCheckInst is done as a tail call. 16753 */ 16754 adrl lr, dvmAsmInstructionStart + (215 * 64) 16755 mov r0, rPC @ arg0 16756 mov r1, rSELF @ arg1 16757 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16758 16759/* ------------------------------ */ 16760 .balign 64 16761.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */ 16762/* File: armv5te/alt_stub.S */ 16763/* 16764 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16765 * any interesting requests and then jump to the real instruction 16766 * handler. Note that the call to dvmCheckInst is done as a tail call. 16767 */ 16768 adrl lr, dvmAsmInstructionStart + (216 * 64) 16769 mov r0, rPC @ arg0 16770 mov r1, rSELF @ arg1 16771 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16772 16773/* ------------------------------ */ 16774 .balign 64 16775.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */ 16776/* File: armv5te/alt_stub.S */ 16777/* 16778 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16779 * any interesting requests and then jump to the real instruction 16780 * handler. Note that the call to dvmCheckInst is done as a tail call. 16781 */ 16782 adrl lr, dvmAsmInstructionStart + (217 * 64) 16783 mov r0, rPC @ arg0 16784 mov r1, rSELF @ arg1 16785 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16786 16787/* ------------------------------ */ 16788 .balign 64 16789.L_ALT_OP_MUL_INT_LIT8: /* 0xda */ 16790/* File: armv5te/alt_stub.S */ 16791/* 16792 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16793 * any interesting requests and then jump to the real instruction 16794 * handler. Note that the call to dvmCheckInst is done as a tail call. 16795 */ 16796 adrl lr, dvmAsmInstructionStart + (218 * 64) 16797 mov r0, rPC @ arg0 16798 mov r1, rSELF @ arg1 16799 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16800 16801/* ------------------------------ */ 16802 .balign 64 16803.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */ 16804/* File: armv5te/alt_stub.S */ 16805/* 16806 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16807 * any interesting requests and then jump to the real instruction 16808 * handler. Note that the call to dvmCheckInst is done as a tail call. 16809 */ 16810 adrl lr, dvmAsmInstructionStart + (219 * 64) 16811 mov r0, rPC @ arg0 16812 mov r1, rSELF @ arg1 16813 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16814 16815/* ------------------------------ */ 16816 .balign 64 16817.L_ALT_OP_REM_INT_LIT8: /* 0xdc */ 16818/* File: armv5te/alt_stub.S */ 16819/* 16820 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16821 * any interesting requests and then jump to the real instruction 16822 * handler. Note that the call to dvmCheckInst is done as a tail call. 16823 */ 16824 adrl lr, dvmAsmInstructionStart + (220 * 64) 16825 mov r0, rPC @ arg0 16826 mov r1, rSELF @ arg1 16827 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16828 16829/* ------------------------------ */ 16830 .balign 64 16831.L_ALT_OP_AND_INT_LIT8: /* 0xdd */ 16832/* File: armv5te/alt_stub.S */ 16833/* 16834 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16835 * any interesting requests and then jump to the real instruction 16836 * handler. Note that the call to dvmCheckInst is done as a tail call. 16837 */ 16838 adrl lr, dvmAsmInstructionStart + (221 * 64) 16839 mov r0, rPC @ arg0 16840 mov r1, rSELF @ arg1 16841 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16842 16843/* ------------------------------ */ 16844 .balign 64 16845.L_ALT_OP_OR_INT_LIT8: /* 0xde */ 16846/* File: armv5te/alt_stub.S */ 16847/* 16848 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16849 * any interesting requests and then jump to the real instruction 16850 * handler. Note that the call to dvmCheckInst is done as a tail call. 16851 */ 16852 adrl lr, dvmAsmInstructionStart + (222 * 64) 16853 mov r0, rPC @ arg0 16854 mov r1, rSELF @ arg1 16855 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16856 16857/* ------------------------------ */ 16858 .balign 64 16859.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */ 16860/* File: armv5te/alt_stub.S */ 16861/* 16862 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16863 * any interesting requests and then jump to the real instruction 16864 * handler. Note that the call to dvmCheckInst is done as a tail call. 16865 */ 16866 adrl lr, dvmAsmInstructionStart + (223 * 64) 16867 mov r0, rPC @ arg0 16868 mov r1, rSELF @ arg1 16869 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16870 16871/* ------------------------------ */ 16872 .balign 64 16873.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */ 16874/* File: armv5te/alt_stub.S */ 16875/* 16876 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16877 * any interesting requests and then jump to the real instruction 16878 * handler. Note that the call to dvmCheckInst is done as a tail call. 16879 */ 16880 adrl lr, dvmAsmInstructionStart + (224 * 64) 16881 mov r0, rPC @ arg0 16882 mov r1, rSELF @ arg1 16883 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16884 16885/* ------------------------------ */ 16886 .balign 64 16887.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */ 16888/* File: armv5te/alt_stub.S */ 16889/* 16890 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16891 * any interesting requests and then jump to the real instruction 16892 * handler. Note that the call to dvmCheckInst is done as a tail call. 16893 */ 16894 adrl lr, dvmAsmInstructionStart + (225 * 64) 16895 mov r0, rPC @ arg0 16896 mov r1, rSELF @ arg1 16897 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16898 16899/* ------------------------------ */ 16900 .balign 64 16901.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */ 16902/* File: armv5te/alt_stub.S */ 16903/* 16904 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16905 * any interesting requests and then jump to the real instruction 16906 * handler. Note that the call to dvmCheckInst is done as a tail call. 16907 */ 16908 adrl lr, dvmAsmInstructionStart + (226 * 64) 16909 mov r0, rPC @ arg0 16910 mov r1, rSELF @ arg1 16911 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16912 16913/* ------------------------------ */ 16914 .balign 64 16915.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */ 16916/* File: armv5te/alt_stub.S */ 16917/* 16918 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16919 * any interesting requests and then jump to the real instruction 16920 * handler. Note that the call to dvmCheckInst is done as a tail call. 16921 */ 16922 adrl lr, dvmAsmInstructionStart + (227 * 64) 16923 mov r0, rPC @ arg0 16924 mov r1, rSELF @ arg1 16925 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16926 16927/* ------------------------------ */ 16928 .balign 64 16929.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */ 16930/* File: armv5te/alt_stub.S */ 16931/* 16932 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16933 * any interesting requests and then jump to the real instruction 16934 * handler. Note that the call to dvmCheckInst is done as a tail call. 16935 */ 16936 adrl lr, dvmAsmInstructionStart + (228 * 64) 16937 mov r0, rPC @ arg0 16938 mov r1, rSELF @ arg1 16939 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16940 16941/* ------------------------------ */ 16942 .balign 64 16943.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */ 16944/* File: armv5te/alt_stub.S */ 16945/* 16946 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16947 * any interesting requests and then jump to the real instruction 16948 * handler. Note that the call to dvmCheckInst is done as a tail call. 16949 */ 16950 adrl lr, dvmAsmInstructionStart + (229 * 64) 16951 mov r0, rPC @ arg0 16952 mov r1, rSELF @ arg1 16953 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16954 16955/* ------------------------------ */ 16956 .balign 64 16957.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */ 16958/* File: armv5te/alt_stub.S */ 16959/* 16960 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16961 * any interesting requests and then jump to the real instruction 16962 * handler. Note that the call to dvmCheckInst is done as a tail call. 16963 */ 16964 adrl lr, dvmAsmInstructionStart + (230 * 64) 16965 mov r0, rPC @ arg0 16966 mov r1, rSELF @ arg1 16967 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16968 16969/* ------------------------------ */ 16970 .balign 64 16971.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 16972/* File: armv5te/alt_stub.S */ 16973/* 16974 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16975 * any interesting requests and then jump to the real instruction 16976 * handler. Note that the call to dvmCheckInst is done as a tail call. 16977 */ 16978 adrl lr, dvmAsmInstructionStart + (231 * 64) 16979 mov r0, rPC @ arg0 16980 mov r1, rSELF @ arg1 16981 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16982 16983/* ------------------------------ */ 16984 .balign 64 16985.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 16986/* File: armv5te/alt_stub.S */ 16987/* 16988 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16989 * any interesting requests and then jump to the real instruction 16990 * handler. Note that the call to dvmCheckInst is done as a tail call. 16991 */ 16992 adrl lr, dvmAsmInstructionStart + (232 * 64) 16993 mov r0, rPC @ arg0 16994 mov r1, rSELF @ arg1 16995 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16996 16997/* ------------------------------ */ 16998 .balign 64 16999.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 17000/* File: armv5te/alt_stub.S */ 17001/* 17002 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17003 * any interesting requests and then jump to the real instruction 17004 * handler. Note that the call to dvmCheckInst is done as a tail call. 17005 */ 17006 adrl lr, dvmAsmInstructionStart + (233 * 64) 17007 mov r0, rPC @ arg0 17008 mov r1, rSELF @ arg1 17009 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17010 17011/* ------------------------------ */ 17012 .balign 64 17013.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */ 17014/* File: armv5te/alt_stub.S */ 17015/* 17016 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17017 * any interesting requests and then jump to the real instruction 17018 * handler. Note that the call to dvmCheckInst is done as a tail call. 17019 */ 17020 adrl lr, dvmAsmInstructionStart + (234 * 64) 17021 mov r0, rPC @ arg0 17022 mov r1, rSELF @ arg1 17023 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17024 17025/* ------------------------------ */ 17026 .balign 64 17027.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 17028/* File: armv5te/alt_stub.S */ 17029/* 17030 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17031 * any interesting requests and then jump to the real instruction 17032 * handler. Note that the call to dvmCheckInst is done as a tail call. 17033 */ 17034 adrl lr, dvmAsmInstructionStart + (235 * 64) 17035 mov r0, rPC @ arg0 17036 mov r1, rSELF @ arg1 17037 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17038 17039/* ------------------------------ */ 17040 .balign 64 17041.L_ALT_OP_BREAKPOINT: /* 0xec */ 17042/* File: armv5te/alt_stub.S */ 17043/* 17044 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17045 * any interesting requests and then jump to the real instruction 17046 * handler. Note that the call to dvmCheckInst is done as a tail call. 17047 */ 17048 adrl lr, dvmAsmInstructionStart + (236 * 64) 17049 mov r0, rPC @ arg0 17050 mov r1, rSELF @ arg1 17051 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17052 17053/* ------------------------------ */ 17054 .balign 64 17055.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 17056/* File: armv5te/alt_stub.S */ 17057/* 17058 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17059 * any interesting requests and then jump to the real instruction 17060 * handler. Note that the call to dvmCheckInst is done as a tail call. 17061 */ 17062 adrl lr, dvmAsmInstructionStart + (237 * 64) 17063 mov r0, rPC @ arg0 17064 mov r1, rSELF @ arg1 17065 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17066 17067/* ------------------------------ */ 17068 .balign 64 17069.L_ALT_OP_EXECUTE_INLINE: /* 0xee */ 17070/* File: armv5te/alt_stub.S */ 17071/* 17072 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17073 * any interesting requests and then jump to the real instruction 17074 * handler. Note that the call to dvmCheckInst is done as a tail call. 17075 */ 17076 adrl lr, dvmAsmInstructionStart + (238 * 64) 17077 mov r0, rPC @ arg0 17078 mov r1, rSELF @ arg1 17079 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17080 17081/* ------------------------------ */ 17082 .balign 64 17083.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 17084/* File: armv5te/alt_stub.S */ 17085/* 17086 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17087 * any interesting requests and then jump to the real instruction 17088 * handler. Note that the call to dvmCheckInst is done as a tail call. 17089 */ 17090 adrl lr, dvmAsmInstructionStart + (239 * 64) 17091 mov r0, rPC @ arg0 17092 mov r1, rSELF @ arg1 17093 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17094 17095/* ------------------------------ */ 17096 .balign 64 17097.L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 17098/* File: armv5te/alt_stub.S */ 17099/* 17100 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17101 * any interesting requests and then jump to the real instruction 17102 * handler. Note that the call to dvmCheckInst is done as a tail call. 17103 */ 17104 adrl lr, dvmAsmInstructionStart + (240 * 64) 17105 mov r0, rPC @ arg0 17106 mov r1, rSELF @ arg1 17107 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17108 17109/* ------------------------------ */ 17110 .balign 64 17111.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 17112/* File: armv5te/alt_stub.S */ 17113/* 17114 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17115 * any interesting requests and then jump to the real instruction 17116 * handler. Note that the call to dvmCheckInst is done as a tail call. 17117 */ 17118 adrl lr, dvmAsmInstructionStart + (241 * 64) 17119 mov r0, rPC @ arg0 17120 mov r1, rSELF @ arg1 17121 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17122 17123/* ------------------------------ */ 17124 .balign 64 17125.L_ALT_OP_IGET_QUICK: /* 0xf2 */ 17126/* File: armv5te/alt_stub.S */ 17127/* 17128 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17129 * any interesting requests and then jump to the real instruction 17130 * handler. Note that the call to dvmCheckInst is done as a tail call. 17131 */ 17132 adrl lr, dvmAsmInstructionStart + (242 * 64) 17133 mov r0, rPC @ arg0 17134 mov r1, rSELF @ arg1 17135 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17136 17137/* ------------------------------ */ 17138 .balign 64 17139.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */ 17140/* File: armv5te/alt_stub.S */ 17141/* 17142 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17143 * any interesting requests and then jump to the real instruction 17144 * handler. Note that the call to dvmCheckInst is done as a tail call. 17145 */ 17146 adrl lr, dvmAsmInstructionStart + (243 * 64) 17147 mov r0, rPC @ arg0 17148 mov r1, rSELF @ arg1 17149 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17150 17151/* ------------------------------ */ 17152 .balign 64 17153.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 17154/* File: armv5te/alt_stub.S */ 17155/* 17156 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17157 * any interesting requests and then jump to the real instruction 17158 * handler. Note that the call to dvmCheckInst is done as a tail call. 17159 */ 17160 adrl lr, dvmAsmInstructionStart + (244 * 64) 17161 mov r0, rPC @ arg0 17162 mov r1, rSELF @ arg1 17163 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17164 17165/* ------------------------------ */ 17166 .balign 64 17167.L_ALT_OP_IPUT_QUICK: /* 0xf5 */ 17168/* File: armv5te/alt_stub.S */ 17169/* 17170 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17171 * any interesting requests and then jump to the real instruction 17172 * handler. Note that the call to dvmCheckInst is done as a tail call. 17173 */ 17174 adrl lr, dvmAsmInstructionStart + (245 * 64) 17175 mov r0, rPC @ arg0 17176 mov r1, rSELF @ arg1 17177 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17178 17179/* ------------------------------ */ 17180 .balign 64 17181.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 17182/* File: armv5te/alt_stub.S */ 17183/* 17184 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17185 * any interesting requests and then jump to the real instruction 17186 * handler. Note that the call to dvmCheckInst is done as a tail call. 17187 */ 17188 adrl lr, dvmAsmInstructionStart + (246 * 64) 17189 mov r0, rPC @ arg0 17190 mov r1, rSELF @ arg1 17191 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17192 17193/* ------------------------------ */ 17194 .balign 64 17195.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 17196/* File: armv5te/alt_stub.S */ 17197/* 17198 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17199 * any interesting requests and then jump to the real instruction 17200 * handler. Note that the call to dvmCheckInst is done as a tail call. 17201 */ 17202 adrl lr, dvmAsmInstructionStart + (247 * 64) 17203 mov r0, rPC @ arg0 17204 mov r1, rSELF @ arg1 17205 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17206 17207/* ------------------------------ */ 17208 .balign 64 17209.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 17210/* File: armv5te/alt_stub.S */ 17211/* 17212 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17213 * any interesting requests and then jump to the real instruction 17214 * handler. Note that the call to dvmCheckInst is done as a tail call. 17215 */ 17216 adrl lr, dvmAsmInstructionStart + (248 * 64) 17217 mov r0, rPC @ arg0 17218 mov r1, rSELF @ arg1 17219 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17220 17221/* ------------------------------ */ 17222 .balign 64 17223.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 17224/* File: armv5te/alt_stub.S */ 17225/* 17226 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17227 * any interesting requests and then jump to the real instruction 17228 * handler. Note that the call to dvmCheckInst is done as a tail call. 17229 */ 17230 adrl lr, dvmAsmInstructionStart + (249 * 64) 17231 mov r0, rPC @ arg0 17232 mov r1, rSELF @ arg1 17233 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17234 17235/* ------------------------------ */ 17236 .balign 64 17237.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 17238/* File: armv5te/alt_stub.S */ 17239/* 17240 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17241 * any interesting requests and then jump to the real instruction 17242 * handler. Note that the call to dvmCheckInst is done as a tail call. 17243 */ 17244 adrl lr, dvmAsmInstructionStart + (250 * 64) 17245 mov r0, rPC @ arg0 17246 mov r1, rSELF @ arg1 17247 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17248 17249/* ------------------------------ */ 17250 .balign 64 17251.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 17252/* File: armv5te/alt_stub.S */ 17253/* 17254 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17255 * any interesting requests and then jump to the real instruction 17256 * handler. Note that the call to dvmCheckInst is done as a tail call. 17257 */ 17258 adrl lr, dvmAsmInstructionStart + (251 * 64) 17259 mov r0, rPC @ arg0 17260 mov r1, rSELF @ arg1 17261 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17262 17263/* ------------------------------ */ 17264 .balign 64 17265.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 17266/* File: armv5te/alt_stub.S */ 17267/* 17268 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17269 * any interesting requests and then jump to the real instruction 17270 * handler. Note that the call to dvmCheckInst is done as a tail call. 17271 */ 17272 adrl lr, dvmAsmInstructionStart + (252 * 64) 17273 mov r0, rPC @ arg0 17274 mov r1, rSELF @ arg1 17275 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17276 17277/* ------------------------------ */ 17278 .balign 64 17279.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 17280/* File: armv5te/alt_stub.S */ 17281/* 17282 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17283 * any interesting requests and then jump to the real instruction 17284 * handler. Note that the call to dvmCheckInst is done as a tail call. 17285 */ 17286 adrl lr, dvmAsmInstructionStart + (253 * 64) 17287 mov r0, rPC @ arg0 17288 mov r1, rSELF @ arg1 17289 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17290 17291/* ------------------------------ */ 17292 .balign 64 17293.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 17294/* File: armv5te/alt_stub.S */ 17295/* 17296 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17297 * any interesting requests and then jump to the real instruction 17298 * handler. Note that the call to dvmCheckInst is done as a tail call. 17299 */ 17300 adrl lr, dvmAsmInstructionStart + (254 * 64) 17301 mov r0, rPC @ arg0 17302 mov r1, rSELF @ arg1 17303 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17304 17305/* ------------------------------ */ 17306 .balign 64 17307.L_ALT_OP_DISPATCH_FF: /* 0xff */ 17308/* File: armv5te/alt_stub.S */ 17309/* 17310 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17311 * any interesting requests and then jump to the real instruction 17312 * handler. Note that the call to dvmCheckInst is done as a tail call. 17313 */ 17314 adrl lr, dvmAsmInstructionStart + (255 * 64) 17315 mov r0, rPC @ arg0 17316 mov r1, rSELF @ arg1 17317 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17318 17319/* ------------------------------ */ 17320 .balign 64 17321.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */ 17322/* File: armv5te/alt_stub.S */ 17323/* 17324 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17325 * any interesting requests and then jump to the real instruction 17326 * handler. Note that the call to dvmCheckInst is done as a tail call. 17327 */ 17328 adrl lr, dvmAsmInstructionStart + (256 * 64) 17329 mov r0, rPC @ arg0 17330 mov r1, rSELF @ arg1 17331 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17332 17333/* ------------------------------ */ 17334 .balign 64 17335.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */ 17336/* File: armv5te/alt_stub.S */ 17337/* 17338 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17339 * any interesting requests and then jump to the real instruction 17340 * handler. Note that the call to dvmCheckInst is done as a tail call. 17341 */ 17342 adrl lr, dvmAsmInstructionStart + (257 * 64) 17343 mov r0, rPC @ arg0 17344 mov r1, rSELF @ arg1 17345 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17346 17347/* ------------------------------ */ 17348 .balign 64 17349.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 17350/* File: armv5te/alt_stub.S */ 17351/* 17352 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17353 * any interesting requests and then jump to the real instruction 17354 * handler. Note that the call to dvmCheckInst is done as a tail call. 17355 */ 17356 adrl lr, dvmAsmInstructionStart + (258 * 64) 17357 mov r0, rPC @ arg0 17358 mov r1, rSELF @ arg1 17359 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17360 17361/* ------------------------------ */ 17362 .balign 64 17363.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 17364/* File: armv5te/alt_stub.S */ 17365/* 17366 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17367 * any interesting requests and then jump to the real instruction 17368 * handler. Note that the call to dvmCheckInst is done as a tail call. 17369 */ 17370 adrl lr, dvmAsmInstructionStart + (259 * 64) 17371 mov r0, rPC @ arg0 17372 mov r1, rSELF @ arg1 17373 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17374 17375/* ------------------------------ */ 17376 .balign 64 17377.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 17378/* File: armv5te/alt_stub.S */ 17379/* 17380 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17381 * any interesting requests and then jump to the real instruction 17382 * handler. Note that the call to dvmCheckInst is done as a tail call. 17383 */ 17384 adrl lr, dvmAsmInstructionStart + (260 * 64) 17385 mov r0, rPC @ arg0 17386 mov r1, rSELF @ arg1 17387 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17388 17389/* ------------------------------ */ 17390 .balign 64 17391.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 17392/* File: armv5te/alt_stub.S */ 17393/* 17394 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17395 * any interesting requests and then jump to the real instruction 17396 * handler. Note that the call to dvmCheckInst is done as a tail call. 17397 */ 17398 adrl lr, dvmAsmInstructionStart + (261 * 64) 17399 mov r0, rPC @ arg0 17400 mov r1, rSELF @ arg1 17401 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17402 17403/* ------------------------------ */ 17404 .balign 64 17405.L_ALT_OP_IGET_JUMBO: /* 0x106 */ 17406/* File: armv5te/alt_stub.S */ 17407/* 17408 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17409 * any interesting requests and then jump to the real instruction 17410 * handler. Note that the call to dvmCheckInst is done as a tail call. 17411 */ 17412 adrl lr, dvmAsmInstructionStart + (262 * 64) 17413 mov r0, rPC @ arg0 17414 mov r1, rSELF @ arg1 17415 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17416 17417/* ------------------------------ */ 17418 .balign 64 17419.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */ 17420/* File: armv5te/alt_stub.S */ 17421/* 17422 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17423 * any interesting requests and then jump to the real instruction 17424 * handler. Note that the call to dvmCheckInst is done as a tail call. 17425 */ 17426 adrl lr, dvmAsmInstructionStart + (263 * 64) 17427 mov r0, rPC @ arg0 17428 mov r1, rSELF @ arg1 17429 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17430 17431/* ------------------------------ */ 17432 .balign 64 17433.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 17434/* File: armv5te/alt_stub.S */ 17435/* 17436 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17437 * any interesting requests and then jump to the real instruction 17438 * handler. Note that the call to dvmCheckInst is done as a tail call. 17439 */ 17440 adrl lr, dvmAsmInstructionStart + (264 * 64) 17441 mov r0, rPC @ arg0 17442 mov r1, rSELF @ arg1 17443 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17444 17445/* ------------------------------ */ 17446 .balign 64 17447.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 17448/* File: armv5te/alt_stub.S */ 17449/* 17450 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17451 * any interesting requests and then jump to the real instruction 17452 * handler. Note that the call to dvmCheckInst is done as a tail call. 17453 */ 17454 adrl lr, dvmAsmInstructionStart + (265 * 64) 17455 mov r0, rPC @ arg0 17456 mov r1, rSELF @ arg1 17457 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17458 17459/* ------------------------------ */ 17460 .balign 64 17461.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */ 17462/* File: armv5te/alt_stub.S */ 17463/* 17464 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17465 * any interesting requests and then jump to the real instruction 17466 * handler. Note that the call to dvmCheckInst is done as a tail call. 17467 */ 17468 adrl lr, dvmAsmInstructionStart + (266 * 64) 17469 mov r0, rPC @ arg0 17470 mov r1, rSELF @ arg1 17471 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17472 17473/* ------------------------------ */ 17474 .balign 64 17475.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */ 17476/* File: armv5te/alt_stub.S */ 17477/* 17478 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17479 * any interesting requests and then jump to the real instruction 17480 * handler. Note that the call to dvmCheckInst is done as a tail call. 17481 */ 17482 adrl lr, dvmAsmInstructionStart + (267 * 64) 17483 mov r0, rPC @ arg0 17484 mov r1, rSELF @ arg1 17485 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17486 17487/* ------------------------------ */ 17488 .balign 64 17489.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */ 17490/* File: armv5te/alt_stub.S */ 17491/* 17492 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17493 * any interesting requests and then jump to the real instruction 17494 * handler. Note that the call to dvmCheckInst is done as a tail call. 17495 */ 17496 adrl lr, dvmAsmInstructionStart + (268 * 64) 17497 mov r0, rPC @ arg0 17498 mov r1, rSELF @ arg1 17499 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17500 17501/* ------------------------------ */ 17502 .balign 64 17503.L_ALT_OP_IPUT_JUMBO: /* 0x10d */ 17504/* File: armv5te/alt_stub.S */ 17505/* 17506 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17507 * any interesting requests and then jump to the real instruction 17508 * handler. Note that the call to dvmCheckInst is done as a tail call. 17509 */ 17510 adrl lr, dvmAsmInstructionStart + (269 * 64) 17511 mov r0, rPC @ arg0 17512 mov r1, rSELF @ arg1 17513 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17514 17515/* ------------------------------ */ 17516 .balign 64 17517.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 17518/* File: armv5te/alt_stub.S */ 17519/* 17520 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17521 * any interesting requests and then jump to the real instruction 17522 * handler. Note that the call to dvmCheckInst is done as a tail call. 17523 */ 17524 adrl lr, dvmAsmInstructionStart + (270 * 64) 17525 mov r0, rPC @ arg0 17526 mov r1, rSELF @ arg1 17527 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17528 17529/* ------------------------------ */ 17530 .balign 64 17531.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 17532/* File: armv5te/alt_stub.S */ 17533/* 17534 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17535 * any interesting requests and then jump to the real instruction 17536 * handler. Note that the call to dvmCheckInst is done as a tail call. 17537 */ 17538 adrl lr, dvmAsmInstructionStart + (271 * 64) 17539 mov r0, rPC @ arg0 17540 mov r1, rSELF @ arg1 17541 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17542 17543/* ------------------------------ */ 17544 .balign 64 17545.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 17546/* File: armv5te/alt_stub.S */ 17547/* 17548 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17549 * any interesting requests and then jump to the real instruction 17550 * handler. Note that the call to dvmCheckInst is done as a tail call. 17551 */ 17552 adrl lr, dvmAsmInstructionStart + (272 * 64) 17553 mov r0, rPC @ arg0 17554 mov r1, rSELF @ arg1 17555 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17556 17557/* ------------------------------ */ 17558 .balign 64 17559.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 17560/* File: armv5te/alt_stub.S */ 17561/* 17562 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17563 * any interesting requests and then jump to the real instruction 17564 * handler. Note that the call to dvmCheckInst is done as a tail call. 17565 */ 17566 adrl lr, dvmAsmInstructionStart + (273 * 64) 17567 mov r0, rPC @ arg0 17568 mov r1, rSELF @ arg1 17569 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17570 17571/* ------------------------------ */ 17572 .balign 64 17573.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 17574/* File: armv5te/alt_stub.S */ 17575/* 17576 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17577 * any interesting requests and then jump to the real instruction 17578 * handler. Note that the call to dvmCheckInst is done as a tail call. 17579 */ 17580 adrl lr, dvmAsmInstructionStart + (274 * 64) 17581 mov r0, rPC @ arg0 17582 mov r1, rSELF @ arg1 17583 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17584 17585/* ------------------------------ */ 17586 .balign 64 17587.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 17588/* File: armv5te/alt_stub.S */ 17589/* 17590 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17591 * any interesting requests and then jump to the real instruction 17592 * handler. Note that the call to dvmCheckInst is done as a tail call. 17593 */ 17594 adrl lr, dvmAsmInstructionStart + (275 * 64) 17595 mov r0, rPC @ arg0 17596 mov r1, rSELF @ arg1 17597 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17598 17599/* ------------------------------ */ 17600 .balign 64 17601.L_ALT_OP_SGET_JUMBO: /* 0x114 */ 17602/* File: armv5te/alt_stub.S */ 17603/* 17604 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17605 * any interesting requests and then jump to the real instruction 17606 * handler. Note that the call to dvmCheckInst is done as a tail call. 17607 */ 17608 adrl lr, dvmAsmInstructionStart + (276 * 64) 17609 mov r0, rPC @ arg0 17610 mov r1, rSELF @ arg1 17611 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17612 17613/* ------------------------------ */ 17614 .balign 64 17615.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */ 17616/* File: armv5te/alt_stub.S */ 17617/* 17618 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17619 * any interesting requests and then jump to the real instruction 17620 * handler. Note that the call to dvmCheckInst is done as a tail call. 17621 */ 17622 adrl lr, dvmAsmInstructionStart + (277 * 64) 17623 mov r0, rPC @ arg0 17624 mov r1, rSELF @ arg1 17625 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17626 17627/* ------------------------------ */ 17628 .balign 64 17629.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 17630/* File: armv5te/alt_stub.S */ 17631/* 17632 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17633 * any interesting requests and then jump to the real instruction 17634 * handler. Note that the call to dvmCheckInst is done as a tail call. 17635 */ 17636 adrl lr, dvmAsmInstructionStart + (278 * 64) 17637 mov r0, rPC @ arg0 17638 mov r1, rSELF @ arg1 17639 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17640 17641/* ------------------------------ */ 17642 .balign 64 17643.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 17644/* File: armv5te/alt_stub.S */ 17645/* 17646 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17647 * any interesting requests and then jump to the real instruction 17648 * handler. Note that the call to dvmCheckInst is done as a tail call. 17649 */ 17650 adrl lr, dvmAsmInstructionStart + (279 * 64) 17651 mov r0, rPC @ arg0 17652 mov r1, rSELF @ arg1 17653 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17654 17655/* ------------------------------ */ 17656 .balign 64 17657.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */ 17658/* File: armv5te/alt_stub.S */ 17659/* 17660 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17661 * any interesting requests and then jump to the real instruction 17662 * handler. Note that the call to dvmCheckInst is done as a tail call. 17663 */ 17664 adrl lr, dvmAsmInstructionStart + (280 * 64) 17665 mov r0, rPC @ arg0 17666 mov r1, rSELF @ arg1 17667 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17668 17669/* ------------------------------ */ 17670 .balign 64 17671.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */ 17672/* File: armv5te/alt_stub.S */ 17673/* 17674 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17675 * any interesting requests and then jump to the real instruction 17676 * handler. Note that the call to dvmCheckInst is done as a tail call. 17677 */ 17678 adrl lr, dvmAsmInstructionStart + (281 * 64) 17679 mov r0, rPC @ arg0 17680 mov r1, rSELF @ arg1 17681 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17682 17683/* ------------------------------ */ 17684 .balign 64 17685.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */ 17686/* File: armv5te/alt_stub.S */ 17687/* 17688 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17689 * any interesting requests and then jump to the real instruction 17690 * handler. Note that the call to dvmCheckInst is done as a tail call. 17691 */ 17692 adrl lr, dvmAsmInstructionStart + (282 * 64) 17693 mov r0, rPC @ arg0 17694 mov r1, rSELF @ arg1 17695 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17696 17697/* ------------------------------ */ 17698 .balign 64 17699.L_ALT_OP_SPUT_JUMBO: /* 0x11b */ 17700/* File: armv5te/alt_stub.S */ 17701/* 17702 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17703 * any interesting requests and then jump to the real instruction 17704 * handler. Note that the call to dvmCheckInst is done as a tail call. 17705 */ 17706 adrl lr, dvmAsmInstructionStart + (283 * 64) 17707 mov r0, rPC @ arg0 17708 mov r1, rSELF @ arg1 17709 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17710 17711/* ------------------------------ */ 17712 .balign 64 17713.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 17714/* File: armv5te/alt_stub.S */ 17715/* 17716 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17717 * any interesting requests and then jump to the real instruction 17718 * handler. Note that the call to dvmCheckInst is done as a tail call. 17719 */ 17720 adrl lr, dvmAsmInstructionStart + (284 * 64) 17721 mov r0, rPC @ arg0 17722 mov r1, rSELF @ arg1 17723 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17724 17725/* ------------------------------ */ 17726 .balign 64 17727.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 17728/* File: armv5te/alt_stub.S */ 17729/* 17730 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17731 * any interesting requests and then jump to the real instruction 17732 * handler. Note that the call to dvmCheckInst is done as a tail call. 17733 */ 17734 adrl lr, dvmAsmInstructionStart + (285 * 64) 17735 mov r0, rPC @ arg0 17736 mov r1, rSELF @ arg1 17737 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17738 17739/* ------------------------------ */ 17740 .balign 64 17741.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 17742/* File: armv5te/alt_stub.S */ 17743/* 17744 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17745 * any interesting requests and then jump to the real instruction 17746 * handler. Note that the call to dvmCheckInst is done as a tail call. 17747 */ 17748 adrl lr, dvmAsmInstructionStart + (286 * 64) 17749 mov r0, rPC @ arg0 17750 mov r1, rSELF @ arg1 17751 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17752 17753/* ------------------------------ */ 17754 .balign 64 17755.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 17756/* File: armv5te/alt_stub.S */ 17757/* 17758 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17759 * any interesting requests and then jump to the real instruction 17760 * handler. Note that the call to dvmCheckInst is done as a tail call. 17761 */ 17762 adrl lr, dvmAsmInstructionStart + (287 * 64) 17763 mov r0, rPC @ arg0 17764 mov r1, rSELF @ arg1 17765 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17766 17767/* ------------------------------ */ 17768 .balign 64 17769.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 17770/* File: armv5te/alt_stub.S */ 17771/* 17772 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17773 * any interesting requests and then jump to the real instruction 17774 * handler. Note that the call to dvmCheckInst is done as a tail call. 17775 */ 17776 adrl lr, dvmAsmInstructionStart + (288 * 64) 17777 mov r0, rPC @ arg0 17778 mov r1, rSELF @ arg1 17779 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17780 17781/* ------------------------------ */ 17782 .balign 64 17783.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 17784/* File: armv5te/alt_stub.S */ 17785/* 17786 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17787 * any interesting requests and then jump to the real instruction 17788 * handler. Note that the call to dvmCheckInst is done as a tail call. 17789 */ 17790 adrl lr, dvmAsmInstructionStart + (289 * 64) 17791 mov r0, rPC @ arg0 17792 mov r1, rSELF @ arg1 17793 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17794 17795/* ------------------------------ */ 17796 .balign 64 17797.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 17798/* File: armv5te/alt_stub.S */ 17799/* 17800 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17801 * any interesting requests and then jump to the real instruction 17802 * handler. Note that the call to dvmCheckInst is done as a tail call. 17803 */ 17804 adrl lr, dvmAsmInstructionStart + (290 * 64) 17805 mov r0, rPC @ arg0 17806 mov r1, rSELF @ arg1 17807 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17808 17809/* ------------------------------ */ 17810 .balign 64 17811.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 17812/* File: armv5te/alt_stub.S */ 17813/* 17814 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17815 * any interesting requests and then jump to the real instruction 17816 * handler. Note that the call to dvmCheckInst is done as a tail call. 17817 */ 17818 adrl lr, dvmAsmInstructionStart + (291 * 64) 17819 mov r0, rPC @ arg0 17820 mov r1, rSELF @ arg1 17821 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17822 17823/* ------------------------------ */ 17824 .balign 64 17825.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 17826/* File: armv5te/alt_stub.S */ 17827/* 17828 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17829 * any interesting requests and then jump to the real instruction 17830 * handler. Note that the call to dvmCheckInst is done as a tail call. 17831 */ 17832 adrl lr, dvmAsmInstructionStart + (292 * 64) 17833 mov r0, rPC @ arg0 17834 mov r1, rSELF @ arg1 17835 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17836 17837/* ------------------------------ */ 17838 .balign 64 17839.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 17840/* File: armv5te/alt_stub.S */ 17841/* 17842 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17843 * any interesting requests and then jump to the real instruction 17844 * handler. Note that the call to dvmCheckInst is done as a tail call. 17845 */ 17846 adrl lr, dvmAsmInstructionStart + (293 * 64) 17847 mov r0, rPC @ arg0 17848 mov r1, rSELF @ arg1 17849 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17850 17851/* ------------------------------ */ 17852 .balign 64 17853.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 17854/* File: armv5te/alt_stub.S */ 17855/* 17856 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17857 * any interesting requests and then jump to the real instruction 17858 * handler. Note that the call to dvmCheckInst is done as a tail call. 17859 */ 17860 adrl lr, dvmAsmInstructionStart + (294 * 64) 17861 mov r0, rPC @ arg0 17862 mov r1, rSELF @ arg1 17863 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17864 17865/* ------------------------------ */ 17866 .balign 64 17867.L_ALT_OP_UNUSED_27FF: /* 0x127 */ 17868/* File: armv5te/alt_stub.S */ 17869/* 17870 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17871 * any interesting requests and then jump to the real instruction 17872 * handler. Note that the call to dvmCheckInst is done as a tail call. 17873 */ 17874 adrl lr, dvmAsmInstructionStart + (295 * 64) 17875 mov r0, rPC @ arg0 17876 mov r1, rSELF @ arg1 17877 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17878 17879/* ------------------------------ */ 17880 .balign 64 17881.L_ALT_OP_UNUSED_28FF: /* 0x128 */ 17882/* File: armv5te/alt_stub.S */ 17883/* 17884 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17885 * any interesting requests and then jump to the real instruction 17886 * handler. Note that the call to dvmCheckInst is done as a tail call. 17887 */ 17888 adrl lr, dvmAsmInstructionStart + (296 * 64) 17889 mov r0, rPC @ arg0 17890 mov r1, rSELF @ arg1 17891 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17892 17893/* ------------------------------ */ 17894 .balign 64 17895.L_ALT_OP_UNUSED_29FF: /* 0x129 */ 17896/* File: armv5te/alt_stub.S */ 17897/* 17898 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17899 * any interesting requests and then jump to the real instruction 17900 * handler. Note that the call to dvmCheckInst is done as a tail call. 17901 */ 17902 adrl lr, dvmAsmInstructionStart + (297 * 64) 17903 mov r0, rPC @ arg0 17904 mov r1, rSELF @ arg1 17905 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17906 17907/* ------------------------------ */ 17908 .balign 64 17909.L_ALT_OP_UNUSED_2AFF: /* 0x12a */ 17910/* File: armv5te/alt_stub.S */ 17911/* 17912 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17913 * any interesting requests and then jump to the real instruction 17914 * handler. Note that the call to dvmCheckInst is done as a tail call. 17915 */ 17916 adrl lr, dvmAsmInstructionStart + (298 * 64) 17917 mov r0, rPC @ arg0 17918 mov r1, rSELF @ arg1 17919 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17920 17921/* ------------------------------ */ 17922 .balign 64 17923.L_ALT_OP_UNUSED_2BFF: /* 0x12b */ 17924/* File: armv5te/alt_stub.S */ 17925/* 17926 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17927 * any interesting requests and then jump to the real instruction 17928 * handler. Note that the call to dvmCheckInst is done as a tail call. 17929 */ 17930 adrl lr, dvmAsmInstructionStart + (299 * 64) 17931 mov r0, rPC @ arg0 17932 mov r1, rSELF @ arg1 17933 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17934 17935/* ------------------------------ */ 17936 .balign 64 17937.L_ALT_OP_UNUSED_2CFF: /* 0x12c */ 17938/* File: armv5te/alt_stub.S */ 17939/* 17940 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17941 * any interesting requests and then jump to the real instruction 17942 * handler. Note that the call to dvmCheckInst is done as a tail call. 17943 */ 17944 adrl lr, dvmAsmInstructionStart + (300 * 64) 17945 mov r0, rPC @ arg0 17946 mov r1, rSELF @ arg1 17947 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17948 17949/* ------------------------------ */ 17950 .balign 64 17951.L_ALT_OP_UNUSED_2DFF: /* 0x12d */ 17952/* File: armv5te/alt_stub.S */ 17953/* 17954 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17955 * any interesting requests and then jump to the real instruction 17956 * handler. Note that the call to dvmCheckInst is done as a tail call. 17957 */ 17958 adrl lr, dvmAsmInstructionStart + (301 * 64) 17959 mov r0, rPC @ arg0 17960 mov r1, rSELF @ arg1 17961 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17962 17963/* ------------------------------ */ 17964 .balign 64 17965.L_ALT_OP_UNUSED_2EFF: /* 0x12e */ 17966/* File: armv5te/alt_stub.S */ 17967/* 17968 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17969 * any interesting requests and then jump to the real instruction 17970 * handler. Note that the call to dvmCheckInst is done as a tail call. 17971 */ 17972 adrl lr, dvmAsmInstructionStart + (302 * 64) 17973 mov r0, rPC @ arg0 17974 mov r1, rSELF @ arg1 17975 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17976 17977/* ------------------------------ */ 17978 .balign 64 17979.L_ALT_OP_UNUSED_2FFF: /* 0x12f */ 17980/* File: armv5te/alt_stub.S */ 17981/* 17982 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17983 * any interesting requests and then jump to the real instruction 17984 * handler. Note that the call to dvmCheckInst is done as a tail call. 17985 */ 17986 adrl lr, dvmAsmInstructionStart + (303 * 64) 17987 mov r0, rPC @ arg0 17988 mov r1, rSELF @ arg1 17989 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17990 17991/* ------------------------------ */ 17992 .balign 64 17993.L_ALT_OP_UNUSED_30FF: /* 0x130 */ 17994/* File: armv5te/alt_stub.S */ 17995/* 17996 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17997 * any interesting requests and then jump to the real instruction 17998 * handler. Note that the call to dvmCheckInst is done as a tail call. 17999 */ 18000 adrl lr, dvmAsmInstructionStart + (304 * 64) 18001 mov r0, rPC @ arg0 18002 mov r1, rSELF @ arg1 18003 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18004 18005/* ------------------------------ */ 18006 .balign 64 18007.L_ALT_OP_UNUSED_31FF: /* 0x131 */ 18008/* File: armv5te/alt_stub.S */ 18009/* 18010 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18011 * any interesting requests and then jump to the real instruction 18012 * handler. Note that the call to dvmCheckInst is done as a tail call. 18013 */ 18014 adrl lr, dvmAsmInstructionStart + (305 * 64) 18015 mov r0, rPC @ arg0 18016 mov r1, rSELF @ arg1 18017 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18018 18019/* ------------------------------ */ 18020 .balign 64 18021.L_ALT_OP_UNUSED_32FF: /* 0x132 */ 18022/* File: armv5te/alt_stub.S */ 18023/* 18024 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18025 * any interesting requests and then jump to the real instruction 18026 * handler. Note that the call to dvmCheckInst is done as a tail call. 18027 */ 18028 adrl lr, dvmAsmInstructionStart + (306 * 64) 18029 mov r0, rPC @ arg0 18030 mov r1, rSELF @ arg1 18031 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18032 18033/* ------------------------------ */ 18034 .balign 64 18035.L_ALT_OP_UNUSED_33FF: /* 0x133 */ 18036/* File: armv5te/alt_stub.S */ 18037/* 18038 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18039 * any interesting requests and then jump to the real instruction 18040 * handler. Note that the call to dvmCheckInst is done as a tail call. 18041 */ 18042 adrl lr, dvmAsmInstructionStart + (307 * 64) 18043 mov r0, rPC @ arg0 18044 mov r1, rSELF @ arg1 18045 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18046 18047/* ------------------------------ */ 18048 .balign 64 18049.L_ALT_OP_UNUSED_34FF: /* 0x134 */ 18050/* File: armv5te/alt_stub.S */ 18051/* 18052 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18053 * any interesting requests and then jump to the real instruction 18054 * handler. Note that the call to dvmCheckInst is done as a tail call. 18055 */ 18056 adrl lr, dvmAsmInstructionStart + (308 * 64) 18057 mov r0, rPC @ arg0 18058 mov r1, rSELF @ arg1 18059 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18060 18061/* ------------------------------ */ 18062 .balign 64 18063.L_ALT_OP_UNUSED_35FF: /* 0x135 */ 18064/* File: armv5te/alt_stub.S */ 18065/* 18066 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18067 * any interesting requests and then jump to the real instruction 18068 * handler. Note that the call to dvmCheckInst is done as a tail call. 18069 */ 18070 adrl lr, dvmAsmInstructionStart + (309 * 64) 18071 mov r0, rPC @ arg0 18072 mov r1, rSELF @ arg1 18073 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18074 18075/* ------------------------------ */ 18076 .balign 64 18077.L_ALT_OP_UNUSED_36FF: /* 0x136 */ 18078/* File: armv5te/alt_stub.S */ 18079/* 18080 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18081 * any interesting requests and then jump to the real instruction 18082 * handler. Note that the call to dvmCheckInst is done as a tail call. 18083 */ 18084 adrl lr, dvmAsmInstructionStart + (310 * 64) 18085 mov r0, rPC @ arg0 18086 mov r1, rSELF @ arg1 18087 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18088 18089/* ------------------------------ */ 18090 .balign 64 18091.L_ALT_OP_UNUSED_37FF: /* 0x137 */ 18092/* File: armv5te/alt_stub.S */ 18093/* 18094 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18095 * any interesting requests and then jump to the real instruction 18096 * handler. Note that the call to dvmCheckInst is done as a tail call. 18097 */ 18098 adrl lr, dvmAsmInstructionStart + (311 * 64) 18099 mov r0, rPC @ arg0 18100 mov r1, rSELF @ arg1 18101 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18102 18103/* ------------------------------ */ 18104 .balign 64 18105.L_ALT_OP_UNUSED_38FF: /* 0x138 */ 18106/* File: armv5te/alt_stub.S */ 18107/* 18108 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18109 * any interesting requests and then jump to the real instruction 18110 * handler. Note that the call to dvmCheckInst is done as a tail call. 18111 */ 18112 adrl lr, dvmAsmInstructionStart + (312 * 64) 18113 mov r0, rPC @ arg0 18114 mov r1, rSELF @ arg1 18115 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18116 18117/* ------------------------------ */ 18118 .balign 64 18119.L_ALT_OP_UNUSED_39FF: /* 0x139 */ 18120/* File: armv5te/alt_stub.S */ 18121/* 18122 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18123 * any interesting requests and then jump to the real instruction 18124 * handler. Note that the call to dvmCheckInst is done as a tail call. 18125 */ 18126 adrl lr, dvmAsmInstructionStart + (313 * 64) 18127 mov r0, rPC @ arg0 18128 mov r1, rSELF @ arg1 18129 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18130 18131/* ------------------------------ */ 18132 .balign 64 18133.L_ALT_OP_UNUSED_3AFF: /* 0x13a */ 18134/* File: armv5te/alt_stub.S */ 18135/* 18136 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18137 * any interesting requests and then jump to the real instruction 18138 * handler. Note that the call to dvmCheckInst is done as a tail call. 18139 */ 18140 adrl lr, dvmAsmInstructionStart + (314 * 64) 18141 mov r0, rPC @ arg0 18142 mov r1, rSELF @ arg1 18143 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18144 18145/* ------------------------------ */ 18146 .balign 64 18147.L_ALT_OP_UNUSED_3BFF: /* 0x13b */ 18148/* File: armv5te/alt_stub.S */ 18149/* 18150 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18151 * any interesting requests and then jump to the real instruction 18152 * handler. Note that the call to dvmCheckInst is done as a tail call. 18153 */ 18154 adrl lr, dvmAsmInstructionStart + (315 * 64) 18155 mov r0, rPC @ arg0 18156 mov r1, rSELF @ arg1 18157 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18158 18159/* ------------------------------ */ 18160 .balign 64 18161.L_ALT_OP_UNUSED_3CFF: /* 0x13c */ 18162/* File: armv5te/alt_stub.S */ 18163/* 18164 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18165 * any interesting requests and then jump to the real instruction 18166 * handler. Note that the call to dvmCheckInst is done as a tail call. 18167 */ 18168 adrl lr, dvmAsmInstructionStart + (316 * 64) 18169 mov r0, rPC @ arg0 18170 mov r1, rSELF @ arg1 18171 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18172 18173/* ------------------------------ */ 18174 .balign 64 18175.L_ALT_OP_UNUSED_3DFF: /* 0x13d */ 18176/* File: armv5te/alt_stub.S */ 18177/* 18178 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18179 * any interesting requests and then jump to the real instruction 18180 * handler. Note that the call to dvmCheckInst is done as a tail call. 18181 */ 18182 adrl lr, dvmAsmInstructionStart + (317 * 64) 18183 mov r0, rPC @ arg0 18184 mov r1, rSELF @ arg1 18185 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18186 18187/* ------------------------------ */ 18188 .balign 64 18189.L_ALT_OP_UNUSED_3EFF: /* 0x13e */ 18190/* File: armv5te/alt_stub.S */ 18191/* 18192 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18193 * any interesting requests and then jump to the real instruction 18194 * handler. Note that the call to dvmCheckInst is done as a tail call. 18195 */ 18196 adrl lr, dvmAsmInstructionStart + (318 * 64) 18197 mov r0, rPC @ arg0 18198 mov r1, rSELF @ arg1 18199 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18200 18201/* ------------------------------ */ 18202 .balign 64 18203.L_ALT_OP_UNUSED_3FFF: /* 0x13f */ 18204/* File: armv5te/alt_stub.S */ 18205/* 18206 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18207 * any interesting requests and then jump to the real instruction 18208 * handler. Note that the call to dvmCheckInst is done as a tail call. 18209 */ 18210 adrl lr, dvmAsmInstructionStart + (319 * 64) 18211 mov r0, rPC @ arg0 18212 mov r1, rSELF @ arg1 18213 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18214 18215/* ------------------------------ */ 18216 .balign 64 18217.L_ALT_OP_UNUSED_40FF: /* 0x140 */ 18218/* File: armv5te/alt_stub.S */ 18219/* 18220 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18221 * any interesting requests and then jump to the real instruction 18222 * handler. Note that the call to dvmCheckInst is done as a tail call. 18223 */ 18224 adrl lr, dvmAsmInstructionStart + (320 * 64) 18225 mov r0, rPC @ arg0 18226 mov r1, rSELF @ arg1 18227 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18228 18229/* ------------------------------ */ 18230 .balign 64 18231.L_ALT_OP_UNUSED_41FF: /* 0x141 */ 18232/* File: armv5te/alt_stub.S */ 18233/* 18234 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18235 * any interesting requests and then jump to the real instruction 18236 * handler. Note that the call to dvmCheckInst is done as a tail call. 18237 */ 18238 adrl lr, dvmAsmInstructionStart + (321 * 64) 18239 mov r0, rPC @ arg0 18240 mov r1, rSELF @ arg1 18241 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18242 18243/* ------------------------------ */ 18244 .balign 64 18245.L_ALT_OP_UNUSED_42FF: /* 0x142 */ 18246/* File: armv5te/alt_stub.S */ 18247/* 18248 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18249 * any interesting requests and then jump to the real instruction 18250 * handler. Note that the call to dvmCheckInst is done as a tail call. 18251 */ 18252 adrl lr, dvmAsmInstructionStart + (322 * 64) 18253 mov r0, rPC @ arg0 18254 mov r1, rSELF @ arg1 18255 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18256 18257/* ------------------------------ */ 18258 .balign 64 18259.L_ALT_OP_UNUSED_43FF: /* 0x143 */ 18260/* File: armv5te/alt_stub.S */ 18261/* 18262 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18263 * any interesting requests and then jump to the real instruction 18264 * handler. Note that the call to dvmCheckInst is done as a tail call. 18265 */ 18266 adrl lr, dvmAsmInstructionStart + (323 * 64) 18267 mov r0, rPC @ arg0 18268 mov r1, rSELF @ arg1 18269 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18270 18271/* ------------------------------ */ 18272 .balign 64 18273.L_ALT_OP_UNUSED_44FF: /* 0x144 */ 18274/* File: armv5te/alt_stub.S */ 18275/* 18276 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18277 * any interesting requests and then jump to the real instruction 18278 * handler. Note that the call to dvmCheckInst is done as a tail call. 18279 */ 18280 adrl lr, dvmAsmInstructionStart + (324 * 64) 18281 mov r0, rPC @ arg0 18282 mov r1, rSELF @ arg1 18283 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18284 18285/* ------------------------------ */ 18286 .balign 64 18287.L_ALT_OP_UNUSED_45FF: /* 0x145 */ 18288/* File: armv5te/alt_stub.S */ 18289/* 18290 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18291 * any interesting requests and then jump to the real instruction 18292 * handler. Note that the call to dvmCheckInst is done as a tail call. 18293 */ 18294 adrl lr, dvmAsmInstructionStart + (325 * 64) 18295 mov r0, rPC @ arg0 18296 mov r1, rSELF @ arg1 18297 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18298 18299/* ------------------------------ */ 18300 .balign 64 18301.L_ALT_OP_UNUSED_46FF: /* 0x146 */ 18302/* File: armv5te/alt_stub.S */ 18303/* 18304 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18305 * any interesting requests and then jump to the real instruction 18306 * handler. Note that the call to dvmCheckInst is done as a tail call. 18307 */ 18308 adrl lr, dvmAsmInstructionStart + (326 * 64) 18309 mov r0, rPC @ arg0 18310 mov r1, rSELF @ arg1 18311 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18312 18313/* ------------------------------ */ 18314 .balign 64 18315.L_ALT_OP_UNUSED_47FF: /* 0x147 */ 18316/* File: armv5te/alt_stub.S */ 18317/* 18318 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18319 * any interesting requests and then jump to the real instruction 18320 * handler. Note that the call to dvmCheckInst is done as a tail call. 18321 */ 18322 adrl lr, dvmAsmInstructionStart + (327 * 64) 18323 mov r0, rPC @ arg0 18324 mov r1, rSELF @ arg1 18325 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18326 18327/* ------------------------------ */ 18328 .balign 64 18329.L_ALT_OP_UNUSED_48FF: /* 0x148 */ 18330/* File: armv5te/alt_stub.S */ 18331/* 18332 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18333 * any interesting requests and then jump to the real instruction 18334 * handler. Note that the call to dvmCheckInst is done as a tail call. 18335 */ 18336 adrl lr, dvmAsmInstructionStart + (328 * 64) 18337 mov r0, rPC @ arg0 18338 mov r1, rSELF @ arg1 18339 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18340 18341/* ------------------------------ */ 18342 .balign 64 18343.L_ALT_OP_UNUSED_49FF: /* 0x149 */ 18344/* File: armv5te/alt_stub.S */ 18345/* 18346 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18347 * any interesting requests and then jump to the real instruction 18348 * handler. Note that the call to dvmCheckInst is done as a tail call. 18349 */ 18350 adrl lr, dvmAsmInstructionStart + (329 * 64) 18351 mov r0, rPC @ arg0 18352 mov r1, rSELF @ arg1 18353 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18354 18355/* ------------------------------ */ 18356 .balign 64 18357.L_ALT_OP_UNUSED_4AFF: /* 0x14a */ 18358/* File: armv5te/alt_stub.S */ 18359/* 18360 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18361 * any interesting requests and then jump to the real instruction 18362 * handler. Note that the call to dvmCheckInst is done as a tail call. 18363 */ 18364 adrl lr, dvmAsmInstructionStart + (330 * 64) 18365 mov r0, rPC @ arg0 18366 mov r1, rSELF @ arg1 18367 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18368 18369/* ------------------------------ */ 18370 .balign 64 18371.L_ALT_OP_UNUSED_4BFF: /* 0x14b */ 18372/* File: armv5te/alt_stub.S */ 18373/* 18374 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18375 * any interesting requests and then jump to the real instruction 18376 * handler. Note that the call to dvmCheckInst is done as a tail call. 18377 */ 18378 adrl lr, dvmAsmInstructionStart + (331 * 64) 18379 mov r0, rPC @ arg0 18380 mov r1, rSELF @ arg1 18381 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18382 18383/* ------------------------------ */ 18384 .balign 64 18385.L_ALT_OP_UNUSED_4CFF: /* 0x14c */ 18386/* File: armv5te/alt_stub.S */ 18387/* 18388 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18389 * any interesting requests and then jump to the real instruction 18390 * handler. Note that the call to dvmCheckInst is done as a tail call. 18391 */ 18392 adrl lr, dvmAsmInstructionStart + (332 * 64) 18393 mov r0, rPC @ arg0 18394 mov r1, rSELF @ arg1 18395 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18396 18397/* ------------------------------ */ 18398 .balign 64 18399.L_ALT_OP_UNUSED_4DFF: /* 0x14d */ 18400/* File: armv5te/alt_stub.S */ 18401/* 18402 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18403 * any interesting requests and then jump to the real instruction 18404 * handler. Note that the call to dvmCheckInst is done as a tail call. 18405 */ 18406 adrl lr, dvmAsmInstructionStart + (333 * 64) 18407 mov r0, rPC @ arg0 18408 mov r1, rSELF @ arg1 18409 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18410 18411/* ------------------------------ */ 18412 .balign 64 18413.L_ALT_OP_UNUSED_4EFF: /* 0x14e */ 18414/* File: armv5te/alt_stub.S */ 18415/* 18416 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18417 * any interesting requests and then jump to the real instruction 18418 * handler. Note that the call to dvmCheckInst is done as a tail call. 18419 */ 18420 adrl lr, dvmAsmInstructionStart + (334 * 64) 18421 mov r0, rPC @ arg0 18422 mov r1, rSELF @ arg1 18423 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18424 18425/* ------------------------------ */ 18426 .balign 64 18427.L_ALT_OP_UNUSED_4FFF: /* 0x14f */ 18428/* File: armv5te/alt_stub.S */ 18429/* 18430 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18431 * any interesting requests and then jump to the real instruction 18432 * handler. Note that the call to dvmCheckInst is done as a tail call. 18433 */ 18434 adrl lr, dvmAsmInstructionStart + (335 * 64) 18435 mov r0, rPC @ arg0 18436 mov r1, rSELF @ arg1 18437 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18438 18439/* ------------------------------ */ 18440 .balign 64 18441.L_ALT_OP_UNUSED_50FF: /* 0x150 */ 18442/* File: armv5te/alt_stub.S */ 18443/* 18444 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18445 * any interesting requests and then jump to the real instruction 18446 * handler. Note that the call to dvmCheckInst is done as a tail call. 18447 */ 18448 adrl lr, dvmAsmInstructionStart + (336 * 64) 18449 mov r0, rPC @ arg0 18450 mov r1, rSELF @ arg1 18451 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18452 18453/* ------------------------------ */ 18454 .balign 64 18455.L_ALT_OP_UNUSED_51FF: /* 0x151 */ 18456/* File: armv5te/alt_stub.S */ 18457/* 18458 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18459 * any interesting requests and then jump to the real instruction 18460 * handler. Note that the call to dvmCheckInst is done as a tail call. 18461 */ 18462 adrl lr, dvmAsmInstructionStart + (337 * 64) 18463 mov r0, rPC @ arg0 18464 mov r1, rSELF @ arg1 18465 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18466 18467/* ------------------------------ */ 18468 .balign 64 18469.L_ALT_OP_UNUSED_52FF: /* 0x152 */ 18470/* File: armv5te/alt_stub.S */ 18471/* 18472 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18473 * any interesting requests and then jump to the real instruction 18474 * handler. Note that the call to dvmCheckInst is done as a tail call. 18475 */ 18476 adrl lr, dvmAsmInstructionStart + (338 * 64) 18477 mov r0, rPC @ arg0 18478 mov r1, rSELF @ arg1 18479 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18480 18481/* ------------------------------ */ 18482 .balign 64 18483.L_ALT_OP_UNUSED_53FF: /* 0x153 */ 18484/* File: armv5te/alt_stub.S */ 18485/* 18486 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18487 * any interesting requests and then jump to the real instruction 18488 * handler. Note that the call to dvmCheckInst is done as a tail call. 18489 */ 18490 adrl lr, dvmAsmInstructionStart + (339 * 64) 18491 mov r0, rPC @ arg0 18492 mov r1, rSELF @ arg1 18493 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18494 18495/* ------------------------------ */ 18496 .balign 64 18497.L_ALT_OP_UNUSED_54FF: /* 0x154 */ 18498/* File: armv5te/alt_stub.S */ 18499/* 18500 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18501 * any interesting requests and then jump to the real instruction 18502 * handler. Note that the call to dvmCheckInst is done as a tail call. 18503 */ 18504 adrl lr, dvmAsmInstructionStart + (340 * 64) 18505 mov r0, rPC @ arg0 18506 mov r1, rSELF @ arg1 18507 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18508 18509/* ------------------------------ */ 18510 .balign 64 18511.L_ALT_OP_UNUSED_55FF: /* 0x155 */ 18512/* File: armv5te/alt_stub.S */ 18513/* 18514 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18515 * any interesting requests and then jump to the real instruction 18516 * handler. Note that the call to dvmCheckInst is done as a tail call. 18517 */ 18518 adrl lr, dvmAsmInstructionStart + (341 * 64) 18519 mov r0, rPC @ arg0 18520 mov r1, rSELF @ arg1 18521 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18522 18523/* ------------------------------ */ 18524 .balign 64 18525.L_ALT_OP_UNUSED_56FF: /* 0x156 */ 18526/* File: armv5te/alt_stub.S */ 18527/* 18528 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18529 * any interesting requests and then jump to the real instruction 18530 * handler. Note that the call to dvmCheckInst is done as a tail call. 18531 */ 18532 adrl lr, dvmAsmInstructionStart + (342 * 64) 18533 mov r0, rPC @ arg0 18534 mov r1, rSELF @ arg1 18535 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18536 18537/* ------------------------------ */ 18538 .balign 64 18539.L_ALT_OP_UNUSED_57FF: /* 0x157 */ 18540/* File: armv5te/alt_stub.S */ 18541/* 18542 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18543 * any interesting requests and then jump to the real instruction 18544 * handler. Note that the call to dvmCheckInst is done as a tail call. 18545 */ 18546 adrl lr, dvmAsmInstructionStart + (343 * 64) 18547 mov r0, rPC @ arg0 18548 mov r1, rSELF @ arg1 18549 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18550 18551/* ------------------------------ */ 18552 .balign 64 18553.L_ALT_OP_UNUSED_58FF: /* 0x158 */ 18554/* File: armv5te/alt_stub.S */ 18555/* 18556 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18557 * any interesting requests and then jump to the real instruction 18558 * handler. Note that the call to dvmCheckInst is done as a tail call. 18559 */ 18560 adrl lr, dvmAsmInstructionStart + (344 * 64) 18561 mov r0, rPC @ arg0 18562 mov r1, rSELF @ arg1 18563 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18564 18565/* ------------------------------ */ 18566 .balign 64 18567.L_ALT_OP_UNUSED_59FF: /* 0x159 */ 18568/* File: armv5te/alt_stub.S */ 18569/* 18570 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18571 * any interesting requests and then jump to the real instruction 18572 * handler. Note that the call to dvmCheckInst is done as a tail call. 18573 */ 18574 adrl lr, dvmAsmInstructionStart + (345 * 64) 18575 mov r0, rPC @ arg0 18576 mov r1, rSELF @ arg1 18577 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18578 18579/* ------------------------------ */ 18580 .balign 64 18581.L_ALT_OP_UNUSED_5AFF: /* 0x15a */ 18582/* File: armv5te/alt_stub.S */ 18583/* 18584 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18585 * any interesting requests and then jump to the real instruction 18586 * handler. Note that the call to dvmCheckInst is done as a tail call. 18587 */ 18588 adrl lr, dvmAsmInstructionStart + (346 * 64) 18589 mov r0, rPC @ arg0 18590 mov r1, rSELF @ arg1 18591 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18592 18593/* ------------------------------ */ 18594 .balign 64 18595.L_ALT_OP_UNUSED_5BFF: /* 0x15b */ 18596/* File: armv5te/alt_stub.S */ 18597/* 18598 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18599 * any interesting requests and then jump to the real instruction 18600 * handler. Note that the call to dvmCheckInst is done as a tail call. 18601 */ 18602 adrl lr, dvmAsmInstructionStart + (347 * 64) 18603 mov r0, rPC @ arg0 18604 mov r1, rSELF @ arg1 18605 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18606 18607/* ------------------------------ */ 18608 .balign 64 18609.L_ALT_OP_UNUSED_5CFF: /* 0x15c */ 18610/* File: armv5te/alt_stub.S */ 18611/* 18612 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18613 * any interesting requests and then jump to the real instruction 18614 * handler. Note that the call to dvmCheckInst is done as a tail call. 18615 */ 18616 adrl lr, dvmAsmInstructionStart + (348 * 64) 18617 mov r0, rPC @ arg0 18618 mov r1, rSELF @ arg1 18619 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18620 18621/* ------------------------------ */ 18622 .balign 64 18623.L_ALT_OP_UNUSED_5DFF: /* 0x15d */ 18624/* File: armv5te/alt_stub.S */ 18625/* 18626 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18627 * any interesting requests and then jump to the real instruction 18628 * handler. Note that the call to dvmCheckInst is done as a tail call. 18629 */ 18630 adrl lr, dvmAsmInstructionStart + (349 * 64) 18631 mov r0, rPC @ arg0 18632 mov r1, rSELF @ arg1 18633 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18634 18635/* ------------------------------ */ 18636 .balign 64 18637.L_ALT_OP_UNUSED_5EFF: /* 0x15e */ 18638/* File: armv5te/alt_stub.S */ 18639/* 18640 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18641 * any interesting requests and then jump to the real instruction 18642 * handler. Note that the call to dvmCheckInst is done as a tail call. 18643 */ 18644 adrl lr, dvmAsmInstructionStart + (350 * 64) 18645 mov r0, rPC @ arg0 18646 mov r1, rSELF @ arg1 18647 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18648 18649/* ------------------------------ */ 18650 .balign 64 18651.L_ALT_OP_UNUSED_5FFF: /* 0x15f */ 18652/* File: armv5te/alt_stub.S */ 18653/* 18654 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18655 * any interesting requests and then jump to the real instruction 18656 * handler. Note that the call to dvmCheckInst is done as a tail call. 18657 */ 18658 adrl lr, dvmAsmInstructionStart + (351 * 64) 18659 mov r0, rPC @ arg0 18660 mov r1, rSELF @ arg1 18661 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18662 18663/* ------------------------------ */ 18664 .balign 64 18665.L_ALT_OP_UNUSED_60FF: /* 0x160 */ 18666/* File: armv5te/alt_stub.S */ 18667/* 18668 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18669 * any interesting requests and then jump to the real instruction 18670 * handler. Note that the call to dvmCheckInst is done as a tail call. 18671 */ 18672 adrl lr, dvmAsmInstructionStart + (352 * 64) 18673 mov r0, rPC @ arg0 18674 mov r1, rSELF @ arg1 18675 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18676 18677/* ------------------------------ */ 18678 .balign 64 18679.L_ALT_OP_UNUSED_61FF: /* 0x161 */ 18680/* File: armv5te/alt_stub.S */ 18681/* 18682 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18683 * any interesting requests and then jump to the real instruction 18684 * handler. Note that the call to dvmCheckInst is done as a tail call. 18685 */ 18686 adrl lr, dvmAsmInstructionStart + (353 * 64) 18687 mov r0, rPC @ arg0 18688 mov r1, rSELF @ arg1 18689 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18690 18691/* ------------------------------ */ 18692 .balign 64 18693.L_ALT_OP_UNUSED_62FF: /* 0x162 */ 18694/* File: armv5te/alt_stub.S */ 18695/* 18696 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18697 * any interesting requests and then jump to the real instruction 18698 * handler. Note that the call to dvmCheckInst is done as a tail call. 18699 */ 18700 adrl lr, dvmAsmInstructionStart + (354 * 64) 18701 mov r0, rPC @ arg0 18702 mov r1, rSELF @ arg1 18703 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18704 18705/* ------------------------------ */ 18706 .balign 64 18707.L_ALT_OP_UNUSED_63FF: /* 0x163 */ 18708/* File: armv5te/alt_stub.S */ 18709/* 18710 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18711 * any interesting requests and then jump to the real instruction 18712 * handler. Note that the call to dvmCheckInst is done as a tail call. 18713 */ 18714 adrl lr, dvmAsmInstructionStart + (355 * 64) 18715 mov r0, rPC @ arg0 18716 mov r1, rSELF @ arg1 18717 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18718 18719/* ------------------------------ */ 18720 .balign 64 18721.L_ALT_OP_UNUSED_64FF: /* 0x164 */ 18722/* File: armv5te/alt_stub.S */ 18723/* 18724 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18725 * any interesting requests and then jump to the real instruction 18726 * handler. Note that the call to dvmCheckInst is done as a tail call. 18727 */ 18728 adrl lr, dvmAsmInstructionStart + (356 * 64) 18729 mov r0, rPC @ arg0 18730 mov r1, rSELF @ arg1 18731 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18732 18733/* ------------------------------ */ 18734 .balign 64 18735.L_ALT_OP_UNUSED_65FF: /* 0x165 */ 18736/* File: armv5te/alt_stub.S */ 18737/* 18738 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18739 * any interesting requests and then jump to the real instruction 18740 * handler. Note that the call to dvmCheckInst is done as a tail call. 18741 */ 18742 adrl lr, dvmAsmInstructionStart + (357 * 64) 18743 mov r0, rPC @ arg0 18744 mov r1, rSELF @ arg1 18745 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18746 18747/* ------------------------------ */ 18748 .balign 64 18749.L_ALT_OP_UNUSED_66FF: /* 0x166 */ 18750/* File: armv5te/alt_stub.S */ 18751/* 18752 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18753 * any interesting requests and then jump to the real instruction 18754 * handler. Note that the call to dvmCheckInst is done as a tail call. 18755 */ 18756 adrl lr, dvmAsmInstructionStart + (358 * 64) 18757 mov r0, rPC @ arg0 18758 mov r1, rSELF @ arg1 18759 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18760 18761/* ------------------------------ */ 18762 .balign 64 18763.L_ALT_OP_UNUSED_67FF: /* 0x167 */ 18764/* File: armv5te/alt_stub.S */ 18765/* 18766 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18767 * any interesting requests and then jump to the real instruction 18768 * handler. Note that the call to dvmCheckInst is done as a tail call. 18769 */ 18770 adrl lr, dvmAsmInstructionStart + (359 * 64) 18771 mov r0, rPC @ arg0 18772 mov r1, rSELF @ arg1 18773 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18774 18775/* ------------------------------ */ 18776 .balign 64 18777.L_ALT_OP_UNUSED_68FF: /* 0x168 */ 18778/* File: armv5te/alt_stub.S */ 18779/* 18780 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18781 * any interesting requests and then jump to the real instruction 18782 * handler. Note that the call to dvmCheckInst is done as a tail call. 18783 */ 18784 adrl lr, dvmAsmInstructionStart + (360 * 64) 18785 mov r0, rPC @ arg0 18786 mov r1, rSELF @ arg1 18787 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18788 18789/* ------------------------------ */ 18790 .balign 64 18791.L_ALT_OP_UNUSED_69FF: /* 0x169 */ 18792/* File: armv5te/alt_stub.S */ 18793/* 18794 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18795 * any interesting requests and then jump to the real instruction 18796 * handler. Note that the call to dvmCheckInst is done as a tail call. 18797 */ 18798 adrl lr, dvmAsmInstructionStart + (361 * 64) 18799 mov r0, rPC @ arg0 18800 mov r1, rSELF @ arg1 18801 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18802 18803/* ------------------------------ */ 18804 .balign 64 18805.L_ALT_OP_UNUSED_6AFF: /* 0x16a */ 18806/* File: armv5te/alt_stub.S */ 18807/* 18808 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18809 * any interesting requests and then jump to the real instruction 18810 * handler. Note that the call to dvmCheckInst is done as a tail call. 18811 */ 18812 adrl lr, dvmAsmInstructionStart + (362 * 64) 18813 mov r0, rPC @ arg0 18814 mov r1, rSELF @ arg1 18815 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18816 18817/* ------------------------------ */ 18818 .balign 64 18819.L_ALT_OP_UNUSED_6BFF: /* 0x16b */ 18820/* File: armv5te/alt_stub.S */ 18821/* 18822 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18823 * any interesting requests and then jump to the real instruction 18824 * handler. Note that the call to dvmCheckInst is done as a tail call. 18825 */ 18826 adrl lr, dvmAsmInstructionStart + (363 * 64) 18827 mov r0, rPC @ arg0 18828 mov r1, rSELF @ arg1 18829 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18830 18831/* ------------------------------ */ 18832 .balign 64 18833.L_ALT_OP_UNUSED_6CFF: /* 0x16c */ 18834/* File: armv5te/alt_stub.S */ 18835/* 18836 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18837 * any interesting requests and then jump to the real instruction 18838 * handler. Note that the call to dvmCheckInst is done as a tail call. 18839 */ 18840 adrl lr, dvmAsmInstructionStart + (364 * 64) 18841 mov r0, rPC @ arg0 18842 mov r1, rSELF @ arg1 18843 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18844 18845/* ------------------------------ */ 18846 .balign 64 18847.L_ALT_OP_UNUSED_6DFF: /* 0x16d */ 18848/* File: armv5te/alt_stub.S */ 18849/* 18850 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18851 * any interesting requests and then jump to the real instruction 18852 * handler. Note that the call to dvmCheckInst is done as a tail call. 18853 */ 18854 adrl lr, dvmAsmInstructionStart + (365 * 64) 18855 mov r0, rPC @ arg0 18856 mov r1, rSELF @ arg1 18857 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18858 18859/* ------------------------------ */ 18860 .balign 64 18861.L_ALT_OP_UNUSED_6EFF: /* 0x16e */ 18862/* File: armv5te/alt_stub.S */ 18863/* 18864 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18865 * any interesting requests and then jump to the real instruction 18866 * handler. Note that the call to dvmCheckInst is done as a tail call. 18867 */ 18868 adrl lr, dvmAsmInstructionStart + (366 * 64) 18869 mov r0, rPC @ arg0 18870 mov r1, rSELF @ arg1 18871 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18872 18873/* ------------------------------ */ 18874 .balign 64 18875.L_ALT_OP_UNUSED_6FFF: /* 0x16f */ 18876/* File: armv5te/alt_stub.S */ 18877/* 18878 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18879 * any interesting requests and then jump to the real instruction 18880 * handler. Note that the call to dvmCheckInst is done as a tail call. 18881 */ 18882 adrl lr, dvmAsmInstructionStart + (367 * 64) 18883 mov r0, rPC @ arg0 18884 mov r1, rSELF @ arg1 18885 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18886 18887/* ------------------------------ */ 18888 .balign 64 18889.L_ALT_OP_UNUSED_70FF: /* 0x170 */ 18890/* File: armv5te/alt_stub.S */ 18891/* 18892 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18893 * any interesting requests and then jump to the real instruction 18894 * handler. Note that the call to dvmCheckInst is done as a tail call. 18895 */ 18896 adrl lr, dvmAsmInstructionStart + (368 * 64) 18897 mov r0, rPC @ arg0 18898 mov r1, rSELF @ arg1 18899 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18900 18901/* ------------------------------ */ 18902 .balign 64 18903.L_ALT_OP_UNUSED_71FF: /* 0x171 */ 18904/* File: armv5te/alt_stub.S */ 18905/* 18906 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18907 * any interesting requests and then jump to the real instruction 18908 * handler. Note that the call to dvmCheckInst is done as a tail call. 18909 */ 18910 adrl lr, dvmAsmInstructionStart + (369 * 64) 18911 mov r0, rPC @ arg0 18912 mov r1, rSELF @ arg1 18913 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18914 18915/* ------------------------------ */ 18916 .balign 64 18917.L_ALT_OP_UNUSED_72FF: /* 0x172 */ 18918/* File: armv5te/alt_stub.S */ 18919/* 18920 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18921 * any interesting requests and then jump to the real instruction 18922 * handler. Note that the call to dvmCheckInst is done as a tail call. 18923 */ 18924 adrl lr, dvmAsmInstructionStart + (370 * 64) 18925 mov r0, rPC @ arg0 18926 mov r1, rSELF @ arg1 18927 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18928 18929/* ------------------------------ */ 18930 .balign 64 18931.L_ALT_OP_UNUSED_73FF: /* 0x173 */ 18932/* File: armv5te/alt_stub.S */ 18933/* 18934 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18935 * any interesting requests and then jump to the real instruction 18936 * handler. Note that the call to dvmCheckInst is done as a tail call. 18937 */ 18938 adrl lr, dvmAsmInstructionStart + (371 * 64) 18939 mov r0, rPC @ arg0 18940 mov r1, rSELF @ arg1 18941 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18942 18943/* ------------------------------ */ 18944 .balign 64 18945.L_ALT_OP_UNUSED_74FF: /* 0x174 */ 18946/* File: armv5te/alt_stub.S */ 18947/* 18948 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18949 * any interesting requests and then jump to the real instruction 18950 * handler. Note that the call to dvmCheckInst is done as a tail call. 18951 */ 18952 adrl lr, dvmAsmInstructionStart + (372 * 64) 18953 mov r0, rPC @ arg0 18954 mov r1, rSELF @ arg1 18955 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18956 18957/* ------------------------------ */ 18958 .balign 64 18959.L_ALT_OP_UNUSED_75FF: /* 0x175 */ 18960/* File: armv5te/alt_stub.S */ 18961/* 18962 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18963 * any interesting requests and then jump to the real instruction 18964 * handler. Note that the call to dvmCheckInst is done as a tail call. 18965 */ 18966 adrl lr, dvmAsmInstructionStart + (373 * 64) 18967 mov r0, rPC @ arg0 18968 mov r1, rSELF @ arg1 18969 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18970 18971/* ------------------------------ */ 18972 .balign 64 18973.L_ALT_OP_UNUSED_76FF: /* 0x176 */ 18974/* File: armv5te/alt_stub.S */ 18975/* 18976 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18977 * any interesting requests and then jump to the real instruction 18978 * handler. Note that the call to dvmCheckInst is done as a tail call. 18979 */ 18980 adrl lr, dvmAsmInstructionStart + (374 * 64) 18981 mov r0, rPC @ arg0 18982 mov r1, rSELF @ arg1 18983 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18984 18985/* ------------------------------ */ 18986 .balign 64 18987.L_ALT_OP_UNUSED_77FF: /* 0x177 */ 18988/* File: armv5te/alt_stub.S */ 18989/* 18990 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18991 * any interesting requests and then jump to the real instruction 18992 * handler. Note that the call to dvmCheckInst is done as a tail call. 18993 */ 18994 adrl lr, dvmAsmInstructionStart + (375 * 64) 18995 mov r0, rPC @ arg0 18996 mov r1, rSELF @ arg1 18997 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18998 18999/* ------------------------------ */ 19000 .balign 64 19001.L_ALT_OP_UNUSED_78FF: /* 0x178 */ 19002/* File: armv5te/alt_stub.S */ 19003/* 19004 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19005 * any interesting requests and then jump to the real instruction 19006 * handler. Note that the call to dvmCheckInst is done as a tail call. 19007 */ 19008 adrl lr, dvmAsmInstructionStart + (376 * 64) 19009 mov r0, rPC @ arg0 19010 mov r1, rSELF @ arg1 19011 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19012 19013/* ------------------------------ */ 19014 .balign 64 19015.L_ALT_OP_UNUSED_79FF: /* 0x179 */ 19016/* File: armv5te/alt_stub.S */ 19017/* 19018 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19019 * any interesting requests and then jump to the real instruction 19020 * handler. Note that the call to dvmCheckInst is done as a tail call. 19021 */ 19022 adrl lr, dvmAsmInstructionStart + (377 * 64) 19023 mov r0, rPC @ arg0 19024 mov r1, rSELF @ arg1 19025 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19026 19027/* ------------------------------ */ 19028 .balign 64 19029.L_ALT_OP_UNUSED_7AFF: /* 0x17a */ 19030/* File: armv5te/alt_stub.S */ 19031/* 19032 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19033 * any interesting requests and then jump to the real instruction 19034 * handler. Note that the call to dvmCheckInst is done as a tail call. 19035 */ 19036 adrl lr, dvmAsmInstructionStart + (378 * 64) 19037 mov r0, rPC @ arg0 19038 mov r1, rSELF @ arg1 19039 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19040 19041/* ------------------------------ */ 19042 .balign 64 19043.L_ALT_OP_UNUSED_7BFF: /* 0x17b */ 19044/* File: armv5te/alt_stub.S */ 19045/* 19046 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19047 * any interesting requests and then jump to the real instruction 19048 * handler. Note that the call to dvmCheckInst is done as a tail call. 19049 */ 19050 adrl lr, dvmAsmInstructionStart + (379 * 64) 19051 mov r0, rPC @ arg0 19052 mov r1, rSELF @ arg1 19053 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19054 19055/* ------------------------------ */ 19056 .balign 64 19057.L_ALT_OP_UNUSED_7CFF: /* 0x17c */ 19058/* File: armv5te/alt_stub.S */ 19059/* 19060 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19061 * any interesting requests and then jump to the real instruction 19062 * handler. Note that the call to dvmCheckInst is done as a tail call. 19063 */ 19064 adrl lr, dvmAsmInstructionStart + (380 * 64) 19065 mov r0, rPC @ arg0 19066 mov r1, rSELF @ arg1 19067 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19068 19069/* ------------------------------ */ 19070 .balign 64 19071.L_ALT_OP_UNUSED_7DFF: /* 0x17d */ 19072/* File: armv5te/alt_stub.S */ 19073/* 19074 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19075 * any interesting requests and then jump to the real instruction 19076 * handler. Note that the call to dvmCheckInst is done as a tail call. 19077 */ 19078 adrl lr, dvmAsmInstructionStart + (381 * 64) 19079 mov r0, rPC @ arg0 19080 mov r1, rSELF @ arg1 19081 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19082 19083/* ------------------------------ */ 19084 .balign 64 19085.L_ALT_OP_UNUSED_7EFF: /* 0x17e */ 19086/* File: armv5te/alt_stub.S */ 19087/* 19088 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19089 * any interesting requests and then jump to the real instruction 19090 * handler. Note that the call to dvmCheckInst is done as a tail call. 19091 */ 19092 adrl lr, dvmAsmInstructionStart + (382 * 64) 19093 mov r0, rPC @ arg0 19094 mov r1, rSELF @ arg1 19095 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19096 19097/* ------------------------------ */ 19098 .balign 64 19099.L_ALT_OP_UNUSED_7FFF: /* 0x17f */ 19100/* File: armv5te/alt_stub.S */ 19101/* 19102 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19103 * any interesting requests and then jump to the real instruction 19104 * handler. Note that the call to dvmCheckInst is done as a tail call. 19105 */ 19106 adrl lr, dvmAsmInstructionStart + (383 * 64) 19107 mov r0, rPC @ arg0 19108 mov r1, rSELF @ arg1 19109 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19110 19111/* ------------------------------ */ 19112 .balign 64 19113.L_ALT_OP_UNUSED_80FF: /* 0x180 */ 19114/* File: armv5te/alt_stub.S */ 19115/* 19116 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19117 * any interesting requests and then jump to the real instruction 19118 * handler. Note that the call to dvmCheckInst is done as a tail call. 19119 */ 19120 adrl lr, dvmAsmInstructionStart + (384 * 64) 19121 mov r0, rPC @ arg0 19122 mov r1, rSELF @ arg1 19123 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19124 19125/* ------------------------------ */ 19126 .balign 64 19127.L_ALT_OP_UNUSED_81FF: /* 0x181 */ 19128/* File: armv5te/alt_stub.S */ 19129/* 19130 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19131 * any interesting requests and then jump to the real instruction 19132 * handler. Note that the call to dvmCheckInst is done as a tail call. 19133 */ 19134 adrl lr, dvmAsmInstructionStart + (385 * 64) 19135 mov r0, rPC @ arg0 19136 mov r1, rSELF @ arg1 19137 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19138 19139/* ------------------------------ */ 19140 .balign 64 19141.L_ALT_OP_UNUSED_82FF: /* 0x182 */ 19142/* File: armv5te/alt_stub.S */ 19143/* 19144 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19145 * any interesting requests and then jump to the real instruction 19146 * handler. Note that the call to dvmCheckInst is done as a tail call. 19147 */ 19148 adrl lr, dvmAsmInstructionStart + (386 * 64) 19149 mov r0, rPC @ arg0 19150 mov r1, rSELF @ arg1 19151 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19152 19153/* ------------------------------ */ 19154 .balign 64 19155.L_ALT_OP_UNUSED_83FF: /* 0x183 */ 19156/* File: armv5te/alt_stub.S */ 19157/* 19158 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19159 * any interesting requests and then jump to the real instruction 19160 * handler. Note that the call to dvmCheckInst is done as a tail call. 19161 */ 19162 adrl lr, dvmAsmInstructionStart + (387 * 64) 19163 mov r0, rPC @ arg0 19164 mov r1, rSELF @ arg1 19165 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19166 19167/* ------------------------------ */ 19168 .balign 64 19169.L_ALT_OP_UNUSED_84FF: /* 0x184 */ 19170/* File: armv5te/alt_stub.S */ 19171/* 19172 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19173 * any interesting requests and then jump to the real instruction 19174 * handler. Note that the call to dvmCheckInst is done as a tail call. 19175 */ 19176 adrl lr, dvmAsmInstructionStart + (388 * 64) 19177 mov r0, rPC @ arg0 19178 mov r1, rSELF @ arg1 19179 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19180 19181/* ------------------------------ */ 19182 .balign 64 19183.L_ALT_OP_UNUSED_85FF: /* 0x185 */ 19184/* File: armv5te/alt_stub.S */ 19185/* 19186 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19187 * any interesting requests and then jump to the real instruction 19188 * handler. Note that the call to dvmCheckInst is done as a tail call. 19189 */ 19190 adrl lr, dvmAsmInstructionStart + (389 * 64) 19191 mov r0, rPC @ arg0 19192 mov r1, rSELF @ arg1 19193 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19194 19195/* ------------------------------ */ 19196 .balign 64 19197.L_ALT_OP_UNUSED_86FF: /* 0x186 */ 19198/* File: armv5te/alt_stub.S */ 19199/* 19200 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19201 * any interesting requests and then jump to the real instruction 19202 * handler. Note that the call to dvmCheckInst is done as a tail call. 19203 */ 19204 adrl lr, dvmAsmInstructionStart + (390 * 64) 19205 mov r0, rPC @ arg0 19206 mov r1, rSELF @ arg1 19207 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19208 19209/* ------------------------------ */ 19210 .balign 64 19211.L_ALT_OP_UNUSED_87FF: /* 0x187 */ 19212/* File: armv5te/alt_stub.S */ 19213/* 19214 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19215 * any interesting requests and then jump to the real instruction 19216 * handler. Note that the call to dvmCheckInst is done as a tail call. 19217 */ 19218 adrl lr, dvmAsmInstructionStart + (391 * 64) 19219 mov r0, rPC @ arg0 19220 mov r1, rSELF @ arg1 19221 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19222 19223/* ------------------------------ */ 19224 .balign 64 19225.L_ALT_OP_UNUSED_88FF: /* 0x188 */ 19226/* File: armv5te/alt_stub.S */ 19227/* 19228 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19229 * any interesting requests and then jump to the real instruction 19230 * handler. Note that the call to dvmCheckInst is done as a tail call. 19231 */ 19232 adrl lr, dvmAsmInstructionStart + (392 * 64) 19233 mov r0, rPC @ arg0 19234 mov r1, rSELF @ arg1 19235 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19236 19237/* ------------------------------ */ 19238 .balign 64 19239.L_ALT_OP_UNUSED_89FF: /* 0x189 */ 19240/* File: armv5te/alt_stub.S */ 19241/* 19242 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19243 * any interesting requests and then jump to the real instruction 19244 * handler. Note that the call to dvmCheckInst is done as a tail call. 19245 */ 19246 adrl lr, dvmAsmInstructionStart + (393 * 64) 19247 mov r0, rPC @ arg0 19248 mov r1, rSELF @ arg1 19249 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19250 19251/* ------------------------------ */ 19252 .balign 64 19253.L_ALT_OP_UNUSED_8AFF: /* 0x18a */ 19254/* File: armv5te/alt_stub.S */ 19255/* 19256 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19257 * any interesting requests and then jump to the real instruction 19258 * handler. Note that the call to dvmCheckInst is done as a tail call. 19259 */ 19260 adrl lr, dvmAsmInstructionStart + (394 * 64) 19261 mov r0, rPC @ arg0 19262 mov r1, rSELF @ arg1 19263 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19264 19265/* ------------------------------ */ 19266 .balign 64 19267.L_ALT_OP_UNUSED_8BFF: /* 0x18b */ 19268/* File: armv5te/alt_stub.S */ 19269/* 19270 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19271 * any interesting requests and then jump to the real instruction 19272 * handler. Note that the call to dvmCheckInst is done as a tail call. 19273 */ 19274 adrl lr, dvmAsmInstructionStart + (395 * 64) 19275 mov r0, rPC @ arg0 19276 mov r1, rSELF @ arg1 19277 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19278 19279/* ------------------------------ */ 19280 .balign 64 19281.L_ALT_OP_UNUSED_8CFF: /* 0x18c */ 19282/* File: armv5te/alt_stub.S */ 19283/* 19284 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19285 * any interesting requests and then jump to the real instruction 19286 * handler. Note that the call to dvmCheckInst is done as a tail call. 19287 */ 19288 adrl lr, dvmAsmInstructionStart + (396 * 64) 19289 mov r0, rPC @ arg0 19290 mov r1, rSELF @ arg1 19291 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19292 19293/* ------------------------------ */ 19294 .balign 64 19295.L_ALT_OP_UNUSED_8DFF: /* 0x18d */ 19296/* File: armv5te/alt_stub.S */ 19297/* 19298 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19299 * any interesting requests and then jump to the real instruction 19300 * handler. Note that the call to dvmCheckInst is done as a tail call. 19301 */ 19302 adrl lr, dvmAsmInstructionStart + (397 * 64) 19303 mov r0, rPC @ arg0 19304 mov r1, rSELF @ arg1 19305 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19306 19307/* ------------------------------ */ 19308 .balign 64 19309.L_ALT_OP_UNUSED_8EFF: /* 0x18e */ 19310/* File: armv5te/alt_stub.S */ 19311/* 19312 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19313 * any interesting requests and then jump to the real instruction 19314 * handler. Note that the call to dvmCheckInst is done as a tail call. 19315 */ 19316 adrl lr, dvmAsmInstructionStart + (398 * 64) 19317 mov r0, rPC @ arg0 19318 mov r1, rSELF @ arg1 19319 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19320 19321/* ------------------------------ */ 19322 .balign 64 19323.L_ALT_OP_UNUSED_8FFF: /* 0x18f */ 19324/* File: armv5te/alt_stub.S */ 19325/* 19326 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19327 * any interesting requests and then jump to the real instruction 19328 * handler. Note that the call to dvmCheckInst is done as a tail call. 19329 */ 19330 adrl lr, dvmAsmInstructionStart + (399 * 64) 19331 mov r0, rPC @ arg0 19332 mov r1, rSELF @ arg1 19333 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19334 19335/* ------------------------------ */ 19336 .balign 64 19337.L_ALT_OP_UNUSED_90FF: /* 0x190 */ 19338/* File: armv5te/alt_stub.S */ 19339/* 19340 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19341 * any interesting requests and then jump to the real instruction 19342 * handler. Note that the call to dvmCheckInst is done as a tail call. 19343 */ 19344 adrl lr, dvmAsmInstructionStart + (400 * 64) 19345 mov r0, rPC @ arg0 19346 mov r1, rSELF @ arg1 19347 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19348 19349/* ------------------------------ */ 19350 .balign 64 19351.L_ALT_OP_UNUSED_91FF: /* 0x191 */ 19352/* File: armv5te/alt_stub.S */ 19353/* 19354 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19355 * any interesting requests and then jump to the real instruction 19356 * handler. Note that the call to dvmCheckInst is done as a tail call. 19357 */ 19358 adrl lr, dvmAsmInstructionStart + (401 * 64) 19359 mov r0, rPC @ arg0 19360 mov r1, rSELF @ arg1 19361 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19362 19363/* ------------------------------ */ 19364 .balign 64 19365.L_ALT_OP_UNUSED_92FF: /* 0x192 */ 19366/* File: armv5te/alt_stub.S */ 19367/* 19368 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19369 * any interesting requests and then jump to the real instruction 19370 * handler. Note that the call to dvmCheckInst is done as a tail call. 19371 */ 19372 adrl lr, dvmAsmInstructionStart + (402 * 64) 19373 mov r0, rPC @ arg0 19374 mov r1, rSELF @ arg1 19375 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19376 19377/* ------------------------------ */ 19378 .balign 64 19379.L_ALT_OP_UNUSED_93FF: /* 0x193 */ 19380/* File: armv5te/alt_stub.S */ 19381/* 19382 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19383 * any interesting requests and then jump to the real instruction 19384 * handler. Note that the call to dvmCheckInst is done as a tail call. 19385 */ 19386 adrl lr, dvmAsmInstructionStart + (403 * 64) 19387 mov r0, rPC @ arg0 19388 mov r1, rSELF @ arg1 19389 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19390 19391/* ------------------------------ */ 19392 .balign 64 19393.L_ALT_OP_UNUSED_94FF: /* 0x194 */ 19394/* File: armv5te/alt_stub.S */ 19395/* 19396 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19397 * any interesting requests and then jump to the real instruction 19398 * handler. Note that the call to dvmCheckInst is done as a tail call. 19399 */ 19400 adrl lr, dvmAsmInstructionStart + (404 * 64) 19401 mov r0, rPC @ arg0 19402 mov r1, rSELF @ arg1 19403 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19404 19405/* ------------------------------ */ 19406 .balign 64 19407.L_ALT_OP_UNUSED_95FF: /* 0x195 */ 19408/* File: armv5te/alt_stub.S */ 19409/* 19410 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19411 * any interesting requests and then jump to the real instruction 19412 * handler. Note that the call to dvmCheckInst is done as a tail call. 19413 */ 19414 adrl lr, dvmAsmInstructionStart + (405 * 64) 19415 mov r0, rPC @ arg0 19416 mov r1, rSELF @ arg1 19417 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19418 19419/* ------------------------------ */ 19420 .balign 64 19421.L_ALT_OP_UNUSED_96FF: /* 0x196 */ 19422/* File: armv5te/alt_stub.S */ 19423/* 19424 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19425 * any interesting requests and then jump to the real instruction 19426 * handler. Note that the call to dvmCheckInst is done as a tail call. 19427 */ 19428 adrl lr, dvmAsmInstructionStart + (406 * 64) 19429 mov r0, rPC @ arg0 19430 mov r1, rSELF @ arg1 19431 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19432 19433/* ------------------------------ */ 19434 .balign 64 19435.L_ALT_OP_UNUSED_97FF: /* 0x197 */ 19436/* File: armv5te/alt_stub.S */ 19437/* 19438 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19439 * any interesting requests and then jump to the real instruction 19440 * handler. Note that the call to dvmCheckInst is done as a tail call. 19441 */ 19442 adrl lr, dvmAsmInstructionStart + (407 * 64) 19443 mov r0, rPC @ arg0 19444 mov r1, rSELF @ arg1 19445 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19446 19447/* ------------------------------ */ 19448 .balign 64 19449.L_ALT_OP_UNUSED_98FF: /* 0x198 */ 19450/* File: armv5te/alt_stub.S */ 19451/* 19452 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19453 * any interesting requests and then jump to the real instruction 19454 * handler. Note that the call to dvmCheckInst is done as a tail call. 19455 */ 19456 adrl lr, dvmAsmInstructionStart + (408 * 64) 19457 mov r0, rPC @ arg0 19458 mov r1, rSELF @ arg1 19459 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19460 19461/* ------------------------------ */ 19462 .balign 64 19463.L_ALT_OP_UNUSED_99FF: /* 0x199 */ 19464/* File: armv5te/alt_stub.S */ 19465/* 19466 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19467 * any interesting requests and then jump to the real instruction 19468 * handler. Note that the call to dvmCheckInst is done as a tail call. 19469 */ 19470 adrl lr, dvmAsmInstructionStart + (409 * 64) 19471 mov r0, rPC @ arg0 19472 mov r1, rSELF @ arg1 19473 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19474 19475/* ------------------------------ */ 19476 .balign 64 19477.L_ALT_OP_UNUSED_9AFF: /* 0x19a */ 19478/* File: armv5te/alt_stub.S */ 19479/* 19480 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19481 * any interesting requests and then jump to the real instruction 19482 * handler. Note that the call to dvmCheckInst is done as a tail call. 19483 */ 19484 adrl lr, dvmAsmInstructionStart + (410 * 64) 19485 mov r0, rPC @ arg0 19486 mov r1, rSELF @ arg1 19487 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19488 19489/* ------------------------------ */ 19490 .balign 64 19491.L_ALT_OP_UNUSED_9BFF: /* 0x19b */ 19492/* File: armv5te/alt_stub.S */ 19493/* 19494 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19495 * any interesting requests and then jump to the real instruction 19496 * handler. Note that the call to dvmCheckInst is done as a tail call. 19497 */ 19498 adrl lr, dvmAsmInstructionStart + (411 * 64) 19499 mov r0, rPC @ arg0 19500 mov r1, rSELF @ arg1 19501 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19502 19503/* ------------------------------ */ 19504 .balign 64 19505.L_ALT_OP_UNUSED_9CFF: /* 0x19c */ 19506/* File: armv5te/alt_stub.S */ 19507/* 19508 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19509 * any interesting requests and then jump to the real instruction 19510 * handler. Note that the call to dvmCheckInst is done as a tail call. 19511 */ 19512 adrl lr, dvmAsmInstructionStart + (412 * 64) 19513 mov r0, rPC @ arg0 19514 mov r1, rSELF @ arg1 19515 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19516 19517/* ------------------------------ */ 19518 .balign 64 19519.L_ALT_OP_UNUSED_9DFF: /* 0x19d */ 19520/* File: armv5te/alt_stub.S */ 19521/* 19522 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19523 * any interesting requests and then jump to the real instruction 19524 * handler. Note that the call to dvmCheckInst is done as a tail call. 19525 */ 19526 adrl lr, dvmAsmInstructionStart + (413 * 64) 19527 mov r0, rPC @ arg0 19528 mov r1, rSELF @ arg1 19529 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19530 19531/* ------------------------------ */ 19532 .balign 64 19533.L_ALT_OP_UNUSED_9EFF: /* 0x19e */ 19534/* File: armv5te/alt_stub.S */ 19535/* 19536 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19537 * any interesting requests and then jump to the real instruction 19538 * handler. Note that the call to dvmCheckInst is done as a tail call. 19539 */ 19540 adrl lr, dvmAsmInstructionStart + (414 * 64) 19541 mov r0, rPC @ arg0 19542 mov r1, rSELF @ arg1 19543 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19544 19545/* ------------------------------ */ 19546 .balign 64 19547.L_ALT_OP_UNUSED_9FFF: /* 0x19f */ 19548/* File: armv5te/alt_stub.S */ 19549/* 19550 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19551 * any interesting requests and then jump to the real instruction 19552 * handler. Note that the call to dvmCheckInst is done as a tail call. 19553 */ 19554 adrl lr, dvmAsmInstructionStart + (415 * 64) 19555 mov r0, rPC @ arg0 19556 mov r1, rSELF @ arg1 19557 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19558 19559/* ------------------------------ */ 19560 .balign 64 19561.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */ 19562/* File: armv5te/alt_stub.S */ 19563/* 19564 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19565 * any interesting requests and then jump to the real instruction 19566 * handler. Note that the call to dvmCheckInst is done as a tail call. 19567 */ 19568 adrl lr, dvmAsmInstructionStart + (416 * 64) 19569 mov r0, rPC @ arg0 19570 mov r1, rSELF @ arg1 19571 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19572 19573/* ------------------------------ */ 19574 .balign 64 19575.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */ 19576/* File: armv5te/alt_stub.S */ 19577/* 19578 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19579 * any interesting requests and then jump to the real instruction 19580 * handler. Note that the call to dvmCheckInst is done as a tail call. 19581 */ 19582 adrl lr, dvmAsmInstructionStart + (417 * 64) 19583 mov r0, rPC @ arg0 19584 mov r1, rSELF @ arg1 19585 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19586 19587/* ------------------------------ */ 19588 .balign 64 19589.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */ 19590/* File: armv5te/alt_stub.S */ 19591/* 19592 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19593 * any interesting requests and then jump to the real instruction 19594 * handler. Note that the call to dvmCheckInst is done as a tail call. 19595 */ 19596 adrl lr, dvmAsmInstructionStart + (418 * 64) 19597 mov r0, rPC @ arg0 19598 mov r1, rSELF @ arg1 19599 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19600 19601/* ------------------------------ */ 19602 .balign 64 19603.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */ 19604/* File: armv5te/alt_stub.S */ 19605/* 19606 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19607 * any interesting requests and then jump to the real instruction 19608 * handler. Note that the call to dvmCheckInst is done as a tail call. 19609 */ 19610 adrl lr, dvmAsmInstructionStart + (419 * 64) 19611 mov r0, rPC @ arg0 19612 mov r1, rSELF @ arg1 19613 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19614 19615/* ------------------------------ */ 19616 .balign 64 19617.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */ 19618/* File: armv5te/alt_stub.S */ 19619/* 19620 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19621 * any interesting requests and then jump to the real instruction 19622 * handler. Note that the call to dvmCheckInst is done as a tail call. 19623 */ 19624 adrl lr, dvmAsmInstructionStart + (420 * 64) 19625 mov r0, rPC @ arg0 19626 mov r1, rSELF @ arg1 19627 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19628 19629/* ------------------------------ */ 19630 .balign 64 19631.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */ 19632/* File: armv5te/alt_stub.S */ 19633/* 19634 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19635 * any interesting requests and then jump to the real instruction 19636 * handler. Note that the call to dvmCheckInst is done as a tail call. 19637 */ 19638 adrl lr, dvmAsmInstructionStart + (421 * 64) 19639 mov r0, rPC @ arg0 19640 mov r1, rSELF @ arg1 19641 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19642 19643/* ------------------------------ */ 19644 .balign 64 19645.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */ 19646/* File: armv5te/alt_stub.S */ 19647/* 19648 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19649 * any interesting requests and then jump to the real instruction 19650 * handler. Note that the call to dvmCheckInst is done as a tail call. 19651 */ 19652 adrl lr, dvmAsmInstructionStart + (422 * 64) 19653 mov r0, rPC @ arg0 19654 mov r1, rSELF @ arg1 19655 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19656 19657/* ------------------------------ */ 19658 .balign 64 19659.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */ 19660/* File: armv5te/alt_stub.S */ 19661/* 19662 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19663 * any interesting requests and then jump to the real instruction 19664 * handler. Note that the call to dvmCheckInst is done as a tail call. 19665 */ 19666 adrl lr, dvmAsmInstructionStart + (423 * 64) 19667 mov r0, rPC @ arg0 19668 mov r1, rSELF @ arg1 19669 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19670 19671/* ------------------------------ */ 19672 .balign 64 19673.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */ 19674/* File: armv5te/alt_stub.S */ 19675/* 19676 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19677 * any interesting requests and then jump to the real instruction 19678 * handler. Note that the call to dvmCheckInst is done as a tail call. 19679 */ 19680 adrl lr, dvmAsmInstructionStart + (424 * 64) 19681 mov r0, rPC @ arg0 19682 mov r1, rSELF @ arg1 19683 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19684 19685/* ------------------------------ */ 19686 .balign 64 19687.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */ 19688/* File: armv5te/alt_stub.S */ 19689/* 19690 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19691 * any interesting requests and then jump to the real instruction 19692 * handler. Note that the call to dvmCheckInst is done as a tail call. 19693 */ 19694 adrl lr, dvmAsmInstructionStart + (425 * 64) 19695 mov r0, rPC @ arg0 19696 mov r1, rSELF @ arg1 19697 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19698 19699/* ------------------------------ */ 19700 .balign 64 19701.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */ 19702/* File: armv5te/alt_stub.S */ 19703/* 19704 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19705 * any interesting requests and then jump to the real instruction 19706 * handler. Note that the call to dvmCheckInst is done as a tail call. 19707 */ 19708 adrl lr, dvmAsmInstructionStart + (426 * 64) 19709 mov r0, rPC @ arg0 19710 mov r1, rSELF @ arg1 19711 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19712 19713/* ------------------------------ */ 19714 .balign 64 19715.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */ 19716/* File: armv5te/alt_stub.S */ 19717/* 19718 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19719 * any interesting requests and then jump to the real instruction 19720 * handler. Note that the call to dvmCheckInst is done as a tail call. 19721 */ 19722 adrl lr, dvmAsmInstructionStart + (427 * 64) 19723 mov r0, rPC @ arg0 19724 mov r1, rSELF @ arg1 19725 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19726 19727/* ------------------------------ */ 19728 .balign 64 19729.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */ 19730/* File: armv5te/alt_stub.S */ 19731/* 19732 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19733 * any interesting requests and then jump to the real instruction 19734 * handler. Note that the call to dvmCheckInst is done as a tail call. 19735 */ 19736 adrl lr, dvmAsmInstructionStart + (428 * 64) 19737 mov r0, rPC @ arg0 19738 mov r1, rSELF @ arg1 19739 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19740 19741/* ------------------------------ */ 19742 .balign 64 19743.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */ 19744/* File: armv5te/alt_stub.S */ 19745/* 19746 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19747 * any interesting requests and then jump to the real instruction 19748 * handler. Note that the call to dvmCheckInst is done as a tail call. 19749 */ 19750 adrl lr, dvmAsmInstructionStart + (429 * 64) 19751 mov r0, rPC @ arg0 19752 mov r1, rSELF @ arg1 19753 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19754 19755/* ------------------------------ */ 19756 .balign 64 19757.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */ 19758/* File: armv5te/alt_stub.S */ 19759/* 19760 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19761 * any interesting requests and then jump to the real instruction 19762 * handler. Note that the call to dvmCheckInst is done as a tail call. 19763 */ 19764 adrl lr, dvmAsmInstructionStart + (430 * 64) 19765 mov r0, rPC @ arg0 19766 mov r1, rSELF @ arg1 19767 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19768 19769/* ------------------------------ */ 19770 .balign 64 19771.L_ALT_OP_UNUSED_AFFF: /* 0x1af */ 19772/* File: armv5te/alt_stub.S */ 19773/* 19774 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19775 * any interesting requests and then jump to the real instruction 19776 * handler. Note that the call to dvmCheckInst is done as a tail call. 19777 */ 19778 adrl lr, dvmAsmInstructionStart + (431 * 64) 19779 mov r0, rPC @ arg0 19780 mov r1, rSELF @ arg1 19781 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19782 19783/* ------------------------------ */ 19784 .balign 64 19785.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */ 19786/* File: armv5te/alt_stub.S */ 19787/* 19788 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19789 * any interesting requests and then jump to the real instruction 19790 * handler. Note that the call to dvmCheckInst is done as a tail call. 19791 */ 19792 adrl lr, dvmAsmInstructionStart + (432 * 64) 19793 mov r0, rPC @ arg0 19794 mov r1, rSELF @ arg1 19795 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19796 19797/* ------------------------------ */ 19798 .balign 64 19799.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */ 19800/* File: armv5te/alt_stub.S */ 19801/* 19802 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19803 * any interesting requests and then jump to the real instruction 19804 * handler. Note that the call to dvmCheckInst is done as a tail call. 19805 */ 19806 adrl lr, dvmAsmInstructionStart + (433 * 64) 19807 mov r0, rPC @ arg0 19808 mov r1, rSELF @ arg1 19809 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19810 19811/* ------------------------------ */ 19812 .balign 64 19813.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */ 19814/* File: armv5te/alt_stub.S */ 19815/* 19816 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19817 * any interesting requests and then jump to the real instruction 19818 * handler. Note that the call to dvmCheckInst is done as a tail call. 19819 */ 19820 adrl lr, dvmAsmInstructionStart + (434 * 64) 19821 mov r0, rPC @ arg0 19822 mov r1, rSELF @ arg1 19823 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19824 19825/* ------------------------------ */ 19826 .balign 64 19827.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */ 19828/* File: armv5te/alt_stub.S */ 19829/* 19830 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19831 * any interesting requests and then jump to the real instruction 19832 * handler. Note that the call to dvmCheckInst is done as a tail call. 19833 */ 19834 adrl lr, dvmAsmInstructionStart + (435 * 64) 19835 mov r0, rPC @ arg0 19836 mov r1, rSELF @ arg1 19837 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19838 19839/* ------------------------------ */ 19840 .balign 64 19841.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */ 19842/* File: armv5te/alt_stub.S */ 19843/* 19844 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19845 * any interesting requests and then jump to the real instruction 19846 * handler. Note that the call to dvmCheckInst is done as a tail call. 19847 */ 19848 adrl lr, dvmAsmInstructionStart + (436 * 64) 19849 mov r0, rPC @ arg0 19850 mov r1, rSELF @ arg1 19851 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19852 19853/* ------------------------------ */ 19854 .balign 64 19855.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */ 19856/* File: armv5te/alt_stub.S */ 19857/* 19858 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19859 * any interesting requests and then jump to the real instruction 19860 * handler. Note that the call to dvmCheckInst is done as a tail call. 19861 */ 19862 adrl lr, dvmAsmInstructionStart + (437 * 64) 19863 mov r0, rPC @ arg0 19864 mov r1, rSELF @ arg1 19865 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19866 19867/* ------------------------------ */ 19868 .balign 64 19869.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */ 19870/* File: armv5te/alt_stub.S */ 19871/* 19872 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19873 * any interesting requests and then jump to the real instruction 19874 * handler. Note that the call to dvmCheckInst is done as a tail call. 19875 */ 19876 adrl lr, dvmAsmInstructionStart + (438 * 64) 19877 mov r0, rPC @ arg0 19878 mov r1, rSELF @ arg1 19879 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19880 19881/* ------------------------------ */ 19882 .balign 64 19883.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */ 19884/* File: armv5te/alt_stub.S */ 19885/* 19886 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19887 * any interesting requests and then jump to the real instruction 19888 * handler. Note that the call to dvmCheckInst is done as a tail call. 19889 */ 19890 adrl lr, dvmAsmInstructionStart + (439 * 64) 19891 mov r0, rPC @ arg0 19892 mov r1, rSELF @ arg1 19893 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19894 19895/* ------------------------------ */ 19896 .balign 64 19897.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */ 19898/* File: armv5te/alt_stub.S */ 19899/* 19900 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19901 * any interesting requests and then jump to the real instruction 19902 * handler. Note that the call to dvmCheckInst is done as a tail call. 19903 */ 19904 adrl lr, dvmAsmInstructionStart + (440 * 64) 19905 mov r0, rPC @ arg0 19906 mov r1, rSELF @ arg1 19907 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19908 19909/* ------------------------------ */ 19910 .balign 64 19911.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */ 19912/* File: armv5te/alt_stub.S */ 19913/* 19914 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19915 * any interesting requests and then jump to the real instruction 19916 * handler. Note that the call to dvmCheckInst is done as a tail call. 19917 */ 19918 adrl lr, dvmAsmInstructionStart + (441 * 64) 19919 mov r0, rPC @ arg0 19920 mov r1, rSELF @ arg1 19921 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19922 19923/* ------------------------------ */ 19924 .balign 64 19925.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */ 19926/* File: armv5te/alt_stub.S */ 19927/* 19928 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19929 * any interesting requests and then jump to the real instruction 19930 * handler. Note that the call to dvmCheckInst is done as a tail call. 19931 */ 19932 adrl lr, dvmAsmInstructionStart + (442 * 64) 19933 mov r0, rPC @ arg0 19934 mov r1, rSELF @ arg1 19935 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19936 19937/* ------------------------------ */ 19938 .balign 64 19939.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */ 19940/* File: armv5te/alt_stub.S */ 19941/* 19942 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19943 * any interesting requests and then jump to the real instruction 19944 * handler. Note that the call to dvmCheckInst is done as a tail call. 19945 */ 19946 adrl lr, dvmAsmInstructionStart + (443 * 64) 19947 mov r0, rPC @ arg0 19948 mov r1, rSELF @ arg1 19949 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19950 19951/* ------------------------------ */ 19952 .balign 64 19953.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */ 19954/* File: armv5te/alt_stub.S */ 19955/* 19956 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19957 * any interesting requests and then jump to the real instruction 19958 * handler. Note that the call to dvmCheckInst is done as a tail call. 19959 */ 19960 adrl lr, dvmAsmInstructionStart + (444 * 64) 19961 mov r0, rPC @ arg0 19962 mov r1, rSELF @ arg1 19963 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19964 19965/* ------------------------------ */ 19966 .balign 64 19967.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */ 19968/* File: armv5te/alt_stub.S */ 19969/* 19970 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19971 * any interesting requests and then jump to the real instruction 19972 * handler. Note that the call to dvmCheckInst is done as a tail call. 19973 */ 19974 adrl lr, dvmAsmInstructionStart + (445 * 64) 19975 mov r0, rPC @ arg0 19976 mov r1, rSELF @ arg1 19977 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19978 19979/* ------------------------------ */ 19980 .balign 64 19981.L_ALT_OP_UNUSED_BEFF: /* 0x1be */ 19982/* File: armv5te/alt_stub.S */ 19983/* 19984 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19985 * any interesting requests and then jump to the real instruction 19986 * handler. Note that the call to dvmCheckInst is done as a tail call. 19987 */ 19988 adrl lr, dvmAsmInstructionStart + (446 * 64) 19989 mov r0, rPC @ arg0 19990 mov r1, rSELF @ arg1 19991 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19992 19993/* ------------------------------ */ 19994 .balign 64 19995.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */ 19996/* File: armv5te/alt_stub.S */ 19997/* 19998 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19999 * any interesting requests and then jump to the real instruction 20000 * handler. Note that the call to dvmCheckInst is done as a tail call. 20001 */ 20002 adrl lr, dvmAsmInstructionStart + (447 * 64) 20003 mov r0, rPC @ arg0 20004 mov r1, rSELF @ arg1 20005 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20006 20007/* ------------------------------ */ 20008 .balign 64 20009.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */ 20010/* File: armv5te/alt_stub.S */ 20011/* 20012 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20013 * any interesting requests and then jump to the real instruction 20014 * handler. Note that the call to dvmCheckInst is done as a tail call. 20015 */ 20016 adrl lr, dvmAsmInstructionStart + (448 * 64) 20017 mov r0, rPC @ arg0 20018 mov r1, rSELF @ arg1 20019 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20020 20021/* ------------------------------ */ 20022 .balign 64 20023.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */ 20024/* File: armv5te/alt_stub.S */ 20025/* 20026 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20027 * any interesting requests and then jump to the real instruction 20028 * handler. Note that the call to dvmCheckInst is done as a tail call. 20029 */ 20030 adrl lr, dvmAsmInstructionStart + (449 * 64) 20031 mov r0, rPC @ arg0 20032 mov r1, rSELF @ arg1 20033 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20034 20035/* ------------------------------ */ 20036 .balign 64 20037.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */ 20038/* File: armv5te/alt_stub.S */ 20039/* 20040 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20041 * any interesting requests and then jump to the real instruction 20042 * handler. Note that the call to dvmCheckInst is done as a tail call. 20043 */ 20044 adrl lr, dvmAsmInstructionStart + (450 * 64) 20045 mov r0, rPC @ arg0 20046 mov r1, rSELF @ arg1 20047 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20048 20049/* ------------------------------ */ 20050 .balign 64 20051.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */ 20052/* File: armv5te/alt_stub.S */ 20053/* 20054 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20055 * any interesting requests and then jump to the real instruction 20056 * handler. Note that the call to dvmCheckInst is done as a tail call. 20057 */ 20058 adrl lr, dvmAsmInstructionStart + (451 * 64) 20059 mov r0, rPC @ arg0 20060 mov r1, rSELF @ arg1 20061 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20062 20063/* ------------------------------ */ 20064 .balign 64 20065.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */ 20066/* File: armv5te/alt_stub.S */ 20067/* 20068 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20069 * any interesting requests and then jump to the real instruction 20070 * handler. Note that the call to dvmCheckInst is done as a tail call. 20071 */ 20072 adrl lr, dvmAsmInstructionStart + (452 * 64) 20073 mov r0, rPC @ arg0 20074 mov r1, rSELF @ arg1 20075 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20076 20077/* ------------------------------ */ 20078 .balign 64 20079.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */ 20080/* File: armv5te/alt_stub.S */ 20081/* 20082 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20083 * any interesting requests and then jump to the real instruction 20084 * handler. Note that the call to dvmCheckInst is done as a tail call. 20085 */ 20086 adrl lr, dvmAsmInstructionStart + (453 * 64) 20087 mov r0, rPC @ arg0 20088 mov r1, rSELF @ arg1 20089 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20090 20091/* ------------------------------ */ 20092 .balign 64 20093.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */ 20094/* File: armv5te/alt_stub.S */ 20095/* 20096 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20097 * any interesting requests and then jump to the real instruction 20098 * handler. Note that the call to dvmCheckInst is done as a tail call. 20099 */ 20100 adrl lr, dvmAsmInstructionStart + (454 * 64) 20101 mov r0, rPC @ arg0 20102 mov r1, rSELF @ arg1 20103 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20104 20105/* ------------------------------ */ 20106 .balign 64 20107.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */ 20108/* File: armv5te/alt_stub.S */ 20109/* 20110 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20111 * any interesting requests and then jump to the real instruction 20112 * handler. Note that the call to dvmCheckInst is done as a tail call. 20113 */ 20114 adrl lr, dvmAsmInstructionStart + (455 * 64) 20115 mov r0, rPC @ arg0 20116 mov r1, rSELF @ arg1 20117 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20118 20119/* ------------------------------ */ 20120 .balign 64 20121.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */ 20122/* File: armv5te/alt_stub.S */ 20123/* 20124 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20125 * any interesting requests and then jump to the real instruction 20126 * handler. Note that the call to dvmCheckInst is done as a tail call. 20127 */ 20128 adrl lr, dvmAsmInstructionStart + (456 * 64) 20129 mov r0, rPC @ arg0 20130 mov r1, rSELF @ arg1 20131 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20132 20133/* ------------------------------ */ 20134 .balign 64 20135.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */ 20136/* File: armv5te/alt_stub.S */ 20137/* 20138 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20139 * any interesting requests and then jump to the real instruction 20140 * handler. Note that the call to dvmCheckInst is done as a tail call. 20141 */ 20142 adrl lr, dvmAsmInstructionStart + (457 * 64) 20143 mov r0, rPC @ arg0 20144 mov r1, rSELF @ arg1 20145 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20146 20147/* ------------------------------ */ 20148 .balign 64 20149.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */ 20150/* File: armv5te/alt_stub.S */ 20151/* 20152 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20153 * any interesting requests and then jump to the real instruction 20154 * handler. Note that the call to dvmCheckInst is done as a tail call. 20155 */ 20156 adrl lr, dvmAsmInstructionStart + (458 * 64) 20157 mov r0, rPC @ arg0 20158 mov r1, rSELF @ arg1 20159 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20160 20161/* ------------------------------ */ 20162 .balign 64 20163.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */ 20164/* File: armv5te/alt_stub.S */ 20165/* 20166 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20167 * any interesting requests and then jump to the real instruction 20168 * handler. Note that the call to dvmCheckInst is done as a tail call. 20169 */ 20170 adrl lr, dvmAsmInstructionStart + (459 * 64) 20171 mov r0, rPC @ arg0 20172 mov r1, rSELF @ arg1 20173 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20174 20175/* ------------------------------ */ 20176 .balign 64 20177.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */ 20178/* File: armv5te/alt_stub.S */ 20179/* 20180 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20181 * any interesting requests and then jump to the real instruction 20182 * handler. Note that the call to dvmCheckInst is done as a tail call. 20183 */ 20184 adrl lr, dvmAsmInstructionStart + (460 * 64) 20185 mov r0, rPC @ arg0 20186 mov r1, rSELF @ arg1 20187 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20188 20189/* ------------------------------ */ 20190 .balign 64 20191.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */ 20192/* File: armv5te/alt_stub.S */ 20193/* 20194 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20195 * any interesting requests and then jump to the real instruction 20196 * handler. Note that the call to dvmCheckInst is done as a tail call. 20197 */ 20198 adrl lr, dvmAsmInstructionStart + (461 * 64) 20199 mov r0, rPC @ arg0 20200 mov r1, rSELF @ arg1 20201 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20202 20203/* ------------------------------ */ 20204 .balign 64 20205.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */ 20206/* File: armv5te/alt_stub.S */ 20207/* 20208 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20209 * any interesting requests and then jump to the real instruction 20210 * handler. Note that the call to dvmCheckInst is done as a tail call. 20211 */ 20212 adrl lr, dvmAsmInstructionStart + (462 * 64) 20213 mov r0, rPC @ arg0 20214 mov r1, rSELF @ arg1 20215 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20216 20217/* ------------------------------ */ 20218 .balign 64 20219.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */ 20220/* File: armv5te/alt_stub.S */ 20221/* 20222 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20223 * any interesting requests and then jump to the real instruction 20224 * handler. Note that the call to dvmCheckInst is done as a tail call. 20225 */ 20226 adrl lr, dvmAsmInstructionStart + (463 * 64) 20227 mov r0, rPC @ arg0 20228 mov r1, rSELF @ arg1 20229 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20230 20231/* ------------------------------ */ 20232 .balign 64 20233.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */ 20234/* File: armv5te/alt_stub.S */ 20235/* 20236 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20237 * any interesting requests and then jump to the real instruction 20238 * handler. Note that the call to dvmCheckInst is done as a tail call. 20239 */ 20240 adrl lr, dvmAsmInstructionStart + (464 * 64) 20241 mov r0, rPC @ arg0 20242 mov r1, rSELF @ arg1 20243 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20244 20245/* ------------------------------ */ 20246 .balign 64 20247.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */ 20248/* File: armv5te/alt_stub.S */ 20249/* 20250 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20251 * any interesting requests and then jump to the real instruction 20252 * handler. Note that the call to dvmCheckInst is done as a tail call. 20253 */ 20254 adrl lr, dvmAsmInstructionStart + (465 * 64) 20255 mov r0, rPC @ arg0 20256 mov r1, rSELF @ arg1 20257 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20258 20259/* ------------------------------ */ 20260 .balign 64 20261.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */ 20262/* File: armv5te/alt_stub.S */ 20263/* 20264 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20265 * any interesting requests and then jump to the real instruction 20266 * handler. Note that the call to dvmCheckInst is done as a tail call. 20267 */ 20268 adrl lr, dvmAsmInstructionStart + (466 * 64) 20269 mov r0, rPC @ arg0 20270 mov r1, rSELF @ arg1 20271 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20272 20273/* ------------------------------ */ 20274 .balign 64 20275.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */ 20276/* File: armv5te/alt_stub.S */ 20277/* 20278 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20279 * any interesting requests and then jump to the real instruction 20280 * handler. Note that the call to dvmCheckInst is done as a tail call. 20281 */ 20282 adrl lr, dvmAsmInstructionStart + (467 * 64) 20283 mov r0, rPC @ arg0 20284 mov r1, rSELF @ arg1 20285 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20286 20287/* ------------------------------ */ 20288 .balign 64 20289.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */ 20290/* File: armv5te/alt_stub.S */ 20291/* 20292 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20293 * any interesting requests and then jump to the real instruction 20294 * handler. Note that the call to dvmCheckInst is done as a tail call. 20295 */ 20296 adrl lr, dvmAsmInstructionStart + (468 * 64) 20297 mov r0, rPC @ arg0 20298 mov r1, rSELF @ arg1 20299 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20300 20301/* ------------------------------ */ 20302 .balign 64 20303.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */ 20304/* File: armv5te/alt_stub.S */ 20305/* 20306 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20307 * any interesting requests and then jump to the real instruction 20308 * handler. Note that the call to dvmCheckInst is done as a tail call. 20309 */ 20310 adrl lr, dvmAsmInstructionStart + (469 * 64) 20311 mov r0, rPC @ arg0 20312 mov r1, rSELF @ arg1 20313 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20314 20315/* ------------------------------ */ 20316 .balign 64 20317.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */ 20318/* File: armv5te/alt_stub.S */ 20319/* 20320 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20321 * any interesting requests and then jump to the real instruction 20322 * handler. Note that the call to dvmCheckInst is done as a tail call. 20323 */ 20324 adrl lr, dvmAsmInstructionStart + (470 * 64) 20325 mov r0, rPC @ arg0 20326 mov r1, rSELF @ arg1 20327 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20328 20329/* ------------------------------ */ 20330 .balign 64 20331.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */ 20332/* File: armv5te/alt_stub.S */ 20333/* 20334 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20335 * any interesting requests and then jump to the real instruction 20336 * handler. Note that the call to dvmCheckInst is done as a tail call. 20337 */ 20338 adrl lr, dvmAsmInstructionStart + (471 * 64) 20339 mov r0, rPC @ arg0 20340 mov r1, rSELF @ arg1 20341 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20342 20343/* ------------------------------ */ 20344 .balign 64 20345.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */ 20346/* File: armv5te/alt_stub.S */ 20347/* 20348 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20349 * any interesting requests and then jump to the real instruction 20350 * handler. Note that the call to dvmCheckInst is done as a tail call. 20351 */ 20352 adrl lr, dvmAsmInstructionStart + (472 * 64) 20353 mov r0, rPC @ arg0 20354 mov r1, rSELF @ arg1 20355 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20356 20357/* ------------------------------ */ 20358 .balign 64 20359.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */ 20360/* File: armv5te/alt_stub.S */ 20361/* 20362 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20363 * any interesting requests and then jump to the real instruction 20364 * handler. Note that the call to dvmCheckInst is done as a tail call. 20365 */ 20366 adrl lr, dvmAsmInstructionStart + (473 * 64) 20367 mov r0, rPC @ arg0 20368 mov r1, rSELF @ arg1 20369 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20370 20371/* ------------------------------ */ 20372 .balign 64 20373.L_ALT_OP_UNUSED_DAFF: /* 0x1da */ 20374/* File: armv5te/alt_stub.S */ 20375/* 20376 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20377 * any interesting requests and then jump to the real instruction 20378 * handler. Note that the call to dvmCheckInst is done as a tail call. 20379 */ 20380 adrl lr, dvmAsmInstructionStart + (474 * 64) 20381 mov r0, rPC @ arg0 20382 mov r1, rSELF @ arg1 20383 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20384 20385/* ------------------------------ */ 20386 .balign 64 20387.L_ALT_OP_UNUSED_DBFF: /* 0x1db */ 20388/* File: armv5te/alt_stub.S */ 20389/* 20390 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20391 * any interesting requests and then jump to the real instruction 20392 * handler. Note that the call to dvmCheckInst is done as a tail call. 20393 */ 20394 adrl lr, dvmAsmInstructionStart + (475 * 64) 20395 mov r0, rPC @ arg0 20396 mov r1, rSELF @ arg1 20397 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20398 20399/* ------------------------------ */ 20400 .balign 64 20401.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */ 20402/* File: armv5te/alt_stub.S */ 20403/* 20404 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20405 * any interesting requests and then jump to the real instruction 20406 * handler. Note that the call to dvmCheckInst is done as a tail call. 20407 */ 20408 adrl lr, dvmAsmInstructionStart + (476 * 64) 20409 mov r0, rPC @ arg0 20410 mov r1, rSELF @ arg1 20411 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20412 20413/* ------------------------------ */ 20414 .balign 64 20415.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */ 20416/* File: armv5te/alt_stub.S */ 20417/* 20418 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20419 * any interesting requests and then jump to the real instruction 20420 * handler. Note that the call to dvmCheckInst is done as a tail call. 20421 */ 20422 adrl lr, dvmAsmInstructionStart + (477 * 64) 20423 mov r0, rPC @ arg0 20424 mov r1, rSELF @ arg1 20425 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20426 20427/* ------------------------------ */ 20428 .balign 64 20429.L_ALT_OP_UNUSED_DEFF: /* 0x1de */ 20430/* File: armv5te/alt_stub.S */ 20431/* 20432 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20433 * any interesting requests and then jump to the real instruction 20434 * handler. Note that the call to dvmCheckInst is done as a tail call. 20435 */ 20436 adrl lr, dvmAsmInstructionStart + (478 * 64) 20437 mov r0, rPC @ arg0 20438 mov r1, rSELF @ arg1 20439 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20440 20441/* ------------------------------ */ 20442 .balign 64 20443.L_ALT_OP_UNUSED_DFFF: /* 0x1df */ 20444/* File: armv5te/alt_stub.S */ 20445/* 20446 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20447 * any interesting requests and then jump to the real instruction 20448 * handler. Note that the call to dvmCheckInst is done as a tail call. 20449 */ 20450 adrl lr, dvmAsmInstructionStart + (479 * 64) 20451 mov r0, rPC @ arg0 20452 mov r1, rSELF @ arg1 20453 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20454 20455/* ------------------------------ */ 20456 .balign 64 20457.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */ 20458/* File: armv5te/alt_stub.S */ 20459/* 20460 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20461 * any interesting requests and then jump to the real instruction 20462 * handler. Note that the call to dvmCheckInst is done as a tail call. 20463 */ 20464 adrl lr, dvmAsmInstructionStart + (480 * 64) 20465 mov r0, rPC @ arg0 20466 mov r1, rSELF @ arg1 20467 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20468 20469/* ------------------------------ */ 20470 .balign 64 20471.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */ 20472/* File: armv5te/alt_stub.S */ 20473/* 20474 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20475 * any interesting requests and then jump to the real instruction 20476 * handler. Note that the call to dvmCheckInst is done as a tail call. 20477 */ 20478 adrl lr, dvmAsmInstructionStart + (481 * 64) 20479 mov r0, rPC @ arg0 20480 mov r1, rSELF @ arg1 20481 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20482 20483/* ------------------------------ */ 20484 .balign 64 20485.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */ 20486/* File: armv5te/alt_stub.S */ 20487/* 20488 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20489 * any interesting requests and then jump to the real instruction 20490 * handler. Note that the call to dvmCheckInst is done as a tail call. 20491 */ 20492 adrl lr, dvmAsmInstructionStart + (482 * 64) 20493 mov r0, rPC @ arg0 20494 mov r1, rSELF @ arg1 20495 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20496 20497/* ------------------------------ */ 20498 .balign 64 20499.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */ 20500/* File: armv5te/alt_stub.S */ 20501/* 20502 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20503 * any interesting requests and then jump to the real instruction 20504 * handler. Note that the call to dvmCheckInst is done as a tail call. 20505 */ 20506 adrl lr, dvmAsmInstructionStart + (483 * 64) 20507 mov r0, rPC @ arg0 20508 mov r1, rSELF @ arg1 20509 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20510 20511/* ------------------------------ */ 20512 .balign 64 20513.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */ 20514/* File: armv5te/alt_stub.S */ 20515/* 20516 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20517 * any interesting requests and then jump to the real instruction 20518 * handler. Note that the call to dvmCheckInst is done as a tail call. 20519 */ 20520 adrl lr, dvmAsmInstructionStart + (484 * 64) 20521 mov r0, rPC @ arg0 20522 mov r1, rSELF @ arg1 20523 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20524 20525/* ------------------------------ */ 20526 .balign 64 20527.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */ 20528/* File: armv5te/alt_stub.S */ 20529/* 20530 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20531 * any interesting requests and then jump to the real instruction 20532 * handler. Note that the call to dvmCheckInst is done as a tail call. 20533 */ 20534 adrl lr, dvmAsmInstructionStart + (485 * 64) 20535 mov r0, rPC @ arg0 20536 mov r1, rSELF @ arg1 20537 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20538 20539/* ------------------------------ */ 20540 .balign 64 20541.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */ 20542/* File: armv5te/alt_stub.S */ 20543/* 20544 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20545 * any interesting requests and then jump to the real instruction 20546 * handler. Note that the call to dvmCheckInst is done as a tail call. 20547 */ 20548 adrl lr, dvmAsmInstructionStart + (486 * 64) 20549 mov r0, rPC @ arg0 20550 mov r1, rSELF @ arg1 20551 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20552 20553/* ------------------------------ */ 20554 .balign 64 20555.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */ 20556/* File: armv5te/alt_stub.S */ 20557/* 20558 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20559 * any interesting requests and then jump to the real instruction 20560 * handler. Note that the call to dvmCheckInst is done as a tail call. 20561 */ 20562 adrl lr, dvmAsmInstructionStart + (487 * 64) 20563 mov r0, rPC @ arg0 20564 mov r1, rSELF @ arg1 20565 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20566 20567/* ------------------------------ */ 20568 .balign 64 20569.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */ 20570/* File: armv5te/alt_stub.S */ 20571/* 20572 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20573 * any interesting requests and then jump to the real instruction 20574 * handler. Note that the call to dvmCheckInst is done as a tail call. 20575 */ 20576 adrl lr, dvmAsmInstructionStart + (488 * 64) 20577 mov r0, rPC @ arg0 20578 mov r1, rSELF @ arg1 20579 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20580 20581/* ------------------------------ */ 20582 .balign 64 20583.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */ 20584/* File: armv5te/alt_stub.S */ 20585/* 20586 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20587 * any interesting requests and then jump to the real instruction 20588 * handler. Note that the call to dvmCheckInst is done as a tail call. 20589 */ 20590 adrl lr, dvmAsmInstructionStart + (489 * 64) 20591 mov r0, rPC @ arg0 20592 mov r1, rSELF @ arg1 20593 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20594 20595/* ------------------------------ */ 20596 .balign 64 20597.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */ 20598/* File: armv5te/alt_stub.S */ 20599/* 20600 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20601 * any interesting requests and then jump to the real instruction 20602 * handler. Note that the call to dvmCheckInst is done as a tail call. 20603 */ 20604 adrl lr, dvmAsmInstructionStart + (490 * 64) 20605 mov r0, rPC @ arg0 20606 mov r1, rSELF @ arg1 20607 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20608 20609/* ------------------------------ */ 20610 .balign 64 20611.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */ 20612/* File: armv5te/alt_stub.S */ 20613/* 20614 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20615 * any interesting requests and then jump to the real instruction 20616 * handler. Note that the call to dvmCheckInst is done as a tail call. 20617 */ 20618 adrl lr, dvmAsmInstructionStart + (491 * 64) 20619 mov r0, rPC @ arg0 20620 mov r1, rSELF @ arg1 20621 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20622 20623/* ------------------------------ */ 20624 .balign 64 20625.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */ 20626/* File: armv5te/alt_stub.S */ 20627/* 20628 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20629 * any interesting requests and then jump to the real instruction 20630 * handler. Note that the call to dvmCheckInst is done as a tail call. 20631 */ 20632 adrl lr, dvmAsmInstructionStart + (492 * 64) 20633 mov r0, rPC @ arg0 20634 mov r1, rSELF @ arg1 20635 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20636 20637/* ------------------------------ */ 20638 .balign 64 20639.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */ 20640/* File: armv5te/alt_stub.S */ 20641/* 20642 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20643 * any interesting requests and then jump to the real instruction 20644 * handler. Note that the call to dvmCheckInst is done as a tail call. 20645 */ 20646 adrl lr, dvmAsmInstructionStart + (493 * 64) 20647 mov r0, rPC @ arg0 20648 mov r1, rSELF @ arg1 20649 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20650 20651/* ------------------------------ */ 20652 .balign 64 20653.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */ 20654/* File: armv5te/alt_stub.S */ 20655/* 20656 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20657 * any interesting requests and then jump to the real instruction 20658 * handler. Note that the call to dvmCheckInst is done as a tail call. 20659 */ 20660 adrl lr, dvmAsmInstructionStart + (494 * 64) 20661 mov r0, rPC @ arg0 20662 mov r1, rSELF @ arg1 20663 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20664 20665/* ------------------------------ */ 20666 .balign 64 20667.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */ 20668/* File: armv5te/alt_stub.S */ 20669/* 20670 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20671 * any interesting requests and then jump to the real instruction 20672 * handler. Note that the call to dvmCheckInst is done as a tail call. 20673 */ 20674 adrl lr, dvmAsmInstructionStart + (495 * 64) 20675 mov r0, rPC @ arg0 20676 mov r1, rSELF @ arg1 20677 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20678 20679/* ------------------------------ */ 20680 .balign 64 20681.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */ 20682/* File: armv5te/alt_stub.S */ 20683/* 20684 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20685 * any interesting requests and then jump to the real instruction 20686 * handler. Note that the call to dvmCheckInst is done as a tail call. 20687 */ 20688 adrl lr, dvmAsmInstructionStart + (496 * 64) 20689 mov r0, rPC @ arg0 20690 mov r1, rSELF @ arg1 20691 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20692 20693/* ------------------------------ */ 20694 .balign 64 20695.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */ 20696/* File: armv5te/alt_stub.S */ 20697/* 20698 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20699 * any interesting requests and then jump to the real instruction 20700 * handler. Note that the call to dvmCheckInst is done as a tail call. 20701 */ 20702 adrl lr, dvmAsmInstructionStart + (497 * 64) 20703 mov r0, rPC @ arg0 20704 mov r1, rSELF @ arg1 20705 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20706 20707/* ------------------------------ */ 20708 .balign 64 20709.L_ALT_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */ 20710/* File: armv5te/alt_stub.S */ 20711/* 20712 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20713 * any interesting requests and then jump to the real instruction 20714 * handler. Note that the call to dvmCheckInst is done as a tail call. 20715 */ 20716 adrl lr, dvmAsmInstructionStart + (498 * 64) 20717 mov r0, rPC @ arg0 20718 mov r1, rSELF @ arg1 20719 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20720 20721/* ------------------------------ */ 20722 .balign 64 20723.L_ALT_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */ 20724/* File: armv5te/alt_stub.S */ 20725/* 20726 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20727 * any interesting requests and then jump to the real instruction 20728 * handler. Note that the call to dvmCheckInst is done as a tail call. 20729 */ 20730 adrl lr, dvmAsmInstructionStart + (499 * 64) 20731 mov r0, rPC @ arg0 20732 mov r1, rSELF @ arg1 20733 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20734 20735/* ------------------------------ */ 20736 .balign 64 20737.L_ALT_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */ 20738/* File: armv5te/alt_stub.S */ 20739/* 20740 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20741 * any interesting requests and then jump to the real instruction 20742 * handler. Note that the call to dvmCheckInst is done as a tail call. 20743 */ 20744 adrl lr, dvmAsmInstructionStart + (500 * 64) 20745 mov r0, rPC @ arg0 20746 mov r1, rSELF @ arg1 20747 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20748 20749/* ------------------------------ */ 20750 .balign 64 20751.L_ALT_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */ 20752/* File: armv5te/alt_stub.S */ 20753/* 20754 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20755 * any interesting requests and then jump to the real instruction 20756 * handler. Note that the call to dvmCheckInst is done as a tail call. 20757 */ 20758 adrl lr, dvmAsmInstructionStart + (501 * 64) 20759 mov r0, rPC @ arg0 20760 mov r1, rSELF @ arg1 20761 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20762 20763/* ------------------------------ */ 20764 .balign 64 20765.L_ALT_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */ 20766/* File: armv5te/alt_stub.S */ 20767/* 20768 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20769 * any interesting requests and then jump to the real instruction 20770 * handler. Note that the call to dvmCheckInst is done as a tail call. 20771 */ 20772 adrl lr, dvmAsmInstructionStart + (502 * 64) 20773 mov r0, rPC @ arg0 20774 mov r1, rSELF @ arg1 20775 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20776 20777/* ------------------------------ */ 20778 .balign 64 20779.L_ALT_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */ 20780/* File: armv5te/alt_stub.S */ 20781/* 20782 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20783 * any interesting requests and then jump to the real instruction 20784 * handler. Note that the call to dvmCheckInst is done as a tail call. 20785 */ 20786 adrl lr, dvmAsmInstructionStart + (503 * 64) 20787 mov r0, rPC @ arg0 20788 mov r1, rSELF @ arg1 20789 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20790 20791/* ------------------------------ */ 20792 .balign 64 20793.L_ALT_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */ 20794/* File: armv5te/alt_stub.S */ 20795/* 20796 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20797 * any interesting requests and then jump to the real instruction 20798 * handler. Note that the call to dvmCheckInst is done as a tail call. 20799 */ 20800 adrl lr, dvmAsmInstructionStart + (504 * 64) 20801 mov r0, rPC @ arg0 20802 mov r1, rSELF @ arg1 20803 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20804 20805/* ------------------------------ */ 20806 .balign 64 20807.L_ALT_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */ 20808/* File: armv5te/alt_stub.S */ 20809/* 20810 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20811 * any interesting requests and then jump to the real instruction 20812 * handler. Note that the call to dvmCheckInst is done as a tail call. 20813 */ 20814 adrl lr, dvmAsmInstructionStart + (505 * 64) 20815 mov r0, rPC @ arg0 20816 mov r1, rSELF @ arg1 20817 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20818 20819/* ------------------------------ */ 20820 .balign 64 20821.L_ALT_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */ 20822/* File: armv5te/alt_stub.S */ 20823/* 20824 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20825 * any interesting requests and then jump to the real instruction 20826 * handler. Note that the call to dvmCheckInst is done as a tail call. 20827 */ 20828 adrl lr, dvmAsmInstructionStart + (506 * 64) 20829 mov r0, rPC @ arg0 20830 mov r1, rSELF @ arg1 20831 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20832 20833/* ------------------------------ */ 20834 .balign 64 20835.L_ALT_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */ 20836/* File: armv5te/alt_stub.S */ 20837/* 20838 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20839 * any interesting requests and then jump to the real instruction 20840 * handler. Note that the call to dvmCheckInst is done as a tail call. 20841 */ 20842 adrl lr, dvmAsmInstructionStart + (507 * 64) 20843 mov r0, rPC @ arg0 20844 mov r1, rSELF @ arg1 20845 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20846 20847/* ------------------------------ */ 20848 .balign 64 20849.L_ALT_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */ 20850/* File: armv5te/alt_stub.S */ 20851/* 20852 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20853 * any interesting requests and then jump to the real instruction 20854 * handler. Note that the call to dvmCheckInst is done as a tail call. 20855 */ 20856 adrl lr, dvmAsmInstructionStart + (508 * 64) 20857 mov r0, rPC @ arg0 20858 mov r1, rSELF @ arg1 20859 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20860 20861/* ------------------------------ */ 20862 .balign 64 20863.L_ALT_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */ 20864/* File: armv5te/alt_stub.S */ 20865/* 20866 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20867 * any interesting requests and then jump to the real instruction 20868 * handler. Note that the call to dvmCheckInst is done as a tail call. 20869 */ 20870 adrl lr, dvmAsmInstructionStart + (509 * 64) 20871 mov r0, rPC @ arg0 20872 mov r1, rSELF @ arg1 20873 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20874 20875/* ------------------------------ */ 20876 .balign 64 20877.L_ALT_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */ 20878/* File: armv5te/alt_stub.S */ 20879/* 20880 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20881 * any interesting requests and then jump to the real instruction 20882 * handler. Note that the call to dvmCheckInst is done as a tail call. 20883 */ 20884 adrl lr, dvmAsmInstructionStart + (510 * 64) 20885 mov r0, rPC @ arg0 20886 mov r1, rSELF @ arg1 20887 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20888 20889/* ------------------------------ */ 20890 .balign 64 20891.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 20892/* File: armv5te/alt_stub.S */ 20893/* 20894 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20895 * any interesting requests and then jump to the real instruction 20896 * handler. Note that the call to dvmCheckInst is done as a tail call. 20897 */ 20898 adrl lr, dvmAsmInstructionStart + (511 * 64) 20899 mov r0, rPC @ arg0 20900 mov r1, rSELF @ arg1 20901 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20902 20903 .balign 64 20904 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart 20905 .global dvmAsmAltInstructionEnd 20906dvmAsmAltInstructionEnd: 20907/* File: armv5te/footer.S */ 20908 20909/* 20910 * =========================================================================== 20911 * Common subroutines and data 20912 * =========================================================================== 20913 */ 20914 20915 20916 20917 .text 20918 .align 2 20919 20920#if defined(WITH_JIT) 20921#if defined(WITH_SELF_VERIFICATION) 20922 .global dvmJitToInterpPunt 20923dvmJitToInterpPunt: 20924 mov r2,#kSVSPunt @ r2<- interpreter entry point 20925 mov r3, #0 20926 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20927 b jitSVShadowRunEnd @ doesn't return 20928 20929 .global dvmJitToInterpSingleStep 20930dvmJitToInterpSingleStep: 20931 str lr,[rSELF,#offThread_jitResumeNPC] 20932 str r1,[rSELF,#offThread_jitResumeDPC] 20933 mov r2,#kSVSSingleStep @ r2<- interpreter entry point 20934 b jitSVShadowRunEnd @ doesn't return 20935 20936 .global dvmJitToInterpNoChainNoProfile 20937dvmJitToInterpNoChainNoProfile: 20938 mov r0,rPC @ pass our target PC 20939 mov r2,#kSVSNoProfile @ r2<- interpreter entry point 20940 mov r3, #0 @ 0 means !inJitCodeCache 20941 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 20942 b jitSVShadowRunEnd @ doesn't return 20943 20944 .global dvmJitToInterpTraceSelectNoChain 20945dvmJitToInterpTraceSelectNoChain: 20946 mov r0,rPC @ pass our target PC 20947 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20948 mov r3, #0 @ 0 means !inJitCodeCache 20949 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20950 b jitSVShadowRunEnd @ doesn't return 20951 20952 .global dvmJitToInterpTraceSelect 20953dvmJitToInterpTraceSelect: 20954 ldr r0,[lr, #-1] @ pass our target PC 20955 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20956 mov r3, #0 @ 0 means !inJitCodeCache 20957 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20958 b jitSVShadowRunEnd @ doesn't return 20959 20960 .global dvmJitToInterpBackwardBranch 20961dvmJitToInterpBackwardBranch: 20962 ldr r0,[lr, #-1] @ pass our target PC 20963 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 20964 mov r3, #0 @ 0 means !inJitCodeCache 20965 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20966 b jitSVShadowRunEnd @ doesn't return 20967 20968 .global dvmJitToInterpNormal 20969dvmJitToInterpNormal: 20970 ldr r0,[lr, #-1] @ pass our target PC 20971 mov r2,#kSVSNormal @ r2<- interpreter entry point 20972 mov r3, #0 @ 0 means !inJitCodeCache 20973 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20974 b jitSVShadowRunEnd @ doesn't return 20975 20976 .global dvmJitToInterpNoChain 20977dvmJitToInterpNoChain: 20978 mov r0,rPC @ pass our target PC 20979 mov r2,#kSVSNoChain @ r2<- interpreter entry point 20980 mov r3, #0 @ 0 means !inJitCodeCache 20981 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20982 b jitSVShadowRunEnd @ doesn't return 20983#else 20984/* 20985 * Return from the translation cache to the interpreter when the compiler is 20986 * having issues translating/executing a Dalvik instruction. We have to skip 20987 * the code cache lookup otherwise it is possible to indefinitely bouce 20988 * between the interpreter and the code cache if the instruction that fails 20989 * to be compiled happens to be at a trace start. 20990 */ 20991 .global dvmJitToInterpPunt 20992dvmJitToInterpPunt: 20993 mov rPC, r0 20994#if defined(WITH_JIT_TUNING) 20995 mov r0,lr 20996 bl dvmBumpPunt; 20997#endif 20998 EXPORT_PC() 20999 mov r0, #0 21000 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 21001 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21002 FETCH_INST() 21003 GET_INST_OPCODE(ip) 21004 GOTO_OPCODE(ip) 21005 21006/* 21007 * Return to the interpreter to handle a single instruction. 21008 * On entry: 21009 * r0 <= PC 21010 * r1 <= PC of resume instruction 21011 * lr <= resume point in translation 21012 */ 21013 .global dvmJitToInterpSingleStep 21014dvmJitToInterpSingleStep: 21015 str lr,[rSELF,#offThread_jitResumeNPC] 21016 str r1,[rSELF,#offThread_jitResumeDPC] 21017 mov r1,#kInterpEntryInstr 21018 @ enum is 4 byte in aapcs-EABI 21019 str r1, [rSELF, #offThread_entryPoint] 21020 mov rPC,r0 21021 EXPORT_PC() 21022 21023 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21024 mov r2,#kJitSingleStep @ Ask for single step and then revert 21025 str r2,[rSELF,#offThread_jitState] 21026 mov r1,#1 @ set changeInterp to bail to debug interp 21027 b common_gotoBail 21028 21029/* 21030 * Return from the translation cache and immediately request 21031 * a translation for the exit target. Commonly used for callees. 21032 */ 21033 .global dvmJitToInterpTraceSelectNoChain 21034dvmJitToInterpTraceSelectNoChain: 21035#if defined(WITH_JIT_TUNING) 21036 bl dvmBumpNoChain 21037#endif 21038 mov r0,rPC 21039 bl dvmJitGetTraceAddr @ Is there a translation? 21040 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21041 mov r1, rPC @ arg1 of translation may need this 21042 mov lr, #0 @ in case target is HANDLER_INTERPRET 21043 cmp r0,#0 @ !0 means translation exists 21044 bxne r0 @ continue native execution if so 21045 b 2f @ branch over to use the interpreter 21046 21047/* 21048 * Return from the translation cache and immediately request 21049 * a translation for the exit target. Commonly used following 21050 * invokes. 21051 */ 21052 .global dvmJitToInterpTraceSelect 21053dvmJitToInterpTraceSelect: 21054 ldr rPC,[lr, #-1] @ get our target PC 21055 add rINST,lr,#-5 @ save start of chain branch 21056 add rINST, #-4 @ .. which is 9 bytes back 21057 mov r0,rPC 21058 bl dvmJitGetTraceAddr @ Is there a translation? 21059 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21060 cmp r0,#0 21061 beq 2f 21062 mov r1,rINST 21063 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 21064 mov r1, rPC @ arg1 of translation may need this 21065 mov lr, #0 @ in case target is HANDLER_INTERPRET 21066 cmp r0,#0 @ successful chain? 21067 bxne r0 @ continue native execution 21068 b toInterpreter @ didn't chain - resume with interpreter 21069 21070/* No translation, so request one if profiling isn't disabled*/ 210712: 21072 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21073 GET_JIT_PROF_TABLE(r0) 21074 FETCH_INST() 21075 cmp r0, #0 21076 movne r2,#kJitTSelectRequestHot @ ask for trace selection 21077 bne common_selectTrace 21078 GET_INST_OPCODE(ip) 21079 GOTO_OPCODE(ip) 21080 21081/* 21082 * Return from the translation cache to the interpreter. 21083 * The return was done with a BLX from thumb mode, and 21084 * the following 32-bit word contains the target rPC value. 21085 * Note that lr (r14) will have its low-order bit set to denote 21086 * its thumb-mode origin. 21087 * 21088 * We'll need to stash our lr origin away, recover the new 21089 * target and then check to see if there is a translation available 21090 * for our new target. If so, we do a translation chain and 21091 * go back to native execution. Otherwise, it's back to the 21092 * interpreter (after treating this entry as a potential 21093 * trace start). 21094 */ 21095 .global dvmJitToInterpNormal 21096dvmJitToInterpNormal: 21097 ldr rPC,[lr, #-1] @ get our target PC 21098 add rINST,lr,#-5 @ save start of chain branch 21099 add rINST,#-4 @ .. which is 9 bytes back 21100#if defined(WITH_JIT_TUNING) 21101 bl dvmBumpNormal 21102#endif 21103 mov r0,rPC 21104 bl dvmJitGetTraceAddr @ Is there a translation? 21105 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21106 cmp r0,#0 21107 beq toInterpreter @ go if not, otherwise do chain 21108 mov r1,rINST 21109 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 21110 mov r1, rPC @ arg1 of translation may need this 21111 mov lr, #0 @ in case target is HANDLER_INTERPRET 21112 cmp r0,#0 @ successful chain? 21113 bxne r0 @ continue native execution 21114 b toInterpreter @ didn't chain - resume with interpreter 21115 21116/* 21117 * Return from the translation cache to the interpreter to do method invocation. 21118 * Check if translation exists for the callee, but don't chain to it. 21119 */ 21120 .global dvmJitToInterpNoChainNoProfile 21121dvmJitToInterpNoChainNoProfile: 21122#if defined(WITH_JIT_TUNING) 21123 bl dvmBumpNoChain 21124#endif 21125 mov r0,rPC 21126 bl dvmJitGetTraceAddr @ Is there a translation? 21127 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21128 mov r1, rPC @ arg1 of translation may need this 21129 mov lr, #0 @ in case target is HANDLER_INTERPRET 21130 cmp r0,#0 21131 bxne r0 @ continue native execution if so 21132 EXPORT_PC() 21133 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21134 FETCH_INST() 21135 GET_INST_OPCODE(ip) @ extract opcode from rINST 21136 GOTO_OPCODE(ip) @ jump to next instruction 21137 21138/* 21139 * Return from the translation cache to the interpreter to do method invocation. 21140 * Check if translation exists for the callee, but don't chain to it. 21141 */ 21142 .global dvmJitToInterpNoChain 21143dvmJitToInterpNoChain: 21144#if defined(WITH_JIT_TUNING) 21145 bl dvmBumpNoChain 21146#endif 21147 mov r0,rPC 21148 bl dvmJitGetTraceAddr @ Is there a translation? 21149 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21150 mov r1, rPC @ arg1 of translation may need this 21151 mov lr, #0 @ in case target is HANDLER_INTERPRET 21152 cmp r0,#0 21153 bxne r0 @ continue native execution if so 21154#endif 21155 21156/* 21157 * No translation, restore interpreter regs and start interpreting. 21158 * rSELF & rFP were preserved in the translated code, and rPC has 21159 * already been restored by the time we get here. We'll need to set 21160 * up rIBASE & rINST, and load the address of the JitTable into r0. 21161 */ 21162toInterpreter: 21163 EXPORT_PC() 21164 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21165 FETCH_INST() 21166 GET_JIT_PROF_TABLE(r0) 21167 @ NOTE: intended fallthrough 21168 21169/* 21170 * Common code to update potential trace start counter, and initiate 21171 * a trace-build if appropriate. On entry, rPC should point to the 21172 * next instruction to execute, and rINST should be already loaded with 21173 * the next opcode word, and r0 holds a pointer to the jit profile 21174 * table (pJitProfTable). 21175 */ 21176common_testUpdateProfile: 21177 cmp r0,#0 21178 GET_INST_OPCODE(ip) 21179 GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 21180 21181common_updateProfile: 21182 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 21183 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 21184 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 21185 GET_INST_OPCODE(ip) 21186 subs r1,r1,#1 @ decrement counter 21187 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 21188 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 21189 21190/* 21191 * Here, we switch to the debug interpreter to request 21192 * trace selection. First, though, check to see if there 21193 * is already a native translation in place (and, if so, 21194 * jump to it now). 21195 */ 21196 21197 GET_JIT_THRESHOLD(r1) 21198 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 21199 EXPORT_PC() 21200 mov r0,rPC 21201 bl dvmJitGetTraceAddr @ r0<- dvmJitGetTraceAddr(rPC) 21202 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21203 mov r1, rPC @ arg1 of translation may need this 21204 mov lr, #0 @ in case target is HANDLER_INTERPRET 21205 cmp r0,#0 21206#if !defined(WITH_SELF_VERIFICATION) 21207 bxne r0 @ jump to the translation 21208 mov r2,#kJitTSelectRequest @ ask for trace selection 21209 @ fall-through to common_selectTrace 21210#else 21211 moveq r2,#kJitTSelectRequest @ ask for trace selection 21212 beq common_selectTrace 21213 /* 21214 * At this point, we have a target translation. However, if 21215 * that translation is actually the interpret-only pseudo-translation 21216 * we want to treat it the same as no translation. 21217 */ 21218 mov r10, r0 @ save target 21219 bl dvmCompilerGetInterpretTemplate 21220 cmp r0, r10 @ special case? 21221 bne jitSVShadowRunStart @ set up self verification shadow space 21222 @ Need to clear the inJitCodeCache flag 21223 mov r3, #0 @ 0 means not in the JIT code cache 21224 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 21225 GET_INST_OPCODE(ip) 21226 GOTO_OPCODE(ip) 21227 /* no return */ 21228#endif 21229 21230/* 21231 * On entry: 21232 * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 21233 */ 21234common_selectTrace: 21235 21236 str r2,[rSELF,#offThread_jitState] 21237 mov r2,#kInterpEntryInstr @ normal entry reason 21238 str r2,[rSELF,#offThread_entryPoint] 21239 mov r1,#1 @ set changeInterp 21240 b common_gotoBail 21241 21242#if defined(WITH_SELF_VERIFICATION) 21243/* 21244 * Save PC and registers to shadow memory for self verification mode 21245 * before jumping to native translation. 21246 * On entry: 21247 * rPC, rFP, rSELF: the values that they should contain 21248 * r10: the address of the target translation. 21249 */ 21250jitSVShadowRunStart: 21251 mov r0,rPC @ r0<- program counter 21252 mov r1,rFP @ r1<- frame pointer 21253 mov r2,rSELF @ r2<- self (Thread) pointer 21254 mov r3,r10 @ r3<- target translation 21255 bl dvmSelfVerificationSaveState @ save registers to shadow space 21256 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 21257 bx r10 @ jump to the translation 21258 21259/* 21260 * Restore PC, registers, and interpreter state to original values 21261 * before jumping back to the interpreter. 21262 */ 21263jitSVShadowRunEnd: 21264 mov r1,rFP @ pass ending fp 21265 mov r3,rSELF @ pass self ptr for convenience 21266 bl dvmSelfVerificationRestoreState @ restore pc and fp values 21267 ldr rPC,[rSELF,#offThread_pc] @ restore PC 21268 ldr rFP,[rSELF,#offThread_fp] @ restore FP 21269 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 21270 cmp r1,#0 @ check for punt condition 21271 beq 1f 21272 mov r2,#kJitSelfVerification @ ask for self verification 21273 str r2,[rSELF,#offThread_jitState] 21274 mov r2,#kInterpEntryInstr @ normal entry reason 21275 str r2,[rSELF,#offThread_entryPoint] 21276 mov r1,#1 @ set changeInterp 21277 b common_gotoBail 21278 212791: @ exit to interpreter without check 21280 EXPORT_PC() 21281 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21282 FETCH_INST() 21283 GET_INST_OPCODE(ip) 21284 GOTO_OPCODE(ip) 21285#endif 21286 21287#endif 21288 21289/* 21290 * Common code when a backward branch is taken. 21291 * 21292 * TODO: we could avoid a branch by just setting r0 and falling through 21293 * into the common_periodicChecks code, and having a test on r0 at the 21294 * end determine if we should return to the caller or update & branch to 21295 * the next instr. 21296 * 21297 * On entry: 21298 * r9 is PC adjustment *in bytes* 21299 */ 21300common_backwardBranch: 21301 mov r0, #kInterpEntryInstr 21302 bl common_periodicChecks 21303#if defined(WITH_JIT) 21304 GET_JIT_PROF_TABLE(r0) 21305 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 21306 cmp r0,#0 21307 bne common_updateProfile 21308 GET_INST_OPCODE(ip) 21309 GOTO_OPCODE(ip) 21310#else 21311 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 21312 GET_INST_OPCODE(ip) @ extract opcode from rINST 21313 GOTO_OPCODE(ip) @ jump to next instruction 21314#endif 21315 21316 21317/* 21318 * Need to see if the thread needs to be suspended or debugger/profiler 21319 * activity has begun. If so, we suspend the thread or side-exit to 21320 * the debug interpreter as appropriate. 21321 * 21322 * The common case is no activity on any of these, so we want to figure 21323 * that out quickly. If something is up, we can then sort out what. 21324 * 21325 * We want to be fast if the VM was built without debugger or profiler 21326 * support, but we also need to recognize that the system is usually 21327 * shipped with both of these enabled. 21328 * 21329 * TODO: reduce this so we're just checking a single location. 21330 * 21331 * On entry: 21332 * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling) 21333 * r9 is trampoline PC adjustment *in bytes* 21334 */ 21335common_periodicChecks: 21336/* TUNING - make this a direct load when interpBreak moved to Thread */ 21337 ldr r1, [rSELF, #offThread_pInterpBreak] @ r3<- &interpBreak 21338 /* speculatively thread-specific suspend count */ 21339 ldr ip, [rSELF, #offThread_suspendCount] 21340 ldr r1, [r1] @ r1<- interpBreak 21341 cmp r1, #0 @ anything unusual? 21342 bxeq lr @ return if not 21343 /* 21344 * One or more interesting events have happened. Figure out what. 21345 * 21346 * r0 still holds the reentry type. 21347 */ 21348 cmp ip, #0 @ want suspend? 21349 beq 3f @ no, must be something else 21350 21351 stmfd sp!, {r0, lr} @ preserve r0 and lr 21352#if defined(WITH_JIT) 21353 /* 21354 * Refresh the Jit's cached copy of profile table pointer. This pointer 21355 * doubles as the Jit's on/off switch. 21356 */ 21357 ldr r3, [rSELF, #offThread_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 21358 mov r0, rSELF @ r0<- self 21359 ldr r3, [r3] @ r3 <- pJitProfTable 21360 EXPORT_PC() @ need for precise GC 21361 str r3, [rSELF, #offThread_pJitProfTable] @ refresh Jit's on/off switch 21362#else 21363 mov r0, rSELF @ r0<- self 21364 EXPORT_PC() @ need for precise GC 21365#endif 21366 bl dvmCheckSuspendPending @ do full check, suspend if necessary 21367 ldmfd sp!, {r0, lr} @ restore r0 and lr 21368 21369 /* 21370 * Reload the interpBreak flags - they may have changed while we 21371 * were suspended. 21372 */ 21373/* TUNING - direct load when InterpBreak moved to Thread */ 21374 ldr r1, [rSELF, #offThread_pInterpBreak] @ r1<- &interpBreak 21375 ldr r1, [r1] @ r1<- interpBreak 213763: 21377 /* 21378 * TODO: this code is too fragile. Need a general mechanism 21379 * to identify what actions to take by submode. Some profiling modes 21380 * (instruction count) need to single-step, while method tracing 21381 * may not. Debugging with breakpoints can run unfettered, but 21382 * source-level single-stepping requires Dalvik singlestepping. 21383 * GC may require a one-shot action and then full-speed resumption. 21384 */ 21385 ands r1, #(kSubModeDebuggerActive | kSubModeEmulatorTrace | kSubModeInstCounting) 21386 bxeq lr @ nothing to do, return 21387 21388 @ debugger/profiler enabled, bail out; self->entryPoint was set above 21389 str r0, [rSELF, #offThread_entryPoint] @ store r0, need for debug/prof 21390 add rPC, rPC, r9 @ update rPC 21391 mov r1, #1 @ "want switch" = true 21392 b common_gotoBail @ side exit 21393 21394 21395/* 21396 * The equivalent of "goto bail", this calls through the "bail handler". 21397 * 21398 * State registers will be saved to the "thread" area before bailing. 21399 * 21400 * On entry: 21401 * r1 is "bool changeInterp", indicating if we want to switch to the 21402 * other interpreter or just bail all the way out 21403 */ 21404common_gotoBail: 21405 SAVE_PC_FP_TO_SELF() @ export state to "thread" 21406 mov r0, rSELF @ r0<- self ptr 21407 b dvmMterpStdBail @ call(self, changeInterp) 21408 21409 @add r1, r1, #1 @ using (boolean+1) 21410 @add r0, rSELF, #offThread_jmpBuf @ r0<- &self->jmpBuf 21411 @bl _longjmp @ does not return 21412 @bl common_abort 21413 21414 21415/* 21416 * Common code for jumbo method invocation. 21417 * NOTE: this adjusts rPC to account for the difference in instruction width. 21418 * As a result, the savedPc in the stack frame will not be wholly accurate. So 21419 * long as that is only used for source file line number calculations, we're 21420 * okay. 21421 * 21422 * On entry: 21423 * r0 is "Method* methodToCall", the method we're trying to call 21424 */ 21425common_invokeMethodJumbo: 21426.LinvokeNewJumbo: 21427 @ prepare to copy args to "outs" area of current frame 21428 add rPC, rPC, #4 @ adjust pc to make return consistent 21429 FETCH(r2, 1) @ r2<- BBBB (arg count) 21430 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 21431 cmp r2, #0 @ no args? 21432 beq .LinvokeArgsDone @ if no args, skip the rest 21433 FETCH(r1, 2) @ r1<- CCCC 21434 b .LinvokeRangeArgs @ handle args like invoke range 21435 21436/* 21437 * Common code for method invocation with range. 21438 * 21439 * On entry: 21440 * r0 is "Method* methodToCall", the method we're trying to call 21441 */ 21442common_invokeMethodRange: 21443.LinvokeNewRange: 21444 @ prepare to copy args to "outs" area of current frame 21445 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 21446 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 21447 beq .LinvokeArgsDone @ if no args, skip the rest 21448 FETCH(r1, 2) @ r1<- CCCC 21449 21450.LinvokeRangeArgs: 21451 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 21452 @ (very few methods have > 10 args; could unroll for common cases) 21453 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 21454 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 214551: ldr r1, [r3], #4 @ val = *fp++ 21456 subs r2, r2, #1 @ count-- 21457 str r1, [r10], #4 @ *outs++ = val 21458 bne 1b @ ...while count != 0 21459 b .LinvokeArgsDone 21460 21461/* 21462 * Common code for method invocation without range. 21463 * 21464 * On entry: 21465 * r0 is "Method* methodToCall", the method we're trying to call 21466 */ 21467common_invokeMethodNoRange: 21468.LinvokeNewNoRange: 21469 @ prepare to copy args to "outs" area of current frame 21470 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 21471 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 21472 FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 21473 beq .LinvokeArgsDone 21474 21475 @ r0=methodToCall, r1=GFED, r2=count, r10=outs 21476.LinvokeNonRange: 21477 rsb r2, r2, #5 @ r2<- 5-r2 21478 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 21479 bl common_abort @ (skipped due to ARM prefetch) 214805: and ip, rINST, #0x0f00 @ isolate A 21481 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 21482 mov r0, r0 @ nop 21483 str r2, [r10, #-4]! @ *--outs = vA 214844: and ip, r1, #0xf000 @ isolate G 21485 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 21486 mov r0, r0 @ nop 21487 str r2, [r10, #-4]! @ *--outs = vG 214883: and ip, r1, #0x0f00 @ isolate F 21489 ldr r2, [rFP, ip, lsr #6] @ r2<- vF 21490 mov r0, r0 @ nop 21491 str r2, [r10, #-4]! @ *--outs = vF 214922: and ip, r1, #0x00f0 @ isolate E 21493 ldr r2, [rFP, ip, lsr #2] @ r2<- vE 21494 mov r0, r0 @ nop 21495 str r2, [r10, #-4]! @ *--outs = vE 214961: and ip, r1, #0x000f @ isolate D 21497 ldr r2, [rFP, ip, lsl #2] @ r2<- vD 21498 mov r0, r0 @ nop 21499 str r2, [r10, #-4]! @ *--outs = vD 215000: @ fall through to .LinvokeArgsDone 21501 21502.LinvokeArgsDone: @ r0=methodToCall 21503 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 21504 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 21505 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 21506 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 21507 @ find space for the new stack frame, check for overflow 21508 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 21509 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 21510 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 21511@ bl common_dumpRegs 21512 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd 21513 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 21514 cmp r3, r9 @ bottom < interpStackEnd? 21515 ldr lr, [rSELF, #offThread_pInterpBreak] 21516 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 21517 blo .LstackOverflow @ yes, this frame will overflow stack 21518 21519 @ set up newSaveArea 21520 ldr lr, [lr] @ lr<- active submodes 21521#ifdef EASY_GDB 21522 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 21523 str ip, [r10, #offStackSaveArea_prevSave] 21524#endif 21525 str rFP, [r10, #offStackSaveArea_prevFrame] 21526 str rPC, [r10, #offStackSaveArea_savedPc] 21527#if defined(WITH_JIT) 21528 mov r9, #0 21529 str r9, [r10, #offStackSaveArea_returnAddr] 21530#endif 21531 ands lr, #kSubModeMethodTrace @ method tracing? 21532 beq 1f @ skip if not 21533 stmfd sp!, {r0-r3} @ preserve r0-r3 21534 mov r1, rSELF 21535 @ r0=methodToCall, r1=rSELF 21536 bl dvmFastMethodTraceEnter 21537 ldmfd sp!, {r0-r3} @ restore r0-r3 215381: 21539 str r0, [r10, #offStackSaveArea_method] 21540 tst r3, #ACC_NATIVE 21541 bne .LinvokeNative 21542 21543 /* 21544 stmfd sp!, {r0-r3} 21545 bl common_printNewline 21546 mov r0, rFP 21547 mov r1, #0 21548 bl dvmDumpFp 21549 ldmfd sp!, {r0-r3} 21550 stmfd sp!, {r0-r3} 21551 mov r0, r1 21552 mov r1, r10 21553 bl dvmDumpFp 21554 bl common_printNewline 21555 ldmfd sp!, {r0-r3} 21556 */ 21557 21558 ldrh r9, [r2] @ r9 <- load INST from new PC 21559 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 21560 mov rPC, r2 @ publish new rPC 21561 21562 @ Update state values for the new method 21563 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST 21564 str r0, [rSELF, #offThread_method] @ self->method = methodToCall 21565 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ... 21566#if defined(WITH_JIT) 21567 GET_JIT_PROF_TABLE(r0) 21568 mov rFP, r1 @ fp = newFp 21569 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 21570 mov rINST, r9 @ publish new rINST 21571 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21572 cmp r0,#0 21573 bne common_updateProfile 21574 GOTO_OPCODE(ip) @ jump to next instruction 21575#else 21576 mov rFP, r1 @ fp = newFp 21577 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 21578 mov rINST, r9 @ publish new rINST 21579 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21580 GOTO_OPCODE(ip) @ jump to next instruction 21581#endif 21582 21583.LinvokeNative: 21584 @ Prep for the native call 21585 @ r0=methodToCall, r1=newFp, r10=newSaveArea 21586 ldr lr, [rSELF, #offThread_pInterpBreak] 21587 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->... 21588 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21589 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 21590 ldr lr, [lr] @ lr<- active submodes 21591 21592 mov r2, r0 @ r2<- methodToCall 21593 mov r0, r1 @ r0<- newFp (points to args) 21594 add r1, rSELF, #offThread_retval @ r1<- &retval 21595 mov r3, rSELF @ arg3<- self 21596 21597#ifdef ASSIST_DEBUGGER 21598 /* insert fake function header to help gdb find the stack frame */ 21599 b .Lskip 21600 .type dalvik_mterp, %function 21601dalvik_mterp: 21602 .fnstart 21603 MTERP_ENTRY1 21604 MTERP_ENTRY2 21605.Lskip: 21606#endif 21607 21608 ands lr, #kSubModeMethodTrace @ method tracing? 21609 bne 330f @ hop if so 21610 mov lr, pc @ set return addr 21611 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 21612220: 21613#if defined(WITH_JIT) 21614 ldr r3, [rSELF, #offThread_ppJitProfTable] @ Refresh Jit's on/off status 21615#endif 21616 21617 @ native return; r10=newSaveArea 21618 @ equivalent to dvmPopJniLocals 21619 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 21620 ldr r1, [rSELF, #offThread_exception] @ check for exception 21621#if defined(WITH_JIT) 21622 ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 21623#endif 21624 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21625 cmp r1, #0 @ null? 21626 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top 21627#if defined(WITH_JIT) 21628 str r3, [rSELF, #offThread_pJitProfTable] @ refresh cached on/off switch 21629#endif 21630 bne common_exceptionThrown @ no, handle exception 21631 21632 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 21633 GET_INST_OPCODE(ip) @ extract opcode from rINST 21634 GOTO_OPCODE(ip) @ jump to next instruction 21635 21636330: 21637 @ r2=JNIMethod, r6=rSELF 21638 stmfd sp!, {r2,r6} 21639 21640 mov lr, pc @ set return addr 21641 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 21642 21643 @ r0=JNIMethod, r1=rSELF 21644 ldmfd sp!, {r0-r1} 21645 bl dvmFastNativeMethodTraceExit 21646 b 220b 21647 21648.LstackOverflow: @ r0=methodToCall 21649 mov r1, r0 @ r1<- methodToCall 21650 mov r0, rSELF @ r0<- self 21651 bl dvmHandleStackOverflow 21652 b common_exceptionThrown 21653#ifdef ASSIST_DEBUGGER 21654 .fnend 21655 .size dalvik_mterp, .-dalvik_mterp 21656#endif 21657 21658 21659 /* 21660 * Common code for method invocation, calling through "glue code". 21661 * 21662 * TODO: now that we have range and non-range invoke handlers, this 21663 * needs to be split into two. Maybe just create entry points 21664 * that set r9 and jump here? 21665 * 21666 * On entry: 21667 * r0 is "Method* methodToCall", the method we're trying to call 21668 * r9 is "bool methodCallRange", indicating if this is a /range variant 21669 */ 21670 .if 0 21671.LinvokeOld: 21672 sub sp, sp, #8 @ space for args + pad 21673 FETCH(ip, 2) @ ip<- FEDC or CCCC 21674 mov r2, r0 @ A2<- methodToCall 21675 mov r0, rSELF @ A0<- self 21676 SAVE_PC_FP_TO_SELF() @ export state to "self" 21677 mov r1, r9 @ A1<- methodCallRange 21678 mov r3, rINST, lsr #8 @ A3<- AA 21679 str ip, [sp, #0] @ A4<- ip 21680 bl dvmMterp_invokeMethod @ call the C invokeMethod 21681 add sp, sp, #8 @ remove arg area 21682 b common_resumeAfterGlueCall @ continue to next instruction 21683 .endif 21684 21685 21686 21687/* 21688 * Common code for handling a return instruction. 21689 * 21690 * This does not return. 21691 */ 21692common_returnFromMethod: 21693.LreturnNew: 21694 mov r0, #kInterpEntryReturn 21695 mov r9, #0 21696 bl common_periodicChecks 21697 21698 ldr lr, [rSELF, #offThread_pInterpBreak] 21699 SAVEAREA_FROM_FP(r0, rFP) 21700 ldr lr, [lr] @ lr<- active submodes 21701 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 21702 ands lr, #kSubModeMethodTrace @ method tracing? 21703 beq 333f 21704 stmfd sp!, {r0-r3} @ preserve r0-r3 21705 mov r0, rSELF 21706 @ r0=rSELF 21707 bl dvmFastJavaMethodTraceExit 21708 ldmfd sp!, {r0-r3} @ restore r0-r3 21709333: 21710 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 21711 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 21712 @ r2<- method we're returning to 21713 cmp r2, #0 @ is this a break frame? 21714#if defined(WORKAROUND_CORTEX_A9_745320) 21715 /* Don't use conditional loads if the HW defect exists */ 21716 beq 101f 21717 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21718101: 21719#else 21720 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21721#endif 21722 mov r1, #0 @ "want switch" = false 21723 beq common_gotoBail @ break frame, bail out completely 21724 21725 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 21726 str r2, [rSELF, #offThread_method]@ self->method = newSave->method 21727 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 21728 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21729#if defined(WITH_JIT) 21730 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 21731 mov rPC, r9 @ publish new rPC 21732 str r1, [rSELF, #offThread_methodClassDex] 21733 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land 21734 cmp r10, #0 @ caller is compiled code 21735 blxne r10 21736 GET_INST_OPCODE(ip) @ extract opcode from rINST 21737 GOTO_OPCODE(ip) @ jump to next instruction 21738#else 21739 GET_INST_OPCODE(ip) @ extract opcode from rINST 21740 mov rPC, r9 @ publish new rPC 21741 str r1, [rSELF, #offThread_methodClassDex] 21742 GOTO_OPCODE(ip) @ jump to next instruction 21743#endif 21744 21745 /* 21746 * Return handling, calls through "glue code". 21747 */ 21748 .if 0 21749.LreturnOld: 21750 SAVE_PC_FP_TO_SELF() @ export state 21751 mov r0, rSELF @ arg to function 21752 bl dvmMterp_returnFromMethod 21753 b common_resumeAfterGlueCall 21754 .endif 21755 21756 21757/* 21758 * Somebody has thrown an exception. Handle it. 21759 * 21760 * If the exception processing code returns to us (instead of falling 21761 * out of the interpreter), continue with whatever the next instruction 21762 * now happens to be. 21763 * 21764 * This does not return. 21765 */ 21766 .global dvmMterpCommonExceptionThrown 21767dvmMterpCommonExceptionThrown: 21768common_exceptionThrown: 21769.LexceptionNew: 21770 mov r0, #kInterpEntryThrow 21771 mov r9, #0 21772 bl common_periodicChecks 21773 21774 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception 21775 mov r1, rSELF @ r1<- self 21776 mov r0, r9 @ r0<- exception 21777 bl dvmAddTrackedAlloc @ don't let the exception be GCed 21778 mov r3, #0 @ r3<- NULL 21779 str r3, [rSELF, #offThread_exception] @ self->exception = NULL 21780 21781 /* set up args and a local for "&fp" */ 21782 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 21783 str rFP, [sp, #-4]! @ *--sp = fp 21784 mov ip, sp @ ip<- &fp 21785 mov r3, #0 @ r3<- false 21786 str ip, [sp, #-4]! @ *--sp = &fp 21787 ldr r1, [rSELF, #offThread_method] @ r1<- self->method 21788 mov r0, rSELF @ r0<- self 21789 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 21790 mov r2, r9 @ r2<- exception 21791 sub r1, rPC, r1 @ r1<- pc - method->insns 21792 mov r1, r1, asr #1 @ r1<- offset in code units 21793 21794 /* call, r0 gets catchRelPc (a code-unit offset) */ 21795 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 21796 21797 /* fix earlier stack overflow if necessary; may trash rFP */ 21798 ldrb r1, [rSELF, #offThread_stackOverflowed] 21799 cmp r1, #0 @ did we overflow earlier? 21800 beq 1f @ no, skip ahead 21801 mov rFP, r0 @ save relPc result in rFP 21802 mov r0, rSELF @ r0<- self 21803 mov r1, r9 @ r1<- exception 21804 bl dvmCleanupStackOverflow @ call(self) 21805 mov r0, rFP @ restore result 218061: 21807 21808 /* update frame pointer and check result from dvmFindCatchBlock */ 21809 ldr rFP, [sp, #4] @ retrieve the updated rFP 21810 cmp r0, #0 @ is catchRelPc < 0? 21811 add sp, sp, #8 @ restore stack 21812 bmi .LnotCaughtLocally 21813 21814 /* adjust locals to match self->curFrame and updated PC */ 21815 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 21816 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 21817 str r1, [rSELF, #offThread_method] @ self->method = new method 21818 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 21819 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 21820 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 21821 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 21822 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth... 21823 21824 /* release the tracked alloc on the exception */ 21825 mov r0, r9 @ r0<- exception 21826 mov r1, rSELF @ r1<- self 21827 bl dvmReleaseTrackedAlloc @ release the exception 21828 21829 /* restore the exception if the handler wants it */ 21830 FETCH_INST() @ load rINST from rPC 21831 GET_INST_OPCODE(ip) @ extract opcode from rINST 21832 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 21833 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception 21834 GOTO_OPCODE(ip) @ jump to next instruction 21835 21836.LnotCaughtLocally: @ r9=exception 21837 /* fix stack overflow if necessary */ 21838 ldrb r1, [rSELF, #offThread_stackOverflowed] 21839 cmp r1, #0 @ did we overflow earlier? 21840 movne r0, rSELF @ if yes: r0<- self 21841 movne r1, r9 @ if yes: r1<- exception 21842 blne dvmCleanupStackOverflow @ if yes: call(self) 21843 21844 @ may want to show "not caught locally" debug messages here 21845#if DVM_SHOW_EXCEPTION >= 2 21846 /* call __android_log_print(prio, tag, format, ...) */ 21847 /* "Exception %s from %s:%d not caught locally" */ 21848 @ dvmLineNumFromPC(method, pc - method->insns) 21849 ldr r0, [rSELF, #offThread_method] 21850 ldr r1, [r0, #offMethod_insns] 21851 sub r1, rPC, r1 21852 asr r1, r1, #1 21853 bl dvmLineNumFromPC 21854 str r0, [sp, #-4]! 21855 @ dvmGetMethodSourceFile(method) 21856 ldr r0, [rSELF, #offThread_method] 21857 bl dvmGetMethodSourceFile 21858 str r0, [sp, #-4]! 21859 @ exception->clazz->descriptor 21860 ldr r3, [r9, #offObject_clazz] 21861 ldr r3, [r3, #offClassObject_descriptor] 21862 @ 21863 ldr r2, strExceptionNotCaughtLocally 21864 ldr r1, strLogTag 21865 mov r0, #3 @ LOG_DEBUG 21866 bl __android_log_print 21867#endif 21868 str r9, [rSELF, #offThread_exception] @ restore exception 21869 mov r0, r9 @ r0<- exception 21870 mov r1, rSELF @ r1<- self 21871 bl dvmReleaseTrackedAlloc @ release the exception 21872 mov r1, #0 @ "want switch" = false 21873 b common_gotoBail @ bail out 21874 21875 21876 /* 21877 * Exception handling, calls through "glue code". 21878 */ 21879 .if 0 21880.LexceptionOld: 21881 SAVE_PC_FP_TO_SELF() @ export state 21882 mov r0, rSELF @ arg to function 21883 bl dvmMterp_exceptionThrown 21884 b common_resumeAfterGlueCall 21885 .endif 21886 21887 21888/* 21889 * After returning from a "glued" function, pull out the updated 21890 * values and start executing at the next instruction. 21891 */ 21892common_resumeAfterGlueCall: 21893 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread 21894 FETCH_INST() @ load rINST from rPC 21895 GET_INST_OPCODE(ip) @ extract opcode from rINST 21896 GOTO_OPCODE(ip) @ jump to next instruction 21897 21898/* 21899 * Invalid array index. Note that our calling convention is strange; we use r1 21900 * and r3 because those just happen to be the registers all our callers are 21901 * using. We move r3 before calling the C function, but r1 happens to match. 21902 * r1: index 21903 * r3: size 21904 */ 21905common_errArrayIndex: 21906 EXPORT_PC() 21907 mov r0, r3 21908 bl dvmThrowArrayIndexOutOfBoundsException 21909 b common_exceptionThrown 21910 21911/* 21912 * Integer divide or mod by zero. 21913 */ 21914common_errDivideByZero: 21915 EXPORT_PC() 21916 ldr r0, strDivideByZero 21917 bl dvmThrowArithmeticException 21918 b common_exceptionThrown 21919 21920/* 21921 * Attempt to allocate an array with a negative size. 21922 * On entry: length in r1 21923 */ 21924common_errNegativeArraySize: 21925 EXPORT_PC() 21926 mov r0, r1 @ arg0 <- len 21927 bl dvmThrowNegativeArraySizeException @ (len) 21928 b common_exceptionThrown 21929 21930/* 21931 * Invocation of a non-existent method. 21932 * On entry: method name in r1 21933 */ 21934common_errNoSuchMethod: 21935 EXPORT_PC() 21936 mov r0, r1 21937 bl dvmThrowNoSuchMethodError 21938 b common_exceptionThrown 21939 21940/* 21941 * We encountered a null object when we weren't expecting one. We 21942 * export the PC, throw a NullPointerException, and goto the exception 21943 * processing code. 21944 */ 21945common_errNullObject: 21946 EXPORT_PC() 21947 mov r0, #0 21948 bl dvmThrowNullPointerException 21949 b common_exceptionThrown 21950 21951/* 21952 * For debugging, cause an immediate fault. The source address will 21953 * be in lr (use a bl instruction to jump here). 21954 */ 21955common_abort: 21956 ldr pc, .LdeadFood 21957.LdeadFood: 21958 .word 0xdeadf00d 21959 21960/* 21961 * Spit out a "we were here", preserving all registers. (The attempt 21962 * to save ip won't work, but we need to save an even number of 21963 * registers for EABI 64-bit stack alignment.) 21964 */ 21965 .macro SQUEAK num 21966common_squeak\num: 21967 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21968 ldr r0, strSqueak 21969 mov r1, #\num 21970 bl printf 21971 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21972 bx lr 21973 .endm 21974 21975 SQUEAK 0 21976 SQUEAK 1 21977 SQUEAK 2 21978 SQUEAK 3 21979 SQUEAK 4 21980 SQUEAK 5 21981 21982/* 21983 * Spit out the number in r0, preserving registers. 21984 */ 21985common_printNum: 21986 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21987 mov r1, r0 21988 ldr r0, strSqueak 21989 bl printf 21990 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21991 bx lr 21992 21993/* 21994 * Print a newline, preserving registers. 21995 */ 21996common_printNewline: 21997 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21998 ldr r0, strNewline 21999 bl printf 22000 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 22001 bx lr 22002 22003 /* 22004 * Print the 32-bit quantity in r0 as a hex value, preserving registers. 22005 */ 22006common_printHex: 22007 stmfd sp!, {r0, r1, r2, r3, ip, lr} 22008 mov r1, r0 22009 ldr r0, strPrintHex 22010 bl printf 22011 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 22012 bx lr 22013 22014/* 22015 * Print the 64-bit quantity in r0-r1, preserving registers. 22016 */ 22017common_printLong: 22018 stmfd sp!, {r0, r1, r2, r3, ip, lr} 22019 mov r3, r1 22020 mov r2, r0 22021 ldr r0, strPrintLong 22022 bl printf 22023 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 22024 bx lr 22025 22026/* 22027 * Print full method info. Pass the Method* in r0. Preserves regs. 22028 */ 22029common_printMethod: 22030 stmfd sp!, {r0, r1, r2, r3, ip, lr} 22031 bl dvmMterpPrintMethod 22032 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 22033 bx lr 22034 22035/* 22036 * Call a C helper function that dumps regs and possibly some 22037 * additional info. Requires the C function to be compiled in. 22038 */ 22039 .if 0 22040common_dumpRegs: 22041 stmfd sp!, {r0, r1, r2, r3, ip, lr} 22042 bl dvmMterpDumpArmRegs 22043 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 22044 bx lr 22045 .endif 22046 22047#if 0 22048/* 22049 * Experiment on VFP mode. 22050 * 22051 * uint32_t setFPSCR(uint32_t val, uint32_t mask) 22052 * 22053 * Updates the bits specified by "mask", setting them to the values in "val". 22054 */ 22055setFPSCR: 22056 and r0, r0, r1 @ make sure no stray bits are set 22057 fmrx r2, fpscr @ get VFP reg 22058 mvn r1, r1 @ bit-invert mask 22059 and r2, r2, r1 @ clear masked bits 22060 orr r2, r2, r0 @ set specified bits 22061 fmxr fpscr, r2 @ set VFP reg 22062 mov r0, r2 @ return new value 22063 bx lr 22064 22065 .align 2 22066 .global dvmConfigureFP 22067 .type dvmConfigureFP, %function 22068dvmConfigureFP: 22069 stmfd sp!, {ip, lr} 22070 /* 0x03000000 sets DN/FZ */ 22071 /* 0x00009f00 clears the six exception enable flags */ 22072 bl common_squeak0 22073 mov r0, #0x03000000 @ r0<- 0x03000000 22074 add r1, r0, #0x9f00 @ r1<- 0x03009f00 22075 bl setFPSCR 22076 ldmfd sp!, {ip, pc} 22077#endif 22078 22079 22080/* 22081 * String references, must be close to the code that uses them. 22082 */ 22083 .align 2 22084strDivideByZero: 22085 .word .LstrDivideByZero 22086strLogTag: 22087 .word .LstrLogTag 22088strExceptionNotCaughtLocally: 22089 .word .LstrExceptionNotCaughtLocally 22090 22091strNewline: 22092 .word .LstrNewline 22093strSqueak: 22094 .word .LstrSqueak 22095strPrintHex: 22096 .word .LstrPrintHex 22097strPrintLong: 22098 .word .LstrPrintLong 22099 22100/* 22101 * Zero-terminated ASCII string data. 22102 * 22103 * On ARM we have two choices: do like gcc does, and LDR from a .word 22104 * with the address, or use an ADR pseudo-op to get the address 22105 * directly. ADR saves 4 bytes and an indirection, but it's using a 22106 * PC-relative addressing mode and hence has a limited range, which 22107 * makes it not work well with mergeable string sections. 22108 */ 22109 .section .rodata.str1.4,"aMS",%progbits,1 22110 22111.LstrBadEntryPoint: 22112 .asciz "Bad entry point %d\n" 22113.LstrFilledNewArrayNotImpl: 22114 .asciz "filled-new-array only implemented for objects and 'int'" 22115.LstrDivideByZero: 22116 .asciz "divide by zero" 22117.LstrLogTag: 22118 .asciz "mterp" 22119.LstrExceptionNotCaughtLocally: 22120 .asciz "Exception %s from %s:%d not caught locally\n" 22121 22122.LstrNewline: 22123 .asciz "\n" 22124.LstrSqueak: 22125 .asciz "<%d>" 22126.LstrPrintHex: 22127 .asciz "<0x%x>" 22128.LstrPrintLong: 22129 .asciz "<%lld>" 22130 22131