InterpAsm-armv5te-vfp.S revision 98f3eb12bf2a33c49712e093d5cc2aa713a93aa5
1/* 2 * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: armv5te/header.S */ 8/* 9 * Copyright (C) 2008 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 * ARMv5 definitions and declarations. 26 */ 27 28/* 29ARM EABI general notes: 30 31r0-r3 hold first 4 args to a method; they are not preserved across method calls 32r4-r8 are available for general use 33r9 is given special treatment in some situations, but not for us 34r10 (sl) seems to be generally available 35r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36r12 (ip) is scratch -- not preserved across method calls 37r13 (sp) should be managed carefully in case a signal arrives 38r14 (lr) must be preserved 39r15 (pc) can be tinkered with directly 40 41r0 holds returns of <= 4 bytes 42r0-r1 hold returns of 8 bytes, low word in r0 43 44Callee must save/restore r4+ (except r12) if it modifies them. If VFP 45is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46s0-s15 (d0-d7, q0-a3) do not need to be. 47 48Stack is "full descending". Only the arguments that don't fit in the first 4 49registers are placed on the stack. "sp" points at the first stacked argument 50(i.e. the 5th arg). 51 52VFP: single-precision results in s0, double-precision results in d0. 53 54In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 5564-bit quantities (long long, double) must be 64-bit aligned. 56*/ 57 58/* 59Mterp and ARM notes: 60 61The following registers have fixed assignments: 62 63 reg nick purpose 64 r4 rPC interpreted program counter, used for fetching instructions 65 r5 rFP interpreted frame pointer, used for accessing locals and args 66 r6 rSELF self (Thread) pointer 67 r7 rINST first 16-bit code unit of current instruction 68 r8 rIBASE interpreted instruction base pointer, used for computed goto 69 70Macros are provided for common operations. Each macro MUST emit only 71one instruction to make instruction-counting easier. They MUST NOT alter 72unspecified registers or condition codes. 73*/ 74 75/* single-purpose registers, given names for clarity */ 76#define rPC r4 77#define rFP r5 78#define rSELF r6 79#define rINST r7 80#define rIBASE r8 81 82/* save/restore the PC and/or FP from the thread struct */ 83#define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc] 84#define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc] 85#define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_fp] 86#define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_fp] 87#define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP} 88#define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP} 89 90/* 91 * "export" the PC to the stack frame, f/b/o future exception objects. Must 92 * be done *before* something throws. 93 * 94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96 * 97 * It's okay to do this more than once. 98 */ 99#define EXPORT_PC() \ 100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101 102/* 103 * Given a frame pointer, find the stack save area. 104 * 105 * In C this is "((StackSaveArea*)(_fp) -1)". 106 */ 107#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108 sub _reg, _fpreg, #sizeofStackSaveArea 109 110/* 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112 */ 113#define FETCH_INST() ldrh rINST, [rPC] 114 115/* 116 * Fetch the next instruction from the specified offset. Advances rPC 117 * to point to the next instruction. "_count" is in 16-bit code units. 118 * 119 * Because of the limited size of immediate constants on ARM, this is only 120 * suitable for small forward movements (i.e. don't try to implement "goto" 121 * with this). 122 * 123 * This must come AFTER anything that can throw an exception, or the 124 * exception catch may miss. (This also implies that it must come after 125 * EXPORT_PC().) 126 */ 127#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 128 129/* 130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132 */ 133#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134 ldrh _dreg, [_sreg, #(_count*2)]! 135 136/* 137 * Fetch the next instruction from an offset specified by _reg. Updates 138 * rPC to point to the next instruction. "_reg" must specify the distance 139 * in bytes, *not* 16-bit code units, and may be a signed value. 140 * 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 142 * bits that hold the shift distance are used for the half/byte/sign flags. 143 * In some cases we can pre-double _reg for free, so we require a byte offset 144 * here. 145 */ 146#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147 148/* 149 * Fetch a half-word code unit from an offset past the current PC. The 150 * "_count" value is in 16-bit code units. Does not advance rPC. 151 * 152 * The "_S" variant works the same but treats the value as signed. 153 */ 154#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 155#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 156 157/* 158 * Fetch one byte from an offset past the current PC. Pass in the same 159 * "_count" as you would for FETCH, and an additional 0/1 indicating which 160 * byte of the halfword you want (lo/hi). 161 */ 162#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 163 164/* 165 * Put the instruction's opcode field into the specified register. 166 */ 167#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168 169/* 170 * Put the prefetched instruction's opcode field into the specified register. 171 */ 172#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173 174/* 175 * Begin executing the opcode in _reg. Because this only jumps within the 176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177 */ 178#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 180#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 181 182/* 183 * Get/set the 32-bit value from a Dalvik register. 184 */ 185#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 186#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 187 188#if defined(WITH_JIT) 189#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rSELF,#offThread_pJitProfTable] 190#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rSELF,#offThread_jitThreshold] 191#endif 192 193/* 194 * Convert a virtual register index into an address. 195 */ 196#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 197 add _reg, rFP, _vreg, lsl #2 198 199/* 200 * This is a #include, not a %include, because we want the C pre-processor 201 * to expand the macros into assembler assignment statements. 202 */ 203#include "../common/asm-constants.h" 204 205#if defined(WITH_JIT) 206#include "../common/jit-config.h" 207#endif 208 209/* File: armv5te/platform.S */ 210/* 211 * =========================================================================== 212 * CPU-version-specific defines 213 * =========================================================================== 214 */ 215 216/* 217 * Macro for data memory barrier; not meaningful pre-ARMv6K. 218 */ 219.macro SMP_DMB 220.endm 221 222/* 223 * Macro for data memory barrier; not meaningful pre-ARMv6K. 224 */ 225.macro SMP_DMB_ST 226.endm 227 228/* File: armv5te/entry.S */ 229/* 230 * Copyright (C) 2008 The Android Open Source Project 231 * 232 * Licensed under the Apache License, Version 2.0 (the "License"); 233 * you may not use this file except in compliance with the License. 234 * You may obtain a copy of the License at 235 * 236 * http://www.apache.org/licenses/LICENSE-2.0 237 * 238 * Unless required by applicable law or agreed to in writing, software 239 * distributed under the License is distributed on an "AS IS" BASIS, 240 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 241 * See the License for the specific language governing permissions and 242 * limitations under the License. 243 */ 244/* 245 * Interpreter entry point. 246 */ 247 248/* 249 * We don't have formal stack frames, so gdb scans upward in the code 250 * to find the start of the function (a label with the %function type), 251 * and then looks at the next few instructions to figure out what 252 * got pushed onto the stack. From this it figures out how to restore 253 * the registers, including PC, for the previous stack frame. If gdb 254 * sees a non-function label, it stops scanning, so either we need to 255 * have nothing but assembler-local labels between the entry point and 256 * the break, or we need to fake it out. 257 * 258 * When this is defined, we add some stuff to make gdb less confused. 259 */ 260#define ASSIST_DEBUGGER 1 261 262 .text 263 .align 2 264 .global dvmMterpStdRun 265 .type dvmMterpStdRun, %function 266 267/* 268 * On entry: 269 * r0 Thread* self 270 * 271 * This function returns a boolean "changeInterp" value. The return comes 272 * via a call to dvmMterpStdBail(). 273 */ 274dvmMterpStdRun: 275#define MTERP_ENTRY1 \ 276 .save {r4-r10,fp,lr}; \ 277 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 278#define MTERP_ENTRY2 \ 279 .pad #4; \ 280 sub sp, sp, #4 @ align 64 281 282 .fnstart 283 MTERP_ENTRY1 284 MTERP_ENTRY2 285 286 /* save stack pointer, add magic word for debuggerd */ 287 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return 288 289 /* set up "named" registers, figure out entry point */ 290 mov rSELF, r0 @ set rSELF 291 ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI 292 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread" 293 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE 294 cmp r1, #kInterpEntryInstr @ usual case? 295 bne .Lnot_instr @ no, handle it 296 297#if defined(WITH_JIT) 298.LentryInstr: 299 /* Entry is always a possible trace start */ 300 GET_JIT_PROF_TABLE(r0) 301 FETCH_INST() 302 mov r1, #0 @ prepare the value for the new state 303 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 304 cmp r0,#0 @ is profiling disabled? 305#if !defined(WITH_SELF_VERIFICATION) 306 bne common_updateProfile @ profiling is enabled 307#else 308 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state 309 beq 1f @ profiling is disabled 310 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 311 cmp r3, #kSVSTraceSelect @ hot trace following? 312 moveq r2,#kJitTSelectRequestHot @ ask for trace selection 313 beq common_selectTrace @ go build the trace 314 cmp r3, #kSVSNoProfile @ don't profile the next instruction? 315 beq 1f @ intrepret the next instruction 316 b common_updateProfile @ collect profiles 317#endif 3181: 319 GET_INST_OPCODE(ip) 320 GOTO_OPCODE(ip) 321#else 322 /* start executing the instruction at rPC */ 323 FETCH_INST() @ load rINST from rPC 324 GET_INST_OPCODE(ip) @ extract opcode from rINST 325 GOTO_OPCODE(ip) @ jump to next instruction 326#endif 327 328.Lnot_instr: 329 cmp r1, #kInterpEntryReturn @ were we returning from a method? 330 beq common_returnFromMethod 331 332.Lnot_return: 333 cmp r1, #kInterpEntryThrow @ were we throwing an exception? 334 beq common_exceptionThrown 335 336#if defined(WITH_JIT) 337.Lnot_throw: 338 ldr r10,[rSELF, #offThread_jitResumeNPC] 339 ldr r2,[rSELF, #offThread_jitResumeDPC] 340 cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 341 bne .Lbad_arg 342 cmp rPC,r2 343 bne .LentryInstr @ must have branched, don't resume 344#if defined(WITH_SELF_VERIFICATION) 345 @ self->entryPoint will be set in dvmSelfVerificationSaveState 346 b jitSVShadowRunStart @ re-enter the translation after the 347 @ single-stepped instruction 348 @noreturn 349#endif 350 mov r1, #kInterpEntryInstr 351 str r1, [rSELF, #offThread_entryPoint] 352 bx r10 @ re-enter the translation 353#endif 354 355.Lbad_arg: 356 ldr r0, strBadEntryPoint 357 @ r1 holds value of entryPoint 358 bl printf 359 bl dvmAbort 360 .fnend 361 .size dvmMterpStdRun, .-dvmMterpStdRun 362 363 364 .global dvmMterpStdBail 365 .type dvmMterpStdBail, %function 366 367/* 368 * Restore the stack pointer and PC from the save point established on entry. 369 * This is essentially the same as a longjmp, but should be cheaper. The 370 * last instruction causes us to return to whoever called dvmMterpStdRun. 371 * 372 * We pushed some registers on the stack in dvmMterpStdRun, then saved 373 * SP and LR. Here we restore SP, restore the registers, and then restore 374 * LR to PC. 375 * 376 * On entry: 377 * r0 Thread* self 378 * r1 bool changeInterp 379 */ 380dvmMterpStdBail: 381 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP 382 mov r0, r1 @ return the changeInterp value 383 add sp, sp, #4 @ un-align 64 384 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return 385 386 387/* 388 * String references. 389 */ 390strBadEntryPoint: 391 .word .LstrBadEntryPoint 392 393 394 .global dvmAsmInstructionStart 395 .type dvmAsmInstructionStart, %function 396dvmAsmInstructionStart = .L_OP_NOP 397 .text 398 399/* ------------------------------ */ 400 .balign 64 401.L_OP_NOP: /* 0x00 */ 402/* File: armv5te/OP_NOP.S */ 403 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 404 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 405 GOTO_OPCODE(ip) @ execute it 406 407#ifdef ASSIST_DEBUGGER 408 /* insert fake function header to help gdb find the stack frame */ 409 .type dalvik_inst, %function 410dalvik_inst: 411 .fnstart 412 MTERP_ENTRY1 413 MTERP_ENTRY2 414 .fnend 415#endif 416 417/* ------------------------------ */ 418 .balign 64 419.L_OP_MOVE: /* 0x01 */ 420/* File: armv5te/OP_MOVE.S */ 421 /* for move, move-object, long-to-int */ 422 /* op vA, vB */ 423 mov r1, rINST, lsr #12 @ r1<- B from 15:12 424 mov r0, rINST, lsr #8 @ r0<- A from 11:8 425 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 426 GET_VREG(r2, r1) @ r2<- fp[B] 427 and r0, r0, #15 428 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 429 SET_VREG(r2, r0) @ fp[A]<- r2 430 GOTO_OPCODE(ip) @ execute next instruction 431 432/* ------------------------------ */ 433 .balign 64 434.L_OP_MOVE_FROM16: /* 0x02 */ 435/* File: armv5te/OP_MOVE_FROM16.S */ 436 /* for: move/from16, move-object/from16 */ 437 /* op vAA, vBBBB */ 438 FETCH(r1, 1) @ r1<- BBBB 439 mov r0, rINST, lsr #8 @ r0<- AA 440 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 441 GET_VREG(r2, r1) @ r2<- fp[BBBB] 442 GET_INST_OPCODE(ip) @ extract opcode from rINST 443 SET_VREG(r2, r0) @ fp[AA]<- r2 444 GOTO_OPCODE(ip) @ jump to next instruction 445 446/* ------------------------------ */ 447 .balign 64 448.L_OP_MOVE_16: /* 0x03 */ 449/* File: armv5te/OP_MOVE_16.S */ 450 /* for: move/16, move-object/16 */ 451 /* op vAAAA, vBBBB */ 452 FETCH(r1, 2) @ r1<- BBBB 453 FETCH(r0, 1) @ r0<- AAAA 454 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 455 GET_VREG(r2, r1) @ r2<- fp[BBBB] 456 GET_INST_OPCODE(ip) @ extract opcode from rINST 457 SET_VREG(r2, r0) @ fp[AAAA]<- r2 458 GOTO_OPCODE(ip) @ jump to next instruction 459 460/* ------------------------------ */ 461 .balign 64 462.L_OP_MOVE_WIDE: /* 0x04 */ 463/* File: armv5te/OP_MOVE_WIDE.S */ 464 /* move-wide vA, vB */ 465 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 466 mov r2, rINST, lsr #8 @ r2<- A(+) 467 mov r3, rINST, lsr #12 @ r3<- B 468 and r2, r2, #15 469 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 470 add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 471 ldmia r3, {r0-r1} @ r0/r1<- fp[B] 472 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 473 GET_INST_OPCODE(ip) @ extract opcode from rINST 474 stmia r2, {r0-r1} @ fp[A]<- r0/r1 475 GOTO_OPCODE(ip) @ jump to next instruction 476 477/* ------------------------------ */ 478 .balign 64 479.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 480/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 481 /* move-wide/from16 vAA, vBBBB */ 482 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 483 FETCH(r3, 1) @ r3<- BBBB 484 mov r2, rINST, lsr #8 @ r2<- AA 485 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 486 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 487 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 488 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 489 GET_INST_OPCODE(ip) @ extract opcode from rINST 490 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 491 GOTO_OPCODE(ip) @ jump to next instruction 492 493/* ------------------------------ */ 494 .balign 64 495.L_OP_MOVE_WIDE_16: /* 0x06 */ 496/* File: armv5te/OP_MOVE_WIDE_16.S */ 497 /* move-wide/16 vAAAA, vBBBB */ 498 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 499 FETCH(r3, 2) @ r3<- BBBB 500 FETCH(r2, 1) @ r2<- AAAA 501 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 502 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 503 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 504 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 505 GET_INST_OPCODE(ip) @ extract opcode from rINST 506 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 507 GOTO_OPCODE(ip) @ jump to next instruction 508 509/* ------------------------------ */ 510 .balign 64 511.L_OP_MOVE_OBJECT: /* 0x07 */ 512/* File: armv5te/OP_MOVE_OBJECT.S */ 513/* File: armv5te/OP_MOVE.S */ 514 /* for move, move-object, long-to-int */ 515 /* op vA, vB */ 516 mov r1, rINST, lsr #12 @ r1<- B from 15:12 517 mov r0, rINST, lsr #8 @ r0<- A from 11:8 518 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 519 GET_VREG(r2, r1) @ r2<- fp[B] 520 and r0, r0, #15 521 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 522 SET_VREG(r2, r0) @ fp[A]<- r2 523 GOTO_OPCODE(ip) @ execute next instruction 524 525 526/* ------------------------------ */ 527 .balign 64 528.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 529/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 530/* File: armv5te/OP_MOVE_FROM16.S */ 531 /* for: move/from16, move-object/from16 */ 532 /* op vAA, vBBBB */ 533 FETCH(r1, 1) @ r1<- BBBB 534 mov r0, rINST, lsr #8 @ r0<- AA 535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 536 GET_VREG(r2, r1) @ r2<- fp[BBBB] 537 GET_INST_OPCODE(ip) @ extract opcode from rINST 538 SET_VREG(r2, r0) @ fp[AA]<- r2 539 GOTO_OPCODE(ip) @ jump to next instruction 540 541 542/* ------------------------------ */ 543 .balign 64 544.L_OP_MOVE_OBJECT_16: /* 0x09 */ 545/* File: armv5te/OP_MOVE_OBJECT_16.S */ 546/* File: armv5te/OP_MOVE_16.S */ 547 /* for: move/16, move-object/16 */ 548 /* op vAAAA, vBBBB */ 549 FETCH(r1, 2) @ r1<- BBBB 550 FETCH(r0, 1) @ r0<- AAAA 551 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 552 GET_VREG(r2, r1) @ r2<- fp[BBBB] 553 GET_INST_OPCODE(ip) @ extract opcode from rINST 554 SET_VREG(r2, r0) @ fp[AAAA]<- r2 555 GOTO_OPCODE(ip) @ jump to next instruction 556 557 558/* ------------------------------ */ 559 .balign 64 560.L_OP_MOVE_RESULT: /* 0x0a */ 561/* File: armv5te/OP_MOVE_RESULT.S */ 562 /* for: move-result, move-result-object */ 563 /* op vAA */ 564 mov r2, rINST, lsr #8 @ r2<- AA 565 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 566 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 567 GET_INST_OPCODE(ip) @ extract opcode from rINST 568 SET_VREG(r0, r2) @ fp[AA]<- r0 569 GOTO_OPCODE(ip) @ jump to next instruction 570 571/* ------------------------------ */ 572 .balign 64 573.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 574/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 575 /* move-result-wide vAA */ 576 mov r2, rINST, lsr #8 @ r2<- AA 577 add r3, rSELF, #offThread_retval @ r3<- &self->retval 578 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 579 ldmia r3, {r0-r1} @ r0/r1<- retval.j 580 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 581 GET_INST_OPCODE(ip) @ extract opcode from rINST 582 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 583 GOTO_OPCODE(ip) @ jump to next instruction 584 585/* ------------------------------ */ 586 .balign 64 587.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 588/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 589/* File: armv5te/OP_MOVE_RESULT.S */ 590 /* for: move-result, move-result-object */ 591 /* op vAA */ 592 mov r2, rINST, lsr #8 @ r2<- AA 593 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 594 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 595 GET_INST_OPCODE(ip) @ extract opcode from rINST 596 SET_VREG(r0, r2) @ fp[AA]<- r0 597 GOTO_OPCODE(ip) @ jump to next instruction 598 599 600/* ------------------------------ */ 601 .balign 64 602.L_OP_MOVE_EXCEPTION: /* 0x0d */ 603/* File: armv5te/OP_MOVE_EXCEPTION.S */ 604 /* move-exception vAA */ 605 mov r2, rINST, lsr #8 @ r2<- AA 606 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass 607 mov r1, #0 @ r1<- 0 608 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 609 SET_VREG(r3, r2) @ fp[AA]<- exception obj 610 GET_INST_OPCODE(ip) @ extract opcode from rINST 611 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass 612 GOTO_OPCODE(ip) @ jump to next instruction 613 614/* ------------------------------ */ 615 .balign 64 616.L_OP_RETURN_VOID: /* 0x0e */ 617/* File: armv5te/OP_RETURN_VOID.S */ 618 b common_returnFromMethod 619 620/* ------------------------------ */ 621 .balign 64 622.L_OP_RETURN: /* 0x0f */ 623/* File: armv5te/OP_RETURN.S */ 624 /* 625 * Return a 32-bit value. Copies the return value into the "thread" 626 * structure, then jumps to the return handler. 627 * 628 * for: return, return-object 629 */ 630 /* op vAA */ 631 mov r2, rINST, lsr #8 @ r2<- AA 632 GET_VREG(r0, r2) @ r0<- vAA 633 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 634 b common_returnFromMethod 635 636/* ------------------------------ */ 637 .balign 64 638.L_OP_RETURN_WIDE: /* 0x10 */ 639/* File: armv5te/OP_RETURN_WIDE.S */ 640 /* 641 * Return a 64-bit value. Copies the return value into the "thread" 642 * structure, then jumps to the return handler. 643 */ 644 /* return-wide vAA */ 645 mov r2, rINST, lsr #8 @ r2<- AA 646 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 647 add r3, rSELF, #offThread_retval @ r3<- &self->retval 648 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 649 stmia r3, {r0-r1} @ retval<- r0/r1 650 b common_returnFromMethod 651 652/* ------------------------------ */ 653 .balign 64 654.L_OP_RETURN_OBJECT: /* 0x11 */ 655/* File: armv5te/OP_RETURN_OBJECT.S */ 656/* File: armv5te/OP_RETURN.S */ 657 /* 658 * Return a 32-bit value. Copies the return value into the "thread" 659 * structure, then jumps to the return handler. 660 * 661 * for: return, return-object 662 */ 663 /* op vAA */ 664 mov r2, rINST, lsr #8 @ r2<- AA 665 GET_VREG(r0, r2) @ r0<- vAA 666 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 667 b common_returnFromMethod 668 669 670/* ------------------------------ */ 671 .balign 64 672.L_OP_CONST_4: /* 0x12 */ 673/* File: armv5te/OP_CONST_4.S */ 674 /* const/4 vA, #+B */ 675 mov r1, rINST, lsl #16 @ r1<- Bxxx0000 676 mov r0, rINST, lsr #8 @ r0<- A+ 677 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 678 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 679 and r0, r0, #15 680 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 681 SET_VREG(r1, r0) @ fp[A]<- r1 682 GOTO_OPCODE(ip) @ execute next instruction 683 684/* ------------------------------ */ 685 .balign 64 686.L_OP_CONST_16: /* 0x13 */ 687/* File: armv5te/OP_CONST_16.S */ 688 /* const/16 vAA, #+BBBB */ 689 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 690 mov r3, rINST, lsr #8 @ r3<- AA 691 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 692 SET_VREG(r0, r3) @ vAA<- r0 693 GET_INST_OPCODE(ip) @ extract opcode from rINST 694 GOTO_OPCODE(ip) @ jump to next instruction 695 696/* ------------------------------ */ 697 .balign 64 698.L_OP_CONST: /* 0x14 */ 699/* File: armv5te/OP_CONST.S */ 700 /* const vAA, #+BBBBbbbb */ 701 mov r3, rINST, lsr #8 @ r3<- AA 702 FETCH(r0, 1) @ r0<- bbbb (low) 703 FETCH(r1, 2) @ r1<- BBBB (high) 704 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 705 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 706 GET_INST_OPCODE(ip) @ extract opcode from rINST 707 SET_VREG(r0, r3) @ vAA<- r0 708 GOTO_OPCODE(ip) @ jump to next instruction 709 710/* ------------------------------ */ 711 .balign 64 712.L_OP_CONST_HIGH16: /* 0x15 */ 713/* File: armv5te/OP_CONST_HIGH16.S */ 714 /* const/high16 vAA, #+BBBB0000 */ 715 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 716 mov r3, rINST, lsr #8 @ r3<- AA 717 mov r0, r0, lsl #16 @ r0<- BBBB0000 718 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 719 SET_VREG(r0, r3) @ vAA<- r0 720 GET_INST_OPCODE(ip) @ extract opcode from rINST 721 GOTO_OPCODE(ip) @ jump to next instruction 722 723/* ------------------------------ */ 724 .balign 64 725.L_OP_CONST_WIDE_16: /* 0x16 */ 726/* File: armv5te/OP_CONST_WIDE_16.S */ 727 /* const-wide/16 vAA, #+BBBB */ 728 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 729 mov r3, rINST, lsr #8 @ r3<- AA 730 mov r1, r0, asr #31 @ r1<- ssssssss 731 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 732 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 733 GET_INST_OPCODE(ip) @ extract opcode from rINST 734 stmia r3, {r0-r1} @ vAA<- r0/r1 735 GOTO_OPCODE(ip) @ jump to next instruction 736 737/* ------------------------------ */ 738 .balign 64 739.L_OP_CONST_WIDE_32: /* 0x17 */ 740/* File: armv5te/OP_CONST_WIDE_32.S */ 741 /* const-wide/32 vAA, #+BBBBbbbb */ 742 FETCH(r0, 1) @ r0<- 0000bbbb (low) 743 mov r3, rINST, lsr #8 @ r3<- AA 744 FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 745 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 746 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 747 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 748 mov r1, r0, asr #31 @ r1<- ssssssss 749 GET_INST_OPCODE(ip) @ extract opcode from rINST 750 stmia r3, {r0-r1} @ vAA<- r0/r1 751 GOTO_OPCODE(ip) @ jump to next instruction 752 753/* ------------------------------ */ 754 .balign 64 755.L_OP_CONST_WIDE: /* 0x18 */ 756/* File: armv5te/OP_CONST_WIDE.S */ 757 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 758 FETCH(r0, 1) @ r0<- bbbb (low) 759 FETCH(r1, 2) @ r1<- BBBB (low middle) 760 FETCH(r2, 3) @ r2<- hhhh (high middle) 761 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 762 FETCH(r3, 4) @ r3<- HHHH (high) 763 mov r9, rINST, lsr #8 @ r9<- AA 764 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 765 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 766 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 767 GET_INST_OPCODE(ip) @ extract opcode from rINST 768 stmia r9, {r0-r1} @ vAA<- r0/r1 769 GOTO_OPCODE(ip) @ jump to next instruction 770 771/* ------------------------------ */ 772 .balign 64 773.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 774/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 775 /* const-wide/high16 vAA, #+BBBB000000000000 */ 776 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 777 mov r3, rINST, lsr #8 @ r3<- AA 778 mov r0, #0 @ r0<- 00000000 779 mov r1, r1, lsl #16 @ r1<- BBBB0000 780 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 781 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 782 GET_INST_OPCODE(ip) @ extract opcode from rINST 783 stmia r3, {r0-r1} @ vAA<- r0/r1 784 GOTO_OPCODE(ip) @ jump to next instruction 785 786/* ------------------------------ */ 787 .balign 64 788.L_OP_CONST_STRING: /* 0x1a */ 789/* File: armv5te/OP_CONST_STRING.S */ 790 /* const/string vAA, String@BBBB */ 791 FETCH(r1, 1) @ r1<- BBBB 792 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 793 mov r9, rINST, lsr #8 @ r9<- AA 794 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 795 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 796 cmp r0, #0 @ not yet resolved? 797 beq .LOP_CONST_STRING_resolve 798 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 799 GET_INST_OPCODE(ip) @ extract opcode from rINST 800 SET_VREG(r0, r9) @ vAA<- r0 801 GOTO_OPCODE(ip) @ jump to next instruction 802 803/* ------------------------------ */ 804 .balign 64 805.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 806/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 807 /* const/string vAA, String@BBBBBBBB */ 808 FETCH(r0, 1) @ r0<- bbbb (low) 809 FETCH(r1, 2) @ r1<- BBBB (high) 810 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 811 mov r9, rINST, lsr #8 @ r9<- AA 812 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 813 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 814 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 815 cmp r0, #0 816 beq .LOP_CONST_STRING_JUMBO_resolve 817 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 818 GET_INST_OPCODE(ip) @ extract opcode from rINST 819 SET_VREG(r0, r9) @ vAA<- r0 820 GOTO_OPCODE(ip) @ jump to next instruction 821 822/* ------------------------------ */ 823 .balign 64 824.L_OP_CONST_CLASS: /* 0x1c */ 825/* File: armv5te/OP_CONST_CLASS.S */ 826 /* const/class vAA, Class@BBBB */ 827 FETCH(r1, 1) @ r1<- BBBB 828 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 829 mov r9, rINST, lsr #8 @ r9<- AA 830 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 831 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 832 cmp r0, #0 @ not yet resolved? 833 beq .LOP_CONST_CLASS_resolve 834 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 835 GET_INST_OPCODE(ip) @ extract opcode from rINST 836 SET_VREG(r0, r9) @ vAA<- r0 837 GOTO_OPCODE(ip) @ jump to next instruction 838 839/* ------------------------------ */ 840 .balign 64 841.L_OP_MONITOR_ENTER: /* 0x1d */ 842/* File: armv5te/OP_MONITOR_ENTER.S */ 843 /* 844 * Synchronize on an object. 845 */ 846 /* monitor-enter vAA */ 847 mov r2, rINST, lsr #8 @ r2<- AA 848 GET_VREG(r1, r2) @ r1<- vAA (object) 849 mov r0, rSELF @ r0<- self 850 cmp r1, #0 @ null object? 851 EXPORT_PC() @ need for precise GC 852 beq common_errNullObject @ null object, throw an exception 853 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 854 bl dvmLockObject @ call(self, obj) 855 GET_INST_OPCODE(ip) @ extract opcode from rINST 856 GOTO_OPCODE(ip) @ jump to next instruction 857 858/* ------------------------------ */ 859 .balign 64 860.L_OP_MONITOR_EXIT: /* 0x1e */ 861/* File: armv5te/OP_MONITOR_EXIT.S */ 862 /* 863 * Unlock an object. 864 * 865 * Exceptions that occur when unlocking a monitor need to appear as 866 * if they happened at the following instruction. See the Dalvik 867 * instruction spec. 868 */ 869 /* monitor-exit vAA */ 870 mov r2, rINST, lsr #8 @ r2<- AA 871 EXPORT_PC() @ before fetch: export the PC 872 GET_VREG(r1, r2) @ r1<- vAA (object) 873 cmp r1, #0 @ null object? 874 beq 1f @ yes 875 mov r0, rSELF @ r0<- self 876 bl dvmUnlockObject @ r0<- success for unlock(self, obj) 877 cmp r0, #0 @ failed? 878 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 879 beq common_exceptionThrown @ yes, exception is pending 880 GET_INST_OPCODE(ip) @ extract opcode from rINST 881 GOTO_OPCODE(ip) @ jump to next instruction 8821: 883 FETCH_ADVANCE_INST(1) @ advance before throw 884 b common_errNullObject 885 886/* ------------------------------ */ 887 .balign 64 888.L_OP_CHECK_CAST: /* 0x1f */ 889/* File: armv5te/OP_CHECK_CAST.S */ 890 /* 891 * Check to see if a cast from one class to another is allowed. 892 */ 893 /* check-cast vAA, class@BBBB */ 894 mov r3, rINST, lsr #8 @ r3<- AA 895 FETCH(r2, 1) @ r2<- BBBB 896 GET_VREG(r9, r3) @ r9<- object 897 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 898 cmp r9, #0 @ is object null? 899 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 900 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 901 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 902 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 903 cmp r1, #0 @ have we resolved this before? 904 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 905.LOP_CHECK_CAST_resolved: 906 cmp r0, r1 @ same class (trivial success)? 907 bne .LOP_CHECK_CAST_fullcheck @ no, do full check 908.LOP_CHECK_CAST_okay: 909 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 910 GET_INST_OPCODE(ip) @ extract opcode from rINST 911 GOTO_OPCODE(ip) @ jump to next instruction 912 913/* ------------------------------ */ 914 .balign 64 915.L_OP_INSTANCE_OF: /* 0x20 */ 916/* File: armv5te/OP_INSTANCE_OF.S */ 917 /* 918 * Check to see if an object reference is an instance of a class. 919 * 920 * Most common situation is a non-null object, being compared against 921 * an already-resolved class. 922 */ 923 /* instance-of vA, vB, class@CCCC */ 924 mov r3, rINST, lsr #12 @ r3<- B 925 mov r9, rINST, lsr #8 @ r9<- A+ 926 GET_VREG(r0, r3) @ r0<- vB (object) 927 and r9, r9, #15 @ r9<- A 928 cmp r0, #0 @ is object null? 929 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 930 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 931 FETCH(r3, 1) @ r3<- CCCC 932 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 933 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 934 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 935 cmp r1, #0 @ have we resolved this before? 936 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 937.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 938 cmp r0, r1 @ same class (trivial success)? 939 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 940 b .LOP_INSTANCE_OF_fullcheck @ no, do full check 941 942/* ------------------------------ */ 943 .balign 64 944.L_OP_ARRAY_LENGTH: /* 0x21 */ 945/* File: armv5te/OP_ARRAY_LENGTH.S */ 946 /* 947 * Return the length of an array. 948 */ 949 mov r1, rINST, lsr #12 @ r1<- B 950 mov r2, rINST, lsr #8 @ r2<- A+ 951 GET_VREG(r0, r1) @ r0<- vB (object ref) 952 and r2, r2, #15 @ r2<- A 953 cmp r0, #0 @ is object null? 954 beq common_errNullObject @ yup, fail 955 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 956 ldr r3, [r0, #offArrayObject_length] @ r3<- array length 957 GET_INST_OPCODE(ip) @ extract opcode from rINST 958 SET_VREG(r3, r2) @ vB<- length 959 GOTO_OPCODE(ip) @ jump to next instruction 960 961/* ------------------------------ */ 962 .balign 64 963.L_OP_NEW_INSTANCE: /* 0x22 */ 964/* File: armv5te/OP_NEW_INSTANCE.S */ 965 /* 966 * Create a new instance of a class. 967 */ 968 /* new-instance vAA, class@BBBB */ 969 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 970 FETCH(r1, 1) @ r1<- BBBB 971 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 972 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 973 EXPORT_PC() @ req'd for init, resolve, alloc 974 cmp r0, #0 @ already resolved? 975 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 976.LOP_NEW_INSTANCE_resolved: @ r0=class 977 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 978 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 979 bne .LOP_NEW_INSTANCE_needinit @ no, init class now 980.LOP_NEW_INSTANCE_initialized: @ r0=class 981 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 982 bl dvmAllocObject @ r0<- new object 983 b .LOP_NEW_INSTANCE_finish @ continue 984 985/* ------------------------------ */ 986 .balign 64 987.L_OP_NEW_ARRAY: /* 0x23 */ 988/* File: armv5te/OP_NEW_ARRAY.S */ 989 /* 990 * Allocate an array of objects, specified with the array class 991 * and a count. 992 * 993 * The verifier guarantees that this is an array class, so we don't 994 * check for it here. 995 */ 996 /* new-array vA, vB, class@CCCC */ 997 mov r0, rINST, lsr #12 @ r0<- B 998 FETCH(r2, 1) @ r2<- CCCC 999 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1000 GET_VREG(r1, r0) @ r1<- vB (array length) 1001 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1002 cmp r1, #0 @ check length 1003 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1004 bmi common_errNegativeArraySize @ negative length, bail - len in r1 1005 cmp r0, #0 @ already resolved? 1006 EXPORT_PC() @ req'd for resolve, alloc 1007 bne .LOP_NEW_ARRAY_finish @ resolved, continue 1008 b .LOP_NEW_ARRAY_resolve @ do resolve now 1009 1010/* ------------------------------ */ 1011 .balign 64 1012.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1013/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1014 /* 1015 * Create a new array with elements filled from registers. 1016 * 1017 * for: filled-new-array, filled-new-array/range 1018 */ 1019 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1020 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1021 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1022 FETCH(r1, 1) @ r1<- BBBB 1023 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1024 EXPORT_PC() @ need for resolve and alloc 1025 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1026 mov r10, rINST, lsr #8 @ r10<- AA or BA 1027 cmp r0, #0 @ already resolved? 1028 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 10298: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1030 mov r2, #0 @ r2<- false 1031 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1032 bl dvmResolveClass @ r0<- call(clazz, ref) 1033 cmp r0, #0 @ got null? 1034 beq common_exceptionThrown @ yes, handle exception 1035 b .LOP_FILLED_NEW_ARRAY_continue 1036 1037/* ------------------------------ */ 1038 .balign 64 1039.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1040/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1041/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1042 /* 1043 * Create a new array with elements filled from registers. 1044 * 1045 * for: filled-new-array, filled-new-array/range 1046 */ 1047 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1048 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1049 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1050 FETCH(r1, 1) @ r1<- BBBB 1051 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1052 EXPORT_PC() @ need for resolve and alloc 1053 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1054 mov r10, rINST, lsr #8 @ r10<- AA or BA 1055 cmp r0, #0 @ already resolved? 1056 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 10578: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1058 mov r2, #0 @ r2<- false 1059 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1060 bl dvmResolveClass @ r0<- call(clazz, ref) 1061 cmp r0, #0 @ got null? 1062 beq common_exceptionThrown @ yes, handle exception 1063 b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1064 1065 1066/* ------------------------------ */ 1067 .balign 64 1068.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1069/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1070 /* fill-array-data vAA, +BBBBBBBB */ 1071 FETCH(r0, 1) @ r0<- bbbb (lo) 1072 FETCH(r1, 2) @ r1<- BBBB (hi) 1073 mov r3, rINST, lsr #8 @ r3<- AA 1074 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1075 GET_VREG(r0, r3) @ r0<- vAA (array object) 1076 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1077 EXPORT_PC(); 1078 bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1079 cmp r0, #0 @ 0 means an exception is thrown 1080 beq common_exceptionThrown @ has exception 1081 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1082 GET_INST_OPCODE(ip) @ extract opcode from rINST 1083 GOTO_OPCODE(ip) @ jump to next instruction 1084 1085/* ------------------------------ */ 1086 .balign 64 1087.L_OP_THROW: /* 0x27 */ 1088/* File: armv5te/OP_THROW.S */ 1089 /* 1090 * Throw an exception object in the current thread. 1091 */ 1092 /* throw vAA */ 1093 mov r2, rINST, lsr #8 @ r2<- AA 1094 GET_VREG(r1, r2) @ r1<- vAA (exception object) 1095 EXPORT_PC() @ exception handler can throw 1096 cmp r1, #0 @ null object? 1097 beq common_errNullObject @ yes, throw an NPE instead 1098 @ bypass dvmSetException, just store it 1099 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj 1100 b common_exceptionThrown 1101 1102/* ------------------------------ */ 1103 .balign 64 1104.L_OP_GOTO: /* 0x28 */ 1105/* File: armv5te/OP_GOTO.S */ 1106 /* 1107 * Unconditional branch, 8-bit offset. 1108 * 1109 * The branch distance is a signed code-unit offset, which we need to 1110 * double to get a byte offset. 1111 */ 1112 /* goto +AA */ 1113 mov r0, rINST, lsl #16 @ r0<- AAxx0000 1114 movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1115 mov r9, r9, lsl #1 @ r9<- byte offset 1116 bmi common_backwardBranch @ backward branch, do periodic checks 1117#if defined(WITH_JIT) 1118 GET_JIT_PROF_TABLE(r0) 1119 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1120 cmp r0,#0 1121 bne common_updateProfile 1122 GET_INST_OPCODE(ip) @ extract opcode from rINST 1123 GOTO_OPCODE(ip) @ jump to next instruction 1124#else 1125 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1126 GET_INST_OPCODE(ip) @ extract opcode from rINST 1127 GOTO_OPCODE(ip) @ jump to next instruction 1128#endif 1129 1130/* ------------------------------ */ 1131 .balign 64 1132.L_OP_GOTO_16: /* 0x29 */ 1133/* File: armv5te/OP_GOTO_16.S */ 1134 /* 1135 * Unconditional branch, 16-bit offset. 1136 * 1137 * The branch distance is a signed code-unit offset, which we need to 1138 * double to get a byte offset. 1139 */ 1140 /* goto/16 +AAAA */ 1141 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1142 movs r9, r0, asl #1 @ r9<- byte offset, check sign 1143 bmi common_backwardBranch @ backward branch, do periodic checks 1144#if defined(WITH_JIT) 1145 GET_JIT_PROF_TABLE(r0) 1146 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1147 cmp r0,#0 1148 bne common_updateProfile 1149 GET_INST_OPCODE(ip) @ extract opcode from rINST 1150 GOTO_OPCODE(ip) @ jump to next instruction 1151#else 1152 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1153 GET_INST_OPCODE(ip) @ extract opcode from rINST 1154 GOTO_OPCODE(ip) @ jump to next instruction 1155#endif 1156 1157/* ------------------------------ */ 1158 .balign 64 1159.L_OP_GOTO_32: /* 0x2a */ 1160/* File: armv5te/OP_GOTO_32.S */ 1161 /* 1162 * Unconditional branch, 32-bit offset. 1163 * 1164 * The branch distance is a signed code-unit offset, which we need to 1165 * double to get a byte offset. 1166 * 1167 * Unlike most opcodes, this one is allowed to branch to itself, so 1168 * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1169 * instruction doesn't affect the V flag, so we need to clear it 1170 * explicitly. 1171 */ 1172 /* goto/32 +AAAAAAAA */ 1173 FETCH(r0, 1) @ r0<- aaaa (lo) 1174 FETCH(r1, 2) @ r1<- AAAA (hi) 1175 cmp ip, ip @ (clear V flag during stall) 1176 orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1177 mov r9, r0, asl #1 @ r9<- byte offset 1178 ble common_backwardBranch @ backward branch, do periodic checks 1179#if defined(WITH_JIT) 1180 GET_JIT_PROF_TABLE(r0) 1181 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1182 cmp r0,#0 1183 bne common_updateProfile 1184 GET_INST_OPCODE(ip) @ extract opcode from rINST 1185 GOTO_OPCODE(ip) @ jump to next instruction 1186#else 1187 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1188 GET_INST_OPCODE(ip) @ extract opcode from rINST 1189 GOTO_OPCODE(ip) @ jump to next instruction 1190#endif 1191 1192/* ------------------------------ */ 1193 .balign 64 1194.L_OP_PACKED_SWITCH: /* 0x2b */ 1195/* File: armv5te/OP_PACKED_SWITCH.S */ 1196 /* 1197 * Handle a packed-switch or sparse-switch instruction. In both cases 1198 * we decode it and hand it off to a helper function. 1199 * 1200 * We don't really expect backward branches in a switch statement, but 1201 * they're perfectly legal, so we check for them here. 1202 * 1203 * for: packed-switch, sparse-switch 1204 */ 1205 /* op vAA, +BBBB */ 1206 FETCH(r0, 1) @ r0<- bbbb (lo) 1207 FETCH(r1, 2) @ r1<- BBBB (hi) 1208 mov r3, rINST, lsr #8 @ r3<- AA 1209 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1210 GET_VREG(r1, r3) @ r1<- vAA 1211 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1212 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1213 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1214 bmi common_backwardBranch @ backward branch, do periodic checks 1215 beq common_backwardBranch @ (want to use BLE but V is unknown) 1216#if defined(WITH_JIT) 1217 GET_JIT_PROF_TABLE(r0) 1218 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1219 cmp r0,#0 1220 bne common_updateProfile 1221 GET_INST_OPCODE(ip) @ extract opcode from rINST 1222 GOTO_OPCODE(ip) @ jump to next instruction 1223#else 1224 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1225 GET_INST_OPCODE(ip) @ extract opcode from rINST 1226 GOTO_OPCODE(ip) @ jump to next instruction 1227#endif 1228 1229/* ------------------------------ */ 1230 .balign 64 1231.L_OP_SPARSE_SWITCH: /* 0x2c */ 1232/* File: armv5te/OP_SPARSE_SWITCH.S */ 1233/* File: armv5te/OP_PACKED_SWITCH.S */ 1234 /* 1235 * Handle a packed-switch or sparse-switch instruction. In both cases 1236 * we decode it and hand it off to a helper function. 1237 * 1238 * We don't really expect backward branches in a switch statement, but 1239 * they're perfectly legal, so we check for them here. 1240 * 1241 * for: packed-switch, sparse-switch 1242 */ 1243 /* op vAA, +BBBB */ 1244 FETCH(r0, 1) @ r0<- bbbb (lo) 1245 FETCH(r1, 2) @ r1<- BBBB (hi) 1246 mov r3, rINST, lsr #8 @ r3<- AA 1247 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1248 GET_VREG(r1, r3) @ r1<- vAA 1249 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1250 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1251 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1252 bmi common_backwardBranch @ backward branch, do periodic checks 1253 beq common_backwardBranch @ (want to use BLE but V is unknown) 1254#if defined(WITH_JIT) 1255 GET_JIT_PROF_TABLE(r0) 1256 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1257 cmp r0,#0 1258 bne common_updateProfile 1259 GET_INST_OPCODE(ip) @ extract opcode from rINST 1260 GOTO_OPCODE(ip) @ jump to next instruction 1261#else 1262 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1263 GET_INST_OPCODE(ip) @ extract opcode from rINST 1264 GOTO_OPCODE(ip) @ jump to next instruction 1265#endif 1266 1267 1268/* ------------------------------ */ 1269 .balign 64 1270.L_OP_CMPL_FLOAT: /* 0x2d */ 1271/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1272 /* 1273 * Compare two floating-point values. Puts 0, 1, or -1 into the 1274 * destination register based on the results of the comparison. 1275 * 1276 * int compare(x, y) { 1277 * if (x == y) { 1278 * return 0; 1279 * } else if (x > y) { 1280 * return 1; 1281 * } else if (x < y) { 1282 * return -1; 1283 * } else { 1284 * return -1; 1285 * } 1286 * } 1287 */ 1288 /* op vAA, vBB, vCC */ 1289 FETCH(r0, 1) @ r0<- CCBB 1290 mov r9, rINST, lsr #8 @ r9<- AA 1291 and r2, r0, #255 @ r2<- BB 1292 mov r3, r0, lsr #8 @ r3<- CC 1293 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1294 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1295 flds s0, [r2] @ s0<- vBB 1296 flds s1, [r3] @ s1<- vCC 1297 fcmpes s0, s1 @ compare (vBB, vCC) 1298 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1299 mvn r0, #0 @ r0<- -1 (default) 1300 GET_INST_OPCODE(ip) @ extract opcode from rINST 1301 fmstat @ export status flags 1302 movgt r0, #1 @ (greater than) r1<- 1 1303 moveq r0, #0 @ (equal) r1<- 0 1304 b .LOP_CMPL_FLOAT_finish @ argh 1305 1306 1307/* ------------------------------ */ 1308 .balign 64 1309.L_OP_CMPG_FLOAT: /* 0x2e */ 1310/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1311 /* 1312 * Compare two floating-point values. Puts 0, 1, or -1 into the 1313 * destination register based on the results of the comparison. 1314 * 1315 * int compare(x, y) { 1316 * if (x == y) { 1317 * return 0; 1318 * } else if (x < y) { 1319 * return -1; 1320 * } else if (x > y) { 1321 * return 1; 1322 * } else { 1323 * return 1; 1324 * } 1325 * } 1326 */ 1327 /* op vAA, vBB, vCC */ 1328 FETCH(r0, 1) @ r0<- CCBB 1329 mov r9, rINST, lsr #8 @ r9<- AA 1330 and r2, r0, #255 @ r2<- BB 1331 mov r3, r0, lsr #8 @ r3<- CC 1332 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1333 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1334 flds s0, [r2] @ s0<- vBB 1335 flds s1, [r3] @ s1<- vCC 1336 fcmpes s0, s1 @ compare (vBB, vCC) 1337 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1338 mov r0, #1 @ r0<- 1 (default) 1339 GET_INST_OPCODE(ip) @ extract opcode from rINST 1340 fmstat @ export status flags 1341 mvnmi r0, #0 @ (less than) r1<- -1 1342 moveq r0, #0 @ (equal) r1<- 0 1343 b .LOP_CMPG_FLOAT_finish @ argh 1344 1345 1346/* ------------------------------ */ 1347 .balign 64 1348.L_OP_CMPL_DOUBLE: /* 0x2f */ 1349/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1350 /* 1351 * Compare two floating-point values. Puts 0, 1, or -1 into the 1352 * destination register based on the results of the comparison. 1353 * 1354 * int compare(x, y) { 1355 * if (x == y) { 1356 * return 0; 1357 * } else if (x > y) { 1358 * return 1; 1359 * } else if (x < y) { 1360 * return -1; 1361 * } else { 1362 * return -1; 1363 * } 1364 * } 1365 */ 1366 /* op vAA, vBB, vCC */ 1367 FETCH(r0, 1) @ r0<- CCBB 1368 mov r9, rINST, lsr #8 @ r9<- AA 1369 and r2, r0, #255 @ r2<- BB 1370 mov r3, r0, lsr #8 @ r3<- CC 1371 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1372 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1373 fldd d0, [r2] @ d0<- vBB 1374 fldd d1, [r3] @ d1<- vCC 1375 fcmped d0, d1 @ compare (vBB, vCC) 1376 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1377 mvn r0, #0 @ r0<- -1 (default) 1378 GET_INST_OPCODE(ip) @ extract opcode from rINST 1379 fmstat @ export status flags 1380 movgt r0, #1 @ (greater than) r1<- 1 1381 moveq r0, #0 @ (equal) r1<- 0 1382 b .LOP_CMPL_DOUBLE_finish @ argh 1383 1384 1385/* ------------------------------ */ 1386 .balign 64 1387.L_OP_CMPG_DOUBLE: /* 0x30 */ 1388/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1389 /* 1390 * Compare two floating-point values. Puts 0, 1, or -1 into the 1391 * destination register based on the results of the comparison. 1392 * 1393 * int compare(x, y) { 1394 * if (x == y) { 1395 * return 0; 1396 * } else if (x < y) { 1397 * return -1; 1398 * } else if (x > y) { 1399 * return 1; 1400 * } else { 1401 * return 1; 1402 * } 1403 * } 1404 */ 1405 /* op vAA, vBB, vCC */ 1406 FETCH(r0, 1) @ r0<- CCBB 1407 mov r9, rINST, lsr #8 @ r9<- AA 1408 and r2, r0, #255 @ r2<- BB 1409 mov r3, r0, lsr #8 @ r3<- CC 1410 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1411 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1412 fldd d0, [r2] @ d0<- vBB 1413 fldd d1, [r3] @ d1<- vCC 1414 fcmped d0, d1 @ compare (vBB, vCC) 1415 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1416 mov r0, #1 @ r0<- 1 (default) 1417 GET_INST_OPCODE(ip) @ extract opcode from rINST 1418 fmstat @ export status flags 1419 mvnmi r0, #0 @ (less than) r1<- -1 1420 moveq r0, #0 @ (equal) r1<- 0 1421 b .LOP_CMPG_DOUBLE_finish @ argh 1422 1423 1424/* ------------------------------ */ 1425 .balign 64 1426.L_OP_CMP_LONG: /* 0x31 */ 1427/* File: armv5te/OP_CMP_LONG.S */ 1428 /* 1429 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1430 * register based on the results of the comparison. 1431 * 1432 * We load the full values with LDM, but in practice many values could 1433 * be resolved by only looking at the high word. This could be made 1434 * faster or slower by splitting the LDM into a pair of LDRs. 1435 * 1436 * If we just wanted to set condition flags, we could do this: 1437 * subs ip, r0, r2 1438 * sbcs ip, r1, r3 1439 * subeqs ip, r0, r2 1440 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1441 * integer value, which we can do with 2 conditional mov/mvn instructions 1442 * (set 1, set -1; if they're equal we already have 0 in ip), giving 1443 * us a constant 5-cycle path plus a branch at the end to the 1444 * instruction epilogue code. The multi-compare approach below needs 1445 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1446 * in the worst case (the 64-bit values are equal). 1447 */ 1448 /* cmp-long vAA, vBB, vCC */ 1449 FETCH(r0, 1) @ r0<- CCBB 1450 mov r9, rINST, lsr #8 @ r9<- AA 1451 and r2, r0, #255 @ r2<- BB 1452 mov r3, r0, lsr #8 @ r3<- CC 1453 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1454 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1455 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1456 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1457 cmp r1, r3 @ compare (vBB+1, vCC+1) 1458 blt .LOP_CMP_LONG_less @ signed compare on high part 1459 bgt .LOP_CMP_LONG_greater 1460 subs r1, r0, r2 @ r1<- r0 - r2 1461 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1462 bne .LOP_CMP_LONG_less 1463 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1464 1465/* ------------------------------ */ 1466 .balign 64 1467.L_OP_IF_EQ: /* 0x32 */ 1468/* File: armv5te/OP_IF_EQ.S */ 1469/* File: armv5te/bincmp.S */ 1470 /* 1471 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1472 * fragment that specifies the *reverse* comparison to perform, e.g. 1473 * for "if-le" you would use "gt". 1474 * 1475 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1476 */ 1477 /* if-cmp vA, vB, +CCCC */ 1478 mov r0, rINST, lsr #8 @ r0<- A+ 1479 mov r1, rINST, lsr #12 @ r1<- B 1480 and r0, r0, #15 1481 GET_VREG(r3, r1) @ r3<- vB 1482 GET_VREG(r2, r0) @ r2<- vA 1483 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1484 cmp r2, r3 @ compare (vA, vB) 1485 bne 1f @ branch to 1 if comparison failed 1486 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1487 movs r9, r9, asl #1 @ convert to bytes, check sign 1488 bmi common_backwardBranch @ yes, do periodic checks 14891: 1490#if defined(WITH_JIT) 1491 GET_JIT_PROF_TABLE(r0) 1492 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1493 b common_testUpdateProfile 1494#else 1495 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1496 GET_INST_OPCODE(ip) @ extract opcode from rINST 1497 GOTO_OPCODE(ip) @ jump to next instruction 1498#endif 1499 1500 1501/* ------------------------------ */ 1502 .balign 64 1503.L_OP_IF_NE: /* 0x33 */ 1504/* File: armv5te/OP_IF_NE.S */ 1505/* File: armv5te/bincmp.S */ 1506 /* 1507 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1508 * fragment that specifies the *reverse* comparison to perform, e.g. 1509 * for "if-le" you would use "gt". 1510 * 1511 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1512 */ 1513 /* if-cmp vA, vB, +CCCC */ 1514 mov r0, rINST, lsr #8 @ r0<- A+ 1515 mov r1, rINST, lsr #12 @ r1<- B 1516 and r0, r0, #15 1517 GET_VREG(r3, r1) @ r3<- vB 1518 GET_VREG(r2, r0) @ r2<- vA 1519 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1520 cmp r2, r3 @ compare (vA, vB) 1521 beq 1f @ branch to 1 if comparison failed 1522 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1523 movs r9, r9, asl #1 @ convert to bytes, check sign 1524 bmi common_backwardBranch @ yes, do periodic checks 15251: 1526#if defined(WITH_JIT) 1527 GET_JIT_PROF_TABLE(r0) 1528 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1529 b common_testUpdateProfile 1530#else 1531 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1532 GET_INST_OPCODE(ip) @ extract opcode from rINST 1533 GOTO_OPCODE(ip) @ jump to next instruction 1534#endif 1535 1536 1537/* ------------------------------ */ 1538 .balign 64 1539.L_OP_IF_LT: /* 0x34 */ 1540/* File: armv5te/OP_IF_LT.S */ 1541/* File: armv5te/bincmp.S */ 1542 /* 1543 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1544 * fragment that specifies the *reverse* comparison to perform, e.g. 1545 * for "if-le" you would use "gt". 1546 * 1547 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1548 */ 1549 /* if-cmp vA, vB, +CCCC */ 1550 mov r0, rINST, lsr #8 @ r0<- A+ 1551 mov r1, rINST, lsr #12 @ r1<- B 1552 and r0, r0, #15 1553 GET_VREG(r3, r1) @ r3<- vB 1554 GET_VREG(r2, r0) @ r2<- vA 1555 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1556 cmp r2, r3 @ compare (vA, vB) 1557 bge 1f @ branch to 1 if comparison failed 1558 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1559 movs r9, r9, asl #1 @ convert to bytes, check sign 1560 bmi common_backwardBranch @ yes, do periodic checks 15611: 1562#if defined(WITH_JIT) 1563 GET_JIT_PROF_TABLE(r0) 1564 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1565 b common_testUpdateProfile 1566#else 1567 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1568 GET_INST_OPCODE(ip) @ extract opcode from rINST 1569 GOTO_OPCODE(ip) @ jump to next instruction 1570#endif 1571 1572 1573/* ------------------------------ */ 1574 .balign 64 1575.L_OP_IF_GE: /* 0x35 */ 1576/* File: armv5te/OP_IF_GE.S */ 1577/* File: armv5te/bincmp.S */ 1578 /* 1579 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1580 * fragment that specifies the *reverse* comparison to perform, e.g. 1581 * for "if-le" you would use "gt". 1582 * 1583 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1584 */ 1585 /* if-cmp vA, vB, +CCCC */ 1586 mov r0, rINST, lsr #8 @ r0<- A+ 1587 mov r1, rINST, lsr #12 @ r1<- B 1588 and r0, r0, #15 1589 GET_VREG(r3, r1) @ r3<- vB 1590 GET_VREG(r2, r0) @ r2<- vA 1591 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1592 cmp r2, r3 @ compare (vA, vB) 1593 blt 1f @ branch to 1 if comparison failed 1594 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1595 movs r9, r9, asl #1 @ convert to bytes, check sign 1596 bmi common_backwardBranch @ yes, do periodic checks 15971: 1598#if defined(WITH_JIT) 1599 GET_JIT_PROF_TABLE(r0) 1600 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1601 b common_testUpdateProfile 1602#else 1603 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1604 GET_INST_OPCODE(ip) @ extract opcode from rINST 1605 GOTO_OPCODE(ip) @ jump to next instruction 1606#endif 1607 1608 1609/* ------------------------------ */ 1610 .balign 64 1611.L_OP_IF_GT: /* 0x36 */ 1612/* File: armv5te/OP_IF_GT.S */ 1613/* File: armv5te/bincmp.S */ 1614 /* 1615 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1616 * fragment that specifies the *reverse* comparison to perform, e.g. 1617 * for "if-le" you would use "gt". 1618 * 1619 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1620 */ 1621 /* if-cmp vA, vB, +CCCC */ 1622 mov r0, rINST, lsr #8 @ r0<- A+ 1623 mov r1, rINST, lsr #12 @ r1<- B 1624 and r0, r0, #15 1625 GET_VREG(r3, r1) @ r3<- vB 1626 GET_VREG(r2, r0) @ r2<- vA 1627 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1628 cmp r2, r3 @ compare (vA, vB) 1629 ble 1f @ branch to 1 if comparison failed 1630 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1631 movs r9, r9, asl #1 @ convert to bytes, check sign 1632 bmi common_backwardBranch @ yes, do periodic checks 16331: 1634#if defined(WITH_JIT) 1635 GET_JIT_PROF_TABLE(r0) 1636 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1637 b common_testUpdateProfile 1638#else 1639 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1640 GET_INST_OPCODE(ip) @ extract opcode from rINST 1641 GOTO_OPCODE(ip) @ jump to next instruction 1642#endif 1643 1644 1645/* ------------------------------ */ 1646 .balign 64 1647.L_OP_IF_LE: /* 0x37 */ 1648/* File: armv5te/OP_IF_LE.S */ 1649/* File: armv5te/bincmp.S */ 1650 /* 1651 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1652 * fragment that specifies the *reverse* comparison to perform, e.g. 1653 * for "if-le" you would use "gt". 1654 * 1655 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1656 */ 1657 /* if-cmp vA, vB, +CCCC */ 1658 mov r0, rINST, lsr #8 @ r0<- A+ 1659 mov r1, rINST, lsr #12 @ r1<- B 1660 and r0, r0, #15 1661 GET_VREG(r3, r1) @ r3<- vB 1662 GET_VREG(r2, r0) @ r2<- vA 1663 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1664 cmp r2, r3 @ compare (vA, vB) 1665 bgt 1f @ branch to 1 if comparison failed 1666 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1667 movs r9, r9, asl #1 @ convert to bytes, check sign 1668 bmi common_backwardBranch @ yes, do periodic checks 16691: 1670#if defined(WITH_JIT) 1671 GET_JIT_PROF_TABLE(r0) 1672 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1673 b common_testUpdateProfile 1674#else 1675 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1676 GET_INST_OPCODE(ip) @ extract opcode from rINST 1677 GOTO_OPCODE(ip) @ jump to next instruction 1678#endif 1679 1680 1681/* ------------------------------ */ 1682 .balign 64 1683.L_OP_IF_EQZ: /* 0x38 */ 1684/* File: armv5te/OP_IF_EQZ.S */ 1685/* File: armv5te/zcmp.S */ 1686 /* 1687 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1688 * fragment that specifies the *reverse* comparison to perform, e.g. 1689 * for "if-le" you would use "gt". 1690 * 1691 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1692 */ 1693 /* if-cmp vAA, +BBBB */ 1694 mov r0, rINST, lsr #8 @ r0<- AA 1695 GET_VREG(r2, r0) @ r2<- vAA 1696 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1697 cmp r2, #0 @ compare (vA, 0) 1698 bne 1f @ branch to 1 if comparison failed 1699 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1700 movs r9, r9, asl #1 @ convert to bytes, check sign 1701 bmi common_backwardBranch @ backward branch, do periodic checks 17021: 1703#if defined(WITH_JIT) 1704 GET_JIT_PROF_TABLE(r0) 1705 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1706 cmp r0,#0 1707 bne common_updateProfile 1708 GET_INST_OPCODE(ip) @ extract opcode from rINST 1709 GOTO_OPCODE(ip) @ jump to next instruction 1710#else 1711 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1712 GET_INST_OPCODE(ip) @ extract opcode from rINST 1713 GOTO_OPCODE(ip) @ jump to next instruction 1714#endif 1715 1716 1717/* ------------------------------ */ 1718 .balign 64 1719.L_OP_IF_NEZ: /* 0x39 */ 1720/* File: armv5te/OP_IF_NEZ.S */ 1721/* File: armv5te/zcmp.S */ 1722 /* 1723 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1724 * fragment that specifies the *reverse* comparison to perform, e.g. 1725 * for "if-le" you would use "gt". 1726 * 1727 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1728 */ 1729 /* if-cmp vAA, +BBBB */ 1730 mov r0, rINST, lsr #8 @ r0<- AA 1731 GET_VREG(r2, r0) @ r2<- vAA 1732 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1733 cmp r2, #0 @ compare (vA, 0) 1734 beq 1f @ branch to 1 if comparison failed 1735 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1736 movs r9, r9, asl #1 @ convert to bytes, check sign 1737 bmi common_backwardBranch @ backward branch, do periodic checks 17381: 1739#if defined(WITH_JIT) 1740 GET_JIT_PROF_TABLE(r0) 1741 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1742 cmp r0,#0 1743 bne common_updateProfile 1744 GET_INST_OPCODE(ip) @ extract opcode from rINST 1745 GOTO_OPCODE(ip) @ jump to next instruction 1746#else 1747 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1748 GET_INST_OPCODE(ip) @ extract opcode from rINST 1749 GOTO_OPCODE(ip) @ jump to next instruction 1750#endif 1751 1752 1753/* ------------------------------ */ 1754 .balign 64 1755.L_OP_IF_LTZ: /* 0x3a */ 1756/* File: armv5te/OP_IF_LTZ.S */ 1757/* File: armv5te/zcmp.S */ 1758 /* 1759 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1760 * fragment that specifies the *reverse* comparison to perform, e.g. 1761 * for "if-le" you would use "gt". 1762 * 1763 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1764 */ 1765 /* if-cmp vAA, +BBBB */ 1766 mov r0, rINST, lsr #8 @ r0<- AA 1767 GET_VREG(r2, r0) @ r2<- vAA 1768 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1769 cmp r2, #0 @ compare (vA, 0) 1770 bge 1f @ branch to 1 if comparison failed 1771 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1772 movs r9, r9, asl #1 @ convert to bytes, check sign 1773 bmi common_backwardBranch @ backward branch, do periodic checks 17741: 1775#if defined(WITH_JIT) 1776 GET_JIT_PROF_TABLE(r0) 1777 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1778 cmp r0,#0 1779 bne common_updateProfile 1780 GET_INST_OPCODE(ip) @ extract opcode from rINST 1781 GOTO_OPCODE(ip) @ jump to next instruction 1782#else 1783 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1784 GET_INST_OPCODE(ip) @ extract opcode from rINST 1785 GOTO_OPCODE(ip) @ jump to next instruction 1786#endif 1787 1788 1789/* ------------------------------ */ 1790 .balign 64 1791.L_OP_IF_GEZ: /* 0x3b */ 1792/* File: armv5te/OP_IF_GEZ.S */ 1793/* File: armv5te/zcmp.S */ 1794 /* 1795 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1796 * fragment that specifies the *reverse* comparison to perform, e.g. 1797 * for "if-le" you would use "gt". 1798 * 1799 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1800 */ 1801 /* if-cmp vAA, +BBBB */ 1802 mov r0, rINST, lsr #8 @ r0<- AA 1803 GET_VREG(r2, r0) @ r2<- vAA 1804 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1805 cmp r2, #0 @ compare (vA, 0) 1806 blt 1f @ branch to 1 if comparison failed 1807 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1808 movs r9, r9, asl #1 @ convert to bytes, check sign 1809 bmi common_backwardBranch @ backward branch, do periodic checks 18101: 1811#if defined(WITH_JIT) 1812 GET_JIT_PROF_TABLE(r0) 1813 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1814 cmp r0,#0 1815 bne common_updateProfile 1816 GET_INST_OPCODE(ip) @ extract opcode from rINST 1817 GOTO_OPCODE(ip) @ jump to next instruction 1818#else 1819 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1820 GET_INST_OPCODE(ip) @ extract opcode from rINST 1821 GOTO_OPCODE(ip) @ jump to next instruction 1822#endif 1823 1824 1825/* ------------------------------ */ 1826 .balign 64 1827.L_OP_IF_GTZ: /* 0x3c */ 1828/* File: armv5te/OP_IF_GTZ.S */ 1829/* File: armv5te/zcmp.S */ 1830 /* 1831 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1832 * fragment that specifies the *reverse* comparison to perform, e.g. 1833 * for "if-le" you would use "gt". 1834 * 1835 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1836 */ 1837 /* if-cmp vAA, +BBBB */ 1838 mov r0, rINST, lsr #8 @ r0<- AA 1839 GET_VREG(r2, r0) @ r2<- vAA 1840 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1841 cmp r2, #0 @ compare (vA, 0) 1842 ble 1f @ branch to 1 if comparison failed 1843 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1844 movs r9, r9, asl #1 @ convert to bytes, check sign 1845 bmi common_backwardBranch @ backward branch, do periodic checks 18461: 1847#if defined(WITH_JIT) 1848 GET_JIT_PROF_TABLE(r0) 1849 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1850 cmp r0,#0 1851 bne common_updateProfile 1852 GET_INST_OPCODE(ip) @ extract opcode from rINST 1853 GOTO_OPCODE(ip) @ jump to next instruction 1854#else 1855 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1856 GET_INST_OPCODE(ip) @ extract opcode from rINST 1857 GOTO_OPCODE(ip) @ jump to next instruction 1858#endif 1859 1860 1861/* ------------------------------ */ 1862 .balign 64 1863.L_OP_IF_LEZ: /* 0x3d */ 1864/* File: armv5te/OP_IF_LEZ.S */ 1865/* File: armv5te/zcmp.S */ 1866 /* 1867 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1868 * fragment that specifies the *reverse* comparison to perform, e.g. 1869 * for "if-le" you would use "gt". 1870 * 1871 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1872 */ 1873 /* if-cmp vAA, +BBBB */ 1874 mov r0, rINST, lsr #8 @ r0<- AA 1875 GET_VREG(r2, r0) @ r2<- vAA 1876 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1877 cmp r2, #0 @ compare (vA, 0) 1878 bgt 1f @ branch to 1 if comparison failed 1879 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1880 movs r9, r9, asl #1 @ convert to bytes, check sign 1881 bmi common_backwardBranch @ backward branch, do periodic checks 18821: 1883#if defined(WITH_JIT) 1884 GET_JIT_PROF_TABLE(r0) 1885 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1886 cmp r0,#0 1887 bne common_updateProfile 1888 GET_INST_OPCODE(ip) @ extract opcode from rINST 1889 GOTO_OPCODE(ip) @ jump to next instruction 1890#else 1891 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1892 GET_INST_OPCODE(ip) @ extract opcode from rINST 1893 GOTO_OPCODE(ip) @ jump to next instruction 1894#endif 1895 1896 1897/* ------------------------------ */ 1898 .balign 64 1899.L_OP_UNUSED_3E: /* 0x3e */ 1900/* File: armv5te/OP_UNUSED_3E.S */ 1901/* File: armv5te/unused.S */ 1902 bl common_abort 1903 1904 1905/* ------------------------------ */ 1906 .balign 64 1907.L_OP_UNUSED_3F: /* 0x3f */ 1908/* File: armv5te/OP_UNUSED_3F.S */ 1909/* File: armv5te/unused.S */ 1910 bl common_abort 1911 1912 1913/* ------------------------------ */ 1914 .balign 64 1915.L_OP_UNUSED_40: /* 0x40 */ 1916/* File: armv5te/OP_UNUSED_40.S */ 1917/* File: armv5te/unused.S */ 1918 bl common_abort 1919 1920 1921/* ------------------------------ */ 1922 .balign 64 1923.L_OP_UNUSED_41: /* 0x41 */ 1924/* File: armv5te/OP_UNUSED_41.S */ 1925/* File: armv5te/unused.S */ 1926 bl common_abort 1927 1928 1929/* ------------------------------ */ 1930 .balign 64 1931.L_OP_UNUSED_42: /* 0x42 */ 1932/* File: armv5te/OP_UNUSED_42.S */ 1933/* File: armv5te/unused.S */ 1934 bl common_abort 1935 1936 1937/* ------------------------------ */ 1938 .balign 64 1939.L_OP_UNUSED_43: /* 0x43 */ 1940/* File: armv5te/OP_UNUSED_43.S */ 1941/* File: armv5te/unused.S */ 1942 bl common_abort 1943 1944 1945/* ------------------------------ */ 1946 .balign 64 1947.L_OP_AGET: /* 0x44 */ 1948/* File: armv5te/OP_AGET.S */ 1949 /* 1950 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1951 * 1952 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1953 * instructions. We use a pair of FETCH_Bs instead. 1954 * 1955 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1956 */ 1957 /* op vAA, vBB, vCC */ 1958 FETCH_B(r2, 1, 0) @ r2<- BB 1959 mov r9, rINST, lsr #8 @ r9<- AA 1960 FETCH_B(r3, 1, 1) @ r3<- CC 1961 GET_VREG(r0, r2) @ r0<- vBB (array object) 1962 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1963 cmp r0, #0 @ null array object? 1964 beq common_errNullObject @ yes, bail 1965 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1966 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1967 cmp r1, r3 @ compare unsigned index, length 1968 bcs common_errArrayIndex @ index >= length, bail 1969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1970 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 1971 GET_INST_OPCODE(ip) @ extract opcode from rINST 1972 SET_VREG(r2, r9) @ vAA<- r2 1973 GOTO_OPCODE(ip) @ jump to next instruction 1974 1975/* ------------------------------ */ 1976 .balign 64 1977.L_OP_AGET_WIDE: /* 0x45 */ 1978/* File: armv5te/OP_AGET_WIDE.S */ 1979 /* 1980 * Array get, 64 bits. vAA <- vBB[vCC]. 1981 * 1982 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 1983 */ 1984 /* aget-wide vAA, vBB, vCC */ 1985 FETCH(r0, 1) @ r0<- CCBB 1986 mov r9, rINST, lsr #8 @ r9<- AA 1987 and r2, r0, #255 @ r2<- BB 1988 mov r3, r0, lsr #8 @ r3<- CC 1989 GET_VREG(r0, r2) @ r0<- vBB (array object) 1990 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1991 cmp r0, #0 @ null array object? 1992 beq common_errNullObject @ yes, bail 1993 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1994 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 1995 cmp r1, r3 @ compare unsigned index, length 1996 bcc .LOP_AGET_WIDE_finish @ okay, continue below 1997 b common_errArrayIndex @ index >= length, bail 1998 @ May want to swap the order of these two branches depending on how the 1999 @ branch prediction (if any) handles conditional forward branches vs. 2000 @ unconditional forward branches. 2001 2002/* ------------------------------ */ 2003 .balign 64 2004.L_OP_AGET_OBJECT: /* 0x46 */ 2005/* File: armv5te/OP_AGET_OBJECT.S */ 2006/* File: armv5te/OP_AGET.S */ 2007 /* 2008 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2009 * 2010 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2011 * instructions. We use a pair of FETCH_Bs instead. 2012 * 2013 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2014 */ 2015 /* op vAA, vBB, vCC */ 2016 FETCH_B(r2, 1, 0) @ r2<- BB 2017 mov r9, rINST, lsr #8 @ r9<- AA 2018 FETCH_B(r3, 1, 1) @ r3<- CC 2019 GET_VREG(r0, r2) @ r0<- vBB (array object) 2020 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2021 cmp r0, #0 @ null array object? 2022 beq common_errNullObject @ yes, bail 2023 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2024 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2025 cmp r1, r3 @ compare unsigned index, length 2026 bcs common_errArrayIndex @ index >= length, bail 2027 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2028 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2029 GET_INST_OPCODE(ip) @ extract opcode from rINST 2030 SET_VREG(r2, r9) @ vAA<- r2 2031 GOTO_OPCODE(ip) @ jump to next instruction 2032 2033 2034/* ------------------------------ */ 2035 .balign 64 2036.L_OP_AGET_BOOLEAN: /* 0x47 */ 2037/* File: armv5te/OP_AGET_BOOLEAN.S */ 2038/* File: armv5te/OP_AGET.S */ 2039 /* 2040 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2041 * 2042 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2043 * instructions. We use a pair of FETCH_Bs instead. 2044 * 2045 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2046 */ 2047 /* op vAA, vBB, vCC */ 2048 FETCH_B(r2, 1, 0) @ r2<- BB 2049 mov r9, rINST, lsr #8 @ r9<- AA 2050 FETCH_B(r3, 1, 1) @ r3<- CC 2051 GET_VREG(r0, r2) @ r0<- vBB (array object) 2052 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2053 cmp r0, #0 @ null array object? 2054 beq common_errNullObject @ yes, bail 2055 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2056 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2057 cmp r1, r3 @ compare unsigned index, length 2058 bcs common_errArrayIndex @ index >= length, bail 2059 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2060 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2061 GET_INST_OPCODE(ip) @ extract opcode from rINST 2062 SET_VREG(r2, r9) @ vAA<- r2 2063 GOTO_OPCODE(ip) @ jump to next instruction 2064 2065 2066/* ------------------------------ */ 2067 .balign 64 2068.L_OP_AGET_BYTE: /* 0x48 */ 2069/* File: armv5te/OP_AGET_BYTE.S */ 2070/* File: armv5te/OP_AGET.S */ 2071 /* 2072 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2073 * 2074 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2075 * instructions. We use a pair of FETCH_Bs instead. 2076 * 2077 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2078 */ 2079 /* op vAA, vBB, vCC */ 2080 FETCH_B(r2, 1, 0) @ r2<- BB 2081 mov r9, rINST, lsr #8 @ r9<- AA 2082 FETCH_B(r3, 1, 1) @ r3<- CC 2083 GET_VREG(r0, r2) @ r0<- vBB (array object) 2084 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2085 cmp r0, #0 @ null array object? 2086 beq common_errNullObject @ yes, bail 2087 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2088 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2089 cmp r1, r3 @ compare unsigned index, length 2090 bcs common_errArrayIndex @ index >= length, bail 2091 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2092 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2093 GET_INST_OPCODE(ip) @ extract opcode from rINST 2094 SET_VREG(r2, r9) @ vAA<- r2 2095 GOTO_OPCODE(ip) @ jump to next instruction 2096 2097 2098/* ------------------------------ */ 2099 .balign 64 2100.L_OP_AGET_CHAR: /* 0x49 */ 2101/* File: armv5te/OP_AGET_CHAR.S */ 2102/* File: armv5te/OP_AGET.S */ 2103 /* 2104 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2105 * 2106 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2107 * instructions. We use a pair of FETCH_Bs instead. 2108 * 2109 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2110 */ 2111 /* op vAA, vBB, vCC */ 2112 FETCH_B(r2, 1, 0) @ r2<- BB 2113 mov r9, rINST, lsr #8 @ r9<- AA 2114 FETCH_B(r3, 1, 1) @ r3<- CC 2115 GET_VREG(r0, r2) @ r0<- vBB (array object) 2116 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2117 cmp r0, #0 @ null array object? 2118 beq common_errNullObject @ yes, bail 2119 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2120 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2121 cmp r1, r3 @ compare unsigned index, length 2122 bcs common_errArrayIndex @ index >= length, bail 2123 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2124 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2125 GET_INST_OPCODE(ip) @ extract opcode from rINST 2126 SET_VREG(r2, r9) @ vAA<- r2 2127 GOTO_OPCODE(ip) @ jump to next instruction 2128 2129 2130/* ------------------------------ */ 2131 .balign 64 2132.L_OP_AGET_SHORT: /* 0x4a */ 2133/* File: armv5te/OP_AGET_SHORT.S */ 2134/* File: armv5te/OP_AGET.S */ 2135 /* 2136 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2137 * 2138 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2139 * instructions. We use a pair of FETCH_Bs instead. 2140 * 2141 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2142 */ 2143 /* op vAA, vBB, vCC */ 2144 FETCH_B(r2, 1, 0) @ r2<- BB 2145 mov r9, rINST, lsr #8 @ r9<- AA 2146 FETCH_B(r3, 1, 1) @ r3<- CC 2147 GET_VREG(r0, r2) @ r0<- vBB (array object) 2148 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2149 cmp r0, #0 @ null array object? 2150 beq common_errNullObject @ yes, bail 2151 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2152 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2153 cmp r1, r3 @ compare unsigned index, length 2154 bcs common_errArrayIndex @ index >= length, bail 2155 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2156 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2157 GET_INST_OPCODE(ip) @ extract opcode from rINST 2158 SET_VREG(r2, r9) @ vAA<- r2 2159 GOTO_OPCODE(ip) @ jump to next instruction 2160 2161 2162/* ------------------------------ */ 2163 .balign 64 2164.L_OP_APUT: /* 0x4b */ 2165/* File: armv5te/OP_APUT.S */ 2166 /* 2167 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2168 * 2169 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2170 * instructions. We use a pair of FETCH_Bs instead. 2171 * 2172 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2173 */ 2174 /* op vAA, vBB, vCC */ 2175 FETCH_B(r2, 1, 0) @ r2<- BB 2176 mov r9, rINST, lsr #8 @ r9<- AA 2177 FETCH_B(r3, 1, 1) @ r3<- CC 2178 GET_VREG(r0, r2) @ r0<- vBB (array object) 2179 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2180 cmp r0, #0 @ null array object? 2181 beq common_errNullObject @ yes, bail 2182 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2183 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2184 cmp r1, r3 @ compare unsigned index, length 2185 bcs common_errArrayIndex @ index >= length, bail 2186 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2187 GET_VREG(r2, r9) @ r2<- vAA 2188 GET_INST_OPCODE(ip) @ extract opcode from rINST 2189 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2190 GOTO_OPCODE(ip) @ jump to next instruction 2191 2192/* ------------------------------ */ 2193 .balign 64 2194.L_OP_APUT_WIDE: /* 0x4c */ 2195/* File: armv5te/OP_APUT_WIDE.S */ 2196 /* 2197 * Array put, 64 bits. vBB[vCC] <- vAA. 2198 * 2199 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2200 */ 2201 /* aput-wide vAA, vBB, vCC */ 2202 FETCH(r0, 1) @ r0<- CCBB 2203 mov r9, rINST, lsr #8 @ r9<- AA 2204 and r2, r0, #255 @ r2<- BB 2205 mov r3, r0, lsr #8 @ r3<- CC 2206 GET_VREG(r0, r2) @ r0<- vBB (array object) 2207 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2208 cmp r0, #0 @ null array object? 2209 beq common_errNullObject @ yes, bail 2210 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2211 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2212 cmp r1, r3 @ compare unsigned index, length 2213 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2214 bcc .LOP_APUT_WIDE_finish @ okay, continue below 2215 b common_errArrayIndex @ index >= length, bail 2216 @ May want to swap the order of these two branches depending on how the 2217 @ branch prediction (if any) handles conditional forward branches vs. 2218 @ unconditional forward branches. 2219 2220/* ------------------------------ */ 2221 .balign 64 2222.L_OP_APUT_OBJECT: /* 0x4d */ 2223/* File: armv5te/OP_APUT_OBJECT.S */ 2224 /* 2225 * Store an object into an array. vBB[vCC] <- vAA. 2226 */ 2227 /* op vAA, vBB, vCC */ 2228 FETCH(r0, 1) @ r0<- CCBB 2229 mov r9, rINST, lsr #8 @ r9<- AA 2230 and r2, r0, #255 @ r2<- BB 2231 mov r3, r0, lsr #8 @ r3<- CC 2232 GET_VREG(rINST, r2) @ rINST<- vBB (array object) 2233 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2234 cmp rINST, #0 @ null array object? 2235 GET_VREG(r9, r9) @ r9<- vAA 2236 beq common_errNullObject @ yes, bail 2237 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length 2238 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width 2239 cmp r1, r3 @ compare unsigned index, length 2240 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2241 b common_errArrayIndex @ index >= length, bail 2242 2243 2244/* ------------------------------ */ 2245 .balign 64 2246.L_OP_APUT_BOOLEAN: /* 0x4e */ 2247/* File: armv5te/OP_APUT_BOOLEAN.S */ 2248/* File: armv5te/OP_APUT.S */ 2249 /* 2250 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2251 * 2252 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2253 * instructions. We use a pair of FETCH_Bs instead. 2254 * 2255 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2256 */ 2257 /* op vAA, vBB, vCC */ 2258 FETCH_B(r2, 1, 0) @ r2<- BB 2259 mov r9, rINST, lsr #8 @ r9<- AA 2260 FETCH_B(r3, 1, 1) @ r3<- CC 2261 GET_VREG(r0, r2) @ r0<- vBB (array object) 2262 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2263 cmp r0, #0 @ null array object? 2264 beq common_errNullObject @ yes, bail 2265 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2266 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2267 cmp r1, r3 @ compare unsigned index, length 2268 bcs common_errArrayIndex @ index >= length, bail 2269 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2270 GET_VREG(r2, r9) @ r2<- vAA 2271 GET_INST_OPCODE(ip) @ extract opcode from rINST 2272 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2273 GOTO_OPCODE(ip) @ jump to next instruction 2274 2275 2276/* ------------------------------ */ 2277 .balign 64 2278.L_OP_APUT_BYTE: /* 0x4f */ 2279/* File: armv5te/OP_APUT_BYTE.S */ 2280/* File: armv5te/OP_APUT.S */ 2281 /* 2282 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2283 * 2284 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2285 * instructions. We use a pair of FETCH_Bs instead. 2286 * 2287 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2288 */ 2289 /* op vAA, vBB, vCC */ 2290 FETCH_B(r2, 1, 0) @ r2<- BB 2291 mov r9, rINST, lsr #8 @ r9<- AA 2292 FETCH_B(r3, 1, 1) @ r3<- CC 2293 GET_VREG(r0, r2) @ r0<- vBB (array object) 2294 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2295 cmp r0, #0 @ null array object? 2296 beq common_errNullObject @ yes, bail 2297 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2298 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2299 cmp r1, r3 @ compare unsigned index, length 2300 bcs common_errArrayIndex @ index >= length, bail 2301 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2302 GET_VREG(r2, r9) @ r2<- vAA 2303 GET_INST_OPCODE(ip) @ extract opcode from rINST 2304 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2305 GOTO_OPCODE(ip) @ jump to next instruction 2306 2307 2308/* ------------------------------ */ 2309 .balign 64 2310.L_OP_APUT_CHAR: /* 0x50 */ 2311/* File: armv5te/OP_APUT_CHAR.S */ 2312/* File: armv5te/OP_APUT.S */ 2313 /* 2314 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2315 * 2316 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2317 * instructions. We use a pair of FETCH_Bs instead. 2318 * 2319 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2320 */ 2321 /* op vAA, vBB, vCC */ 2322 FETCH_B(r2, 1, 0) @ r2<- BB 2323 mov r9, rINST, lsr #8 @ r9<- AA 2324 FETCH_B(r3, 1, 1) @ r3<- CC 2325 GET_VREG(r0, r2) @ r0<- vBB (array object) 2326 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2327 cmp r0, #0 @ null array object? 2328 beq common_errNullObject @ yes, bail 2329 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2330 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2331 cmp r1, r3 @ compare unsigned index, length 2332 bcs common_errArrayIndex @ index >= length, bail 2333 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2334 GET_VREG(r2, r9) @ r2<- vAA 2335 GET_INST_OPCODE(ip) @ extract opcode from rINST 2336 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2337 GOTO_OPCODE(ip) @ jump to next instruction 2338 2339 2340/* ------------------------------ */ 2341 .balign 64 2342.L_OP_APUT_SHORT: /* 0x51 */ 2343/* File: armv5te/OP_APUT_SHORT.S */ 2344/* File: armv5te/OP_APUT.S */ 2345 /* 2346 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2347 * 2348 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2349 * instructions. We use a pair of FETCH_Bs instead. 2350 * 2351 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2352 */ 2353 /* op vAA, vBB, vCC */ 2354 FETCH_B(r2, 1, 0) @ r2<- BB 2355 mov r9, rINST, lsr #8 @ r9<- AA 2356 FETCH_B(r3, 1, 1) @ r3<- CC 2357 GET_VREG(r0, r2) @ r0<- vBB (array object) 2358 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2359 cmp r0, #0 @ null array object? 2360 beq common_errNullObject @ yes, bail 2361 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2362 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2363 cmp r1, r3 @ compare unsigned index, length 2364 bcs common_errArrayIndex @ index >= length, bail 2365 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2366 GET_VREG(r2, r9) @ r2<- vAA 2367 GET_INST_OPCODE(ip) @ extract opcode from rINST 2368 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2369 GOTO_OPCODE(ip) @ jump to next instruction 2370 2371 2372/* ------------------------------ */ 2373 .balign 64 2374.L_OP_IGET: /* 0x52 */ 2375/* File: armv5te/OP_IGET.S */ 2376 /* 2377 * General 32-bit instance field get. 2378 * 2379 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2380 */ 2381 /* op vA, vB, field@CCCC */ 2382 mov r0, rINST, lsr #12 @ r0<- B 2383 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2384 FETCH(r1, 1) @ r1<- field ref CCCC 2385 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2386 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2387 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2388 cmp r0, #0 @ is resolved entry null? 2389 bne .LOP_IGET_finish @ no, already resolved 23908: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2391 EXPORT_PC() @ resolve() could throw 2392 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2393 bl dvmResolveInstField @ r0<- resolved InstField ptr 2394 cmp r0, #0 2395 bne .LOP_IGET_finish 2396 b common_exceptionThrown 2397 2398/* ------------------------------ */ 2399 .balign 64 2400.L_OP_IGET_WIDE: /* 0x53 */ 2401/* File: armv5te/OP_IGET_WIDE.S */ 2402 /* 2403 * Wide 32-bit instance field get. 2404 */ 2405 /* iget-wide vA, vB, field@CCCC */ 2406 mov r0, rINST, lsr #12 @ r0<- B 2407 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2408 FETCH(r1, 1) @ r1<- field ref CCCC 2409 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2410 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2411 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2412 cmp r0, #0 @ is resolved entry null? 2413 bne .LOP_IGET_WIDE_finish @ no, already resolved 24148: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2415 EXPORT_PC() @ resolve() could throw 2416 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2417 bl dvmResolveInstField @ r0<- resolved InstField ptr 2418 cmp r0, #0 2419 bne .LOP_IGET_WIDE_finish 2420 b common_exceptionThrown 2421 2422/* ------------------------------ */ 2423 .balign 64 2424.L_OP_IGET_OBJECT: /* 0x54 */ 2425/* File: armv5te/OP_IGET_OBJECT.S */ 2426/* File: armv5te/OP_IGET.S */ 2427 /* 2428 * General 32-bit instance field get. 2429 * 2430 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2431 */ 2432 /* op vA, vB, field@CCCC */ 2433 mov r0, rINST, lsr #12 @ r0<- B 2434 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2435 FETCH(r1, 1) @ r1<- field ref CCCC 2436 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2437 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2438 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2439 cmp r0, #0 @ is resolved entry null? 2440 bne .LOP_IGET_OBJECT_finish @ no, already resolved 24418: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2442 EXPORT_PC() @ resolve() could throw 2443 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2444 bl dvmResolveInstField @ r0<- resolved InstField ptr 2445 cmp r0, #0 2446 bne .LOP_IGET_OBJECT_finish 2447 b common_exceptionThrown 2448 2449 2450/* ------------------------------ */ 2451 .balign 64 2452.L_OP_IGET_BOOLEAN: /* 0x55 */ 2453/* File: armv5te/OP_IGET_BOOLEAN.S */ 2454@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2455/* File: armv5te/OP_IGET.S */ 2456 /* 2457 * General 32-bit instance field get. 2458 * 2459 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2460 */ 2461 /* op vA, vB, field@CCCC */ 2462 mov r0, rINST, lsr #12 @ r0<- B 2463 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2464 FETCH(r1, 1) @ r1<- field ref CCCC 2465 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2466 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2467 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2468 cmp r0, #0 @ is resolved entry null? 2469 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 24708: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2471 EXPORT_PC() @ resolve() could throw 2472 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2473 bl dvmResolveInstField @ r0<- resolved InstField ptr 2474 cmp r0, #0 2475 bne .LOP_IGET_BOOLEAN_finish 2476 b common_exceptionThrown 2477 2478 2479/* ------------------------------ */ 2480 .balign 64 2481.L_OP_IGET_BYTE: /* 0x56 */ 2482/* File: armv5te/OP_IGET_BYTE.S */ 2483@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2484/* File: armv5te/OP_IGET.S */ 2485 /* 2486 * General 32-bit instance field get. 2487 * 2488 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2489 */ 2490 /* op vA, vB, field@CCCC */ 2491 mov r0, rINST, lsr #12 @ r0<- B 2492 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2493 FETCH(r1, 1) @ r1<- field ref CCCC 2494 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2495 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2496 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2497 cmp r0, #0 @ is resolved entry null? 2498 bne .LOP_IGET_BYTE_finish @ no, already resolved 24998: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2500 EXPORT_PC() @ resolve() could throw 2501 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2502 bl dvmResolveInstField @ r0<- resolved InstField ptr 2503 cmp r0, #0 2504 bne .LOP_IGET_BYTE_finish 2505 b common_exceptionThrown 2506 2507 2508/* ------------------------------ */ 2509 .balign 64 2510.L_OP_IGET_CHAR: /* 0x57 */ 2511/* File: armv5te/OP_IGET_CHAR.S */ 2512@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2513/* File: armv5te/OP_IGET.S */ 2514 /* 2515 * General 32-bit instance field get. 2516 * 2517 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2518 */ 2519 /* op vA, vB, field@CCCC */ 2520 mov r0, rINST, lsr #12 @ r0<- B 2521 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2522 FETCH(r1, 1) @ r1<- field ref CCCC 2523 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2524 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2525 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2526 cmp r0, #0 @ is resolved entry null? 2527 bne .LOP_IGET_CHAR_finish @ no, already resolved 25288: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2529 EXPORT_PC() @ resolve() could throw 2530 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2531 bl dvmResolveInstField @ r0<- resolved InstField ptr 2532 cmp r0, #0 2533 bne .LOP_IGET_CHAR_finish 2534 b common_exceptionThrown 2535 2536 2537/* ------------------------------ */ 2538 .balign 64 2539.L_OP_IGET_SHORT: /* 0x58 */ 2540/* File: armv5te/OP_IGET_SHORT.S */ 2541@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2542/* File: armv5te/OP_IGET.S */ 2543 /* 2544 * General 32-bit instance field get. 2545 * 2546 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2547 */ 2548 /* op vA, vB, field@CCCC */ 2549 mov r0, rINST, lsr #12 @ r0<- B 2550 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2551 FETCH(r1, 1) @ r1<- field ref CCCC 2552 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2553 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2554 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2555 cmp r0, #0 @ is resolved entry null? 2556 bne .LOP_IGET_SHORT_finish @ no, already resolved 25578: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2558 EXPORT_PC() @ resolve() could throw 2559 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2560 bl dvmResolveInstField @ r0<- resolved InstField ptr 2561 cmp r0, #0 2562 bne .LOP_IGET_SHORT_finish 2563 b common_exceptionThrown 2564 2565 2566/* ------------------------------ */ 2567 .balign 64 2568.L_OP_IPUT: /* 0x59 */ 2569/* File: armv5te/OP_IPUT.S */ 2570 /* 2571 * General 32-bit instance field put. 2572 * 2573 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2574 */ 2575 /* op vA, vB, field@CCCC */ 2576 mov r0, rINST, lsr #12 @ r0<- B 2577 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2578 FETCH(r1, 1) @ r1<- field ref CCCC 2579 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2580 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2581 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2582 cmp r0, #0 @ is resolved entry null? 2583 bne .LOP_IPUT_finish @ no, already resolved 25848: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2585 EXPORT_PC() @ resolve() could throw 2586 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2587 bl dvmResolveInstField @ r0<- resolved InstField ptr 2588 cmp r0, #0 @ success? 2589 bne .LOP_IPUT_finish @ yes, finish up 2590 b common_exceptionThrown 2591 2592/* ------------------------------ */ 2593 .balign 64 2594.L_OP_IPUT_WIDE: /* 0x5a */ 2595/* File: armv5te/OP_IPUT_WIDE.S */ 2596 /* iput-wide vA, vB, field@CCCC */ 2597 mov r0, rINST, lsr #12 @ r0<- B 2598 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2599 FETCH(r1, 1) @ r1<- field ref CCCC 2600 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2601 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2602 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2603 cmp r0, #0 @ is resolved entry null? 2604 bne .LOP_IPUT_WIDE_finish @ no, already resolved 26058: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2606 EXPORT_PC() @ resolve() could throw 2607 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2608 bl dvmResolveInstField @ r0<- resolved InstField ptr 2609 cmp r0, #0 @ success? 2610 bne .LOP_IPUT_WIDE_finish @ yes, finish up 2611 b common_exceptionThrown 2612 2613/* ------------------------------ */ 2614 .balign 64 2615.L_OP_IPUT_OBJECT: /* 0x5b */ 2616/* File: armv5te/OP_IPUT_OBJECT.S */ 2617 /* 2618 * 32-bit instance field put. 2619 * 2620 * for: iput-object, iput-object-volatile 2621 */ 2622 /* op vA, vB, field@CCCC */ 2623 mov r0, rINST, lsr #12 @ r0<- B 2624 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2625 FETCH(r1, 1) @ r1<- field ref CCCC 2626 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2627 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2628 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2629 cmp r0, #0 @ is resolved entry null? 2630 bne .LOP_IPUT_OBJECT_finish @ no, already resolved 26318: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2632 EXPORT_PC() @ resolve() could throw 2633 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2634 bl dvmResolveInstField @ r0<- resolved InstField ptr 2635 cmp r0, #0 @ success? 2636 bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2637 b common_exceptionThrown 2638 2639/* ------------------------------ */ 2640 .balign 64 2641.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2642/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2643@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2644/* File: armv5te/OP_IPUT.S */ 2645 /* 2646 * General 32-bit instance field put. 2647 * 2648 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2649 */ 2650 /* op vA, vB, field@CCCC */ 2651 mov r0, rINST, lsr #12 @ r0<- B 2652 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2653 FETCH(r1, 1) @ r1<- field ref CCCC 2654 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2655 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2656 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2657 cmp r0, #0 @ is resolved entry null? 2658 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 26598: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2660 EXPORT_PC() @ resolve() could throw 2661 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2662 bl dvmResolveInstField @ r0<- resolved InstField ptr 2663 cmp r0, #0 @ success? 2664 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2665 b common_exceptionThrown 2666 2667 2668/* ------------------------------ */ 2669 .balign 64 2670.L_OP_IPUT_BYTE: /* 0x5d */ 2671/* File: armv5te/OP_IPUT_BYTE.S */ 2672@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2673/* File: armv5te/OP_IPUT.S */ 2674 /* 2675 * General 32-bit instance field put. 2676 * 2677 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2678 */ 2679 /* op vA, vB, field@CCCC */ 2680 mov r0, rINST, lsr #12 @ r0<- B 2681 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2682 FETCH(r1, 1) @ r1<- field ref CCCC 2683 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2684 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2685 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2686 cmp r0, #0 @ is resolved entry null? 2687 bne .LOP_IPUT_BYTE_finish @ no, already resolved 26888: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2689 EXPORT_PC() @ resolve() could throw 2690 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2691 bl dvmResolveInstField @ r0<- resolved InstField ptr 2692 cmp r0, #0 @ success? 2693 bne .LOP_IPUT_BYTE_finish @ yes, finish up 2694 b common_exceptionThrown 2695 2696 2697/* ------------------------------ */ 2698 .balign 64 2699.L_OP_IPUT_CHAR: /* 0x5e */ 2700/* File: armv5te/OP_IPUT_CHAR.S */ 2701@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2702/* File: armv5te/OP_IPUT.S */ 2703 /* 2704 * General 32-bit instance field put. 2705 * 2706 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2707 */ 2708 /* op vA, vB, field@CCCC */ 2709 mov r0, rINST, lsr #12 @ r0<- B 2710 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2711 FETCH(r1, 1) @ r1<- field ref CCCC 2712 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2713 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2714 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2715 cmp r0, #0 @ is resolved entry null? 2716 bne .LOP_IPUT_CHAR_finish @ no, already resolved 27178: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2718 EXPORT_PC() @ resolve() could throw 2719 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2720 bl dvmResolveInstField @ r0<- resolved InstField ptr 2721 cmp r0, #0 @ success? 2722 bne .LOP_IPUT_CHAR_finish @ yes, finish up 2723 b common_exceptionThrown 2724 2725 2726/* ------------------------------ */ 2727 .balign 64 2728.L_OP_IPUT_SHORT: /* 0x5f */ 2729/* File: armv5te/OP_IPUT_SHORT.S */ 2730@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2731/* File: armv5te/OP_IPUT.S */ 2732 /* 2733 * General 32-bit instance field put. 2734 * 2735 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2736 */ 2737 /* op vA, vB, field@CCCC */ 2738 mov r0, rINST, lsr #12 @ r0<- B 2739 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2740 FETCH(r1, 1) @ r1<- field ref CCCC 2741 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2742 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2743 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2744 cmp r0, #0 @ is resolved entry null? 2745 bne .LOP_IPUT_SHORT_finish @ no, already resolved 27468: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2747 EXPORT_PC() @ resolve() could throw 2748 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2749 bl dvmResolveInstField @ r0<- resolved InstField ptr 2750 cmp r0, #0 @ success? 2751 bne .LOP_IPUT_SHORT_finish @ yes, finish up 2752 b common_exceptionThrown 2753 2754 2755/* ------------------------------ */ 2756 .balign 64 2757.L_OP_SGET: /* 0x60 */ 2758/* File: armv5te/OP_SGET.S */ 2759 /* 2760 * General 32-bit SGET handler. 2761 * 2762 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2763 */ 2764 /* op vAA, field@BBBB */ 2765 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2766 FETCH(r1, 1) @ r1<- field ref BBBB 2767 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2768 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2769 cmp r0, #0 @ is resolved entry null? 2770 beq .LOP_SGET_resolve @ yes, do resolve 2771.LOP_SGET_finish: @ field ptr in r0 2772 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2773 @ no-op @ acquiring load 2774 mov r2, rINST, lsr #8 @ r2<- AA 2775 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2776 SET_VREG(r1, r2) @ fp[AA]<- r1 2777 GET_INST_OPCODE(ip) @ extract opcode from rINST 2778 GOTO_OPCODE(ip) @ jump to next instruction 2779 2780/* ------------------------------ */ 2781 .balign 64 2782.L_OP_SGET_WIDE: /* 0x61 */ 2783/* File: armv5te/OP_SGET_WIDE.S */ 2784 /* 2785 * 64-bit SGET handler. 2786 */ 2787 /* sget-wide vAA, field@BBBB */ 2788 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2789 FETCH(r1, 1) @ r1<- field ref BBBB 2790 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2791 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2792 cmp r0, #0 @ is resolved entry null? 2793 beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2794.LOP_SGET_WIDE_finish: 2795 mov r9, rINST, lsr #8 @ r9<- AA 2796 .if 0 2797 add r0, r0, #offStaticField_value @ r0<- pointer to data 2798 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2799 .else 2800 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2801 .endif 2802 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2803 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2804 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2805 GET_INST_OPCODE(ip) @ extract opcode from rINST 2806 GOTO_OPCODE(ip) @ jump to next instruction 2807 2808/* ------------------------------ */ 2809 .balign 64 2810.L_OP_SGET_OBJECT: /* 0x62 */ 2811/* File: armv5te/OP_SGET_OBJECT.S */ 2812/* File: armv5te/OP_SGET.S */ 2813 /* 2814 * General 32-bit SGET handler. 2815 * 2816 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2817 */ 2818 /* op vAA, field@BBBB */ 2819 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2820 FETCH(r1, 1) @ r1<- field ref BBBB 2821 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2822 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2823 cmp r0, #0 @ is resolved entry null? 2824 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2825.LOP_SGET_OBJECT_finish: @ field ptr in r0 2826 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2827 @ no-op @ acquiring load 2828 mov r2, rINST, lsr #8 @ r2<- AA 2829 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2830 SET_VREG(r1, r2) @ fp[AA]<- r1 2831 GET_INST_OPCODE(ip) @ extract opcode from rINST 2832 GOTO_OPCODE(ip) @ jump to next instruction 2833 2834 2835/* ------------------------------ */ 2836 .balign 64 2837.L_OP_SGET_BOOLEAN: /* 0x63 */ 2838/* File: armv5te/OP_SGET_BOOLEAN.S */ 2839/* File: armv5te/OP_SGET.S */ 2840 /* 2841 * General 32-bit SGET handler. 2842 * 2843 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2844 */ 2845 /* op vAA, field@BBBB */ 2846 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2847 FETCH(r1, 1) @ r1<- field ref BBBB 2848 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2849 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2850 cmp r0, #0 @ is resolved entry null? 2851 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2852.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2853 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2854 @ no-op @ acquiring load 2855 mov r2, rINST, lsr #8 @ r2<- AA 2856 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2857 SET_VREG(r1, r2) @ fp[AA]<- r1 2858 GET_INST_OPCODE(ip) @ extract opcode from rINST 2859 GOTO_OPCODE(ip) @ jump to next instruction 2860 2861 2862/* ------------------------------ */ 2863 .balign 64 2864.L_OP_SGET_BYTE: /* 0x64 */ 2865/* File: armv5te/OP_SGET_BYTE.S */ 2866/* File: armv5te/OP_SGET.S */ 2867 /* 2868 * General 32-bit SGET handler. 2869 * 2870 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2871 */ 2872 /* op vAA, field@BBBB */ 2873 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2874 FETCH(r1, 1) @ r1<- field ref BBBB 2875 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2876 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2877 cmp r0, #0 @ is resolved entry null? 2878 beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2879.LOP_SGET_BYTE_finish: @ field ptr in r0 2880 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2881 @ no-op @ acquiring load 2882 mov r2, rINST, lsr #8 @ r2<- AA 2883 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2884 SET_VREG(r1, r2) @ fp[AA]<- r1 2885 GET_INST_OPCODE(ip) @ extract opcode from rINST 2886 GOTO_OPCODE(ip) @ jump to next instruction 2887 2888 2889/* ------------------------------ */ 2890 .balign 64 2891.L_OP_SGET_CHAR: /* 0x65 */ 2892/* File: armv5te/OP_SGET_CHAR.S */ 2893/* File: armv5te/OP_SGET.S */ 2894 /* 2895 * General 32-bit SGET handler. 2896 * 2897 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2898 */ 2899 /* op vAA, field@BBBB */ 2900 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2901 FETCH(r1, 1) @ r1<- field ref BBBB 2902 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2903 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2904 cmp r0, #0 @ is resolved entry null? 2905 beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2906.LOP_SGET_CHAR_finish: @ field ptr in r0 2907 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2908 @ no-op @ acquiring load 2909 mov r2, rINST, lsr #8 @ r2<- AA 2910 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2911 SET_VREG(r1, r2) @ fp[AA]<- r1 2912 GET_INST_OPCODE(ip) @ extract opcode from rINST 2913 GOTO_OPCODE(ip) @ jump to next instruction 2914 2915 2916/* ------------------------------ */ 2917 .balign 64 2918.L_OP_SGET_SHORT: /* 0x66 */ 2919/* File: armv5te/OP_SGET_SHORT.S */ 2920/* File: armv5te/OP_SGET.S */ 2921 /* 2922 * General 32-bit SGET handler. 2923 * 2924 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2925 */ 2926 /* op vAA, field@BBBB */ 2927 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2928 FETCH(r1, 1) @ r1<- field ref BBBB 2929 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2930 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2931 cmp r0, #0 @ is resolved entry null? 2932 beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2933.LOP_SGET_SHORT_finish: @ field ptr in r0 2934 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2935 @ no-op @ acquiring load 2936 mov r2, rINST, lsr #8 @ r2<- AA 2937 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2938 SET_VREG(r1, r2) @ fp[AA]<- r1 2939 GET_INST_OPCODE(ip) @ extract opcode from rINST 2940 GOTO_OPCODE(ip) @ jump to next instruction 2941 2942 2943/* ------------------------------ */ 2944 .balign 64 2945.L_OP_SPUT: /* 0x67 */ 2946/* File: armv5te/OP_SPUT.S */ 2947 /* 2948 * General 32-bit SPUT handler. 2949 * 2950 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2951 */ 2952 /* op vAA, field@BBBB */ 2953 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2954 FETCH(r1, 1) @ r1<- field ref BBBB 2955 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2956 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2957 cmp r0, #0 @ is resolved entry null? 2958 beq .LOP_SPUT_resolve @ yes, do resolve 2959.LOP_SPUT_finish: @ field ptr in r0 2960 mov r2, rINST, lsr #8 @ r2<- AA 2961 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2962 GET_VREG(r1, r2) @ r1<- fp[AA] 2963 GET_INST_OPCODE(ip) @ extract opcode from rINST 2964 @ no-op @ releasing store 2965 str r1, [r0, #offStaticField_value] @ field<- vAA 2966 GOTO_OPCODE(ip) @ jump to next instruction 2967 2968/* ------------------------------ */ 2969 .balign 64 2970.L_OP_SPUT_WIDE: /* 0x68 */ 2971/* File: armv5te/OP_SPUT_WIDE.S */ 2972 /* 2973 * 64-bit SPUT handler. 2974 */ 2975 /* sput-wide vAA, field@BBBB */ 2976 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 2977 FETCH(r1, 1) @ r1<- field ref BBBB 2978 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 2979 mov r9, rINST, lsr #8 @ r9<- AA 2980 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 2981 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2982 cmp r2, #0 @ is resolved entry null? 2983 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 2984.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 2985 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2986 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 2987 GET_INST_OPCODE(r10) @ extract opcode from rINST 2988 .if 0 2989 add r2, r2, #offStaticField_value @ r2<- pointer to data 2990 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 2991 .else 2992 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 2993 .endif 2994 GOTO_OPCODE(r10) @ jump to next instruction 2995 2996/* ------------------------------ */ 2997 .balign 64 2998.L_OP_SPUT_OBJECT: /* 0x69 */ 2999/* File: armv5te/OP_SPUT_OBJECT.S */ 3000 /* 3001 * 32-bit SPUT handler for objects 3002 * 3003 * for: sput-object, sput-object-volatile 3004 */ 3005 /* op vAA, field@BBBB */ 3006 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3007 FETCH(r1, 1) @ r1<- field ref BBBB 3008 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3009 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3010 cmp r0, #0 @ is resolved entry null? 3011 bne .LOP_SPUT_OBJECT_finish @ no, continue 3012 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3013 EXPORT_PC() @ resolve() could throw, so export now 3014 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 3015 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 3016 cmp r0, #0 @ success? 3017 bne .LOP_SPUT_OBJECT_finish @ yes, finish 3018 b common_exceptionThrown @ no, handle exception 3019 3020 3021/* ------------------------------ */ 3022 .balign 64 3023.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3024/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3025/* File: armv5te/OP_SPUT.S */ 3026 /* 3027 * General 32-bit SPUT handler. 3028 * 3029 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3030 */ 3031 /* op vAA, field@BBBB */ 3032 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3033 FETCH(r1, 1) @ r1<- field ref BBBB 3034 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3035 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3036 cmp r0, #0 @ is resolved entry null? 3037 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3038.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3039 mov r2, rINST, lsr #8 @ r2<- AA 3040 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3041 GET_VREG(r1, r2) @ r1<- fp[AA] 3042 GET_INST_OPCODE(ip) @ extract opcode from rINST 3043 @ no-op @ releasing store 3044 str r1, [r0, #offStaticField_value] @ field<- vAA 3045 GOTO_OPCODE(ip) @ jump to next instruction 3046 3047 3048/* ------------------------------ */ 3049 .balign 64 3050.L_OP_SPUT_BYTE: /* 0x6b */ 3051/* File: armv5te/OP_SPUT_BYTE.S */ 3052/* File: armv5te/OP_SPUT.S */ 3053 /* 3054 * General 32-bit SPUT handler. 3055 * 3056 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3057 */ 3058 /* op vAA, field@BBBB */ 3059 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3060 FETCH(r1, 1) @ r1<- field ref BBBB 3061 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3062 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3063 cmp r0, #0 @ is resolved entry null? 3064 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3065.LOP_SPUT_BYTE_finish: @ field ptr in r0 3066 mov r2, rINST, lsr #8 @ r2<- AA 3067 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3068 GET_VREG(r1, r2) @ r1<- fp[AA] 3069 GET_INST_OPCODE(ip) @ extract opcode from rINST 3070 @ no-op @ releasing store 3071 str r1, [r0, #offStaticField_value] @ field<- vAA 3072 GOTO_OPCODE(ip) @ jump to next instruction 3073 3074 3075/* ------------------------------ */ 3076 .balign 64 3077.L_OP_SPUT_CHAR: /* 0x6c */ 3078/* File: armv5te/OP_SPUT_CHAR.S */ 3079/* File: armv5te/OP_SPUT.S */ 3080 /* 3081 * General 32-bit SPUT handler. 3082 * 3083 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3084 */ 3085 /* op vAA, field@BBBB */ 3086 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3087 FETCH(r1, 1) @ r1<- field ref BBBB 3088 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3089 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3090 cmp r0, #0 @ is resolved entry null? 3091 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3092.LOP_SPUT_CHAR_finish: @ field ptr in r0 3093 mov r2, rINST, lsr #8 @ r2<- AA 3094 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3095 GET_VREG(r1, r2) @ r1<- fp[AA] 3096 GET_INST_OPCODE(ip) @ extract opcode from rINST 3097 @ no-op @ releasing store 3098 str r1, [r0, #offStaticField_value] @ field<- vAA 3099 GOTO_OPCODE(ip) @ jump to next instruction 3100 3101 3102/* ------------------------------ */ 3103 .balign 64 3104.L_OP_SPUT_SHORT: /* 0x6d */ 3105/* File: armv5te/OP_SPUT_SHORT.S */ 3106/* File: armv5te/OP_SPUT.S */ 3107 /* 3108 * General 32-bit SPUT handler. 3109 * 3110 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3111 */ 3112 /* op vAA, field@BBBB */ 3113 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3114 FETCH(r1, 1) @ r1<- field ref BBBB 3115 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3116 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3117 cmp r0, #0 @ is resolved entry null? 3118 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3119.LOP_SPUT_SHORT_finish: @ field ptr in r0 3120 mov r2, rINST, lsr #8 @ r2<- AA 3121 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3122 GET_VREG(r1, r2) @ r1<- fp[AA] 3123 GET_INST_OPCODE(ip) @ extract opcode from rINST 3124 @ no-op @ releasing store 3125 str r1, [r0, #offStaticField_value] @ field<- vAA 3126 GOTO_OPCODE(ip) @ jump to next instruction 3127 3128 3129/* ------------------------------ */ 3130 .balign 64 3131.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3132/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3133 /* 3134 * Handle a virtual method call. 3135 * 3136 * for: invoke-virtual, invoke-virtual/range 3137 */ 3138 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3139 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3140 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3141 FETCH(r1, 1) @ r1<- BBBB 3142 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3143 FETCH(r10, 2) @ r10<- GFED or CCCC 3144 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3145 .if (!0) 3146 and r10, r10, #15 @ r10<- D (or stays CCCC) 3147 .endif 3148 cmp r0, #0 @ already resolved? 3149 EXPORT_PC() @ must export for invoke 3150 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3151 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3152 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3153 mov r2, #METHOD_VIRTUAL @ resolver method type 3154 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3155 cmp r0, #0 @ got null? 3156 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3157 b common_exceptionThrown @ yes, handle exception 3158 3159/* ------------------------------ */ 3160 .balign 64 3161.L_OP_INVOKE_SUPER: /* 0x6f */ 3162/* File: armv5te/OP_INVOKE_SUPER.S */ 3163 /* 3164 * Handle a "super" method call. 3165 * 3166 * for: invoke-super, invoke-super/range 3167 */ 3168 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3169 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3170 FETCH(r10, 2) @ r10<- GFED or CCCC 3171 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3172 .if (!0) 3173 and r10, r10, #15 @ r10<- D (or stays CCCC) 3174 .endif 3175 FETCH(r1, 1) @ r1<- BBBB 3176 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3177 GET_VREG(r2, r10) @ r2<- "this" ptr 3178 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3179 cmp r2, #0 @ null "this"? 3180 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3181 beq common_errNullObject @ null "this", throw exception 3182 cmp r0, #0 @ already resolved? 3183 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3184 EXPORT_PC() @ must export for invoke 3185 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3186 b .LOP_INVOKE_SUPER_resolve @ do resolve now 3187 3188/* ------------------------------ */ 3189 .balign 64 3190.L_OP_INVOKE_DIRECT: /* 0x70 */ 3191/* File: armv5te/OP_INVOKE_DIRECT.S */ 3192 /* 3193 * Handle a direct method call. 3194 * 3195 * (We could defer the "is 'this' pointer null" test to the common 3196 * method invocation code, and use a flag to indicate that static 3197 * calls don't count. If we do this as part of copying the arguments 3198 * out we could avoiding loading the first arg twice.) 3199 * 3200 * for: invoke-direct, invoke-direct/range 3201 */ 3202 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3203 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3204 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3205 FETCH(r1, 1) @ r1<- BBBB 3206 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3207 FETCH(r10, 2) @ r10<- GFED or CCCC 3208 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3209 .if (!0) 3210 and r10, r10, #15 @ r10<- D (or stays CCCC) 3211 .endif 3212 cmp r0, #0 @ already resolved? 3213 EXPORT_PC() @ must export for invoke 3214 GET_VREG(r2, r10) @ r2<- "this" ptr 3215 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3216.LOP_INVOKE_DIRECT_finish: 3217 cmp r2, #0 @ null "this" ref? 3218 bne common_invokeMethodNoRange @ no, continue on 3219 b common_errNullObject @ yes, throw exception 3220 3221/* ------------------------------ */ 3222 .balign 64 3223.L_OP_INVOKE_STATIC: /* 0x71 */ 3224/* File: armv5te/OP_INVOKE_STATIC.S */ 3225 /* 3226 * Handle a static method call. 3227 * 3228 * for: invoke-static, invoke-static/range 3229 */ 3230 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3231 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3232 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3233 FETCH(r1, 1) @ r1<- BBBB 3234 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3235 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3236 cmp r0, #0 @ already resolved? 3237 EXPORT_PC() @ must export for invoke 3238 bne common_invokeMethodNoRange @ yes, continue on 32390: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3240 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3241 mov r2, #METHOD_STATIC @ resolver method type 3242 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3243 cmp r0, #0 @ got null? 3244 bne common_invokeMethodNoRange @ no, continue 3245 b common_exceptionThrown @ yes, handle exception 3246 3247/* ------------------------------ */ 3248 .balign 64 3249.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3250/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3251 /* 3252 * Handle an interface method call. 3253 * 3254 * for: invoke-interface, invoke-interface/range 3255 */ 3256 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3257 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3258 FETCH(r2, 2) @ r2<- FEDC or CCCC 3259 FETCH(r1, 1) @ r1<- BBBB 3260 .if (!0) 3261 and r2, r2, #15 @ r2<- C (or stays CCCC) 3262 .endif 3263 EXPORT_PC() @ must export for invoke 3264 GET_VREG(r0, r2) @ r0<- first arg ("this") 3265 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3266 cmp r0, #0 @ null obj? 3267 ldr r2, [rSELF, #offThread_method] @ r2<- method 3268 beq common_errNullObject @ yes, fail 3269 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3270 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3271 cmp r0, #0 @ failed? 3272 beq common_exceptionThrown @ yes, handle exception 3273 b common_invokeMethodNoRange @ jump to common handler 3274 3275/* ------------------------------ */ 3276 .balign 64 3277.L_OP_UNUSED_73: /* 0x73 */ 3278/* File: armv5te/OP_UNUSED_73.S */ 3279/* File: armv5te/unused.S */ 3280 bl common_abort 3281 3282 3283/* ------------------------------ */ 3284 .balign 64 3285.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3286/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3287/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3288 /* 3289 * Handle a virtual method call. 3290 * 3291 * for: invoke-virtual, invoke-virtual/range 3292 */ 3293 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3294 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3295 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3296 FETCH(r1, 1) @ r1<- BBBB 3297 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3298 FETCH(r10, 2) @ r10<- GFED or CCCC 3299 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3300 .if (!1) 3301 and r10, r10, #15 @ r10<- D (or stays CCCC) 3302 .endif 3303 cmp r0, #0 @ already resolved? 3304 EXPORT_PC() @ must export for invoke 3305 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3306 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3307 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3308 mov r2, #METHOD_VIRTUAL @ resolver method type 3309 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3310 cmp r0, #0 @ got null? 3311 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3312 b common_exceptionThrown @ yes, handle exception 3313 3314 3315/* ------------------------------ */ 3316 .balign 64 3317.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3318/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3319/* File: armv5te/OP_INVOKE_SUPER.S */ 3320 /* 3321 * Handle a "super" method call. 3322 * 3323 * for: invoke-super, invoke-super/range 3324 */ 3325 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3326 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3327 FETCH(r10, 2) @ r10<- GFED or CCCC 3328 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3329 .if (!1) 3330 and r10, r10, #15 @ r10<- D (or stays CCCC) 3331 .endif 3332 FETCH(r1, 1) @ r1<- BBBB 3333 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3334 GET_VREG(r2, r10) @ r2<- "this" ptr 3335 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3336 cmp r2, #0 @ null "this"? 3337 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3338 beq common_errNullObject @ null "this", throw exception 3339 cmp r0, #0 @ already resolved? 3340 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3341 EXPORT_PC() @ must export for invoke 3342 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3343 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3344 3345 3346/* ------------------------------ */ 3347 .balign 64 3348.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3349/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3350/* File: armv5te/OP_INVOKE_DIRECT.S */ 3351 /* 3352 * Handle a direct method call. 3353 * 3354 * (We could defer the "is 'this' pointer null" test to the common 3355 * method invocation code, and use a flag to indicate that static 3356 * calls don't count. If we do this as part of copying the arguments 3357 * out we could avoiding loading the first arg twice.) 3358 * 3359 * for: invoke-direct, invoke-direct/range 3360 */ 3361 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3362 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3363 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3364 FETCH(r1, 1) @ r1<- BBBB 3365 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3366 FETCH(r10, 2) @ r10<- GFED or CCCC 3367 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3368 .if (!1) 3369 and r10, r10, #15 @ r10<- D (or stays CCCC) 3370 .endif 3371 cmp r0, #0 @ already resolved? 3372 EXPORT_PC() @ must export for invoke 3373 GET_VREG(r2, r10) @ r2<- "this" ptr 3374 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3375.LOP_INVOKE_DIRECT_RANGE_finish: 3376 cmp r2, #0 @ null "this" ref? 3377 bne common_invokeMethodRange @ no, continue on 3378 b common_errNullObject @ yes, throw exception 3379 3380 3381/* ------------------------------ */ 3382 .balign 64 3383.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3384/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3385/* File: armv5te/OP_INVOKE_STATIC.S */ 3386 /* 3387 * Handle a static method call. 3388 * 3389 * for: invoke-static, invoke-static/range 3390 */ 3391 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3392 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3393 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3394 FETCH(r1, 1) @ r1<- BBBB 3395 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3396 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3397 cmp r0, #0 @ already resolved? 3398 EXPORT_PC() @ must export for invoke 3399 bne common_invokeMethodRange @ yes, continue on 34000: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3401 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3402 mov r2, #METHOD_STATIC @ resolver method type 3403 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3404 cmp r0, #0 @ got null? 3405 bne common_invokeMethodRange @ no, continue 3406 b common_exceptionThrown @ yes, handle exception 3407 3408 3409/* ------------------------------ */ 3410 .balign 64 3411.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3412/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3413/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3414 /* 3415 * Handle an interface method call. 3416 * 3417 * for: invoke-interface, invoke-interface/range 3418 */ 3419 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3420 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3421 FETCH(r2, 2) @ r2<- FEDC or CCCC 3422 FETCH(r1, 1) @ r1<- BBBB 3423 .if (!1) 3424 and r2, r2, #15 @ r2<- C (or stays CCCC) 3425 .endif 3426 EXPORT_PC() @ must export for invoke 3427 GET_VREG(r0, r2) @ r0<- first arg ("this") 3428 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3429 cmp r0, #0 @ null obj? 3430 ldr r2, [rSELF, #offThread_method] @ r2<- method 3431 beq common_errNullObject @ yes, fail 3432 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3433 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3434 cmp r0, #0 @ failed? 3435 beq common_exceptionThrown @ yes, handle exception 3436 b common_invokeMethodRange @ jump to common handler 3437 3438 3439/* ------------------------------ */ 3440 .balign 64 3441.L_OP_UNUSED_79: /* 0x79 */ 3442/* File: armv5te/OP_UNUSED_79.S */ 3443/* File: armv5te/unused.S */ 3444 bl common_abort 3445 3446 3447/* ------------------------------ */ 3448 .balign 64 3449.L_OP_UNUSED_7A: /* 0x7a */ 3450/* File: armv5te/OP_UNUSED_7A.S */ 3451/* File: armv5te/unused.S */ 3452 bl common_abort 3453 3454 3455/* ------------------------------ */ 3456 .balign 64 3457.L_OP_NEG_INT: /* 0x7b */ 3458/* File: armv5te/OP_NEG_INT.S */ 3459/* File: armv5te/unop.S */ 3460 /* 3461 * Generic 32-bit unary operation. Provide an "instr" line that 3462 * specifies an instruction that performs "result = op r0". 3463 * This could be an ARM instruction or a function call. 3464 * 3465 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3466 * int-to-byte, int-to-char, int-to-short 3467 */ 3468 /* unop vA, vB */ 3469 mov r3, rINST, lsr #12 @ r3<- B 3470 mov r9, rINST, lsr #8 @ r9<- A+ 3471 GET_VREG(r0, r3) @ r0<- vB 3472 and r9, r9, #15 3473 @ optional op; may set condition codes 3474 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3475 rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3476 GET_INST_OPCODE(ip) @ extract opcode from rINST 3477 SET_VREG(r0, r9) @ vAA<- r0 3478 GOTO_OPCODE(ip) @ jump to next instruction 3479 /* 9-10 instructions */ 3480 3481 3482/* ------------------------------ */ 3483 .balign 64 3484.L_OP_NOT_INT: /* 0x7c */ 3485/* File: armv5te/OP_NOT_INT.S */ 3486/* File: armv5te/unop.S */ 3487 /* 3488 * Generic 32-bit unary operation. Provide an "instr" line that 3489 * specifies an instruction that performs "result = op r0". 3490 * This could be an ARM instruction or a function call. 3491 * 3492 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3493 * int-to-byte, int-to-char, int-to-short 3494 */ 3495 /* unop vA, vB */ 3496 mov r3, rINST, lsr #12 @ r3<- B 3497 mov r9, rINST, lsr #8 @ r9<- A+ 3498 GET_VREG(r0, r3) @ r0<- vB 3499 and r9, r9, #15 3500 @ optional op; may set condition codes 3501 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3502 mvn r0, r0 @ r0<- op, r0-r3 changed 3503 GET_INST_OPCODE(ip) @ extract opcode from rINST 3504 SET_VREG(r0, r9) @ vAA<- r0 3505 GOTO_OPCODE(ip) @ jump to next instruction 3506 /* 9-10 instructions */ 3507 3508 3509/* ------------------------------ */ 3510 .balign 64 3511.L_OP_NEG_LONG: /* 0x7d */ 3512/* File: armv5te/OP_NEG_LONG.S */ 3513/* File: armv5te/unopWide.S */ 3514 /* 3515 * Generic 64-bit unary operation. Provide an "instr" line that 3516 * specifies an instruction that performs "result = op r0/r1". 3517 * This could be an ARM instruction or a function call. 3518 * 3519 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3520 */ 3521 /* unop vA, vB */ 3522 mov r9, rINST, lsr #8 @ r9<- A+ 3523 mov r3, rINST, lsr #12 @ r3<- B 3524 and r9, r9, #15 3525 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3526 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3527 ldmia r3, {r0-r1} @ r0/r1<- vAA 3528 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3529 rsbs r0, r0, #0 @ optional op; may set condition codes 3530 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3531 GET_INST_OPCODE(ip) @ extract opcode from rINST 3532 stmia r9, {r0-r1} @ vAA<- r0/r1 3533 GOTO_OPCODE(ip) @ jump to next instruction 3534 /* 12-13 instructions */ 3535 3536 3537/* ------------------------------ */ 3538 .balign 64 3539.L_OP_NOT_LONG: /* 0x7e */ 3540/* File: armv5te/OP_NOT_LONG.S */ 3541/* File: armv5te/unopWide.S */ 3542 /* 3543 * Generic 64-bit unary operation. Provide an "instr" line that 3544 * specifies an instruction that performs "result = op r0/r1". 3545 * This could be an ARM instruction or a function call. 3546 * 3547 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3548 */ 3549 /* unop vA, vB */ 3550 mov r9, rINST, lsr #8 @ r9<- A+ 3551 mov r3, rINST, lsr #12 @ r3<- B 3552 and r9, r9, #15 3553 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3554 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3555 ldmia r3, {r0-r1} @ r0/r1<- vAA 3556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3557 mvn r0, r0 @ optional op; may set condition codes 3558 mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3559 GET_INST_OPCODE(ip) @ extract opcode from rINST 3560 stmia r9, {r0-r1} @ vAA<- r0/r1 3561 GOTO_OPCODE(ip) @ jump to next instruction 3562 /* 12-13 instructions */ 3563 3564 3565/* ------------------------------ */ 3566 .balign 64 3567.L_OP_NEG_FLOAT: /* 0x7f */ 3568/* File: armv5te/OP_NEG_FLOAT.S */ 3569/* File: armv5te/unop.S */ 3570 /* 3571 * Generic 32-bit unary operation. Provide an "instr" line that 3572 * specifies an instruction that performs "result = op r0". 3573 * This could be an ARM instruction or a function call. 3574 * 3575 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3576 * int-to-byte, int-to-char, int-to-short 3577 */ 3578 /* unop vA, vB */ 3579 mov r3, rINST, lsr #12 @ r3<- B 3580 mov r9, rINST, lsr #8 @ r9<- A+ 3581 GET_VREG(r0, r3) @ r0<- vB 3582 and r9, r9, #15 3583 @ optional op; may set condition codes 3584 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3585 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3586 GET_INST_OPCODE(ip) @ extract opcode from rINST 3587 SET_VREG(r0, r9) @ vAA<- r0 3588 GOTO_OPCODE(ip) @ jump to next instruction 3589 /* 9-10 instructions */ 3590 3591 3592/* ------------------------------ */ 3593 .balign 64 3594.L_OP_NEG_DOUBLE: /* 0x80 */ 3595/* File: armv5te/OP_NEG_DOUBLE.S */ 3596/* File: armv5te/unopWide.S */ 3597 /* 3598 * Generic 64-bit unary operation. Provide an "instr" line that 3599 * specifies an instruction that performs "result = op r0/r1". 3600 * This could be an ARM instruction or a function call. 3601 * 3602 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3603 */ 3604 /* unop vA, vB */ 3605 mov r9, rINST, lsr #8 @ r9<- A+ 3606 mov r3, rINST, lsr #12 @ r3<- B 3607 and r9, r9, #15 3608 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3609 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3610 ldmia r3, {r0-r1} @ r0/r1<- vAA 3611 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3612 @ optional op; may set condition codes 3613 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3614 GET_INST_OPCODE(ip) @ extract opcode from rINST 3615 stmia r9, {r0-r1} @ vAA<- r0/r1 3616 GOTO_OPCODE(ip) @ jump to next instruction 3617 /* 12-13 instructions */ 3618 3619 3620/* ------------------------------ */ 3621 .balign 64 3622.L_OP_INT_TO_LONG: /* 0x81 */ 3623/* File: armv5te/OP_INT_TO_LONG.S */ 3624/* File: armv5te/unopWider.S */ 3625 /* 3626 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3627 * that specifies an instruction that performs "result = op r0", where 3628 * "result" is a 64-bit quantity in r0/r1. 3629 * 3630 * For: int-to-long, int-to-double, float-to-long, float-to-double 3631 */ 3632 /* unop vA, vB */ 3633 mov r9, rINST, lsr #8 @ r9<- A+ 3634 mov r3, rINST, lsr #12 @ r3<- B 3635 and r9, r9, #15 3636 GET_VREG(r0, r3) @ r0<- vB 3637 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3638 @ optional op; may set condition codes 3639 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3640 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3641 GET_INST_OPCODE(ip) @ extract opcode from rINST 3642 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3643 GOTO_OPCODE(ip) @ jump to next instruction 3644 /* 10-11 instructions */ 3645 3646 3647/* ------------------------------ */ 3648 .balign 64 3649.L_OP_INT_TO_FLOAT: /* 0x82 */ 3650/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3651/* File: arm-vfp/funop.S */ 3652 /* 3653 * Generic 32-bit unary floating-point operation. Provide an "instr" 3654 * line that specifies an instruction that performs "s1 = op s0". 3655 * 3656 * for: int-to-float, float-to-int 3657 */ 3658 /* unop vA, vB */ 3659 mov r3, rINST, lsr #12 @ r3<- B 3660 mov r9, rINST, lsr #8 @ r9<- A+ 3661 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3662 flds s0, [r3] @ s0<- vB 3663 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3664 and r9, r9, #15 @ r9<- A 3665 fsitos s1, s0 @ s1<- op 3666 GET_INST_OPCODE(ip) @ extract opcode from rINST 3667 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3668 fsts s1, [r9] @ vA<- s1 3669 GOTO_OPCODE(ip) @ jump to next instruction 3670 3671 3672/* ------------------------------ */ 3673 .balign 64 3674.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3675/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3676/* File: arm-vfp/funopWider.S */ 3677 /* 3678 * Generic 32bit-to-64bit floating point unary operation. Provide an 3679 * "instr" line that specifies an instruction that performs "d0 = op s0". 3680 * 3681 * For: int-to-double, float-to-double 3682 */ 3683 /* unop vA, vB */ 3684 mov r3, rINST, lsr #12 @ r3<- B 3685 mov r9, rINST, lsr #8 @ r9<- A+ 3686 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3687 flds s0, [r3] @ s0<- vB 3688 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3689 and r9, r9, #15 @ r9<- A 3690 fsitod d0, s0 @ d0<- op 3691 GET_INST_OPCODE(ip) @ extract opcode from rINST 3692 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3693 fstd d0, [r9] @ vA<- d0 3694 GOTO_OPCODE(ip) @ jump to next instruction 3695 3696 3697/* ------------------------------ */ 3698 .balign 64 3699.L_OP_LONG_TO_INT: /* 0x84 */ 3700/* File: armv5te/OP_LONG_TO_INT.S */ 3701/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3702/* File: armv5te/OP_MOVE.S */ 3703 /* for move, move-object, long-to-int */ 3704 /* op vA, vB */ 3705 mov r1, rINST, lsr #12 @ r1<- B from 15:12 3706 mov r0, rINST, lsr #8 @ r0<- A from 11:8 3707 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3708 GET_VREG(r2, r1) @ r2<- fp[B] 3709 and r0, r0, #15 3710 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3711 SET_VREG(r2, r0) @ fp[A]<- r2 3712 GOTO_OPCODE(ip) @ execute next instruction 3713 3714 3715/* ------------------------------ */ 3716 .balign 64 3717.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3718/* File: armv5te/OP_LONG_TO_FLOAT.S */ 3719/* File: armv5te/unopNarrower.S */ 3720 /* 3721 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3722 * that specifies an instruction that performs "result = op r0/r1", where 3723 * "result" is a 32-bit quantity in r0. 3724 * 3725 * For: long-to-float, double-to-int, double-to-float 3726 * 3727 * (This would work for long-to-int, but that instruction is actually 3728 * an exact match for OP_MOVE.) 3729 */ 3730 /* unop vA, vB */ 3731 mov r3, rINST, lsr #12 @ r3<- B 3732 mov r9, rINST, lsr #8 @ r9<- A+ 3733 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3734 and r9, r9, #15 3735 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3736 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3737 @ optional op; may set condition codes 3738 bl __aeabi_l2f @ r0<- op, r0-r3 changed 3739 GET_INST_OPCODE(ip) @ extract opcode from rINST 3740 SET_VREG(r0, r9) @ vA<- r0 3741 GOTO_OPCODE(ip) @ jump to next instruction 3742 /* 10-11 instructions */ 3743 3744 3745/* ------------------------------ */ 3746 .balign 64 3747.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3748/* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3749/* File: armv5te/unopWide.S */ 3750 /* 3751 * Generic 64-bit unary operation. Provide an "instr" line that 3752 * specifies an instruction that performs "result = op r0/r1". 3753 * This could be an ARM instruction or a function call. 3754 * 3755 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3756 */ 3757 /* unop vA, vB */ 3758 mov r9, rINST, lsr #8 @ r9<- A+ 3759 mov r3, rINST, lsr #12 @ r3<- B 3760 and r9, r9, #15 3761 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3762 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3763 ldmia r3, {r0-r1} @ r0/r1<- vAA 3764 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3765 @ optional op; may set condition codes 3766 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3767 GET_INST_OPCODE(ip) @ extract opcode from rINST 3768 stmia r9, {r0-r1} @ vAA<- r0/r1 3769 GOTO_OPCODE(ip) @ jump to next instruction 3770 /* 12-13 instructions */ 3771 3772 3773/* ------------------------------ */ 3774 .balign 64 3775.L_OP_FLOAT_TO_INT: /* 0x87 */ 3776/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3777/* File: arm-vfp/funop.S */ 3778 /* 3779 * Generic 32-bit unary floating-point operation. Provide an "instr" 3780 * line that specifies an instruction that performs "s1 = op s0". 3781 * 3782 * for: int-to-float, float-to-int 3783 */ 3784 /* unop vA, vB */ 3785 mov r3, rINST, lsr #12 @ r3<- B 3786 mov r9, rINST, lsr #8 @ r9<- A+ 3787 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3788 flds s0, [r3] @ s0<- vB 3789 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3790 and r9, r9, #15 @ r9<- A 3791 ftosizs s1, s0 @ s1<- op 3792 GET_INST_OPCODE(ip) @ extract opcode from rINST 3793 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3794 fsts s1, [r9] @ vA<- s1 3795 GOTO_OPCODE(ip) @ jump to next instruction 3796 3797 3798/* ------------------------------ */ 3799 .balign 64 3800.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3801/* File: armv5te/OP_FLOAT_TO_LONG.S */ 3802@include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3803/* File: armv5te/unopWider.S */ 3804 /* 3805 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3806 * that specifies an instruction that performs "result = op r0", where 3807 * "result" is a 64-bit quantity in r0/r1. 3808 * 3809 * For: int-to-long, int-to-double, float-to-long, float-to-double 3810 */ 3811 /* unop vA, vB */ 3812 mov r9, rINST, lsr #8 @ r9<- A+ 3813 mov r3, rINST, lsr #12 @ r3<- B 3814 and r9, r9, #15 3815 GET_VREG(r0, r3) @ r0<- vB 3816 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3817 @ optional op; may set condition codes 3818 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3819 bl f2l_doconv @ r0<- op, r0-r3 changed 3820 GET_INST_OPCODE(ip) @ extract opcode from rINST 3821 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3822 GOTO_OPCODE(ip) @ jump to next instruction 3823 /* 10-11 instructions */ 3824 3825 3826 3827/* ------------------------------ */ 3828 .balign 64 3829.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3830/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3831/* File: arm-vfp/funopWider.S */ 3832 /* 3833 * Generic 32bit-to-64bit floating point unary operation. Provide an 3834 * "instr" line that specifies an instruction that performs "d0 = op s0". 3835 * 3836 * For: int-to-double, float-to-double 3837 */ 3838 /* unop vA, vB */ 3839 mov r3, rINST, lsr #12 @ r3<- B 3840 mov r9, rINST, lsr #8 @ r9<- A+ 3841 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3842 flds s0, [r3] @ s0<- vB 3843 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3844 and r9, r9, #15 @ r9<- A 3845 fcvtds d0, s0 @ d0<- op 3846 GET_INST_OPCODE(ip) @ extract opcode from rINST 3847 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3848 fstd d0, [r9] @ vA<- d0 3849 GOTO_OPCODE(ip) @ jump to next instruction 3850 3851 3852/* ------------------------------ */ 3853 .balign 64 3854.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3855/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3856/* File: arm-vfp/funopNarrower.S */ 3857 /* 3858 * Generic 64bit-to-32bit unary floating point operation. Provide an 3859 * "instr" line that specifies an instruction that performs "s0 = op d0". 3860 * 3861 * For: double-to-int, double-to-float 3862 */ 3863 /* unop vA, vB */ 3864 mov r3, rINST, lsr #12 @ r3<- B 3865 mov r9, rINST, lsr #8 @ r9<- A+ 3866 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3867 fldd d0, [r3] @ d0<- vB 3868 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3869 and r9, r9, #15 @ r9<- A 3870 ftosizd s0, d0 @ s0<- op 3871 GET_INST_OPCODE(ip) @ extract opcode from rINST 3872 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3873 fsts s0, [r9] @ vA<- s0 3874 GOTO_OPCODE(ip) @ jump to next instruction 3875 3876 3877/* ------------------------------ */ 3878 .balign 64 3879.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3880/* File: armv5te/OP_DOUBLE_TO_LONG.S */ 3881@include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3882/* File: armv5te/unopWide.S */ 3883 /* 3884 * Generic 64-bit unary operation. Provide an "instr" line that 3885 * specifies an instruction that performs "result = op r0/r1". 3886 * This could be an ARM instruction or a function call. 3887 * 3888 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3889 */ 3890 /* unop vA, vB */ 3891 mov r9, rINST, lsr #8 @ r9<- A+ 3892 mov r3, rINST, lsr #12 @ r3<- B 3893 and r9, r9, #15 3894 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3895 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3896 ldmia r3, {r0-r1} @ r0/r1<- vAA 3897 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3898 @ optional op; may set condition codes 3899 bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3900 GET_INST_OPCODE(ip) @ extract opcode from rINST 3901 stmia r9, {r0-r1} @ vAA<- r0/r1 3902 GOTO_OPCODE(ip) @ jump to next instruction 3903 /* 12-13 instructions */ 3904 3905 3906 3907/* ------------------------------ */ 3908 .balign 64 3909.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3910/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3911/* File: arm-vfp/funopNarrower.S */ 3912 /* 3913 * Generic 64bit-to-32bit unary floating point operation. Provide an 3914 * "instr" line that specifies an instruction that performs "s0 = op d0". 3915 * 3916 * For: double-to-int, double-to-float 3917 */ 3918 /* unop vA, vB */ 3919 mov r3, rINST, lsr #12 @ r3<- B 3920 mov r9, rINST, lsr #8 @ r9<- A+ 3921 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3922 fldd d0, [r3] @ d0<- vB 3923 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3924 and r9, r9, #15 @ r9<- A 3925 fcvtsd s0, d0 @ s0<- op 3926 GET_INST_OPCODE(ip) @ extract opcode from rINST 3927 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3928 fsts s0, [r9] @ vA<- s0 3929 GOTO_OPCODE(ip) @ jump to next instruction 3930 3931 3932/* ------------------------------ */ 3933 .balign 64 3934.L_OP_INT_TO_BYTE: /* 0x8d */ 3935/* File: armv5te/OP_INT_TO_BYTE.S */ 3936/* File: armv5te/unop.S */ 3937 /* 3938 * Generic 32-bit unary operation. Provide an "instr" line that 3939 * specifies an instruction that performs "result = op r0". 3940 * This could be an ARM instruction or a function call. 3941 * 3942 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3943 * int-to-byte, int-to-char, int-to-short 3944 */ 3945 /* unop vA, vB */ 3946 mov r3, rINST, lsr #12 @ r3<- B 3947 mov r9, rINST, lsr #8 @ r9<- A+ 3948 GET_VREG(r0, r3) @ r0<- vB 3949 and r9, r9, #15 3950 mov r0, r0, asl #24 @ optional op; may set condition codes 3951 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3952 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 3953 GET_INST_OPCODE(ip) @ extract opcode from rINST 3954 SET_VREG(r0, r9) @ vAA<- r0 3955 GOTO_OPCODE(ip) @ jump to next instruction 3956 /* 9-10 instructions */ 3957 3958 3959/* ------------------------------ */ 3960 .balign 64 3961.L_OP_INT_TO_CHAR: /* 0x8e */ 3962/* File: armv5te/OP_INT_TO_CHAR.S */ 3963/* File: armv5te/unop.S */ 3964 /* 3965 * Generic 32-bit unary operation. Provide an "instr" line that 3966 * specifies an instruction that performs "result = op r0". 3967 * This could be an ARM instruction or a function call. 3968 * 3969 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3970 * int-to-byte, int-to-char, int-to-short 3971 */ 3972 /* unop vA, vB */ 3973 mov r3, rINST, lsr #12 @ r3<- B 3974 mov r9, rINST, lsr #8 @ r9<- A+ 3975 GET_VREG(r0, r3) @ r0<- vB 3976 and r9, r9, #15 3977 mov r0, r0, asl #16 @ optional op; may set condition codes 3978 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3979 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 3980 GET_INST_OPCODE(ip) @ extract opcode from rINST 3981 SET_VREG(r0, r9) @ vAA<- r0 3982 GOTO_OPCODE(ip) @ jump to next instruction 3983 /* 9-10 instructions */ 3984 3985 3986/* ------------------------------ */ 3987 .balign 64 3988.L_OP_INT_TO_SHORT: /* 0x8f */ 3989/* File: armv5te/OP_INT_TO_SHORT.S */ 3990/* File: armv5te/unop.S */ 3991 /* 3992 * Generic 32-bit unary operation. Provide an "instr" line that 3993 * specifies an instruction that performs "result = op r0". 3994 * This could be an ARM instruction or a function call. 3995 * 3996 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3997 * int-to-byte, int-to-char, int-to-short 3998 */ 3999 /* unop vA, vB */ 4000 mov r3, rINST, lsr #12 @ r3<- B 4001 mov r9, rINST, lsr #8 @ r9<- A+ 4002 GET_VREG(r0, r3) @ r0<- vB 4003 and r9, r9, #15 4004 mov r0, r0, asl #16 @ optional op; may set condition codes 4005 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4006 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 4007 GET_INST_OPCODE(ip) @ extract opcode from rINST 4008 SET_VREG(r0, r9) @ vAA<- r0 4009 GOTO_OPCODE(ip) @ jump to next instruction 4010 /* 9-10 instructions */ 4011 4012 4013/* ------------------------------ */ 4014 .balign 64 4015.L_OP_ADD_INT: /* 0x90 */ 4016/* File: armv5te/OP_ADD_INT.S */ 4017/* File: armv5te/binop.S */ 4018 /* 4019 * Generic 32-bit binary operation. Provide an "instr" line that 4020 * specifies an instruction that performs "result = r0 op r1". 4021 * This could be an ARM instruction or a function call. (If the result 4022 * comes back in a register other than r0, you can override "result".) 4023 * 4024 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4025 * vCC (r1). Useful for integer division and modulus. Note that we 4026 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4027 * handles it correctly. 4028 * 4029 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4030 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4031 * mul-float, div-float, rem-float 4032 */ 4033 /* binop vAA, vBB, vCC */ 4034 FETCH(r0, 1) @ r0<- CCBB 4035 mov r9, rINST, lsr #8 @ r9<- AA 4036 mov r3, r0, lsr #8 @ r3<- CC 4037 and r2, r0, #255 @ r2<- BB 4038 GET_VREG(r1, r3) @ r1<- vCC 4039 GET_VREG(r0, r2) @ r0<- vBB 4040 .if 0 4041 cmp r1, #0 @ is second operand zero? 4042 beq common_errDivideByZero 4043 .endif 4044 4045 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4046 @ optional op; may set condition codes 4047 add r0, r0, r1 @ r0<- op, r0-r3 changed 4048 GET_INST_OPCODE(ip) @ extract opcode from rINST 4049 SET_VREG(r0, r9) @ vAA<- r0 4050 GOTO_OPCODE(ip) @ jump to next instruction 4051 /* 11-14 instructions */ 4052 4053 4054/* ------------------------------ */ 4055 .balign 64 4056.L_OP_SUB_INT: /* 0x91 */ 4057/* File: armv5te/OP_SUB_INT.S */ 4058/* File: armv5te/binop.S */ 4059 /* 4060 * Generic 32-bit binary operation. Provide an "instr" line that 4061 * specifies an instruction that performs "result = r0 op r1". 4062 * This could be an ARM instruction or a function call. (If the result 4063 * comes back in a register other than r0, you can override "result".) 4064 * 4065 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4066 * vCC (r1). Useful for integer division and modulus. Note that we 4067 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4068 * handles it correctly. 4069 * 4070 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4071 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4072 * mul-float, div-float, rem-float 4073 */ 4074 /* binop vAA, vBB, vCC */ 4075 FETCH(r0, 1) @ r0<- CCBB 4076 mov r9, rINST, lsr #8 @ r9<- AA 4077 mov r3, r0, lsr #8 @ r3<- CC 4078 and r2, r0, #255 @ r2<- BB 4079 GET_VREG(r1, r3) @ r1<- vCC 4080 GET_VREG(r0, r2) @ r0<- vBB 4081 .if 0 4082 cmp r1, #0 @ is second operand zero? 4083 beq common_errDivideByZero 4084 .endif 4085 4086 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4087 @ optional op; may set condition codes 4088 sub r0, r0, r1 @ r0<- op, r0-r3 changed 4089 GET_INST_OPCODE(ip) @ extract opcode from rINST 4090 SET_VREG(r0, r9) @ vAA<- r0 4091 GOTO_OPCODE(ip) @ jump to next instruction 4092 /* 11-14 instructions */ 4093 4094 4095/* ------------------------------ */ 4096 .balign 64 4097.L_OP_MUL_INT: /* 0x92 */ 4098/* File: armv5te/OP_MUL_INT.S */ 4099/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4100/* File: armv5te/binop.S */ 4101 /* 4102 * Generic 32-bit binary operation. Provide an "instr" line that 4103 * specifies an instruction that performs "result = r0 op r1". 4104 * This could be an ARM instruction or a function call. (If the result 4105 * comes back in a register other than r0, you can override "result".) 4106 * 4107 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4108 * vCC (r1). Useful for integer division and modulus. Note that we 4109 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4110 * handles it correctly. 4111 * 4112 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4113 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4114 * mul-float, div-float, rem-float 4115 */ 4116 /* binop vAA, vBB, vCC */ 4117 FETCH(r0, 1) @ r0<- CCBB 4118 mov r9, rINST, lsr #8 @ r9<- AA 4119 mov r3, r0, lsr #8 @ r3<- CC 4120 and r2, r0, #255 @ r2<- BB 4121 GET_VREG(r1, r3) @ r1<- vCC 4122 GET_VREG(r0, r2) @ r0<- vBB 4123 .if 0 4124 cmp r1, #0 @ is second operand zero? 4125 beq common_errDivideByZero 4126 .endif 4127 4128 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4129 @ optional op; may set condition codes 4130 mul r0, r1, r0 @ r0<- op, r0-r3 changed 4131 GET_INST_OPCODE(ip) @ extract opcode from rINST 4132 SET_VREG(r0, r9) @ vAA<- r0 4133 GOTO_OPCODE(ip) @ jump to next instruction 4134 /* 11-14 instructions */ 4135 4136 4137/* ------------------------------ */ 4138 .balign 64 4139.L_OP_DIV_INT: /* 0x93 */ 4140/* File: armv5te/OP_DIV_INT.S */ 4141/* File: armv5te/binop.S */ 4142 /* 4143 * Generic 32-bit binary operation. Provide an "instr" line that 4144 * specifies an instruction that performs "result = r0 op r1". 4145 * This could be an ARM instruction or a function call. (If the result 4146 * comes back in a register other than r0, you can override "result".) 4147 * 4148 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4149 * vCC (r1). Useful for integer division and modulus. Note that we 4150 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4151 * handles it correctly. 4152 * 4153 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4154 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4155 * mul-float, div-float, rem-float 4156 */ 4157 /* binop vAA, vBB, vCC */ 4158 FETCH(r0, 1) @ r0<- CCBB 4159 mov r9, rINST, lsr #8 @ r9<- AA 4160 mov r3, r0, lsr #8 @ r3<- CC 4161 and r2, r0, #255 @ r2<- BB 4162 GET_VREG(r1, r3) @ r1<- vCC 4163 GET_VREG(r0, r2) @ r0<- vBB 4164 .if 1 4165 cmp r1, #0 @ is second operand zero? 4166 beq common_errDivideByZero 4167 .endif 4168 4169 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4170 @ optional op; may set condition codes 4171 bl __aeabi_idiv @ r0<- op, r0-r3 changed 4172 GET_INST_OPCODE(ip) @ extract opcode from rINST 4173 SET_VREG(r0, r9) @ vAA<- r0 4174 GOTO_OPCODE(ip) @ jump to next instruction 4175 /* 11-14 instructions */ 4176 4177 4178/* ------------------------------ */ 4179 .balign 64 4180.L_OP_REM_INT: /* 0x94 */ 4181/* File: armv5te/OP_REM_INT.S */ 4182/* idivmod returns quotient in r0 and remainder in r1 */ 4183/* File: armv5te/binop.S */ 4184 /* 4185 * Generic 32-bit binary operation. Provide an "instr" line that 4186 * specifies an instruction that performs "result = r0 op r1". 4187 * This could be an ARM instruction or a function call. (If the result 4188 * comes back in a register other than r0, you can override "result".) 4189 * 4190 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4191 * vCC (r1). Useful for integer division and modulus. Note that we 4192 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4193 * handles it correctly. 4194 * 4195 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4196 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4197 * mul-float, div-float, rem-float 4198 */ 4199 /* binop vAA, vBB, vCC */ 4200 FETCH(r0, 1) @ r0<- CCBB 4201 mov r9, rINST, lsr #8 @ r9<- AA 4202 mov r3, r0, lsr #8 @ r3<- CC 4203 and r2, r0, #255 @ r2<- BB 4204 GET_VREG(r1, r3) @ r1<- vCC 4205 GET_VREG(r0, r2) @ r0<- vBB 4206 .if 1 4207 cmp r1, #0 @ is second operand zero? 4208 beq common_errDivideByZero 4209 .endif 4210 4211 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4212 @ optional op; may set condition codes 4213 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4214 GET_INST_OPCODE(ip) @ extract opcode from rINST 4215 SET_VREG(r1, r9) @ vAA<- r1 4216 GOTO_OPCODE(ip) @ jump to next instruction 4217 /* 11-14 instructions */ 4218 4219 4220/* ------------------------------ */ 4221 .balign 64 4222.L_OP_AND_INT: /* 0x95 */ 4223/* File: armv5te/OP_AND_INT.S */ 4224/* File: armv5te/binop.S */ 4225 /* 4226 * Generic 32-bit binary operation. Provide an "instr" line that 4227 * specifies an instruction that performs "result = r0 op r1". 4228 * This could be an ARM instruction or a function call. (If the result 4229 * comes back in a register other than r0, you can override "result".) 4230 * 4231 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4232 * vCC (r1). Useful for integer division and modulus. Note that we 4233 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4234 * handles it correctly. 4235 * 4236 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4237 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4238 * mul-float, div-float, rem-float 4239 */ 4240 /* binop vAA, vBB, vCC */ 4241 FETCH(r0, 1) @ r0<- CCBB 4242 mov r9, rINST, lsr #8 @ r9<- AA 4243 mov r3, r0, lsr #8 @ r3<- CC 4244 and r2, r0, #255 @ r2<- BB 4245 GET_VREG(r1, r3) @ r1<- vCC 4246 GET_VREG(r0, r2) @ r0<- vBB 4247 .if 0 4248 cmp r1, #0 @ is second operand zero? 4249 beq common_errDivideByZero 4250 .endif 4251 4252 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4253 @ optional op; may set condition codes 4254 and r0, r0, r1 @ r0<- op, r0-r3 changed 4255 GET_INST_OPCODE(ip) @ extract opcode from rINST 4256 SET_VREG(r0, r9) @ vAA<- r0 4257 GOTO_OPCODE(ip) @ jump to next instruction 4258 /* 11-14 instructions */ 4259 4260 4261/* ------------------------------ */ 4262 .balign 64 4263.L_OP_OR_INT: /* 0x96 */ 4264/* File: armv5te/OP_OR_INT.S */ 4265/* File: armv5te/binop.S */ 4266 /* 4267 * Generic 32-bit binary operation. Provide an "instr" line that 4268 * specifies an instruction that performs "result = r0 op r1". 4269 * This could be an ARM instruction or a function call. (If the result 4270 * comes back in a register other than r0, you can override "result".) 4271 * 4272 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4273 * vCC (r1). Useful for integer division and modulus. Note that we 4274 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4275 * handles it correctly. 4276 * 4277 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4278 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4279 * mul-float, div-float, rem-float 4280 */ 4281 /* binop vAA, vBB, vCC */ 4282 FETCH(r0, 1) @ r0<- CCBB 4283 mov r9, rINST, lsr #8 @ r9<- AA 4284 mov r3, r0, lsr #8 @ r3<- CC 4285 and r2, r0, #255 @ r2<- BB 4286 GET_VREG(r1, r3) @ r1<- vCC 4287 GET_VREG(r0, r2) @ r0<- vBB 4288 .if 0 4289 cmp r1, #0 @ is second operand zero? 4290 beq common_errDivideByZero 4291 .endif 4292 4293 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4294 @ optional op; may set condition codes 4295 orr r0, r0, r1 @ r0<- op, r0-r3 changed 4296 GET_INST_OPCODE(ip) @ extract opcode from rINST 4297 SET_VREG(r0, r9) @ vAA<- r0 4298 GOTO_OPCODE(ip) @ jump to next instruction 4299 /* 11-14 instructions */ 4300 4301 4302/* ------------------------------ */ 4303 .balign 64 4304.L_OP_XOR_INT: /* 0x97 */ 4305/* File: armv5te/OP_XOR_INT.S */ 4306/* File: armv5te/binop.S */ 4307 /* 4308 * Generic 32-bit binary operation. Provide an "instr" line that 4309 * specifies an instruction that performs "result = r0 op r1". 4310 * This could be an ARM instruction or a function call. (If the result 4311 * comes back in a register other than r0, you can override "result".) 4312 * 4313 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4314 * vCC (r1). Useful for integer division and modulus. Note that we 4315 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4316 * handles it correctly. 4317 * 4318 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4319 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4320 * mul-float, div-float, rem-float 4321 */ 4322 /* binop vAA, vBB, vCC */ 4323 FETCH(r0, 1) @ r0<- CCBB 4324 mov r9, rINST, lsr #8 @ r9<- AA 4325 mov r3, r0, lsr #8 @ r3<- CC 4326 and r2, r0, #255 @ r2<- BB 4327 GET_VREG(r1, r3) @ r1<- vCC 4328 GET_VREG(r0, r2) @ r0<- vBB 4329 .if 0 4330 cmp r1, #0 @ is second operand zero? 4331 beq common_errDivideByZero 4332 .endif 4333 4334 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4335 @ optional op; may set condition codes 4336 eor r0, r0, r1 @ r0<- op, r0-r3 changed 4337 GET_INST_OPCODE(ip) @ extract opcode from rINST 4338 SET_VREG(r0, r9) @ vAA<- r0 4339 GOTO_OPCODE(ip) @ jump to next instruction 4340 /* 11-14 instructions */ 4341 4342 4343/* ------------------------------ */ 4344 .balign 64 4345.L_OP_SHL_INT: /* 0x98 */ 4346/* File: armv5te/OP_SHL_INT.S */ 4347/* File: armv5te/binop.S */ 4348 /* 4349 * Generic 32-bit binary operation. Provide an "instr" line that 4350 * specifies an instruction that performs "result = r0 op r1". 4351 * This could be an ARM instruction or a function call. (If the result 4352 * comes back in a register other than r0, you can override "result".) 4353 * 4354 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4355 * vCC (r1). Useful for integer division and modulus. Note that we 4356 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4357 * handles it correctly. 4358 * 4359 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4360 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4361 * mul-float, div-float, rem-float 4362 */ 4363 /* binop vAA, vBB, vCC */ 4364 FETCH(r0, 1) @ r0<- CCBB 4365 mov r9, rINST, lsr #8 @ r9<- AA 4366 mov r3, r0, lsr #8 @ r3<- CC 4367 and r2, r0, #255 @ r2<- BB 4368 GET_VREG(r1, r3) @ r1<- vCC 4369 GET_VREG(r0, r2) @ r0<- vBB 4370 .if 0 4371 cmp r1, #0 @ is second operand zero? 4372 beq common_errDivideByZero 4373 .endif 4374 4375 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4376 and r1, r1, #31 @ optional op; may set condition codes 4377 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4378 GET_INST_OPCODE(ip) @ extract opcode from rINST 4379 SET_VREG(r0, r9) @ vAA<- r0 4380 GOTO_OPCODE(ip) @ jump to next instruction 4381 /* 11-14 instructions */ 4382 4383 4384/* ------------------------------ */ 4385 .balign 64 4386.L_OP_SHR_INT: /* 0x99 */ 4387/* File: armv5te/OP_SHR_INT.S */ 4388/* File: armv5te/binop.S */ 4389 /* 4390 * Generic 32-bit binary operation. Provide an "instr" line that 4391 * specifies an instruction that performs "result = r0 op r1". 4392 * This could be an ARM instruction or a function call. (If the result 4393 * comes back in a register other than r0, you can override "result".) 4394 * 4395 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4396 * vCC (r1). Useful for integer division and modulus. Note that we 4397 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4398 * handles it correctly. 4399 * 4400 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4401 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4402 * mul-float, div-float, rem-float 4403 */ 4404 /* binop vAA, vBB, vCC */ 4405 FETCH(r0, 1) @ r0<- CCBB 4406 mov r9, rINST, lsr #8 @ r9<- AA 4407 mov r3, r0, lsr #8 @ r3<- CC 4408 and r2, r0, #255 @ r2<- BB 4409 GET_VREG(r1, r3) @ r1<- vCC 4410 GET_VREG(r0, r2) @ r0<- vBB 4411 .if 0 4412 cmp r1, #0 @ is second operand zero? 4413 beq common_errDivideByZero 4414 .endif 4415 4416 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4417 and r1, r1, #31 @ optional op; may set condition codes 4418 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4419 GET_INST_OPCODE(ip) @ extract opcode from rINST 4420 SET_VREG(r0, r9) @ vAA<- r0 4421 GOTO_OPCODE(ip) @ jump to next instruction 4422 /* 11-14 instructions */ 4423 4424 4425/* ------------------------------ */ 4426 .balign 64 4427.L_OP_USHR_INT: /* 0x9a */ 4428/* File: armv5te/OP_USHR_INT.S */ 4429/* File: armv5te/binop.S */ 4430 /* 4431 * Generic 32-bit binary operation. Provide an "instr" line that 4432 * specifies an instruction that performs "result = r0 op r1". 4433 * This could be an ARM instruction or a function call. (If the result 4434 * comes back in a register other than r0, you can override "result".) 4435 * 4436 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4437 * vCC (r1). Useful for integer division and modulus. Note that we 4438 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4439 * handles it correctly. 4440 * 4441 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4442 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4443 * mul-float, div-float, rem-float 4444 */ 4445 /* binop vAA, vBB, vCC */ 4446 FETCH(r0, 1) @ r0<- CCBB 4447 mov r9, rINST, lsr #8 @ r9<- AA 4448 mov r3, r0, lsr #8 @ r3<- CC 4449 and r2, r0, #255 @ r2<- BB 4450 GET_VREG(r1, r3) @ r1<- vCC 4451 GET_VREG(r0, r2) @ r0<- vBB 4452 .if 0 4453 cmp r1, #0 @ is second operand zero? 4454 beq common_errDivideByZero 4455 .endif 4456 4457 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4458 and r1, r1, #31 @ optional op; may set condition codes 4459 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4460 GET_INST_OPCODE(ip) @ extract opcode from rINST 4461 SET_VREG(r0, r9) @ vAA<- r0 4462 GOTO_OPCODE(ip) @ jump to next instruction 4463 /* 11-14 instructions */ 4464 4465 4466/* ------------------------------ */ 4467 .balign 64 4468.L_OP_ADD_LONG: /* 0x9b */ 4469/* File: armv5te/OP_ADD_LONG.S */ 4470/* File: armv5te/binopWide.S */ 4471 /* 4472 * Generic 64-bit binary operation. Provide an "instr" line that 4473 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4474 * This could be an ARM instruction or a function call. (If the result 4475 * comes back in a register other than r0, you can override "result".) 4476 * 4477 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4478 * vCC (r1). Useful for integer division and modulus. 4479 * 4480 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4481 * xor-long, add-double, sub-double, mul-double, div-double, 4482 * rem-double 4483 * 4484 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4485 */ 4486 /* binop vAA, vBB, vCC */ 4487 FETCH(r0, 1) @ r0<- CCBB 4488 mov r9, rINST, lsr #8 @ r9<- AA 4489 and r2, r0, #255 @ r2<- BB 4490 mov r3, r0, lsr #8 @ r3<- CC 4491 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4492 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4493 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4494 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4495 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4496 .if 0 4497 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4498 beq common_errDivideByZero 4499 .endif 4500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4501 4502 adds r0, r0, r2 @ optional op; may set condition codes 4503 adc r1, r1, r3 @ result<- op, r0-r3 changed 4504 GET_INST_OPCODE(ip) @ extract opcode from rINST 4505 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4506 GOTO_OPCODE(ip) @ jump to next instruction 4507 /* 14-17 instructions */ 4508 4509 4510/* ------------------------------ */ 4511 .balign 64 4512.L_OP_SUB_LONG: /* 0x9c */ 4513/* File: armv5te/OP_SUB_LONG.S */ 4514/* File: armv5te/binopWide.S */ 4515 /* 4516 * Generic 64-bit binary operation. Provide an "instr" line that 4517 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4518 * This could be an ARM instruction or a function call. (If the result 4519 * comes back in a register other than r0, you can override "result".) 4520 * 4521 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4522 * vCC (r1). Useful for integer division and modulus. 4523 * 4524 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4525 * xor-long, add-double, sub-double, mul-double, div-double, 4526 * rem-double 4527 * 4528 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4529 */ 4530 /* binop vAA, vBB, vCC */ 4531 FETCH(r0, 1) @ r0<- CCBB 4532 mov r9, rINST, lsr #8 @ r9<- AA 4533 and r2, r0, #255 @ r2<- BB 4534 mov r3, r0, lsr #8 @ r3<- CC 4535 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4536 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4537 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4538 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4539 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4540 .if 0 4541 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4542 beq common_errDivideByZero 4543 .endif 4544 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4545 4546 subs r0, r0, r2 @ optional op; may set condition codes 4547 sbc r1, r1, r3 @ result<- op, r0-r3 changed 4548 GET_INST_OPCODE(ip) @ extract opcode from rINST 4549 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4550 GOTO_OPCODE(ip) @ jump to next instruction 4551 /* 14-17 instructions */ 4552 4553 4554/* ------------------------------ */ 4555 .balign 64 4556.L_OP_MUL_LONG: /* 0x9d */ 4557/* File: armv5te/OP_MUL_LONG.S */ 4558 /* 4559 * Signed 64-bit integer multiply. 4560 * 4561 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4562 * WX 4563 * x YZ 4564 * -------- 4565 * ZW ZX 4566 * YW YX 4567 * 4568 * The low word of the result holds ZX, the high word holds 4569 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4570 * it doesn't fit in the low 64 bits. 4571 * 4572 * Unlike most ARM math operations, multiply instructions have 4573 * restrictions on using the same register more than once (Rd and Rm 4574 * cannot be the same). 4575 */ 4576 /* mul-long vAA, vBB, vCC */ 4577 FETCH(r0, 1) @ r0<- CCBB 4578 and r2, r0, #255 @ r2<- BB 4579 mov r3, r0, lsr #8 @ r3<- CC 4580 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4581 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4582 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4583 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4584 mul ip, r2, r1 @ ip<- ZxW 4585 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4586 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4587 mov r0, rINST, lsr #8 @ r0<- AA 4588 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4589 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4590 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4591 b .LOP_MUL_LONG_finish 4592 4593/* ------------------------------ */ 4594 .balign 64 4595.L_OP_DIV_LONG: /* 0x9e */ 4596/* File: armv5te/OP_DIV_LONG.S */ 4597/* File: armv5te/binopWide.S */ 4598 /* 4599 * Generic 64-bit binary operation. Provide an "instr" line that 4600 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4601 * This could be an ARM instruction or a function call. (If the result 4602 * comes back in a register other than r0, you can override "result".) 4603 * 4604 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4605 * vCC (r1). Useful for integer division and modulus. 4606 * 4607 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4608 * xor-long, add-double, sub-double, mul-double, div-double, 4609 * rem-double 4610 * 4611 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4612 */ 4613 /* binop vAA, vBB, vCC */ 4614 FETCH(r0, 1) @ r0<- CCBB 4615 mov r9, rINST, lsr #8 @ r9<- AA 4616 and r2, r0, #255 @ r2<- BB 4617 mov r3, r0, lsr #8 @ r3<- CC 4618 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4619 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4620 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4621 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4622 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4623 .if 1 4624 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4625 beq common_errDivideByZero 4626 .endif 4627 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4628 4629 @ optional op; may set condition codes 4630 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4631 GET_INST_OPCODE(ip) @ extract opcode from rINST 4632 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4633 GOTO_OPCODE(ip) @ jump to next instruction 4634 /* 14-17 instructions */ 4635 4636 4637/* ------------------------------ */ 4638 .balign 64 4639.L_OP_REM_LONG: /* 0x9f */ 4640/* File: armv5te/OP_REM_LONG.S */ 4641/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4642/* File: armv5te/binopWide.S */ 4643 /* 4644 * Generic 64-bit binary operation. Provide an "instr" line that 4645 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4646 * This could be an ARM instruction or a function call. (If the result 4647 * comes back in a register other than r0, you can override "result".) 4648 * 4649 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4650 * vCC (r1). Useful for integer division and modulus. 4651 * 4652 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4653 * xor-long, add-double, sub-double, mul-double, div-double, 4654 * rem-double 4655 * 4656 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4657 */ 4658 /* binop vAA, vBB, vCC */ 4659 FETCH(r0, 1) @ r0<- CCBB 4660 mov r9, rINST, lsr #8 @ r9<- AA 4661 and r2, r0, #255 @ r2<- BB 4662 mov r3, r0, lsr #8 @ r3<- CC 4663 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4664 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4665 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4666 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4667 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4668 .if 1 4669 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4670 beq common_errDivideByZero 4671 .endif 4672 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4673 4674 @ optional op; may set condition codes 4675 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4676 GET_INST_OPCODE(ip) @ extract opcode from rINST 4677 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4678 GOTO_OPCODE(ip) @ jump to next instruction 4679 /* 14-17 instructions */ 4680 4681 4682/* ------------------------------ */ 4683 .balign 64 4684.L_OP_AND_LONG: /* 0xa0 */ 4685/* File: armv5te/OP_AND_LONG.S */ 4686/* File: armv5te/binopWide.S */ 4687 /* 4688 * Generic 64-bit binary operation. Provide an "instr" line that 4689 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4690 * This could be an ARM instruction or a function call. (If the result 4691 * comes back in a register other than r0, you can override "result".) 4692 * 4693 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4694 * vCC (r1). Useful for integer division and modulus. 4695 * 4696 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4697 * xor-long, add-double, sub-double, mul-double, div-double, 4698 * rem-double 4699 * 4700 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4701 */ 4702 /* binop vAA, vBB, vCC */ 4703 FETCH(r0, 1) @ r0<- CCBB 4704 mov r9, rINST, lsr #8 @ r9<- AA 4705 and r2, r0, #255 @ r2<- BB 4706 mov r3, r0, lsr #8 @ r3<- CC 4707 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4708 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4709 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4710 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4711 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4712 .if 0 4713 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4714 beq common_errDivideByZero 4715 .endif 4716 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4717 4718 and r0, r0, r2 @ optional op; may set condition codes 4719 and r1, r1, r3 @ result<- op, r0-r3 changed 4720 GET_INST_OPCODE(ip) @ extract opcode from rINST 4721 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4722 GOTO_OPCODE(ip) @ jump to next instruction 4723 /* 14-17 instructions */ 4724 4725 4726/* ------------------------------ */ 4727 .balign 64 4728.L_OP_OR_LONG: /* 0xa1 */ 4729/* File: armv5te/OP_OR_LONG.S */ 4730/* File: armv5te/binopWide.S */ 4731 /* 4732 * Generic 64-bit binary operation. Provide an "instr" line that 4733 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4734 * This could be an ARM instruction or a function call. (If the result 4735 * comes back in a register other than r0, you can override "result".) 4736 * 4737 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4738 * vCC (r1). Useful for integer division and modulus. 4739 * 4740 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4741 * xor-long, add-double, sub-double, mul-double, div-double, 4742 * rem-double 4743 * 4744 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4745 */ 4746 /* binop vAA, vBB, vCC */ 4747 FETCH(r0, 1) @ r0<- CCBB 4748 mov r9, rINST, lsr #8 @ r9<- AA 4749 and r2, r0, #255 @ r2<- BB 4750 mov r3, r0, lsr #8 @ r3<- CC 4751 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4752 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4753 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4754 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4755 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4756 .if 0 4757 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4758 beq common_errDivideByZero 4759 .endif 4760 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4761 4762 orr r0, r0, r2 @ optional op; may set condition codes 4763 orr r1, r1, r3 @ result<- op, r0-r3 changed 4764 GET_INST_OPCODE(ip) @ extract opcode from rINST 4765 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4766 GOTO_OPCODE(ip) @ jump to next instruction 4767 /* 14-17 instructions */ 4768 4769 4770/* ------------------------------ */ 4771 .balign 64 4772.L_OP_XOR_LONG: /* 0xa2 */ 4773/* File: armv5te/OP_XOR_LONG.S */ 4774/* File: armv5te/binopWide.S */ 4775 /* 4776 * Generic 64-bit binary operation. Provide an "instr" line that 4777 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4778 * This could be an ARM instruction or a function call. (If the result 4779 * comes back in a register other than r0, you can override "result".) 4780 * 4781 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4782 * vCC (r1). Useful for integer division and modulus. 4783 * 4784 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4785 * xor-long, add-double, sub-double, mul-double, div-double, 4786 * rem-double 4787 * 4788 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4789 */ 4790 /* binop vAA, vBB, vCC */ 4791 FETCH(r0, 1) @ r0<- CCBB 4792 mov r9, rINST, lsr #8 @ r9<- AA 4793 and r2, r0, #255 @ r2<- BB 4794 mov r3, r0, lsr #8 @ r3<- CC 4795 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4796 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4797 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4798 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4799 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4800 .if 0 4801 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4802 beq common_errDivideByZero 4803 .endif 4804 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4805 4806 eor r0, r0, r2 @ optional op; may set condition codes 4807 eor r1, r1, r3 @ result<- op, r0-r3 changed 4808 GET_INST_OPCODE(ip) @ extract opcode from rINST 4809 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4810 GOTO_OPCODE(ip) @ jump to next instruction 4811 /* 14-17 instructions */ 4812 4813 4814/* ------------------------------ */ 4815 .balign 64 4816.L_OP_SHL_LONG: /* 0xa3 */ 4817/* File: armv5te/OP_SHL_LONG.S */ 4818 /* 4819 * Long integer shift. This is different from the generic 32/64-bit 4820 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4821 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4822 * 6 bits of the shift distance. 4823 */ 4824 /* shl-long vAA, vBB, vCC */ 4825 FETCH(r0, 1) @ r0<- CCBB 4826 mov r9, rINST, lsr #8 @ r9<- AA 4827 and r3, r0, #255 @ r3<- BB 4828 mov r0, r0, lsr #8 @ r0<- CC 4829 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4830 GET_VREG(r2, r0) @ r2<- vCC 4831 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4832 and r2, r2, #63 @ r2<- r2 & 0x3f 4833 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4834 4835 mov r1, r1, asl r2 @ r1<- r1 << r2 4836 rsb r3, r2, #32 @ r3<- 32 - r2 4837 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4838 subs ip, r2, #32 @ ip<- r2 - 32 4839 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4840 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4841 b .LOP_SHL_LONG_finish 4842 4843/* ------------------------------ */ 4844 .balign 64 4845.L_OP_SHR_LONG: /* 0xa4 */ 4846/* File: armv5te/OP_SHR_LONG.S */ 4847 /* 4848 * Long integer shift. This is different from the generic 32/64-bit 4849 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4850 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4851 * 6 bits of the shift distance. 4852 */ 4853 /* shr-long vAA, vBB, vCC */ 4854 FETCH(r0, 1) @ r0<- CCBB 4855 mov r9, rINST, lsr #8 @ r9<- AA 4856 and r3, r0, #255 @ r3<- BB 4857 mov r0, r0, lsr #8 @ r0<- CC 4858 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4859 GET_VREG(r2, r0) @ r2<- vCC 4860 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4861 and r2, r2, #63 @ r0<- r0 & 0x3f 4862 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4863 4864 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4865 rsb r3, r2, #32 @ r3<- 32 - r2 4866 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4867 subs ip, r2, #32 @ ip<- r2 - 32 4868 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4869 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4870 b .LOP_SHR_LONG_finish 4871 4872/* ------------------------------ */ 4873 .balign 64 4874.L_OP_USHR_LONG: /* 0xa5 */ 4875/* File: armv5te/OP_USHR_LONG.S */ 4876 /* 4877 * Long integer shift. This is different from the generic 32/64-bit 4878 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4879 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4880 * 6 bits of the shift distance. 4881 */ 4882 /* ushr-long vAA, vBB, vCC */ 4883 FETCH(r0, 1) @ r0<- CCBB 4884 mov r9, rINST, lsr #8 @ r9<- AA 4885 and r3, r0, #255 @ r3<- BB 4886 mov r0, r0, lsr #8 @ r0<- CC 4887 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4888 GET_VREG(r2, r0) @ r2<- vCC 4889 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4890 and r2, r2, #63 @ r0<- r0 & 0x3f 4891 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4892 4893 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4894 rsb r3, r2, #32 @ r3<- 32 - r2 4895 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4896 subs ip, r2, #32 @ ip<- r2 - 32 4897 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4898 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4899 b .LOP_USHR_LONG_finish 4900 4901/* ------------------------------ */ 4902 .balign 64 4903.L_OP_ADD_FLOAT: /* 0xa6 */ 4904/* File: arm-vfp/OP_ADD_FLOAT.S */ 4905/* File: arm-vfp/fbinop.S */ 4906 /* 4907 * Generic 32-bit floating-point operation. Provide an "instr" line that 4908 * specifies an instruction that performs "s2 = s0 op s1". Because we 4909 * use the "softfp" ABI, this must be an instruction, not a function call. 4910 * 4911 * For: add-float, sub-float, mul-float, div-float 4912 */ 4913 /* floatop vAA, vBB, vCC */ 4914 FETCH(r0, 1) @ r0<- CCBB 4915 mov r9, rINST, lsr #8 @ r9<- AA 4916 mov r3, r0, lsr #8 @ r3<- CC 4917 and r2, r0, #255 @ r2<- BB 4918 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4919 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4920 flds s1, [r3] @ s1<- vCC 4921 flds s0, [r2] @ s0<- vBB 4922 4923 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4924 fadds s2, s0, s1 @ s2<- op 4925 GET_INST_OPCODE(ip) @ extract opcode from rINST 4926 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4927 fsts s2, [r9] @ vAA<- s2 4928 GOTO_OPCODE(ip) @ jump to next instruction 4929 4930 4931/* ------------------------------ */ 4932 .balign 64 4933.L_OP_SUB_FLOAT: /* 0xa7 */ 4934/* File: arm-vfp/OP_SUB_FLOAT.S */ 4935/* File: arm-vfp/fbinop.S */ 4936 /* 4937 * Generic 32-bit floating-point operation. Provide an "instr" line that 4938 * specifies an instruction that performs "s2 = s0 op s1". Because we 4939 * use the "softfp" ABI, this must be an instruction, not a function call. 4940 * 4941 * For: add-float, sub-float, mul-float, div-float 4942 */ 4943 /* floatop vAA, vBB, vCC */ 4944 FETCH(r0, 1) @ r0<- CCBB 4945 mov r9, rINST, lsr #8 @ r9<- AA 4946 mov r3, r0, lsr #8 @ r3<- CC 4947 and r2, r0, #255 @ r2<- BB 4948 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4949 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4950 flds s1, [r3] @ s1<- vCC 4951 flds s0, [r2] @ s0<- vBB 4952 4953 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4954 fsubs s2, s0, s1 @ s2<- op 4955 GET_INST_OPCODE(ip) @ extract opcode from rINST 4956 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4957 fsts s2, [r9] @ vAA<- s2 4958 GOTO_OPCODE(ip) @ jump to next instruction 4959 4960 4961/* ------------------------------ */ 4962 .balign 64 4963.L_OP_MUL_FLOAT: /* 0xa8 */ 4964/* File: arm-vfp/OP_MUL_FLOAT.S */ 4965/* File: arm-vfp/fbinop.S */ 4966 /* 4967 * Generic 32-bit floating-point operation. Provide an "instr" line that 4968 * specifies an instruction that performs "s2 = s0 op s1". Because we 4969 * use the "softfp" ABI, this must be an instruction, not a function call. 4970 * 4971 * For: add-float, sub-float, mul-float, div-float 4972 */ 4973 /* floatop vAA, vBB, vCC */ 4974 FETCH(r0, 1) @ r0<- CCBB 4975 mov r9, rINST, lsr #8 @ r9<- AA 4976 mov r3, r0, lsr #8 @ r3<- CC 4977 and r2, r0, #255 @ r2<- BB 4978 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4979 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4980 flds s1, [r3] @ s1<- vCC 4981 flds s0, [r2] @ s0<- vBB 4982 4983 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4984 fmuls s2, s0, s1 @ s2<- op 4985 GET_INST_OPCODE(ip) @ extract opcode from rINST 4986 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4987 fsts s2, [r9] @ vAA<- s2 4988 GOTO_OPCODE(ip) @ jump to next instruction 4989 4990 4991/* ------------------------------ */ 4992 .balign 64 4993.L_OP_DIV_FLOAT: /* 0xa9 */ 4994/* File: arm-vfp/OP_DIV_FLOAT.S */ 4995/* File: arm-vfp/fbinop.S */ 4996 /* 4997 * Generic 32-bit floating-point operation. Provide an "instr" line that 4998 * specifies an instruction that performs "s2 = s0 op s1". Because we 4999 * use the "softfp" ABI, this must be an instruction, not a function call. 5000 * 5001 * For: add-float, sub-float, mul-float, div-float 5002 */ 5003 /* floatop vAA, vBB, vCC */ 5004 FETCH(r0, 1) @ r0<- CCBB 5005 mov r9, rINST, lsr #8 @ r9<- AA 5006 mov r3, r0, lsr #8 @ r3<- CC 5007 and r2, r0, #255 @ r2<- BB 5008 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5009 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5010 flds s1, [r3] @ s1<- vCC 5011 flds s0, [r2] @ s0<- vBB 5012 5013 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5014 fdivs s2, s0, s1 @ s2<- op 5015 GET_INST_OPCODE(ip) @ extract opcode from rINST 5016 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5017 fsts s2, [r9] @ vAA<- s2 5018 GOTO_OPCODE(ip) @ jump to next instruction 5019 5020 5021/* ------------------------------ */ 5022 .balign 64 5023.L_OP_REM_FLOAT: /* 0xaa */ 5024/* File: armv5te/OP_REM_FLOAT.S */ 5025/* EABI doesn't define a float remainder function, but libm does */ 5026/* File: armv5te/binop.S */ 5027 /* 5028 * Generic 32-bit binary operation. Provide an "instr" line that 5029 * specifies an instruction that performs "result = r0 op r1". 5030 * This could be an ARM instruction or a function call. (If the result 5031 * comes back in a register other than r0, you can override "result".) 5032 * 5033 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5034 * vCC (r1). Useful for integer division and modulus. Note that we 5035 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5036 * handles it correctly. 5037 * 5038 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5039 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5040 * mul-float, div-float, rem-float 5041 */ 5042 /* binop vAA, vBB, vCC */ 5043 FETCH(r0, 1) @ r0<- CCBB 5044 mov r9, rINST, lsr #8 @ r9<- AA 5045 mov r3, r0, lsr #8 @ r3<- CC 5046 and r2, r0, #255 @ r2<- BB 5047 GET_VREG(r1, r3) @ r1<- vCC 5048 GET_VREG(r0, r2) @ r0<- vBB 5049 .if 0 5050 cmp r1, #0 @ is second operand zero? 5051 beq common_errDivideByZero 5052 .endif 5053 5054 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5055 @ optional op; may set condition codes 5056 bl fmodf @ r0<- op, r0-r3 changed 5057 GET_INST_OPCODE(ip) @ extract opcode from rINST 5058 SET_VREG(r0, r9) @ vAA<- r0 5059 GOTO_OPCODE(ip) @ jump to next instruction 5060 /* 11-14 instructions */ 5061 5062 5063/* ------------------------------ */ 5064 .balign 64 5065.L_OP_ADD_DOUBLE: /* 0xab */ 5066/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5067/* File: arm-vfp/fbinopWide.S */ 5068 /* 5069 * Generic 64-bit double-precision floating point binary operation. 5070 * Provide an "instr" line that specifies an instruction that performs 5071 * "d2 = d0 op d1". 5072 * 5073 * for: add-double, sub-double, mul-double, div-double 5074 */ 5075 /* doubleop vAA, vBB, vCC */ 5076 FETCH(r0, 1) @ r0<- CCBB 5077 mov r9, rINST, lsr #8 @ r9<- AA 5078 mov r3, r0, lsr #8 @ r3<- CC 5079 and r2, r0, #255 @ r2<- BB 5080 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5081 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5082 fldd d1, [r3] @ d1<- vCC 5083 fldd d0, [r2] @ d0<- vBB 5084 5085 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5086 faddd d2, d0, d1 @ s2<- op 5087 GET_INST_OPCODE(ip) @ extract opcode from rINST 5088 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5089 fstd d2, [r9] @ vAA<- d2 5090 GOTO_OPCODE(ip) @ jump to next instruction 5091 5092 5093/* ------------------------------ */ 5094 .balign 64 5095.L_OP_SUB_DOUBLE: /* 0xac */ 5096/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5097/* File: arm-vfp/fbinopWide.S */ 5098 /* 5099 * Generic 64-bit double-precision floating point binary operation. 5100 * Provide an "instr" line that specifies an instruction that performs 5101 * "d2 = d0 op d1". 5102 * 5103 * for: add-double, sub-double, mul-double, div-double 5104 */ 5105 /* doubleop vAA, vBB, vCC */ 5106 FETCH(r0, 1) @ r0<- CCBB 5107 mov r9, rINST, lsr #8 @ r9<- AA 5108 mov r3, r0, lsr #8 @ r3<- CC 5109 and r2, r0, #255 @ r2<- BB 5110 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5111 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5112 fldd d1, [r3] @ d1<- vCC 5113 fldd d0, [r2] @ d0<- vBB 5114 5115 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5116 fsubd d2, d0, d1 @ s2<- op 5117 GET_INST_OPCODE(ip) @ extract opcode from rINST 5118 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5119 fstd d2, [r9] @ vAA<- d2 5120 GOTO_OPCODE(ip) @ jump to next instruction 5121 5122 5123/* ------------------------------ */ 5124 .balign 64 5125.L_OP_MUL_DOUBLE: /* 0xad */ 5126/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5127/* File: arm-vfp/fbinopWide.S */ 5128 /* 5129 * Generic 64-bit double-precision floating point binary operation. 5130 * Provide an "instr" line that specifies an instruction that performs 5131 * "d2 = d0 op d1". 5132 * 5133 * for: add-double, sub-double, mul-double, div-double 5134 */ 5135 /* doubleop vAA, vBB, vCC */ 5136 FETCH(r0, 1) @ r0<- CCBB 5137 mov r9, rINST, lsr #8 @ r9<- AA 5138 mov r3, r0, lsr #8 @ r3<- CC 5139 and r2, r0, #255 @ r2<- BB 5140 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5141 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5142 fldd d1, [r3] @ d1<- vCC 5143 fldd d0, [r2] @ d0<- vBB 5144 5145 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5146 fmuld d2, d0, d1 @ s2<- op 5147 GET_INST_OPCODE(ip) @ extract opcode from rINST 5148 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5149 fstd d2, [r9] @ vAA<- d2 5150 GOTO_OPCODE(ip) @ jump to next instruction 5151 5152 5153/* ------------------------------ */ 5154 .balign 64 5155.L_OP_DIV_DOUBLE: /* 0xae */ 5156/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5157/* File: arm-vfp/fbinopWide.S */ 5158 /* 5159 * Generic 64-bit double-precision floating point binary operation. 5160 * Provide an "instr" line that specifies an instruction that performs 5161 * "d2 = d0 op d1". 5162 * 5163 * for: add-double, sub-double, mul-double, div-double 5164 */ 5165 /* doubleop vAA, vBB, vCC */ 5166 FETCH(r0, 1) @ r0<- CCBB 5167 mov r9, rINST, lsr #8 @ r9<- AA 5168 mov r3, r0, lsr #8 @ r3<- CC 5169 and r2, r0, #255 @ r2<- BB 5170 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5171 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5172 fldd d1, [r3] @ d1<- vCC 5173 fldd d0, [r2] @ d0<- vBB 5174 5175 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5176 fdivd d2, d0, d1 @ s2<- op 5177 GET_INST_OPCODE(ip) @ extract opcode from rINST 5178 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5179 fstd d2, [r9] @ vAA<- d2 5180 GOTO_OPCODE(ip) @ jump to next instruction 5181 5182 5183/* ------------------------------ */ 5184 .balign 64 5185.L_OP_REM_DOUBLE: /* 0xaf */ 5186/* File: armv5te/OP_REM_DOUBLE.S */ 5187/* EABI doesn't define a double remainder function, but libm does */ 5188/* File: armv5te/binopWide.S */ 5189 /* 5190 * Generic 64-bit binary operation. Provide an "instr" line that 5191 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5192 * This could be an ARM instruction or a function call. (If the result 5193 * comes back in a register other than r0, you can override "result".) 5194 * 5195 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5196 * vCC (r1). Useful for integer division and modulus. 5197 * 5198 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5199 * xor-long, add-double, sub-double, mul-double, div-double, 5200 * rem-double 5201 * 5202 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5203 */ 5204 /* binop vAA, vBB, vCC */ 5205 FETCH(r0, 1) @ r0<- CCBB 5206 mov r9, rINST, lsr #8 @ r9<- AA 5207 and r2, r0, #255 @ r2<- BB 5208 mov r3, r0, lsr #8 @ r3<- CC 5209 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5210 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5211 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5212 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5213 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5214 .if 0 5215 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5216 beq common_errDivideByZero 5217 .endif 5218 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5219 5220 @ optional op; may set condition codes 5221 bl fmod @ result<- op, r0-r3 changed 5222 GET_INST_OPCODE(ip) @ extract opcode from rINST 5223 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5224 GOTO_OPCODE(ip) @ jump to next instruction 5225 /* 14-17 instructions */ 5226 5227 5228/* ------------------------------ */ 5229 .balign 64 5230.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5231/* File: armv5te/OP_ADD_INT_2ADDR.S */ 5232/* File: armv5te/binop2addr.S */ 5233 /* 5234 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5235 * that specifies an instruction that performs "result = r0 op r1". 5236 * This could be an ARM instruction or a function call. (If the result 5237 * comes back in a register other than r0, you can override "result".) 5238 * 5239 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5240 * vCC (r1). Useful for integer division and modulus. 5241 * 5242 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5243 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5244 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5245 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5246 */ 5247 /* binop/2addr vA, vB */ 5248 mov r9, rINST, lsr #8 @ r9<- A+ 5249 mov r3, rINST, lsr #12 @ r3<- B 5250 and r9, r9, #15 5251 GET_VREG(r1, r3) @ r1<- vB 5252 GET_VREG(r0, r9) @ r0<- vA 5253 .if 0 5254 cmp r1, #0 @ is second operand zero? 5255 beq common_errDivideByZero 5256 .endif 5257 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5258 5259 @ optional op; may set condition codes 5260 add r0, r0, r1 @ r0<- op, r0-r3 changed 5261 GET_INST_OPCODE(ip) @ extract opcode from rINST 5262 SET_VREG(r0, r9) @ vAA<- r0 5263 GOTO_OPCODE(ip) @ jump to next instruction 5264 /* 10-13 instructions */ 5265 5266 5267/* ------------------------------ */ 5268 .balign 64 5269.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5270/* File: armv5te/OP_SUB_INT_2ADDR.S */ 5271/* File: armv5te/binop2addr.S */ 5272 /* 5273 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5274 * that specifies an instruction that performs "result = r0 op r1". 5275 * This could be an ARM instruction or a function call. (If the result 5276 * comes back in a register other than r0, you can override "result".) 5277 * 5278 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5279 * vCC (r1). Useful for integer division and modulus. 5280 * 5281 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5282 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5283 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5284 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5285 */ 5286 /* binop/2addr vA, vB */ 5287 mov r9, rINST, lsr #8 @ r9<- A+ 5288 mov r3, rINST, lsr #12 @ r3<- B 5289 and r9, r9, #15 5290 GET_VREG(r1, r3) @ r1<- vB 5291 GET_VREG(r0, r9) @ r0<- vA 5292 .if 0 5293 cmp r1, #0 @ is second operand zero? 5294 beq common_errDivideByZero 5295 .endif 5296 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5297 5298 @ optional op; may set condition codes 5299 sub r0, r0, r1 @ r0<- op, r0-r3 changed 5300 GET_INST_OPCODE(ip) @ extract opcode from rINST 5301 SET_VREG(r0, r9) @ vAA<- r0 5302 GOTO_OPCODE(ip) @ jump to next instruction 5303 /* 10-13 instructions */ 5304 5305 5306/* ------------------------------ */ 5307 .balign 64 5308.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5309/* File: armv5te/OP_MUL_INT_2ADDR.S */ 5310/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5311/* File: armv5te/binop2addr.S */ 5312 /* 5313 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5314 * that specifies an instruction that performs "result = r0 op r1". 5315 * This could be an ARM instruction or a function call. (If the result 5316 * comes back in a register other than r0, you can override "result".) 5317 * 5318 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5319 * vCC (r1). Useful for integer division and modulus. 5320 * 5321 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5322 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5323 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5324 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5325 */ 5326 /* binop/2addr vA, vB */ 5327 mov r9, rINST, lsr #8 @ r9<- A+ 5328 mov r3, rINST, lsr #12 @ r3<- B 5329 and r9, r9, #15 5330 GET_VREG(r1, r3) @ r1<- vB 5331 GET_VREG(r0, r9) @ r0<- vA 5332 .if 0 5333 cmp r1, #0 @ is second operand zero? 5334 beq common_errDivideByZero 5335 .endif 5336 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5337 5338 @ optional op; may set condition codes 5339 mul r0, r1, r0 @ r0<- op, r0-r3 changed 5340 GET_INST_OPCODE(ip) @ extract opcode from rINST 5341 SET_VREG(r0, r9) @ vAA<- r0 5342 GOTO_OPCODE(ip) @ jump to next instruction 5343 /* 10-13 instructions */ 5344 5345 5346/* ------------------------------ */ 5347 .balign 64 5348.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5349/* File: armv5te/OP_DIV_INT_2ADDR.S */ 5350/* File: armv5te/binop2addr.S */ 5351 /* 5352 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5353 * that specifies an instruction that performs "result = r0 op r1". 5354 * This could be an ARM instruction or a function call. (If the result 5355 * comes back in a register other than r0, you can override "result".) 5356 * 5357 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5358 * vCC (r1). Useful for integer division and modulus. 5359 * 5360 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5361 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5362 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5363 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5364 */ 5365 /* binop/2addr vA, vB */ 5366 mov r9, rINST, lsr #8 @ r9<- A+ 5367 mov r3, rINST, lsr #12 @ r3<- B 5368 and r9, r9, #15 5369 GET_VREG(r1, r3) @ r1<- vB 5370 GET_VREG(r0, r9) @ r0<- vA 5371 .if 1 5372 cmp r1, #0 @ is second operand zero? 5373 beq common_errDivideByZero 5374 .endif 5375 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5376 5377 @ optional op; may set condition codes 5378 bl __aeabi_idiv @ r0<- op, r0-r3 changed 5379 GET_INST_OPCODE(ip) @ extract opcode from rINST 5380 SET_VREG(r0, r9) @ vAA<- r0 5381 GOTO_OPCODE(ip) @ jump to next instruction 5382 /* 10-13 instructions */ 5383 5384 5385/* ------------------------------ */ 5386 .balign 64 5387.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5388/* File: armv5te/OP_REM_INT_2ADDR.S */ 5389/* idivmod returns quotient in r0 and remainder in r1 */ 5390/* File: armv5te/binop2addr.S */ 5391 /* 5392 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5393 * that specifies an instruction that performs "result = r0 op r1". 5394 * This could be an ARM instruction or a function call. (If the result 5395 * comes back in a register other than r0, you can override "result".) 5396 * 5397 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5398 * vCC (r1). Useful for integer division and modulus. 5399 * 5400 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5401 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5402 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5403 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5404 */ 5405 /* binop/2addr vA, vB */ 5406 mov r9, rINST, lsr #8 @ r9<- A+ 5407 mov r3, rINST, lsr #12 @ r3<- B 5408 and r9, r9, #15 5409 GET_VREG(r1, r3) @ r1<- vB 5410 GET_VREG(r0, r9) @ r0<- vA 5411 .if 1 5412 cmp r1, #0 @ is second operand zero? 5413 beq common_errDivideByZero 5414 .endif 5415 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5416 5417 @ optional op; may set condition codes 5418 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5419 GET_INST_OPCODE(ip) @ extract opcode from rINST 5420 SET_VREG(r1, r9) @ vAA<- r1 5421 GOTO_OPCODE(ip) @ jump to next instruction 5422 /* 10-13 instructions */ 5423 5424 5425/* ------------------------------ */ 5426 .balign 64 5427.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5428/* File: armv5te/OP_AND_INT_2ADDR.S */ 5429/* File: armv5te/binop2addr.S */ 5430 /* 5431 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5432 * that specifies an instruction that performs "result = r0 op r1". 5433 * This could be an ARM instruction or a function call. (If the result 5434 * comes back in a register other than r0, you can override "result".) 5435 * 5436 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5437 * vCC (r1). Useful for integer division and modulus. 5438 * 5439 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5440 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5441 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5442 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5443 */ 5444 /* binop/2addr vA, vB */ 5445 mov r9, rINST, lsr #8 @ r9<- A+ 5446 mov r3, rINST, lsr #12 @ r3<- B 5447 and r9, r9, #15 5448 GET_VREG(r1, r3) @ r1<- vB 5449 GET_VREG(r0, r9) @ r0<- vA 5450 .if 0 5451 cmp r1, #0 @ is second operand zero? 5452 beq common_errDivideByZero 5453 .endif 5454 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5455 5456 @ optional op; may set condition codes 5457 and r0, r0, r1 @ r0<- op, r0-r3 changed 5458 GET_INST_OPCODE(ip) @ extract opcode from rINST 5459 SET_VREG(r0, r9) @ vAA<- r0 5460 GOTO_OPCODE(ip) @ jump to next instruction 5461 /* 10-13 instructions */ 5462 5463 5464/* ------------------------------ */ 5465 .balign 64 5466.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5467/* File: armv5te/OP_OR_INT_2ADDR.S */ 5468/* File: armv5te/binop2addr.S */ 5469 /* 5470 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5471 * that specifies an instruction that performs "result = r0 op r1". 5472 * This could be an ARM instruction or a function call. (If the result 5473 * comes back in a register other than r0, you can override "result".) 5474 * 5475 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5476 * vCC (r1). Useful for integer division and modulus. 5477 * 5478 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5479 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5480 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5481 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5482 */ 5483 /* binop/2addr vA, vB */ 5484 mov r9, rINST, lsr #8 @ r9<- A+ 5485 mov r3, rINST, lsr #12 @ r3<- B 5486 and r9, r9, #15 5487 GET_VREG(r1, r3) @ r1<- vB 5488 GET_VREG(r0, r9) @ r0<- vA 5489 .if 0 5490 cmp r1, #0 @ is second operand zero? 5491 beq common_errDivideByZero 5492 .endif 5493 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5494 5495 @ optional op; may set condition codes 5496 orr r0, r0, r1 @ r0<- op, r0-r3 changed 5497 GET_INST_OPCODE(ip) @ extract opcode from rINST 5498 SET_VREG(r0, r9) @ vAA<- r0 5499 GOTO_OPCODE(ip) @ jump to next instruction 5500 /* 10-13 instructions */ 5501 5502 5503/* ------------------------------ */ 5504 .balign 64 5505.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5506/* File: armv5te/OP_XOR_INT_2ADDR.S */ 5507/* File: armv5te/binop2addr.S */ 5508 /* 5509 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5510 * that specifies an instruction that performs "result = r0 op r1". 5511 * This could be an ARM instruction or a function call. (If the result 5512 * comes back in a register other than r0, you can override "result".) 5513 * 5514 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5515 * vCC (r1). Useful for integer division and modulus. 5516 * 5517 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5518 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5519 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5520 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5521 */ 5522 /* binop/2addr vA, vB */ 5523 mov r9, rINST, lsr #8 @ r9<- A+ 5524 mov r3, rINST, lsr #12 @ r3<- B 5525 and r9, r9, #15 5526 GET_VREG(r1, r3) @ r1<- vB 5527 GET_VREG(r0, r9) @ r0<- vA 5528 .if 0 5529 cmp r1, #0 @ is second operand zero? 5530 beq common_errDivideByZero 5531 .endif 5532 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5533 5534 @ optional op; may set condition codes 5535 eor r0, r0, r1 @ r0<- op, r0-r3 changed 5536 GET_INST_OPCODE(ip) @ extract opcode from rINST 5537 SET_VREG(r0, r9) @ vAA<- r0 5538 GOTO_OPCODE(ip) @ jump to next instruction 5539 /* 10-13 instructions */ 5540 5541 5542/* ------------------------------ */ 5543 .balign 64 5544.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5545/* File: armv5te/OP_SHL_INT_2ADDR.S */ 5546/* File: armv5te/binop2addr.S */ 5547 /* 5548 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5549 * that specifies an instruction that performs "result = r0 op r1". 5550 * This could be an ARM instruction or a function call. (If the result 5551 * comes back in a register other than r0, you can override "result".) 5552 * 5553 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5554 * vCC (r1). Useful for integer division and modulus. 5555 * 5556 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5557 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5558 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5559 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5560 */ 5561 /* binop/2addr vA, vB */ 5562 mov r9, rINST, lsr #8 @ r9<- A+ 5563 mov r3, rINST, lsr #12 @ r3<- B 5564 and r9, r9, #15 5565 GET_VREG(r1, r3) @ r1<- vB 5566 GET_VREG(r0, r9) @ r0<- vA 5567 .if 0 5568 cmp r1, #0 @ is second operand zero? 5569 beq common_errDivideByZero 5570 .endif 5571 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5572 5573 and r1, r1, #31 @ optional op; may set condition codes 5574 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5575 GET_INST_OPCODE(ip) @ extract opcode from rINST 5576 SET_VREG(r0, r9) @ vAA<- r0 5577 GOTO_OPCODE(ip) @ jump to next instruction 5578 /* 10-13 instructions */ 5579 5580 5581/* ------------------------------ */ 5582 .balign 64 5583.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5584/* File: armv5te/OP_SHR_INT_2ADDR.S */ 5585/* File: armv5te/binop2addr.S */ 5586 /* 5587 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5588 * that specifies an instruction that performs "result = r0 op r1". 5589 * This could be an ARM instruction or a function call. (If the result 5590 * comes back in a register other than r0, you can override "result".) 5591 * 5592 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5593 * vCC (r1). Useful for integer division and modulus. 5594 * 5595 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5596 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5597 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5598 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5599 */ 5600 /* binop/2addr vA, vB */ 5601 mov r9, rINST, lsr #8 @ r9<- A+ 5602 mov r3, rINST, lsr #12 @ r3<- B 5603 and r9, r9, #15 5604 GET_VREG(r1, r3) @ r1<- vB 5605 GET_VREG(r0, r9) @ r0<- vA 5606 .if 0 5607 cmp r1, #0 @ is second operand zero? 5608 beq common_errDivideByZero 5609 .endif 5610 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5611 5612 and r1, r1, #31 @ optional op; may set condition codes 5613 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5614 GET_INST_OPCODE(ip) @ extract opcode from rINST 5615 SET_VREG(r0, r9) @ vAA<- r0 5616 GOTO_OPCODE(ip) @ jump to next instruction 5617 /* 10-13 instructions */ 5618 5619 5620/* ------------------------------ */ 5621 .balign 64 5622.L_OP_USHR_INT_2ADDR: /* 0xba */ 5623/* File: armv5te/OP_USHR_INT_2ADDR.S */ 5624/* File: armv5te/binop2addr.S */ 5625 /* 5626 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5627 * that specifies an instruction that performs "result = r0 op r1". 5628 * This could be an ARM instruction or a function call. (If the result 5629 * comes back in a register other than r0, you can override "result".) 5630 * 5631 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5632 * vCC (r1). Useful for integer division and modulus. 5633 * 5634 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5635 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5636 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5637 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5638 */ 5639 /* binop/2addr vA, vB */ 5640 mov r9, rINST, lsr #8 @ r9<- A+ 5641 mov r3, rINST, lsr #12 @ r3<- B 5642 and r9, r9, #15 5643 GET_VREG(r1, r3) @ r1<- vB 5644 GET_VREG(r0, r9) @ r0<- vA 5645 .if 0 5646 cmp r1, #0 @ is second operand zero? 5647 beq common_errDivideByZero 5648 .endif 5649 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5650 5651 and r1, r1, #31 @ optional op; may set condition codes 5652 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5653 GET_INST_OPCODE(ip) @ extract opcode from rINST 5654 SET_VREG(r0, r9) @ vAA<- r0 5655 GOTO_OPCODE(ip) @ jump to next instruction 5656 /* 10-13 instructions */ 5657 5658 5659/* ------------------------------ */ 5660 .balign 64 5661.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5662/* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5663/* File: armv5te/binopWide2addr.S */ 5664 /* 5665 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5666 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5667 * This could be an ARM instruction or a function call. (If the result 5668 * comes back in a register other than r0, you can override "result".) 5669 * 5670 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5671 * vCC (r1). Useful for integer division and modulus. 5672 * 5673 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5674 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5675 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5676 * rem-double/2addr 5677 */ 5678 /* binop/2addr vA, vB */ 5679 mov r9, rINST, lsr #8 @ r9<- A+ 5680 mov r1, rINST, lsr #12 @ r1<- B 5681 and r9, r9, #15 5682 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5683 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5684 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5685 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5686 .if 0 5687 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5688 beq common_errDivideByZero 5689 .endif 5690 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5691 5692 adds r0, r0, r2 @ optional op; may set condition codes 5693 adc r1, r1, r3 @ result<- op, r0-r3 changed 5694 GET_INST_OPCODE(ip) @ extract opcode from rINST 5695 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5696 GOTO_OPCODE(ip) @ jump to next instruction 5697 /* 12-15 instructions */ 5698 5699 5700/* ------------------------------ */ 5701 .balign 64 5702.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5703/* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5704/* File: armv5te/binopWide2addr.S */ 5705 /* 5706 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5707 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5708 * This could be an ARM instruction or a function call. (If the result 5709 * comes back in a register other than r0, you can override "result".) 5710 * 5711 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5712 * vCC (r1). Useful for integer division and modulus. 5713 * 5714 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5715 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5716 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5717 * rem-double/2addr 5718 */ 5719 /* binop/2addr vA, vB */ 5720 mov r9, rINST, lsr #8 @ r9<- A+ 5721 mov r1, rINST, lsr #12 @ r1<- B 5722 and r9, r9, #15 5723 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5724 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5725 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5726 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5727 .if 0 5728 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5729 beq common_errDivideByZero 5730 .endif 5731 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5732 5733 subs r0, r0, r2 @ optional op; may set condition codes 5734 sbc r1, r1, r3 @ result<- op, r0-r3 changed 5735 GET_INST_OPCODE(ip) @ extract opcode from rINST 5736 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5737 GOTO_OPCODE(ip) @ jump to next instruction 5738 /* 12-15 instructions */ 5739 5740 5741/* ------------------------------ */ 5742 .balign 64 5743.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5744/* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5745 /* 5746 * Signed 64-bit integer multiply, "/2addr" version. 5747 * 5748 * See OP_MUL_LONG for an explanation. 5749 * 5750 * We get a little tight on registers, so to avoid looking up &fp[A] 5751 * again we stuff it into rINST. 5752 */ 5753 /* mul-long/2addr vA, vB */ 5754 mov r9, rINST, lsr #8 @ r9<- A+ 5755 mov r1, rINST, lsr #12 @ r1<- B 5756 and r9, r9, #15 5757 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5758 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5759 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5760 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5761 mul ip, r2, r1 @ ip<- ZxW 5762 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5763 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5764 mov r0, rINST @ r0<- &fp[A] (free up rINST) 5765 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5766 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5767 GET_INST_OPCODE(ip) @ extract opcode from rINST 5768 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5769 GOTO_OPCODE(ip) @ jump to next instruction 5770 5771/* ------------------------------ */ 5772 .balign 64 5773.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5774/* File: armv5te/OP_DIV_LONG_2ADDR.S */ 5775/* File: armv5te/binopWide2addr.S */ 5776 /* 5777 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5778 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5779 * This could be an ARM instruction or a function call. (If the result 5780 * comes back in a register other than r0, you can override "result".) 5781 * 5782 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5783 * vCC (r1). Useful for integer division and modulus. 5784 * 5785 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5786 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5787 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5788 * rem-double/2addr 5789 */ 5790 /* binop/2addr vA, vB */ 5791 mov r9, rINST, lsr #8 @ r9<- A+ 5792 mov r1, rINST, lsr #12 @ r1<- B 5793 and r9, r9, #15 5794 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5795 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5796 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5797 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5798 .if 1 5799 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5800 beq common_errDivideByZero 5801 .endif 5802 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5803 5804 @ optional op; may set condition codes 5805 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5806 GET_INST_OPCODE(ip) @ extract opcode from rINST 5807 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5808 GOTO_OPCODE(ip) @ jump to next instruction 5809 /* 12-15 instructions */ 5810 5811 5812/* ------------------------------ */ 5813 .balign 64 5814.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5815/* File: armv5te/OP_REM_LONG_2ADDR.S */ 5816/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5817/* File: armv5te/binopWide2addr.S */ 5818 /* 5819 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5820 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5821 * This could be an ARM instruction or a function call. (If the result 5822 * comes back in a register other than r0, you can override "result".) 5823 * 5824 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5825 * vCC (r1). Useful for integer division and modulus. 5826 * 5827 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5828 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5829 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5830 * rem-double/2addr 5831 */ 5832 /* binop/2addr vA, vB */ 5833 mov r9, rINST, lsr #8 @ r9<- A+ 5834 mov r1, rINST, lsr #12 @ r1<- B 5835 and r9, r9, #15 5836 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5837 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5838 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5839 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5840 .if 1 5841 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5842 beq common_errDivideByZero 5843 .endif 5844 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5845 5846 @ optional op; may set condition codes 5847 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5848 GET_INST_OPCODE(ip) @ extract opcode from rINST 5849 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5850 GOTO_OPCODE(ip) @ jump to next instruction 5851 /* 12-15 instructions */ 5852 5853 5854/* ------------------------------ */ 5855 .balign 64 5856.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5857/* File: armv5te/OP_AND_LONG_2ADDR.S */ 5858/* File: armv5te/binopWide2addr.S */ 5859 /* 5860 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5861 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5862 * This could be an ARM instruction or a function call. (If the result 5863 * comes back in a register other than r0, you can override "result".) 5864 * 5865 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5866 * vCC (r1). Useful for integer division and modulus. 5867 * 5868 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5869 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5870 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5871 * rem-double/2addr 5872 */ 5873 /* binop/2addr vA, vB */ 5874 mov r9, rINST, lsr #8 @ r9<- A+ 5875 mov r1, rINST, lsr #12 @ r1<- B 5876 and r9, r9, #15 5877 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5878 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5879 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5880 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5881 .if 0 5882 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5883 beq common_errDivideByZero 5884 .endif 5885 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5886 5887 and r0, r0, r2 @ optional op; may set condition codes 5888 and r1, r1, r3 @ result<- op, r0-r3 changed 5889 GET_INST_OPCODE(ip) @ extract opcode from rINST 5890 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5891 GOTO_OPCODE(ip) @ jump to next instruction 5892 /* 12-15 instructions */ 5893 5894 5895/* ------------------------------ */ 5896 .balign 64 5897.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5898/* File: armv5te/OP_OR_LONG_2ADDR.S */ 5899/* File: armv5te/binopWide2addr.S */ 5900 /* 5901 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5902 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5903 * This could be an ARM instruction or a function call. (If the result 5904 * comes back in a register other than r0, you can override "result".) 5905 * 5906 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5907 * vCC (r1). Useful for integer division and modulus. 5908 * 5909 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5910 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5911 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5912 * rem-double/2addr 5913 */ 5914 /* binop/2addr vA, vB */ 5915 mov r9, rINST, lsr #8 @ r9<- A+ 5916 mov r1, rINST, lsr #12 @ r1<- B 5917 and r9, r9, #15 5918 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5919 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5920 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5921 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5922 .if 0 5923 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5924 beq common_errDivideByZero 5925 .endif 5926 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5927 5928 orr r0, r0, r2 @ optional op; may set condition codes 5929 orr r1, r1, r3 @ result<- op, r0-r3 changed 5930 GET_INST_OPCODE(ip) @ extract opcode from rINST 5931 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5932 GOTO_OPCODE(ip) @ jump to next instruction 5933 /* 12-15 instructions */ 5934 5935 5936/* ------------------------------ */ 5937 .balign 64 5938.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5939/* File: armv5te/OP_XOR_LONG_2ADDR.S */ 5940/* File: armv5te/binopWide2addr.S */ 5941 /* 5942 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5943 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5944 * This could be an ARM instruction or a function call. (If the result 5945 * comes back in a register other than r0, you can override "result".) 5946 * 5947 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5948 * vCC (r1). Useful for integer division and modulus. 5949 * 5950 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5951 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5952 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5953 * rem-double/2addr 5954 */ 5955 /* binop/2addr vA, vB */ 5956 mov r9, rINST, lsr #8 @ r9<- A+ 5957 mov r1, rINST, lsr #12 @ r1<- B 5958 and r9, r9, #15 5959 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5960 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5961 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5962 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5963 .if 0 5964 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5965 beq common_errDivideByZero 5966 .endif 5967 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5968 5969 eor r0, r0, r2 @ optional op; may set condition codes 5970 eor r1, r1, r3 @ result<- op, r0-r3 changed 5971 GET_INST_OPCODE(ip) @ extract opcode from rINST 5972 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5973 GOTO_OPCODE(ip) @ jump to next instruction 5974 /* 12-15 instructions */ 5975 5976 5977/* ------------------------------ */ 5978 .balign 64 5979.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 5980/* File: armv5te/OP_SHL_LONG_2ADDR.S */ 5981 /* 5982 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5983 * 32-bit shift distance. 5984 */ 5985 /* shl-long/2addr vA, vB */ 5986 mov r9, rINST, lsr #8 @ r9<- A+ 5987 mov r3, rINST, lsr #12 @ r3<- B 5988 and r9, r9, #15 5989 GET_VREG(r2, r3) @ r2<- vB 5990 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5991 and r2, r2, #63 @ r2<- r2 & 0x3f 5992 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5993 5994 mov r1, r1, asl r2 @ r1<- r1 << r2 5995 rsb r3, r2, #32 @ r3<- 32 - r2 5996 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 5997 subs ip, r2, #32 @ ip<- r2 - 32 5998 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5999 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6000 mov r0, r0, asl r2 @ r0<- r0 << r2 6001 b .LOP_SHL_LONG_2ADDR_finish 6002 6003/* ------------------------------ */ 6004 .balign 64 6005.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6006/* File: armv5te/OP_SHR_LONG_2ADDR.S */ 6007 /* 6008 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6009 * 32-bit shift distance. 6010 */ 6011 /* shr-long/2addr vA, vB */ 6012 mov r9, rINST, lsr #8 @ r9<- A+ 6013 mov r3, rINST, lsr #12 @ r3<- B 6014 and r9, r9, #15 6015 GET_VREG(r2, r3) @ r2<- vB 6016 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6017 and r2, r2, #63 @ r2<- r2 & 0x3f 6018 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6019 6020 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6021 rsb r3, r2, #32 @ r3<- 32 - r2 6022 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6023 subs ip, r2, #32 @ ip<- r2 - 32 6024 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6025 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6026 mov r1, r1, asr r2 @ r1<- r1 >> r2 6027 b .LOP_SHR_LONG_2ADDR_finish 6028 6029/* ------------------------------ */ 6030 .balign 64 6031.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6032/* File: armv5te/OP_USHR_LONG_2ADDR.S */ 6033 /* 6034 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6035 * 32-bit shift distance. 6036 */ 6037 /* ushr-long/2addr vA, vB */ 6038 mov r9, rINST, lsr #8 @ r9<- A+ 6039 mov r3, rINST, lsr #12 @ r3<- B 6040 and r9, r9, #15 6041 GET_VREG(r2, r3) @ r2<- vB 6042 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6043 and r2, r2, #63 @ r2<- r2 & 0x3f 6044 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6045 6046 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6047 rsb r3, r2, #32 @ r3<- 32 - r2 6048 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6049 subs ip, r2, #32 @ ip<- r2 - 32 6050 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6051 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6052 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6053 b .LOP_USHR_LONG_2ADDR_finish 6054 6055/* ------------------------------ */ 6056 .balign 64 6057.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6058/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6059/* File: arm-vfp/fbinop2addr.S */ 6060 /* 6061 * Generic 32-bit floating point "/2addr" binary operation. Provide 6062 * an "instr" line that specifies an instruction that performs 6063 * "s2 = s0 op s1". 6064 * 6065 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6066 */ 6067 /* binop/2addr vA, vB */ 6068 mov r3, rINST, lsr #12 @ r3<- B 6069 mov r9, rINST, lsr #8 @ r9<- A+ 6070 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6071 and r9, r9, #15 @ r9<- A 6072 flds s1, [r3] @ s1<- vB 6073 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6074 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6075 flds s0, [r9] @ s0<- vA 6076 6077 fadds s2, s0, s1 @ s2<- op 6078 GET_INST_OPCODE(ip) @ extract opcode from rINST 6079 fsts s2, [r9] @ vAA<- s2 6080 GOTO_OPCODE(ip) @ jump to next instruction 6081 6082 6083/* ------------------------------ */ 6084 .balign 64 6085.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6086/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6087/* File: arm-vfp/fbinop2addr.S */ 6088 /* 6089 * Generic 32-bit floating point "/2addr" binary operation. Provide 6090 * an "instr" line that specifies an instruction that performs 6091 * "s2 = s0 op s1". 6092 * 6093 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6094 */ 6095 /* binop/2addr vA, vB */ 6096 mov r3, rINST, lsr #12 @ r3<- B 6097 mov r9, rINST, lsr #8 @ r9<- A+ 6098 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6099 and r9, r9, #15 @ r9<- A 6100 flds s1, [r3] @ s1<- vB 6101 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6102 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6103 flds s0, [r9] @ s0<- vA 6104 6105 fsubs s2, s0, s1 @ s2<- op 6106 GET_INST_OPCODE(ip) @ extract opcode from rINST 6107 fsts s2, [r9] @ vAA<- s2 6108 GOTO_OPCODE(ip) @ jump to next instruction 6109 6110 6111/* ------------------------------ */ 6112 .balign 64 6113.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6114/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6115/* File: arm-vfp/fbinop2addr.S */ 6116 /* 6117 * Generic 32-bit floating point "/2addr" binary operation. Provide 6118 * an "instr" line that specifies an instruction that performs 6119 * "s2 = s0 op s1". 6120 * 6121 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6122 */ 6123 /* binop/2addr vA, vB */ 6124 mov r3, rINST, lsr #12 @ r3<- B 6125 mov r9, rINST, lsr #8 @ r9<- A+ 6126 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6127 and r9, r9, #15 @ r9<- A 6128 flds s1, [r3] @ s1<- vB 6129 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6130 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6131 flds s0, [r9] @ s0<- vA 6132 6133 fmuls s2, s0, s1 @ s2<- op 6134 GET_INST_OPCODE(ip) @ extract opcode from rINST 6135 fsts s2, [r9] @ vAA<- s2 6136 GOTO_OPCODE(ip) @ jump to next instruction 6137 6138 6139/* ------------------------------ */ 6140 .balign 64 6141.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6142/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6143/* File: arm-vfp/fbinop2addr.S */ 6144 /* 6145 * Generic 32-bit floating point "/2addr" binary operation. Provide 6146 * an "instr" line that specifies an instruction that performs 6147 * "s2 = s0 op s1". 6148 * 6149 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6150 */ 6151 /* binop/2addr vA, vB */ 6152 mov r3, rINST, lsr #12 @ r3<- B 6153 mov r9, rINST, lsr #8 @ r9<- A+ 6154 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6155 and r9, r9, #15 @ r9<- A 6156 flds s1, [r3] @ s1<- vB 6157 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6158 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6159 flds s0, [r9] @ s0<- vA 6160 6161 fdivs s2, s0, s1 @ s2<- op 6162 GET_INST_OPCODE(ip) @ extract opcode from rINST 6163 fsts s2, [r9] @ vAA<- s2 6164 GOTO_OPCODE(ip) @ jump to next instruction 6165 6166 6167/* ------------------------------ */ 6168 .balign 64 6169.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6170/* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6171/* EABI doesn't define a float remainder function, but libm does */ 6172/* File: armv5te/binop2addr.S */ 6173 /* 6174 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6175 * that specifies an instruction that performs "result = r0 op r1". 6176 * This could be an ARM instruction or a function call. (If the result 6177 * comes back in a register other than r0, you can override "result".) 6178 * 6179 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6180 * vCC (r1). Useful for integer division and modulus. 6181 * 6182 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6183 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6184 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6185 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6186 */ 6187 /* binop/2addr vA, vB */ 6188 mov r9, rINST, lsr #8 @ r9<- A+ 6189 mov r3, rINST, lsr #12 @ r3<- B 6190 and r9, r9, #15 6191 GET_VREG(r1, r3) @ r1<- vB 6192 GET_VREG(r0, r9) @ r0<- vA 6193 .if 0 6194 cmp r1, #0 @ is second operand zero? 6195 beq common_errDivideByZero 6196 .endif 6197 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6198 6199 @ optional op; may set condition codes 6200 bl fmodf @ r0<- op, r0-r3 changed 6201 GET_INST_OPCODE(ip) @ extract opcode from rINST 6202 SET_VREG(r0, r9) @ vAA<- r0 6203 GOTO_OPCODE(ip) @ jump to next instruction 6204 /* 10-13 instructions */ 6205 6206 6207/* ------------------------------ */ 6208 .balign 64 6209.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6210/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6211/* File: arm-vfp/fbinopWide2addr.S */ 6212 /* 6213 * Generic 64-bit floating point "/2addr" binary operation. Provide 6214 * an "instr" line that specifies an instruction that performs 6215 * "d2 = d0 op d1". 6216 * 6217 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6218 * div-double/2addr 6219 */ 6220 /* binop/2addr vA, vB */ 6221 mov r3, rINST, lsr #12 @ r3<- B 6222 mov r9, rINST, lsr #8 @ r9<- A+ 6223 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6224 and r9, r9, #15 @ r9<- A 6225 fldd d1, [r3] @ d1<- vB 6226 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6227 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6228 fldd d0, [r9] @ d0<- vA 6229 6230 faddd d2, d0, d1 @ d2<- op 6231 GET_INST_OPCODE(ip) @ extract opcode from rINST 6232 fstd d2, [r9] @ vAA<- d2 6233 GOTO_OPCODE(ip) @ jump to next instruction 6234 6235 6236/* ------------------------------ */ 6237 .balign 64 6238.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6239/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6240/* File: arm-vfp/fbinopWide2addr.S */ 6241 /* 6242 * Generic 64-bit floating point "/2addr" binary operation. Provide 6243 * an "instr" line that specifies an instruction that performs 6244 * "d2 = d0 op d1". 6245 * 6246 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6247 * div-double/2addr 6248 */ 6249 /* binop/2addr vA, vB */ 6250 mov r3, rINST, lsr #12 @ r3<- B 6251 mov r9, rINST, lsr #8 @ r9<- A+ 6252 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6253 and r9, r9, #15 @ r9<- A 6254 fldd d1, [r3] @ d1<- vB 6255 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6256 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6257 fldd d0, [r9] @ d0<- vA 6258 6259 fsubd d2, d0, d1 @ d2<- op 6260 GET_INST_OPCODE(ip) @ extract opcode from rINST 6261 fstd d2, [r9] @ vAA<- d2 6262 GOTO_OPCODE(ip) @ jump to next instruction 6263 6264 6265/* ------------------------------ */ 6266 .balign 64 6267.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6268/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6269/* File: arm-vfp/fbinopWide2addr.S */ 6270 /* 6271 * Generic 64-bit floating point "/2addr" binary operation. Provide 6272 * an "instr" line that specifies an instruction that performs 6273 * "d2 = d0 op d1". 6274 * 6275 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6276 * div-double/2addr 6277 */ 6278 /* binop/2addr vA, vB */ 6279 mov r3, rINST, lsr #12 @ r3<- B 6280 mov r9, rINST, lsr #8 @ r9<- A+ 6281 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6282 and r9, r9, #15 @ r9<- A 6283 fldd d1, [r3] @ d1<- vB 6284 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6285 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6286 fldd d0, [r9] @ d0<- vA 6287 6288 fmuld d2, d0, d1 @ d2<- op 6289 GET_INST_OPCODE(ip) @ extract opcode from rINST 6290 fstd d2, [r9] @ vAA<- d2 6291 GOTO_OPCODE(ip) @ jump to next instruction 6292 6293 6294/* ------------------------------ */ 6295 .balign 64 6296.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6297/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6298/* File: arm-vfp/fbinopWide2addr.S */ 6299 /* 6300 * Generic 64-bit floating point "/2addr" binary operation. Provide 6301 * an "instr" line that specifies an instruction that performs 6302 * "d2 = d0 op d1". 6303 * 6304 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6305 * div-double/2addr 6306 */ 6307 /* binop/2addr vA, vB */ 6308 mov r3, rINST, lsr #12 @ r3<- B 6309 mov r9, rINST, lsr #8 @ r9<- A+ 6310 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6311 and r9, r9, #15 @ r9<- A 6312 fldd d1, [r3] @ d1<- vB 6313 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6314 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6315 fldd d0, [r9] @ d0<- vA 6316 6317 fdivd d2, d0, d1 @ d2<- op 6318 GET_INST_OPCODE(ip) @ extract opcode from rINST 6319 fstd d2, [r9] @ vAA<- d2 6320 GOTO_OPCODE(ip) @ jump to next instruction 6321 6322 6323/* ------------------------------ */ 6324 .balign 64 6325.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6326/* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6327/* EABI doesn't define a double remainder function, but libm does */ 6328/* File: armv5te/binopWide2addr.S */ 6329 /* 6330 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6331 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6332 * This could be an ARM instruction or a function call. (If the result 6333 * comes back in a register other than r0, you can override "result".) 6334 * 6335 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6336 * vCC (r1). Useful for integer division and modulus. 6337 * 6338 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6339 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6340 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6341 * rem-double/2addr 6342 */ 6343 /* binop/2addr vA, vB */ 6344 mov r9, rINST, lsr #8 @ r9<- A+ 6345 mov r1, rINST, lsr #12 @ r1<- B 6346 and r9, r9, #15 6347 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6348 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6349 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6350 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6351 .if 0 6352 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6353 beq common_errDivideByZero 6354 .endif 6355 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6356 6357 @ optional op; may set condition codes 6358 bl fmod @ result<- op, r0-r3 changed 6359 GET_INST_OPCODE(ip) @ extract opcode from rINST 6360 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6361 GOTO_OPCODE(ip) @ jump to next instruction 6362 /* 12-15 instructions */ 6363 6364 6365/* ------------------------------ */ 6366 .balign 64 6367.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6368/* File: armv5te/OP_ADD_INT_LIT16.S */ 6369/* File: armv5te/binopLit16.S */ 6370 /* 6371 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6372 * that specifies an instruction that performs "result = r0 op r1". 6373 * This could be an ARM instruction or a function call. (If the result 6374 * comes back in a register other than r0, you can override "result".) 6375 * 6376 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6377 * vCC (r1). Useful for integer division and modulus. 6378 * 6379 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6380 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6381 */ 6382 /* binop/lit16 vA, vB, #+CCCC */ 6383 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6384 mov r2, rINST, lsr #12 @ r2<- B 6385 mov r9, rINST, lsr #8 @ r9<- A+ 6386 GET_VREG(r0, r2) @ r0<- vB 6387 and r9, r9, #15 6388 .if 0 6389 cmp r1, #0 @ is second operand zero? 6390 beq common_errDivideByZero 6391 .endif 6392 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6393 6394 add r0, r0, r1 @ r0<- op, r0-r3 changed 6395 GET_INST_OPCODE(ip) @ extract opcode from rINST 6396 SET_VREG(r0, r9) @ vAA<- r0 6397 GOTO_OPCODE(ip) @ jump to next instruction 6398 /* 10-13 instructions */ 6399 6400 6401/* ------------------------------ */ 6402 .balign 64 6403.L_OP_RSUB_INT: /* 0xd1 */ 6404/* File: armv5te/OP_RSUB_INT.S */ 6405/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6406/* File: armv5te/binopLit16.S */ 6407 /* 6408 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6409 * that specifies an instruction that performs "result = r0 op r1". 6410 * This could be an ARM instruction or a function call. (If the result 6411 * comes back in a register other than r0, you can override "result".) 6412 * 6413 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6414 * vCC (r1). Useful for integer division and modulus. 6415 * 6416 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6417 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6418 */ 6419 /* binop/lit16 vA, vB, #+CCCC */ 6420 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6421 mov r2, rINST, lsr #12 @ r2<- B 6422 mov r9, rINST, lsr #8 @ r9<- A+ 6423 GET_VREG(r0, r2) @ r0<- vB 6424 and r9, r9, #15 6425 .if 0 6426 cmp r1, #0 @ is second operand zero? 6427 beq common_errDivideByZero 6428 .endif 6429 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6430 6431 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6432 GET_INST_OPCODE(ip) @ extract opcode from rINST 6433 SET_VREG(r0, r9) @ vAA<- r0 6434 GOTO_OPCODE(ip) @ jump to next instruction 6435 /* 10-13 instructions */ 6436 6437 6438/* ------------------------------ */ 6439 .balign 64 6440.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6441/* File: armv5te/OP_MUL_INT_LIT16.S */ 6442/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6443/* File: armv5te/binopLit16.S */ 6444 /* 6445 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6446 * that specifies an instruction that performs "result = r0 op r1". 6447 * This could be an ARM instruction or a function call. (If the result 6448 * comes back in a register other than r0, you can override "result".) 6449 * 6450 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6451 * vCC (r1). Useful for integer division and modulus. 6452 * 6453 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6454 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6455 */ 6456 /* binop/lit16 vA, vB, #+CCCC */ 6457 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6458 mov r2, rINST, lsr #12 @ r2<- B 6459 mov r9, rINST, lsr #8 @ r9<- A+ 6460 GET_VREG(r0, r2) @ r0<- vB 6461 and r9, r9, #15 6462 .if 0 6463 cmp r1, #0 @ is second operand zero? 6464 beq common_errDivideByZero 6465 .endif 6466 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6467 6468 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6469 GET_INST_OPCODE(ip) @ extract opcode from rINST 6470 SET_VREG(r0, r9) @ vAA<- r0 6471 GOTO_OPCODE(ip) @ jump to next instruction 6472 /* 10-13 instructions */ 6473 6474 6475/* ------------------------------ */ 6476 .balign 64 6477.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6478/* File: armv5te/OP_DIV_INT_LIT16.S */ 6479/* File: armv5te/binopLit16.S */ 6480 /* 6481 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6482 * that specifies an instruction that performs "result = r0 op r1". 6483 * This could be an ARM instruction or a function call. (If the result 6484 * comes back in a register other than r0, you can override "result".) 6485 * 6486 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6487 * vCC (r1). Useful for integer division and modulus. 6488 * 6489 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6490 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6491 */ 6492 /* binop/lit16 vA, vB, #+CCCC */ 6493 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6494 mov r2, rINST, lsr #12 @ r2<- B 6495 mov r9, rINST, lsr #8 @ r9<- A+ 6496 GET_VREG(r0, r2) @ r0<- vB 6497 and r9, r9, #15 6498 .if 1 6499 cmp r1, #0 @ is second operand zero? 6500 beq common_errDivideByZero 6501 .endif 6502 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6503 6504 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6505 GET_INST_OPCODE(ip) @ extract opcode from rINST 6506 SET_VREG(r0, r9) @ vAA<- r0 6507 GOTO_OPCODE(ip) @ jump to next instruction 6508 /* 10-13 instructions */ 6509 6510 6511/* ------------------------------ */ 6512 .balign 64 6513.L_OP_REM_INT_LIT16: /* 0xd4 */ 6514/* File: armv5te/OP_REM_INT_LIT16.S */ 6515/* idivmod returns quotient in r0 and remainder in r1 */ 6516/* File: armv5te/binopLit16.S */ 6517 /* 6518 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6519 * that specifies an instruction that performs "result = r0 op r1". 6520 * This could be an ARM instruction or a function call. (If the result 6521 * comes back in a register other than r0, you can override "result".) 6522 * 6523 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6524 * vCC (r1). Useful for integer division and modulus. 6525 * 6526 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6527 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6528 */ 6529 /* binop/lit16 vA, vB, #+CCCC */ 6530 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6531 mov r2, rINST, lsr #12 @ r2<- B 6532 mov r9, rINST, lsr #8 @ r9<- A+ 6533 GET_VREG(r0, r2) @ r0<- vB 6534 and r9, r9, #15 6535 .if 1 6536 cmp r1, #0 @ is second operand zero? 6537 beq common_errDivideByZero 6538 .endif 6539 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6540 6541 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6542 GET_INST_OPCODE(ip) @ extract opcode from rINST 6543 SET_VREG(r1, r9) @ vAA<- r1 6544 GOTO_OPCODE(ip) @ jump to next instruction 6545 /* 10-13 instructions */ 6546 6547 6548/* ------------------------------ */ 6549 .balign 64 6550.L_OP_AND_INT_LIT16: /* 0xd5 */ 6551/* File: armv5te/OP_AND_INT_LIT16.S */ 6552/* File: armv5te/binopLit16.S */ 6553 /* 6554 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6555 * that specifies an instruction that performs "result = r0 op r1". 6556 * This could be an ARM instruction or a function call. (If the result 6557 * comes back in a register other than r0, you can override "result".) 6558 * 6559 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6560 * vCC (r1). Useful for integer division and modulus. 6561 * 6562 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6563 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6564 */ 6565 /* binop/lit16 vA, vB, #+CCCC */ 6566 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6567 mov r2, rINST, lsr #12 @ r2<- B 6568 mov r9, rINST, lsr #8 @ r9<- A+ 6569 GET_VREG(r0, r2) @ r0<- vB 6570 and r9, r9, #15 6571 .if 0 6572 cmp r1, #0 @ is second operand zero? 6573 beq common_errDivideByZero 6574 .endif 6575 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6576 6577 and r0, r0, r1 @ r0<- op, r0-r3 changed 6578 GET_INST_OPCODE(ip) @ extract opcode from rINST 6579 SET_VREG(r0, r9) @ vAA<- r0 6580 GOTO_OPCODE(ip) @ jump to next instruction 6581 /* 10-13 instructions */ 6582 6583 6584/* ------------------------------ */ 6585 .balign 64 6586.L_OP_OR_INT_LIT16: /* 0xd6 */ 6587/* File: armv5te/OP_OR_INT_LIT16.S */ 6588/* File: armv5te/binopLit16.S */ 6589 /* 6590 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6591 * that specifies an instruction that performs "result = r0 op r1". 6592 * This could be an ARM instruction or a function call. (If the result 6593 * comes back in a register other than r0, you can override "result".) 6594 * 6595 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6596 * vCC (r1). Useful for integer division and modulus. 6597 * 6598 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6599 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6600 */ 6601 /* binop/lit16 vA, vB, #+CCCC */ 6602 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6603 mov r2, rINST, lsr #12 @ r2<- B 6604 mov r9, rINST, lsr #8 @ r9<- A+ 6605 GET_VREG(r0, r2) @ r0<- vB 6606 and r9, r9, #15 6607 .if 0 6608 cmp r1, #0 @ is second operand zero? 6609 beq common_errDivideByZero 6610 .endif 6611 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6612 6613 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6614 GET_INST_OPCODE(ip) @ extract opcode from rINST 6615 SET_VREG(r0, r9) @ vAA<- r0 6616 GOTO_OPCODE(ip) @ jump to next instruction 6617 /* 10-13 instructions */ 6618 6619 6620/* ------------------------------ */ 6621 .balign 64 6622.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6623/* File: armv5te/OP_XOR_INT_LIT16.S */ 6624/* File: armv5te/binopLit16.S */ 6625 /* 6626 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6627 * that specifies an instruction that performs "result = r0 op r1". 6628 * This could be an ARM instruction or a function call. (If the result 6629 * comes back in a register other than r0, you can override "result".) 6630 * 6631 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6632 * vCC (r1). Useful for integer division and modulus. 6633 * 6634 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6635 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6636 */ 6637 /* binop/lit16 vA, vB, #+CCCC */ 6638 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6639 mov r2, rINST, lsr #12 @ r2<- B 6640 mov r9, rINST, lsr #8 @ r9<- A+ 6641 GET_VREG(r0, r2) @ r0<- vB 6642 and r9, r9, #15 6643 .if 0 6644 cmp r1, #0 @ is second operand zero? 6645 beq common_errDivideByZero 6646 .endif 6647 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6648 6649 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6650 GET_INST_OPCODE(ip) @ extract opcode from rINST 6651 SET_VREG(r0, r9) @ vAA<- r0 6652 GOTO_OPCODE(ip) @ jump to next instruction 6653 /* 10-13 instructions */ 6654 6655 6656/* ------------------------------ */ 6657 .balign 64 6658.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6659/* File: armv5te/OP_ADD_INT_LIT8.S */ 6660/* File: armv5te/binopLit8.S */ 6661 /* 6662 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6663 * that specifies an instruction that performs "result = r0 op r1". 6664 * This could be an ARM instruction or a function call. (If the result 6665 * comes back in a register other than r0, you can override "result".) 6666 * 6667 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6668 * vCC (r1). Useful for integer division and modulus. 6669 * 6670 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6671 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6672 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6673 */ 6674 /* binop/lit8 vAA, vBB, #+CC */ 6675 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6676 mov r9, rINST, lsr #8 @ r9<- AA 6677 and r2, r3, #255 @ r2<- BB 6678 GET_VREG(r0, r2) @ r0<- vBB 6679 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6680 .if 0 6681 @cmp r1, #0 @ is second operand zero? 6682 beq common_errDivideByZero 6683 .endif 6684 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6685 6686 @ optional op; may set condition codes 6687 add r0, r0, r1 @ r0<- op, r0-r3 changed 6688 GET_INST_OPCODE(ip) @ extract opcode from rINST 6689 SET_VREG(r0, r9) @ vAA<- r0 6690 GOTO_OPCODE(ip) @ jump to next instruction 6691 /* 10-12 instructions */ 6692 6693 6694/* ------------------------------ */ 6695 .balign 64 6696.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6697/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6698/* File: armv5te/binopLit8.S */ 6699 /* 6700 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6701 * that specifies an instruction that performs "result = r0 op r1". 6702 * This could be an ARM instruction or a function call. (If the result 6703 * comes back in a register other than r0, you can override "result".) 6704 * 6705 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6706 * vCC (r1). Useful for integer division and modulus. 6707 * 6708 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6709 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6710 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6711 */ 6712 /* binop/lit8 vAA, vBB, #+CC */ 6713 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6714 mov r9, rINST, lsr #8 @ r9<- AA 6715 and r2, r3, #255 @ r2<- BB 6716 GET_VREG(r0, r2) @ r0<- vBB 6717 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6718 .if 0 6719 @cmp r1, #0 @ is second operand zero? 6720 beq common_errDivideByZero 6721 .endif 6722 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6723 6724 @ optional op; may set condition codes 6725 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6726 GET_INST_OPCODE(ip) @ extract opcode from rINST 6727 SET_VREG(r0, r9) @ vAA<- r0 6728 GOTO_OPCODE(ip) @ jump to next instruction 6729 /* 10-12 instructions */ 6730 6731 6732/* ------------------------------ */ 6733 .balign 64 6734.L_OP_MUL_INT_LIT8: /* 0xda */ 6735/* File: armv5te/OP_MUL_INT_LIT8.S */ 6736/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6737/* File: armv5te/binopLit8.S */ 6738 /* 6739 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6740 * that specifies an instruction that performs "result = r0 op r1". 6741 * This could be an ARM instruction or a function call. (If the result 6742 * comes back in a register other than r0, you can override "result".) 6743 * 6744 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6745 * vCC (r1). Useful for integer division and modulus. 6746 * 6747 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6748 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6749 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6750 */ 6751 /* binop/lit8 vAA, vBB, #+CC */ 6752 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6753 mov r9, rINST, lsr #8 @ r9<- AA 6754 and r2, r3, #255 @ r2<- BB 6755 GET_VREG(r0, r2) @ r0<- vBB 6756 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6757 .if 0 6758 @cmp r1, #0 @ is second operand zero? 6759 beq common_errDivideByZero 6760 .endif 6761 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6762 6763 @ optional op; may set condition codes 6764 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6765 GET_INST_OPCODE(ip) @ extract opcode from rINST 6766 SET_VREG(r0, r9) @ vAA<- r0 6767 GOTO_OPCODE(ip) @ jump to next instruction 6768 /* 10-12 instructions */ 6769 6770 6771/* ------------------------------ */ 6772 .balign 64 6773.L_OP_DIV_INT_LIT8: /* 0xdb */ 6774/* File: armv5te/OP_DIV_INT_LIT8.S */ 6775/* File: armv5te/binopLit8.S */ 6776 /* 6777 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6778 * that specifies an instruction that performs "result = r0 op r1". 6779 * This could be an ARM instruction or a function call. (If the result 6780 * comes back in a register other than r0, you can override "result".) 6781 * 6782 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6783 * vCC (r1). Useful for integer division and modulus. 6784 * 6785 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6786 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6787 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6788 */ 6789 /* binop/lit8 vAA, vBB, #+CC */ 6790 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6791 mov r9, rINST, lsr #8 @ r9<- AA 6792 and r2, r3, #255 @ r2<- BB 6793 GET_VREG(r0, r2) @ r0<- vBB 6794 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6795 .if 1 6796 @cmp r1, #0 @ is second operand zero? 6797 beq common_errDivideByZero 6798 .endif 6799 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6800 6801 @ optional op; may set condition codes 6802 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6803 GET_INST_OPCODE(ip) @ extract opcode from rINST 6804 SET_VREG(r0, r9) @ vAA<- r0 6805 GOTO_OPCODE(ip) @ jump to next instruction 6806 /* 10-12 instructions */ 6807 6808 6809/* ------------------------------ */ 6810 .balign 64 6811.L_OP_REM_INT_LIT8: /* 0xdc */ 6812/* File: armv5te/OP_REM_INT_LIT8.S */ 6813/* idivmod returns quotient in r0 and remainder in r1 */ 6814/* File: armv5te/binopLit8.S */ 6815 /* 6816 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6817 * that specifies an instruction that performs "result = r0 op r1". 6818 * This could be an ARM instruction or a function call. (If the result 6819 * comes back in a register other than r0, you can override "result".) 6820 * 6821 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6822 * vCC (r1). Useful for integer division and modulus. 6823 * 6824 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6825 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6826 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6827 */ 6828 /* binop/lit8 vAA, vBB, #+CC */ 6829 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6830 mov r9, rINST, lsr #8 @ r9<- AA 6831 and r2, r3, #255 @ r2<- BB 6832 GET_VREG(r0, r2) @ r0<- vBB 6833 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6834 .if 1 6835 @cmp r1, #0 @ is second operand zero? 6836 beq common_errDivideByZero 6837 .endif 6838 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6839 6840 @ optional op; may set condition codes 6841 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6842 GET_INST_OPCODE(ip) @ extract opcode from rINST 6843 SET_VREG(r1, r9) @ vAA<- r1 6844 GOTO_OPCODE(ip) @ jump to next instruction 6845 /* 10-12 instructions */ 6846 6847 6848/* ------------------------------ */ 6849 .balign 64 6850.L_OP_AND_INT_LIT8: /* 0xdd */ 6851/* File: armv5te/OP_AND_INT_LIT8.S */ 6852/* File: armv5te/binopLit8.S */ 6853 /* 6854 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6855 * that specifies an instruction that performs "result = r0 op r1". 6856 * This could be an ARM instruction or a function call. (If the result 6857 * comes back in a register other than r0, you can override "result".) 6858 * 6859 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6860 * vCC (r1). Useful for integer division and modulus. 6861 * 6862 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6863 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6864 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6865 */ 6866 /* binop/lit8 vAA, vBB, #+CC */ 6867 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6868 mov r9, rINST, lsr #8 @ r9<- AA 6869 and r2, r3, #255 @ r2<- BB 6870 GET_VREG(r0, r2) @ r0<- vBB 6871 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6872 .if 0 6873 @cmp r1, #0 @ is second operand zero? 6874 beq common_errDivideByZero 6875 .endif 6876 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6877 6878 @ optional op; may set condition codes 6879 and r0, r0, r1 @ r0<- op, r0-r3 changed 6880 GET_INST_OPCODE(ip) @ extract opcode from rINST 6881 SET_VREG(r0, r9) @ vAA<- r0 6882 GOTO_OPCODE(ip) @ jump to next instruction 6883 /* 10-12 instructions */ 6884 6885 6886/* ------------------------------ */ 6887 .balign 64 6888.L_OP_OR_INT_LIT8: /* 0xde */ 6889/* File: armv5te/OP_OR_INT_LIT8.S */ 6890/* File: armv5te/binopLit8.S */ 6891 /* 6892 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6893 * that specifies an instruction that performs "result = r0 op r1". 6894 * This could be an ARM instruction or a function call. (If the result 6895 * comes back in a register other than r0, you can override "result".) 6896 * 6897 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6898 * vCC (r1). Useful for integer division and modulus. 6899 * 6900 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6901 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6902 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6903 */ 6904 /* binop/lit8 vAA, vBB, #+CC */ 6905 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6906 mov r9, rINST, lsr #8 @ r9<- AA 6907 and r2, r3, #255 @ r2<- BB 6908 GET_VREG(r0, r2) @ r0<- vBB 6909 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6910 .if 0 6911 @cmp r1, #0 @ is second operand zero? 6912 beq common_errDivideByZero 6913 .endif 6914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6915 6916 @ optional op; may set condition codes 6917 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6918 GET_INST_OPCODE(ip) @ extract opcode from rINST 6919 SET_VREG(r0, r9) @ vAA<- r0 6920 GOTO_OPCODE(ip) @ jump to next instruction 6921 /* 10-12 instructions */ 6922 6923 6924/* ------------------------------ */ 6925 .balign 64 6926.L_OP_XOR_INT_LIT8: /* 0xdf */ 6927/* File: armv5te/OP_XOR_INT_LIT8.S */ 6928/* File: armv5te/binopLit8.S */ 6929 /* 6930 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6931 * that specifies an instruction that performs "result = r0 op r1". 6932 * This could be an ARM instruction or a function call. (If the result 6933 * comes back in a register other than r0, you can override "result".) 6934 * 6935 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6936 * vCC (r1). Useful for integer division and modulus. 6937 * 6938 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6939 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6940 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6941 */ 6942 /* binop/lit8 vAA, vBB, #+CC */ 6943 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6944 mov r9, rINST, lsr #8 @ r9<- AA 6945 and r2, r3, #255 @ r2<- BB 6946 GET_VREG(r0, r2) @ r0<- vBB 6947 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6948 .if 0 6949 @cmp r1, #0 @ is second operand zero? 6950 beq common_errDivideByZero 6951 .endif 6952 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6953 6954 @ optional op; may set condition codes 6955 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6956 GET_INST_OPCODE(ip) @ extract opcode from rINST 6957 SET_VREG(r0, r9) @ vAA<- r0 6958 GOTO_OPCODE(ip) @ jump to next instruction 6959 /* 10-12 instructions */ 6960 6961 6962/* ------------------------------ */ 6963 .balign 64 6964.L_OP_SHL_INT_LIT8: /* 0xe0 */ 6965/* File: armv5te/OP_SHL_INT_LIT8.S */ 6966/* File: armv5te/binopLit8.S */ 6967 /* 6968 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6969 * that specifies an instruction that performs "result = r0 op r1". 6970 * This could be an ARM instruction or a function call. (If the result 6971 * comes back in a register other than r0, you can override "result".) 6972 * 6973 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6974 * vCC (r1). Useful for integer division and modulus. 6975 * 6976 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6977 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6978 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6979 */ 6980 /* binop/lit8 vAA, vBB, #+CC */ 6981 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6982 mov r9, rINST, lsr #8 @ r9<- AA 6983 and r2, r3, #255 @ r2<- BB 6984 GET_VREG(r0, r2) @ r0<- vBB 6985 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6986 .if 0 6987 @cmp r1, #0 @ is second operand zero? 6988 beq common_errDivideByZero 6989 .endif 6990 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6991 6992 and r1, r1, #31 @ optional op; may set condition codes 6993 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 6994 GET_INST_OPCODE(ip) @ extract opcode from rINST 6995 SET_VREG(r0, r9) @ vAA<- r0 6996 GOTO_OPCODE(ip) @ jump to next instruction 6997 /* 10-12 instructions */ 6998 6999 7000/* ------------------------------ */ 7001 .balign 64 7002.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7003/* File: armv5te/OP_SHR_INT_LIT8.S */ 7004/* File: armv5te/binopLit8.S */ 7005 /* 7006 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7007 * that specifies an instruction that performs "result = r0 op r1". 7008 * This could be an ARM instruction or a function call. (If the result 7009 * comes back in a register other than r0, you can override "result".) 7010 * 7011 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7012 * vCC (r1). Useful for integer division and modulus. 7013 * 7014 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7015 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7016 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7017 */ 7018 /* binop/lit8 vAA, vBB, #+CC */ 7019 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7020 mov r9, rINST, lsr #8 @ r9<- AA 7021 and r2, r3, #255 @ r2<- BB 7022 GET_VREG(r0, r2) @ r0<- vBB 7023 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7024 .if 0 7025 @cmp r1, #0 @ is second operand zero? 7026 beq common_errDivideByZero 7027 .endif 7028 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7029 7030 and r1, r1, #31 @ optional op; may set condition codes 7031 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7032 GET_INST_OPCODE(ip) @ extract opcode from rINST 7033 SET_VREG(r0, r9) @ vAA<- r0 7034 GOTO_OPCODE(ip) @ jump to next instruction 7035 /* 10-12 instructions */ 7036 7037 7038/* ------------------------------ */ 7039 .balign 64 7040.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7041/* File: armv5te/OP_USHR_INT_LIT8.S */ 7042/* File: armv5te/binopLit8.S */ 7043 /* 7044 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7045 * that specifies an instruction that performs "result = r0 op r1". 7046 * This could be an ARM instruction or a function call. (If the result 7047 * comes back in a register other than r0, you can override "result".) 7048 * 7049 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7050 * vCC (r1). Useful for integer division and modulus. 7051 * 7052 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7053 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7054 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7055 */ 7056 /* binop/lit8 vAA, vBB, #+CC */ 7057 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7058 mov r9, rINST, lsr #8 @ r9<- AA 7059 and r2, r3, #255 @ r2<- BB 7060 GET_VREG(r0, r2) @ r0<- vBB 7061 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7062 .if 0 7063 @cmp r1, #0 @ is second operand zero? 7064 beq common_errDivideByZero 7065 .endif 7066 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7067 7068 and r1, r1, #31 @ optional op; may set condition codes 7069 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7070 GET_INST_OPCODE(ip) @ extract opcode from rINST 7071 SET_VREG(r0, r9) @ vAA<- r0 7072 GOTO_OPCODE(ip) @ jump to next instruction 7073 /* 10-12 instructions */ 7074 7075 7076/* ------------------------------ */ 7077 .balign 64 7078.L_OP_IGET_VOLATILE: /* 0xe3 */ 7079/* File: armv5te/OP_IGET_VOLATILE.S */ 7080/* File: armv5te/OP_IGET.S */ 7081 /* 7082 * General 32-bit instance field get. 7083 * 7084 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7085 */ 7086 /* op vA, vB, field@CCCC */ 7087 mov r0, rINST, lsr #12 @ r0<- B 7088 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7089 FETCH(r1, 1) @ r1<- field ref CCCC 7090 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7091 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7092 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7093 cmp r0, #0 @ is resolved entry null? 7094 bne .LOP_IGET_VOLATILE_finish @ no, already resolved 70958: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7096 EXPORT_PC() @ resolve() could throw 7097 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7098 bl dvmResolveInstField @ r0<- resolved InstField ptr 7099 cmp r0, #0 7100 bne .LOP_IGET_VOLATILE_finish 7101 b common_exceptionThrown 7102 7103 7104/* ------------------------------ */ 7105 .balign 64 7106.L_OP_IPUT_VOLATILE: /* 0xe4 */ 7107/* File: armv5te/OP_IPUT_VOLATILE.S */ 7108/* File: armv5te/OP_IPUT.S */ 7109 /* 7110 * General 32-bit instance field put. 7111 * 7112 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7113 */ 7114 /* op vA, vB, field@CCCC */ 7115 mov r0, rINST, lsr #12 @ r0<- B 7116 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7117 FETCH(r1, 1) @ r1<- field ref CCCC 7118 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7119 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7120 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7121 cmp r0, #0 @ is resolved entry null? 7122 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 71238: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7124 EXPORT_PC() @ resolve() could throw 7125 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7126 bl dvmResolveInstField @ r0<- resolved InstField ptr 7127 cmp r0, #0 @ success? 7128 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7129 b common_exceptionThrown 7130 7131 7132/* ------------------------------ */ 7133 .balign 64 7134.L_OP_SGET_VOLATILE: /* 0xe5 */ 7135/* File: armv5te/OP_SGET_VOLATILE.S */ 7136/* File: armv5te/OP_SGET.S */ 7137 /* 7138 * General 32-bit SGET handler. 7139 * 7140 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7141 */ 7142 /* op vAA, field@BBBB */ 7143 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7144 FETCH(r1, 1) @ r1<- field ref BBBB 7145 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7146 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7147 cmp r0, #0 @ is resolved entry null? 7148 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7149.LOP_SGET_VOLATILE_finish: @ field ptr in r0 7150 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7151 SMP_DMB @ acquiring load 7152 mov r2, rINST, lsr #8 @ r2<- AA 7153 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7154 SET_VREG(r1, r2) @ fp[AA]<- r1 7155 GET_INST_OPCODE(ip) @ extract opcode from rINST 7156 GOTO_OPCODE(ip) @ jump to next instruction 7157 7158 7159/* ------------------------------ */ 7160 .balign 64 7161.L_OP_SPUT_VOLATILE: /* 0xe6 */ 7162/* File: armv5te/OP_SPUT_VOLATILE.S */ 7163/* File: armv5te/OP_SPUT.S */ 7164 /* 7165 * General 32-bit SPUT handler. 7166 * 7167 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7168 */ 7169 /* op vAA, field@BBBB */ 7170 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7171 FETCH(r1, 1) @ r1<- field ref BBBB 7172 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7173 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7174 cmp r0, #0 @ is resolved entry null? 7175 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7176.LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7177 mov r2, rINST, lsr #8 @ r2<- AA 7178 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7179 GET_VREG(r1, r2) @ r1<- fp[AA] 7180 GET_INST_OPCODE(ip) @ extract opcode from rINST 7181 SMP_DMB @ releasing store 7182 str r1, [r0, #offStaticField_value] @ field<- vAA 7183 GOTO_OPCODE(ip) @ jump to next instruction 7184 7185 7186/* ------------------------------ */ 7187 .balign 64 7188.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7189/* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7190/* File: armv5te/OP_IGET.S */ 7191 /* 7192 * General 32-bit instance field get. 7193 * 7194 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7195 */ 7196 /* op vA, vB, field@CCCC */ 7197 mov r0, rINST, lsr #12 @ r0<- B 7198 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7199 FETCH(r1, 1) @ r1<- field ref CCCC 7200 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7201 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7202 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7203 cmp r0, #0 @ is resolved entry null? 7204 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 72058: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7206 EXPORT_PC() @ resolve() could throw 7207 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7208 bl dvmResolveInstField @ r0<- resolved InstField ptr 7209 cmp r0, #0 7210 bne .LOP_IGET_OBJECT_VOLATILE_finish 7211 b common_exceptionThrown 7212 7213 7214/* ------------------------------ */ 7215 .balign 64 7216.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 7217/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 7218/* File: armv5te/OP_IGET_WIDE.S */ 7219 /* 7220 * Wide 32-bit instance field get. 7221 */ 7222 /* iget-wide vA, vB, field@CCCC */ 7223 mov r0, rINST, lsr #12 @ r0<- B 7224 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7225 FETCH(r1, 1) @ r1<- field ref CCCC 7226 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7227 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7228 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7229 cmp r0, #0 @ is resolved entry null? 7230 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 72318: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7232 EXPORT_PC() @ resolve() could throw 7233 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7234 bl dvmResolveInstField @ r0<- resolved InstField ptr 7235 cmp r0, #0 7236 bne .LOP_IGET_WIDE_VOLATILE_finish 7237 b common_exceptionThrown 7238 7239 7240/* ------------------------------ */ 7241 .balign 64 7242.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 7243/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 7244/* File: armv5te/OP_IPUT_WIDE.S */ 7245 /* iput-wide vA, vB, field@CCCC */ 7246 mov r0, rINST, lsr #12 @ r0<- B 7247 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7248 FETCH(r1, 1) @ r1<- field ref CCCC 7249 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7250 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7251 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7252 cmp r0, #0 @ is resolved entry null? 7253 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 72548: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7255 EXPORT_PC() @ resolve() could throw 7256 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7257 bl dvmResolveInstField @ r0<- resolved InstField ptr 7258 cmp r0, #0 @ success? 7259 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 7260 b common_exceptionThrown 7261 7262 7263/* ------------------------------ */ 7264 .balign 64 7265.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 7266/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 7267/* File: armv5te/OP_SGET_WIDE.S */ 7268 /* 7269 * 64-bit SGET handler. 7270 */ 7271 /* sget-wide vAA, field@BBBB */ 7272 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7273 FETCH(r1, 1) @ r1<- field ref BBBB 7274 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7275 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7276 cmp r0, #0 @ is resolved entry null? 7277 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 7278.LOP_SGET_WIDE_VOLATILE_finish: 7279 mov r9, rINST, lsr #8 @ r9<- AA 7280 .if 1 7281 add r0, r0, #offStaticField_value @ r0<- pointer to data 7282 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7283 .else 7284 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7285 .endif 7286 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7287 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7288 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 7289 GET_INST_OPCODE(ip) @ extract opcode from rINST 7290 GOTO_OPCODE(ip) @ jump to next instruction 7291 7292 7293/* ------------------------------ */ 7294 .balign 64 7295.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 7296/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 7297/* File: armv5te/OP_SPUT_WIDE.S */ 7298 /* 7299 * 64-bit SPUT handler. 7300 */ 7301 /* sput-wide vAA, field@BBBB */ 7302 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 7303 FETCH(r1, 1) @ r1<- field ref BBBB 7304 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 7305 mov r9, rINST, lsr #8 @ r9<- AA 7306 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 7307 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7308 cmp r2, #0 @ is resolved entry null? 7309 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7310.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 7311 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7312 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7313 GET_INST_OPCODE(r10) @ extract opcode from rINST 7314 .if 1 7315 add r2, r2, #offStaticField_value @ r2<- pointer to data 7316 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 7317 .else 7318 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7319 .endif 7320 GOTO_OPCODE(r10) @ jump to next instruction 7321 7322 7323/* ------------------------------ */ 7324 .balign 64 7325.L_OP_BREAKPOINT: /* 0xec */ 7326/* File: armv5te/OP_BREAKPOINT.S */ 7327/* File: armv5te/unused.S */ 7328 bl common_abort 7329 7330 7331/* ------------------------------ */ 7332 .balign 64 7333.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7334/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7335 /* 7336 * Handle a throw-verification-error instruction. This throws an 7337 * exception for an error discovered during verification. The 7338 * exception is indicated by AA, with some detail provided by BBBB. 7339 */ 7340 /* op AA, ref@BBBB */ 7341 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 7342 FETCH(r2, 1) @ r2<- BBBB 7343 EXPORT_PC() @ export the PC 7344 mov r1, rINST, lsr #8 @ r1<- AA 7345 bl dvmThrowVerificationError @ always throws 7346 b common_exceptionThrown @ handle exception 7347 7348/* ------------------------------ */ 7349 .balign 64 7350.L_OP_EXECUTE_INLINE: /* 0xee */ 7351/* File: armv5te/OP_EXECUTE_INLINE.S */ 7352 /* 7353 * Execute a "native inline" instruction. 7354 * 7355 * We need to call an InlineOp4Func: 7356 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7357 * 7358 * The first four args are in r0-r3, pointer to return value storage 7359 * is on the stack. The function's return value is a flag that tells 7360 * us if an exception was thrown. 7361 */ 7362 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7363 FETCH(r10, 1) @ r10<- BBBB 7364 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7365 EXPORT_PC() @ can throw 7366 sub sp, sp, #8 @ make room for arg, +64 bit align 7367 mov r0, rINST, lsr #12 @ r0<- B 7368 str r1, [sp] @ push &self->retval 7369 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7370 add sp, sp, #8 @ pop stack 7371 cmp r0, #0 @ test boolean result of inline 7372 beq common_exceptionThrown @ returned false, handle exception 7373 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7374 GET_INST_OPCODE(ip) @ extract opcode from rINST 7375 GOTO_OPCODE(ip) @ jump to next instruction 7376 7377/* ------------------------------ */ 7378 .balign 64 7379.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7380/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7381 /* 7382 * Execute a "native inline" instruction, using "/range" semantics. 7383 * Same idea as execute-inline, but we get the args differently. 7384 * 7385 * We need to call an InlineOp4Func: 7386 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7387 * 7388 * The first four args are in r0-r3, pointer to return value storage 7389 * is on the stack. The function's return value is a flag that tells 7390 * us if an exception was thrown. 7391 */ 7392 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7393 FETCH(r10, 1) @ r10<- BBBB 7394 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7395 EXPORT_PC() @ can throw 7396 sub sp, sp, #8 @ make room for arg, +64 bit align 7397 mov r0, rINST, lsr #8 @ r0<- AA 7398 str r1, [sp] @ push &self->retval 7399 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7400 add sp, sp, #8 @ pop stack 7401 cmp r0, #0 @ test boolean result of inline 7402 beq common_exceptionThrown @ returned false, handle exception 7403 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7404 GET_INST_OPCODE(ip) @ extract opcode from rINST 7405 GOTO_OPCODE(ip) @ jump to next instruction 7406 7407/* ------------------------------ */ 7408 .balign 64 7409.L_OP_INVOKE_OBJECT_INIT: /* 0xf0 */ 7410/* File: armv5te/OP_INVOKE_OBJECT_INIT.S */ 7411 /* 7412 * Invoke Object.<init> on an object. In practice we know that 7413 * Object's nullary constructor doesn't do anything, so we just 7414 * skip it (we know a debugger isn't active). 7415 */ 7416 FETCH(r0, 2) @ r0<- GFED 7417 and r1, r0, #15 @ r1<- D 7418 GET_VREG(r0, r1) @ r0<- "this" ptr 7419 cmp r0, #0 @ check for NULL 7420 beq common_errNullObject @ export PC and throw NPE 7421 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 7422 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 7423 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 7424 beq 1f @ nope, done 7425 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 74261: FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7427 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7428 GOTO_OPCODE(ip) @ execute it 7429 7430/* ------------------------------ */ 7431 .balign 64 7432.L_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 7433/* File: armv5te/OP_RETURN_VOID_BARRIER.S */ 7434 SMP_DMB_ST 7435 b common_returnFromMethod 7436 7437/* ------------------------------ */ 7438 .balign 64 7439.L_OP_IGET_QUICK: /* 0xf2 */ 7440/* File: armv5te/OP_IGET_QUICK.S */ 7441 /* For: iget-quick, iget-object-quick */ 7442 /* op vA, vB, offset@CCCC */ 7443 mov r2, rINST, lsr #12 @ r2<- B 7444 GET_VREG(r3, r2) @ r3<- object we're operating on 7445 FETCH(r1, 1) @ r1<- field byte offset 7446 cmp r3, #0 @ check object for null 7447 mov r2, rINST, lsr #8 @ r2<- A(+) 7448 beq common_errNullObject @ object was null 7449 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7450 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7451 and r2, r2, #15 7452 GET_INST_OPCODE(ip) @ extract opcode from rINST 7453 SET_VREG(r0, r2) @ fp[A]<- r0 7454 GOTO_OPCODE(ip) @ jump to next instruction 7455 7456/* ------------------------------ */ 7457 .balign 64 7458.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7459/* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7460 /* iget-wide-quick vA, vB, offset@CCCC */ 7461 mov r2, rINST, lsr #12 @ r2<- B 7462 GET_VREG(r3, r2) @ r3<- object we're operating on 7463 FETCH(ip, 1) @ ip<- field byte offset 7464 cmp r3, #0 @ check object for null 7465 mov r2, rINST, lsr #8 @ r2<- A(+) 7466 beq common_errNullObject @ object was null 7467 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7468 and r2, r2, #15 7469 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7470 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7471 GET_INST_OPCODE(ip) @ extract opcode from rINST 7472 stmia r3, {r0-r1} @ fp[A]<- r0/r1 7473 GOTO_OPCODE(ip) @ jump to next instruction 7474 7475/* ------------------------------ */ 7476 .balign 64 7477.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7478/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7479/* File: armv5te/OP_IGET_QUICK.S */ 7480 /* For: iget-quick, iget-object-quick */ 7481 /* op vA, vB, offset@CCCC */ 7482 mov r2, rINST, lsr #12 @ r2<- B 7483 GET_VREG(r3, r2) @ r3<- object we're operating on 7484 FETCH(r1, 1) @ r1<- field byte offset 7485 cmp r3, #0 @ check object for null 7486 mov r2, rINST, lsr #8 @ r2<- A(+) 7487 beq common_errNullObject @ object was null 7488 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7489 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7490 and r2, r2, #15 7491 GET_INST_OPCODE(ip) @ extract opcode from rINST 7492 SET_VREG(r0, r2) @ fp[A]<- r0 7493 GOTO_OPCODE(ip) @ jump to next instruction 7494 7495 7496/* ------------------------------ */ 7497 .balign 64 7498.L_OP_IPUT_QUICK: /* 0xf5 */ 7499/* File: armv5te/OP_IPUT_QUICK.S */ 7500 /* For: iput-quick */ 7501 /* op vA, vB, offset@CCCC */ 7502 mov r2, rINST, lsr #12 @ r2<- B 7503 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7504 FETCH(r1, 1) @ r1<- field byte offset 7505 cmp r3, #0 @ check object for null 7506 mov r2, rINST, lsr #8 @ r2<- A(+) 7507 beq common_errNullObject @ object was null 7508 and r2, r2, #15 7509 GET_VREG(r0, r2) @ r0<- fp[A] 7510 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7511 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7512 GET_INST_OPCODE(ip) @ extract opcode from rINST 7513 GOTO_OPCODE(ip) @ jump to next instruction 7514 7515/* ------------------------------ */ 7516 .balign 64 7517.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7518/* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7519 /* iput-wide-quick vA, vB, offset@CCCC */ 7520 mov r0, rINST, lsr #8 @ r0<- A(+) 7521 mov r1, rINST, lsr #12 @ r1<- B 7522 and r0, r0, #15 7523 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7524 add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7525 cmp r2, #0 @ check object for null 7526 ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7527 beq common_errNullObject @ object was null 7528 FETCH(r3, 1) @ r3<- field byte offset 7529 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7530 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7531 GET_INST_OPCODE(ip) @ extract opcode from rINST 7532 GOTO_OPCODE(ip) @ jump to next instruction 7533 7534/* ------------------------------ */ 7535 .balign 64 7536.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7537/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7538 /* For: iput-object-quick */ 7539 /* op vA, vB, offset@CCCC */ 7540 mov r2, rINST, lsr #12 @ r2<- B 7541 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7542 FETCH(r1, 1) @ r1<- field byte offset 7543 cmp r3, #0 @ check object for null 7544 mov r2, rINST, lsr #8 @ r2<- A(+) 7545 beq common_errNullObject @ object was null 7546 and r2, r2, #15 7547 GET_VREG(r0, r2) @ r0<- fp[A] 7548 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 7549 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7550 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7551 cmp r0, #0 7552 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head 7553 GET_INST_OPCODE(ip) @ extract opcode from rINST 7554 GOTO_OPCODE(ip) @ jump to next instruction 7555 7556/* ------------------------------ */ 7557 .balign 64 7558.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7559/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7560 /* 7561 * Handle an optimized virtual method call. 7562 * 7563 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7564 */ 7565 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7566 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7567 FETCH(r3, 2) @ r3<- FEDC or CCCC 7568 FETCH(r1, 1) @ r1<- BBBB 7569 .if (!0) 7570 and r3, r3, #15 @ r3<- C (or stays CCCC) 7571 .endif 7572 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7573 cmp r2, #0 @ is "this" null? 7574 beq common_errNullObject @ null "this", throw exception 7575 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7576 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7577 EXPORT_PC() @ invoke must export 7578 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7579 bl common_invokeMethodNoRange @ continue on 7580 7581/* ------------------------------ */ 7582 .balign 64 7583.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7584/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7585/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7586 /* 7587 * Handle an optimized virtual method call. 7588 * 7589 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7590 */ 7591 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7592 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7593 FETCH(r3, 2) @ r3<- FEDC or CCCC 7594 FETCH(r1, 1) @ r1<- BBBB 7595 .if (!1) 7596 and r3, r3, #15 @ r3<- C (or stays CCCC) 7597 .endif 7598 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7599 cmp r2, #0 @ is "this" null? 7600 beq common_errNullObject @ null "this", throw exception 7601 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7602 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7603 EXPORT_PC() @ invoke must export 7604 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7605 bl common_invokeMethodRange @ continue on 7606 7607 7608/* ------------------------------ */ 7609 .balign 64 7610.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7611/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7612 /* 7613 * Handle an optimized "super" method call. 7614 * 7615 * for: [opt] invoke-super-quick, invoke-super-quick/range 7616 */ 7617 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7618 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7619 FETCH(r10, 2) @ r10<- GFED or CCCC 7620 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7621 .if (!0) 7622 and r10, r10, #15 @ r10<- D (or stays CCCC) 7623 .endif 7624 FETCH(r1, 1) @ r1<- BBBB 7625 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7626 EXPORT_PC() @ must export for invoke 7627 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7628 GET_VREG(r3, r10) @ r3<- "this" 7629 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7630 cmp r3, #0 @ null "this" ref? 7631 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7632 beq common_errNullObject @ "this" is null, throw exception 7633 bl common_invokeMethodNoRange @ continue on 7634 7635/* ------------------------------ */ 7636 .balign 64 7637.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7638/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7639/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7640 /* 7641 * Handle an optimized "super" method call. 7642 * 7643 * for: [opt] invoke-super-quick, invoke-super-quick/range 7644 */ 7645 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7646 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7647 FETCH(r10, 2) @ r10<- GFED or CCCC 7648 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7649 .if (!1) 7650 and r10, r10, #15 @ r10<- D (or stays CCCC) 7651 .endif 7652 FETCH(r1, 1) @ r1<- BBBB 7653 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7654 EXPORT_PC() @ must export for invoke 7655 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7656 GET_VREG(r3, r10) @ r3<- "this" 7657 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7658 cmp r3, #0 @ null "this" ref? 7659 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7660 beq common_errNullObject @ "this" is null, throw exception 7661 bl common_invokeMethodRange @ continue on 7662 7663 7664/* ------------------------------ */ 7665 .balign 64 7666.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7667/* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7668/* File: armv5te/OP_IPUT_OBJECT.S */ 7669 /* 7670 * 32-bit instance field put. 7671 * 7672 * for: iput-object, iput-object-volatile 7673 */ 7674 /* op vA, vB, field@CCCC */ 7675 mov r0, rINST, lsr #12 @ r0<- B 7676 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7677 FETCH(r1, 1) @ r1<- field ref CCCC 7678 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7679 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7680 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7681 cmp r0, #0 @ is resolved entry null? 7682 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 76838: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7684 EXPORT_PC() @ resolve() could throw 7685 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7686 bl dvmResolveInstField @ r0<- resolved InstField ptr 7687 cmp r0, #0 @ success? 7688 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 7689 b common_exceptionThrown 7690 7691 7692/* ------------------------------ */ 7693 .balign 64 7694.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 7695/* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 7696/* File: armv5te/OP_SGET.S */ 7697 /* 7698 * General 32-bit SGET handler. 7699 * 7700 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7701 */ 7702 /* op vAA, field@BBBB */ 7703 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7704 FETCH(r1, 1) @ r1<- field ref BBBB 7705 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7706 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7707 cmp r0, #0 @ is resolved entry null? 7708 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 7709.LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 7710 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7711 SMP_DMB @ acquiring load 7712 mov r2, rINST, lsr #8 @ r2<- AA 7713 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7714 SET_VREG(r1, r2) @ fp[AA]<- r1 7715 GET_INST_OPCODE(ip) @ extract opcode from rINST 7716 GOTO_OPCODE(ip) @ jump to next instruction 7717 7718 7719/* ------------------------------ */ 7720 .balign 64 7721.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 7722/* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 7723/* File: armv5te/OP_SPUT_OBJECT.S */ 7724 /* 7725 * 32-bit SPUT handler for objects 7726 * 7727 * for: sput-object, sput-object-volatile 7728 */ 7729 /* op vAA, field@BBBB */ 7730 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7731 FETCH(r1, 1) @ r1<- field ref BBBB 7732 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7733 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7734 cmp r0, #0 @ is resolved entry null? 7735 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue 7736 ldr r9, [rSELF, #offThread_method] @ r9<- current method 7737 EXPORT_PC() @ resolve() could throw, so export now 7738 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 7739 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 7740 cmp r0, #0 @ success? 7741 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish 7742 b common_exceptionThrown @ no, handle exception 7743 7744 7745 7746/* ------------------------------ */ 7747 .balign 64 7748.L_OP_DISPATCH_FF: /* 0xff */ 7749/* File: armv5te/OP_DISPATCH_FF.S */ 7750 mov ip, rINST, lsr #8 @ ip<- extended opcode 7751 add ip, ip, #256 @ add offset for extended opcodes 7752 GOTO_OPCODE(ip) @ go to proper extended handler 7753 7754 7755/* ------------------------------ */ 7756 .balign 64 7757.L_OP_CONST_CLASS_JUMBO: /* 0x100 */ 7758/* File: armv5te/OP_CONST_CLASS_JUMBO.S */ 7759 /* const-class/jumbo vBBBB, Class@AAAAAAAA */ 7760 FETCH(r0, 1) @ r0<- aaaa (lo) 7761 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex 7762 FETCH(r1, 2) @ r1<- AAAA (hi) 7763 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 7764 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7765 FETCH(r9, 3) @ r9<- BBBB 7766 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa] 7767 cmp r0, #0 @ not yet resolved? 7768 beq .LOP_CONST_CLASS_JUMBO_resolve 7769 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 7770 GET_INST_OPCODE(ip) @ extract opcode from rINST 7771 SET_VREG(r0, r9) @ vBBBB<- r0 7772 GOTO_OPCODE(ip) @ jump to next instruction 7773 7774/* ------------------------------ */ 7775 .balign 64 7776.L_OP_CHECK_CAST_JUMBO: /* 0x101 */ 7777/* File: armv5te/OP_CHECK_CAST_JUMBO.S */ 7778 /* 7779 * Check to see if a cast from one class to another is allowed. 7780 */ 7781 /* check-cast/jumbo vBBBB, class@AAAAAAAA */ 7782 FETCH(r0, 1) @ r0<- aaaa (lo) 7783 FETCH(r2, 2) @ r2<- AAAA (hi) 7784 FETCH(r3, 3) @ r3<- BBBB 7785 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa 7786 GET_VREG(r9, r3) @ r9<- object 7787 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 7788 cmp r9, #0 @ is object null? 7789 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 7790 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds 7791 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 7792 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7793 cmp r1, #0 @ have we resolved this before? 7794 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now 7795.LOP_CHECK_CAST_JUMBO_resolved: 7796 cmp r0, r1 @ same class (trivial success)? 7797 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check 7798 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up 7799 7800/* ------------------------------ */ 7801 .balign 64 7802.L_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 7803/* File: armv5te/OP_INSTANCE_OF_JUMBO.S */ 7804 /* 7805 * Check to see if an object reference is an instance of a class. 7806 * 7807 * Most common situation is a non-null object, being compared against 7808 * an already-resolved class. 7809 * 7810 * TODO: convert most of this into a common subroutine, shared with 7811 * OP_INSTANCE_OF.S. 7812 */ 7813 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7814 FETCH(r3, 4) @ r3<- vCCCC 7815 FETCH(r9, 3) @ r9<- vBBBB 7816 GET_VREG(r0, r3) @ r0<- vCCCC (object) 7817 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 7818 cmp r0, #0 @ is object null? 7819 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0 7820 FETCH(r1, 1) @ r1<- aaaa (lo) 7821 FETCH(r3, 2) @ r3<- AAAA (hi) 7822 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 7823 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa 7824 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 7825 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7826 cmp r1, #0 @ have we resolved this before? 7827 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now 7828 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue 7829 7830/* ------------------------------ */ 7831 .balign 64 7832.L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 7833/* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */ 7834 /* 7835 * Create a new instance of a class. 7836 */ 7837 /* new-instance/jumbo vBBBB, class@AAAAAAAA */ 7838 FETCH(r0, 1) @ r0<- aaaa (lo) 7839 FETCH(r1, 2) @ r1<- AAAA (hi) 7840 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7841 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7842 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7843 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7844 EXPORT_PC() @ req'd for init, resolve, alloc 7845 cmp r0, #0 @ already resolved? 7846 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now 7847.LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class 7848 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 7849 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 7850 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now 7851.LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class 7852 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 7853 bl dvmAllocObject @ r0<- new object 7854 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue 7855 7856/* ------------------------------ */ 7857 .balign 64 7858.L_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 7859/* File: armv5te/OP_NEW_ARRAY_JUMBO.S */ 7860 /* 7861 * Allocate an array of objects, specified with the array class 7862 * and a count. 7863 * 7864 * The verifier guarantees that this is an array class, so we don't 7865 * check for it here. 7866 */ 7867 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7868 FETCH(r2, 1) @ r2<- aaaa (lo) 7869 FETCH(r3, 2) @ r3<- AAAA (hi) 7870 FETCH(r0, 4) @ r0<- vCCCC 7871 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa 7872 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7873 GET_VREG(r1, r0) @ r1<- vCCCC (array length) 7874 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7875 cmp r1, #0 @ check length 7876 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 7877 bmi common_errNegativeArraySize @ negative length, bail - len in r1 7878 cmp r0, #0 @ already resolved? 7879 EXPORT_PC() @ req'd for resolve, alloc 7880 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue 7881 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now 7882 7883/* ------------------------------ */ 7884 .balign 64 7885.L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 7886/* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */ 7887 /* 7888 * Create a new array with elements filled from registers. 7889 * 7890 * TODO: convert most of this into a common subroutine, shared with 7891 * OP_FILLED_NEW_ARRAY.S. 7892 */ 7893 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */ 7894 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7895 FETCH(r0, 1) @ r0<- aaaa (lo) 7896 FETCH(r1, 2) @ r1<- AAAA (hi) 7897 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7898 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7899 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7900 EXPORT_PC() @ need for resolve and alloc 7901 cmp r0, #0 @ already resolved? 7902 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on 79038: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 7904 mov r2, #0 @ r2<- false 7905 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7906 bl dvmResolveClass @ r0<- call(clazz, ref) 7907 cmp r0, #0 @ got null? 7908 beq common_exceptionThrown @ yes, handle exception 7909 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue 7910 7911/* ------------------------------ */ 7912 .balign 64 7913.L_OP_IGET_JUMBO: /* 0x106 */ 7914/* File: armv5te/OP_IGET_JUMBO.S */ 7915 /* 7916 * Jumbo 32-bit instance field get. 7917 * 7918 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7919 * iget-char/jumbo, iget-short/jumbo 7920 */ 7921 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7922 FETCH(r1, 1) @ r1<- aaaa (lo) 7923 FETCH(r2, 2) @ r2<- AAAA (hi) 7924 FETCH(r0, 4) @ r0<- CCCC 7925 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7926 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7927 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7928 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7929 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7930 cmp r0, #0 @ is resolved entry null? 7931 bne .LOP_IGET_JUMBO_finish @ no, already resolved 79328: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7933 EXPORT_PC() @ resolve() could throw 7934 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7935 bl dvmResolveInstField @ r0<- resolved InstField ptr 7936 b .LOP_IGET_JUMBO_resolved @ resolved, continue 7937 7938/* ------------------------------ */ 7939 .balign 64 7940.L_OP_IGET_WIDE_JUMBO: /* 0x107 */ 7941/* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 7942 /* 7943 * Jumbo 64-bit instance field get. 7944 */ 7945 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 7946 FETCH(r1, 1) @ r1<- aaaa (lo) 7947 FETCH(r2, 2) @ r2<- AAAA (hi) 7948 FETCH(r0, 4) @ r0<- CCCC 7949 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7950 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7951 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7952 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7953 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7954 cmp r0, #0 @ is resolved entry null? 7955 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved 79568: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7957 EXPORT_PC() @ resolve() could throw 7958 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7959 bl dvmResolveInstField @ r0<- resolved InstField ptr 7960 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue 7961 7962/* ------------------------------ */ 7963 .balign 64 7964.L_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 7965/* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 7966/* File: armv5te/OP_IGET_JUMBO.S */ 7967 /* 7968 * Jumbo 32-bit instance field get. 7969 * 7970 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7971 * iget-char/jumbo, iget-short/jumbo 7972 */ 7973 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7974 FETCH(r1, 1) @ r1<- aaaa (lo) 7975 FETCH(r2, 2) @ r2<- AAAA (hi) 7976 FETCH(r0, 4) @ r0<- CCCC 7977 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7978 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7979 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7980 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7981 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7982 cmp r0, #0 @ is resolved entry null? 7983 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved 79848: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7985 EXPORT_PC() @ resolve() could throw 7986 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7987 bl dvmResolveInstField @ r0<- resolved InstField ptr 7988 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue 7989 7990 7991/* ------------------------------ */ 7992 .balign 64 7993.L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 7994/* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */ 7995@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" } 7996/* File: armv5te/OP_IGET_JUMBO.S */ 7997 /* 7998 * Jumbo 32-bit instance field get. 7999 * 8000 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8001 * iget-char/jumbo, iget-short/jumbo 8002 */ 8003 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8004 FETCH(r1, 1) @ r1<- aaaa (lo) 8005 FETCH(r2, 2) @ r2<- AAAA (hi) 8006 FETCH(r0, 4) @ r0<- CCCC 8007 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8008 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8009 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8010 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8011 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8012 cmp r0, #0 @ is resolved entry null? 8013 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved 80148: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8015 EXPORT_PC() @ resolve() could throw 8016 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8017 bl dvmResolveInstField @ r0<- resolved InstField ptr 8018 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue 8019 8020 8021/* ------------------------------ */ 8022 .balign 64 8023.L_OP_IGET_BYTE_JUMBO: /* 0x10a */ 8024/* File: armv5te/OP_IGET_BYTE_JUMBO.S */ 8025@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" } 8026/* File: armv5te/OP_IGET_JUMBO.S */ 8027 /* 8028 * Jumbo 32-bit instance field get. 8029 * 8030 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8031 * iget-char/jumbo, iget-short/jumbo 8032 */ 8033 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8034 FETCH(r1, 1) @ r1<- aaaa (lo) 8035 FETCH(r2, 2) @ r2<- AAAA (hi) 8036 FETCH(r0, 4) @ r0<- CCCC 8037 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8038 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8039 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8040 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8041 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8042 cmp r0, #0 @ is resolved entry null? 8043 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved 80448: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8045 EXPORT_PC() @ resolve() could throw 8046 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8047 bl dvmResolveInstField @ r0<- resolved InstField ptr 8048 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue 8049 8050 8051/* ------------------------------ */ 8052 .balign 64 8053.L_OP_IGET_CHAR_JUMBO: /* 0x10b */ 8054/* File: armv5te/OP_IGET_CHAR_JUMBO.S */ 8055@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" } 8056/* File: armv5te/OP_IGET_JUMBO.S */ 8057 /* 8058 * Jumbo 32-bit instance field get. 8059 * 8060 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8061 * iget-char/jumbo, iget-short/jumbo 8062 */ 8063 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8064 FETCH(r1, 1) @ r1<- aaaa (lo) 8065 FETCH(r2, 2) @ r2<- AAAA (hi) 8066 FETCH(r0, 4) @ r0<- CCCC 8067 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8068 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8069 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8070 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8071 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8072 cmp r0, #0 @ is resolved entry null? 8073 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved 80748: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8075 EXPORT_PC() @ resolve() could throw 8076 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8077 bl dvmResolveInstField @ r0<- resolved InstField ptr 8078 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue 8079 8080 8081/* ------------------------------ */ 8082 .balign 64 8083.L_OP_IGET_SHORT_JUMBO: /* 0x10c */ 8084/* File: armv5te/OP_IGET_SHORT_JUMBO.S */ 8085@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" } 8086/* File: armv5te/OP_IGET_JUMBO.S */ 8087 /* 8088 * Jumbo 32-bit instance field get. 8089 * 8090 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8091 * iget-char/jumbo, iget-short/jumbo 8092 */ 8093 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8094 FETCH(r1, 1) @ r1<- aaaa (lo) 8095 FETCH(r2, 2) @ r2<- AAAA (hi) 8096 FETCH(r0, 4) @ r0<- CCCC 8097 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8098 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8099 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8100 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8101 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8102 cmp r0, #0 @ is resolved entry null? 8103 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved 81048: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8105 EXPORT_PC() @ resolve() could throw 8106 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8107 bl dvmResolveInstField @ r0<- resolved InstField ptr 8108 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue 8109 8110 8111/* ------------------------------ */ 8112 .balign 64 8113.L_OP_IPUT_JUMBO: /* 0x10d */ 8114/* File: armv5te/OP_IPUT_JUMBO.S */ 8115 /* 8116 * Jumbo 32-bit instance field put. 8117 * 8118 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8119 * iput-short/jumbo 8120 */ 8121 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8122 FETCH(r1, 1) @ r1<- aaaa (lo) 8123 FETCH(r2, 2) @ r2<- AAAA (hi) 8124 FETCH(r0, 4) @ r0<- CCCC 8125 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8126 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8127 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8128 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8129 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8130 cmp r0, #0 @ is resolved entry null? 8131 bne .LOP_IPUT_JUMBO_finish @ no, already resolved 81328: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8133 EXPORT_PC() @ resolve() could throw 8134 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8135 bl dvmResolveInstField @ r0<- resolved InstField ptr 8136 b .LOP_IPUT_JUMBO_resolved @ resolved, continue 8137 8138/* ------------------------------ */ 8139 .balign 64 8140.L_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 8141/* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 8142 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8143 FETCH(r1, 1) @ r1<- aaaa (lo) 8144 FETCH(r2, 2) @ r2<- AAAA (hi) 8145 FETCH(r0, 4) @ r0<- CCCC 8146 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8147 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8148 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 8149 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 8150 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8151 cmp r0, #0 @ is resolved entry null? 8152 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved 81538: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8154 EXPORT_PC() @ resolve() could throw 8155 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8156 bl dvmResolveInstField @ r0<- resolved InstField ptr 8157 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue 8158 8159/* ------------------------------ */ 8160 .balign 64 8161.L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 8162/* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 8163 /* 8164 * Jumbo 32-bit instance field put. 8165 */ 8166 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8167 FETCH(r1, 1) @ r1<- aaaa (lo) 8168 FETCH(r2, 2) @ r2<- AAAA (hi) 8169 FETCH(r0, 4) @ r0<- CCCC 8170 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8171 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8172 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8173 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8174 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8175 cmp r0, #0 @ is resolved entry null? 8176 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved 81778: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8178 EXPORT_PC() @ resolve() could throw 8179 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8180 bl dvmResolveInstField @ r0<- resolved InstField ptr 8181 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue 8182 8183/* ------------------------------ */ 8184 .balign 64 8185.L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 8186/* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */ 8187@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" } 8188/* File: armv5te/OP_IPUT_JUMBO.S */ 8189 /* 8190 * Jumbo 32-bit instance field put. 8191 * 8192 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8193 * iput-short/jumbo 8194 */ 8195 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8196 FETCH(r1, 1) @ r1<- aaaa (lo) 8197 FETCH(r2, 2) @ r2<- AAAA (hi) 8198 FETCH(r0, 4) @ r0<- CCCC 8199 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8200 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8201 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8202 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8203 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8204 cmp r0, #0 @ is resolved entry null? 8205 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved 82068: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8207 EXPORT_PC() @ resolve() could throw 8208 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8209 bl dvmResolveInstField @ r0<- resolved InstField ptr 8210 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue 8211 8212 8213/* ------------------------------ */ 8214 .balign 64 8215.L_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 8216/* File: armv5te/OP_IPUT_BYTE_JUMBO.S */ 8217@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" } 8218/* File: armv5te/OP_IPUT_JUMBO.S */ 8219 /* 8220 * Jumbo 32-bit instance field put. 8221 * 8222 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8223 * iput-short/jumbo 8224 */ 8225 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8226 FETCH(r1, 1) @ r1<- aaaa (lo) 8227 FETCH(r2, 2) @ r2<- AAAA (hi) 8228 FETCH(r0, 4) @ r0<- CCCC 8229 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8230 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8231 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8232 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8233 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8234 cmp r0, #0 @ is resolved entry null? 8235 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved 82368: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8237 EXPORT_PC() @ resolve() could throw 8238 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8239 bl dvmResolveInstField @ r0<- resolved InstField ptr 8240 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue 8241 8242 8243/* ------------------------------ */ 8244 .balign 64 8245.L_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 8246/* File: armv5te/OP_IPUT_CHAR_JUMBO.S */ 8247@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" } 8248/* File: armv5te/OP_IPUT_JUMBO.S */ 8249 /* 8250 * Jumbo 32-bit instance field put. 8251 * 8252 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8253 * iput-short/jumbo 8254 */ 8255 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8256 FETCH(r1, 1) @ r1<- aaaa (lo) 8257 FETCH(r2, 2) @ r2<- AAAA (hi) 8258 FETCH(r0, 4) @ r0<- CCCC 8259 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8260 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8261 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8262 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8263 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8264 cmp r0, #0 @ is resolved entry null? 8265 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved 82668: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8267 EXPORT_PC() @ resolve() could throw 8268 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8269 bl dvmResolveInstField @ r0<- resolved InstField ptr 8270 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue 8271 8272 8273/* ------------------------------ */ 8274 .balign 64 8275.L_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 8276/* File: armv5te/OP_IPUT_SHORT_JUMBO.S */ 8277@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" } 8278/* File: armv5te/OP_IPUT_JUMBO.S */ 8279 /* 8280 * Jumbo 32-bit instance field put. 8281 * 8282 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8283 * iput-short/jumbo 8284 */ 8285 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8286 FETCH(r1, 1) @ r1<- aaaa (lo) 8287 FETCH(r2, 2) @ r2<- AAAA (hi) 8288 FETCH(r0, 4) @ r0<- CCCC 8289 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8290 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8291 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8292 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8293 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8294 cmp r0, #0 @ is resolved entry null? 8295 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved 82968: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8297 EXPORT_PC() @ resolve() could throw 8298 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8299 bl dvmResolveInstField @ r0<- resolved InstField ptr 8300 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue 8301 8302 8303/* ------------------------------ */ 8304 .balign 64 8305.L_OP_SGET_JUMBO: /* 0x114 */ 8306/* File: armv5te/OP_SGET_JUMBO.S */ 8307 /* 8308 * Jumbo 32-bit SGET handler. 8309 * 8310 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8311 * sget-char/jumbo, sget-short/jumbo 8312 */ 8313 /* exop vBBBB, field@AAAAAAAA */ 8314 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8315 FETCH(r0, 1) @ r0<- aaaa (lo) 8316 FETCH(r1, 2) @ r1<- AAAA (hi) 8317 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8318 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8319 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8320 cmp r0, #0 @ is resolved entry null? 8321 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve 8322.LOP_SGET_JUMBO_finish: @ field ptr in r0 8323 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8324 @ no-op @ acquiring load 8325 FETCH(r2, 3) @ r2<- BBBB 8326 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8327 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8328 GET_INST_OPCODE(ip) @ extract opcode from rINST 8329 GOTO_OPCODE(ip) @ jump to next instruction 8330 8331/* ------------------------------ */ 8332 .balign 64 8333.L_OP_SGET_WIDE_JUMBO: /* 0x115 */ 8334/* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 8335 /* 8336 * Jumbo 64-bit SGET handler. 8337 */ 8338 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 8339 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8340 FETCH(r0, 1) @ r0<- aaaa (lo) 8341 FETCH(r1, 2) @ r1<- AAAA (hi) 8342 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8343 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8344 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8345 cmp r0, #0 @ is resolved entry null? 8346 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve 8347.LOP_SGET_WIDE_JUMBO_finish: 8348 FETCH(r9, 3) @ r9<- BBBB 8349 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 8350 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8351 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8352 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 8353 GET_INST_OPCODE(ip) @ extract opcode from rINST 8354 GOTO_OPCODE(ip) @ jump to next instruction 8355 8356/* ------------------------------ */ 8357 .balign 64 8358.L_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 8359/* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 8360/* File: armv5te/OP_SGET_JUMBO.S */ 8361 /* 8362 * Jumbo 32-bit SGET handler. 8363 * 8364 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8365 * sget-char/jumbo, sget-short/jumbo 8366 */ 8367 /* exop vBBBB, field@AAAAAAAA */ 8368 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8369 FETCH(r0, 1) @ r0<- aaaa (lo) 8370 FETCH(r1, 2) @ r1<- AAAA (hi) 8371 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8372 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8373 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8374 cmp r0, #0 @ is resolved entry null? 8375 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve 8376.LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0 8377 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8378 @ no-op @ acquiring load 8379 FETCH(r2, 3) @ r2<- BBBB 8380 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8381 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8382 GET_INST_OPCODE(ip) @ extract opcode from rINST 8383 GOTO_OPCODE(ip) @ jump to next instruction 8384 8385 8386/* ------------------------------ */ 8387 .balign 64 8388.L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 8389/* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */ 8390/* File: armv5te/OP_SGET_JUMBO.S */ 8391 /* 8392 * Jumbo 32-bit SGET handler. 8393 * 8394 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8395 * sget-char/jumbo, sget-short/jumbo 8396 */ 8397 /* exop vBBBB, field@AAAAAAAA */ 8398 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8399 FETCH(r0, 1) @ r0<- aaaa (lo) 8400 FETCH(r1, 2) @ r1<- AAAA (hi) 8401 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8402 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8403 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8404 cmp r0, #0 @ is resolved entry null? 8405 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve 8406.LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0 8407 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8408 @ no-op @ acquiring load 8409 FETCH(r2, 3) @ r2<- BBBB 8410 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8411 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8412 GET_INST_OPCODE(ip) @ extract opcode from rINST 8413 GOTO_OPCODE(ip) @ jump to next instruction 8414 8415 8416/* ------------------------------ */ 8417 .balign 64 8418.L_OP_SGET_BYTE_JUMBO: /* 0x118 */ 8419/* File: armv5te/OP_SGET_BYTE_JUMBO.S */ 8420/* File: armv5te/OP_SGET_JUMBO.S */ 8421 /* 8422 * Jumbo 32-bit SGET handler. 8423 * 8424 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8425 * sget-char/jumbo, sget-short/jumbo 8426 */ 8427 /* exop vBBBB, field@AAAAAAAA */ 8428 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8429 FETCH(r0, 1) @ r0<- aaaa (lo) 8430 FETCH(r1, 2) @ r1<- AAAA (hi) 8431 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8432 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8433 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8434 cmp r0, #0 @ is resolved entry null? 8435 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve 8436.LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0 8437 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8438 @ no-op @ acquiring load 8439 FETCH(r2, 3) @ r2<- BBBB 8440 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8441 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8442 GET_INST_OPCODE(ip) @ extract opcode from rINST 8443 GOTO_OPCODE(ip) @ jump to next instruction 8444 8445 8446/* ------------------------------ */ 8447 .balign 64 8448.L_OP_SGET_CHAR_JUMBO: /* 0x119 */ 8449/* File: armv5te/OP_SGET_CHAR_JUMBO.S */ 8450/* File: armv5te/OP_SGET_JUMBO.S */ 8451 /* 8452 * Jumbo 32-bit SGET handler. 8453 * 8454 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8455 * sget-char/jumbo, sget-short/jumbo 8456 */ 8457 /* exop vBBBB, field@AAAAAAAA */ 8458 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8459 FETCH(r0, 1) @ r0<- aaaa (lo) 8460 FETCH(r1, 2) @ r1<- AAAA (hi) 8461 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8462 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8463 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8464 cmp r0, #0 @ is resolved entry null? 8465 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve 8466.LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0 8467 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8468 @ no-op @ acquiring load 8469 FETCH(r2, 3) @ r2<- BBBB 8470 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8471 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8472 GET_INST_OPCODE(ip) @ extract opcode from rINST 8473 GOTO_OPCODE(ip) @ jump to next instruction 8474 8475 8476/* ------------------------------ */ 8477 .balign 64 8478.L_OP_SGET_SHORT_JUMBO: /* 0x11a */ 8479/* File: armv5te/OP_SGET_SHORT_JUMBO.S */ 8480/* File: armv5te/OP_SGET_JUMBO.S */ 8481 /* 8482 * Jumbo 32-bit SGET handler. 8483 * 8484 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8485 * sget-char/jumbo, sget-short/jumbo 8486 */ 8487 /* exop vBBBB, field@AAAAAAAA */ 8488 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8489 FETCH(r0, 1) @ r0<- aaaa (lo) 8490 FETCH(r1, 2) @ r1<- AAAA (hi) 8491 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8492 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8493 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8494 cmp r0, #0 @ is resolved entry null? 8495 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve 8496.LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0 8497 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8498 @ no-op @ acquiring load 8499 FETCH(r2, 3) @ r2<- BBBB 8500 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8501 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8502 GET_INST_OPCODE(ip) @ extract opcode from rINST 8503 GOTO_OPCODE(ip) @ jump to next instruction 8504 8505 8506/* ------------------------------ */ 8507 .balign 64 8508.L_OP_SPUT_JUMBO: /* 0x11b */ 8509/* File: armv5te/OP_SPUT_JUMBO.S */ 8510 /* 8511 * Jumbo 32-bit SPUT handler. 8512 * 8513 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8514 * sput-short/jumbo 8515 */ 8516 /* exop vBBBB, field@AAAAAAAA */ 8517 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8518 FETCH(r0, 1) @ r0<- aaaa (lo) 8519 FETCH(r1, 2) @ r1<- AAAA (hi) 8520 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8521 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8522 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8523 cmp r0, #0 @ is resolved entry null? 8524 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve 8525.LOP_SPUT_JUMBO_finish: @ field ptr in r0 8526 FETCH(r2, 3) @ r2<- BBBB 8527 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8528 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8529 GET_INST_OPCODE(ip) @ extract opcode from rINST 8530 @ no-op @ releasing store 8531 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8532 GOTO_OPCODE(ip) @ jump to next instruction 8533 8534/* ------------------------------ */ 8535 .balign 64 8536.L_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 8537/* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 8538 /* 8539 * Jumbo 64-bit SPUT handler. 8540 */ 8541 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 8542 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 8543 FETCH(r1, 1) @ r1<- aaaa (lo) 8544 FETCH(r2, 2) @ r2<- AAAA (hi) 8545 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 8546 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8547 FETCH(r9, 3) @ r9<- BBBB 8548 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 8549 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8550 cmp r2, #0 @ is resolved entry null? 8551 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve 8552.LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9 8553 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8554 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 8555 GET_INST_OPCODE(r10) @ extract opcode from rINST 8556 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 8557 GOTO_OPCODE(r10) @ jump to next instruction 8558 8559/* ------------------------------ */ 8560 .balign 64 8561.L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 8562/* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 8563 /* 8564 * Jumbo 32-bit SPUT handler for objects 8565 */ 8566 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 8567 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8568 FETCH(r0, 1) @ r0<- aaaa (lo) 8569 FETCH(r1, 2) @ r1<- AAAA (hi) 8570 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8571 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8572 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8573 cmp r0, #0 @ is resolved entry null? 8574 bne .LOP_SPUT_OBJECT_JUMBO_finish @ no, continue 8575 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8576 EXPORT_PC() @ resolve() could throw, so export now 8577 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 8578 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8579 cmp r0, #0 @ success? 8580 bne .LOP_SPUT_OBJECT_JUMBO_finish @ yes, finish 8581 b common_exceptionThrown @ no, handle exception 8582 8583/* ------------------------------ */ 8584 .balign 64 8585.L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 8586/* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */ 8587/* File: armv5te/OP_SPUT_JUMBO.S */ 8588 /* 8589 * Jumbo 32-bit SPUT handler. 8590 * 8591 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8592 * sput-short/jumbo 8593 */ 8594 /* exop vBBBB, field@AAAAAAAA */ 8595 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8596 FETCH(r0, 1) @ r0<- aaaa (lo) 8597 FETCH(r1, 2) @ r1<- AAAA (hi) 8598 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8599 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8600 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8601 cmp r0, #0 @ is resolved entry null? 8602 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve 8603.LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0 8604 FETCH(r2, 3) @ r2<- BBBB 8605 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8606 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8607 GET_INST_OPCODE(ip) @ extract opcode from rINST 8608 @ no-op @ releasing store 8609 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8610 GOTO_OPCODE(ip) @ jump to next instruction 8611 8612 8613/* ------------------------------ */ 8614 .balign 64 8615.L_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 8616/* File: armv5te/OP_SPUT_BYTE_JUMBO.S */ 8617/* File: armv5te/OP_SPUT_JUMBO.S */ 8618 /* 8619 * Jumbo 32-bit SPUT handler. 8620 * 8621 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8622 * sput-short/jumbo 8623 */ 8624 /* exop vBBBB, field@AAAAAAAA */ 8625 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8626 FETCH(r0, 1) @ r0<- aaaa (lo) 8627 FETCH(r1, 2) @ r1<- AAAA (hi) 8628 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8629 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8630 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8631 cmp r0, #0 @ is resolved entry null? 8632 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve 8633.LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0 8634 FETCH(r2, 3) @ r2<- BBBB 8635 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8636 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8637 GET_INST_OPCODE(ip) @ extract opcode from rINST 8638 @ no-op @ releasing store 8639 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8640 GOTO_OPCODE(ip) @ jump to next instruction 8641 8642 8643/* ------------------------------ */ 8644 .balign 64 8645.L_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 8646/* File: armv5te/OP_SPUT_CHAR_JUMBO.S */ 8647/* File: armv5te/OP_SPUT_JUMBO.S */ 8648 /* 8649 * Jumbo 32-bit SPUT handler. 8650 * 8651 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8652 * sput-short/jumbo 8653 */ 8654 /* exop vBBBB, field@AAAAAAAA */ 8655 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8656 FETCH(r0, 1) @ r0<- aaaa (lo) 8657 FETCH(r1, 2) @ r1<- AAAA (hi) 8658 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8659 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8660 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8661 cmp r0, #0 @ is resolved entry null? 8662 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve 8663.LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0 8664 FETCH(r2, 3) @ r2<- BBBB 8665 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8666 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8667 GET_INST_OPCODE(ip) @ extract opcode from rINST 8668 @ no-op @ releasing store 8669 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8670 GOTO_OPCODE(ip) @ jump to next instruction 8671 8672 8673/* ------------------------------ */ 8674 .balign 64 8675.L_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 8676/* File: armv5te/OP_SPUT_SHORT_JUMBO.S */ 8677/* File: armv5te/OP_SPUT_JUMBO.S */ 8678 /* 8679 * Jumbo 32-bit SPUT handler. 8680 * 8681 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8682 * sput-short/jumbo 8683 */ 8684 /* exop vBBBB, field@AAAAAAAA */ 8685 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8686 FETCH(r0, 1) @ r0<- aaaa (lo) 8687 FETCH(r1, 2) @ r1<- AAAA (hi) 8688 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8689 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8690 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8691 cmp r0, #0 @ is resolved entry null? 8692 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve 8693.LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0 8694 FETCH(r2, 3) @ r2<- BBBB 8695 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8696 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8697 GET_INST_OPCODE(ip) @ extract opcode from rINST 8698 @ no-op @ releasing store 8699 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8700 GOTO_OPCODE(ip) @ jump to next instruction 8701 8702 8703/* ------------------------------ */ 8704 .balign 64 8705.L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 8706/* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */ 8707 /* 8708 * Handle a virtual method call. 8709 */ 8710 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8711 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8712 FETCH(r0, 1) @ r1<- aaaa (lo) 8713 FETCH(r1, 2) @ r1<- AAAA (hi) 8714 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8715 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8716 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8717 cmp r0, #0 @ already resolved? 8718 EXPORT_PC() @ must export for invoke 8719 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on 8720 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8721 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8722 mov r2, #METHOD_VIRTUAL @ resolver method type 8723 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8724 cmp r0, #0 @ got null? 8725 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue 8726 b common_exceptionThrown @ yes, handle exception 8727 8728/* ------------------------------ */ 8729 .balign 64 8730.L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 8731/* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */ 8732 /* 8733 * Handle a "super" method call. 8734 */ 8735 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8736 FETCH(r10, 4) @ r10<- CCCC 8737 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8738 FETCH(r0, 1) @ r1<- aaaa (lo) 8739 FETCH(r1, 2) @ r1<- AAAA (hi) 8740 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8741 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8742 GET_VREG(r2, r10) @ r2<- "this" ptr 8743 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8744 cmp r2, #0 @ null "this"? 8745 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8746 beq common_errNullObject @ null "this", throw exception 8747 cmp r0, #0 @ already resolved? 8748 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 8749 EXPORT_PC() @ must export for invoke 8750 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on 8751 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now 8752 8753/* ------------------------------ */ 8754 .balign 64 8755.L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 8756/* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */ 8757 /* 8758 * Handle a direct method call. 8759 * 8760 * (We could defer the "is 'this' pointer null" test to the common 8761 * method invocation code, and use a flag to indicate that static 8762 * calls don't count. If we do this as part of copying the arguments 8763 * out we could avoiding loading the first arg twice.) 8764 * 8765 */ 8766 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8767 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8768 FETCH(r0, 1) @ r1<- aaaa (lo) 8769 FETCH(r1, 2) @ r1<- AAAA (hi) 8770 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8771 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8772 FETCH(r10, 4) @ r10<- CCCC 8773 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8774 cmp r0, #0 @ already resolved? 8775 EXPORT_PC() @ must export for invoke 8776 GET_VREG(r2, r10) @ r2<- "this" ptr 8777 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now 8778.LOP_INVOKE_DIRECT_JUMBO_finish: 8779 cmp r2, #0 @ null "this" ref? 8780 bne common_invokeMethodJumbo @ no, continue on 8781 b common_errNullObject @ yes, throw exception 8782 8783/* ------------------------------ */ 8784 .balign 64 8785.L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 8786/* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */ 8787 /* 8788 * Handle a static method call. 8789 */ 8790 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8791 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8792 FETCH(r0, 1) @ r1<- aaaa (lo) 8793 FETCH(r1, 2) @ r1<- AAAA (hi) 8794 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8795 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8796 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8797 cmp r0, #0 @ already resolved? 8798 EXPORT_PC() @ must export for invoke 8799 bne common_invokeMethodJumbo @ yes, continue on 88000: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8801 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8802 mov r2, #METHOD_STATIC @ resolver method type 8803 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8804 cmp r0, #0 @ got null? 8805 bne common_invokeMethodJumbo @ no, continue 8806 b common_exceptionThrown @ yes, handle exception 8807 8808/* ------------------------------ */ 8809 .balign 64 8810.L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 8811/* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */ 8812 /* 8813 * Handle an interface method call. 8814 */ 8815 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8816 FETCH(r2, 4) @ r2<- CCCC 8817 FETCH(r0, 1) @ r0<- aaaa (lo) 8818 FETCH(r1, 2) @ r1<- AAAA (hi) 8819 EXPORT_PC() @ must export for invoke 8820 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8821 GET_VREG(r0, r2) @ r0<- first arg ("this") 8822 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 8823 cmp r0, #0 @ null obj? 8824 ldr r2, [rSELF, #offThread_method] @ r2<- method 8825 beq common_errNullObject @ yes, fail 8826 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 8827 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 8828 cmp r0, #0 @ failed? 8829 beq common_exceptionThrown @ yes, handle exception 8830 b common_invokeMethodJumbo @ jump to common handler 8831 8832/* ------------------------------ */ 8833 .balign 64 8834.L_OP_UNUSED_27FF: /* 0x127 */ 8835/* File: armv5te/OP_UNUSED_27FF.S */ 8836/* File: armv5te/unused.S */ 8837 bl common_abort 8838 8839 8840/* ------------------------------ */ 8841 .balign 64 8842.L_OP_UNUSED_28FF: /* 0x128 */ 8843/* File: armv5te/OP_UNUSED_28FF.S */ 8844/* File: armv5te/unused.S */ 8845 bl common_abort 8846 8847 8848/* ------------------------------ */ 8849 .balign 64 8850.L_OP_UNUSED_29FF: /* 0x129 */ 8851/* File: armv5te/OP_UNUSED_29FF.S */ 8852/* File: armv5te/unused.S */ 8853 bl common_abort 8854 8855 8856/* ------------------------------ */ 8857 .balign 64 8858.L_OP_UNUSED_2AFF: /* 0x12a */ 8859/* File: armv5te/OP_UNUSED_2AFF.S */ 8860/* File: armv5te/unused.S */ 8861 bl common_abort 8862 8863 8864/* ------------------------------ */ 8865 .balign 64 8866.L_OP_UNUSED_2BFF: /* 0x12b */ 8867/* File: armv5te/OP_UNUSED_2BFF.S */ 8868/* File: armv5te/unused.S */ 8869 bl common_abort 8870 8871 8872/* ------------------------------ */ 8873 .balign 64 8874.L_OP_UNUSED_2CFF: /* 0x12c */ 8875/* File: armv5te/OP_UNUSED_2CFF.S */ 8876/* File: armv5te/unused.S */ 8877 bl common_abort 8878 8879 8880/* ------------------------------ */ 8881 .balign 64 8882.L_OP_UNUSED_2DFF: /* 0x12d */ 8883/* File: armv5te/OP_UNUSED_2DFF.S */ 8884/* File: armv5te/unused.S */ 8885 bl common_abort 8886 8887 8888/* ------------------------------ */ 8889 .balign 64 8890.L_OP_UNUSED_2EFF: /* 0x12e */ 8891/* File: armv5te/OP_UNUSED_2EFF.S */ 8892/* File: armv5te/unused.S */ 8893 bl common_abort 8894 8895 8896/* ------------------------------ */ 8897 .balign 64 8898.L_OP_UNUSED_2FFF: /* 0x12f */ 8899/* File: armv5te/OP_UNUSED_2FFF.S */ 8900/* File: armv5te/unused.S */ 8901 bl common_abort 8902 8903 8904/* ------------------------------ */ 8905 .balign 64 8906.L_OP_UNUSED_30FF: /* 0x130 */ 8907/* File: armv5te/OP_UNUSED_30FF.S */ 8908/* File: armv5te/unused.S */ 8909 bl common_abort 8910 8911 8912/* ------------------------------ */ 8913 .balign 64 8914.L_OP_UNUSED_31FF: /* 0x131 */ 8915/* File: armv5te/OP_UNUSED_31FF.S */ 8916/* File: armv5te/unused.S */ 8917 bl common_abort 8918 8919 8920/* ------------------------------ */ 8921 .balign 64 8922.L_OP_UNUSED_32FF: /* 0x132 */ 8923/* File: armv5te/OP_UNUSED_32FF.S */ 8924/* File: armv5te/unused.S */ 8925 bl common_abort 8926 8927 8928/* ------------------------------ */ 8929 .balign 64 8930.L_OP_UNUSED_33FF: /* 0x133 */ 8931/* File: armv5te/OP_UNUSED_33FF.S */ 8932/* File: armv5te/unused.S */ 8933 bl common_abort 8934 8935 8936/* ------------------------------ */ 8937 .balign 64 8938.L_OP_UNUSED_34FF: /* 0x134 */ 8939/* File: armv5te/OP_UNUSED_34FF.S */ 8940/* File: armv5te/unused.S */ 8941 bl common_abort 8942 8943 8944/* ------------------------------ */ 8945 .balign 64 8946.L_OP_UNUSED_35FF: /* 0x135 */ 8947/* File: armv5te/OP_UNUSED_35FF.S */ 8948/* File: armv5te/unused.S */ 8949 bl common_abort 8950 8951 8952/* ------------------------------ */ 8953 .balign 64 8954.L_OP_UNUSED_36FF: /* 0x136 */ 8955/* File: armv5te/OP_UNUSED_36FF.S */ 8956/* File: armv5te/unused.S */ 8957 bl common_abort 8958 8959 8960/* ------------------------------ */ 8961 .balign 64 8962.L_OP_UNUSED_37FF: /* 0x137 */ 8963/* File: armv5te/OP_UNUSED_37FF.S */ 8964/* File: armv5te/unused.S */ 8965 bl common_abort 8966 8967 8968/* ------------------------------ */ 8969 .balign 64 8970.L_OP_UNUSED_38FF: /* 0x138 */ 8971/* File: armv5te/OP_UNUSED_38FF.S */ 8972/* File: armv5te/unused.S */ 8973 bl common_abort 8974 8975 8976/* ------------------------------ */ 8977 .balign 64 8978.L_OP_UNUSED_39FF: /* 0x139 */ 8979/* File: armv5te/OP_UNUSED_39FF.S */ 8980/* File: armv5te/unused.S */ 8981 bl common_abort 8982 8983 8984/* ------------------------------ */ 8985 .balign 64 8986.L_OP_UNUSED_3AFF: /* 0x13a */ 8987/* File: armv5te/OP_UNUSED_3AFF.S */ 8988/* File: armv5te/unused.S */ 8989 bl common_abort 8990 8991 8992/* ------------------------------ */ 8993 .balign 64 8994.L_OP_UNUSED_3BFF: /* 0x13b */ 8995/* File: armv5te/OP_UNUSED_3BFF.S */ 8996/* File: armv5te/unused.S */ 8997 bl common_abort 8998 8999 9000/* ------------------------------ */ 9001 .balign 64 9002.L_OP_UNUSED_3CFF: /* 0x13c */ 9003/* File: armv5te/OP_UNUSED_3CFF.S */ 9004/* File: armv5te/unused.S */ 9005 bl common_abort 9006 9007 9008/* ------------------------------ */ 9009 .balign 64 9010.L_OP_UNUSED_3DFF: /* 0x13d */ 9011/* File: armv5te/OP_UNUSED_3DFF.S */ 9012/* File: armv5te/unused.S */ 9013 bl common_abort 9014 9015 9016/* ------------------------------ */ 9017 .balign 64 9018.L_OP_UNUSED_3EFF: /* 0x13e */ 9019/* File: armv5te/OP_UNUSED_3EFF.S */ 9020/* File: armv5te/unused.S */ 9021 bl common_abort 9022 9023 9024/* ------------------------------ */ 9025 .balign 64 9026.L_OP_UNUSED_3FFF: /* 0x13f */ 9027/* File: armv5te/OP_UNUSED_3FFF.S */ 9028/* File: armv5te/unused.S */ 9029 bl common_abort 9030 9031 9032/* ------------------------------ */ 9033 .balign 64 9034.L_OP_UNUSED_40FF: /* 0x140 */ 9035/* File: armv5te/OP_UNUSED_40FF.S */ 9036/* File: armv5te/unused.S */ 9037 bl common_abort 9038 9039 9040/* ------------------------------ */ 9041 .balign 64 9042.L_OP_UNUSED_41FF: /* 0x141 */ 9043/* File: armv5te/OP_UNUSED_41FF.S */ 9044/* File: armv5te/unused.S */ 9045 bl common_abort 9046 9047 9048/* ------------------------------ */ 9049 .balign 64 9050.L_OP_UNUSED_42FF: /* 0x142 */ 9051/* File: armv5te/OP_UNUSED_42FF.S */ 9052/* File: armv5te/unused.S */ 9053 bl common_abort 9054 9055 9056/* ------------------------------ */ 9057 .balign 64 9058.L_OP_UNUSED_43FF: /* 0x143 */ 9059/* File: armv5te/OP_UNUSED_43FF.S */ 9060/* File: armv5te/unused.S */ 9061 bl common_abort 9062 9063 9064/* ------------------------------ */ 9065 .balign 64 9066.L_OP_UNUSED_44FF: /* 0x144 */ 9067/* File: armv5te/OP_UNUSED_44FF.S */ 9068/* File: armv5te/unused.S */ 9069 bl common_abort 9070 9071 9072/* ------------------------------ */ 9073 .balign 64 9074.L_OP_UNUSED_45FF: /* 0x145 */ 9075/* File: armv5te/OP_UNUSED_45FF.S */ 9076/* File: armv5te/unused.S */ 9077 bl common_abort 9078 9079 9080/* ------------------------------ */ 9081 .balign 64 9082.L_OP_UNUSED_46FF: /* 0x146 */ 9083/* File: armv5te/OP_UNUSED_46FF.S */ 9084/* File: armv5te/unused.S */ 9085 bl common_abort 9086 9087 9088/* ------------------------------ */ 9089 .balign 64 9090.L_OP_UNUSED_47FF: /* 0x147 */ 9091/* File: armv5te/OP_UNUSED_47FF.S */ 9092/* File: armv5te/unused.S */ 9093 bl common_abort 9094 9095 9096/* ------------------------------ */ 9097 .balign 64 9098.L_OP_UNUSED_48FF: /* 0x148 */ 9099/* File: armv5te/OP_UNUSED_48FF.S */ 9100/* File: armv5te/unused.S */ 9101 bl common_abort 9102 9103 9104/* ------------------------------ */ 9105 .balign 64 9106.L_OP_UNUSED_49FF: /* 0x149 */ 9107/* File: armv5te/OP_UNUSED_49FF.S */ 9108/* File: armv5te/unused.S */ 9109 bl common_abort 9110 9111 9112/* ------------------------------ */ 9113 .balign 64 9114.L_OP_UNUSED_4AFF: /* 0x14a */ 9115/* File: armv5te/OP_UNUSED_4AFF.S */ 9116/* File: armv5te/unused.S */ 9117 bl common_abort 9118 9119 9120/* ------------------------------ */ 9121 .balign 64 9122.L_OP_UNUSED_4BFF: /* 0x14b */ 9123/* File: armv5te/OP_UNUSED_4BFF.S */ 9124/* File: armv5te/unused.S */ 9125 bl common_abort 9126 9127 9128/* ------------------------------ */ 9129 .balign 64 9130.L_OP_UNUSED_4CFF: /* 0x14c */ 9131/* File: armv5te/OP_UNUSED_4CFF.S */ 9132/* File: armv5te/unused.S */ 9133 bl common_abort 9134 9135 9136/* ------------------------------ */ 9137 .balign 64 9138.L_OP_UNUSED_4DFF: /* 0x14d */ 9139/* File: armv5te/OP_UNUSED_4DFF.S */ 9140/* File: armv5te/unused.S */ 9141 bl common_abort 9142 9143 9144/* ------------------------------ */ 9145 .balign 64 9146.L_OP_UNUSED_4EFF: /* 0x14e */ 9147/* File: armv5te/OP_UNUSED_4EFF.S */ 9148/* File: armv5te/unused.S */ 9149 bl common_abort 9150 9151 9152/* ------------------------------ */ 9153 .balign 64 9154.L_OP_UNUSED_4FFF: /* 0x14f */ 9155/* File: armv5te/OP_UNUSED_4FFF.S */ 9156/* File: armv5te/unused.S */ 9157 bl common_abort 9158 9159 9160/* ------------------------------ */ 9161 .balign 64 9162.L_OP_UNUSED_50FF: /* 0x150 */ 9163/* File: armv5te/OP_UNUSED_50FF.S */ 9164/* File: armv5te/unused.S */ 9165 bl common_abort 9166 9167 9168/* ------------------------------ */ 9169 .balign 64 9170.L_OP_UNUSED_51FF: /* 0x151 */ 9171/* File: armv5te/OP_UNUSED_51FF.S */ 9172/* File: armv5te/unused.S */ 9173 bl common_abort 9174 9175 9176/* ------------------------------ */ 9177 .balign 64 9178.L_OP_UNUSED_52FF: /* 0x152 */ 9179/* File: armv5te/OP_UNUSED_52FF.S */ 9180/* File: armv5te/unused.S */ 9181 bl common_abort 9182 9183 9184/* ------------------------------ */ 9185 .balign 64 9186.L_OP_UNUSED_53FF: /* 0x153 */ 9187/* File: armv5te/OP_UNUSED_53FF.S */ 9188/* File: armv5te/unused.S */ 9189 bl common_abort 9190 9191 9192/* ------------------------------ */ 9193 .balign 64 9194.L_OP_UNUSED_54FF: /* 0x154 */ 9195/* File: armv5te/OP_UNUSED_54FF.S */ 9196/* File: armv5te/unused.S */ 9197 bl common_abort 9198 9199 9200/* ------------------------------ */ 9201 .balign 64 9202.L_OP_UNUSED_55FF: /* 0x155 */ 9203/* File: armv5te/OP_UNUSED_55FF.S */ 9204/* File: armv5te/unused.S */ 9205 bl common_abort 9206 9207 9208/* ------------------------------ */ 9209 .balign 64 9210.L_OP_UNUSED_56FF: /* 0x156 */ 9211/* File: armv5te/OP_UNUSED_56FF.S */ 9212/* File: armv5te/unused.S */ 9213 bl common_abort 9214 9215 9216/* ------------------------------ */ 9217 .balign 64 9218.L_OP_UNUSED_57FF: /* 0x157 */ 9219/* File: armv5te/OP_UNUSED_57FF.S */ 9220/* File: armv5te/unused.S */ 9221 bl common_abort 9222 9223 9224/* ------------------------------ */ 9225 .balign 64 9226.L_OP_UNUSED_58FF: /* 0x158 */ 9227/* File: armv5te/OP_UNUSED_58FF.S */ 9228/* File: armv5te/unused.S */ 9229 bl common_abort 9230 9231 9232/* ------------------------------ */ 9233 .balign 64 9234.L_OP_UNUSED_59FF: /* 0x159 */ 9235/* File: armv5te/OP_UNUSED_59FF.S */ 9236/* File: armv5te/unused.S */ 9237 bl common_abort 9238 9239 9240/* ------------------------------ */ 9241 .balign 64 9242.L_OP_UNUSED_5AFF: /* 0x15a */ 9243/* File: armv5te/OP_UNUSED_5AFF.S */ 9244/* File: armv5te/unused.S */ 9245 bl common_abort 9246 9247 9248/* ------------------------------ */ 9249 .balign 64 9250.L_OP_UNUSED_5BFF: /* 0x15b */ 9251/* File: armv5te/OP_UNUSED_5BFF.S */ 9252/* File: armv5te/unused.S */ 9253 bl common_abort 9254 9255 9256/* ------------------------------ */ 9257 .balign 64 9258.L_OP_UNUSED_5CFF: /* 0x15c */ 9259/* File: armv5te/OP_UNUSED_5CFF.S */ 9260/* File: armv5te/unused.S */ 9261 bl common_abort 9262 9263 9264/* ------------------------------ */ 9265 .balign 64 9266.L_OP_UNUSED_5DFF: /* 0x15d */ 9267/* File: armv5te/OP_UNUSED_5DFF.S */ 9268/* File: armv5te/unused.S */ 9269 bl common_abort 9270 9271 9272/* ------------------------------ */ 9273 .balign 64 9274.L_OP_UNUSED_5EFF: /* 0x15e */ 9275/* File: armv5te/OP_UNUSED_5EFF.S */ 9276/* File: armv5te/unused.S */ 9277 bl common_abort 9278 9279 9280/* ------------------------------ */ 9281 .balign 64 9282.L_OP_UNUSED_5FFF: /* 0x15f */ 9283/* File: armv5te/OP_UNUSED_5FFF.S */ 9284/* File: armv5te/unused.S */ 9285 bl common_abort 9286 9287 9288/* ------------------------------ */ 9289 .balign 64 9290.L_OP_UNUSED_60FF: /* 0x160 */ 9291/* File: armv5te/OP_UNUSED_60FF.S */ 9292/* File: armv5te/unused.S */ 9293 bl common_abort 9294 9295 9296/* ------------------------------ */ 9297 .balign 64 9298.L_OP_UNUSED_61FF: /* 0x161 */ 9299/* File: armv5te/OP_UNUSED_61FF.S */ 9300/* File: armv5te/unused.S */ 9301 bl common_abort 9302 9303 9304/* ------------------------------ */ 9305 .balign 64 9306.L_OP_UNUSED_62FF: /* 0x162 */ 9307/* File: armv5te/OP_UNUSED_62FF.S */ 9308/* File: armv5te/unused.S */ 9309 bl common_abort 9310 9311 9312/* ------------------------------ */ 9313 .balign 64 9314.L_OP_UNUSED_63FF: /* 0x163 */ 9315/* File: armv5te/OP_UNUSED_63FF.S */ 9316/* File: armv5te/unused.S */ 9317 bl common_abort 9318 9319 9320/* ------------------------------ */ 9321 .balign 64 9322.L_OP_UNUSED_64FF: /* 0x164 */ 9323/* File: armv5te/OP_UNUSED_64FF.S */ 9324/* File: armv5te/unused.S */ 9325 bl common_abort 9326 9327 9328/* ------------------------------ */ 9329 .balign 64 9330.L_OP_UNUSED_65FF: /* 0x165 */ 9331/* File: armv5te/OP_UNUSED_65FF.S */ 9332/* File: armv5te/unused.S */ 9333 bl common_abort 9334 9335 9336/* ------------------------------ */ 9337 .balign 64 9338.L_OP_UNUSED_66FF: /* 0x166 */ 9339/* File: armv5te/OP_UNUSED_66FF.S */ 9340/* File: armv5te/unused.S */ 9341 bl common_abort 9342 9343 9344/* ------------------------------ */ 9345 .balign 64 9346.L_OP_UNUSED_67FF: /* 0x167 */ 9347/* File: armv5te/OP_UNUSED_67FF.S */ 9348/* File: armv5te/unused.S */ 9349 bl common_abort 9350 9351 9352/* ------------------------------ */ 9353 .balign 64 9354.L_OP_UNUSED_68FF: /* 0x168 */ 9355/* File: armv5te/OP_UNUSED_68FF.S */ 9356/* File: armv5te/unused.S */ 9357 bl common_abort 9358 9359 9360/* ------------------------------ */ 9361 .balign 64 9362.L_OP_UNUSED_69FF: /* 0x169 */ 9363/* File: armv5te/OP_UNUSED_69FF.S */ 9364/* File: armv5te/unused.S */ 9365 bl common_abort 9366 9367 9368/* ------------------------------ */ 9369 .balign 64 9370.L_OP_UNUSED_6AFF: /* 0x16a */ 9371/* File: armv5te/OP_UNUSED_6AFF.S */ 9372/* File: armv5te/unused.S */ 9373 bl common_abort 9374 9375 9376/* ------------------------------ */ 9377 .balign 64 9378.L_OP_UNUSED_6BFF: /* 0x16b */ 9379/* File: armv5te/OP_UNUSED_6BFF.S */ 9380/* File: armv5te/unused.S */ 9381 bl common_abort 9382 9383 9384/* ------------------------------ */ 9385 .balign 64 9386.L_OP_UNUSED_6CFF: /* 0x16c */ 9387/* File: armv5te/OP_UNUSED_6CFF.S */ 9388/* File: armv5te/unused.S */ 9389 bl common_abort 9390 9391 9392/* ------------------------------ */ 9393 .balign 64 9394.L_OP_UNUSED_6DFF: /* 0x16d */ 9395/* File: armv5te/OP_UNUSED_6DFF.S */ 9396/* File: armv5te/unused.S */ 9397 bl common_abort 9398 9399 9400/* ------------------------------ */ 9401 .balign 64 9402.L_OP_UNUSED_6EFF: /* 0x16e */ 9403/* File: armv5te/OP_UNUSED_6EFF.S */ 9404/* File: armv5te/unused.S */ 9405 bl common_abort 9406 9407 9408/* ------------------------------ */ 9409 .balign 64 9410.L_OP_UNUSED_6FFF: /* 0x16f */ 9411/* File: armv5te/OP_UNUSED_6FFF.S */ 9412/* File: armv5te/unused.S */ 9413 bl common_abort 9414 9415 9416/* ------------------------------ */ 9417 .balign 64 9418.L_OP_UNUSED_70FF: /* 0x170 */ 9419/* File: armv5te/OP_UNUSED_70FF.S */ 9420/* File: armv5te/unused.S */ 9421 bl common_abort 9422 9423 9424/* ------------------------------ */ 9425 .balign 64 9426.L_OP_UNUSED_71FF: /* 0x171 */ 9427/* File: armv5te/OP_UNUSED_71FF.S */ 9428/* File: armv5te/unused.S */ 9429 bl common_abort 9430 9431 9432/* ------------------------------ */ 9433 .balign 64 9434.L_OP_UNUSED_72FF: /* 0x172 */ 9435/* File: armv5te/OP_UNUSED_72FF.S */ 9436/* File: armv5te/unused.S */ 9437 bl common_abort 9438 9439 9440/* ------------------------------ */ 9441 .balign 64 9442.L_OP_UNUSED_73FF: /* 0x173 */ 9443/* File: armv5te/OP_UNUSED_73FF.S */ 9444/* File: armv5te/unused.S */ 9445 bl common_abort 9446 9447 9448/* ------------------------------ */ 9449 .balign 64 9450.L_OP_UNUSED_74FF: /* 0x174 */ 9451/* File: armv5te/OP_UNUSED_74FF.S */ 9452/* File: armv5te/unused.S */ 9453 bl common_abort 9454 9455 9456/* ------------------------------ */ 9457 .balign 64 9458.L_OP_UNUSED_75FF: /* 0x175 */ 9459/* File: armv5te/OP_UNUSED_75FF.S */ 9460/* File: armv5te/unused.S */ 9461 bl common_abort 9462 9463 9464/* ------------------------------ */ 9465 .balign 64 9466.L_OP_UNUSED_76FF: /* 0x176 */ 9467/* File: armv5te/OP_UNUSED_76FF.S */ 9468/* File: armv5te/unused.S */ 9469 bl common_abort 9470 9471 9472/* ------------------------------ */ 9473 .balign 64 9474.L_OP_UNUSED_77FF: /* 0x177 */ 9475/* File: armv5te/OP_UNUSED_77FF.S */ 9476/* File: armv5te/unused.S */ 9477 bl common_abort 9478 9479 9480/* ------------------------------ */ 9481 .balign 64 9482.L_OP_UNUSED_78FF: /* 0x178 */ 9483/* File: armv5te/OP_UNUSED_78FF.S */ 9484/* File: armv5te/unused.S */ 9485 bl common_abort 9486 9487 9488/* ------------------------------ */ 9489 .balign 64 9490.L_OP_UNUSED_79FF: /* 0x179 */ 9491/* File: armv5te/OP_UNUSED_79FF.S */ 9492/* File: armv5te/unused.S */ 9493 bl common_abort 9494 9495 9496/* ------------------------------ */ 9497 .balign 64 9498.L_OP_UNUSED_7AFF: /* 0x17a */ 9499/* File: armv5te/OP_UNUSED_7AFF.S */ 9500/* File: armv5te/unused.S */ 9501 bl common_abort 9502 9503 9504/* ------------------------------ */ 9505 .balign 64 9506.L_OP_UNUSED_7BFF: /* 0x17b */ 9507/* File: armv5te/OP_UNUSED_7BFF.S */ 9508/* File: armv5te/unused.S */ 9509 bl common_abort 9510 9511 9512/* ------------------------------ */ 9513 .balign 64 9514.L_OP_UNUSED_7CFF: /* 0x17c */ 9515/* File: armv5te/OP_UNUSED_7CFF.S */ 9516/* File: armv5te/unused.S */ 9517 bl common_abort 9518 9519 9520/* ------------------------------ */ 9521 .balign 64 9522.L_OP_UNUSED_7DFF: /* 0x17d */ 9523/* File: armv5te/OP_UNUSED_7DFF.S */ 9524/* File: armv5te/unused.S */ 9525 bl common_abort 9526 9527 9528/* ------------------------------ */ 9529 .balign 64 9530.L_OP_UNUSED_7EFF: /* 0x17e */ 9531/* File: armv5te/OP_UNUSED_7EFF.S */ 9532/* File: armv5te/unused.S */ 9533 bl common_abort 9534 9535 9536/* ------------------------------ */ 9537 .balign 64 9538.L_OP_UNUSED_7FFF: /* 0x17f */ 9539/* File: armv5te/OP_UNUSED_7FFF.S */ 9540/* File: armv5te/unused.S */ 9541 bl common_abort 9542 9543 9544/* ------------------------------ */ 9545 .balign 64 9546.L_OP_UNUSED_80FF: /* 0x180 */ 9547/* File: armv5te/OP_UNUSED_80FF.S */ 9548/* File: armv5te/unused.S */ 9549 bl common_abort 9550 9551 9552/* ------------------------------ */ 9553 .balign 64 9554.L_OP_UNUSED_81FF: /* 0x181 */ 9555/* File: armv5te/OP_UNUSED_81FF.S */ 9556/* File: armv5te/unused.S */ 9557 bl common_abort 9558 9559 9560/* ------------------------------ */ 9561 .balign 64 9562.L_OP_UNUSED_82FF: /* 0x182 */ 9563/* File: armv5te/OP_UNUSED_82FF.S */ 9564/* File: armv5te/unused.S */ 9565 bl common_abort 9566 9567 9568/* ------------------------------ */ 9569 .balign 64 9570.L_OP_UNUSED_83FF: /* 0x183 */ 9571/* File: armv5te/OP_UNUSED_83FF.S */ 9572/* File: armv5te/unused.S */ 9573 bl common_abort 9574 9575 9576/* ------------------------------ */ 9577 .balign 64 9578.L_OP_UNUSED_84FF: /* 0x184 */ 9579/* File: armv5te/OP_UNUSED_84FF.S */ 9580/* File: armv5te/unused.S */ 9581 bl common_abort 9582 9583 9584/* ------------------------------ */ 9585 .balign 64 9586.L_OP_UNUSED_85FF: /* 0x185 */ 9587/* File: armv5te/OP_UNUSED_85FF.S */ 9588/* File: armv5te/unused.S */ 9589 bl common_abort 9590 9591 9592/* ------------------------------ */ 9593 .balign 64 9594.L_OP_UNUSED_86FF: /* 0x186 */ 9595/* File: armv5te/OP_UNUSED_86FF.S */ 9596/* File: armv5te/unused.S */ 9597 bl common_abort 9598 9599 9600/* ------------------------------ */ 9601 .balign 64 9602.L_OP_UNUSED_87FF: /* 0x187 */ 9603/* File: armv5te/OP_UNUSED_87FF.S */ 9604/* File: armv5te/unused.S */ 9605 bl common_abort 9606 9607 9608/* ------------------------------ */ 9609 .balign 64 9610.L_OP_UNUSED_88FF: /* 0x188 */ 9611/* File: armv5te/OP_UNUSED_88FF.S */ 9612/* File: armv5te/unused.S */ 9613 bl common_abort 9614 9615 9616/* ------------------------------ */ 9617 .balign 64 9618.L_OP_UNUSED_89FF: /* 0x189 */ 9619/* File: armv5te/OP_UNUSED_89FF.S */ 9620/* File: armv5te/unused.S */ 9621 bl common_abort 9622 9623 9624/* ------------------------------ */ 9625 .balign 64 9626.L_OP_UNUSED_8AFF: /* 0x18a */ 9627/* File: armv5te/OP_UNUSED_8AFF.S */ 9628/* File: armv5te/unused.S */ 9629 bl common_abort 9630 9631 9632/* ------------------------------ */ 9633 .balign 64 9634.L_OP_UNUSED_8BFF: /* 0x18b */ 9635/* File: armv5te/OP_UNUSED_8BFF.S */ 9636/* File: armv5te/unused.S */ 9637 bl common_abort 9638 9639 9640/* ------------------------------ */ 9641 .balign 64 9642.L_OP_UNUSED_8CFF: /* 0x18c */ 9643/* File: armv5te/OP_UNUSED_8CFF.S */ 9644/* File: armv5te/unused.S */ 9645 bl common_abort 9646 9647 9648/* ------------------------------ */ 9649 .balign 64 9650.L_OP_UNUSED_8DFF: /* 0x18d */ 9651/* File: armv5te/OP_UNUSED_8DFF.S */ 9652/* File: armv5te/unused.S */ 9653 bl common_abort 9654 9655 9656/* ------------------------------ */ 9657 .balign 64 9658.L_OP_UNUSED_8EFF: /* 0x18e */ 9659/* File: armv5te/OP_UNUSED_8EFF.S */ 9660/* File: armv5te/unused.S */ 9661 bl common_abort 9662 9663 9664/* ------------------------------ */ 9665 .balign 64 9666.L_OP_UNUSED_8FFF: /* 0x18f */ 9667/* File: armv5te/OP_UNUSED_8FFF.S */ 9668/* File: armv5te/unused.S */ 9669 bl common_abort 9670 9671 9672/* ------------------------------ */ 9673 .balign 64 9674.L_OP_UNUSED_90FF: /* 0x190 */ 9675/* File: armv5te/OP_UNUSED_90FF.S */ 9676/* File: armv5te/unused.S */ 9677 bl common_abort 9678 9679 9680/* ------------------------------ */ 9681 .balign 64 9682.L_OP_UNUSED_91FF: /* 0x191 */ 9683/* File: armv5te/OP_UNUSED_91FF.S */ 9684/* File: armv5te/unused.S */ 9685 bl common_abort 9686 9687 9688/* ------------------------------ */ 9689 .balign 64 9690.L_OP_UNUSED_92FF: /* 0x192 */ 9691/* File: armv5te/OP_UNUSED_92FF.S */ 9692/* File: armv5te/unused.S */ 9693 bl common_abort 9694 9695 9696/* ------------------------------ */ 9697 .balign 64 9698.L_OP_UNUSED_93FF: /* 0x193 */ 9699/* File: armv5te/OP_UNUSED_93FF.S */ 9700/* File: armv5te/unused.S */ 9701 bl common_abort 9702 9703 9704/* ------------------------------ */ 9705 .balign 64 9706.L_OP_UNUSED_94FF: /* 0x194 */ 9707/* File: armv5te/OP_UNUSED_94FF.S */ 9708/* File: armv5te/unused.S */ 9709 bl common_abort 9710 9711 9712/* ------------------------------ */ 9713 .balign 64 9714.L_OP_UNUSED_95FF: /* 0x195 */ 9715/* File: armv5te/OP_UNUSED_95FF.S */ 9716/* File: armv5te/unused.S */ 9717 bl common_abort 9718 9719 9720/* ------------------------------ */ 9721 .balign 64 9722.L_OP_UNUSED_96FF: /* 0x196 */ 9723/* File: armv5te/OP_UNUSED_96FF.S */ 9724/* File: armv5te/unused.S */ 9725 bl common_abort 9726 9727 9728/* ------------------------------ */ 9729 .balign 64 9730.L_OP_UNUSED_97FF: /* 0x197 */ 9731/* File: armv5te/OP_UNUSED_97FF.S */ 9732/* File: armv5te/unused.S */ 9733 bl common_abort 9734 9735 9736/* ------------------------------ */ 9737 .balign 64 9738.L_OP_UNUSED_98FF: /* 0x198 */ 9739/* File: armv5te/OP_UNUSED_98FF.S */ 9740/* File: armv5te/unused.S */ 9741 bl common_abort 9742 9743 9744/* ------------------------------ */ 9745 .balign 64 9746.L_OP_UNUSED_99FF: /* 0x199 */ 9747/* File: armv5te/OP_UNUSED_99FF.S */ 9748/* File: armv5te/unused.S */ 9749 bl common_abort 9750 9751 9752/* ------------------------------ */ 9753 .balign 64 9754.L_OP_UNUSED_9AFF: /* 0x19a */ 9755/* File: armv5te/OP_UNUSED_9AFF.S */ 9756/* File: armv5te/unused.S */ 9757 bl common_abort 9758 9759 9760/* ------------------------------ */ 9761 .balign 64 9762.L_OP_UNUSED_9BFF: /* 0x19b */ 9763/* File: armv5te/OP_UNUSED_9BFF.S */ 9764/* File: armv5te/unused.S */ 9765 bl common_abort 9766 9767 9768/* ------------------------------ */ 9769 .balign 64 9770.L_OP_UNUSED_9CFF: /* 0x19c */ 9771/* File: armv5te/OP_UNUSED_9CFF.S */ 9772/* File: armv5te/unused.S */ 9773 bl common_abort 9774 9775 9776/* ------------------------------ */ 9777 .balign 64 9778.L_OP_UNUSED_9DFF: /* 0x19d */ 9779/* File: armv5te/OP_UNUSED_9DFF.S */ 9780/* File: armv5te/unused.S */ 9781 bl common_abort 9782 9783 9784/* ------------------------------ */ 9785 .balign 64 9786.L_OP_UNUSED_9EFF: /* 0x19e */ 9787/* File: armv5te/OP_UNUSED_9EFF.S */ 9788/* File: armv5te/unused.S */ 9789 bl common_abort 9790 9791 9792/* ------------------------------ */ 9793 .balign 64 9794.L_OP_UNUSED_9FFF: /* 0x19f */ 9795/* File: armv5te/OP_UNUSED_9FFF.S */ 9796/* File: armv5te/unused.S */ 9797 bl common_abort 9798 9799 9800/* ------------------------------ */ 9801 .balign 64 9802.L_OP_UNUSED_A0FF: /* 0x1a0 */ 9803/* File: armv5te/OP_UNUSED_A0FF.S */ 9804/* File: armv5te/unused.S */ 9805 bl common_abort 9806 9807 9808/* ------------------------------ */ 9809 .balign 64 9810.L_OP_UNUSED_A1FF: /* 0x1a1 */ 9811/* File: armv5te/OP_UNUSED_A1FF.S */ 9812/* File: armv5te/unused.S */ 9813 bl common_abort 9814 9815 9816/* ------------------------------ */ 9817 .balign 64 9818.L_OP_UNUSED_A2FF: /* 0x1a2 */ 9819/* File: armv5te/OP_UNUSED_A2FF.S */ 9820/* File: armv5te/unused.S */ 9821 bl common_abort 9822 9823 9824/* ------------------------------ */ 9825 .balign 64 9826.L_OP_UNUSED_A3FF: /* 0x1a3 */ 9827/* File: armv5te/OP_UNUSED_A3FF.S */ 9828/* File: armv5te/unused.S */ 9829 bl common_abort 9830 9831 9832/* ------------------------------ */ 9833 .balign 64 9834.L_OP_UNUSED_A4FF: /* 0x1a4 */ 9835/* File: armv5te/OP_UNUSED_A4FF.S */ 9836/* File: armv5te/unused.S */ 9837 bl common_abort 9838 9839 9840/* ------------------------------ */ 9841 .balign 64 9842.L_OP_UNUSED_A5FF: /* 0x1a5 */ 9843/* File: armv5te/OP_UNUSED_A5FF.S */ 9844/* File: armv5te/unused.S */ 9845 bl common_abort 9846 9847 9848/* ------------------------------ */ 9849 .balign 64 9850.L_OP_UNUSED_A6FF: /* 0x1a6 */ 9851/* File: armv5te/OP_UNUSED_A6FF.S */ 9852/* File: armv5te/unused.S */ 9853 bl common_abort 9854 9855 9856/* ------------------------------ */ 9857 .balign 64 9858.L_OP_UNUSED_A7FF: /* 0x1a7 */ 9859/* File: armv5te/OP_UNUSED_A7FF.S */ 9860/* File: armv5te/unused.S */ 9861 bl common_abort 9862 9863 9864/* ------------------------------ */ 9865 .balign 64 9866.L_OP_UNUSED_A8FF: /* 0x1a8 */ 9867/* File: armv5te/OP_UNUSED_A8FF.S */ 9868/* File: armv5te/unused.S */ 9869 bl common_abort 9870 9871 9872/* ------------------------------ */ 9873 .balign 64 9874.L_OP_UNUSED_A9FF: /* 0x1a9 */ 9875/* File: armv5te/OP_UNUSED_A9FF.S */ 9876/* File: armv5te/unused.S */ 9877 bl common_abort 9878 9879 9880/* ------------------------------ */ 9881 .balign 64 9882.L_OP_UNUSED_AAFF: /* 0x1aa */ 9883/* File: armv5te/OP_UNUSED_AAFF.S */ 9884/* File: armv5te/unused.S */ 9885 bl common_abort 9886 9887 9888/* ------------------------------ */ 9889 .balign 64 9890.L_OP_UNUSED_ABFF: /* 0x1ab */ 9891/* File: armv5te/OP_UNUSED_ABFF.S */ 9892/* File: armv5te/unused.S */ 9893 bl common_abort 9894 9895 9896/* ------------------------------ */ 9897 .balign 64 9898.L_OP_UNUSED_ACFF: /* 0x1ac */ 9899/* File: armv5te/OP_UNUSED_ACFF.S */ 9900/* File: armv5te/unused.S */ 9901 bl common_abort 9902 9903 9904/* ------------------------------ */ 9905 .balign 64 9906.L_OP_UNUSED_ADFF: /* 0x1ad */ 9907/* File: armv5te/OP_UNUSED_ADFF.S */ 9908/* File: armv5te/unused.S */ 9909 bl common_abort 9910 9911 9912/* ------------------------------ */ 9913 .balign 64 9914.L_OP_UNUSED_AEFF: /* 0x1ae */ 9915/* File: armv5te/OP_UNUSED_AEFF.S */ 9916/* File: armv5te/unused.S */ 9917 bl common_abort 9918 9919 9920/* ------------------------------ */ 9921 .balign 64 9922.L_OP_UNUSED_AFFF: /* 0x1af */ 9923/* File: armv5te/OP_UNUSED_AFFF.S */ 9924/* File: armv5te/unused.S */ 9925 bl common_abort 9926 9927 9928/* ------------------------------ */ 9929 .balign 64 9930.L_OP_UNUSED_B0FF: /* 0x1b0 */ 9931/* File: armv5te/OP_UNUSED_B0FF.S */ 9932/* File: armv5te/unused.S */ 9933 bl common_abort 9934 9935 9936/* ------------------------------ */ 9937 .balign 64 9938.L_OP_UNUSED_B1FF: /* 0x1b1 */ 9939/* File: armv5te/OP_UNUSED_B1FF.S */ 9940/* File: armv5te/unused.S */ 9941 bl common_abort 9942 9943 9944/* ------------------------------ */ 9945 .balign 64 9946.L_OP_UNUSED_B2FF: /* 0x1b2 */ 9947/* File: armv5te/OP_UNUSED_B2FF.S */ 9948/* File: armv5te/unused.S */ 9949 bl common_abort 9950 9951 9952/* ------------------------------ */ 9953 .balign 64 9954.L_OP_UNUSED_B3FF: /* 0x1b3 */ 9955/* File: armv5te/OP_UNUSED_B3FF.S */ 9956/* File: armv5te/unused.S */ 9957 bl common_abort 9958 9959 9960/* ------------------------------ */ 9961 .balign 64 9962.L_OP_UNUSED_B4FF: /* 0x1b4 */ 9963/* File: armv5te/OP_UNUSED_B4FF.S */ 9964/* File: armv5te/unused.S */ 9965 bl common_abort 9966 9967 9968/* ------------------------------ */ 9969 .balign 64 9970.L_OP_UNUSED_B5FF: /* 0x1b5 */ 9971/* File: armv5te/OP_UNUSED_B5FF.S */ 9972/* File: armv5te/unused.S */ 9973 bl common_abort 9974 9975 9976/* ------------------------------ */ 9977 .balign 64 9978.L_OP_UNUSED_B6FF: /* 0x1b6 */ 9979/* File: armv5te/OP_UNUSED_B6FF.S */ 9980/* File: armv5te/unused.S */ 9981 bl common_abort 9982 9983 9984/* ------------------------------ */ 9985 .balign 64 9986.L_OP_UNUSED_B7FF: /* 0x1b7 */ 9987/* File: armv5te/OP_UNUSED_B7FF.S */ 9988/* File: armv5te/unused.S */ 9989 bl common_abort 9990 9991 9992/* ------------------------------ */ 9993 .balign 64 9994.L_OP_UNUSED_B8FF: /* 0x1b8 */ 9995/* File: armv5te/OP_UNUSED_B8FF.S */ 9996/* File: armv5te/unused.S */ 9997 bl common_abort 9998 9999 10000/* ------------------------------ */ 10001 .balign 64 10002.L_OP_UNUSED_B9FF: /* 0x1b9 */ 10003/* File: armv5te/OP_UNUSED_B9FF.S */ 10004/* File: armv5te/unused.S */ 10005 bl common_abort 10006 10007 10008/* ------------------------------ */ 10009 .balign 64 10010.L_OP_UNUSED_BAFF: /* 0x1ba */ 10011/* File: armv5te/OP_UNUSED_BAFF.S */ 10012/* File: armv5te/unused.S */ 10013 bl common_abort 10014 10015 10016/* ------------------------------ */ 10017 .balign 64 10018.L_OP_UNUSED_BBFF: /* 0x1bb */ 10019/* File: armv5te/OP_UNUSED_BBFF.S */ 10020/* File: armv5te/unused.S */ 10021 bl common_abort 10022 10023 10024/* ------------------------------ */ 10025 .balign 64 10026.L_OP_UNUSED_BCFF: /* 0x1bc */ 10027/* File: armv5te/OP_UNUSED_BCFF.S */ 10028/* File: armv5te/unused.S */ 10029 bl common_abort 10030 10031 10032/* ------------------------------ */ 10033 .balign 64 10034.L_OP_UNUSED_BDFF: /* 0x1bd */ 10035/* File: armv5te/OP_UNUSED_BDFF.S */ 10036/* File: armv5te/unused.S */ 10037 bl common_abort 10038 10039 10040/* ------------------------------ */ 10041 .balign 64 10042.L_OP_UNUSED_BEFF: /* 0x1be */ 10043/* File: armv5te/OP_UNUSED_BEFF.S */ 10044/* File: armv5te/unused.S */ 10045 bl common_abort 10046 10047 10048/* ------------------------------ */ 10049 .balign 64 10050.L_OP_UNUSED_BFFF: /* 0x1bf */ 10051/* File: armv5te/OP_UNUSED_BFFF.S */ 10052/* File: armv5te/unused.S */ 10053 bl common_abort 10054 10055 10056/* ------------------------------ */ 10057 .balign 64 10058.L_OP_UNUSED_C0FF: /* 0x1c0 */ 10059/* File: armv5te/OP_UNUSED_C0FF.S */ 10060/* File: armv5te/unused.S */ 10061 bl common_abort 10062 10063 10064/* ------------------------------ */ 10065 .balign 64 10066.L_OP_UNUSED_C1FF: /* 0x1c1 */ 10067/* File: armv5te/OP_UNUSED_C1FF.S */ 10068/* File: armv5te/unused.S */ 10069 bl common_abort 10070 10071 10072/* ------------------------------ */ 10073 .balign 64 10074.L_OP_UNUSED_C2FF: /* 0x1c2 */ 10075/* File: armv5te/OP_UNUSED_C2FF.S */ 10076/* File: armv5te/unused.S */ 10077 bl common_abort 10078 10079 10080/* ------------------------------ */ 10081 .balign 64 10082.L_OP_UNUSED_C3FF: /* 0x1c3 */ 10083/* File: armv5te/OP_UNUSED_C3FF.S */ 10084/* File: armv5te/unused.S */ 10085 bl common_abort 10086 10087 10088/* ------------------------------ */ 10089 .balign 64 10090.L_OP_UNUSED_C4FF: /* 0x1c4 */ 10091/* File: armv5te/OP_UNUSED_C4FF.S */ 10092/* File: armv5te/unused.S */ 10093 bl common_abort 10094 10095 10096/* ------------------------------ */ 10097 .balign 64 10098.L_OP_UNUSED_C5FF: /* 0x1c5 */ 10099/* File: armv5te/OP_UNUSED_C5FF.S */ 10100/* File: armv5te/unused.S */ 10101 bl common_abort 10102 10103 10104/* ------------------------------ */ 10105 .balign 64 10106.L_OP_UNUSED_C6FF: /* 0x1c6 */ 10107/* File: armv5te/OP_UNUSED_C6FF.S */ 10108/* File: armv5te/unused.S */ 10109 bl common_abort 10110 10111 10112/* ------------------------------ */ 10113 .balign 64 10114.L_OP_UNUSED_C7FF: /* 0x1c7 */ 10115/* File: armv5te/OP_UNUSED_C7FF.S */ 10116/* File: armv5te/unused.S */ 10117 bl common_abort 10118 10119 10120/* ------------------------------ */ 10121 .balign 64 10122.L_OP_UNUSED_C8FF: /* 0x1c8 */ 10123/* File: armv5te/OP_UNUSED_C8FF.S */ 10124/* File: armv5te/unused.S */ 10125 bl common_abort 10126 10127 10128/* ------------------------------ */ 10129 .balign 64 10130.L_OP_UNUSED_C9FF: /* 0x1c9 */ 10131/* File: armv5te/OP_UNUSED_C9FF.S */ 10132/* File: armv5te/unused.S */ 10133 bl common_abort 10134 10135 10136/* ------------------------------ */ 10137 .balign 64 10138.L_OP_UNUSED_CAFF: /* 0x1ca */ 10139/* File: armv5te/OP_UNUSED_CAFF.S */ 10140/* File: armv5te/unused.S */ 10141 bl common_abort 10142 10143 10144/* ------------------------------ */ 10145 .balign 64 10146.L_OP_UNUSED_CBFF: /* 0x1cb */ 10147/* File: armv5te/OP_UNUSED_CBFF.S */ 10148/* File: armv5te/unused.S */ 10149 bl common_abort 10150 10151 10152/* ------------------------------ */ 10153 .balign 64 10154.L_OP_UNUSED_CCFF: /* 0x1cc */ 10155/* File: armv5te/OP_UNUSED_CCFF.S */ 10156/* File: armv5te/unused.S */ 10157 bl common_abort 10158 10159 10160/* ------------------------------ */ 10161 .balign 64 10162.L_OP_UNUSED_CDFF: /* 0x1cd */ 10163/* File: armv5te/OP_UNUSED_CDFF.S */ 10164/* File: armv5te/unused.S */ 10165 bl common_abort 10166 10167 10168/* ------------------------------ */ 10169 .balign 64 10170.L_OP_UNUSED_CEFF: /* 0x1ce */ 10171/* File: armv5te/OP_UNUSED_CEFF.S */ 10172/* File: armv5te/unused.S */ 10173 bl common_abort 10174 10175 10176/* ------------------------------ */ 10177 .balign 64 10178.L_OP_UNUSED_CFFF: /* 0x1cf */ 10179/* File: armv5te/OP_UNUSED_CFFF.S */ 10180/* File: armv5te/unused.S */ 10181 bl common_abort 10182 10183 10184/* ------------------------------ */ 10185 .balign 64 10186.L_OP_UNUSED_D0FF: /* 0x1d0 */ 10187/* File: armv5te/OP_UNUSED_D0FF.S */ 10188/* File: armv5te/unused.S */ 10189 bl common_abort 10190 10191 10192/* ------------------------------ */ 10193 .balign 64 10194.L_OP_UNUSED_D1FF: /* 0x1d1 */ 10195/* File: armv5te/OP_UNUSED_D1FF.S */ 10196/* File: armv5te/unused.S */ 10197 bl common_abort 10198 10199 10200/* ------------------------------ */ 10201 .balign 64 10202.L_OP_UNUSED_D2FF: /* 0x1d2 */ 10203/* File: armv5te/OP_UNUSED_D2FF.S */ 10204/* File: armv5te/unused.S */ 10205 bl common_abort 10206 10207 10208/* ------------------------------ */ 10209 .balign 64 10210.L_OP_UNUSED_D3FF: /* 0x1d3 */ 10211/* File: armv5te/OP_UNUSED_D3FF.S */ 10212/* File: armv5te/unused.S */ 10213 bl common_abort 10214 10215 10216/* ------------------------------ */ 10217 .balign 64 10218.L_OP_UNUSED_D4FF: /* 0x1d4 */ 10219/* File: armv5te/OP_UNUSED_D4FF.S */ 10220/* File: armv5te/unused.S */ 10221 bl common_abort 10222 10223 10224/* ------------------------------ */ 10225 .balign 64 10226.L_OP_UNUSED_D5FF: /* 0x1d5 */ 10227/* File: armv5te/OP_UNUSED_D5FF.S */ 10228/* File: armv5te/unused.S */ 10229 bl common_abort 10230 10231 10232/* ------------------------------ */ 10233 .balign 64 10234.L_OP_UNUSED_D6FF: /* 0x1d6 */ 10235/* File: armv5te/OP_UNUSED_D6FF.S */ 10236/* File: armv5te/unused.S */ 10237 bl common_abort 10238 10239 10240/* ------------------------------ */ 10241 .balign 64 10242.L_OP_UNUSED_D7FF: /* 0x1d7 */ 10243/* File: armv5te/OP_UNUSED_D7FF.S */ 10244/* File: armv5te/unused.S */ 10245 bl common_abort 10246 10247 10248/* ------------------------------ */ 10249 .balign 64 10250.L_OP_UNUSED_D8FF: /* 0x1d8 */ 10251/* File: armv5te/OP_UNUSED_D8FF.S */ 10252/* File: armv5te/unused.S */ 10253 bl common_abort 10254 10255 10256/* ------------------------------ */ 10257 .balign 64 10258.L_OP_UNUSED_D9FF: /* 0x1d9 */ 10259/* File: armv5te/OP_UNUSED_D9FF.S */ 10260/* File: armv5te/unused.S */ 10261 bl common_abort 10262 10263 10264/* ------------------------------ */ 10265 .balign 64 10266.L_OP_UNUSED_DAFF: /* 0x1da */ 10267/* File: armv5te/OP_UNUSED_DAFF.S */ 10268/* File: armv5te/unused.S */ 10269 bl common_abort 10270 10271 10272/* ------------------------------ */ 10273 .balign 64 10274.L_OP_UNUSED_DBFF: /* 0x1db */ 10275/* File: armv5te/OP_UNUSED_DBFF.S */ 10276/* File: armv5te/unused.S */ 10277 bl common_abort 10278 10279 10280/* ------------------------------ */ 10281 .balign 64 10282.L_OP_UNUSED_DCFF: /* 0x1dc */ 10283/* File: armv5te/OP_UNUSED_DCFF.S */ 10284/* File: armv5te/unused.S */ 10285 bl common_abort 10286 10287 10288/* ------------------------------ */ 10289 .balign 64 10290.L_OP_UNUSED_DDFF: /* 0x1dd */ 10291/* File: armv5te/OP_UNUSED_DDFF.S */ 10292/* File: armv5te/unused.S */ 10293 bl common_abort 10294 10295 10296/* ------------------------------ */ 10297 .balign 64 10298.L_OP_UNUSED_DEFF: /* 0x1de */ 10299/* File: armv5te/OP_UNUSED_DEFF.S */ 10300/* File: armv5te/unused.S */ 10301 bl common_abort 10302 10303 10304/* ------------------------------ */ 10305 .balign 64 10306.L_OP_UNUSED_DFFF: /* 0x1df */ 10307/* File: armv5te/OP_UNUSED_DFFF.S */ 10308/* File: armv5te/unused.S */ 10309 bl common_abort 10310 10311 10312/* ------------------------------ */ 10313 .balign 64 10314.L_OP_UNUSED_E0FF: /* 0x1e0 */ 10315/* File: armv5te/OP_UNUSED_E0FF.S */ 10316/* File: armv5te/unused.S */ 10317 bl common_abort 10318 10319 10320/* ------------------------------ */ 10321 .balign 64 10322.L_OP_UNUSED_E1FF: /* 0x1e1 */ 10323/* File: armv5te/OP_UNUSED_E1FF.S */ 10324/* File: armv5te/unused.S */ 10325 bl common_abort 10326 10327 10328/* ------------------------------ */ 10329 .balign 64 10330.L_OP_UNUSED_E2FF: /* 0x1e2 */ 10331/* File: armv5te/OP_UNUSED_E2FF.S */ 10332/* File: armv5te/unused.S */ 10333 bl common_abort 10334 10335 10336/* ------------------------------ */ 10337 .balign 64 10338.L_OP_UNUSED_E3FF: /* 0x1e3 */ 10339/* File: armv5te/OP_UNUSED_E3FF.S */ 10340/* File: armv5te/unused.S */ 10341 bl common_abort 10342 10343 10344/* ------------------------------ */ 10345 .balign 64 10346.L_OP_UNUSED_E4FF: /* 0x1e4 */ 10347/* File: armv5te/OP_UNUSED_E4FF.S */ 10348/* File: armv5te/unused.S */ 10349 bl common_abort 10350 10351 10352/* ------------------------------ */ 10353 .balign 64 10354.L_OP_UNUSED_E5FF: /* 0x1e5 */ 10355/* File: armv5te/OP_UNUSED_E5FF.S */ 10356/* File: armv5te/unused.S */ 10357 bl common_abort 10358 10359 10360/* ------------------------------ */ 10361 .balign 64 10362.L_OP_UNUSED_E6FF: /* 0x1e6 */ 10363/* File: armv5te/OP_UNUSED_E6FF.S */ 10364/* File: armv5te/unused.S */ 10365 bl common_abort 10366 10367 10368/* ------------------------------ */ 10369 .balign 64 10370.L_OP_UNUSED_E7FF: /* 0x1e7 */ 10371/* File: armv5te/OP_UNUSED_E7FF.S */ 10372/* File: armv5te/unused.S */ 10373 bl common_abort 10374 10375 10376/* ------------------------------ */ 10377 .balign 64 10378.L_OP_UNUSED_E8FF: /* 0x1e8 */ 10379/* File: armv5te/OP_UNUSED_E8FF.S */ 10380/* File: armv5te/unused.S */ 10381 bl common_abort 10382 10383 10384/* ------------------------------ */ 10385 .balign 64 10386.L_OP_UNUSED_E9FF: /* 0x1e9 */ 10387/* File: armv5te/OP_UNUSED_E9FF.S */ 10388/* File: armv5te/unused.S */ 10389 bl common_abort 10390 10391 10392/* ------------------------------ */ 10393 .balign 64 10394.L_OP_UNUSED_EAFF: /* 0x1ea */ 10395/* File: armv5te/OP_UNUSED_EAFF.S */ 10396/* File: armv5te/unused.S */ 10397 bl common_abort 10398 10399 10400/* ------------------------------ */ 10401 .balign 64 10402.L_OP_UNUSED_EBFF: /* 0x1eb */ 10403/* File: armv5te/OP_UNUSED_EBFF.S */ 10404/* File: armv5te/unused.S */ 10405 bl common_abort 10406 10407 10408/* ------------------------------ */ 10409 .balign 64 10410.L_OP_UNUSED_ECFF: /* 0x1ec */ 10411/* File: armv5te/OP_UNUSED_ECFF.S */ 10412/* File: armv5te/unused.S */ 10413 bl common_abort 10414 10415 10416/* ------------------------------ */ 10417 .balign 64 10418.L_OP_UNUSED_EDFF: /* 0x1ed */ 10419/* File: armv5te/OP_UNUSED_EDFF.S */ 10420/* File: armv5te/unused.S */ 10421 bl common_abort 10422 10423 10424/* ------------------------------ */ 10425 .balign 64 10426.L_OP_UNUSED_EEFF: /* 0x1ee */ 10427/* File: armv5te/OP_UNUSED_EEFF.S */ 10428/* File: armv5te/unused.S */ 10429 bl common_abort 10430 10431 10432/* ------------------------------ */ 10433 .balign 64 10434.L_OP_UNUSED_EFFF: /* 0x1ef */ 10435/* File: armv5te/OP_UNUSED_EFFF.S */ 10436/* File: armv5te/unused.S */ 10437 bl common_abort 10438 10439 10440/* ------------------------------ */ 10441 .balign 64 10442.L_OP_UNUSED_F0FF: /* 0x1f0 */ 10443/* File: armv5te/OP_UNUSED_F0FF.S */ 10444/* File: armv5te/unused.S */ 10445 bl common_abort 10446 10447 10448/* ------------------------------ */ 10449 .balign 64 10450.L_OP_UNUSED_F1FF: /* 0x1f1 */ 10451/* File: armv5te/OP_UNUSED_F1FF.S */ 10452/* File: armv5te/unused.S */ 10453 bl common_abort 10454 10455 10456/* ------------------------------ */ 10457 .balign 64 10458.L_OP_UNUSED_F2FF: /* 0x1f2 */ 10459/* File: armv5te/OP_UNUSED_F2FF.S */ 10460/* File: armv5te/unused.S */ 10461 bl common_abort 10462 10463 10464/* ------------------------------ */ 10465 .balign 64 10466.L_OP_UNUSED_F3FF: /* 0x1f3 */ 10467/* File: armv5te/OP_UNUSED_F3FF.S */ 10468/* File: armv5te/unused.S */ 10469 bl common_abort 10470 10471 10472/* ------------------------------ */ 10473 .balign 64 10474.L_OP_UNUSED_F4FF: /* 0x1f4 */ 10475/* File: armv5te/OP_UNUSED_F4FF.S */ 10476/* File: armv5te/unused.S */ 10477 bl common_abort 10478 10479 10480/* ------------------------------ */ 10481 .balign 64 10482.L_OP_UNUSED_F5FF: /* 0x1f5 */ 10483/* File: armv5te/OP_UNUSED_F5FF.S */ 10484/* File: armv5te/unused.S */ 10485 bl common_abort 10486 10487 10488/* ------------------------------ */ 10489 .balign 64 10490.L_OP_UNUSED_F6FF: /* 0x1f6 */ 10491/* File: armv5te/OP_UNUSED_F6FF.S */ 10492/* File: armv5te/unused.S */ 10493 bl common_abort 10494 10495 10496/* ------------------------------ */ 10497 .balign 64 10498.L_OP_UNUSED_F7FF: /* 0x1f7 */ 10499/* File: armv5te/OP_UNUSED_F7FF.S */ 10500/* File: armv5te/unused.S */ 10501 bl common_abort 10502 10503 10504/* ------------------------------ */ 10505 .balign 64 10506.L_OP_UNUSED_F8FF: /* 0x1f8 */ 10507/* File: armv5te/OP_UNUSED_F8FF.S */ 10508/* File: armv5te/unused.S */ 10509 bl common_abort 10510 10511 10512/* ------------------------------ */ 10513 .balign 64 10514.L_OP_UNUSED_F9FF: /* 0x1f9 */ 10515/* File: armv5te/OP_UNUSED_F9FF.S */ 10516/* File: armv5te/unused.S */ 10517 bl common_abort 10518 10519 10520/* ------------------------------ */ 10521 .balign 64 10522.L_OP_UNUSED_FAFF: /* 0x1fa */ 10523/* File: armv5te/OP_UNUSED_FAFF.S */ 10524/* File: armv5te/unused.S */ 10525 bl common_abort 10526 10527 10528/* ------------------------------ */ 10529 .balign 64 10530.L_OP_UNUSED_FBFF: /* 0x1fb */ 10531/* File: armv5te/OP_UNUSED_FBFF.S */ 10532/* File: armv5te/unused.S */ 10533 bl common_abort 10534 10535 10536/* ------------------------------ */ 10537 .balign 64 10538.L_OP_UNUSED_FCFF: /* 0x1fc */ 10539/* File: armv5te/OP_UNUSED_FCFF.S */ 10540/* File: armv5te/unused.S */ 10541 bl common_abort 10542 10543 10544/* ------------------------------ */ 10545 .balign 64 10546.L_OP_UNUSED_FDFF: /* 0x1fd */ 10547/* File: armv5te/OP_UNUSED_FDFF.S */ 10548/* File: armv5te/unused.S */ 10549 bl common_abort 10550 10551 10552/* ------------------------------ */ 10553 .balign 64 10554.L_OP_UNUSED_FEFF: /* 0x1fe */ 10555/* File: armv5te/OP_UNUSED_FEFF.S */ 10556/* File: armv5te/unused.S */ 10557 bl common_abort 10558 10559 10560/* ------------------------------ */ 10561 .balign 64 10562.L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 10563/* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */ 10564 /* 10565 * Handle a jumbo throw-verification-error instruction. This throws an 10566 * exception for an error discovered during verification. The 10567 * exception is indicated by BBBB, with some detail provided by AAAAAAAA. 10568 */ 10569 /* exop BBBB, Class@AAAAAAAA */ 10570 FETCH(r1, 1) @ r1<- aaaa (lo) 10571 FETCH(r2, 2) @ r2<- AAAA (hi) 10572 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10573 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa 10574 EXPORT_PC() @ export the PC 10575 FETCH(r1, 3) @ r1<- BBBB 10576 bl dvmThrowVerificationError @ always throws 10577 b common_exceptionThrown @ handle exception 10578 10579 .balign 64 10580 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 10581 .global dvmAsmInstructionEnd 10582dvmAsmInstructionEnd: 10583 10584/* 10585 * =========================================================================== 10586 * Sister implementations 10587 * =========================================================================== 10588 */ 10589 .global dvmAsmSisterStart 10590 .type dvmAsmSisterStart, %function 10591 .text 10592 .balign 4 10593dvmAsmSisterStart: 10594 10595/* continuation for OP_CONST_STRING */ 10596 10597 /* 10598 * Continuation if the String has not yet been resolved. 10599 * r1: BBBB (String ref) 10600 * r9: target register 10601 */ 10602.LOP_CONST_STRING_resolve: 10603 EXPORT_PC() 10604 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10605 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10606 bl dvmResolveString @ r0<- String reference 10607 cmp r0, #0 @ failed? 10608 beq common_exceptionThrown @ yup, handle the exception 10609 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10610 GET_INST_OPCODE(ip) @ extract opcode from rINST 10611 SET_VREG(r0, r9) @ vAA<- r0 10612 GOTO_OPCODE(ip) @ jump to next instruction 10613 10614/* continuation for OP_CONST_STRING_JUMBO */ 10615 10616 /* 10617 * Continuation if the String has not yet been resolved. 10618 * r1: BBBBBBBB (String ref) 10619 * r9: target register 10620 */ 10621.LOP_CONST_STRING_JUMBO_resolve: 10622 EXPORT_PC() 10623 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10624 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10625 bl dvmResolveString @ r0<- String reference 10626 cmp r0, #0 @ failed? 10627 beq common_exceptionThrown @ yup, handle the exception 10628 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10629 GET_INST_OPCODE(ip) @ extract opcode from rINST 10630 SET_VREG(r0, r9) @ vAA<- r0 10631 GOTO_OPCODE(ip) @ jump to next instruction 10632 10633/* continuation for OP_CONST_CLASS */ 10634 10635 /* 10636 * Continuation if the Class has not yet been resolved. 10637 * r1: BBBB (Class ref) 10638 * r9: target register 10639 */ 10640.LOP_CONST_CLASS_resolve: 10641 EXPORT_PC() 10642 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10643 mov r2, #1 @ r2<- true 10644 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10645 bl dvmResolveClass @ r0<- Class reference 10646 cmp r0, #0 @ failed? 10647 beq common_exceptionThrown @ yup, handle the exception 10648 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10649 GET_INST_OPCODE(ip) @ extract opcode from rINST 10650 SET_VREG(r0, r9) @ vAA<- r0 10651 GOTO_OPCODE(ip) @ jump to next instruction 10652 10653/* continuation for OP_CHECK_CAST */ 10654 10655 /* 10656 * Trivial test failed, need to perform full check. This is common. 10657 * r0 holds obj->clazz 10658 * r1 holds desired class resolved from BBBB 10659 * r9 holds object 10660 */ 10661.LOP_CHECK_CAST_fullcheck: 10662 mov r10, r1 @ avoid ClassObject getting clobbered 10663 bl dvmInstanceofNonTrivial @ r0<- boolean result 10664 cmp r0, #0 @ failed? 10665 bne .LOP_CHECK_CAST_okay @ no, success 10666 10667 @ A cast has failed. We need to throw a ClassCastException. 10668 EXPORT_PC() @ about to throw 10669 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 10670 mov r1, r10 @ r1<- desired class 10671 bl dvmThrowClassCastException 10672 b common_exceptionThrown 10673 10674 /* 10675 * Resolution required. This is the least-likely path. 10676 * 10677 * r2 holds BBBB 10678 * r9 holds object 10679 */ 10680.LOP_CHECK_CAST_resolve: 10681 EXPORT_PC() @ resolve() could throw 10682 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10683 mov r1, r2 @ r1<- BBBB 10684 mov r2, #0 @ r2<- false 10685 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10686 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10687 cmp r0, #0 @ got null? 10688 beq common_exceptionThrown @ yes, handle exception 10689 mov r1, r0 @ r1<- class resolved from BBB 10690 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 10691 b .LOP_CHECK_CAST_resolved @ pick up where we left off 10692 10693/* continuation for OP_INSTANCE_OF */ 10694 10695 /* 10696 * Trivial test failed, need to perform full check. This is common. 10697 * r0 holds obj->clazz 10698 * r1 holds class resolved from BBBB 10699 * r9 holds A 10700 */ 10701.LOP_INSTANCE_OF_fullcheck: 10702 bl dvmInstanceofNonTrivial @ r0<- boolean result 10703 @ fall through to OP_INSTANCE_OF_store 10704 10705 /* 10706 * r0 holds boolean result 10707 * r9 holds A 10708 */ 10709.LOP_INSTANCE_OF_store: 10710 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10711 SET_VREG(r0, r9) @ vA<- r0 10712 GET_INST_OPCODE(ip) @ extract opcode from rINST 10713 GOTO_OPCODE(ip) @ jump to next instruction 10714 10715 /* 10716 * Trivial test succeeded, save and bail. 10717 * r9 holds A 10718 */ 10719.LOP_INSTANCE_OF_trivial: 10720 mov r0, #1 @ indicate success 10721 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 10722 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10723 SET_VREG(r0, r9) @ vA<- r0 10724 GET_INST_OPCODE(ip) @ extract opcode from rINST 10725 GOTO_OPCODE(ip) @ jump to next instruction 10726 10727 /* 10728 * Resolution required. This is the least-likely path. 10729 * 10730 * r3 holds BBBB 10731 * r9 holds A 10732 */ 10733.LOP_INSTANCE_OF_resolve: 10734 EXPORT_PC() @ resolve() could throw 10735 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10736 mov r1, r3 @ r1<- BBBB 10737 mov r2, #1 @ r2<- true 10738 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10739 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10740 cmp r0, #0 @ got null? 10741 beq common_exceptionThrown @ yes, handle exception 10742 mov r1, r0 @ r1<- class resolved from BBB 10743 mov r3, rINST, lsr #12 @ r3<- B 10744 GET_VREG(r0, r3) @ r0<- vB (object) 10745 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 10746 b .LOP_INSTANCE_OF_resolved @ pick up where we left off 10747 10748/* continuation for OP_NEW_INSTANCE */ 10749 10750 .balign 32 @ minimize cache lines 10751.LOP_NEW_INSTANCE_finish: @ r0=new object 10752 mov r3, rINST, lsr #8 @ r3<- AA 10753 cmp r0, #0 @ failed? 10754 beq common_exceptionThrown @ yes, handle the exception 10755 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10756 GET_INST_OPCODE(ip) @ extract opcode from rINST 10757 SET_VREG(r0, r3) @ vAA<- r0 10758 GOTO_OPCODE(ip) @ jump to next instruction 10759 10760 /* 10761 * Class initialization required. 10762 * 10763 * r0 holds class object 10764 */ 10765.LOP_NEW_INSTANCE_needinit: 10766 mov r9, r0 @ save r0 10767 bl dvmInitClass @ initialize class 10768 cmp r0, #0 @ check boolean result 10769 mov r0, r9 @ restore r0 10770 bne .LOP_NEW_INSTANCE_initialized @ success, continue 10771 b common_exceptionThrown @ failed, deal with init exception 10772 10773 /* 10774 * Resolution required. This is the least-likely path. 10775 * 10776 * r1 holds BBBB 10777 */ 10778.LOP_NEW_INSTANCE_resolve: 10779 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10780 mov r2, #0 @ r2<- false 10781 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10782 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10783 cmp r0, #0 @ got null? 10784 bne .LOP_NEW_INSTANCE_resolved @ no, continue 10785 b common_exceptionThrown @ yes, handle exception 10786 10787/* continuation for OP_NEW_ARRAY */ 10788 10789 10790 /* 10791 * Resolve class. (This is an uncommon case.) 10792 * 10793 * r1 holds array length 10794 * r2 holds class ref CCCC 10795 */ 10796.LOP_NEW_ARRAY_resolve: 10797 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10798 mov r9, r1 @ r9<- length (save) 10799 mov r1, r2 @ r1<- CCCC 10800 mov r2, #0 @ r2<- false 10801 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10802 bl dvmResolveClass @ r0<- call(clazz, ref) 10803 cmp r0, #0 @ got null? 10804 mov r1, r9 @ r1<- length (restore) 10805 beq common_exceptionThrown @ yes, handle exception 10806 @ fall through to OP_NEW_ARRAY_finish 10807 10808 /* 10809 * Finish allocation. 10810 * 10811 * r0 holds class 10812 * r1 holds array length 10813 */ 10814.LOP_NEW_ARRAY_finish: 10815 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 10816 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 10817 cmp r0, #0 @ failed? 10818 mov r2, rINST, lsr #8 @ r2<- A+ 10819 beq common_exceptionThrown @ yes, handle the exception 10820 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10821 and r2, r2, #15 @ r2<- A 10822 GET_INST_OPCODE(ip) @ extract opcode from rINST 10823 SET_VREG(r0, r2) @ vA<- r0 10824 GOTO_OPCODE(ip) @ jump to next instruction 10825 10826/* continuation for OP_FILLED_NEW_ARRAY */ 10827 10828 /* 10829 * On entry: 10830 * r0 holds array class 10831 * r10 holds AA or BA 10832 */ 10833.LOP_FILLED_NEW_ARRAY_continue: 10834 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 10835 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 10836 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 10837 .if 0 10838 mov r1, r10 @ r1<- AA (length) 10839 .else 10840 mov r1, r10, lsr #4 @ r1<- B (length) 10841 .endif 10842 cmp rINST, #'I' @ array of ints? 10843 cmpne rINST, #'L' @ array of objects? 10844 cmpne rINST, #'[' @ array of arrays? 10845 mov r9, r1 @ save length in r9 10846 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 10847 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 10848 cmp r0, #0 @ null return? 10849 beq common_exceptionThrown @ alloc failed, handle exception 10850 10851 FETCH(r1, 2) @ r1<- FEDC or CCCC 10852 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 10853 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 10854 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 10855 subs r9, r9, #1 @ length--, check for neg 10856 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 10857 bmi 2f @ was zero, bail 10858 10859 @ copy values from registers into the array 10860 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 10861 .if 0 10862 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 108631: ldr r3, [r2], #4 @ r3<- *r2++ 10864 subs r9, r9, #1 @ count-- 10865 str r3, [r0], #4 @ *contents++ = vX 10866 bpl 1b 10867 @ continue at 2 10868 .else 10869 cmp r9, #4 @ length was initially 5? 10870 and r2, r10, #15 @ r2<- A 10871 bne 1f @ <= 4 args, branch 10872 GET_VREG(r3, r2) @ r3<- vA 10873 sub r9, r9, #1 @ count-- 10874 str r3, [r0, #16] @ contents[4] = vA 108751: and r2, r1, #15 @ r2<- F/E/D/C 10876 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 10877 mov r1, r1, lsr #4 @ r1<- next reg in low 4 10878 subs r9, r9, #1 @ count-- 10879 str r3, [r0], #4 @ *contents++ = vX 10880 bpl 1b 10881 @ continue at 2 10882 .endif 10883 108842: 10885 ldr r0, [rSELF, #offThread_retval] @ r0<- object 10886 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 10887 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 10888 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 10889 cmp r1, #'I' @ Is int array? 10890 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 10891 GOTO_OPCODE(ip) @ execute it 10892 10893 /* 10894 * Throw an exception indicating that we have not implemented this 10895 * mode of filled-new-array. 10896 */ 10897.LOP_FILLED_NEW_ARRAY_notimpl: 10898 ldr r0, .L_strFilledNewArrayNotImpl 10899 bl dvmThrowInternalError 10900 b common_exceptionThrown 10901 10902 .if (!0) @ define in one or the other, not both 10903.L_strFilledNewArrayNotImpl: 10904 .word .LstrFilledNewArrayNotImpl 10905 .endif 10906 10907/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 10908 10909 /* 10910 * On entry: 10911 * r0 holds array class 10912 * r10 holds AA or BA 10913 */ 10914.LOP_FILLED_NEW_ARRAY_RANGE_continue: 10915 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 10916 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 10917 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 10918 .if 1 10919 mov r1, r10 @ r1<- AA (length) 10920 .else 10921 mov r1, r10, lsr #4 @ r1<- B (length) 10922 .endif 10923 cmp rINST, #'I' @ array of ints? 10924 cmpne rINST, #'L' @ array of objects? 10925 cmpne rINST, #'[' @ array of arrays? 10926 mov r9, r1 @ save length in r9 10927 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 10928 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 10929 cmp r0, #0 @ null return? 10930 beq common_exceptionThrown @ alloc failed, handle exception 10931 10932 FETCH(r1, 2) @ r1<- FEDC or CCCC 10933 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 10934 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 10935 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 10936 subs r9, r9, #1 @ length--, check for neg 10937 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 10938 bmi 2f @ was zero, bail 10939 10940 @ copy values from registers into the array 10941 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 10942 .if 1 10943 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 109441: ldr r3, [r2], #4 @ r3<- *r2++ 10945 subs r9, r9, #1 @ count-- 10946 str r3, [r0], #4 @ *contents++ = vX 10947 bpl 1b 10948 @ continue at 2 10949 .else 10950 cmp r9, #4 @ length was initially 5? 10951 and r2, r10, #15 @ r2<- A 10952 bne 1f @ <= 4 args, branch 10953 GET_VREG(r3, r2) @ r3<- vA 10954 sub r9, r9, #1 @ count-- 10955 str r3, [r0, #16] @ contents[4] = vA 109561: and r2, r1, #15 @ r2<- F/E/D/C 10957 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 10958 mov r1, r1, lsr #4 @ r1<- next reg in low 4 10959 subs r9, r9, #1 @ count-- 10960 str r3, [r0], #4 @ *contents++ = vX 10961 bpl 1b 10962 @ continue at 2 10963 .endif 10964 109652: 10966 ldr r0, [rSELF, #offThread_retval] @ r0<- object 10967 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 10968 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 10969 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 10970 cmp r1, #'I' @ Is int array? 10971 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 10972 GOTO_OPCODE(ip) @ execute it 10973 10974 /* 10975 * Throw an exception indicating that we have not implemented this 10976 * mode of filled-new-array. 10977 */ 10978.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 10979 ldr r0, .L_strFilledNewArrayNotImpl 10980 bl dvmThrowInternalError 10981 b common_exceptionThrown 10982 10983 .if (!1) @ define in one or the other, not both 10984.L_strFilledNewArrayNotImpl: 10985 .word .LstrFilledNewArrayNotImpl 10986 .endif 10987 10988/* continuation for OP_CMPL_FLOAT */ 10989.LOP_CMPL_FLOAT_finish: 10990 SET_VREG(r0, r9) @ vAA<- r0 10991 GOTO_OPCODE(ip) @ jump to next instruction 10992 10993/* continuation for OP_CMPG_FLOAT */ 10994.LOP_CMPG_FLOAT_finish: 10995 SET_VREG(r0, r9) @ vAA<- r0 10996 GOTO_OPCODE(ip) @ jump to next instruction 10997 10998/* continuation for OP_CMPL_DOUBLE */ 10999.LOP_CMPL_DOUBLE_finish: 11000 SET_VREG(r0, r9) @ vAA<- r0 11001 GOTO_OPCODE(ip) @ jump to next instruction 11002 11003/* continuation for OP_CMPG_DOUBLE */ 11004.LOP_CMPG_DOUBLE_finish: 11005 SET_VREG(r0, r9) @ vAA<- r0 11006 GOTO_OPCODE(ip) @ jump to next instruction 11007 11008/* continuation for OP_CMP_LONG */ 11009 11010.LOP_CMP_LONG_less: 11011 mvn r1, #0 @ r1<- -1 11012 @ Want to cond code the next mov so we can avoid branch, but don't see it; 11013 @ instead, we just replicate the tail end. 11014 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11015 SET_VREG(r1, r9) @ vAA<- r1 11016 GET_INST_OPCODE(ip) @ extract opcode from rINST 11017 GOTO_OPCODE(ip) @ jump to next instruction 11018 11019.LOP_CMP_LONG_greater: 11020 mov r1, #1 @ r1<- 1 11021 @ fall through to _finish 11022 11023.LOP_CMP_LONG_finish: 11024 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11025 SET_VREG(r1, r9) @ vAA<- r1 11026 GET_INST_OPCODE(ip) @ extract opcode from rINST 11027 GOTO_OPCODE(ip) @ jump to next instruction 11028 11029/* continuation for OP_AGET_WIDE */ 11030 11031.LOP_AGET_WIDE_finish: 11032 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11033 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11034 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 11035 GET_INST_OPCODE(ip) @ extract opcode from rINST 11036 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 11037 GOTO_OPCODE(ip) @ jump to next instruction 11038 11039/* continuation for OP_APUT_WIDE */ 11040 11041.LOP_APUT_WIDE_finish: 11042 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11043 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 11044 GET_INST_OPCODE(ip) @ extract opcode from rINST 11045 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11046 GOTO_OPCODE(ip) @ jump to next instruction 11047 11048/* continuation for OP_APUT_OBJECT */ 11049 /* 11050 * On entry: 11051 * rINST = vBB (arrayObj) 11052 * r9 = vAA (obj) 11053 * r10 = offset into array (vBB + vCC * width) 11054 */ 11055.LOP_APUT_OBJECT_finish: 11056 cmp r9, #0 @ storing null reference? 11057 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 11058 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 11059 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz 11060 bl dvmCanPutArrayElement @ test object type vs. array type 11061 cmp r0, #0 @ okay? 11062 beq .LOP_APUT_OBJECT_throw @ no 11063 mov r1, rINST @ r1<- arrayObj 11064 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11065 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base 11066 add r10, #offArrayObject_contents @ r0<- pointer to slot 11067 GET_INST_OPCODE(ip) @ extract opcode from rINST 11068 str r9, [r10] @ vBB[vCC]<- vAA 11069 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head 11070 GOTO_OPCODE(ip) @ jump to next instruction 11071.LOP_APUT_OBJECT_skip_check: 11072 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11073 GET_INST_OPCODE(ip) @ extract opcode from rINST 11074 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 11075 GOTO_OPCODE(ip) @ jump to next instruction 11076.LOP_APUT_OBJECT_throw: 11077 @ The types don't match. We need to throw an ArrayStoreException. 11078 ldr r0, [r9, #offObject_clazz] 11079 ldr r1, [rINST, #offObject_clazz] 11080 EXPORT_PC() 11081 bl dvmThrowArrayStoreException 11082 b common_exceptionThrown 11083 11084/* continuation for OP_IGET */ 11085 11086 /* 11087 * Currently: 11088 * r0 holds resolved field 11089 * r9 holds object 11090 */ 11091.LOP_IGET_finish: 11092 @bl common_squeak0 11093 cmp r9, #0 @ check object for null 11094 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11095 beq common_errNullObject @ object was null 11096 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11097 @ no-op @ acquiring load 11098 mov r2, rINST, lsr #8 @ r2<- A+ 11099 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11100 and r2, r2, #15 @ r2<- A 11101 GET_INST_OPCODE(ip) @ extract opcode from rINST 11102 SET_VREG(r0, r2) @ fp[A]<- r0 11103 GOTO_OPCODE(ip) @ jump to next instruction 11104 11105/* continuation for OP_IGET_WIDE */ 11106 11107 /* 11108 * Currently: 11109 * r0 holds resolved field 11110 * r9 holds object 11111 */ 11112.LOP_IGET_WIDE_finish: 11113 cmp r9, #0 @ check object for null 11114 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11115 beq common_errNullObject @ object was null 11116 .if 0 11117 add r0, r9, r3 @ r0<- address of field 11118 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 11119 .else 11120 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11121 .endif 11122 mov r2, rINST, lsr #8 @ r2<- A+ 11123 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11124 and r2, r2, #15 @ r2<- A 11125 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11126 GET_INST_OPCODE(ip) @ extract opcode from rINST 11127 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11128 GOTO_OPCODE(ip) @ jump to next instruction 11129 11130/* continuation for OP_IGET_OBJECT */ 11131 11132 /* 11133 * Currently: 11134 * r0 holds resolved field 11135 * r9 holds object 11136 */ 11137.LOP_IGET_OBJECT_finish: 11138 @bl common_squeak0 11139 cmp r9, #0 @ check object for null 11140 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11141 beq common_errNullObject @ object was null 11142 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11143 @ no-op @ acquiring load 11144 mov r2, rINST, lsr #8 @ r2<- A+ 11145 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11146 and r2, r2, #15 @ r2<- A 11147 GET_INST_OPCODE(ip) @ extract opcode from rINST 11148 SET_VREG(r0, r2) @ fp[A]<- r0 11149 GOTO_OPCODE(ip) @ jump to next instruction 11150 11151/* continuation for OP_IGET_BOOLEAN */ 11152 11153 /* 11154 * Currently: 11155 * r0 holds resolved field 11156 * r9 holds object 11157 */ 11158.LOP_IGET_BOOLEAN_finish: 11159 @bl common_squeak1 11160 cmp r9, #0 @ check object for null 11161 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11162 beq common_errNullObject @ object was null 11163 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11164 @ no-op @ acquiring load 11165 mov r2, rINST, lsr #8 @ r2<- A+ 11166 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11167 and r2, r2, #15 @ r2<- A 11168 GET_INST_OPCODE(ip) @ extract opcode from rINST 11169 SET_VREG(r0, r2) @ fp[A]<- r0 11170 GOTO_OPCODE(ip) @ jump to next instruction 11171 11172/* continuation for OP_IGET_BYTE */ 11173 11174 /* 11175 * Currently: 11176 * r0 holds resolved field 11177 * r9 holds object 11178 */ 11179.LOP_IGET_BYTE_finish: 11180 @bl common_squeak2 11181 cmp r9, #0 @ check object for null 11182 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11183 beq common_errNullObject @ object was null 11184 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11185 @ no-op @ acquiring load 11186 mov r2, rINST, lsr #8 @ r2<- A+ 11187 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11188 and r2, r2, #15 @ r2<- A 11189 GET_INST_OPCODE(ip) @ extract opcode from rINST 11190 SET_VREG(r0, r2) @ fp[A]<- r0 11191 GOTO_OPCODE(ip) @ jump to next instruction 11192 11193/* continuation for OP_IGET_CHAR */ 11194 11195 /* 11196 * Currently: 11197 * r0 holds resolved field 11198 * r9 holds object 11199 */ 11200.LOP_IGET_CHAR_finish: 11201 @bl common_squeak3 11202 cmp r9, #0 @ check object for null 11203 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11204 beq common_errNullObject @ object was null 11205 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11206 @ no-op @ acquiring load 11207 mov r2, rINST, lsr #8 @ r2<- A+ 11208 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11209 and r2, r2, #15 @ r2<- A 11210 GET_INST_OPCODE(ip) @ extract opcode from rINST 11211 SET_VREG(r0, r2) @ fp[A]<- r0 11212 GOTO_OPCODE(ip) @ jump to next instruction 11213 11214/* continuation for OP_IGET_SHORT */ 11215 11216 /* 11217 * Currently: 11218 * r0 holds resolved field 11219 * r9 holds object 11220 */ 11221.LOP_IGET_SHORT_finish: 11222 @bl common_squeak4 11223 cmp r9, #0 @ check object for null 11224 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11225 beq common_errNullObject @ object was null 11226 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11227 @ no-op @ acquiring load 11228 mov r2, rINST, lsr #8 @ r2<- A+ 11229 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11230 and r2, r2, #15 @ r2<- A 11231 GET_INST_OPCODE(ip) @ extract opcode from rINST 11232 SET_VREG(r0, r2) @ fp[A]<- r0 11233 GOTO_OPCODE(ip) @ jump to next instruction 11234 11235/* continuation for OP_IPUT */ 11236 11237 /* 11238 * Currently: 11239 * r0 holds resolved field 11240 * r9 holds object 11241 */ 11242.LOP_IPUT_finish: 11243 @bl common_squeak0 11244 mov r1, rINST, lsr #8 @ r1<- A+ 11245 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11246 and r1, r1, #15 @ r1<- A 11247 cmp r9, #0 @ check object for null 11248 GET_VREG(r0, r1) @ r0<- fp[A] 11249 beq common_errNullObject @ object was null 11250 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11251 GET_INST_OPCODE(ip) @ extract opcode from rINST 11252 @ no-op @ releasing store 11253 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11254 GOTO_OPCODE(ip) @ jump to next instruction 11255 11256/* continuation for OP_IPUT_WIDE */ 11257 11258 /* 11259 * Currently: 11260 * r0 holds resolved field 11261 * r9 holds object 11262 */ 11263.LOP_IPUT_WIDE_finish: 11264 mov r2, rINST, lsr #8 @ r2<- A+ 11265 cmp r9, #0 @ check object for null 11266 and r2, r2, #15 @ r2<- A 11267 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11268 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 11269 beq common_errNullObject @ object was null 11270 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11271 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 11272 GET_INST_OPCODE(r10) @ extract opcode from rINST 11273 .if 0 11274 add r2, r9, r3 @ r2<- target address 11275 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 11276 .else 11277 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 11278 .endif 11279 GOTO_OPCODE(r10) @ jump to next instruction 11280 11281/* continuation for OP_IPUT_OBJECT */ 11282 11283 /* 11284 * Currently: 11285 * r0 holds resolved field 11286 * r9 holds object 11287 */ 11288.LOP_IPUT_OBJECT_finish: 11289 @bl common_squeak0 11290 mov r1, rINST, lsr #8 @ r1<- A+ 11291 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11292 and r1, r1, #15 @ r1<- A 11293 cmp r9, #0 @ check object for null 11294 GET_VREG(r0, r1) @ r0<- fp[A] 11295 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11296 beq common_errNullObject @ object was null 11297 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11298 GET_INST_OPCODE(ip) @ extract opcode from rINST 11299 @ no-op @ releasing store 11300 str r0, [r9, r3] @ obj.field (32 bits)<- r0 11301 cmp r0, #0 @ stored a null reference? 11302 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 11303 GOTO_OPCODE(ip) @ jump to next instruction 11304 11305/* continuation for OP_IPUT_BOOLEAN */ 11306 11307 /* 11308 * Currently: 11309 * r0 holds resolved field 11310 * r9 holds object 11311 */ 11312.LOP_IPUT_BOOLEAN_finish: 11313 @bl common_squeak1 11314 mov r1, rINST, lsr #8 @ r1<- A+ 11315 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11316 and r1, r1, #15 @ r1<- A 11317 cmp r9, #0 @ check object for null 11318 GET_VREG(r0, r1) @ r0<- fp[A] 11319 beq common_errNullObject @ object was null 11320 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11321 GET_INST_OPCODE(ip) @ extract opcode from rINST 11322 @ no-op @ releasing store 11323 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11324 GOTO_OPCODE(ip) @ jump to next instruction 11325 11326/* continuation for OP_IPUT_BYTE */ 11327 11328 /* 11329 * Currently: 11330 * r0 holds resolved field 11331 * r9 holds object 11332 */ 11333.LOP_IPUT_BYTE_finish: 11334 @bl common_squeak2 11335 mov r1, rINST, lsr #8 @ r1<- A+ 11336 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11337 and r1, r1, #15 @ r1<- A 11338 cmp r9, #0 @ check object for null 11339 GET_VREG(r0, r1) @ r0<- fp[A] 11340 beq common_errNullObject @ object was null 11341 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11342 GET_INST_OPCODE(ip) @ extract opcode from rINST 11343 @ no-op @ releasing store 11344 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11345 GOTO_OPCODE(ip) @ jump to next instruction 11346 11347/* continuation for OP_IPUT_CHAR */ 11348 11349 /* 11350 * Currently: 11351 * r0 holds resolved field 11352 * r9 holds object 11353 */ 11354.LOP_IPUT_CHAR_finish: 11355 @bl common_squeak3 11356 mov r1, rINST, lsr #8 @ r1<- A+ 11357 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11358 and r1, r1, #15 @ r1<- A 11359 cmp r9, #0 @ check object for null 11360 GET_VREG(r0, r1) @ r0<- fp[A] 11361 beq common_errNullObject @ object was null 11362 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11363 GET_INST_OPCODE(ip) @ extract opcode from rINST 11364 @ no-op @ releasing store 11365 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11366 GOTO_OPCODE(ip) @ jump to next instruction 11367 11368/* continuation for OP_IPUT_SHORT */ 11369 11370 /* 11371 * Currently: 11372 * r0 holds resolved field 11373 * r9 holds object 11374 */ 11375.LOP_IPUT_SHORT_finish: 11376 @bl common_squeak4 11377 mov r1, rINST, lsr #8 @ r1<- A+ 11378 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11379 and r1, r1, #15 @ r1<- A 11380 cmp r9, #0 @ check object for null 11381 GET_VREG(r0, r1) @ r0<- fp[A] 11382 beq common_errNullObject @ object was null 11383 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11384 GET_INST_OPCODE(ip) @ extract opcode from rINST 11385 @ no-op @ releasing store 11386 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11387 GOTO_OPCODE(ip) @ jump to next instruction 11388 11389/* continuation for OP_SGET */ 11390 11391 /* 11392 * Continuation if the field has not yet been resolved. 11393 * r1: BBBB field ref 11394 */ 11395.LOP_SGET_resolve: 11396 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11397 EXPORT_PC() @ resolve() could throw, so export now 11398 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11399 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11400 cmp r0, #0 @ success? 11401 bne .LOP_SGET_finish @ yes, finish 11402 b common_exceptionThrown @ no, handle exception 11403 11404/* continuation for OP_SGET_WIDE */ 11405 11406 /* 11407 * Continuation if the field has not yet been resolved. 11408 * r1: BBBB field ref 11409 * 11410 * Returns StaticField pointer in r0. 11411 */ 11412.LOP_SGET_WIDE_resolve: 11413 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11414 EXPORT_PC() @ resolve() could throw, so export now 11415 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11416 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11417 cmp r0, #0 @ success? 11418 bne .LOP_SGET_WIDE_finish @ yes, finish 11419 b common_exceptionThrown @ no, handle exception 11420 11421/* continuation for OP_SGET_OBJECT */ 11422 11423 /* 11424 * Continuation if the field has not yet been resolved. 11425 * r1: BBBB field ref 11426 */ 11427.LOP_SGET_OBJECT_resolve: 11428 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11429 EXPORT_PC() @ resolve() could throw, so export now 11430 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11431 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11432 cmp r0, #0 @ success? 11433 bne .LOP_SGET_OBJECT_finish @ yes, finish 11434 b common_exceptionThrown @ no, handle exception 11435 11436/* continuation for OP_SGET_BOOLEAN */ 11437 11438 /* 11439 * Continuation if the field has not yet been resolved. 11440 * r1: BBBB field ref 11441 */ 11442.LOP_SGET_BOOLEAN_resolve: 11443 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11444 EXPORT_PC() @ resolve() could throw, so export now 11445 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11446 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11447 cmp r0, #0 @ success? 11448 bne .LOP_SGET_BOOLEAN_finish @ yes, finish 11449 b common_exceptionThrown @ no, handle exception 11450 11451/* continuation for OP_SGET_BYTE */ 11452 11453 /* 11454 * Continuation if the field has not yet been resolved. 11455 * r1: BBBB field ref 11456 */ 11457.LOP_SGET_BYTE_resolve: 11458 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11459 EXPORT_PC() @ resolve() could throw, so export now 11460 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11461 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11462 cmp r0, #0 @ success? 11463 bne .LOP_SGET_BYTE_finish @ yes, finish 11464 b common_exceptionThrown @ no, handle exception 11465 11466/* continuation for OP_SGET_CHAR */ 11467 11468 /* 11469 * Continuation if the field has not yet been resolved. 11470 * r1: BBBB field ref 11471 */ 11472.LOP_SGET_CHAR_resolve: 11473 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11474 EXPORT_PC() @ resolve() could throw, so export now 11475 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11476 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11477 cmp r0, #0 @ success? 11478 bne .LOP_SGET_CHAR_finish @ yes, finish 11479 b common_exceptionThrown @ no, handle exception 11480 11481/* continuation for OP_SGET_SHORT */ 11482 11483 /* 11484 * Continuation if the field has not yet been resolved. 11485 * r1: BBBB field ref 11486 */ 11487.LOP_SGET_SHORT_resolve: 11488 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11489 EXPORT_PC() @ resolve() could throw, so export now 11490 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11491 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11492 cmp r0, #0 @ success? 11493 bne .LOP_SGET_SHORT_finish @ yes, finish 11494 b common_exceptionThrown @ no, handle exception 11495 11496/* continuation for OP_SPUT */ 11497 11498 /* 11499 * Continuation if the field has not yet been resolved. 11500 * r1: BBBB field ref 11501 */ 11502.LOP_SPUT_resolve: 11503 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11504 EXPORT_PC() @ resolve() could throw, so export now 11505 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11506 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11507 cmp r0, #0 @ success? 11508 bne .LOP_SPUT_finish @ yes, finish 11509 b common_exceptionThrown @ no, handle exception 11510 11511/* continuation for OP_SPUT_WIDE */ 11512 11513 /* 11514 * Continuation if the field has not yet been resolved. 11515 * r1: BBBB field ref 11516 * r9: &fp[AA] 11517 * 11518 * Returns StaticField pointer in r2. 11519 */ 11520.LOP_SPUT_WIDE_resolve: 11521 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11522 EXPORT_PC() @ resolve() could throw, so export now 11523 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11524 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11525 cmp r0, #0 @ success? 11526 mov r2, r0 @ copy to r2 11527 bne .LOP_SPUT_WIDE_finish @ yes, finish 11528 b common_exceptionThrown @ no, handle exception 11529 11530/* continuation for OP_SPUT_OBJECT */ 11531.LOP_SPUT_OBJECT_finish: @ field ptr in r0 11532 mov r2, rINST, lsr #8 @ r2<- AA 11533 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11534 GET_VREG(r1, r2) @ r1<- fp[AA] 11535 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11536 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 11537 GET_INST_OPCODE(ip) @ extract opcode from rINST 11538 @ no-op @ releasing store 11539 str r1, [r0, #offStaticField_value] @ field<- vAA 11540 cmp r1, #0 @ stored a null object? 11541 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 11542 GOTO_OPCODE(ip) @ jump to next instruction 11543 11544/* continuation for OP_SPUT_BOOLEAN */ 11545 11546 /* 11547 * Continuation if the field has not yet been resolved. 11548 * r1: BBBB field ref 11549 */ 11550.LOP_SPUT_BOOLEAN_resolve: 11551 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11552 EXPORT_PC() @ resolve() could throw, so export now 11553 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11554 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11555 cmp r0, #0 @ success? 11556 bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 11557 b common_exceptionThrown @ no, handle exception 11558 11559/* continuation for OP_SPUT_BYTE */ 11560 11561 /* 11562 * Continuation if the field has not yet been resolved. 11563 * r1: BBBB field ref 11564 */ 11565.LOP_SPUT_BYTE_resolve: 11566 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11567 EXPORT_PC() @ resolve() could throw, so export now 11568 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11569 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11570 cmp r0, #0 @ success? 11571 bne .LOP_SPUT_BYTE_finish @ yes, finish 11572 b common_exceptionThrown @ no, handle exception 11573 11574/* continuation for OP_SPUT_CHAR */ 11575 11576 /* 11577 * Continuation if the field has not yet been resolved. 11578 * r1: BBBB field ref 11579 */ 11580.LOP_SPUT_CHAR_resolve: 11581 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11582 EXPORT_PC() @ resolve() could throw, so export now 11583 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11584 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11585 cmp r0, #0 @ success? 11586 bne .LOP_SPUT_CHAR_finish @ yes, finish 11587 b common_exceptionThrown @ no, handle exception 11588 11589/* continuation for OP_SPUT_SHORT */ 11590 11591 /* 11592 * Continuation if the field has not yet been resolved. 11593 * r1: BBBB field ref 11594 */ 11595.LOP_SPUT_SHORT_resolve: 11596 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11597 EXPORT_PC() @ resolve() could throw, so export now 11598 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11599 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11600 cmp r0, #0 @ success? 11601 bne .LOP_SPUT_SHORT_finish @ yes, finish 11602 b common_exceptionThrown @ no, handle exception 11603 11604/* continuation for OP_INVOKE_VIRTUAL */ 11605 11606 /* 11607 * At this point: 11608 * r0 = resolved base method 11609 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11610 */ 11611.LOP_INVOKE_VIRTUAL_continue: 11612 GET_VREG(r1, r10) @ r1<- "this" ptr 11613 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11614 cmp r1, #0 @ is "this" null? 11615 beq common_errNullObject @ null "this", throw exception 11616 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11617 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11618 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11619 bl common_invokeMethodNoRange @ continue on 11620 11621/* continuation for OP_INVOKE_SUPER */ 11622 11623 /* 11624 * At this point: 11625 * r0 = resolved base method 11626 * r9 = method->clazz 11627 */ 11628.LOP_INVOKE_SUPER_continue: 11629 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11630 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11631 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11632 EXPORT_PC() @ must export for invoke 11633 cmp r2, r3 @ compare (methodIndex, vtableCount) 11634 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 11635 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11636 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11637 bl common_invokeMethodNoRange @ continue on 11638 11639.LOP_INVOKE_SUPER_resolve: 11640 mov r0, r9 @ r0<- method->clazz 11641 mov r2, #METHOD_VIRTUAL @ resolver method type 11642 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11643 cmp r0, #0 @ got null? 11644 bne .LOP_INVOKE_SUPER_continue @ no, continue 11645 b common_exceptionThrown @ yes, handle exception 11646 11647 /* 11648 * Throw a NoSuchMethodError with the method name as the message. 11649 * r0 = resolved base method 11650 */ 11651.LOP_INVOKE_SUPER_nsm: 11652 ldr r1, [r0, #offMethod_name] @ r1<- method name 11653 b common_errNoSuchMethod 11654 11655/* continuation for OP_INVOKE_DIRECT */ 11656 11657 /* 11658 * On entry: 11659 * r1 = reference (BBBB or CCCC) 11660 * r10 = "this" register 11661 */ 11662.LOP_INVOKE_DIRECT_resolve: 11663 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11664 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11665 mov r2, #METHOD_DIRECT @ resolver method type 11666 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11667 cmp r0, #0 @ got null? 11668 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 11669 bne .LOP_INVOKE_DIRECT_finish @ no, continue 11670 b common_exceptionThrown @ yes, handle exception 11671 11672/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 11673 11674 /* 11675 * At this point: 11676 * r0 = resolved base method 11677 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11678 */ 11679.LOP_INVOKE_VIRTUAL_RANGE_continue: 11680 GET_VREG(r1, r10) @ r1<- "this" ptr 11681 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11682 cmp r1, #0 @ is "this" null? 11683 beq common_errNullObject @ null "this", throw exception 11684 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11685 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11686 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11687 bl common_invokeMethodRange @ continue on 11688 11689/* continuation for OP_INVOKE_SUPER_RANGE */ 11690 11691 /* 11692 * At this point: 11693 * r0 = resolved base method 11694 * r9 = method->clazz 11695 */ 11696.LOP_INVOKE_SUPER_RANGE_continue: 11697 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11698 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11699 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11700 EXPORT_PC() @ must export for invoke 11701 cmp r2, r3 @ compare (methodIndex, vtableCount) 11702 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 11703 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11704 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11705 bl common_invokeMethodRange @ continue on 11706 11707.LOP_INVOKE_SUPER_RANGE_resolve: 11708 mov r0, r9 @ r0<- method->clazz 11709 mov r2, #METHOD_VIRTUAL @ resolver method type 11710 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11711 cmp r0, #0 @ got null? 11712 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 11713 b common_exceptionThrown @ yes, handle exception 11714 11715 /* 11716 * Throw a NoSuchMethodError with the method name as the message. 11717 * r0 = resolved base method 11718 */ 11719.LOP_INVOKE_SUPER_RANGE_nsm: 11720 ldr r1, [r0, #offMethod_name] @ r1<- method name 11721 b common_errNoSuchMethod 11722 11723/* continuation for OP_INVOKE_DIRECT_RANGE */ 11724 11725 /* 11726 * On entry: 11727 * r1 = reference (BBBB or CCCC) 11728 * r10 = "this" register 11729 */ 11730.LOP_INVOKE_DIRECT_RANGE_resolve: 11731 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11732 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11733 mov r2, #METHOD_DIRECT @ resolver method type 11734 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11735 cmp r0, #0 @ got null? 11736 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 11737 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 11738 b common_exceptionThrown @ yes, handle exception 11739 11740/* continuation for OP_FLOAT_TO_LONG */ 11741/* 11742 * Convert the float in r0 to a long in r0/r1. 11743 * 11744 * We have to clip values to long min/max per the specification. The 11745 * expected common case is a "reasonable" value that converts directly 11746 * to modest integer. The EABI convert function isn't doing this for us. 11747 */ 11748f2l_doconv: 11749 stmfd sp!, {r4, lr} 11750 mov r1, #0x5f000000 @ (float)maxlong 11751 mov r4, r0 11752 bl __aeabi_fcmpge @ is arg >= maxlong? 11753 cmp r0, #0 @ nonzero == yes 11754 mvnne r0, #0 @ return maxlong (7fffffff) 11755 mvnne r1, #0x80000000 11756 ldmnefd sp!, {r4, pc} 11757 11758 mov r0, r4 @ recover arg 11759 mov r1, #0xdf000000 @ (float)minlong 11760 bl __aeabi_fcmple @ is arg <= minlong? 11761 cmp r0, #0 @ nonzero == yes 11762 movne r0, #0 @ return minlong (80000000) 11763 movne r1, #0x80000000 11764 ldmnefd sp!, {r4, pc} 11765 11766 mov r0, r4 @ recover arg 11767 mov r1, r4 11768 bl __aeabi_fcmpeq @ is arg == self? 11769 cmp r0, #0 @ zero == no 11770 moveq r1, #0 @ return zero for NaN 11771 ldmeqfd sp!, {r4, pc} 11772 11773 mov r0, r4 @ recover arg 11774 bl __aeabi_f2lz @ convert float to long 11775 ldmfd sp!, {r4, pc} 11776 11777/* continuation for OP_DOUBLE_TO_LONG */ 11778/* 11779 * Convert the double in r0/r1 to a long in r0/r1. 11780 * 11781 * We have to clip values to long min/max per the specification. The 11782 * expected common case is a "reasonable" value that converts directly 11783 * to modest integer. The EABI convert function isn't doing this for us. 11784 */ 11785d2l_doconv: 11786 stmfd sp!, {r4, r5, lr} @ save regs 11787 mov r3, #0x43000000 @ maxlong, as a double (high word) 11788 add r3, #0x00e00000 @ 0x43e00000 11789 mov r2, #0 @ maxlong, as a double (low word) 11790 sub sp, sp, #4 @ align for EABI 11791 mov r4, r0 @ save a copy of r0 11792 mov r5, r1 @ and r1 11793 bl __aeabi_dcmpge @ is arg >= maxlong? 11794 cmp r0, #0 @ nonzero == yes 11795 mvnne r0, #0 @ return maxlong (7fffffffffffffff) 11796 mvnne r1, #0x80000000 11797 bne 1f 11798 11799 mov r0, r4 @ recover arg 11800 mov r1, r5 11801 mov r3, #0xc3000000 @ minlong, as a double (high word) 11802 add r3, #0x00e00000 @ 0xc3e00000 11803 mov r2, #0 @ minlong, as a double (low word) 11804 bl __aeabi_dcmple @ is arg <= minlong? 11805 cmp r0, #0 @ nonzero == yes 11806 movne r0, #0 @ return minlong (8000000000000000) 11807 movne r1, #0x80000000 11808 bne 1f 11809 11810 mov r0, r4 @ recover arg 11811 mov r1, r5 11812 mov r2, r4 @ compare against self 11813 mov r3, r5 11814 bl __aeabi_dcmpeq @ is arg == self? 11815 cmp r0, #0 @ zero == no 11816 moveq r1, #0 @ return zero for NaN 11817 beq 1f 11818 11819 mov r0, r4 @ recover arg 11820 mov r1, r5 11821 bl __aeabi_d2lz @ convert double to long 11822 118231: 11824 add sp, sp, #4 11825 ldmfd sp!, {r4, r5, pc} 11826 11827/* continuation for OP_MUL_LONG */ 11828 11829.LOP_MUL_LONG_finish: 11830 GET_INST_OPCODE(ip) @ extract opcode from rINST 11831 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 11832 GOTO_OPCODE(ip) @ jump to next instruction 11833 11834/* continuation for OP_SHL_LONG */ 11835 11836.LOP_SHL_LONG_finish: 11837 mov r0, r0, asl r2 @ r0<- r0 << r2 11838 GET_INST_OPCODE(ip) @ extract opcode from rINST 11839 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11840 GOTO_OPCODE(ip) @ jump to next instruction 11841 11842/* continuation for OP_SHR_LONG */ 11843 11844.LOP_SHR_LONG_finish: 11845 mov r1, r1, asr r2 @ r1<- r1 >> r2 11846 GET_INST_OPCODE(ip) @ extract opcode from rINST 11847 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11848 GOTO_OPCODE(ip) @ jump to next instruction 11849 11850/* continuation for OP_USHR_LONG */ 11851 11852.LOP_USHR_LONG_finish: 11853 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 11854 GET_INST_OPCODE(ip) @ extract opcode from rINST 11855 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11856 GOTO_OPCODE(ip) @ jump to next instruction 11857 11858/* continuation for OP_SHL_LONG_2ADDR */ 11859 11860.LOP_SHL_LONG_2ADDR_finish: 11861 GET_INST_OPCODE(ip) @ extract opcode from rINST 11862 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11863 GOTO_OPCODE(ip) @ jump to next instruction 11864 11865/* continuation for OP_SHR_LONG_2ADDR */ 11866 11867.LOP_SHR_LONG_2ADDR_finish: 11868 GET_INST_OPCODE(ip) @ extract opcode from rINST 11869 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11870 GOTO_OPCODE(ip) @ jump to next instruction 11871 11872/* continuation for OP_USHR_LONG_2ADDR */ 11873 11874.LOP_USHR_LONG_2ADDR_finish: 11875 GET_INST_OPCODE(ip) @ extract opcode from rINST 11876 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11877 GOTO_OPCODE(ip) @ jump to next instruction 11878 11879/* continuation for OP_IGET_VOLATILE */ 11880 11881 /* 11882 * Currently: 11883 * r0 holds resolved field 11884 * r9 holds object 11885 */ 11886.LOP_IGET_VOLATILE_finish: 11887 @bl common_squeak0 11888 cmp r9, #0 @ check object for null 11889 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11890 beq common_errNullObject @ object was null 11891 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11892 SMP_DMB @ acquiring load 11893 mov r2, rINST, lsr #8 @ r2<- A+ 11894 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11895 and r2, r2, #15 @ r2<- A 11896 GET_INST_OPCODE(ip) @ extract opcode from rINST 11897 SET_VREG(r0, r2) @ fp[A]<- r0 11898 GOTO_OPCODE(ip) @ jump to next instruction 11899 11900/* continuation for OP_IPUT_VOLATILE */ 11901 11902 /* 11903 * Currently: 11904 * r0 holds resolved field 11905 * r9 holds object 11906 */ 11907.LOP_IPUT_VOLATILE_finish: 11908 @bl common_squeak0 11909 mov r1, rINST, lsr #8 @ r1<- A+ 11910 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11911 and r1, r1, #15 @ r1<- A 11912 cmp r9, #0 @ check object for null 11913 GET_VREG(r0, r1) @ r0<- fp[A] 11914 beq common_errNullObject @ object was null 11915 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11916 GET_INST_OPCODE(ip) @ extract opcode from rINST 11917 SMP_DMB @ releasing store 11918 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11919 GOTO_OPCODE(ip) @ jump to next instruction 11920 11921/* continuation for OP_SGET_VOLATILE */ 11922 11923 /* 11924 * Continuation if the field has not yet been resolved. 11925 * r1: BBBB field ref 11926 */ 11927.LOP_SGET_VOLATILE_resolve: 11928 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11929 EXPORT_PC() @ resolve() could throw, so export now 11930 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11931 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11932 cmp r0, #0 @ success? 11933 bne .LOP_SGET_VOLATILE_finish @ yes, finish 11934 b common_exceptionThrown @ no, handle exception 11935 11936/* continuation for OP_SPUT_VOLATILE */ 11937 11938 /* 11939 * Continuation if the field has not yet been resolved. 11940 * r1: BBBB field ref 11941 */ 11942.LOP_SPUT_VOLATILE_resolve: 11943 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11944 EXPORT_PC() @ resolve() could throw, so export now 11945 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11946 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11947 cmp r0, #0 @ success? 11948 bne .LOP_SPUT_VOLATILE_finish @ yes, finish 11949 b common_exceptionThrown @ no, handle exception 11950 11951/* continuation for OP_IGET_OBJECT_VOLATILE */ 11952 11953 /* 11954 * Currently: 11955 * r0 holds resolved field 11956 * r9 holds object 11957 */ 11958.LOP_IGET_OBJECT_VOLATILE_finish: 11959 @bl common_squeak0 11960 cmp r9, #0 @ check object for null 11961 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11962 beq common_errNullObject @ object was null 11963 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11964 SMP_DMB @ acquiring load 11965 mov r2, rINST, lsr #8 @ r2<- A+ 11966 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11967 and r2, r2, #15 @ r2<- A 11968 GET_INST_OPCODE(ip) @ extract opcode from rINST 11969 SET_VREG(r0, r2) @ fp[A]<- r0 11970 GOTO_OPCODE(ip) @ jump to next instruction 11971 11972/* continuation for OP_IGET_WIDE_VOLATILE */ 11973 11974 /* 11975 * Currently: 11976 * r0 holds resolved field 11977 * r9 holds object 11978 */ 11979.LOP_IGET_WIDE_VOLATILE_finish: 11980 cmp r9, #0 @ check object for null 11981 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11982 beq common_errNullObject @ object was null 11983 .if 1 11984 add r0, r9, r3 @ r0<- address of field 11985 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 11986 .else 11987 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11988 .endif 11989 mov r2, rINST, lsr #8 @ r2<- A+ 11990 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11991 and r2, r2, #15 @ r2<- A 11992 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11993 GET_INST_OPCODE(ip) @ extract opcode from rINST 11994 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11995 GOTO_OPCODE(ip) @ jump to next instruction 11996 11997/* continuation for OP_IPUT_WIDE_VOLATILE */ 11998 11999 /* 12000 * Currently: 12001 * r0 holds resolved field 12002 * r9 holds object 12003 */ 12004.LOP_IPUT_WIDE_VOLATILE_finish: 12005 mov r2, rINST, lsr #8 @ r2<- A+ 12006 cmp r9, #0 @ check object for null 12007 and r2, r2, #15 @ r2<- A 12008 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12009 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 12010 beq common_errNullObject @ object was null 12011 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12012 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 12013 GET_INST_OPCODE(r10) @ extract opcode from rINST 12014 .if 1 12015 add r2, r9, r3 @ r2<- target address 12016 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 12017 .else 12018 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12019 .endif 12020 GOTO_OPCODE(r10) @ jump to next instruction 12021 12022/* continuation for OP_SGET_WIDE_VOLATILE */ 12023 12024 /* 12025 * Continuation if the field has not yet been resolved. 12026 * r1: BBBB field ref 12027 * 12028 * Returns StaticField pointer in r0. 12029 */ 12030.LOP_SGET_WIDE_VOLATILE_resolve: 12031 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12032 EXPORT_PC() @ resolve() could throw, so export now 12033 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12034 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12035 cmp r0, #0 @ success? 12036 bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 12037 b common_exceptionThrown @ no, handle exception 12038 12039/* continuation for OP_SPUT_WIDE_VOLATILE */ 12040 12041 /* 12042 * Continuation if the field has not yet been resolved. 12043 * r1: BBBB field ref 12044 * r9: &fp[AA] 12045 * 12046 * Returns StaticField pointer in r2. 12047 */ 12048.LOP_SPUT_WIDE_VOLATILE_resolve: 12049 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12050 EXPORT_PC() @ resolve() could throw, so export now 12051 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12052 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12053 cmp r0, #0 @ success? 12054 mov r2, r0 @ copy to r2 12055 bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 12056 b common_exceptionThrown @ no, handle exception 12057 12058/* continuation for OP_EXECUTE_INLINE */ 12059 12060 /* 12061 * Extract args, call function. 12062 * r0 = #of args (0-4) 12063 * r10 = call index 12064 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12065 * 12066 * Other ideas: 12067 * - Use a jump table from the main piece to jump directly into the 12068 * AND/LDR pairs. Costs a data load, saves a branch. 12069 * - Have five separate pieces that do the loading, so we can work the 12070 * interleave a little better. Increases code size. 12071 */ 12072.LOP_EXECUTE_INLINE_continue: 12073 rsb r0, r0, #4 @ r0<- 4-r0 12074 FETCH(r9, 2) @ r9<- FEDC 12075 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12076 bl common_abort @ (skipped due to ARM prefetch) 120774: and ip, r9, #0xf000 @ isolate F 12078 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 120793: and ip, r9, #0x0f00 @ isolate E 12080 ldr r2, [rFP, ip, lsr #6] @ r2<- vE 120812: and ip, r9, #0x00f0 @ isolate D 12082 ldr r1, [rFP, ip, lsr #2] @ r1<- vD 120831: and ip, r9, #0x000f @ isolate C 12084 ldr r0, [rFP, ip, lsl #2] @ r0<- vC 120850: 12086 ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 12087 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12088 @ (not reached) 12089 12090.LOP_EXECUTE_INLINE_table: 12091 .word gDvmInlineOpsTable 12092 12093/* continuation for OP_EXECUTE_INLINE_RANGE */ 12094 12095 /* 12096 * Extract args, call function. 12097 * r0 = #of args (0-4) 12098 * r10 = call index 12099 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12100 */ 12101.LOP_EXECUTE_INLINE_RANGE_continue: 12102 rsb r0, r0, #4 @ r0<- 4-r0 12103 FETCH(r9, 2) @ r9<- CCCC 12104 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12105 bl common_abort @ (skipped due to ARM prefetch) 121064: add ip, r9, #3 @ base+3 12107 GET_VREG(r3, ip) @ r3<- vBase[3] 121083: add ip, r9, #2 @ base+2 12109 GET_VREG(r2, ip) @ r2<- vBase[2] 121102: add ip, r9, #1 @ base+1 12111 GET_VREG(r1, ip) @ r1<- vBase[1] 121121: add ip, r9, #0 @ (nop) 12113 GET_VREG(r0, ip) @ r0<- vBase[0] 121140: 12115 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 12116 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12117 @ (not reached) 12118 12119.LOP_EXECUTE_INLINE_RANGE_table: 12120 .word gDvmInlineOpsTable 12121 12122/* continuation for OP_IPUT_OBJECT_VOLATILE */ 12123 12124 /* 12125 * Currently: 12126 * r0 holds resolved field 12127 * r9 holds object 12128 */ 12129.LOP_IPUT_OBJECT_VOLATILE_finish: 12130 @bl common_squeak0 12131 mov r1, rINST, lsr #8 @ r1<- A+ 12132 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12133 and r1, r1, #15 @ r1<- A 12134 cmp r9, #0 @ check object for null 12135 GET_VREG(r0, r1) @ r0<- fp[A] 12136 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12137 beq common_errNullObject @ object was null 12138 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12139 GET_INST_OPCODE(ip) @ extract opcode from rINST 12140 SMP_DMB @ releasing store 12141 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12142 cmp r0, #0 @ stored a null reference? 12143 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12144 GOTO_OPCODE(ip) @ jump to next instruction 12145 12146/* continuation for OP_SGET_OBJECT_VOLATILE */ 12147 12148 /* 12149 * Continuation if the field has not yet been resolved. 12150 * r1: BBBB field ref 12151 */ 12152.LOP_SGET_OBJECT_VOLATILE_resolve: 12153 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12154 EXPORT_PC() @ resolve() could throw, so export now 12155 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12156 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12157 cmp r0, #0 @ success? 12158 bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish 12159 b common_exceptionThrown @ no, handle exception 12160 12161/* continuation for OP_SPUT_OBJECT_VOLATILE */ 12162.LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 12163 mov r2, rINST, lsr #8 @ r2<- AA 12164 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12165 GET_VREG(r1, r2) @ r1<- fp[AA] 12166 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12167 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 12168 GET_INST_OPCODE(ip) @ extract opcode from rINST 12169 SMP_DMB @ releasing store 12170 str r1, [r0, #offStaticField_value] @ field<- vAA 12171 cmp r1, #0 @ stored a null object? 12172 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12173 GOTO_OPCODE(ip) @ jump to next instruction 12174 12175/* continuation for OP_CONST_CLASS_JUMBO */ 12176 12177 /* 12178 * Continuation if the Class has not yet been resolved. 12179 * r1: AAAAAAAA (Class ref) 12180 * r9: target register 12181 */ 12182.LOP_CONST_CLASS_JUMBO_resolve: 12183 EXPORT_PC() 12184 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12185 mov r2, #1 @ r2<- true 12186 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12187 bl dvmResolveClass @ r0<- Class reference 12188 cmp r0, #0 @ failed? 12189 beq common_exceptionThrown @ yup, handle the exception 12190 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12191 GET_INST_OPCODE(ip) @ extract opcode from rINST 12192 SET_VREG(r0, r9) @ vBBBB<- r0 12193 GOTO_OPCODE(ip) @ jump to next instruction 12194 12195/* continuation for OP_CHECK_CAST_JUMBO */ 12196 12197 /* 12198 * Trivial test failed, need to perform full check. This is common. 12199 * r0 holds obj->clazz 12200 * r1 holds desired class resolved from AAAAAAAA 12201 * r9 holds object 12202 */ 12203.LOP_CHECK_CAST_JUMBO_fullcheck: 12204 mov r10, r1 @ avoid ClassObject getting clobbered 12205 bl dvmInstanceofNonTrivial @ r0<- boolean result 12206 cmp r0, #0 @ failed? 12207 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success 12208 12209 @ A cast has failed. We need to throw a ClassCastException. 12210 EXPORT_PC() @ about to throw 12211 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 12212 mov r1, r10 @ r1<- desired class 12213 bl dvmThrowClassCastException 12214 b common_exceptionThrown 12215 12216 /* 12217 * Advance PC and get the next opcode. 12218 */ 12219.LOP_CHECK_CAST_JUMBO_okay: 12220 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12221 GET_INST_OPCODE(ip) @ extract opcode from rINST 12222 GOTO_OPCODE(ip) @ jump to next instruction 12223 12224 /* 12225 * Resolution required. This is the least-likely path. 12226 * 12227 * r2 holds AAAAAAAA 12228 * r9 holds object 12229 */ 12230.LOP_CHECK_CAST_JUMBO_resolve: 12231 EXPORT_PC() @ resolve() could throw 12232 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12233 mov r1, r2 @ r1<- AAAAAAAA 12234 mov r2, #0 @ r2<- false 12235 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12236 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12237 cmp r0, #0 @ got null? 12238 beq common_exceptionThrown @ yes, handle exception 12239 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12240 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 12241 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off 12242 12243/* continuation for OP_INSTANCE_OF_JUMBO */ 12244 12245 /* 12246 * Class resolved, determine type of check necessary. This is common. 12247 * r0 holds obj->clazz 12248 * r1 holds class resolved from AAAAAAAA 12249 * r9 holds BBBB 12250 */ 12251.LOP_INSTANCE_OF_JUMBO_resolved: 12252 cmp r0, r1 @ same class (trivial success)? 12253 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish 12254 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck 12255 12256 /* 12257 * Trivial test failed, need to perform full check. This is common. 12258 * r0 holds obj->clazz 12259 * r1 holds class resolved from AAAAAAAA 12260 * r9 holds BBBB 12261 */ 12262.LOP_INSTANCE_OF_JUMBO_fullcheck: 12263 bl dvmInstanceofNonTrivial @ r0<- boolean result 12264 @ fall through to OP_INSTANCE_OF_JUMBO_store 12265 12266 /* 12267 * r0 holds boolean result 12268 * r9 holds BBBB 12269 */ 12270.LOP_INSTANCE_OF_JUMBO_store: 12271 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12272 SET_VREG(r0, r9) @ vBBBB<- r0 12273 GET_INST_OPCODE(ip) @ extract opcode from rINST 12274 GOTO_OPCODE(ip) @ jump to next instruction 12275 12276 /* 12277 * Trivial test succeeded, save and bail. 12278 * r9 holds BBBB 12279 */ 12280.LOP_INSTANCE_OF_JUMBO_trivial: 12281 mov r0, #1 @ indicate success 12282 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper 12283 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12284 SET_VREG(r0, r9) @ vBBBB<- r0 12285 GET_INST_OPCODE(ip) @ extract opcode from rINST 12286 GOTO_OPCODE(ip) @ jump to next instruction 12287 12288 /* 12289 * Resolution required. This is the least-likely path. 12290 * 12291 * r3 holds AAAAAAAA 12292 * r9 holds BBBB 12293 */ 12294 12295.LOP_INSTANCE_OF_JUMBO_resolve: 12296 EXPORT_PC() @ resolve() could throw 12297 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12298 mov r1, r3 @ r1<- AAAAAAAA 12299 mov r2, #1 @ r2<- true 12300 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12301 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12302 cmp r0, #0 @ got null? 12303 beq common_exceptionThrown @ yes, handle exception 12304 FETCH(r3, 4) @ r3<- vCCCC 12305 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12306 GET_VREG(r0, r3) @ r0<- vCCCC (object) 12307 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 12308 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off 12309 12310/* continuation for OP_NEW_INSTANCE_JUMBO */ 12311 12312 .balign 32 @ minimize cache lines 12313.LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object 12314 FETCH(r3, 3) @ r3<- BBBB 12315 cmp r0, #0 @ failed? 12316 beq common_exceptionThrown @ yes, handle the exception 12317 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12318 GET_INST_OPCODE(ip) @ extract opcode from rINST 12319 SET_VREG(r0, r3) @ vBBBB<- r0 12320 GOTO_OPCODE(ip) @ jump to next instruction 12321 12322 /* 12323 * Class initialization required. 12324 * 12325 * r0 holds class object 12326 */ 12327.LOP_NEW_INSTANCE_JUMBO_needinit: 12328 mov r9, r0 @ save r0 12329 bl dvmInitClass @ initialize class 12330 cmp r0, #0 @ check boolean result 12331 mov r0, r9 @ restore r0 12332 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue 12333 b common_exceptionThrown @ failed, deal with init exception 12334 12335 /* 12336 * Resolution required. This is the least-likely path. 12337 * 12338 * r1 holds AAAAAAAA 12339 */ 12340.LOP_NEW_INSTANCE_JUMBO_resolve: 12341 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12342 mov r2, #0 @ r2<- false 12343 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12344 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12345 cmp r0, #0 @ got null? 12346 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue 12347 b common_exceptionThrown @ yes, handle exception 12348 12349/* continuation for OP_NEW_ARRAY_JUMBO */ 12350 12351 12352 /* 12353 * Resolve class. (This is an uncommon case.) 12354 * 12355 * r1 holds array length 12356 * r2 holds class ref AAAAAAAA 12357 */ 12358.LOP_NEW_ARRAY_JUMBO_resolve: 12359 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12360 mov r9, r1 @ r9<- length (save) 12361 mov r1, r2 @ r1<- AAAAAAAA 12362 mov r2, #0 @ r2<- false 12363 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12364 bl dvmResolveClass @ r0<- call(clazz, ref) 12365 cmp r0, #0 @ got null? 12366 mov r1, r9 @ r1<- length (restore) 12367 beq common_exceptionThrown @ yes, handle exception 12368 @ fall through to OP_NEW_ARRAY_JUMBO_finish 12369 12370 /* 12371 * Finish allocation. 12372 * 12373 * r0 holds class 12374 * r1 holds array length 12375 */ 12376.LOP_NEW_ARRAY_JUMBO_finish: 12377 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 12378 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 12379 cmp r0, #0 @ failed? 12380 FETCH(r2, 3) @ r2<- vBBBB 12381 beq common_exceptionThrown @ yes, handle the exception 12382 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12383 GET_INST_OPCODE(ip) @ extract opcode from rINST 12384 SET_VREG(r0, r2) @ vBBBB<- r0 12385 GOTO_OPCODE(ip) @ jump to next instruction 12386 12387/* continuation for OP_FILLED_NEW_ARRAY_JUMBO */ 12388 12389 /* 12390 * On entry: 12391 * r0 holds array class 12392 */ 12393.LOP_FILLED_NEW_ARRAY_JUMBO_continue: 12394 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 12395 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 12396 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 12397 FETCH(r1, 3) @ r1<- BBBB (length) 12398 cmp rINST, #'I' @ array of ints? 12399 cmpne rINST, #'L' @ array of objects? 12400 cmpne rINST, #'[' @ array of arrays? 12401 mov r9, r1 @ save length in r9 12402 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet 12403 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 12404 cmp r0, #0 @ null return? 12405 beq common_exceptionThrown @ alloc failed, handle exception 12406 12407 FETCH(r1, 4) @ r1<- CCCC 12408 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 12409 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 12410 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 12411 subs r9, r9, #1 @ length--, check for neg 12412 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST 12413 bmi 2f @ was zero, bail 12414 12415 @ copy values from registers into the array 12416 @ r0=array, r1=CCCC, r9=BBBB (length) 12417 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 124181: ldr r3, [r2], #4 @ r3<- *r2++ 12419 subs r9, r9, #1 @ count-- 12420 str r3, [r0], #4 @ *contents++ = vX 12421 bpl 1b 12422 124232: ldr r0, [rSELF, #offThread_retval] @ r0<- object 12424 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 12425 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12426 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 12427 cmp r1, #'I' @ Is int array? 12428 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 12429 GOTO_OPCODE(ip) @ execute it 12430 12431 /* 12432 * Throw an exception indicating that we have not implemented this 12433 * mode of filled-new-array. 12434 */ 12435.LOP_FILLED_NEW_ARRAY_JUMBO_notimpl: 12436 ldr r0, .L_strFilledNewArrayNotImpl 12437 bl dvmThrowInternalError 12438 b common_exceptionThrown 12439 12440/* continuation for OP_IGET_JUMBO */ 12441 12442 /* 12443 * Currently: 12444 * r0 holds resolved field 12445 * r9 holds object 12446 */ 12447.LOP_IGET_JUMBO_resolved: 12448 cmp r0, #0 @ resolution unsuccessful? 12449 beq common_exceptionThrown @ yes, throw exception 12450 @ fall through to OP_IGET_JUMBO_finish 12451 12452 /* 12453 * Currently: 12454 * r0 holds resolved field 12455 * r9 holds object 12456 */ 12457.LOP_IGET_JUMBO_finish: 12458 @bl common_squeak0 12459 cmp r9, #0 @ check object for null 12460 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12461 beq common_errNullObject @ object was null 12462 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12463 @ no-op @ acquiring load 12464 FETCH(r2, 3) @ r2<- BBBB 12465 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12466 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12467 GET_INST_OPCODE(ip) @ extract opcode from rINST 12468 GOTO_OPCODE(ip) @ jump to next instruction 12469 12470/* continuation for OP_IGET_WIDE_JUMBO */ 12471 12472 /* 12473 * Currently: 12474 * r0 holds resolved field 12475 * r9 holds object 12476 */ 12477.LOP_IGET_WIDE_JUMBO_resolved: 12478 cmp r0, #0 @ resolution unsuccessful? 12479 beq common_exceptionThrown @ yes, throw exception 12480 @ fall through to OP_IGET_WIDE_JUMBO_finish 12481 12482 /* 12483 * Currently: 12484 * r0 holds resolved field 12485 * r9 holds object 12486 */ 12487.LOP_IGET_WIDE_JUMBO_finish: 12488 cmp r9, #0 @ check object for null 12489 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12490 beq common_errNullObject @ object was null 12491 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12492 FETCH(r2, 3) @ r2<- BBBB 12493 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12494 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12495 GET_INST_OPCODE(ip) @ extract opcode from rINST 12496 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 12497 GOTO_OPCODE(ip) @ jump to next instruction 12498 12499/* continuation for OP_IGET_OBJECT_JUMBO */ 12500 12501 /* 12502 * Currently: 12503 * r0 holds resolved field 12504 * r9 holds object 12505 */ 12506.LOP_IGET_OBJECT_JUMBO_resolved: 12507 cmp r0, #0 @ resolution unsuccessful? 12508 beq common_exceptionThrown @ yes, throw exception 12509 @ fall through to OP_IGET_OBJECT_JUMBO_finish 12510 12511 /* 12512 * Currently: 12513 * r0 holds resolved field 12514 * r9 holds object 12515 */ 12516.LOP_IGET_OBJECT_JUMBO_finish: 12517 @bl common_squeak0 12518 cmp r9, #0 @ check object for null 12519 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12520 beq common_errNullObject @ object was null 12521 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12522 @ no-op @ acquiring load 12523 FETCH(r2, 3) @ r2<- BBBB 12524 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12525 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12526 GET_INST_OPCODE(ip) @ extract opcode from rINST 12527 GOTO_OPCODE(ip) @ jump to next instruction 12528 12529/* continuation for OP_IGET_BOOLEAN_JUMBO */ 12530 12531 /* 12532 * Currently: 12533 * r0 holds resolved field 12534 * r9 holds object 12535 */ 12536.LOP_IGET_BOOLEAN_JUMBO_resolved: 12537 cmp r0, #0 @ resolution unsuccessful? 12538 beq common_exceptionThrown @ yes, throw exception 12539 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish 12540 12541 /* 12542 * Currently: 12543 * r0 holds resolved field 12544 * r9 holds object 12545 */ 12546.LOP_IGET_BOOLEAN_JUMBO_finish: 12547 @bl common_squeak1 12548 cmp r9, #0 @ check object for null 12549 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12550 beq common_errNullObject @ object was null 12551 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12552 @ no-op @ acquiring load 12553 FETCH(r2, 3) @ r2<- BBBB 12554 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12555 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12556 GET_INST_OPCODE(ip) @ extract opcode from rINST 12557 GOTO_OPCODE(ip) @ jump to next instruction 12558 12559/* continuation for OP_IGET_BYTE_JUMBO */ 12560 12561 /* 12562 * Currently: 12563 * r0 holds resolved field 12564 * r9 holds object 12565 */ 12566.LOP_IGET_BYTE_JUMBO_resolved: 12567 cmp r0, #0 @ resolution unsuccessful? 12568 beq common_exceptionThrown @ yes, throw exception 12569 @ fall through to OP_IGET_BYTE_JUMBO_finish 12570 12571 /* 12572 * Currently: 12573 * r0 holds resolved field 12574 * r9 holds object 12575 */ 12576.LOP_IGET_BYTE_JUMBO_finish: 12577 @bl common_squeak2 12578 cmp r9, #0 @ check object for null 12579 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12580 beq common_errNullObject @ object was null 12581 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12582 @ no-op @ acquiring load 12583 FETCH(r2, 3) @ r2<- BBBB 12584 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12585 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12586 GET_INST_OPCODE(ip) @ extract opcode from rINST 12587 GOTO_OPCODE(ip) @ jump to next instruction 12588 12589/* continuation for OP_IGET_CHAR_JUMBO */ 12590 12591 /* 12592 * Currently: 12593 * r0 holds resolved field 12594 * r9 holds object 12595 */ 12596.LOP_IGET_CHAR_JUMBO_resolved: 12597 cmp r0, #0 @ resolution unsuccessful? 12598 beq common_exceptionThrown @ yes, throw exception 12599 @ fall through to OP_IGET_CHAR_JUMBO_finish 12600 12601 /* 12602 * Currently: 12603 * r0 holds resolved field 12604 * r9 holds object 12605 */ 12606.LOP_IGET_CHAR_JUMBO_finish: 12607 @bl common_squeak3 12608 cmp r9, #0 @ check object for null 12609 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12610 beq common_errNullObject @ object was null 12611 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12612 @ no-op @ acquiring load 12613 FETCH(r2, 3) @ r2<- BBBB 12614 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12615 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12616 GET_INST_OPCODE(ip) @ extract opcode from rINST 12617 GOTO_OPCODE(ip) @ jump to next instruction 12618 12619/* continuation for OP_IGET_SHORT_JUMBO */ 12620 12621 /* 12622 * Currently: 12623 * r0 holds resolved field 12624 * r9 holds object 12625 */ 12626.LOP_IGET_SHORT_JUMBO_resolved: 12627 cmp r0, #0 @ resolution unsuccessful? 12628 beq common_exceptionThrown @ yes, throw exception 12629 @ fall through to OP_IGET_SHORT_JUMBO_finish 12630 12631 /* 12632 * Currently: 12633 * r0 holds resolved field 12634 * r9 holds object 12635 */ 12636.LOP_IGET_SHORT_JUMBO_finish: 12637 @bl common_squeak4 12638 cmp r9, #0 @ check object for null 12639 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12640 beq common_errNullObject @ object was null 12641 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12642 @ no-op @ acquiring load 12643 FETCH(r2, 3) @ r2<- BBBB 12644 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12645 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12646 GET_INST_OPCODE(ip) @ extract opcode from rINST 12647 GOTO_OPCODE(ip) @ jump to next instruction 12648 12649/* continuation for OP_IPUT_JUMBO */ 12650 12651 /* 12652 * Currently: 12653 * r0 holds resolved field 12654 * r9 holds object 12655 */ 12656.LOP_IPUT_JUMBO_resolved: 12657 cmp r0, #0 @ resolution unsuccessful? 12658 beq common_exceptionThrown @ yes, throw exception 12659 @ fall through to OP_IPUT_JUMBO_finish 12660 12661 /* 12662 * Currently: 12663 * r0 holds resolved field 12664 * r9 holds object 12665 */ 12666.LOP_IPUT_JUMBO_finish: 12667 @bl common_squeak0 12668 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12669 FETCH(r1, 3) @ r1<- BBBB 12670 cmp r9, #0 @ check object for null 12671 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12672 beq common_errNullObject @ object was null 12673 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12674 GET_INST_OPCODE(ip) @ extract opcode from rINST 12675 @ no-op @ releasing store 12676 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12677 GOTO_OPCODE(ip) @ jump to next instruction 12678 12679/* continuation for OP_IPUT_WIDE_JUMBO */ 12680 12681 /* 12682 * Currently: 12683 * r0 holds resolved field 12684 * r9 holds object 12685 */ 12686.LOP_IPUT_WIDE_JUMBO_resolved: 12687 cmp r0, #0 @ resolution unsuccessful? 12688 beq common_exceptionThrown @ yes, throw exception 12689 @ fall through to OP_IPUT_WIDE_JUMBO_finish 12690 12691 /* 12692 * Currently: 12693 * r0 holds resolved field 12694 * r9 holds object 12695 */ 12696.LOP_IPUT_WIDE_JUMBO_finish: 12697 cmp r9, #0 @ check object for null 12698 FETCH(r2, 3) @ r1<- BBBB 12699 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12700 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12701 beq common_errNullObject @ object was null 12702 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12703 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 12704 GET_INST_OPCODE(r10) @ extract opcode from rINST 12705 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12706 GOTO_OPCODE(r10) @ jump to next instruction 12707 12708/* continuation for OP_IPUT_OBJECT_JUMBO */ 12709 12710 /* 12711 * Currently: 12712 * r0 holds resolved field 12713 * r9 holds object 12714 */ 12715.LOP_IPUT_OBJECT_JUMBO_resolved: 12716 cmp r0, #0 @ resolution unsuccessful? 12717 beq common_exceptionThrown @ yes, throw exception 12718 @ fall through to OP_IPUT_OBJECT_JUMBO_finish 12719 12720 /* 12721 * Currently: 12722 * r0 holds resolved field 12723 * r9 holds object 12724 */ 12725.LOP_IPUT_OBJECT_JUMBO_finish: 12726 @bl common_squeak0 12727 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12728 FETCH(r1, 3) @ r1<- BBBB 12729 cmp r9, #0 @ check object for null 12730 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12731 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12732 beq common_errNullObject @ object was null 12733 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12734 GET_INST_OPCODE(ip) @ extract opcode from rINST 12735 @ no-op @ releasing store 12736 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12737 cmp r0, #0 @ stored a null reference? 12738 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12739 GOTO_OPCODE(ip) @ jump to next instruction 12740 12741/* continuation for OP_IPUT_BOOLEAN_JUMBO */ 12742 12743 /* 12744 * Currently: 12745 * r0 holds resolved field 12746 * r9 holds object 12747 */ 12748.LOP_IPUT_BOOLEAN_JUMBO_resolved: 12749 cmp r0, #0 @ resolution unsuccessful? 12750 beq common_exceptionThrown @ yes, throw exception 12751 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish 12752 12753 /* 12754 * Currently: 12755 * r0 holds resolved field 12756 * r9 holds object 12757 */ 12758.LOP_IPUT_BOOLEAN_JUMBO_finish: 12759 @bl common_squeak1 12760 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12761 FETCH(r1, 3) @ r1<- BBBB 12762 cmp r9, #0 @ check object for null 12763 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12764 beq common_errNullObject @ object was null 12765 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12766 GET_INST_OPCODE(ip) @ extract opcode from rINST 12767 @ no-op @ releasing store 12768 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12769 GOTO_OPCODE(ip) @ jump to next instruction 12770 12771/* continuation for OP_IPUT_BYTE_JUMBO */ 12772 12773 /* 12774 * Currently: 12775 * r0 holds resolved field 12776 * r9 holds object 12777 */ 12778.LOP_IPUT_BYTE_JUMBO_resolved: 12779 cmp r0, #0 @ resolution unsuccessful? 12780 beq common_exceptionThrown @ yes, throw exception 12781 @ fall through to OP_IPUT_BYTE_JUMBO_finish 12782 12783 /* 12784 * Currently: 12785 * r0 holds resolved field 12786 * r9 holds object 12787 */ 12788.LOP_IPUT_BYTE_JUMBO_finish: 12789 @bl common_squeak2 12790 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12791 FETCH(r1, 3) @ r1<- BBBB 12792 cmp r9, #0 @ check object for null 12793 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12794 beq common_errNullObject @ object was null 12795 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12796 GET_INST_OPCODE(ip) @ extract opcode from rINST 12797 @ no-op @ releasing store 12798 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12799 GOTO_OPCODE(ip) @ jump to next instruction 12800 12801/* continuation for OP_IPUT_CHAR_JUMBO */ 12802 12803 /* 12804 * Currently: 12805 * r0 holds resolved field 12806 * r9 holds object 12807 */ 12808.LOP_IPUT_CHAR_JUMBO_resolved: 12809 cmp r0, #0 @ resolution unsuccessful? 12810 beq common_exceptionThrown @ yes, throw exception 12811 @ fall through to OP_IPUT_CHAR_JUMBO_finish 12812 12813 /* 12814 * Currently: 12815 * r0 holds resolved field 12816 * r9 holds object 12817 */ 12818.LOP_IPUT_CHAR_JUMBO_finish: 12819 @bl common_squeak3 12820 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12821 FETCH(r1, 3) @ r1<- BBBB 12822 cmp r9, #0 @ check object for null 12823 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12824 beq common_errNullObject @ object was null 12825 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12826 GET_INST_OPCODE(ip) @ extract opcode from rINST 12827 @ no-op @ releasing store 12828 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12829 GOTO_OPCODE(ip) @ jump to next instruction 12830 12831/* continuation for OP_IPUT_SHORT_JUMBO */ 12832 12833 /* 12834 * Currently: 12835 * r0 holds resolved field 12836 * r9 holds object 12837 */ 12838.LOP_IPUT_SHORT_JUMBO_resolved: 12839 cmp r0, #0 @ resolution unsuccessful? 12840 beq common_exceptionThrown @ yes, throw exception 12841 @ fall through to OP_IPUT_SHORT_JUMBO_finish 12842 12843 /* 12844 * Currently: 12845 * r0 holds resolved field 12846 * r9 holds object 12847 */ 12848.LOP_IPUT_SHORT_JUMBO_finish: 12849 @bl common_squeak4 12850 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12851 FETCH(r1, 3) @ r1<- BBBB 12852 cmp r9, #0 @ check object for null 12853 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12854 beq common_errNullObject @ object was null 12855 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12856 GET_INST_OPCODE(ip) @ extract opcode from rINST 12857 @ no-op @ releasing store 12858 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12859 GOTO_OPCODE(ip) @ jump to next instruction 12860 12861/* continuation for OP_SGET_JUMBO */ 12862 12863 /* 12864 * Continuation if the field has not yet been resolved. 12865 * r1: AAAAAAAA field ref 12866 */ 12867.LOP_SGET_JUMBO_resolve: 12868 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12869 EXPORT_PC() @ resolve() could throw, so export now 12870 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12871 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12872 cmp r0, #0 @ success? 12873 bne .LOP_SGET_JUMBO_finish @ yes, finish 12874 b common_exceptionThrown @ no, handle exception 12875 12876/* continuation for OP_SGET_WIDE_JUMBO */ 12877 12878 /* 12879 * Continuation if the field has not yet been resolved. 12880 * r1: BBBB field ref 12881 * 12882 * Returns StaticField pointer in r0. 12883 */ 12884.LOP_SGET_WIDE_JUMBO_resolve: 12885 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12886 EXPORT_PC() @ resolve() could throw, so export now 12887 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12888 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12889 cmp r0, #0 @ success? 12890 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish 12891 b common_exceptionThrown @ no, handle exception 12892 12893/* continuation for OP_SGET_OBJECT_JUMBO */ 12894 12895 /* 12896 * Continuation if the field has not yet been resolved. 12897 * r1: AAAAAAAA field ref 12898 */ 12899.LOP_SGET_OBJECT_JUMBO_resolve: 12900 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12901 EXPORT_PC() @ resolve() could throw, so export now 12902 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12903 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12904 cmp r0, #0 @ success? 12905 bne .LOP_SGET_OBJECT_JUMBO_finish @ yes, finish 12906 b common_exceptionThrown @ no, handle exception 12907 12908/* continuation for OP_SGET_BOOLEAN_JUMBO */ 12909 12910 /* 12911 * Continuation if the field has not yet been resolved. 12912 * r1: AAAAAAAA field ref 12913 */ 12914.LOP_SGET_BOOLEAN_JUMBO_resolve: 12915 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12916 EXPORT_PC() @ resolve() could throw, so export now 12917 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12918 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12919 cmp r0, #0 @ success? 12920 bne .LOP_SGET_BOOLEAN_JUMBO_finish @ yes, finish 12921 b common_exceptionThrown @ no, handle exception 12922 12923/* continuation for OP_SGET_BYTE_JUMBO */ 12924 12925 /* 12926 * Continuation if the field has not yet been resolved. 12927 * r1: AAAAAAAA field ref 12928 */ 12929.LOP_SGET_BYTE_JUMBO_resolve: 12930 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12931 EXPORT_PC() @ resolve() could throw, so export now 12932 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12933 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12934 cmp r0, #0 @ success? 12935 bne .LOP_SGET_BYTE_JUMBO_finish @ yes, finish 12936 b common_exceptionThrown @ no, handle exception 12937 12938/* continuation for OP_SGET_CHAR_JUMBO */ 12939 12940 /* 12941 * Continuation if the field has not yet been resolved. 12942 * r1: AAAAAAAA field ref 12943 */ 12944.LOP_SGET_CHAR_JUMBO_resolve: 12945 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12946 EXPORT_PC() @ resolve() could throw, so export now 12947 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12948 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12949 cmp r0, #0 @ success? 12950 bne .LOP_SGET_CHAR_JUMBO_finish @ yes, finish 12951 b common_exceptionThrown @ no, handle exception 12952 12953/* continuation for OP_SGET_SHORT_JUMBO */ 12954 12955 /* 12956 * Continuation if the field has not yet been resolved. 12957 * r1: AAAAAAAA field ref 12958 */ 12959.LOP_SGET_SHORT_JUMBO_resolve: 12960 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12961 EXPORT_PC() @ resolve() could throw, so export now 12962 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12963 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12964 cmp r0, #0 @ success? 12965 bne .LOP_SGET_SHORT_JUMBO_finish @ yes, finish 12966 b common_exceptionThrown @ no, handle exception 12967 12968/* continuation for OP_SPUT_JUMBO */ 12969 12970 /* 12971 * Continuation if the field has not yet been resolved. 12972 * r1: AAAAAAAA field ref 12973 */ 12974.LOP_SPUT_JUMBO_resolve: 12975 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12976 EXPORT_PC() @ resolve() could throw, so export now 12977 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12978 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12979 cmp r0, #0 @ success? 12980 bne .LOP_SPUT_JUMBO_finish @ yes, finish 12981 b common_exceptionThrown @ no, handle exception 12982 12983/* continuation for OP_SPUT_WIDE_JUMBO */ 12984 12985 /* 12986 * Continuation if the field has not yet been resolved. 12987 * r1: BBBB field ref 12988 * r9: &fp[AA] 12989 * 12990 * Returns StaticField pointer in r2. 12991 */ 12992.LOP_SPUT_WIDE_JUMBO_resolve: 12993 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12994 EXPORT_PC() @ resolve() could throw, so export now 12995 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12996 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12997 cmp r0, #0 @ success? 12998 mov r2, r0 @ copy to r2 12999 bne .LOP_SPUT_WIDE_JUMBO_finish @ yes, finish 13000 b common_exceptionThrown @ no, handle exception 13001 13002/* continuation for OP_SPUT_OBJECT_JUMBO */ 13003 13004.LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0 13005 FETCH(r2, 3) @ r2<- BBBB 13006 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 13007 GET_VREG(r1, r2) @ r1<- fp[BBBB] 13008 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13009 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 13010 GET_INST_OPCODE(ip) @ extract opcode from rINST 13011 @ no-op @ releasing store 13012 str r1, [r0, #offStaticField_value] @ field<- vBBBB 13013 cmp r1, #0 @ stored a null object? 13014 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 13015 GOTO_OPCODE(ip) @ jump to next instruction 13016 13017/* continuation for OP_SPUT_BOOLEAN_JUMBO */ 13018 13019 /* 13020 * Continuation if the field has not yet been resolved. 13021 * r1: AAAAAAAA field ref 13022 */ 13023.LOP_SPUT_BOOLEAN_JUMBO_resolve: 13024 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13025 EXPORT_PC() @ resolve() could throw, so export now 13026 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13027 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13028 cmp r0, #0 @ success? 13029 bne .LOP_SPUT_BOOLEAN_JUMBO_finish @ yes, finish 13030 b common_exceptionThrown @ no, handle exception 13031 13032/* continuation for OP_SPUT_BYTE_JUMBO */ 13033 13034 /* 13035 * Continuation if the field has not yet been resolved. 13036 * r1: AAAAAAAA field ref 13037 */ 13038.LOP_SPUT_BYTE_JUMBO_resolve: 13039 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13040 EXPORT_PC() @ resolve() could throw, so export now 13041 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13042 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13043 cmp r0, #0 @ success? 13044 bne .LOP_SPUT_BYTE_JUMBO_finish @ yes, finish 13045 b common_exceptionThrown @ no, handle exception 13046 13047/* continuation for OP_SPUT_CHAR_JUMBO */ 13048 13049 /* 13050 * Continuation if the field has not yet been resolved. 13051 * r1: AAAAAAAA field ref 13052 */ 13053.LOP_SPUT_CHAR_JUMBO_resolve: 13054 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13055 EXPORT_PC() @ resolve() could throw, so export now 13056 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13057 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13058 cmp r0, #0 @ success? 13059 bne .LOP_SPUT_CHAR_JUMBO_finish @ yes, finish 13060 b common_exceptionThrown @ no, handle exception 13061 13062/* continuation for OP_SPUT_SHORT_JUMBO */ 13063 13064 /* 13065 * Continuation if the field has not yet been resolved. 13066 * r1: AAAAAAAA field ref 13067 */ 13068.LOP_SPUT_SHORT_JUMBO_resolve: 13069 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13070 EXPORT_PC() @ resolve() could throw, so export now 13071 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13072 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13073 cmp r0, #0 @ success? 13074 bne .LOP_SPUT_SHORT_JUMBO_finish @ yes, finish 13075 b common_exceptionThrown @ no, handle exception 13076 13077/* continuation for OP_INVOKE_VIRTUAL_JUMBO */ 13078 13079 /* 13080 * At this point: 13081 * r0 = resolved base method 13082 */ 13083.LOP_INVOKE_VIRTUAL_JUMBO_continue: 13084 FETCH(r10, 4) @ r10<- CCCC 13085 GET_VREG(r1, r10) @ r1<- "this" ptr 13086 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13087 cmp r1, #0 @ is "this" null? 13088 beq common_errNullObject @ null "this", throw exception 13089 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 13090 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 13091 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 13092 bl common_invokeMethodJumbo @ continue on 13093 13094/* continuation for OP_INVOKE_SUPER_JUMBO */ 13095 13096 /* 13097 * At this point: 13098 * r0 = resolved base method 13099 * r9 = method->clazz 13100 */ 13101.LOP_INVOKE_SUPER_JUMBO_continue: 13102 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 13103 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13104 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 13105 EXPORT_PC() @ must export for invoke 13106 cmp r2, r3 @ compare (methodIndex, vtableCount) 13107 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass 13108 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 13109 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 13110 bl common_invokeMethodJumbo @ continue on 13111 13112.LOP_INVOKE_SUPER_JUMBO_resolve: 13113 mov r0, r9 @ r0<- method->clazz 13114 mov r2, #METHOD_VIRTUAL @ resolver method type 13115 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13116 cmp r0, #0 @ got null? 13117 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue 13118 b common_exceptionThrown @ yes, handle exception 13119 13120 /* 13121 * Throw a NoSuchMethodError with the method name as the message. 13122 * r0 = resolved base method 13123 */ 13124.LOP_INVOKE_SUPER_JUMBO_nsm: 13125 ldr r1, [r0, #offMethod_name] @ r1<- method name 13126 b common_errNoSuchMethod 13127 13128/* continuation for OP_INVOKE_DIRECT_JUMBO */ 13129 13130 /* 13131 * On entry: 13132 * r1 = reference (CCCC) 13133 * r10 = "this" register 13134 */ 13135.LOP_INVOKE_DIRECT_JUMBO_resolve: 13136 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 13137 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 13138 mov r2, #METHOD_DIRECT @ resolver method type 13139 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13140 cmp r0, #0 @ got null? 13141 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 13142 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue 13143 b common_exceptionThrown @ yes, handle exception 13144 13145 .size dvmAsmSisterStart, .-dvmAsmSisterStart 13146 .global dvmAsmSisterEnd 13147dvmAsmSisterEnd: 13148 13149 13150 .global dvmAsmAltInstructionStart 13151 .type dvmAsmAltInstructionStart, %function 13152dvmAsmAltInstructionStart: 13153 .text 13154 13155/* ------------------------------ */ 13156 .balign 64 13157.L_ALT_OP_NOP: /* 0x00 */ 13158/* File: armv5te/ALT_STUB.S */ 13159/* 13160 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13161 * any interesting requests and then jump to the real instruction 13162 * handler. Note that the call to dvmCheckInst is done as a tail call. 13163 */ 13164 adrl lr, dvmAsmInstructionStart + (0 * 64) 13165 mov r0, rPC @ arg0 13166 mov r1, rSELF @ arg1 13167 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13168 13169/* ------------------------------ */ 13170 .balign 64 13171.L_ALT_OP_MOVE: /* 0x01 */ 13172/* File: armv5te/ALT_STUB.S */ 13173/* 13174 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13175 * any interesting requests and then jump to the real instruction 13176 * handler. Note that the call to dvmCheckInst is done as a tail call. 13177 */ 13178 adrl lr, dvmAsmInstructionStart + (1 * 64) 13179 mov r0, rPC @ arg0 13180 mov r1, rSELF @ arg1 13181 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13182 13183/* ------------------------------ */ 13184 .balign 64 13185.L_ALT_OP_MOVE_FROM16: /* 0x02 */ 13186/* File: armv5te/ALT_STUB.S */ 13187/* 13188 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13189 * any interesting requests and then jump to the real instruction 13190 * handler. Note that the call to dvmCheckInst is done as a tail call. 13191 */ 13192 adrl lr, dvmAsmInstructionStart + (2 * 64) 13193 mov r0, rPC @ arg0 13194 mov r1, rSELF @ arg1 13195 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13196 13197/* ------------------------------ */ 13198 .balign 64 13199.L_ALT_OP_MOVE_16: /* 0x03 */ 13200/* File: armv5te/ALT_STUB.S */ 13201/* 13202 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13203 * any interesting requests and then jump to the real instruction 13204 * handler. Note that the call to dvmCheckInst is done as a tail call. 13205 */ 13206 adrl lr, dvmAsmInstructionStart + (3 * 64) 13207 mov r0, rPC @ arg0 13208 mov r1, rSELF @ arg1 13209 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13210 13211/* ------------------------------ */ 13212 .balign 64 13213.L_ALT_OP_MOVE_WIDE: /* 0x04 */ 13214/* File: armv5te/ALT_STUB.S */ 13215/* 13216 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13217 * any interesting requests and then jump to the real instruction 13218 * handler. Note that the call to dvmCheckInst is done as a tail call. 13219 */ 13220 adrl lr, dvmAsmInstructionStart + (4 * 64) 13221 mov r0, rPC @ arg0 13222 mov r1, rSELF @ arg1 13223 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13224 13225/* ------------------------------ */ 13226 .balign 64 13227.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */ 13228/* File: armv5te/ALT_STUB.S */ 13229/* 13230 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13231 * any interesting requests and then jump to the real instruction 13232 * handler. Note that the call to dvmCheckInst is done as a tail call. 13233 */ 13234 adrl lr, dvmAsmInstructionStart + (5 * 64) 13235 mov r0, rPC @ arg0 13236 mov r1, rSELF @ arg1 13237 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13238 13239/* ------------------------------ */ 13240 .balign 64 13241.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */ 13242/* File: armv5te/ALT_STUB.S */ 13243/* 13244 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13245 * any interesting requests and then jump to the real instruction 13246 * handler. Note that the call to dvmCheckInst is done as a tail call. 13247 */ 13248 adrl lr, dvmAsmInstructionStart + (6 * 64) 13249 mov r0, rPC @ arg0 13250 mov r1, rSELF @ arg1 13251 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13252 13253/* ------------------------------ */ 13254 .balign 64 13255.L_ALT_OP_MOVE_OBJECT: /* 0x07 */ 13256/* File: armv5te/ALT_STUB.S */ 13257/* 13258 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13259 * any interesting requests and then jump to the real instruction 13260 * handler. Note that the call to dvmCheckInst is done as a tail call. 13261 */ 13262 adrl lr, dvmAsmInstructionStart + (7 * 64) 13263 mov r0, rPC @ arg0 13264 mov r1, rSELF @ arg1 13265 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13266 13267/* ------------------------------ */ 13268 .balign 64 13269.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 13270/* File: armv5te/ALT_STUB.S */ 13271/* 13272 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13273 * any interesting requests and then jump to the real instruction 13274 * handler. Note that the call to dvmCheckInst is done as a tail call. 13275 */ 13276 adrl lr, dvmAsmInstructionStart + (8 * 64) 13277 mov r0, rPC @ arg0 13278 mov r1, rSELF @ arg1 13279 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13280 13281/* ------------------------------ */ 13282 .balign 64 13283.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */ 13284/* File: armv5te/ALT_STUB.S */ 13285/* 13286 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13287 * any interesting requests and then jump to the real instruction 13288 * handler. Note that the call to dvmCheckInst is done as a tail call. 13289 */ 13290 adrl lr, dvmAsmInstructionStart + (9 * 64) 13291 mov r0, rPC @ arg0 13292 mov r1, rSELF @ arg1 13293 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13294 13295/* ------------------------------ */ 13296 .balign 64 13297.L_ALT_OP_MOVE_RESULT: /* 0x0a */ 13298/* File: armv5te/ALT_STUB.S */ 13299/* 13300 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13301 * any interesting requests and then jump to the real instruction 13302 * handler. Note that the call to dvmCheckInst is done as a tail call. 13303 */ 13304 adrl lr, dvmAsmInstructionStart + (10 * 64) 13305 mov r0, rPC @ arg0 13306 mov r1, rSELF @ arg1 13307 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13308 13309/* ------------------------------ */ 13310 .balign 64 13311.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */ 13312/* File: armv5te/ALT_STUB.S */ 13313/* 13314 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13315 * any interesting requests and then jump to the real instruction 13316 * handler. Note that the call to dvmCheckInst is done as a tail call. 13317 */ 13318 adrl lr, dvmAsmInstructionStart + (11 * 64) 13319 mov r0, rPC @ arg0 13320 mov r1, rSELF @ arg1 13321 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13322 13323/* ------------------------------ */ 13324 .balign 64 13325.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 13326/* File: armv5te/ALT_STUB.S */ 13327/* 13328 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13329 * any interesting requests and then jump to the real instruction 13330 * handler. Note that the call to dvmCheckInst is done as a tail call. 13331 */ 13332 adrl lr, dvmAsmInstructionStart + (12 * 64) 13333 mov r0, rPC @ arg0 13334 mov r1, rSELF @ arg1 13335 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13336 13337/* ------------------------------ */ 13338 .balign 64 13339.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */ 13340/* File: armv5te/ALT_STUB.S */ 13341/* 13342 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13343 * any interesting requests and then jump to the real instruction 13344 * handler. Note that the call to dvmCheckInst is done as a tail call. 13345 */ 13346 adrl lr, dvmAsmInstructionStart + (13 * 64) 13347 mov r0, rPC @ arg0 13348 mov r1, rSELF @ arg1 13349 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13350 13351/* ------------------------------ */ 13352 .balign 64 13353.L_ALT_OP_RETURN_VOID: /* 0x0e */ 13354/* File: armv5te/ALT_STUB.S */ 13355/* 13356 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13357 * any interesting requests and then jump to the real instruction 13358 * handler. Note that the call to dvmCheckInst is done as a tail call. 13359 */ 13360 adrl lr, dvmAsmInstructionStart + (14 * 64) 13361 mov r0, rPC @ arg0 13362 mov r1, rSELF @ arg1 13363 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13364 13365/* ------------------------------ */ 13366 .balign 64 13367.L_ALT_OP_RETURN: /* 0x0f */ 13368/* File: armv5te/ALT_STUB.S */ 13369/* 13370 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13371 * any interesting requests and then jump to the real instruction 13372 * handler. Note that the call to dvmCheckInst is done as a tail call. 13373 */ 13374 adrl lr, dvmAsmInstructionStart + (15 * 64) 13375 mov r0, rPC @ arg0 13376 mov r1, rSELF @ arg1 13377 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13378 13379/* ------------------------------ */ 13380 .balign 64 13381.L_ALT_OP_RETURN_WIDE: /* 0x10 */ 13382/* File: armv5te/ALT_STUB.S */ 13383/* 13384 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13385 * any interesting requests and then jump to the real instruction 13386 * handler. Note that the call to dvmCheckInst is done as a tail call. 13387 */ 13388 adrl lr, dvmAsmInstructionStart + (16 * 64) 13389 mov r0, rPC @ arg0 13390 mov r1, rSELF @ arg1 13391 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13392 13393/* ------------------------------ */ 13394 .balign 64 13395.L_ALT_OP_RETURN_OBJECT: /* 0x11 */ 13396/* File: armv5te/ALT_STUB.S */ 13397/* 13398 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13399 * any interesting requests and then jump to the real instruction 13400 * handler. Note that the call to dvmCheckInst is done as a tail call. 13401 */ 13402 adrl lr, dvmAsmInstructionStart + (17 * 64) 13403 mov r0, rPC @ arg0 13404 mov r1, rSELF @ arg1 13405 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13406 13407/* ------------------------------ */ 13408 .balign 64 13409.L_ALT_OP_CONST_4: /* 0x12 */ 13410/* File: armv5te/ALT_STUB.S */ 13411/* 13412 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13413 * any interesting requests and then jump to the real instruction 13414 * handler. Note that the call to dvmCheckInst is done as a tail call. 13415 */ 13416 adrl lr, dvmAsmInstructionStart + (18 * 64) 13417 mov r0, rPC @ arg0 13418 mov r1, rSELF @ arg1 13419 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13420 13421/* ------------------------------ */ 13422 .balign 64 13423.L_ALT_OP_CONST_16: /* 0x13 */ 13424/* File: armv5te/ALT_STUB.S */ 13425/* 13426 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13427 * any interesting requests and then jump to the real instruction 13428 * handler. Note that the call to dvmCheckInst is done as a tail call. 13429 */ 13430 adrl lr, dvmAsmInstructionStart + (19 * 64) 13431 mov r0, rPC @ arg0 13432 mov r1, rSELF @ arg1 13433 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13434 13435/* ------------------------------ */ 13436 .balign 64 13437.L_ALT_OP_CONST: /* 0x14 */ 13438/* File: armv5te/ALT_STUB.S */ 13439/* 13440 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13441 * any interesting requests and then jump to the real instruction 13442 * handler. Note that the call to dvmCheckInst is done as a tail call. 13443 */ 13444 adrl lr, dvmAsmInstructionStart + (20 * 64) 13445 mov r0, rPC @ arg0 13446 mov r1, rSELF @ arg1 13447 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13448 13449/* ------------------------------ */ 13450 .balign 64 13451.L_ALT_OP_CONST_HIGH16: /* 0x15 */ 13452/* File: armv5te/ALT_STUB.S */ 13453/* 13454 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13455 * any interesting requests and then jump to the real instruction 13456 * handler. Note that the call to dvmCheckInst is done as a tail call. 13457 */ 13458 adrl lr, dvmAsmInstructionStart + (21 * 64) 13459 mov r0, rPC @ arg0 13460 mov r1, rSELF @ arg1 13461 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13462 13463/* ------------------------------ */ 13464 .balign 64 13465.L_ALT_OP_CONST_WIDE_16: /* 0x16 */ 13466/* File: armv5te/ALT_STUB.S */ 13467/* 13468 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13469 * any interesting requests and then jump to the real instruction 13470 * handler. Note that the call to dvmCheckInst is done as a tail call. 13471 */ 13472 adrl lr, dvmAsmInstructionStart + (22 * 64) 13473 mov r0, rPC @ arg0 13474 mov r1, rSELF @ arg1 13475 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13476 13477/* ------------------------------ */ 13478 .balign 64 13479.L_ALT_OP_CONST_WIDE_32: /* 0x17 */ 13480/* File: armv5te/ALT_STUB.S */ 13481/* 13482 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13483 * any interesting requests and then jump to the real instruction 13484 * handler. Note that the call to dvmCheckInst is done as a tail call. 13485 */ 13486 adrl lr, dvmAsmInstructionStart + (23 * 64) 13487 mov r0, rPC @ arg0 13488 mov r1, rSELF @ arg1 13489 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13490 13491/* ------------------------------ */ 13492 .balign 64 13493.L_ALT_OP_CONST_WIDE: /* 0x18 */ 13494/* File: armv5te/ALT_STUB.S */ 13495/* 13496 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13497 * any interesting requests and then jump to the real instruction 13498 * handler. Note that the call to dvmCheckInst is done as a tail call. 13499 */ 13500 adrl lr, dvmAsmInstructionStart + (24 * 64) 13501 mov r0, rPC @ arg0 13502 mov r1, rSELF @ arg1 13503 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13504 13505/* ------------------------------ */ 13506 .balign 64 13507.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */ 13508/* File: armv5te/ALT_STUB.S */ 13509/* 13510 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13511 * any interesting requests and then jump to the real instruction 13512 * handler. Note that the call to dvmCheckInst is done as a tail call. 13513 */ 13514 adrl lr, dvmAsmInstructionStart + (25 * 64) 13515 mov r0, rPC @ arg0 13516 mov r1, rSELF @ arg1 13517 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13518 13519/* ------------------------------ */ 13520 .balign 64 13521.L_ALT_OP_CONST_STRING: /* 0x1a */ 13522/* File: armv5te/ALT_STUB.S */ 13523/* 13524 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13525 * any interesting requests and then jump to the real instruction 13526 * handler. Note that the call to dvmCheckInst is done as a tail call. 13527 */ 13528 adrl lr, dvmAsmInstructionStart + (26 * 64) 13529 mov r0, rPC @ arg0 13530 mov r1, rSELF @ arg1 13531 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13532 13533/* ------------------------------ */ 13534 .balign 64 13535.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */ 13536/* File: armv5te/ALT_STUB.S */ 13537/* 13538 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13539 * any interesting requests and then jump to the real instruction 13540 * handler. Note that the call to dvmCheckInst is done as a tail call. 13541 */ 13542 adrl lr, dvmAsmInstructionStart + (27 * 64) 13543 mov r0, rPC @ arg0 13544 mov r1, rSELF @ arg1 13545 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13546 13547/* ------------------------------ */ 13548 .balign 64 13549.L_ALT_OP_CONST_CLASS: /* 0x1c */ 13550/* File: armv5te/ALT_STUB.S */ 13551/* 13552 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13553 * any interesting requests and then jump to the real instruction 13554 * handler. Note that the call to dvmCheckInst is done as a tail call. 13555 */ 13556 adrl lr, dvmAsmInstructionStart + (28 * 64) 13557 mov r0, rPC @ arg0 13558 mov r1, rSELF @ arg1 13559 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13560 13561/* ------------------------------ */ 13562 .balign 64 13563.L_ALT_OP_MONITOR_ENTER: /* 0x1d */ 13564/* File: armv5te/ALT_STUB.S */ 13565/* 13566 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13567 * any interesting requests and then jump to the real instruction 13568 * handler. Note that the call to dvmCheckInst is done as a tail call. 13569 */ 13570 adrl lr, dvmAsmInstructionStart + (29 * 64) 13571 mov r0, rPC @ arg0 13572 mov r1, rSELF @ arg1 13573 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13574 13575/* ------------------------------ */ 13576 .balign 64 13577.L_ALT_OP_MONITOR_EXIT: /* 0x1e */ 13578/* File: armv5te/ALT_STUB.S */ 13579/* 13580 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13581 * any interesting requests and then jump to the real instruction 13582 * handler. Note that the call to dvmCheckInst is done as a tail call. 13583 */ 13584 adrl lr, dvmAsmInstructionStart + (30 * 64) 13585 mov r0, rPC @ arg0 13586 mov r1, rSELF @ arg1 13587 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13588 13589/* ------------------------------ */ 13590 .balign 64 13591.L_ALT_OP_CHECK_CAST: /* 0x1f */ 13592/* File: armv5te/ALT_STUB.S */ 13593/* 13594 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13595 * any interesting requests and then jump to the real instruction 13596 * handler. Note that the call to dvmCheckInst is done as a tail call. 13597 */ 13598 adrl lr, dvmAsmInstructionStart + (31 * 64) 13599 mov r0, rPC @ arg0 13600 mov r1, rSELF @ arg1 13601 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13602 13603/* ------------------------------ */ 13604 .balign 64 13605.L_ALT_OP_INSTANCE_OF: /* 0x20 */ 13606/* File: armv5te/ALT_STUB.S */ 13607/* 13608 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13609 * any interesting requests and then jump to the real instruction 13610 * handler. Note that the call to dvmCheckInst is done as a tail call. 13611 */ 13612 adrl lr, dvmAsmInstructionStart + (32 * 64) 13613 mov r0, rPC @ arg0 13614 mov r1, rSELF @ arg1 13615 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13616 13617/* ------------------------------ */ 13618 .balign 64 13619.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */ 13620/* File: armv5te/ALT_STUB.S */ 13621/* 13622 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13623 * any interesting requests and then jump to the real instruction 13624 * handler. Note that the call to dvmCheckInst is done as a tail call. 13625 */ 13626 adrl lr, dvmAsmInstructionStart + (33 * 64) 13627 mov r0, rPC @ arg0 13628 mov r1, rSELF @ arg1 13629 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13630 13631/* ------------------------------ */ 13632 .balign 64 13633.L_ALT_OP_NEW_INSTANCE: /* 0x22 */ 13634/* File: armv5te/ALT_STUB.S */ 13635/* 13636 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13637 * any interesting requests and then jump to the real instruction 13638 * handler. Note that the call to dvmCheckInst is done as a tail call. 13639 */ 13640 adrl lr, dvmAsmInstructionStart + (34 * 64) 13641 mov r0, rPC @ arg0 13642 mov r1, rSELF @ arg1 13643 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13644 13645/* ------------------------------ */ 13646 .balign 64 13647.L_ALT_OP_NEW_ARRAY: /* 0x23 */ 13648/* File: armv5te/ALT_STUB.S */ 13649/* 13650 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13651 * any interesting requests and then jump to the real instruction 13652 * handler. Note that the call to dvmCheckInst is done as a tail call. 13653 */ 13654 adrl lr, dvmAsmInstructionStart + (35 * 64) 13655 mov r0, rPC @ arg0 13656 mov r1, rSELF @ arg1 13657 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13658 13659/* ------------------------------ */ 13660 .balign 64 13661.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */ 13662/* File: armv5te/ALT_STUB.S */ 13663/* 13664 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13665 * any interesting requests and then jump to the real instruction 13666 * handler. Note that the call to dvmCheckInst is done as a tail call. 13667 */ 13668 adrl lr, dvmAsmInstructionStart + (36 * 64) 13669 mov r0, rPC @ arg0 13670 mov r1, rSELF @ arg1 13671 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13672 13673/* ------------------------------ */ 13674 .balign 64 13675.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 13676/* File: armv5te/ALT_STUB.S */ 13677/* 13678 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13679 * any interesting requests and then jump to the real instruction 13680 * handler. Note that the call to dvmCheckInst is done as a tail call. 13681 */ 13682 adrl lr, dvmAsmInstructionStart + (37 * 64) 13683 mov r0, rPC @ arg0 13684 mov r1, rSELF @ arg1 13685 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13686 13687/* ------------------------------ */ 13688 .balign 64 13689.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */ 13690/* File: armv5te/ALT_STUB.S */ 13691/* 13692 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13693 * any interesting requests and then jump to the real instruction 13694 * handler. Note that the call to dvmCheckInst is done as a tail call. 13695 */ 13696 adrl lr, dvmAsmInstructionStart + (38 * 64) 13697 mov r0, rPC @ arg0 13698 mov r1, rSELF @ arg1 13699 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13700 13701/* ------------------------------ */ 13702 .balign 64 13703.L_ALT_OP_THROW: /* 0x27 */ 13704/* File: armv5te/ALT_STUB.S */ 13705/* 13706 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13707 * any interesting requests and then jump to the real instruction 13708 * handler. Note that the call to dvmCheckInst is done as a tail call. 13709 */ 13710 adrl lr, dvmAsmInstructionStart + (39 * 64) 13711 mov r0, rPC @ arg0 13712 mov r1, rSELF @ arg1 13713 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13714 13715/* ------------------------------ */ 13716 .balign 64 13717.L_ALT_OP_GOTO: /* 0x28 */ 13718/* File: armv5te/ALT_STUB.S */ 13719/* 13720 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13721 * any interesting requests and then jump to the real instruction 13722 * handler. Note that the call to dvmCheckInst is done as a tail call. 13723 */ 13724 adrl lr, dvmAsmInstructionStart + (40 * 64) 13725 mov r0, rPC @ arg0 13726 mov r1, rSELF @ arg1 13727 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13728 13729/* ------------------------------ */ 13730 .balign 64 13731.L_ALT_OP_GOTO_16: /* 0x29 */ 13732/* File: armv5te/ALT_STUB.S */ 13733/* 13734 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13735 * any interesting requests and then jump to the real instruction 13736 * handler. Note that the call to dvmCheckInst is done as a tail call. 13737 */ 13738 adrl lr, dvmAsmInstructionStart + (41 * 64) 13739 mov r0, rPC @ arg0 13740 mov r1, rSELF @ arg1 13741 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13742 13743/* ------------------------------ */ 13744 .balign 64 13745.L_ALT_OP_GOTO_32: /* 0x2a */ 13746/* File: armv5te/ALT_STUB.S */ 13747/* 13748 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13749 * any interesting requests and then jump to the real instruction 13750 * handler. Note that the call to dvmCheckInst is done as a tail call. 13751 */ 13752 adrl lr, dvmAsmInstructionStart + (42 * 64) 13753 mov r0, rPC @ arg0 13754 mov r1, rSELF @ arg1 13755 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13756 13757/* ------------------------------ */ 13758 .balign 64 13759.L_ALT_OP_PACKED_SWITCH: /* 0x2b */ 13760/* File: armv5te/ALT_STUB.S */ 13761/* 13762 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13763 * any interesting requests and then jump to the real instruction 13764 * handler. Note that the call to dvmCheckInst is done as a tail call. 13765 */ 13766 adrl lr, dvmAsmInstructionStart + (43 * 64) 13767 mov r0, rPC @ arg0 13768 mov r1, rSELF @ arg1 13769 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13770 13771/* ------------------------------ */ 13772 .balign 64 13773.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */ 13774/* File: armv5te/ALT_STUB.S */ 13775/* 13776 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13777 * any interesting requests and then jump to the real instruction 13778 * handler. Note that the call to dvmCheckInst is done as a tail call. 13779 */ 13780 adrl lr, dvmAsmInstructionStart + (44 * 64) 13781 mov r0, rPC @ arg0 13782 mov r1, rSELF @ arg1 13783 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13784 13785/* ------------------------------ */ 13786 .balign 64 13787.L_ALT_OP_CMPL_FLOAT: /* 0x2d */ 13788/* File: armv5te/ALT_STUB.S */ 13789/* 13790 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13791 * any interesting requests and then jump to the real instruction 13792 * handler. Note that the call to dvmCheckInst is done as a tail call. 13793 */ 13794 adrl lr, dvmAsmInstructionStart + (45 * 64) 13795 mov r0, rPC @ arg0 13796 mov r1, rSELF @ arg1 13797 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13798 13799/* ------------------------------ */ 13800 .balign 64 13801.L_ALT_OP_CMPG_FLOAT: /* 0x2e */ 13802/* File: armv5te/ALT_STUB.S */ 13803/* 13804 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13805 * any interesting requests and then jump to the real instruction 13806 * handler. Note that the call to dvmCheckInst is done as a tail call. 13807 */ 13808 adrl lr, dvmAsmInstructionStart + (46 * 64) 13809 mov r0, rPC @ arg0 13810 mov r1, rSELF @ arg1 13811 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13812 13813/* ------------------------------ */ 13814 .balign 64 13815.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */ 13816/* File: armv5te/ALT_STUB.S */ 13817/* 13818 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13819 * any interesting requests and then jump to the real instruction 13820 * handler. Note that the call to dvmCheckInst is done as a tail call. 13821 */ 13822 adrl lr, dvmAsmInstructionStart + (47 * 64) 13823 mov r0, rPC @ arg0 13824 mov r1, rSELF @ arg1 13825 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13826 13827/* ------------------------------ */ 13828 .balign 64 13829.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */ 13830/* File: armv5te/ALT_STUB.S */ 13831/* 13832 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13833 * any interesting requests and then jump to the real instruction 13834 * handler. Note that the call to dvmCheckInst is done as a tail call. 13835 */ 13836 adrl lr, dvmAsmInstructionStart + (48 * 64) 13837 mov r0, rPC @ arg0 13838 mov r1, rSELF @ arg1 13839 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13840 13841/* ------------------------------ */ 13842 .balign 64 13843.L_ALT_OP_CMP_LONG: /* 0x31 */ 13844/* File: armv5te/ALT_STUB.S */ 13845/* 13846 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13847 * any interesting requests and then jump to the real instruction 13848 * handler. Note that the call to dvmCheckInst is done as a tail call. 13849 */ 13850 adrl lr, dvmAsmInstructionStart + (49 * 64) 13851 mov r0, rPC @ arg0 13852 mov r1, rSELF @ arg1 13853 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13854 13855/* ------------------------------ */ 13856 .balign 64 13857.L_ALT_OP_IF_EQ: /* 0x32 */ 13858/* File: armv5te/ALT_STUB.S */ 13859/* 13860 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13861 * any interesting requests and then jump to the real instruction 13862 * handler. Note that the call to dvmCheckInst is done as a tail call. 13863 */ 13864 adrl lr, dvmAsmInstructionStart + (50 * 64) 13865 mov r0, rPC @ arg0 13866 mov r1, rSELF @ arg1 13867 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13868 13869/* ------------------------------ */ 13870 .balign 64 13871.L_ALT_OP_IF_NE: /* 0x33 */ 13872/* File: armv5te/ALT_STUB.S */ 13873/* 13874 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13875 * any interesting requests and then jump to the real instruction 13876 * handler. Note that the call to dvmCheckInst is done as a tail call. 13877 */ 13878 adrl lr, dvmAsmInstructionStart + (51 * 64) 13879 mov r0, rPC @ arg0 13880 mov r1, rSELF @ arg1 13881 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13882 13883/* ------------------------------ */ 13884 .balign 64 13885.L_ALT_OP_IF_LT: /* 0x34 */ 13886/* File: armv5te/ALT_STUB.S */ 13887/* 13888 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13889 * any interesting requests and then jump to the real instruction 13890 * handler. Note that the call to dvmCheckInst is done as a tail call. 13891 */ 13892 adrl lr, dvmAsmInstructionStart + (52 * 64) 13893 mov r0, rPC @ arg0 13894 mov r1, rSELF @ arg1 13895 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13896 13897/* ------------------------------ */ 13898 .balign 64 13899.L_ALT_OP_IF_GE: /* 0x35 */ 13900/* File: armv5te/ALT_STUB.S */ 13901/* 13902 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13903 * any interesting requests and then jump to the real instruction 13904 * handler. Note that the call to dvmCheckInst is done as a tail call. 13905 */ 13906 adrl lr, dvmAsmInstructionStart + (53 * 64) 13907 mov r0, rPC @ arg0 13908 mov r1, rSELF @ arg1 13909 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13910 13911/* ------------------------------ */ 13912 .balign 64 13913.L_ALT_OP_IF_GT: /* 0x36 */ 13914/* File: armv5te/ALT_STUB.S */ 13915/* 13916 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13917 * any interesting requests and then jump to the real instruction 13918 * handler. Note that the call to dvmCheckInst is done as a tail call. 13919 */ 13920 adrl lr, dvmAsmInstructionStart + (54 * 64) 13921 mov r0, rPC @ arg0 13922 mov r1, rSELF @ arg1 13923 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13924 13925/* ------------------------------ */ 13926 .balign 64 13927.L_ALT_OP_IF_LE: /* 0x37 */ 13928/* File: armv5te/ALT_STUB.S */ 13929/* 13930 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13931 * any interesting requests and then jump to the real instruction 13932 * handler. Note that the call to dvmCheckInst is done as a tail call. 13933 */ 13934 adrl lr, dvmAsmInstructionStart + (55 * 64) 13935 mov r0, rPC @ arg0 13936 mov r1, rSELF @ arg1 13937 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13938 13939/* ------------------------------ */ 13940 .balign 64 13941.L_ALT_OP_IF_EQZ: /* 0x38 */ 13942/* File: armv5te/ALT_STUB.S */ 13943/* 13944 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13945 * any interesting requests and then jump to the real instruction 13946 * handler. Note that the call to dvmCheckInst is done as a tail call. 13947 */ 13948 adrl lr, dvmAsmInstructionStart + (56 * 64) 13949 mov r0, rPC @ arg0 13950 mov r1, rSELF @ arg1 13951 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13952 13953/* ------------------------------ */ 13954 .balign 64 13955.L_ALT_OP_IF_NEZ: /* 0x39 */ 13956/* File: armv5te/ALT_STUB.S */ 13957/* 13958 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13959 * any interesting requests and then jump to the real instruction 13960 * handler. Note that the call to dvmCheckInst is done as a tail call. 13961 */ 13962 adrl lr, dvmAsmInstructionStart + (57 * 64) 13963 mov r0, rPC @ arg0 13964 mov r1, rSELF @ arg1 13965 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13966 13967/* ------------------------------ */ 13968 .balign 64 13969.L_ALT_OP_IF_LTZ: /* 0x3a */ 13970/* File: armv5te/ALT_STUB.S */ 13971/* 13972 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13973 * any interesting requests and then jump to the real instruction 13974 * handler. Note that the call to dvmCheckInst is done as a tail call. 13975 */ 13976 adrl lr, dvmAsmInstructionStart + (58 * 64) 13977 mov r0, rPC @ arg0 13978 mov r1, rSELF @ arg1 13979 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13980 13981/* ------------------------------ */ 13982 .balign 64 13983.L_ALT_OP_IF_GEZ: /* 0x3b */ 13984/* File: armv5te/ALT_STUB.S */ 13985/* 13986 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13987 * any interesting requests and then jump to the real instruction 13988 * handler. Note that the call to dvmCheckInst is done as a tail call. 13989 */ 13990 adrl lr, dvmAsmInstructionStart + (59 * 64) 13991 mov r0, rPC @ arg0 13992 mov r1, rSELF @ arg1 13993 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13994 13995/* ------------------------------ */ 13996 .balign 64 13997.L_ALT_OP_IF_GTZ: /* 0x3c */ 13998/* File: armv5te/ALT_STUB.S */ 13999/* 14000 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14001 * any interesting requests and then jump to the real instruction 14002 * handler. Note that the call to dvmCheckInst is done as a tail call. 14003 */ 14004 adrl lr, dvmAsmInstructionStart + (60 * 64) 14005 mov r0, rPC @ arg0 14006 mov r1, rSELF @ arg1 14007 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14008 14009/* ------------------------------ */ 14010 .balign 64 14011.L_ALT_OP_IF_LEZ: /* 0x3d */ 14012/* File: armv5te/ALT_STUB.S */ 14013/* 14014 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14015 * any interesting requests and then jump to the real instruction 14016 * handler. Note that the call to dvmCheckInst is done as a tail call. 14017 */ 14018 adrl lr, dvmAsmInstructionStart + (61 * 64) 14019 mov r0, rPC @ arg0 14020 mov r1, rSELF @ arg1 14021 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14022 14023/* ------------------------------ */ 14024 .balign 64 14025.L_ALT_OP_UNUSED_3E: /* 0x3e */ 14026/* File: armv5te/ALT_STUB.S */ 14027/* 14028 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14029 * any interesting requests and then jump to the real instruction 14030 * handler. Note that the call to dvmCheckInst is done as a tail call. 14031 */ 14032 adrl lr, dvmAsmInstructionStart + (62 * 64) 14033 mov r0, rPC @ arg0 14034 mov r1, rSELF @ arg1 14035 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14036 14037/* ------------------------------ */ 14038 .balign 64 14039.L_ALT_OP_UNUSED_3F: /* 0x3f */ 14040/* File: armv5te/ALT_STUB.S */ 14041/* 14042 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14043 * any interesting requests and then jump to the real instruction 14044 * handler. Note that the call to dvmCheckInst is done as a tail call. 14045 */ 14046 adrl lr, dvmAsmInstructionStart + (63 * 64) 14047 mov r0, rPC @ arg0 14048 mov r1, rSELF @ arg1 14049 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14050 14051/* ------------------------------ */ 14052 .balign 64 14053.L_ALT_OP_UNUSED_40: /* 0x40 */ 14054/* File: armv5te/ALT_STUB.S */ 14055/* 14056 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14057 * any interesting requests and then jump to the real instruction 14058 * handler. Note that the call to dvmCheckInst is done as a tail call. 14059 */ 14060 adrl lr, dvmAsmInstructionStart + (64 * 64) 14061 mov r0, rPC @ arg0 14062 mov r1, rSELF @ arg1 14063 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14064 14065/* ------------------------------ */ 14066 .balign 64 14067.L_ALT_OP_UNUSED_41: /* 0x41 */ 14068/* File: armv5te/ALT_STUB.S */ 14069/* 14070 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14071 * any interesting requests and then jump to the real instruction 14072 * handler. Note that the call to dvmCheckInst is done as a tail call. 14073 */ 14074 adrl lr, dvmAsmInstructionStart + (65 * 64) 14075 mov r0, rPC @ arg0 14076 mov r1, rSELF @ arg1 14077 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14078 14079/* ------------------------------ */ 14080 .balign 64 14081.L_ALT_OP_UNUSED_42: /* 0x42 */ 14082/* File: armv5te/ALT_STUB.S */ 14083/* 14084 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14085 * any interesting requests and then jump to the real instruction 14086 * handler. Note that the call to dvmCheckInst is done as a tail call. 14087 */ 14088 adrl lr, dvmAsmInstructionStart + (66 * 64) 14089 mov r0, rPC @ arg0 14090 mov r1, rSELF @ arg1 14091 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14092 14093/* ------------------------------ */ 14094 .balign 64 14095.L_ALT_OP_UNUSED_43: /* 0x43 */ 14096/* File: armv5te/ALT_STUB.S */ 14097/* 14098 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14099 * any interesting requests and then jump to the real instruction 14100 * handler. Note that the call to dvmCheckInst is done as a tail call. 14101 */ 14102 adrl lr, dvmAsmInstructionStart + (67 * 64) 14103 mov r0, rPC @ arg0 14104 mov r1, rSELF @ arg1 14105 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14106 14107/* ------------------------------ */ 14108 .balign 64 14109.L_ALT_OP_AGET: /* 0x44 */ 14110/* File: armv5te/ALT_STUB.S */ 14111/* 14112 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14113 * any interesting requests and then jump to the real instruction 14114 * handler. Note that the call to dvmCheckInst is done as a tail call. 14115 */ 14116 adrl lr, dvmAsmInstructionStart + (68 * 64) 14117 mov r0, rPC @ arg0 14118 mov r1, rSELF @ arg1 14119 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14120 14121/* ------------------------------ */ 14122 .balign 64 14123.L_ALT_OP_AGET_WIDE: /* 0x45 */ 14124/* File: armv5te/ALT_STUB.S */ 14125/* 14126 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14127 * any interesting requests and then jump to the real instruction 14128 * handler. Note that the call to dvmCheckInst is done as a tail call. 14129 */ 14130 adrl lr, dvmAsmInstructionStart + (69 * 64) 14131 mov r0, rPC @ arg0 14132 mov r1, rSELF @ arg1 14133 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14134 14135/* ------------------------------ */ 14136 .balign 64 14137.L_ALT_OP_AGET_OBJECT: /* 0x46 */ 14138/* File: armv5te/ALT_STUB.S */ 14139/* 14140 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14141 * any interesting requests and then jump to the real instruction 14142 * handler. Note that the call to dvmCheckInst is done as a tail call. 14143 */ 14144 adrl lr, dvmAsmInstructionStart + (70 * 64) 14145 mov r0, rPC @ arg0 14146 mov r1, rSELF @ arg1 14147 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14148 14149/* ------------------------------ */ 14150 .balign 64 14151.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */ 14152/* File: armv5te/ALT_STUB.S */ 14153/* 14154 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14155 * any interesting requests and then jump to the real instruction 14156 * handler. Note that the call to dvmCheckInst is done as a tail call. 14157 */ 14158 adrl lr, dvmAsmInstructionStart + (71 * 64) 14159 mov r0, rPC @ arg0 14160 mov r1, rSELF @ arg1 14161 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14162 14163/* ------------------------------ */ 14164 .balign 64 14165.L_ALT_OP_AGET_BYTE: /* 0x48 */ 14166/* File: armv5te/ALT_STUB.S */ 14167/* 14168 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14169 * any interesting requests and then jump to the real instruction 14170 * handler. Note that the call to dvmCheckInst is done as a tail call. 14171 */ 14172 adrl lr, dvmAsmInstructionStart + (72 * 64) 14173 mov r0, rPC @ arg0 14174 mov r1, rSELF @ arg1 14175 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14176 14177/* ------------------------------ */ 14178 .balign 64 14179.L_ALT_OP_AGET_CHAR: /* 0x49 */ 14180/* File: armv5te/ALT_STUB.S */ 14181/* 14182 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14183 * any interesting requests and then jump to the real instruction 14184 * handler. Note that the call to dvmCheckInst is done as a tail call. 14185 */ 14186 adrl lr, dvmAsmInstructionStart + (73 * 64) 14187 mov r0, rPC @ arg0 14188 mov r1, rSELF @ arg1 14189 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14190 14191/* ------------------------------ */ 14192 .balign 64 14193.L_ALT_OP_AGET_SHORT: /* 0x4a */ 14194/* File: armv5te/ALT_STUB.S */ 14195/* 14196 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14197 * any interesting requests and then jump to the real instruction 14198 * handler. Note that the call to dvmCheckInst is done as a tail call. 14199 */ 14200 adrl lr, dvmAsmInstructionStart + (74 * 64) 14201 mov r0, rPC @ arg0 14202 mov r1, rSELF @ arg1 14203 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14204 14205/* ------------------------------ */ 14206 .balign 64 14207.L_ALT_OP_APUT: /* 0x4b */ 14208/* File: armv5te/ALT_STUB.S */ 14209/* 14210 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14211 * any interesting requests and then jump to the real instruction 14212 * handler. Note that the call to dvmCheckInst is done as a tail call. 14213 */ 14214 adrl lr, dvmAsmInstructionStart + (75 * 64) 14215 mov r0, rPC @ arg0 14216 mov r1, rSELF @ arg1 14217 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14218 14219/* ------------------------------ */ 14220 .balign 64 14221.L_ALT_OP_APUT_WIDE: /* 0x4c */ 14222/* File: armv5te/ALT_STUB.S */ 14223/* 14224 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14225 * any interesting requests and then jump to the real instruction 14226 * handler. Note that the call to dvmCheckInst is done as a tail call. 14227 */ 14228 adrl lr, dvmAsmInstructionStart + (76 * 64) 14229 mov r0, rPC @ arg0 14230 mov r1, rSELF @ arg1 14231 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14232 14233/* ------------------------------ */ 14234 .balign 64 14235.L_ALT_OP_APUT_OBJECT: /* 0x4d */ 14236/* File: armv5te/ALT_STUB.S */ 14237/* 14238 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14239 * any interesting requests and then jump to the real instruction 14240 * handler. Note that the call to dvmCheckInst is done as a tail call. 14241 */ 14242 adrl lr, dvmAsmInstructionStart + (77 * 64) 14243 mov r0, rPC @ arg0 14244 mov r1, rSELF @ arg1 14245 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14246 14247/* ------------------------------ */ 14248 .balign 64 14249.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */ 14250/* File: armv5te/ALT_STUB.S */ 14251/* 14252 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14253 * any interesting requests and then jump to the real instruction 14254 * handler. Note that the call to dvmCheckInst is done as a tail call. 14255 */ 14256 adrl lr, dvmAsmInstructionStart + (78 * 64) 14257 mov r0, rPC @ arg0 14258 mov r1, rSELF @ arg1 14259 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14260 14261/* ------------------------------ */ 14262 .balign 64 14263.L_ALT_OP_APUT_BYTE: /* 0x4f */ 14264/* File: armv5te/ALT_STUB.S */ 14265/* 14266 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14267 * any interesting requests and then jump to the real instruction 14268 * handler. Note that the call to dvmCheckInst is done as a tail call. 14269 */ 14270 adrl lr, dvmAsmInstructionStart + (79 * 64) 14271 mov r0, rPC @ arg0 14272 mov r1, rSELF @ arg1 14273 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14274 14275/* ------------------------------ */ 14276 .balign 64 14277.L_ALT_OP_APUT_CHAR: /* 0x50 */ 14278/* File: armv5te/ALT_STUB.S */ 14279/* 14280 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14281 * any interesting requests and then jump to the real instruction 14282 * handler. Note that the call to dvmCheckInst is done as a tail call. 14283 */ 14284 adrl lr, dvmAsmInstructionStart + (80 * 64) 14285 mov r0, rPC @ arg0 14286 mov r1, rSELF @ arg1 14287 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14288 14289/* ------------------------------ */ 14290 .balign 64 14291.L_ALT_OP_APUT_SHORT: /* 0x51 */ 14292/* File: armv5te/ALT_STUB.S */ 14293/* 14294 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14295 * any interesting requests and then jump to the real instruction 14296 * handler. Note that the call to dvmCheckInst is done as a tail call. 14297 */ 14298 adrl lr, dvmAsmInstructionStart + (81 * 64) 14299 mov r0, rPC @ arg0 14300 mov r1, rSELF @ arg1 14301 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14302 14303/* ------------------------------ */ 14304 .balign 64 14305.L_ALT_OP_IGET: /* 0x52 */ 14306/* File: armv5te/ALT_STUB.S */ 14307/* 14308 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14309 * any interesting requests and then jump to the real instruction 14310 * handler. Note that the call to dvmCheckInst is done as a tail call. 14311 */ 14312 adrl lr, dvmAsmInstructionStart + (82 * 64) 14313 mov r0, rPC @ arg0 14314 mov r1, rSELF @ arg1 14315 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14316 14317/* ------------------------------ */ 14318 .balign 64 14319.L_ALT_OP_IGET_WIDE: /* 0x53 */ 14320/* File: armv5te/ALT_STUB.S */ 14321/* 14322 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14323 * any interesting requests and then jump to the real instruction 14324 * handler. Note that the call to dvmCheckInst is done as a tail call. 14325 */ 14326 adrl lr, dvmAsmInstructionStart + (83 * 64) 14327 mov r0, rPC @ arg0 14328 mov r1, rSELF @ arg1 14329 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14330 14331/* ------------------------------ */ 14332 .balign 64 14333.L_ALT_OP_IGET_OBJECT: /* 0x54 */ 14334/* File: armv5te/ALT_STUB.S */ 14335/* 14336 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14337 * any interesting requests and then jump to the real instruction 14338 * handler. Note that the call to dvmCheckInst is done as a tail call. 14339 */ 14340 adrl lr, dvmAsmInstructionStart + (84 * 64) 14341 mov r0, rPC @ arg0 14342 mov r1, rSELF @ arg1 14343 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14344 14345/* ------------------------------ */ 14346 .balign 64 14347.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */ 14348/* File: armv5te/ALT_STUB.S */ 14349/* 14350 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14351 * any interesting requests and then jump to the real instruction 14352 * handler. Note that the call to dvmCheckInst is done as a tail call. 14353 */ 14354 adrl lr, dvmAsmInstructionStart + (85 * 64) 14355 mov r0, rPC @ arg0 14356 mov r1, rSELF @ arg1 14357 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14358 14359/* ------------------------------ */ 14360 .balign 64 14361.L_ALT_OP_IGET_BYTE: /* 0x56 */ 14362/* File: armv5te/ALT_STUB.S */ 14363/* 14364 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14365 * any interesting requests and then jump to the real instruction 14366 * handler. Note that the call to dvmCheckInst is done as a tail call. 14367 */ 14368 adrl lr, dvmAsmInstructionStart + (86 * 64) 14369 mov r0, rPC @ arg0 14370 mov r1, rSELF @ arg1 14371 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14372 14373/* ------------------------------ */ 14374 .balign 64 14375.L_ALT_OP_IGET_CHAR: /* 0x57 */ 14376/* File: armv5te/ALT_STUB.S */ 14377/* 14378 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14379 * any interesting requests and then jump to the real instruction 14380 * handler. Note that the call to dvmCheckInst is done as a tail call. 14381 */ 14382 adrl lr, dvmAsmInstructionStart + (87 * 64) 14383 mov r0, rPC @ arg0 14384 mov r1, rSELF @ arg1 14385 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14386 14387/* ------------------------------ */ 14388 .balign 64 14389.L_ALT_OP_IGET_SHORT: /* 0x58 */ 14390/* File: armv5te/ALT_STUB.S */ 14391/* 14392 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14393 * any interesting requests and then jump to the real instruction 14394 * handler. Note that the call to dvmCheckInst is done as a tail call. 14395 */ 14396 adrl lr, dvmAsmInstructionStart + (88 * 64) 14397 mov r0, rPC @ arg0 14398 mov r1, rSELF @ arg1 14399 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14400 14401/* ------------------------------ */ 14402 .balign 64 14403.L_ALT_OP_IPUT: /* 0x59 */ 14404/* File: armv5te/ALT_STUB.S */ 14405/* 14406 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14407 * any interesting requests and then jump to the real instruction 14408 * handler. Note that the call to dvmCheckInst is done as a tail call. 14409 */ 14410 adrl lr, dvmAsmInstructionStart + (89 * 64) 14411 mov r0, rPC @ arg0 14412 mov r1, rSELF @ arg1 14413 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14414 14415/* ------------------------------ */ 14416 .balign 64 14417.L_ALT_OP_IPUT_WIDE: /* 0x5a */ 14418/* File: armv5te/ALT_STUB.S */ 14419/* 14420 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14421 * any interesting requests and then jump to the real instruction 14422 * handler. Note that the call to dvmCheckInst is done as a tail call. 14423 */ 14424 adrl lr, dvmAsmInstructionStart + (90 * 64) 14425 mov r0, rPC @ arg0 14426 mov r1, rSELF @ arg1 14427 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14428 14429/* ------------------------------ */ 14430 .balign 64 14431.L_ALT_OP_IPUT_OBJECT: /* 0x5b */ 14432/* File: armv5te/ALT_STUB.S */ 14433/* 14434 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14435 * any interesting requests and then jump to the real instruction 14436 * handler. Note that the call to dvmCheckInst is done as a tail call. 14437 */ 14438 adrl lr, dvmAsmInstructionStart + (91 * 64) 14439 mov r0, rPC @ arg0 14440 mov r1, rSELF @ arg1 14441 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14442 14443/* ------------------------------ */ 14444 .balign 64 14445.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */ 14446/* File: armv5te/ALT_STUB.S */ 14447/* 14448 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14449 * any interesting requests and then jump to the real instruction 14450 * handler. Note that the call to dvmCheckInst is done as a tail call. 14451 */ 14452 adrl lr, dvmAsmInstructionStart + (92 * 64) 14453 mov r0, rPC @ arg0 14454 mov r1, rSELF @ arg1 14455 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14456 14457/* ------------------------------ */ 14458 .balign 64 14459.L_ALT_OP_IPUT_BYTE: /* 0x5d */ 14460/* File: armv5te/ALT_STUB.S */ 14461/* 14462 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14463 * any interesting requests and then jump to the real instruction 14464 * handler. Note that the call to dvmCheckInst is done as a tail call. 14465 */ 14466 adrl lr, dvmAsmInstructionStart + (93 * 64) 14467 mov r0, rPC @ arg0 14468 mov r1, rSELF @ arg1 14469 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14470 14471/* ------------------------------ */ 14472 .balign 64 14473.L_ALT_OP_IPUT_CHAR: /* 0x5e */ 14474/* File: armv5te/ALT_STUB.S */ 14475/* 14476 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14477 * any interesting requests and then jump to the real instruction 14478 * handler. Note that the call to dvmCheckInst is done as a tail call. 14479 */ 14480 adrl lr, dvmAsmInstructionStart + (94 * 64) 14481 mov r0, rPC @ arg0 14482 mov r1, rSELF @ arg1 14483 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14484 14485/* ------------------------------ */ 14486 .balign 64 14487.L_ALT_OP_IPUT_SHORT: /* 0x5f */ 14488/* File: armv5te/ALT_STUB.S */ 14489/* 14490 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14491 * any interesting requests and then jump to the real instruction 14492 * handler. Note that the call to dvmCheckInst is done as a tail call. 14493 */ 14494 adrl lr, dvmAsmInstructionStart + (95 * 64) 14495 mov r0, rPC @ arg0 14496 mov r1, rSELF @ arg1 14497 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14498 14499/* ------------------------------ */ 14500 .balign 64 14501.L_ALT_OP_SGET: /* 0x60 */ 14502/* File: armv5te/ALT_STUB.S */ 14503/* 14504 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14505 * any interesting requests and then jump to the real instruction 14506 * handler. Note that the call to dvmCheckInst is done as a tail call. 14507 */ 14508 adrl lr, dvmAsmInstructionStart + (96 * 64) 14509 mov r0, rPC @ arg0 14510 mov r1, rSELF @ arg1 14511 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14512 14513/* ------------------------------ */ 14514 .balign 64 14515.L_ALT_OP_SGET_WIDE: /* 0x61 */ 14516/* File: armv5te/ALT_STUB.S */ 14517/* 14518 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14519 * any interesting requests and then jump to the real instruction 14520 * handler. Note that the call to dvmCheckInst is done as a tail call. 14521 */ 14522 adrl lr, dvmAsmInstructionStart + (97 * 64) 14523 mov r0, rPC @ arg0 14524 mov r1, rSELF @ arg1 14525 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14526 14527/* ------------------------------ */ 14528 .balign 64 14529.L_ALT_OP_SGET_OBJECT: /* 0x62 */ 14530/* File: armv5te/ALT_STUB.S */ 14531/* 14532 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14533 * any interesting requests and then jump to the real instruction 14534 * handler. Note that the call to dvmCheckInst is done as a tail call. 14535 */ 14536 adrl lr, dvmAsmInstructionStart + (98 * 64) 14537 mov r0, rPC @ arg0 14538 mov r1, rSELF @ arg1 14539 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14540 14541/* ------------------------------ */ 14542 .balign 64 14543.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */ 14544/* File: armv5te/ALT_STUB.S */ 14545/* 14546 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14547 * any interesting requests and then jump to the real instruction 14548 * handler. Note that the call to dvmCheckInst is done as a tail call. 14549 */ 14550 adrl lr, dvmAsmInstructionStart + (99 * 64) 14551 mov r0, rPC @ arg0 14552 mov r1, rSELF @ arg1 14553 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14554 14555/* ------------------------------ */ 14556 .balign 64 14557.L_ALT_OP_SGET_BYTE: /* 0x64 */ 14558/* File: armv5te/ALT_STUB.S */ 14559/* 14560 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14561 * any interesting requests and then jump to the real instruction 14562 * handler. Note that the call to dvmCheckInst is done as a tail call. 14563 */ 14564 adrl lr, dvmAsmInstructionStart + (100 * 64) 14565 mov r0, rPC @ arg0 14566 mov r1, rSELF @ arg1 14567 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14568 14569/* ------------------------------ */ 14570 .balign 64 14571.L_ALT_OP_SGET_CHAR: /* 0x65 */ 14572/* File: armv5te/ALT_STUB.S */ 14573/* 14574 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14575 * any interesting requests and then jump to the real instruction 14576 * handler. Note that the call to dvmCheckInst is done as a tail call. 14577 */ 14578 adrl lr, dvmAsmInstructionStart + (101 * 64) 14579 mov r0, rPC @ arg0 14580 mov r1, rSELF @ arg1 14581 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14582 14583/* ------------------------------ */ 14584 .balign 64 14585.L_ALT_OP_SGET_SHORT: /* 0x66 */ 14586/* File: armv5te/ALT_STUB.S */ 14587/* 14588 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14589 * any interesting requests and then jump to the real instruction 14590 * handler. Note that the call to dvmCheckInst is done as a tail call. 14591 */ 14592 adrl lr, dvmAsmInstructionStart + (102 * 64) 14593 mov r0, rPC @ arg0 14594 mov r1, rSELF @ arg1 14595 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14596 14597/* ------------------------------ */ 14598 .balign 64 14599.L_ALT_OP_SPUT: /* 0x67 */ 14600/* File: armv5te/ALT_STUB.S */ 14601/* 14602 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14603 * any interesting requests and then jump to the real instruction 14604 * handler. Note that the call to dvmCheckInst is done as a tail call. 14605 */ 14606 adrl lr, dvmAsmInstructionStart + (103 * 64) 14607 mov r0, rPC @ arg0 14608 mov r1, rSELF @ arg1 14609 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14610 14611/* ------------------------------ */ 14612 .balign 64 14613.L_ALT_OP_SPUT_WIDE: /* 0x68 */ 14614/* File: armv5te/ALT_STUB.S */ 14615/* 14616 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14617 * any interesting requests and then jump to the real instruction 14618 * handler. Note that the call to dvmCheckInst is done as a tail call. 14619 */ 14620 adrl lr, dvmAsmInstructionStart + (104 * 64) 14621 mov r0, rPC @ arg0 14622 mov r1, rSELF @ arg1 14623 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14624 14625/* ------------------------------ */ 14626 .balign 64 14627.L_ALT_OP_SPUT_OBJECT: /* 0x69 */ 14628/* File: armv5te/ALT_STUB.S */ 14629/* 14630 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14631 * any interesting requests and then jump to the real instruction 14632 * handler. Note that the call to dvmCheckInst is done as a tail call. 14633 */ 14634 adrl lr, dvmAsmInstructionStart + (105 * 64) 14635 mov r0, rPC @ arg0 14636 mov r1, rSELF @ arg1 14637 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14638 14639/* ------------------------------ */ 14640 .balign 64 14641.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */ 14642/* File: armv5te/ALT_STUB.S */ 14643/* 14644 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14645 * any interesting requests and then jump to the real instruction 14646 * handler. Note that the call to dvmCheckInst is done as a tail call. 14647 */ 14648 adrl lr, dvmAsmInstructionStart + (106 * 64) 14649 mov r0, rPC @ arg0 14650 mov r1, rSELF @ arg1 14651 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14652 14653/* ------------------------------ */ 14654 .balign 64 14655.L_ALT_OP_SPUT_BYTE: /* 0x6b */ 14656/* File: armv5te/ALT_STUB.S */ 14657/* 14658 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14659 * any interesting requests and then jump to the real instruction 14660 * handler. Note that the call to dvmCheckInst is done as a tail call. 14661 */ 14662 adrl lr, dvmAsmInstructionStart + (107 * 64) 14663 mov r0, rPC @ arg0 14664 mov r1, rSELF @ arg1 14665 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14666 14667/* ------------------------------ */ 14668 .balign 64 14669.L_ALT_OP_SPUT_CHAR: /* 0x6c */ 14670/* File: armv5te/ALT_STUB.S */ 14671/* 14672 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14673 * any interesting requests and then jump to the real instruction 14674 * handler. Note that the call to dvmCheckInst is done as a tail call. 14675 */ 14676 adrl lr, dvmAsmInstructionStart + (108 * 64) 14677 mov r0, rPC @ arg0 14678 mov r1, rSELF @ arg1 14679 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14680 14681/* ------------------------------ */ 14682 .balign 64 14683.L_ALT_OP_SPUT_SHORT: /* 0x6d */ 14684/* File: armv5te/ALT_STUB.S */ 14685/* 14686 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14687 * any interesting requests and then jump to the real instruction 14688 * handler. Note that the call to dvmCheckInst is done as a tail call. 14689 */ 14690 adrl lr, dvmAsmInstructionStart + (109 * 64) 14691 mov r0, rPC @ arg0 14692 mov r1, rSELF @ arg1 14693 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14694 14695/* ------------------------------ */ 14696 .balign 64 14697.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */ 14698/* File: armv5te/ALT_STUB.S */ 14699/* 14700 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14701 * any interesting requests and then jump to the real instruction 14702 * handler. Note that the call to dvmCheckInst is done as a tail call. 14703 */ 14704 adrl lr, dvmAsmInstructionStart + (110 * 64) 14705 mov r0, rPC @ arg0 14706 mov r1, rSELF @ arg1 14707 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14708 14709/* ------------------------------ */ 14710 .balign 64 14711.L_ALT_OP_INVOKE_SUPER: /* 0x6f */ 14712/* File: armv5te/ALT_STUB.S */ 14713/* 14714 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14715 * any interesting requests and then jump to the real instruction 14716 * handler. Note that the call to dvmCheckInst is done as a tail call. 14717 */ 14718 adrl lr, dvmAsmInstructionStart + (111 * 64) 14719 mov r0, rPC @ arg0 14720 mov r1, rSELF @ arg1 14721 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14722 14723/* ------------------------------ */ 14724 .balign 64 14725.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */ 14726/* File: armv5te/ALT_STUB.S */ 14727/* 14728 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14729 * any interesting requests and then jump to the real instruction 14730 * handler. Note that the call to dvmCheckInst is done as a tail call. 14731 */ 14732 adrl lr, dvmAsmInstructionStart + (112 * 64) 14733 mov r0, rPC @ arg0 14734 mov r1, rSELF @ arg1 14735 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14736 14737/* ------------------------------ */ 14738 .balign 64 14739.L_ALT_OP_INVOKE_STATIC: /* 0x71 */ 14740/* File: armv5te/ALT_STUB.S */ 14741/* 14742 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14743 * any interesting requests and then jump to the real instruction 14744 * handler. Note that the call to dvmCheckInst is done as a tail call. 14745 */ 14746 adrl lr, dvmAsmInstructionStart + (113 * 64) 14747 mov r0, rPC @ arg0 14748 mov r1, rSELF @ arg1 14749 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14750 14751/* ------------------------------ */ 14752 .balign 64 14753.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */ 14754/* File: armv5te/ALT_STUB.S */ 14755/* 14756 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14757 * any interesting requests and then jump to the real instruction 14758 * handler. Note that the call to dvmCheckInst is done as a tail call. 14759 */ 14760 adrl lr, dvmAsmInstructionStart + (114 * 64) 14761 mov r0, rPC @ arg0 14762 mov r1, rSELF @ arg1 14763 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14764 14765/* ------------------------------ */ 14766 .balign 64 14767.L_ALT_OP_UNUSED_73: /* 0x73 */ 14768/* File: armv5te/ALT_STUB.S */ 14769/* 14770 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14771 * any interesting requests and then jump to the real instruction 14772 * handler. Note that the call to dvmCheckInst is done as a tail call. 14773 */ 14774 adrl lr, dvmAsmInstructionStart + (115 * 64) 14775 mov r0, rPC @ arg0 14776 mov r1, rSELF @ arg1 14777 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14778 14779/* ------------------------------ */ 14780 .balign 64 14781.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 14782/* File: armv5te/ALT_STUB.S */ 14783/* 14784 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14785 * any interesting requests and then jump to the real instruction 14786 * handler. Note that the call to dvmCheckInst is done as a tail call. 14787 */ 14788 adrl lr, dvmAsmInstructionStart + (116 * 64) 14789 mov r0, rPC @ arg0 14790 mov r1, rSELF @ arg1 14791 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14792 14793/* ------------------------------ */ 14794 .balign 64 14795.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 14796/* File: armv5te/ALT_STUB.S */ 14797/* 14798 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14799 * any interesting requests and then jump to the real instruction 14800 * handler. Note that the call to dvmCheckInst is done as a tail call. 14801 */ 14802 adrl lr, dvmAsmInstructionStart + (117 * 64) 14803 mov r0, rPC @ arg0 14804 mov r1, rSELF @ arg1 14805 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14806 14807/* ------------------------------ */ 14808 .balign 64 14809.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 14810/* File: armv5te/ALT_STUB.S */ 14811/* 14812 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14813 * any interesting requests and then jump to the real instruction 14814 * handler. Note that the call to dvmCheckInst is done as a tail call. 14815 */ 14816 adrl lr, dvmAsmInstructionStart + (118 * 64) 14817 mov r0, rPC @ arg0 14818 mov r1, rSELF @ arg1 14819 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14820 14821/* ------------------------------ */ 14822 .balign 64 14823.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 14824/* File: armv5te/ALT_STUB.S */ 14825/* 14826 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14827 * any interesting requests and then jump to the real instruction 14828 * handler. Note that the call to dvmCheckInst is done as a tail call. 14829 */ 14830 adrl lr, dvmAsmInstructionStart + (119 * 64) 14831 mov r0, rPC @ arg0 14832 mov r1, rSELF @ arg1 14833 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14834 14835/* ------------------------------ */ 14836 .balign 64 14837.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 14838/* File: armv5te/ALT_STUB.S */ 14839/* 14840 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14841 * any interesting requests and then jump to the real instruction 14842 * handler. Note that the call to dvmCheckInst is done as a tail call. 14843 */ 14844 adrl lr, dvmAsmInstructionStart + (120 * 64) 14845 mov r0, rPC @ arg0 14846 mov r1, rSELF @ arg1 14847 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14848 14849/* ------------------------------ */ 14850 .balign 64 14851.L_ALT_OP_UNUSED_79: /* 0x79 */ 14852/* File: armv5te/ALT_STUB.S */ 14853/* 14854 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14855 * any interesting requests and then jump to the real instruction 14856 * handler. Note that the call to dvmCheckInst is done as a tail call. 14857 */ 14858 adrl lr, dvmAsmInstructionStart + (121 * 64) 14859 mov r0, rPC @ arg0 14860 mov r1, rSELF @ arg1 14861 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14862 14863/* ------------------------------ */ 14864 .balign 64 14865.L_ALT_OP_UNUSED_7A: /* 0x7a */ 14866/* File: armv5te/ALT_STUB.S */ 14867/* 14868 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14869 * any interesting requests and then jump to the real instruction 14870 * handler. Note that the call to dvmCheckInst is done as a tail call. 14871 */ 14872 adrl lr, dvmAsmInstructionStart + (122 * 64) 14873 mov r0, rPC @ arg0 14874 mov r1, rSELF @ arg1 14875 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14876 14877/* ------------------------------ */ 14878 .balign 64 14879.L_ALT_OP_NEG_INT: /* 0x7b */ 14880/* File: armv5te/ALT_STUB.S */ 14881/* 14882 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14883 * any interesting requests and then jump to the real instruction 14884 * handler. Note that the call to dvmCheckInst is done as a tail call. 14885 */ 14886 adrl lr, dvmAsmInstructionStart + (123 * 64) 14887 mov r0, rPC @ arg0 14888 mov r1, rSELF @ arg1 14889 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14890 14891/* ------------------------------ */ 14892 .balign 64 14893.L_ALT_OP_NOT_INT: /* 0x7c */ 14894/* File: armv5te/ALT_STUB.S */ 14895/* 14896 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14897 * any interesting requests and then jump to the real instruction 14898 * handler. Note that the call to dvmCheckInst is done as a tail call. 14899 */ 14900 adrl lr, dvmAsmInstructionStart + (124 * 64) 14901 mov r0, rPC @ arg0 14902 mov r1, rSELF @ arg1 14903 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14904 14905/* ------------------------------ */ 14906 .balign 64 14907.L_ALT_OP_NEG_LONG: /* 0x7d */ 14908/* File: armv5te/ALT_STUB.S */ 14909/* 14910 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14911 * any interesting requests and then jump to the real instruction 14912 * handler. Note that the call to dvmCheckInst is done as a tail call. 14913 */ 14914 adrl lr, dvmAsmInstructionStart + (125 * 64) 14915 mov r0, rPC @ arg0 14916 mov r1, rSELF @ arg1 14917 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14918 14919/* ------------------------------ */ 14920 .balign 64 14921.L_ALT_OP_NOT_LONG: /* 0x7e */ 14922/* File: armv5te/ALT_STUB.S */ 14923/* 14924 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14925 * any interesting requests and then jump to the real instruction 14926 * handler. Note that the call to dvmCheckInst is done as a tail call. 14927 */ 14928 adrl lr, dvmAsmInstructionStart + (126 * 64) 14929 mov r0, rPC @ arg0 14930 mov r1, rSELF @ arg1 14931 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14932 14933/* ------------------------------ */ 14934 .balign 64 14935.L_ALT_OP_NEG_FLOAT: /* 0x7f */ 14936/* File: armv5te/ALT_STUB.S */ 14937/* 14938 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14939 * any interesting requests and then jump to the real instruction 14940 * handler. Note that the call to dvmCheckInst is done as a tail call. 14941 */ 14942 adrl lr, dvmAsmInstructionStart + (127 * 64) 14943 mov r0, rPC @ arg0 14944 mov r1, rSELF @ arg1 14945 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14946 14947/* ------------------------------ */ 14948 .balign 64 14949.L_ALT_OP_NEG_DOUBLE: /* 0x80 */ 14950/* File: armv5te/ALT_STUB.S */ 14951/* 14952 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14953 * any interesting requests and then jump to the real instruction 14954 * handler. Note that the call to dvmCheckInst is done as a tail call. 14955 */ 14956 adrl lr, dvmAsmInstructionStart + (128 * 64) 14957 mov r0, rPC @ arg0 14958 mov r1, rSELF @ arg1 14959 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14960 14961/* ------------------------------ */ 14962 .balign 64 14963.L_ALT_OP_INT_TO_LONG: /* 0x81 */ 14964/* File: armv5te/ALT_STUB.S */ 14965/* 14966 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14967 * any interesting requests and then jump to the real instruction 14968 * handler. Note that the call to dvmCheckInst is done as a tail call. 14969 */ 14970 adrl lr, dvmAsmInstructionStart + (129 * 64) 14971 mov r0, rPC @ arg0 14972 mov r1, rSELF @ arg1 14973 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14974 14975/* ------------------------------ */ 14976 .balign 64 14977.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */ 14978/* File: armv5te/ALT_STUB.S */ 14979/* 14980 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14981 * any interesting requests and then jump to the real instruction 14982 * handler. Note that the call to dvmCheckInst is done as a tail call. 14983 */ 14984 adrl lr, dvmAsmInstructionStart + (130 * 64) 14985 mov r0, rPC @ arg0 14986 mov r1, rSELF @ arg1 14987 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14988 14989/* ------------------------------ */ 14990 .balign 64 14991.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */ 14992/* File: armv5te/ALT_STUB.S */ 14993/* 14994 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14995 * any interesting requests and then jump to the real instruction 14996 * handler. Note that the call to dvmCheckInst is done as a tail call. 14997 */ 14998 adrl lr, dvmAsmInstructionStart + (131 * 64) 14999 mov r0, rPC @ arg0 15000 mov r1, rSELF @ arg1 15001 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15002 15003/* ------------------------------ */ 15004 .balign 64 15005.L_ALT_OP_LONG_TO_INT: /* 0x84 */ 15006/* File: armv5te/ALT_STUB.S */ 15007/* 15008 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15009 * any interesting requests and then jump to the real instruction 15010 * handler. Note that the call to dvmCheckInst is done as a tail call. 15011 */ 15012 adrl lr, dvmAsmInstructionStart + (132 * 64) 15013 mov r0, rPC @ arg0 15014 mov r1, rSELF @ arg1 15015 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15016 15017/* ------------------------------ */ 15018 .balign 64 15019.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */ 15020/* File: armv5te/ALT_STUB.S */ 15021/* 15022 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15023 * any interesting requests and then jump to the real instruction 15024 * handler. Note that the call to dvmCheckInst is done as a tail call. 15025 */ 15026 adrl lr, dvmAsmInstructionStart + (133 * 64) 15027 mov r0, rPC @ arg0 15028 mov r1, rSELF @ arg1 15029 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15030 15031/* ------------------------------ */ 15032 .balign 64 15033.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */ 15034/* File: armv5te/ALT_STUB.S */ 15035/* 15036 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15037 * any interesting requests and then jump to the real instruction 15038 * handler. Note that the call to dvmCheckInst is done as a tail call. 15039 */ 15040 adrl lr, dvmAsmInstructionStart + (134 * 64) 15041 mov r0, rPC @ arg0 15042 mov r1, rSELF @ arg1 15043 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15044 15045/* ------------------------------ */ 15046 .balign 64 15047.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */ 15048/* File: armv5te/ALT_STUB.S */ 15049/* 15050 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15051 * any interesting requests and then jump to the real instruction 15052 * handler. Note that the call to dvmCheckInst is done as a tail call. 15053 */ 15054 adrl lr, dvmAsmInstructionStart + (135 * 64) 15055 mov r0, rPC @ arg0 15056 mov r1, rSELF @ arg1 15057 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15058 15059/* ------------------------------ */ 15060 .balign 64 15061.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */ 15062/* File: armv5te/ALT_STUB.S */ 15063/* 15064 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15065 * any interesting requests and then jump to the real instruction 15066 * handler. Note that the call to dvmCheckInst is done as a tail call. 15067 */ 15068 adrl lr, dvmAsmInstructionStart + (136 * 64) 15069 mov r0, rPC @ arg0 15070 mov r1, rSELF @ arg1 15071 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15072 15073/* ------------------------------ */ 15074 .balign 64 15075.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 15076/* File: armv5te/ALT_STUB.S */ 15077/* 15078 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15079 * any interesting requests and then jump to the real instruction 15080 * handler. Note that the call to dvmCheckInst is done as a tail call. 15081 */ 15082 adrl lr, dvmAsmInstructionStart + (137 * 64) 15083 mov r0, rPC @ arg0 15084 mov r1, rSELF @ arg1 15085 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15086 15087/* ------------------------------ */ 15088 .balign 64 15089.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */ 15090/* File: armv5te/ALT_STUB.S */ 15091/* 15092 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15093 * any interesting requests and then jump to the real instruction 15094 * handler. Note that the call to dvmCheckInst is done as a tail call. 15095 */ 15096 adrl lr, dvmAsmInstructionStart + (138 * 64) 15097 mov r0, rPC @ arg0 15098 mov r1, rSELF @ arg1 15099 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15100 15101/* ------------------------------ */ 15102 .balign 64 15103.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */ 15104/* File: armv5te/ALT_STUB.S */ 15105/* 15106 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15107 * any interesting requests and then jump to the real instruction 15108 * handler. Note that the call to dvmCheckInst is done as a tail call. 15109 */ 15110 adrl lr, dvmAsmInstructionStart + (139 * 64) 15111 mov r0, rPC @ arg0 15112 mov r1, rSELF @ arg1 15113 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15114 15115/* ------------------------------ */ 15116 .balign 64 15117.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 15118/* File: armv5te/ALT_STUB.S */ 15119/* 15120 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15121 * any interesting requests and then jump to the real instruction 15122 * handler. Note that the call to dvmCheckInst is done as a tail call. 15123 */ 15124 adrl lr, dvmAsmInstructionStart + (140 * 64) 15125 mov r0, rPC @ arg0 15126 mov r1, rSELF @ arg1 15127 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15128 15129/* ------------------------------ */ 15130 .balign 64 15131.L_ALT_OP_INT_TO_BYTE: /* 0x8d */ 15132/* File: armv5te/ALT_STUB.S */ 15133/* 15134 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15135 * any interesting requests and then jump to the real instruction 15136 * handler. Note that the call to dvmCheckInst is done as a tail call. 15137 */ 15138 adrl lr, dvmAsmInstructionStart + (141 * 64) 15139 mov r0, rPC @ arg0 15140 mov r1, rSELF @ arg1 15141 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15142 15143/* ------------------------------ */ 15144 .balign 64 15145.L_ALT_OP_INT_TO_CHAR: /* 0x8e */ 15146/* File: armv5te/ALT_STUB.S */ 15147/* 15148 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15149 * any interesting requests and then jump to the real instruction 15150 * handler. Note that the call to dvmCheckInst is done as a tail call. 15151 */ 15152 adrl lr, dvmAsmInstructionStart + (142 * 64) 15153 mov r0, rPC @ arg0 15154 mov r1, rSELF @ arg1 15155 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15156 15157/* ------------------------------ */ 15158 .balign 64 15159.L_ALT_OP_INT_TO_SHORT: /* 0x8f */ 15160/* File: armv5te/ALT_STUB.S */ 15161/* 15162 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15163 * any interesting requests and then jump to the real instruction 15164 * handler. Note that the call to dvmCheckInst is done as a tail call. 15165 */ 15166 adrl lr, dvmAsmInstructionStart + (143 * 64) 15167 mov r0, rPC @ arg0 15168 mov r1, rSELF @ arg1 15169 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15170 15171/* ------------------------------ */ 15172 .balign 64 15173.L_ALT_OP_ADD_INT: /* 0x90 */ 15174/* File: armv5te/ALT_STUB.S */ 15175/* 15176 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15177 * any interesting requests and then jump to the real instruction 15178 * handler. Note that the call to dvmCheckInst is done as a tail call. 15179 */ 15180 adrl lr, dvmAsmInstructionStart + (144 * 64) 15181 mov r0, rPC @ arg0 15182 mov r1, rSELF @ arg1 15183 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15184 15185/* ------------------------------ */ 15186 .balign 64 15187.L_ALT_OP_SUB_INT: /* 0x91 */ 15188/* File: armv5te/ALT_STUB.S */ 15189/* 15190 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15191 * any interesting requests and then jump to the real instruction 15192 * handler. Note that the call to dvmCheckInst is done as a tail call. 15193 */ 15194 adrl lr, dvmAsmInstructionStart + (145 * 64) 15195 mov r0, rPC @ arg0 15196 mov r1, rSELF @ arg1 15197 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15198 15199/* ------------------------------ */ 15200 .balign 64 15201.L_ALT_OP_MUL_INT: /* 0x92 */ 15202/* File: armv5te/ALT_STUB.S */ 15203/* 15204 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15205 * any interesting requests and then jump to the real instruction 15206 * handler. Note that the call to dvmCheckInst is done as a tail call. 15207 */ 15208 adrl lr, dvmAsmInstructionStart + (146 * 64) 15209 mov r0, rPC @ arg0 15210 mov r1, rSELF @ arg1 15211 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15212 15213/* ------------------------------ */ 15214 .balign 64 15215.L_ALT_OP_DIV_INT: /* 0x93 */ 15216/* File: armv5te/ALT_STUB.S */ 15217/* 15218 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15219 * any interesting requests and then jump to the real instruction 15220 * handler. Note that the call to dvmCheckInst is done as a tail call. 15221 */ 15222 adrl lr, dvmAsmInstructionStart + (147 * 64) 15223 mov r0, rPC @ arg0 15224 mov r1, rSELF @ arg1 15225 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15226 15227/* ------------------------------ */ 15228 .balign 64 15229.L_ALT_OP_REM_INT: /* 0x94 */ 15230/* File: armv5te/ALT_STUB.S */ 15231/* 15232 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15233 * any interesting requests and then jump to the real instruction 15234 * handler. Note that the call to dvmCheckInst is done as a tail call. 15235 */ 15236 adrl lr, dvmAsmInstructionStart + (148 * 64) 15237 mov r0, rPC @ arg0 15238 mov r1, rSELF @ arg1 15239 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15240 15241/* ------------------------------ */ 15242 .balign 64 15243.L_ALT_OP_AND_INT: /* 0x95 */ 15244/* File: armv5te/ALT_STUB.S */ 15245/* 15246 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15247 * any interesting requests and then jump to the real instruction 15248 * handler. Note that the call to dvmCheckInst is done as a tail call. 15249 */ 15250 adrl lr, dvmAsmInstructionStart + (149 * 64) 15251 mov r0, rPC @ arg0 15252 mov r1, rSELF @ arg1 15253 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15254 15255/* ------------------------------ */ 15256 .balign 64 15257.L_ALT_OP_OR_INT: /* 0x96 */ 15258/* File: armv5te/ALT_STUB.S */ 15259/* 15260 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15261 * any interesting requests and then jump to the real instruction 15262 * handler. Note that the call to dvmCheckInst is done as a tail call. 15263 */ 15264 adrl lr, dvmAsmInstructionStart + (150 * 64) 15265 mov r0, rPC @ arg0 15266 mov r1, rSELF @ arg1 15267 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15268 15269/* ------------------------------ */ 15270 .balign 64 15271.L_ALT_OP_XOR_INT: /* 0x97 */ 15272/* File: armv5te/ALT_STUB.S */ 15273/* 15274 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15275 * any interesting requests and then jump to the real instruction 15276 * handler. Note that the call to dvmCheckInst is done as a tail call. 15277 */ 15278 adrl lr, dvmAsmInstructionStart + (151 * 64) 15279 mov r0, rPC @ arg0 15280 mov r1, rSELF @ arg1 15281 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15282 15283/* ------------------------------ */ 15284 .balign 64 15285.L_ALT_OP_SHL_INT: /* 0x98 */ 15286/* File: armv5te/ALT_STUB.S */ 15287/* 15288 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15289 * any interesting requests and then jump to the real instruction 15290 * handler. Note that the call to dvmCheckInst is done as a tail call. 15291 */ 15292 adrl lr, dvmAsmInstructionStart + (152 * 64) 15293 mov r0, rPC @ arg0 15294 mov r1, rSELF @ arg1 15295 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15296 15297/* ------------------------------ */ 15298 .balign 64 15299.L_ALT_OP_SHR_INT: /* 0x99 */ 15300/* File: armv5te/ALT_STUB.S */ 15301/* 15302 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15303 * any interesting requests and then jump to the real instruction 15304 * handler. Note that the call to dvmCheckInst is done as a tail call. 15305 */ 15306 adrl lr, dvmAsmInstructionStart + (153 * 64) 15307 mov r0, rPC @ arg0 15308 mov r1, rSELF @ arg1 15309 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15310 15311/* ------------------------------ */ 15312 .balign 64 15313.L_ALT_OP_USHR_INT: /* 0x9a */ 15314/* File: armv5te/ALT_STUB.S */ 15315/* 15316 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15317 * any interesting requests and then jump to the real instruction 15318 * handler. Note that the call to dvmCheckInst is done as a tail call. 15319 */ 15320 adrl lr, dvmAsmInstructionStart + (154 * 64) 15321 mov r0, rPC @ arg0 15322 mov r1, rSELF @ arg1 15323 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15324 15325/* ------------------------------ */ 15326 .balign 64 15327.L_ALT_OP_ADD_LONG: /* 0x9b */ 15328/* File: armv5te/ALT_STUB.S */ 15329/* 15330 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15331 * any interesting requests and then jump to the real instruction 15332 * handler. Note that the call to dvmCheckInst is done as a tail call. 15333 */ 15334 adrl lr, dvmAsmInstructionStart + (155 * 64) 15335 mov r0, rPC @ arg0 15336 mov r1, rSELF @ arg1 15337 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15338 15339/* ------------------------------ */ 15340 .balign 64 15341.L_ALT_OP_SUB_LONG: /* 0x9c */ 15342/* File: armv5te/ALT_STUB.S */ 15343/* 15344 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15345 * any interesting requests and then jump to the real instruction 15346 * handler. Note that the call to dvmCheckInst is done as a tail call. 15347 */ 15348 adrl lr, dvmAsmInstructionStart + (156 * 64) 15349 mov r0, rPC @ arg0 15350 mov r1, rSELF @ arg1 15351 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15352 15353/* ------------------------------ */ 15354 .balign 64 15355.L_ALT_OP_MUL_LONG: /* 0x9d */ 15356/* File: armv5te/ALT_STUB.S */ 15357/* 15358 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15359 * any interesting requests and then jump to the real instruction 15360 * handler. Note that the call to dvmCheckInst is done as a tail call. 15361 */ 15362 adrl lr, dvmAsmInstructionStart + (157 * 64) 15363 mov r0, rPC @ arg0 15364 mov r1, rSELF @ arg1 15365 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15366 15367/* ------------------------------ */ 15368 .balign 64 15369.L_ALT_OP_DIV_LONG: /* 0x9e */ 15370/* File: armv5te/ALT_STUB.S */ 15371/* 15372 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15373 * any interesting requests and then jump to the real instruction 15374 * handler. Note that the call to dvmCheckInst is done as a tail call. 15375 */ 15376 adrl lr, dvmAsmInstructionStart + (158 * 64) 15377 mov r0, rPC @ arg0 15378 mov r1, rSELF @ arg1 15379 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15380 15381/* ------------------------------ */ 15382 .balign 64 15383.L_ALT_OP_REM_LONG: /* 0x9f */ 15384/* File: armv5te/ALT_STUB.S */ 15385/* 15386 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15387 * any interesting requests and then jump to the real instruction 15388 * handler. Note that the call to dvmCheckInst is done as a tail call. 15389 */ 15390 adrl lr, dvmAsmInstructionStart + (159 * 64) 15391 mov r0, rPC @ arg0 15392 mov r1, rSELF @ arg1 15393 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15394 15395/* ------------------------------ */ 15396 .balign 64 15397.L_ALT_OP_AND_LONG: /* 0xa0 */ 15398/* File: armv5te/ALT_STUB.S */ 15399/* 15400 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15401 * any interesting requests and then jump to the real instruction 15402 * handler. Note that the call to dvmCheckInst is done as a tail call. 15403 */ 15404 adrl lr, dvmAsmInstructionStart + (160 * 64) 15405 mov r0, rPC @ arg0 15406 mov r1, rSELF @ arg1 15407 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15408 15409/* ------------------------------ */ 15410 .balign 64 15411.L_ALT_OP_OR_LONG: /* 0xa1 */ 15412/* File: armv5te/ALT_STUB.S */ 15413/* 15414 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15415 * any interesting requests and then jump to the real instruction 15416 * handler. Note that the call to dvmCheckInst is done as a tail call. 15417 */ 15418 adrl lr, dvmAsmInstructionStart + (161 * 64) 15419 mov r0, rPC @ arg0 15420 mov r1, rSELF @ arg1 15421 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15422 15423/* ------------------------------ */ 15424 .balign 64 15425.L_ALT_OP_XOR_LONG: /* 0xa2 */ 15426/* File: armv5te/ALT_STUB.S */ 15427/* 15428 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15429 * any interesting requests and then jump to the real instruction 15430 * handler. Note that the call to dvmCheckInst is done as a tail call. 15431 */ 15432 adrl lr, dvmAsmInstructionStart + (162 * 64) 15433 mov r0, rPC @ arg0 15434 mov r1, rSELF @ arg1 15435 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15436 15437/* ------------------------------ */ 15438 .balign 64 15439.L_ALT_OP_SHL_LONG: /* 0xa3 */ 15440/* File: armv5te/ALT_STUB.S */ 15441/* 15442 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15443 * any interesting requests and then jump to the real instruction 15444 * handler. Note that the call to dvmCheckInst is done as a tail call. 15445 */ 15446 adrl lr, dvmAsmInstructionStart + (163 * 64) 15447 mov r0, rPC @ arg0 15448 mov r1, rSELF @ arg1 15449 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15450 15451/* ------------------------------ */ 15452 .balign 64 15453.L_ALT_OP_SHR_LONG: /* 0xa4 */ 15454/* File: armv5te/ALT_STUB.S */ 15455/* 15456 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15457 * any interesting requests and then jump to the real instruction 15458 * handler. Note that the call to dvmCheckInst is done as a tail call. 15459 */ 15460 adrl lr, dvmAsmInstructionStart + (164 * 64) 15461 mov r0, rPC @ arg0 15462 mov r1, rSELF @ arg1 15463 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15464 15465/* ------------------------------ */ 15466 .balign 64 15467.L_ALT_OP_USHR_LONG: /* 0xa5 */ 15468/* File: armv5te/ALT_STUB.S */ 15469/* 15470 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15471 * any interesting requests and then jump to the real instruction 15472 * handler. Note that the call to dvmCheckInst is done as a tail call. 15473 */ 15474 adrl lr, dvmAsmInstructionStart + (165 * 64) 15475 mov r0, rPC @ arg0 15476 mov r1, rSELF @ arg1 15477 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15478 15479/* ------------------------------ */ 15480 .balign 64 15481.L_ALT_OP_ADD_FLOAT: /* 0xa6 */ 15482/* File: armv5te/ALT_STUB.S */ 15483/* 15484 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15485 * any interesting requests and then jump to the real instruction 15486 * handler. Note that the call to dvmCheckInst is done as a tail call. 15487 */ 15488 adrl lr, dvmAsmInstructionStart + (166 * 64) 15489 mov r0, rPC @ arg0 15490 mov r1, rSELF @ arg1 15491 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15492 15493/* ------------------------------ */ 15494 .balign 64 15495.L_ALT_OP_SUB_FLOAT: /* 0xa7 */ 15496/* File: armv5te/ALT_STUB.S */ 15497/* 15498 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15499 * any interesting requests and then jump to the real instruction 15500 * handler. Note that the call to dvmCheckInst is done as a tail call. 15501 */ 15502 adrl lr, dvmAsmInstructionStart + (167 * 64) 15503 mov r0, rPC @ arg0 15504 mov r1, rSELF @ arg1 15505 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15506 15507/* ------------------------------ */ 15508 .balign 64 15509.L_ALT_OP_MUL_FLOAT: /* 0xa8 */ 15510/* File: armv5te/ALT_STUB.S */ 15511/* 15512 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15513 * any interesting requests and then jump to the real instruction 15514 * handler. Note that the call to dvmCheckInst is done as a tail call. 15515 */ 15516 adrl lr, dvmAsmInstructionStart + (168 * 64) 15517 mov r0, rPC @ arg0 15518 mov r1, rSELF @ arg1 15519 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15520 15521/* ------------------------------ */ 15522 .balign 64 15523.L_ALT_OP_DIV_FLOAT: /* 0xa9 */ 15524/* File: armv5te/ALT_STUB.S */ 15525/* 15526 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15527 * any interesting requests and then jump to the real instruction 15528 * handler. Note that the call to dvmCheckInst is done as a tail call. 15529 */ 15530 adrl lr, dvmAsmInstructionStart + (169 * 64) 15531 mov r0, rPC @ arg0 15532 mov r1, rSELF @ arg1 15533 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15534 15535/* ------------------------------ */ 15536 .balign 64 15537.L_ALT_OP_REM_FLOAT: /* 0xaa */ 15538/* File: armv5te/ALT_STUB.S */ 15539/* 15540 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15541 * any interesting requests and then jump to the real instruction 15542 * handler. Note that the call to dvmCheckInst is done as a tail call. 15543 */ 15544 adrl lr, dvmAsmInstructionStart + (170 * 64) 15545 mov r0, rPC @ arg0 15546 mov r1, rSELF @ arg1 15547 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15548 15549/* ------------------------------ */ 15550 .balign 64 15551.L_ALT_OP_ADD_DOUBLE: /* 0xab */ 15552/* File: armv5te/ALT_STUB.S */ 15553/* 15554 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15555 * any interesting requests and then jump to the real instruction 15556 * handler. Note that the call to dvmCheckInst is done as a tail call. 15557 */ 15558 adrl lr, dvmAsmInstructionStart + (171 * 64) 15559 mov r0, rPC @ arg0 15560 mov r1, rSELF @ arg1 15561 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15562 15563/* ------------------------------ */ 15564 .balign 64 15565.L_ALT_OP_SUB_DOUBLE: /* 0xac */ 15566/* File: armv5te/ALT_STUB.S */ 15567/* 15568 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15569 * any interesting requests and then jump to the real instruction 15570 * handler. Note that the call to dvmCheckInst is done as a tail call. 15571 */ 15572 adrl lr, dvmAsmInstructionStart + (172 * 64) 15573 mov r0, rPC @ arg0 15574 mov r1, rSELF @ arg1 15575 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15576 15577/* ------------------------------ */ 15578 .balign 64 15579.L_ALT_OP_MUL_DOUBLE: /* 0xad */ 15580/* File: armv5te/ALT_STUB.S */ 15581/* 15582 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15583 * any interesting requests and then jump to the real instruction 15584 * handler. Note that the call to dvmCheckInst is done as a tail call. 15585 */ 15586 adrl lr, dvmAsmInstructionStart + (173 * 64) 15587 mov r0, rPC @ arg0 15588 mov r1, rSELF @ arg1 15589 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15590 15591/* ------------------------------ */ 15592 .balign 64 15593.L_ALT_OP_DIV_DOUBLE: /* 0xae */ 15594/* File: armv5te/ALT_STUB.S */ 15595/* 15596 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15597 * any interesting requests and then jump to the real instruction 15598 * handler. Note that the call to dvmCheckInst is done as a tail call. 15599 */ 15600 adrl lr, dvmAsmInstructionStart + (174 * 64) 15601 mov r0, rPC @ arg0 15602 mov r1, rSELF @ arg1 15603 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15604 15605/* ------------------------------ */ 15606 .balign 64 15607.L_ALT_OP_REM_DOUBLE: /* 0xaf */ 15608/* File: armv5te/ALT_STUB.S */ 15609/* 15610 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15611 * any interesting requests and then jump to the real instruction 15612 * handler. Note that the call to dvmCheckInst is done as a tail call. 15613 */ 15614 adrl lr, dvmAsmInstructionStart + (175 * 64) 15615 mov r0, rPC @ arg0 15616 mov r1, rSELF @ arg1 15617 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15618 15619/* ------------------------------ */ 15620 .balign 64 15621.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */ 15622/* File: armv5te/ALT_STUB.S */ 15623/* 15624 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15625 * any interesting requests and then jump to the real instruction 15626 * handler. Note that the call to dvmCheckInst is done as a tail call. 15627 */ 15628 adrl lr, dvmAsmInstructionStart + (176 * 64) 15629 mov r0, rPC @ arg0 15630 mov r1, rSELF @ arg1 15631 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15632 15633/* ------------------------------ */ 15634 .balign 64 15635.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */ 15636/* File: armv5te/ALT_STUB.S */ 15637/* 15638 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15639 * any interesting requests and then jump to the real instruction 15640 * handler. Note that the call to dvmCheckInst is done as a tail call. 15641 */ 15642 adrl lr, dvmAsmInstructionStart + (177 * 64) 15643 mov r0, rPC @ arg0 15644 mov r1, rSELF @ arg1 15645 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15646 15647/* ------------------------------ */ 15648 .balign 64 15649.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */ 15650/* File: armv5te/ALT_STUB.S */ 15651/* 15652 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15653 * any interesting requests and then jump to the real instruction 15654 * handler. Note that the call to dvmCheckInst is done as a tail call. 15655 */ 15656 adrl lr, dvmAsmInstructionStart + (178 * 64) 15657 mov r0, rPC @ arg0 15658 mov r1, rSELF @ arg1 15659 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15660 15661/* ------------------------------ */ 15662 .balign 64 15663.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */ 15664/* File: armv5te/ALT_STUB.S */ 15665/* 15666 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15667 * any interesting requests and then jump to the real instruction 15668 * handler. Note that the call to dvmCheckInst is done as a tail call. 15669 */ 15670 adrl lr, dvmAsmInstructionStart + (179 * 64) 15671 mov r0, rPC @ arg0 15672 mov r1, rSELF @ arg1 15673 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15674 15675/* ------------------------------ */ 15676 .balign 64 15677.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */ 15678/* File: armv5te/ALT_STUB.S */ 15679/* 15680 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15681 * any interesting requests and then jump to the real instruction 15682 * handler. Note that the call to dvmCheckInst is done as a tail call. 15683 */ 15684 adrl lr, dvmAsmInstructionStart + (180 * 64) 15685 mov r0, rPC @ arg0 15686 mov r1, rSELF @ arg1 15687 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15688 15689/* ------------------------------ */ 15690 .balign 64 15691.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */ 15692/* File: armv5te/ALT_STUB.S */ 15693/* 15694 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15695 * any interesting requests and then jump to the real instruction 15696 * handler. Note that the call to dvmCheckInst is done as a tail call. 15697 */ 15698 adrl lr, dvmAsmInstructionStart + (181 * 64) 15699 mov r0, rPC @ arg0 15700 mov r1, rSELF @ arg1 15701 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15702 15703/* ------------------------------ */ 15704 .balign 64 15705.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */ 15706/* File: armv5te/ALT_STUB.S */ 15707/* 15708 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15709 * any interesting requests and then jump to the real instruction 15710 * handler. Note that the call to dvmCheckInst is done as a tail call. 15711 */ 15712 adrl lr, dvmAsmInstructionStart + (182 * 64) 15713 mov r0, rPC @ arg0 15714 mov r1, rSELF @ arg1 15715 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15716 15717/* ------------------------------ */ 15718 .balign 64 15719.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */ 15720/* File: armv5te/ALT_STUB.S */ 15721/* 15722 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15723 * any interesting requests and then jump to the real instruction 15724 * handler. Note that the call to dvmCheckInst is done as a tail call. 15725 */ 15726 adrl lr, dvmAsmInstructionStart + (183 * 64) 15727 mov r0, rPC @ arg0 15728 mov r1, rSELF @ arg1 15729 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15730 15731/* ------------------------------ */ 15732 .balign 64 15733.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */ 15734/* File: armv5te/ALT_STUB.S */ 15735/* 15736 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15737 * any interesting requests and then jump to the real instruction 15738 * handler. Note that the call to dvmCheckInst is done as a tail call. 15739 */ 15740 adrl lr, dvmAsmInstructionStart + (184 * 64) 15741 mov r0, rPC @ arg0 15742 mov r1, rSELF @ arg1 15743 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15744 15745/* ------------------------------ */ 15746 .balign 64 15747.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */ 15748/* File: armv5te/ALT_STUB.S */ 15749/* 15750 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15751 * any interesting requests and then jump to the real instruction 15752 * handler. Note that the call to dvmCheckInst is done as a tail call. 15753 */ 15754 adrl lr, dvmAsmInstructionStart + (185 * 64) 15755 mov r0, rPC @ arg0 15756 mov r1, rSELF @ arg1 15757 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15758 15759/* ------------------------------ */ 15760 .balign 64 15761.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */ 15762/* File: armv5te/ALT_STUB.S */ 15763/* 15764 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15765 * any interesting requests and then jump to the real instruction 15766 * handler. Note that the call to dvmCheckInst is done as a tail call. 15767 */ 15768 adrl lr, dvmAsmInstructionStart + (186 * 64) 15769 mov r0, rPC @ arg0 15770 mov r1, rSELF @ arg1 15771 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15772 15773/* ------------------------------ */ 15774 .balign 64 15775.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */ 15776/* File: armv5te/ALT_STUB.S */ 15777/* 15778 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15779 * any interesting requests and then jump to the real instruction 15780 * handler. Note that the call to dvmCheckInst is done as a tail call. 15781 */ 15782 adrl lr, dvmAsmInstructionStart + (187 * 64) 15783 mov r0, rPC @ arg0 15784 mov r1, rSELF @ arg1 15785 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15786 15787/* ------------------------------ */ 15788 .balign 64 15789.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */ 15790/* File: armv5te/ALT_STUB.S */ 15791/* 15792 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15793 * any interesting requests and then jump to the real instruction 15794 * handler. Note that the call to dvmCheckInst is done as a tail call. 15795 */ 15796 adrl lr, dvmAsmInstructionStart + (188 * 64) 15797 mov r0, rPC @ arg0 15798 mov r1, rSELF @ arg1 15799 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15800 15801/* ------------------------------ */ 15802 .balign 64 15803.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */ 15804/* File: armv5te/ALT_STUB.S */ 15805/* 15806 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15807 * any interesting requests and then jump to the real instruction 15808 * handler. Note that the call to dvmCheckInst is done as a tail call. 15809 */ 15810 adrl lr, dvmAsmInstructionStart + (189 * 64) 15811 mov r0, rPC @ arg0 15812 mov r1, rSELF @ arg1 15813 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15814 15815/* ------------------------------ */ 15816 .balign 64 15817.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */ 15818/* File: armv5te/ALT_STUB.S */ 15819/* 15820 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15821 * any interesting requests and then jump to the real instruction 15822 * handler. Note that the call to dvmCheckInst is done as a tail call. 15823 */ 15824 adrl lr, dvmAsmInstructionStart + (190 * 64) 15825 mov r0, rPC @ arg0 15826 mov r1, rSELF @ arg1 15827 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15828 15829/* ------------------------------ */ 15830 .balign 64 15831.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */ 15832/* File: armv5te/ALT_STUB.S */ 15833/* 15834 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15835 * any interesting requests and then jump to the real instruction 15836 * handler. Note that the call to dvmCheckInst is done as a tail call. 15837 */ 15838 adrl lr, dvmAsmInstructionStart + (191 * 64) 15839 mov r0, rPC @ arg0 15840 mov r1, rSELF @ arg1 15841 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15842 15843/* ------------------------------ */ 15844 .balign 64 15845.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */ 15846/* File: armv5te/ALT_STUB.S */ 15847/* 15848 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15849 * any interesting requests and then jump to the real instruction 15850 * handler. Note that the call to dvmCheckInst is done as a tail call. 15851 */ 15852 adrl lr, dvmAsmInstructionStart + (192 * 64) 15853 mov r0, rPC @ arg0 15854 mov r1, rSELF @ arg1 15855 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15856 15857/* ------------------------------ */ 15858 .balign 64 15859.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */ 15860/* File: armv5te/ALT_STUB.S */ 15861/* 15862 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15863 * any interesting requests and then jump to the real instruction 15864 * handler. Note that the call to dvmCheckInst is done as a tail call. 15865 */ 15866 adrl lr, dvmAsmInstructionStart + (193 * 64) 15867 mov r0, rPC @ arg0 15868 mov r1, rSELF @ arg1 15869 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15870 15871/* ------------------------------ */ 15872 .balign 64 15873.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */ 15874/* File: armv5te/ALT_STUB.S */ 15875/* 15876 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15877 * any interesting requests and then jump to the real instruction 15878 * handler. Note that the call to dvmCheckInst is done as a tail call. 15879 */ 15880 adrl lr, dvmAsmInstructionStart + (194 * 64) 15881 mov r0, rPC @ arg0 15882 mov r1, rSELF @ arg1 15883 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15884 15885/* ------------------------------ */ 15886 .balign 64 15887.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */ 15888/* File: armv5te/ALT_STUB.S */ 15889/* 15890 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15891 * any interesting requests and then jump to the real instruction 15892 * handler. Note that the call to dvmCheckInst is done as a tail call. 15893 */ 15894 adrl lr, dvmAsmInstructionStart + (195 * 64) 15895 mov r0, rPC @ arg0 15896 mov r1, rSELF @ arg1 15897 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15898 15899/* ------------------------------ */ 15900 .balign 64 15901.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */ 15902/* File: armv5te/ALT_STUB.S */ 15903/* 15904 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15905 * any interesting requests and then jump to the real instruction 15906 * handler. Note that the call to dvmCheckInst is done as a tail call. 15907 */ 15908 adrl lr, dvmAsmInstructionStart + (196 * 64) 15909 mov r0, rPC @ arg0 15910 mov r1, rSELF @ arg1 15911 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15912 15913/* ------------------------------ */ 15914 .balign 64 15915.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */ 15916/* File: armv5te/ALT_STUB.S */ 15917/* 15918 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15919 * any interesting requests and then jump to the real instruction 15920 * handler. Note that the call to dvmCheckInst is done as a tail call. 15921 */ 15922 adrl lr, dvmAsmInstructionStart + (197 * 64) 15923 mov r0, rPC @ arg0 15924 mov r1, rSELF @ arg1 15925 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15926 15927/* ------------------------------ */ 15928 .balign 64 15929.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 15930/* File: armv5te/ALT_STUB.S */ 15931/* 15932 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15933 * any interesting requests and then jump to the real instruction 15934 * handler. Note that the call to dvmCheckInst is done as a tail call. 15935 */ 15936 adrl lr, dvmAsmInstructionStart + (198 * 64) 15937 mov r0, rPC @ arg0 15938 mov r1, rSELF @ arg1 15939 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15940 15941/* ------------------------------ */ 15942 .balign 64 15943.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 15944/* File: armv5te/ALT_STUB.S */ 15945/* 15946 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15947 * any interesting requests and then jump to the real instruction 15948 * handler. Note that the call to dvmCheckInst is done as a tail call. 15949 */ 15950 adrl lr, dvmAsmInstructionStart + (199 * 64) 15951 mov r0, rPC @ arg0 15952 mov r1, rSELF @ arg1 15953 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15954 15955/* ------------------------------ */ 15956 .balign 64 15957.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 15958/* File: armv5te/ALT_STUB.S */ 15959/* 15960 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15961 * any interesting requests and then jump to the real instruction 15962 * handler. Note that the call to dvmCheckInst is done as a tail call. 15963 */ 15964 adrl lr, dvmAsmInstructionStart + (200 * 64) 15965 mov r0, rPC @ arg0 15966 mov r1, rSELF @ arg1 15967 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15968 15969/* ------------------------------ */ 15970 .balign 64 15971.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 15972/* File: armv5te/ALT_STUB.S */ 15973/* 15974 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15975 * any interesting requests and then jump to the real instruction 15976 * handler. Note that the call to dvmCheckInst is done as a tail call. 15977 */ 15978 adrl lr, dvmAsmInstructionStart + (201 * 64) 15979 mov r0, rPC @ arg0 15980 mov r1, rSELF @ arg1 15981 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15982 15983/* ------------------------------ */ 15984 .balign 64 15985.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */ 15986/* File: armv5te/ALT_STUB.S */ 15987/* 15988 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15989 * any interesting requests and then jump to the real instruction 15990 * handler. Note that the call to dvmCheckInst is done as a tail call. 15991 */ 15992 adrl lr, dvmAsmInstructionStart + (202 * 64) 15993 mov r0, rPC @ arg0 15994 mov r1, rSELF @ arg1 15995 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15996 15997/* ------------------------------ */ 15998 .balign 64 15999.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 16000/* File: armv5te/ALT_STUB.S */ 16001/* 16002 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16003 * any interesting requests and then jump to the real instruction 16004 * handler. Note that the call to dvmCheckInst is done as a tail call. 16005 */ 16006 adrl lr, dvmAsmInstructionStart + (203 * 64) 16007 mov r0, rPC @ arg0 16008 mov r1, rSELF @ arg1 16009 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16010 16011/* ------------------------------ */ 16012 .balign 64 16013.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 16014/* File: armv5te/ALT_STUB.S */ 16015/* 16016 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16017 * any interesting requests and then jump to the real instruction 16018 * handler. Note that the call to dvmCheckInst is done as a tail call. 16019 */ 16020 adrl lr, dvmAsmInstructionStart + (204 * 64) 16021 mov r0, rPC @ arg0 16022 mov r1, rSELF @ arg1 16023 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16024 16025/* ------------------------------ */ 16026 .balign 64 16027.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 16028/* File: armv5te/ALT_STUB.S */ 16029/* 16030 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16031 * any interesting requests and then jump to the real instruction 16032 * handler. Note that the call to dvmCheckInst is done as a tail call. 16033 */ 16034 adrl lr, dvmAsmInstructionStart + (205 * 64) 16035 mov r0, rPC @ arg0 16036 mov r1, rSELF @ arg1 16037 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16038 16039/* ------------------------------ */ 16040 .balign 64 16041.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 16042/* File: armv5te/ALT_STUB.S */ 16043/* 16044 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16045 * any interesting requests and then jump to the real instruction 16046 * handler. Note that the call to dvmCheckInst is done as a tail call. 16047 */ 16048 adrl lr, dvmAsmInstructionStart + (206 * 64) 16049 mov r0, rPC @ arg0 16050 mov r1, rSELF @ arg1 16051 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16052 16053/* ------------------------------ */ 16054 .balign 64 16055.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 16056/* File: armv5te/ALT_STUB.S */ 16057/* 16058 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16059 * any interesting requests and then jump to the real instruction 16060 * handler. Note that the call to dvmCheckInst is done as a tail call. 16061 */ 16062 adrl lr, dvmAsmInstructionStart + (207 * 64) 16063 mov r0, rPC @ arg0 16064 mov r1, rSELF @ arg1 16065 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16066 16067/* ------------------------------ */ 16068 .balign 64 16069.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */ 16070/* File: armv5te/ALT_STUB.S */ 16071/* 16072 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16073 * any interesting requests and then jump to the real instruction 16074 * handler. Note that the call to dvmCheckInst is done as a tail call. 16075 */ 16076 adrl lr, dvmAsmInstructionStart + (208 * 64) 16077 mov r0, rPC @ arg0 16078 mov r1, rSELF @ arg1 16079 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16080 16081/* ------------------------------ */ 16082 .balign 64 16083.L_ALT_OP_RSUB_INT: /* 0xd1 */ 16084/* File: armv5te/ALT_STUB.S */ 16085/* 16086 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16087 * any interesting requests and then jump to the real instruction 16088 * handler. Note that the call to dvmCheckInst is done as a tail call. 16089 */ 16090 adrl lr, dvmAsmInstructionStart + (209 * 64) 16091 mov r0, rPC @ arg0 16092 mov r1, rSELF @ arg1 16093 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16094 16095/* ------------------------------ */ 16096 .balign 64 16097.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */ 16098/* File: armv5te/ALT_STUB.S */ 16099/* 16100 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16101 * any interesting requests and then jump to the real instruction 16102 * handler. Note that the call to dvmCheckInst is done as a tail call. 16103 */ 16104 adrl lr, dvmAsmInstructionStart + (210 * 64) 16105 mov r0, rPC @ arg0 16106 mov r1, rSELF @ arg1 16107 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16108 16109/* ------------------------------ */ 16110 .balign 64 16111.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */ 16112/* File: armv5te/ALT_STUB.S */ 16113/* 16114 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16115 * any interesting requests and then jump to the real instruction 16116 * handler. Note that the call to dvmCheckInst is done as a tail call. 16117 */ 16118 adrl lr, dvmAsmInstructionStart + (211 * 64) 16119 mov r0, rPC @ arg0 16120 mov r1, rSELF @ arg1 16121 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16122 16123/* ------------------------------ */ 16124 .balign 64 16125.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */ 16126/* File: armv5te/ALT_STUB.S */ 16127/* 16128 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16129 * any interesting requests and then jump to the real instruction 16130 * handler. Note that the call to dvmCheckInst is done as a tail call. 16131 */ 16132 adrl lr, dvmAsmInstructionStart + (212 * 64) 16133 mov r0, rPC @ arg0 16134 mov r1, rSELF @ arg1 16135 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16136 16137/* ------------------------------ */ 16138 .balign 64 16139.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */ 16140/* File: armv5te/ALT_STUB.S */ 16141/* 16142 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16143 * any interesting requests and then jump to the real instruction 16144 * handler. Note that the call to dvmCheckInst is done as a tail call. 16145 */ 16146 adrl lr, dvmAsmInstructionStart + (213 * 64) 16147 mov r0, rPC @ arg0 16148 mov r1, rSELF @ arg1 16149 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16150 16151/* ------------------------------ */ 16152 .balign 64 16153.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */ 16154/* File: armv5te/ALT_STUB.S */ 16155/* 16156 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16157 * any interesting requests and then jump to the real instruction 16158 * handler. Note that the call to dvmCheckInst is done as a tail call. 16159 */ 16160 adrl lr, dvmAsmInstructionStart + (214 * 64) 16161 mov r0, rPC @ arg0 16162 mov r1, rSELF @ arg1 16163 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16164 16165/* ------------------------------ */ 16166 .balign 64 16167.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */ 16168/* File: armv5te/ALT_STUB.S */ 16169/* 16170 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16171 * any interesting requests and then jump to the real instruction 16172 * handler. Note that the call to dvmCheckInst is done as a tail call. 16173 */ 16174 adrl lr, dvmAsmInstructionStart + (215 * 64) 16175 mov r0, rPC @ arg0 16176 mov r1, rSELF @ arg1 16177 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16178 16179/* ------------------------------ */ 16180 .balign 64 16181.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */ 16182/* File: armv5te/ALT_STUB.S */ 16183/* 16184 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16185 * any interesting requests and then jump to the real instruction 16186 * handler. Note that the call to dvmCheckInst is done as a tail call. 16187 */ 16188 adrl lr, dvmAsmInstructionStart + (216 * 64) 16189 mov r0, rPC @ arg0 16190 mov r1, rSELF @ arg1 16191 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16192 16193/* ------------------------------ */ 16194 .balign 64 16195.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */ 16196/* File: armv5te/ALT_STUB.S */ 16197/* 16198 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16199 * any interesting requests and then jump to the real instruction 16200 * handler. Note that the call to dvmCheckInst is done as a tail call. 16201 */ 16202 adrl lr, dvmAsmInstructionStart + (217 * 64) 16203 mov r0, rPC @ arg0 16204 mov r1, rSELF @ arg1 16205 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16206 16207/* ------------------------------ */ 16208 .balign 64 16209.L_ALT_OP_MUL_INT_LIT8: /* 0xda */ 16210/* File: armv5te/ALT_STUB.S */ 16211/* 16212 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16213 * any interesting requests and then jump to the real instruction 16214 * handler. Note that the call to dvmCheckInst is done as a tail call. 16215 */ 16216 adrl lr, dvmAsmInstructionStart + (218 * 64) 16217 mov r0, rPC @ arg0 16218 mov r1, rSELF @ arg1 16219 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16220 16221/* ------------------------------ */ 16222 .balign 64 16223.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */ 16224/* File: armv5te/ALT_STUB.S */ 16225/* 16226 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16227 * any interesting requests and then jump to the real instruction 16228 * handler. Note that the call to dvmCheckInst is done as a tail call. 16229 */ 16230 adrl lr, dvmAsmInstructionStart + (219 * 64) 16231 mov r0, rPC @ arg0 16232 mov r1, rSELF @ arg1 16233 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16234 16235/* ------------------------------ */ 16236 .balign 64 16237.L_ALT_OP_REM_INT_LIT8: /* 0xdc */ 16238/* File: armv5te/ALT_STUB.S */ 16239/* 16240 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16241 * any interesting requests and then jump to the real instruction 16242 * handler. Note that the call to dvmCheckInst is done as a tail call. 16243 */ 16244 adrl lr, dvmAsmInstructionStart + (220 * 64) 16245 mov r0, rPC @ arg0 16246 mov r1, rSELF @ arg1 16247 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16248 16249/* ------------------------------ */ 16250 .balign 64 16251.L_ALT_OP_AND_INT_LIT8: /* 0xdd */ 16252/* File: armv5te/ALT_STUB.S */ 16253/* 16254 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16255 * any interesting requests and then jump to the real instruction 16256 * handler. Note that the call to dvmCheckInst is done as a tail call. 16257 */ 16258 adrl lr, dvmAsmInstructionStart + (221 * 64) 16259 mov r0, rPC @ arg0 16260 mov r1, rSELF @ arg1 16261 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16262 16263/* ------------------------------ */ 16264 .balign 64 16265.L_ALT_OP_OR_INT_LIT8: /* 0xde */ 16266/* File: armv5te/ALT_STUB.S */ 16267/* 16268 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16269 * any interesting requests and then jump to the real instruction 16270 * handler. Note that the call to dvmCheckInst is done as a tail call. 16271 */ 16272 adrl lr, dvmAsmInstructionStart + (222 * 64) 16273 mov r0, rPC @ arg0 16274 mov r1, rSELF @ arg1 16275 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16276 16277/* ------------------------------ */ 16278 .balign 64 16279.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */ 16280/* File: armv5te/ALT_STUB.S */ 16281/* 16282 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16283 * any interesting requests and then jump to the real instruction 16284 * handler. Note that the call to dvmCheckInst is done as a tail call. 16285 */ 16286 adrl lr, dvmAsmInstructionStart + (223 * 64) 16287 mov r0, rPC @ arg0 16288 mov r1, rSELF @ arg1 16289 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16290 16291/* ------------------------------ */ 16292 .balign 64 16293.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */ 16294/* File: armv5te/ALT_STUB.S */ 16295/* 16296 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16297 * any interesting requests and then jump to the real instruction 16298 * handler. Note that the call to dvmCheckInst is done as a tail call. 16299 */ 16300 adrl lr, dvmAsmInstructionStart + (224 * 64) 16301 mov r0, rPC @ arg0 16302 mov r1, rSELF @ arg1 16303 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16304 16305/* ------------------------------ */ 16306 .balign 64 16307.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */ 16308/* File: armv5te/ALT_STUB.S */ 16309/* 16310 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16311 * any interesting requests and then jump to the real instruction 16312 * handler. Note that the call to dvmCheckInst is done as a tail call. 16313 */ 16314 adrl lr, dvmAsmInstructionStart + (225 * 64) 16315 mov r0, rPC @ arg0 16316 mov r1, rSELF @ arg1 16317 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16318 16319/* ------------------------------ */ 16320 .balign 64 16321.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */ 16322/* File: armv5te/ALT_STUB.S */ 16323/* 16324 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16325 * any interesting requests and then jump to the real instruction 16326 * handler. Note that the call to dvmCheckInst is done as a tail call. 16327 */ 16328 adrl lr, dvmAsmInstructionStart + (226 * 64) 16329 mov r0, rPC @ arg0 16330 mov r1, rSELF @ arg1 16331 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16332 16333/* ------------------------------ */ 16334 .balign 64 16335.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */ 16336/* File: armv5te/ALT_STUB.S */ 16337/* 16338 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16339 * any interesting requests and then jump to the real instruction 16340 * handler. Note that the call to dvmCheckInst is done as a tail call. 16341 */ 16342 adrl lr, dvmAsmInstructionStart + (227 * 64) 16343 mov r0, rPC @ arg0 16344 mov r1, rSELF @ arg1 16345 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16346 16347/* ------------------------------ */ 16348 .balign 64 16349.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */ 16350/* File: armv5te/ALT_STUB.S */ 16351/* 16352 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16353 * any interesting requests and then jump to the real instruction 16354 * handler. Note that the call to dvmCheckInst is done as a tail call. 16355 */ 16356 adrl lr, dvmAsmInstructionStart + (228 * 64) 16357 mov r0, rPC @ arg0 16358 mov r1, rSELF @ arg1 16359 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16360 16361/* ------------------------------ */ 16362 .balign 64 16363.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */ 16364/* File: armv5te/ALT_STUB.S */ 16365/* 16366 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16367 * any interesting requests and then jump to the real instruction 16368 * handler. Note that the call to dvmCheckInst is done as a tail call. 16369 */ 16370 adrl lr, dvmAsmInstructionStart + (229 * 64) 16371 mov r0, rPC @ arg0 16372 mov r1, rSELF @ arg1 16373 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16374 16375/* ------------------------------ */ 16376 .balign 64 16377.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */ 16378/* File: armv5te/ALT_STUB.S */ 16379/* 16380 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16381 * any interesting requests and then jump to the real instruction 16382 * handler. Note that the call to dvmCheckInst is done as a tail call. 16383 */ 16384 adrl lr, dvmAsmInstructionStart + (230 * 64) 16385 mov r0, rPC @ arg0 16386 mov r1, rSELF @ arg1 16387 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16388 16389/* ------------------------------ */ 16390 .balign 64 16391.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 16392/* File: armv5te/ALT_STUB.S */ 16393/* 16394 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16395 * any interesting requests and then jump to the real instruction 16396 * handler. Note that the call to dvmCheckInst is done as a tail call. 16397 */ 16398 adrl lr, dvmAsmInstructionStart + (231 * 64) 16399 mov r0, rPC @ arg0 16400 mov r1, rSELF @ arg1 16401 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16402 16403/* ------------------------------ */ 16404 .balign 64 16405.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 16406/* File: armv5te/ALT_STUB.S */ 16407/* 16408 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16409 * any interesting requests and then jump to the real instruction 16410 * handler. Note that the call to dvmCheckInst is done as a tail call. 16411 */ 16412 adrl lr, dvmAsmInstructionStart + (232 * 64) 16413 mov r0, rPC @ arg0 16414 mov r1, rSELF @ arg1 16415 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16416 16417/* ------------------------------ */ 16418 .balign 64 16419.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 16420/* File: armv5te/ALT_STUB.S */ 16421/* 16422 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16423 * any interesting requests and then jump to the real instruction 16424 * handler. Note that the call to dvmCheckInst is done as a tail call. 16425 */ 16426 adrl lr, dvmAsmInstructionStart + (233 * 64) 16427 mov r0, rPC @ arg0 16428 mov r1, rSELF @ arg1 16429 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16430 16431/* ------------------------------ */ 16432 .balign 64 16433.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */ 16434/* File: armv5te/ALT_STUB.S */ 16435/* 16436 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16437 * any interesting requests and then jump to the real instruction 16438 * handler. Note that the call to dvmCheckInst is done as a tail call. 16439 */ 16440 adrl lr, dvmAsmInstructionStart + (234 * 64) 16441 mov r0, rPC @ arg0 16442 mov r1, rSELF @ arg1 16443 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16444 16445/* ------------------------------ */ 16446 .balign 64 16447.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 16448/* File: armv5te/ALT_STUB.S */ 16449/* 16450 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16451 * any interesting requests and then jump to the real instruction 16452 * handler. Note that the call to dvmCheckInst is done as a tail call. 16453 */ 16454 adrl lr, dvmAsmInstructionStart + (235 * 64) 16455 mov r0, rPC @ arg0 16456 mov r1, rSELF @ arg1 16457 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16458 16459/* ------------------------------ */ 16460 .balign 64 16461.L_ALT_OP_BREAKPOINT: /* 0xec */ 16462/* File: armv5te/ALT_STUB.S */ 16463/* 16464 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16465 * any interesting requests and then jump to the real instruction 16466 * handler. Note that the call to dvmCheckInst is done as a tail call. 16467 */ 16468 adrl lr, dvmAsmInstructionStart + (236 * 64) 16469 mov r0, rPC @ arg0 16470 mov r1, rSELF @ arg1 16471 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16472 16473/* ------------------------------ */ 16474 .balign 64 16475.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 16476/* File: armv5te/ALT_STUB.S */ 16477/* 16478 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16479 * any interesting requests and then jump to the real instruction 16480 * handler. Note that the call to dvmCheckInst is done as a tail call. 16481 */ 16482 adrl lr, dvmAsmInstructionStart + (237 * 64) 16483 mov r0, rPC @ arg0 16484 mov r1, rSELF @ arg1 16485 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16486 16487/* ------------------------------ */ 16488 .balign 64 16489.L_ALT_OP_EXECUTE_INLINE: /* 0xee */ 16490/* File: armv5te/ALT_STUB.S */ 16491/* 16492 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16493 * any interesting requests and then jump to the real instruction 16494 * handler. Note that the call to dvmCheckInst is done as a tail call. 16495 */ 16496 adrl lr, dvmAsmInstructionStart + (238 * 64) 16497 mov r0, rPC @ arg0 16498 mov r1, rSELF @ arg1 16499 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16500 16501/* ------------------------------ */ 16502 .balign 64 16503.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 16504/* File: armv5te/ALT_STUB.S */ 16505/* 16506 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16507 * any interesting requests and then jump to the real instruction 16508 * handler. Note that the call to dvmCheckInst is done as a tail call. 16509 */ 16510 adrl lr, dvmAsmInstructionStart + (239 * 64) 16511 mov r0, rPC @ arg0 16512 mov r1, rSELF @ arg1 16513 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16514 16515/* ------------------------------ */ 16516 .balign 64 16517.L_ALT_OP_INVOKE_OBJECT_INIT: /* 0xf0 */ 16518/* File: armv5te/ALT_STUB.S */ 16519/* 16520 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16521 * any interesting requests and then jump to the real instruction 16522 * handler. Note that the call to dvmCheckInst is done as a tail call. 16523 */ 16524 adrl lr, dvmAsmInstructionStart + (240 * 64) 16525 mov r0, rPC @ arg0 16526 mov r1, rSELF @ arg1 16527 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16528 16529/* ------------------------------ */ 16530 .balign 64 16531.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 16532/* File: armv5te/ALT_STUB.S */ 16533/* 16534 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16535 * any interesting requests and then jump to the real instruction 16536 * handler. Note that the call to dvmCheckInst is done as a tail call. 16537 */ 16538 adrl lr, dvmAsmInstructionStart + (241 * 64) 16539 mov r0, rPC @ arg0 16540 mov r1, rSELF @ arg1 16541 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16542 16543/* ------------------------------ */ 16544 .balign 64 16545.L_ALT_OP_IGET_QUICK: /* 0xf2 */ 16546/* File: armv5te/ALT_STUB.S */ 16547/* 16548 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16549 * any interesting requests and then jump to the real instruction 16550 * handler. Note that the call to dvmCheckInst is done as a tail call. 16551 */ 16552 adrl lr, dvmAsmInstructionStart + (242 * 64) 16553 mov r0, rPC @ arg0 16554 mov r1, rSELF @ arg1 16555 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16556 16557/* ------------------------------ */ 16558 .balign 64 16559.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */ 16560/* File: armv5te/ALT_STUB.S */ 16561/* 16562 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16563 * any interesting requests and then jump to the real instruction 16564 * handler. Note that the call to dvmCheckInst is done as a tail call. 16565 */ 16566 adrl lr, dvmAsmInstructionStart + (243 * 64) 16567 mov r0, rPC @ arg0 16568 mov r1, rSELF @ arg1 16569 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16570 16571/* ------------------------------ */ 16572 .balign 64 16573.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 16574/* File: armv5te/ALT_STUB.S */ 16575/* 16576 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16577 * any interesting requests and then jump to the real instruction 16578 * handler. Note that the call to dvmCheckInst is done as a tail call. 16579 */ 16580 adrl lr, dvmAsmInstructionStart + (244 * 64) 16581 mov r0, rPC @ arg0 16582 mov r1, rSELF @ arg1 16583 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16584 16585/* ------------------------------ */ 16586 .balign 64 16587.L_ALT_OP_IPUT_QUICK: /* 0xf5 */ 16588/* File: armv5te/ALT_STUB.S */ 16589/* 16590 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16591 * any interesting requests and then jump to the real instruction 16592 * handler. Note that the call to dvmCheckInst is done as a tail call. 16593 */ 16594 adrl lr, dvmAsmInstructionStart + (245 * 64) 16595 mov r0, rPC @ arg0 16596 mov r1, rSELF @ arg1 16597 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16598 16599/* ------------------------------ */ 16600 .balign 64 16601.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 16602/* File: armv5te/ALT_STUB.S */ 16603/* 16604 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16605 * any interesting requests and then jump to the real instruction 16606 * handler. Note that the call to dvmCheckInst is done as a tail call. 16607 */ 16608 adrl lr, dvmAsmInstructionStart + (246 * 64) 16609 mov r0, rPC @ arg0 16610 mov r1, rSELF @ arg1 16611 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16612 16613/* ------------------------------ */ 16614 .balign 64 16615.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 16616/* File: armv5te/ALT_STUB.S */ 16617/* 16618 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16619 * any interesting requests and then jump to the real instruction 16620 * handler. Note that the call to dvmCheckInst is done as a tail call. 16621 */ 16622 adrl lr, dvmAsmInstructionStart + (247 * 64) 16623 mov r0, rPC @ arg0 16624 mov r1, rSELF @ arg1 16625 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16626 16627/* ------------------------------ */ 16628 .balign 64 16629.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 16630/* File: armv5te/ALT_STUB.S */ 16631/* 16632 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16633 * any interesting requests and then jump to the real instruction 16634 * handler. Note that the call to dvmCheckInst is done as a tail call. 16635 */ 16636 adrl lr, dvmAsmInstructionStart + (248 * 64) 16637 mov r0, rPC @ arg0 16638 mov r1, rSELF @ arg1 16639 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16640 16641/* ------------------------------ */ 16642 .balign 64 16643.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 16644/* File: armv5te/ALT_STUB.S */ 16645/* 16646 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16647 * any interesting requests and then jump to the real instruction 16648 * handler. Note that the call to dvmCheckInst is done as a tail call. 16649 */ 16650 adrl lr, dvmAsmInstructionStart + (249 * 64) 16651 mov r0, rPC @ arg0 16652 mov r1, rSELF @ arg1 16653 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16654 16655/* ------------------------------ */ 16656 .balign 64 16657.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 16658/* File: armv5te/ALT_STUB.S */ 16659/* 16660 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16661 * any interesting requests and then jump to the real instruction 16662 * handler. Note that the call to dvmCheckInst is done as a tail call. 16663 */ 16664 adrl lr, dvmAsmInstructionStart + (250 * 64) 16665 mov r0, rPC @ arg0 16666 mov r1, rSELF @ arg1 16667 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16668 16669/* ------------------------------ */ 16670 .balign 64 16671.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 16672/* File: armv5te/ALT_STUB.S */ 16673/* 16674 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16675 * any interesting requests and then jump to the real instruction 16676 * handler. Note that the call to dvmCheckInst is done as a tail call. 16677 */ 16678 adrl lr, dvmAsmInstructionStart + (251 * 64) 16679 mov r0, rPC @ arg0 16680 mov r1, rSELF @ arg1 16681 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16682 16683/* ------------------------------ */ 16684 .balign 64 16685.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 16686/* File: armv5te/ALT_STUB.S */ 16687/* 16688 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16689 * any interesting requests and then jump to the real instruction 16690 * handler. Note that the call to dvmCheckInst is done as a tail call. 16691 */ 16692 adrl lr, dvmAsmInstructionStart + (252 * 64) 16693 mov r0, rPC @ arg0 16694 mov r1, rSELF @ arg1 16695 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16696 16697/* ------------------------------ */ 16698 .balign 64 16699.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 16700/* File: armv5te/ALT_STUB.S */ 16701/* 16702 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16703 * any interesting requests and then jump to the real instruction 16704 * handler. Note that the call to dvmCheckInst is done as a tail call. 16705 */ 16706 adrl lr, dvmAsmInstructionStart + (253 * 64) 16707 mov r0, rPC @ arg0 16708 mov r1, rSELF @ arg1 16709 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16710 16711/* ------------------------------ */ 16712 .balign 64 16713.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 16714/* File: armv5te/ALT_STUB.S */ 16715/* 16716 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16717 * any interesting requests and then jump to the real instruction 16718 * handler. Note that the call to dvmCheckInst is done as a tail call. 16719 */ 16720 adrl lr, dvmAsmInstructionStart + (254 * 64) 16721 mov r0, rPC @ arg0 16722 mov r1, rSELF @ arg1 16723 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16724 16725/* ------------------------------ */ 16726 .balign 64 16727.L_ALT_OP_DISPATCH_FF: /* 0xff */ 16728/* File: armv5te/ALT_OP_DISPATCH_FF.S */ 16729 mov ip, rINST, lsr #8 @ ip<- extended opcode 16730 add ip, ip, #256 @ add offset for extended opcodes 16731 GOTO_OPCODE(ip) @ go to proper extended handler 16732 16733 16734/* ------------------------------ */ 16735 .balign 64 16736.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */ 16737/* File: armv5te/ALT_STUB.S */ 16738/* 16739 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16740 * any interesting requests and then jump to the real instruction 16741 * handler. Note that the call to dvmCheckInst is done as a tail call. 16742 */ 16743 adrl lr, dvmAsmInstructionStart + (256 * 64) 16744 mov r0, rPC @ arg0 16745 mov r1, rSELF @ arg1 16746 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16747 16748/* ------------------------------ */ 16749 .balign 64 16750.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */ 16751/* File: armv5te/ALT_STUB.S */ 16752/* 16753 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16754 * any interesting requests and then jump to the real instruction 16755 * handler. Note that the call to dvmCheckInst is done as a tail call. 16756 */ 16757 adrl lr, dvmAsmInstructionStart + (257 * 64) 16758 mov r0, rPC @ arg0 16759 mov r1, rSELF @ arg1 16760 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16761 16762/* ------------------------------ */ 16763 .balign 64 16764.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 16765/* File: armv5te/ALT_STUB.S */ 16766/* 16767 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16768 * any interesting requests and then jump to the real instruction 16769 * handler. Note that the call to dvmCheckInst is done as a tail call. 16770 */ 16771 adrl lr, dvmAsmInstructionStart + (258 * 64) 16772 mov r0, rPC @ arg0 16773 mov r1, rSELF @ arg1 16774 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16775 16776/* ------------------------------ */ 16777 .balign 64 16778.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 16779/* File: armv5te/ALT_STUB.S */ 16780/* 16781 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16782 * any interesting requests and then jump to the real instruction 16783 * handler. Note that the call to dvmCheckInst is done as a tail call. 16784 */ 16785 adrl lr, dvmAsmInstructionStart + (259 * 64) 16786 mov r0, rPC @ arg0 16787 mov r1, rSELF @ arg1 16788 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16789 16790/* ------------------------------ */ 16791 .balign 64 16792.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 16793/* File: armv5te/ALT_STUB.S */ 16794/* 16795 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16796 * any interesting requests and then jump to the real instruction 16797 * handler. Note that the call to dvmCheckInst is done as a tail call. 16798 */ 16799 adrl lr, dvmAsmInstructionStart + (260 * 64) 16800 mov r0, rPC @ arg0 16801 mov r1, rSELF @ arg1 16802 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16803 16804/* ------------------------------ */ 16805 .balign 64 16806.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 16807/* File: armv5te/ALT_STUB.S */ 16808/* 16809 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16810 * any interesting requests and then jump to the real instruction 16811 * handler. Note that the call to dvmCheckInst is done as a tail call. 16812 */ 16813 adrl lr, dvmAsmInstructionStart + (261 * 64) 16814 mov r0, rPC @ arg0 16815 mov r1, rSELF @ arg1 16816 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16817 16818/* ------------------------------ */ 16819 .balign 64 16820.L_ALT_OP_IGET_JUMBO: /* 0x106 */ 16821/* File: armv5te/ALT_STUB.S */ 16822/* 16823 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16824 * any interesting requests and then jump to the real instruction 16825 * handler. Note that the call to dvmCheckInst is done as a tail call. 16826 */ 16827 adrl lr, dvmAsmInstructionStart + (262 * 64) 16828 mov r0, rPC @ arg0 16829 mov r1, rSELF @ arg1 16830 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16831 16832/* ------------------------------ */ 16833 .balign 64 16834.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */ 16835/* File: armv5te/ALT_STUB.S */ 16836/* 16837 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16838 * any interesting requests and then jump to the real instruction 16839 * handler. Note that the call to dvmCheckInst is done as a tail call. 16840 */ 16841 adrl lr, dvmAsmInstructionStart + (263 * 64) 16842 mov r0, rPC @ arg0 16843 mov r1, rSELF @ arg1 16844 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16845 16846/* ------------------------------ */ 16847 .balign 64 16848.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 16849/* File: armv5te/ALT_STUB.S */ 16850/* 16851 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16852 * any interesting requests and then jump to the real instruction 16853 * handler. Note that the call to dvmCheckInst is done as a tail call. 16854 */ 16855 adrl lr, dvmAsmInstructionStart + (264 * 64) 16856 mov r0, rPC @ arg0 16857 mov r1, rSELF @ arg1 16858 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16859 16860/* ------------------------------ */ 16861 .balign 64 16862.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 16863/* File: armv5te/ALT_STUB.S */ 16864/* 16865 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16866 * any interesting requests and then jump to the real instruction 16867 * handler. Note that the call to dvmCheckInst is done as a tail call. 16868 */ 16869 adrl lr, dvmAsmInstructionStart + (265 * 64) 16870 mov r0, rPC @ arg0 16871 mov r1, rSELF @ arg1 16872 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16873 16874/* ------------------------------ */ 16875 .balign 64 16876.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */ 16877/* File: armv5te/ALT_STUB.S */ 16878/* 16879 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16880 * any interesting requests and then jump to the real instruction 16881 * handler. Note that the call to dvmCheckInst is done as a tail call. 16882 */ 16883 adrl lr, dvmAsmInstructionStart + (266 * 64) 16884 mov r0, rPC @ arg0 16885 mov r1, rSELF @ arg1 16886 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16887 16888/* ------------------------------ */ 16889 .balign 64 16890.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */ 16891/* File: armv5te/ALT_STUB.S */ 16892/* 16893 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16894 * any interesting requests and then jump to the real instruction 16895 * handler. Note that the call to dvmCheckInst is done as a tail call. 16896 */ 16897 adrl lr, dvmAsmInstructionStart + (267 * 64) 16898 mov r0, rPC @ arg0 16899 mov r1, rSELF @ arg1 16900 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16901 16902/* ------------------------------ */ 16903 .balign 64 16904.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */ 16905/* File: armv5te/ALT_STUB.S */ 16906/* 16907 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16908 * any interesting requests and then jump to the real instruction 16909 * handler. Note that the call to dvmCheckInst is done as a tail call. 16910 */ 16911 adrl lr, dvmAsmInstructionStart + (268 * 64) 16912 mov r0, rPC @ arg0 16913 mov r1, rSELF @ arg1 16914 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16915 16916/* ------------------------------ */ 16917 .balign 64 16918.L_ALT_OP_IPUT_JUMBO: /* 0x10d */ 16919/* File: armv5te/ALT_STUB.S */ 16920/* 16921 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16922 * any interesting requests and then jump to the real instruction 16923 * handler. Note that the call to dvmCheckInst is done as a tail call. 16924 */ 16925 adrl lr, dvmAsmInstructionStart + (269 * 64) 16926 mov r0, rPC @ arg0 16927 mov r1, rSELF @ arg1 16928 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16929 16930/* ------------------------------ */ 16931 .balign 64 16932.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 16933/* File: armv5te/ALT_STUB.S */ 16934/* 16935 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16936 * any interesting requests and then jump to the real instruction 16937 * handler. Note that the call to dvmCheckInst is done as a tail call. 16938 */ 16939 adrl lr, dvmAsmInstructionStart + (270 * 64) 16940 mov r0, rPC @ arg0 16941 mov r1, rSELF @ arg1 16942 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16943 16944/* ------------------------------ */ 16945 .balign 64 16946.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 16947/* File: armv5te/ALT_STUB.S */ 16948/* 16949 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16950 * any interesting requests and then jump to the real instruction 16951 * handler. Note that the call to dvmCheckInst is done as a tail call. 16952 */ 16953 adrl lr, dvmAsmInstructionStart + (271 * 64) 16954 mov r0, rPC @ arg0 16955 mov r1, rSELF @ arg1 16956 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16957 16958/* ------------------------------ */ 16959 .balign 64 16960.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 16961/* File: armv5te/ALT_STUB.S */ 16962/* 16963 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16964 * any interesting requests and then jump to the real instruction 16965 * handler. Note that the call to dvmCheckInst is done as a tail call. 16966 */ 16967 adrl lr, dvmAsmInstructionStart + (272 * 64) 16968 mov r0, rPC @ arg0 16969 mov r1, rSELF @ arg1 16970 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16971 16972/* ------------------------------ */ 16973 .balign 64 16974.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 16975/* File: armv5te/ALT_STUB.S */ 16976/* 16977 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16978 * any interesting requests and then jump to the real instruction 16979 * handler. Note that the call to dvmCheckInst is done as a tail call. 16980 */ 16981 adrl lr, dvmAsmInstructionStart + (273 * 64) 16982 mov r0, rPC @ arg0 16983 mov r1, rSELF @ arg1 16984 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16985 16986/* ------------------------------ */ 16987 .balign 64 16988.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 16989/* File: armv5te/ALT_STUB.S */ 16990/* 16991 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16992 * any interesting requests and then jump to the real instruction 16993 * handler. Note that the call to dvmCheckInst is done as a tail call. 16994 */ 16995 adrl lr, dvmAsmInstructionStart + (274 * 64) 16996 mov r0, rPC @ arg0 16997 mov r1, rSELF @ arg1 16998 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16999 17000/* ------------------------------ */ 17001 .balign 64 17002.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 17003/* File: armv5te/ALT_STUB.S */ 17004/* 17005 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17006 * any interesting requests and then jump to the real instruction 17007 * handler. Note that the call to dvmCheckInst is done as a tail call. 17008 */ 17009 adrl lr, dvmAsmInstructionStart + (275 * 64) 17010 mov r0, rPC @ arg0 17011 mov r1, rSELF @ arg1 17012 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17013 17014/* ------------------------------ */ 17015 .balign 64 17016.L_ALT_OP_SGET_JUMBO: /* 0x114 */ 17017/* File: armv5te/ALT_STUB.S */ 17018/* 17019 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17020 * any interesting requests and then jump to the real instruction 17021 * handler. Note that the call to dvmCheckInst is done as a tail call. 17022 */ 17023 adrl lr, dvmAsmInstructionStart + (276 * 64) 17024 mov r0, rPC @ arg0 17025 mov r1, rSELF @ arg1 17026 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17027 17028/* ------------------------------ */ 17029 .balign 64 17030.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */ 17031/* File: armv5te/ALT_STUB.S */ 17032/* 17033 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17034 * any interesting requests and then jump to the real instruction 17035 * handler. Note that the call to dvmCheckInst is done as a tail call. 17036 */ 17037 adrl lr, dvmAsmInstructionStart + (277 * 64) 17038 mov r0, rPC @ arg0 17039 mov r1, rSELF @ arg1 17040 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17041 17042/* ------------------------------ */ 17043 .balign 64 17044.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 17045/* File: armv5te/ALT_STUB.S */ 17046/* 17047 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17048 * any interesting requests and then jump to the real instruction 17049 * handler. Note that the call to dvmCheckInst is done as a tail call. 17050 */ 17051 adrl lr, dvmAsmInstructionStart + (278 * 64) 17052 mov r0, rPC @ arg0 17053 mov r1, rSELF @ arg1 17054 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17055 17056/* ------------------------------ */ 17057 .balign 64 17058.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 17059/* File: armv5te/ALT_STUB.S */ 17060/* 17061 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17062 * any interesting requests and then jump to the real instruction 17063 * handler. Note that the call to dvmCheckInst is done as a tail call. 17064 */ 17065 adrl lr, dvmAsmInstructionStart + (279 * 64) 17066 mov r0, rPC @ arg0 17067 mov r1, rSELF @ arg1 17068 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17069 17070/* ------------------------------ */ 17071 .balign 64 17072.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */ 17073/* File: armv5te/ALT_STUB.S */ 17074/* 17075 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17076 * any interesting requests and then jump to the real instruction 17077 * handler. Note that the call to dvmCheckInst is done as a tail call. 17078 */ 17079 adrl lr, dvmAsmInstructionStart + (280 * 64) 17080 mov r0, rPC @ arg0 17081 mov r1, rSELF @ arg1 17082 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17083 17084/* ------------------------------ */ 17085 .balign 64 17086.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */ 17087/* File: armv5te/ALT_STUB.S */ 17088/* 17089 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17090 * any interesting requests and then jump to the real instruction 17091 * handler. Note that the call to dvmCheckInst is done as a tail call. 17092 */ 17093 adrl lr, dvmAsmInstructionStart + (281 * 64) 17094 mov r0, rPC @ arg0 17095 mov r1, rSELF @ arg1 17096 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17097 17098/* ------------------------------ */ 17099 .balign 64 17100.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */ 17101/* File: armv5te/ALT_STUB.S */ 17102/* 17103 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17104 * any interesting requests and then jump to the real instruction 17105 * handler. Note that the call to dvmCheckInst is done as a tail call. 17106 */ 17107 adrl lr, dvmAsmInstructionStart + (282 * 64) 17108 mov r0, rPC @ arg0 17109 mov r1, rSELF @ arg1 17110 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17111 17112/* ------------------------------ */ 17113 .balign 64 17114.L_ALT_OP_SPUT_JUMBO: /* 0x11b */ 17115/* File: armv5te/ALT_STUB.S */ 17116/* 17117 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17118 * any interesting requests and then jump to the real instruction 17119 * handler. Note that the call to dvmCheckInst is done as a tail call. 17120 */ 17121 adrl lr, dvmAsmInstructionStart + (283 * 64) 17122 mov r0, rPC @ arg0 17123 mov r1, rSELF @ arg1 17124 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17125 17126/* ------------------------------ */ 17127 .balign 64 17128.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 17129/* File: armv5te/ALT_STUB.S */ 17130/* 17131 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17132 * any interesting requests and then jump to the real instruction 17133 * handler. Note that the call to dvmCheckInst is done as a tail call. 17134 */ 17135 adrl lr, dvmAsmInstructionStart + (284 * 64) 17136 mov r0, rPC @ arg0 17137 mov r1, rSELF @ arg1 17138 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17139 17140/* ------------------------------ */ 17141 .balign 64 17142.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 17143/* File: armv5te/ALT_STUB.S */ 17144/* 17145 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17146 * any interesting requests and then jump to the real instruction 17147 * handler. Note that the call to dvmCheckInst is done as a tail call. 17148 */ 17149 adrl lr, dvmAsmInstructionStart + (285 * 64) 17150 mov r0, rPC @ arg0 17151 mov r1, rSELF @ arg1 17152 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17153 17154/* ------------------------------ */ 17155 .balign 64 17156.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 17157/* File: armv5te/ALT_STUB.S */ 17158/* 17159 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17160 * any interesting requests and then jump to the real instruction 17161 * handler. Note that the call to dvmCheckInst is done as a tail call. 17162 */ 17163 adrl lr, dvmAsmInstructionStart + (286 * 64) 17164 mov r0, rPC @ arg0 17165 mov r1, rSELF @ arg1 17166 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17167 17168/* ------------------------------ */ 17169 .balign 64 17170.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 17171/* File: armv5te/ALT_STUB.S */ 17172/* 17173 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17174 * any interesting requests and then jump to the real instruction 17175 * handler. Note that the call to dvmCheckInst is done as a tail call. 17176 */ 17177 adrl lr, dvmAsmInstructionStart + (287 * 64) 17178 mov r0, rPC @ arg0 17179 mov r1, rSELF @ arg1 17180 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17181 17182/* ------------------------------ */ 17183 .balign 64 17184.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 17185/* File: armv5te/ALT_STUB.S */ 17186/* 17187 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17188 * any interesting requests and then jump to the real instruction 17189 * handler. Note that the call to dvmCheckInst is done as a tail call. 17190 */ 17191 adrl lr, dvmAsmInstructionStart + (288 * 64) 17192 mov r0, rPC @ arg0 17193 mov r1, rSELF @ arg1 17194 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17195 17196/* ------------------------------ */ 17197 .balign 64 17198.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 17199/* File: armv5te/ALT_STUB.S */ 17200/* 17201 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17202 * any interesting requests and then jump to the real instruction 17203 * handler. Note that the call to dvmCheckInst is done as a tail call. 17204 */ 17205 adrl lr, dvmAsmInstructionStart + (289 * 64) 17206 mov r0, rPC @ arg0 17207 mov r1, rSELF @ arg1 17208 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17209 17210/* ------------------------------ */ 17211 .balign 64 17212.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 17213/* File: armv5te/ALT_STUB.S */ 17214/* 17215 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17216 * any interesting requests and then jump to the real instruction 17217 * handler. Note that the call to dvmCheckInst is done as a tail call. 17218 */ 17219 adrl lr, dvmAsmInstructionStart + (290 * 64) 17220 mov r0, rPC @ arg0 17221 mov r1, rSELF @ arg1 17222 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17223 17224/* ------------------------------ */ 17225 .balign 64 17226.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 17227/* File: armv5te/ALT_STUB.S */ 17228/* 17229 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17230 * any interesting requests and then jump to the real instruction 17231 * handler. Note that the call to dvmCheckInst is done as a tail call. 17232 */ 17233 adrl lr, dvmAsmInstructionStart + (291 * 64) 17234 mov r0, rPC @ arg0 17235 mov r1, rSELF @ arg1 17236 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17237 17238/* ------------------------------ */ 17239 .balign 64 17240.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 17241/* File: armv5te/ALT_STUB.S */ 17242/* 17243 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17244 * any interesting requests and then jump to the real instruction 17245 * handler. Note that the call to dvmCheckInst is done as a tail call. 17246 */ 17247 adrl lr, dvmAsmInstructionStart + (292 * 64) 17248 mov r0, rPC @ arg0 17249 mov r1, rSELF @ arg1 17250 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17251 17252/* ------------------------------ */ 17253 .balign 64 17254.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 17255/* File: armv5te/ALT_STUB.S */ 17256/* 17257 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17258 * any interesting requests and then jump to the real instruction 17259 * handler. Note that the call to dvmCheckInst is done as a tail call. 17260 */ 17261 adrl lr, dvmAsmInstructionStart + (293 * 64) 17262 mov r0, rPC @ arg0 17263 mov r1, rSELF @ arg1 17264 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17265 17266/* ------------------------------ */ 17267 .balign 64 17268.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 17269/* File: armv5te/ALT_STUB.S */ 17270/* 17271 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17272 * any interesting requests and then jump to the real instruction 17273 * handler. Note that the call to dvmCheckInst is done as a tail call. 17274 */ 17275 adrl lr, dvmAsmInstructionStart + (294 * 64) 17276 mov r0, rPC @ arg0 17277 mov r1, rSELF @ arg1 17278 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17279 17280/* ------------------------------ */ 17281 .balign 64 17282.L_ALT_OP_UNUSED_27FF: /* 0x127 */ 17283/* File: armv5te/ALT_STUB.S */ 17284/* 17285 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17286 * any interesting requests and then jump to the real instruction 17287 * handler. Note that the call to dvmCheckInst is done as a tail call. 17288 */ 17289 adrl lr, dvmAsmInstructionStart + (295 * 64) 17290 mov r0, rPC @ arg0 17291 mov r1, rSELF @ arg1 17292 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17293 17294/* ------------------------------ */ 17295 .balign 64 17296.L_ALT_OP_UNUSED_28FF: /* 0x128 */ 17297/* File: armv5te/ALT_STUB.S */ 17298/* 17299 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17300 * any interesting requests and then jump to the real instruction 17301 * handler. Note that the call to dvmCheckInst is done as a tail call. 17302 */ 17303 adrl lr, dvmAsmInstructionStart + (296 * 64) 17304 mov r0, rPC @ arg0 17305 mov r1, rSELF @ arg1 17306 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17307 17308/* ------------------------------ */ 17309 .balign 64 17310.L_ALT_OP_UNUSED_29FF: /* 0x129 */ 17311/* File: armv5te/ALT_STUB.S */ 17312/* 17313 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17314 * any interesting requests and then jump to the real instruction 17315 * handler. Note that the call to dvmCheckInst is done as a tail call. 17316 */ 17317 adrl lr, dvmAsmInstructionStart + (297 * 64) 17318 mov r0, rPC @ arg0 17319 mov r1, rSELF @ arg1 17320 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17321 17322/* ------------------------------ */ 17323 .balign 64 17324.L_ALT_OP_UNUSED_2AFF: /* 0x12a */ 17325/* File: armv5te/ALT_STUB.S */ 17326/* 17327 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17328 * any interesting requests and then jump to the real instruction 17329 * handler. Note that the call to dvmCheckInst is done as a tail call. 17330 */ 17331 adrl lr, dvmAsmInstructionStart + (298 * 64) 17332 mov r0, rPC @ arg0 17333 mov r1, rSELF @ arg1 17334 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17335 17336/* ------------------------------ */ 17337 .balign 64 17338.L_ALT_OP_UNUSED_2BFF: /* 0x12b */ 17339/* File: armv5te/ALT_STUB.S */ 17340/* 17341 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17342 * any interesting requests and then jump to the real instruction 17343 * handler. Note that the call to dvmCheckInst is done as a tail call. 17344 */ 17345 adrl lr, dvmAsmInstructionStart + (299 * 64) 17346 mov r0, rPC @ arg0 17347 mov r1, rSELF @ arg1 17348 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17349 17350/* ------------------------------ */ 17351 .balign 64 17352.L_ALT_OP_UNUSED_2CFF: /* 0x12c */ 17353/* File: armv5te/ALT_STUB.S */ 17354/* 17355 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17356 * any interesting requests and then jump to the real instruction 17357 * handler. Note that the call to dvmCheckInst is done as a tail call. 17358 */ 17359 adrl lr, dvmAsmInstructionStart + (300 * 64) 17360 mov r0, rPC @ arg0 17361 mov r1, rSELF @ arg1 17362 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17363 17364/* ------------------------------ */ 17365 .balign 64 17366.L_ALT_OP_UNUSED_2DFF: /* 0x12d */ 17367/* File: armv5te/ALT_STUB.S */ 17368/* 17369 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17370 * any interesting requests and then jump to the real instruction 17371 * handler. Note that the call to dvmCheckInst is done as a tail call. 17372 */ 17373 adrl lr, dvmAsmInstructionStart + (301 * 64) 17374 mov r0, rPC @ arg0 17375 mov r1, rSELF @ arg1 17376 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17377 17378/* ------------------------------ */ 17379 .balign 64 17380.L_ALT_OP_UNUSED_2EFF: /* 0x12e */ 17381/* File: armv5te/ALT_STUB.S */ 17382/* 17383 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17384 * any interesting requests and then jump to the real instruction 17385 * handler. Note that the call to dvmCheckInst is done as a tail call. 17386 */ 17387 adrl lr, dvmAsmInstructionStart + (302 * 64) 17388 mov r0, rPC @ arg0 17389 mov r1, rSELF @ arg1 17390 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17391 17392/* ------------------------------ */ 17393 .balign 64 17394.L_ALT_OP_UNUSED_2FFF: /* 0x12f */ 17395/* File: armv5te/ALT_STUB.S */ 17396/* 17397 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17398 * any interesting requests and then jump to the real instruction 17399 * handler. Note that the call to dvmCheckInst is done as a tail call. 17400 */ 17401 adrl lr, dvmAsmInstructionStart + (303 * 64) 17402 mov r0, rPC @ arg0 17403 mov r1, rSELF @ arg1 17404 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17405 17406/* ------------------------------ */ 17407 .balign 64 17408.L_ALT_OP_UNUSED_30FF: /* 0x130 */ 17409/* File: armv5te/ALT_STUB.S */ 17410/* 17411 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17412 * any interesting requests and then jump to the real instruction 17413 * handler. Note that the call to dvmCheckInst is done as a tail call. 17414 */ 17415 adrl lr, dvmAsmInstructionStart + (304 * 64) 17416 mov r0, rPC @ arg0 17417 mov r1, rSELF @ arg1 17418 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17419 17420/* ------------------------------ */ 17421 .balign 64 17422.L_ALT_OP_UNUSED_31FF: /* 0x131 */ 17423/* File: armv5te/ALT_STUB.S */ 17424/* 17425 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17426 * any interesting requests and then jump to the real instruction 17427 * handler. Note that the call to dvmCheckInst is done as a tail call. 17428 */ 17429 adrl lr, dvmAsmInstructionStart + (305 * 64) 17430 mov r0, rPC @ arg0 17431 mov r1, rSELF @ arg1 17432 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17433 17434/* ------------------------------ */ 17435 .balign 64 17436.L_ALT_OP_UNUSED_32FF: /* 0x132 */ 17437/* File: armv5te/ALT_STUB.S */ 17438/* 17439 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17440 * any interesting requests and then jump to the real instruction 17441 * handler. Note that the call to dvmCheckInst is done as a tail call. 17442 */ 17443 adrl lr, dvmAsmInstructionStart + (306 * 64) 17444 mov r0, rPC @ arg0 17445 mov r1, rSELF @ arg1 17446 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17447 17448/* ------------------------------ */ 17449 .balign 64 17450.L_ALT_OP_UNUSED_33FF: /* 0x133 */ 17451/* File: armv5te/ALT_STUB.S */ 17452/* 17453 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17454 * any interesting requests and then jump to the real instruction 17455 * handler. Note that the call to dvmCheckInst is done as a tail call. 17456 */ 17457 adrl lr, dvmAsmInstructionStart + (307 * 64) 17458 mov r0, rPC @ arg0 17459 mov r1, rSELF @ arg1 17460 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17461 17462/* ------------------------------ */ 17463 .balign 64 17464.L_ALT_OP_UNUSED_34FF: /* 0x134 */ 17465/* File: armv5te/ALT_STUB.S */ 17466/* 17467 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17468 * any interesting requests and then jump to the real instruction 17469 * handler. Note that the call to dvmCheckInst is done as a tail call. 17470 */ 17471 adrl lr, dvmAsmInstructionStart + (308 * 64) 17472 mov r0, rPC @ arg0 17473 mov r1, rSELF @ arg1 17474 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17475 17476/* ------------------------------ */ 17477 .balign 64 17478.L_ALT_OP_UNUSED_35FF: /* 0x135 */ 17479/* File: armv5te/ALT_STUB.S */ 17480/* 17481 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17482 * any interesting requests and then jump to the real instruction 17483 * handler. Note that the call to dvmCheckInst is done as a tail call. 17484 */ 17485 adrl lr, dvmAsmInstructionStart + (309 * 64) 17486 mov r0, rPC @ arg0 17487 mov r1, rSELF @ arg1 17488 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17489 17490/* ------------------------------ */ 17491 .balign 64 17492.L_ALT_OP_UNUSED_36FF: /* 0x136 */ 17493/* File: armv5te/ALT_STUB.S */ 17494/* 17495 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17496 * any interesting requests and then jump to the real instruction 17497 * handler. Note that the call to dvmCheckInst is done as a tail call. 17498 */ 17499 adrl lr, dvmAsmInstructionStart + (310 * 64) 17500 mov r0, rPC @ arg0 17501 mov r1, rSELF @ arg1 17502 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17503 17504/* ------------------------------ */ 17505 .balign 64 17506.L_ALT_OP_UNUSED_37FF: /* 0x137 */ 17507/* File: armv5te/ALT_STUB.S */ 17508/* 17509 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17510 * any interesting requests and then jump to the real instruction 17511 * handler. Note that the call to dvmCheckInst is done as a tail call. 17512 */ 17513 adrl lr, dvmAsmInstructionStart + (311 * 64) 17514 mov r0, rPC @ arg0 17515 mov r1, rSELF @ arg1 17516 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17517 17518/* ------------------------------ */ 17519 .balign 64 17520.L_ALT_OP_UNUSED_38FF: /* 0x138 */ 17521/* File: armv5te/ALT_STUB.S */ 17522/* 17523 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17524 * any interesting requests and then jump to the real instruction 17525 * handler. Note that the call to dvmCheckInst is done as a tail call. 17526 */ 17527 adrl lr, dvmAsmInstructionStart + (312 * 64) 17528 mov r0, rPC @ arg0 17529 mov r1, rSELF @ arg1 17530 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17531 17532/* ------------------------------ */ 17533 .balign 64 17534.L_ALT_OP_UNUSED_39FF: /* 0x139 */ 17535/* File: armv5te/ALT_STUB.S */ 17536/* 17537 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17538 * any interesting requests and then jump to the real instruction 17539 * handler. Note that the call to dvmCheckInst is done as a tail call. 17540 */ 17541 adrl lr, dvmAsmInstructionStart + (313 * 64) 17542 mov r0, rPC @ arg0 17543 mov r1, rSELF @ arg1 17544 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17545 17546/* ------------------------------ */ 17547 .balign 64 17548.L_ALT_OP_UNUSED_3AFF: /* 0x13a */ 17549/* File: armv5te/ALT_STUB.S */ 17550/* 17551 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17552 * any interesting requests and then jump to the real instruction 17553 * handler. Note that the call to dvmCheckInst is done as a tail call. 17554 */ 17555 adrl lr, dvmAsmInstructionStart + (314 * 64) 17556 mov r0, rPC @ arg0 17557 mov r1, rSELF @ arg1 17558 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17559 17560/* ------------------------------ */ 17561 .balign 64 17562.L_ALT_OP_UNUSED_3BFF: /* 0x13b */ 17563/* File: armv5te/ALT_STUB.S */ 17564/* 17565 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17566 * any interesting requests and then jump to the real instruction 17567 * handler. Note that the call to dvmCheckInst is done as a tail call. 17568 */ 17569 adrl lr, dvmAsmInstructionStart + (315 * 64) 17570 mov r0, rPC @ arg0 17571 mov r1, rSELF @ arg1 17572 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17573 17574/* ------------------------------ */ 17575 .balign 64 17576.L_ALT_OP_UNUSED_3CFF: /* 0x13c */ 17577/* File: armv5te/ALT_STUB.S */ 17578/* 17579 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17580 * any interesting requests and then jump to the real instruction 17581 * handler. Note that the call to dvmCheckInst is done as a tail call. 17582 */ 17583 adrl lr, dvmAsmInstructionStart + (316 * 64) 17584 mov r0, rPC @ arg0 17585 mov r1, rSELF @ arg1 17586 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17587 17588/* ------------------------------ */ 17589 .balign 64 17590.L_ALT_OP_UNUSED_3DFF: /* 0x13d */ 17591/* File: armv5te/ALT_STUB.S */ 17592/* 17593 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17594 * any interesting requests and then jump to the real instruction 17595 * handler. Note that the call to dvmCheckInst is done as a tail call. 17596 */ 17597 adrl lr, dvmAsmInstructionStart + (317 * 64) 17598 mov r0, rPC @ arg0 17599 mov r1, rSELF @ arg1 17600 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17601 17602/* ------------------------------ */ 17603 .balign 64 17604.L_ALT_OP_UNUSED_3EFF: /* 0x13e */ 17605/* File: armv5te/ALT_STUB.S */ 17606/* 17607 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17608 * any interesting requests and then jump to the real instruction 17609 * handler. Note that the call to dvmCheckInst is done as a tail call. 17610 */ 17611 adrl lr, dvmAsmInstructionStart + (318 * 64) 17612 mov r0, rPC @ arg0 17613 mov r1, rSELF @ arg1 17614 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17615 17616/* ------------------------------ */ 17617 .balign 64 17618.L_ALT_OP_UNUSED_3FFF: /* 0x13f */ 17619/* File: armv5te/ALT_STUB.S */ 17620/* 17621 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17622 * any interesting requests and then jump to the real instruction 17623 * handler. Note that the call to dvmCheckInst is done as a tail call. 17624 */ 17625 adrl lr, dvmAsmInstructionStart + (319 * 64) 17626 mov r0, rPC @ arg0 17627 mov r1, rSELF @ arg1 17628 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17629 17630/* ------------------------------ */ 17631 .balign 64 17632.L_ALT_OP_UNUSED_40FF: /* 0x140 */ 17633/* File: armv5te/ALT_STUB.S */ 17634/* 17635 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17636 * any interesting requests and then jump to the real instruction 17637 * handler. Note that the call to dvmCheckInst is done as a tail call. 17638 */ 17639 adrl lr, dvmAsmInstructionStart + (320 * 64) 17640 mov r0, rPC @ arg0 17641 mov r1, rSELF @ arg1 17642 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17643 17644/* ------------------------------ */ 17645 .balign 64 17646.L_ALT_OP_UNUSED_41FF: /* 0x141 */ 17647/* File: armv5te/ALT_STUB.S */ 17648/* 17649 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17650 * any interesting requests and then jump to the real instruction 17651 * handler. Note that the call to dvmCheckInst is done as a tail call. 17652 */ 17653 adrl lr, dvmAsmInstructionStart + (321 * 64) 17654 mov r0, rPC @ arg0 17655 mov r1, rSELF @ arg1 17656 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17657 17658/* ------------------------------ */ 17659 .balign 64 17660.L_ALT_OP_UNUSED_42FF: /* 0x142 */ 17661/* File: armv5te/ALT_STUB.S */ 17662/* 17663 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17664 * any interesting requests and then jump to the real instruction 17665 * handler. Note that the call to dvmCheckInst is done as a tail call. 17666 */ 17667 adrl lr, dvmAsmInstructionStart + (322 * 64) 17668 mov r0, rPC @ arg0 17669 mov r1, rSELF @ arg1 17670 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17671 17672/* ------------------------------ */ 17673 .balign 64 17674.L_ALT_OP_UNUSED_43FF: /* 0x143 */ 17675/* File: armv5te/ALT_STUB.S */ 17676/* 17677 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17678 * any interesting requests and then jump to the real instruction 17679 * handler. Note that the call to dvmCheckInst is done as a tail call. 17680 */ 17681 adrl lr, dvmAsmInstructionStart + (323 * 64) 17682 mov r0, rPC @ arg0 17683 mov r1, rSELF @ arg1 17684 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17685 17686/* ------------------------------ */ 17687 .balign 64 17688.L_ALT_OP_UNUSED_44FF: /* 0x144 */ 17689/* File: armv5te/ALT_STUB.S */ 17690/* 17691 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17692 * any interesting requests and then jump to the real instruction 17693 * handler. Note that the call to dvmCheckInst is done as a tail call. 17694 */ 17695 adrl lr, dvmAsmInstructionStart + (324 * 64) 17696 mov r0, rPC @ arg0 17697 mov r1, rSELF @ arg1 17698 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17699 17700/* ------------------------------ */ 17701 .balign 64 17702.L_ALT_OP_UNUSED_45FF: /* 0x145 */ 17703/* File: armv5te/ALT_STUB.S */ 17704/* 17705 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17706 * any interesting requests and then jump to the real instruction 17707 * handler. Note that the call to dvmCheckInst is done as a tail call. 17708 */ 17709 adrl lr, dvmAsmInstructionStart + (325 * 64) 17710 mov r0, rPC @ arg0 17711 mov r1, rSELF @ arg1 17712 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17713 17714/* ------------------------------ */ 17715 .balign 64 17716.L_ALT_OP_UNUSED_46FF: /* 0x146 */ 17717/* File: armv5te/ALT_STUB.S */ 17718/* 17719 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17720 * any interesting requests and then jump to the real instruction 17721 * handler. Note that the call to dvmCheckInst is done as a tail call. 17722 */ 17723 adrl lr, dvmAsmInstructionStart + (326 * 64) 17724 mov r0, rPC @ arg0 17725 mov r1, rSELF @ arg1 17726 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17727 17728/* ------------------------------ */ 17729 .balign 64 17730.L_ALT_OP_UNUSED_47FF: /* 0x147 */ 17731/* File: armv5te/ALT_STUB.S */ 17732/* 17733 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17734 * any interesting requests and then jump to the real instruction 17735 * handler. Note that the call to dvmCheckInst is done as a tail call. 17736 */ 17737 adrl lr, dvmAsmInstructionStart + (327 * 64) 17738 mov r0, rPC @ arg0 17739 mov r1, rSELF @ arg1 17740 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17741 17742/* ------------------------------ */ 17743 .balign 64 17744.L_ALT_OP_UNUSED_48FF: /* 0x148 */ 17745/* File: armv5te/ALT_STUB.S */ 17746/* 17747 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17748 * any interesting requests and then jump to the real instruction 17749 * handler. Note that the call to dvmCheckInst is done as a tail call. 17750 */ 17751 adrl lr, dvmAsmInstructionStart + (328 * 64) 17752 mov r0, rPC @ arg0 17753 mov r1, rSELF @ arg1 17754 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17755 17756/* ------------------------------ */ 17757 .balign 64 17758.L_ALT_OP_UNUSED_49FF: /* 0x149 */ 17759/* File: armv5te/ALT_STUB.S */ 17760/* 17761 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17762 * any interesting requests and then jump to the real instruction 17763 * handler. Note that the call to dvmCheckInst is done as a tail call. 17764 */ 17765 adrl lr, dvmAsmInstructionStart + (329 * 64) 17766 mov r0, rPC @ arg0 17767 mov r1, rSELF @ arg1 17768 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17769 17770/* ------------------------------ */ 17771 .balign 64 17772.L_ALT_OP_UNUSED_4AFF: /* 0x14a */ 17773/* File: armv5te/ALT_STUB.S */ 17774/* 17775 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17776 * any interesting requests and then jump to the real instruction 17777 * handler. Note that the call to dvmCheckInst is done as a tail call. 17778 */ 17779 adrl lr, dvmAsmInstructionStart + (330 * 64) 17780 mov r0, rPC @ arg0 17781 mov r1, rSELF @ arg1 17782 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17783 17784/* ------------------------------ */ 17785 .balign 64 17786.L_ALT_OP_UNUSED_4BFF: /* 0x14b */ 17787/* File: armv5te/ALT_STUB.S */ 17788/* 17789 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17790 * any interesting requests and then jump to the real instruction 17791 * handler. Note that the call to dvmCheckInst is done as a tail call. 17792 */ 17793 adrl lr, dvmAsmInstructionStart + (331 * 64) 17794 mov r0, rPC @ arg0 17795 mov r1, rSELF @ arg1 17796 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17797 17798/* ------------------------------ */ 17799 .balign 64 17800.L_ALT_OP_UNUSED_4CFF: /* 0x14c */ 17801/* File: armv5te/ALT_STUB.S */ 17802/* 17803 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17804 * any interesting requests and then jump to the real instruction 17805 * handler. Note that the call to dvmCheckInst is done as a tail call. 17806 */ 17807 adrl lr, dvmAsmInstructionStart + (332 * 64) 17808 mov r0, rPC @ arg0 17809 mov r1, rSELF @ arg1 17810 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17811 17812/* ------------------------------ */ 17813 .balign 64 17814.L_ALT_OP_UNUSED_4DFF: /* 0x14d */ 17815/* File: armv5te/ALT_STUB.S */ 17816/* 17817 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17818 * any interesting requests and then jump to the real instruction 17819 * handler. Note that the call to dvmCheckInst is done as a tail call. 17820 */ 17821 adrl lr, dvmAsmInstructionStart + (333 * 64) 17822 mov r0, rPC @ arg0 17823 mov r1, rSELF @ arg1 17824 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17825 17826/* ------------------------------ */ 17827 .balign 64 17828.L_ALT_OP_UNUSED_4EFF: /* 0x14e */ 17829/* File: armv5te/ALT_STUB.S */ 17830/* 17831 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17832 * any interesting requests and then jump to the real instruction 17833 * handler. Note that the call to dvmCheckInst is done as a tail call. 17834 */ 17835 adrl lr, dvmAsmInstructionStart + (334 * 64) 17836 mov r0, rPC @ arg0 17837 mov r1, rSELF @ arg1 17838 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17839 17840/* ------------------------------ */ 17841 .balign 64 17842.L_ALT_OP_UNUSED_4FFF: /* 0x14f */ 17843/* File: armv5te/ALT_STUB.S */ 17844/* 17845 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17846 * any interesting requests and then jump to the real instruction 17847 * handler. Note that the call to dvmCheckInst is done as a tail call. 17848 */ 17849 adrl lr, dvmAsmInstructionStart + (335 * 64) 17850 mov r0, rPC @ arg0 17851 mov r1, rSELF @ arg1 17852 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17853 17854/* ------------------------------ */ 17855 .balign 64 17856.L_ALT_OP_UNUSED_50FF: /* 0x150 */ 17857/* File: armv5te/ALT_STUB.S */ 17858/* 17859 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17860 * any interesting requests and then jump to the real instruction 17861 * handler. Note that the call to dvmCheckInst is done as a tail call. 17862 */ 17863 adrl lr, dvmAsmInstructionStart + (336 * 64) 17864 mov r0, rPC @ arg0 17865 mov r1, rSELF @ arg1 17866 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17867 17868/* ------------------------------ */ 17869 .balign 64 17870.L_ALT_OP_UNUSED_51FF: /* 0x151 */ 17871/* File: armv5te/ALT_STUB.S */ 17872/* 17873 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17874 * any interesting requests and then jump to the real instruction 17875 * handler. Note that the call to dvmCheckInst is done as a tail call. 17876 */ 17877 adrl lr, dvmAsmInstructionStart + (337 * 64) 17878 mov r0, rPC @ arg0 17879 mov r1, rSELF @ arg1 17880 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17881 17882/* ------------------------------ */ 17883 .balign 64 17884.L_ALT_OP_UNUSED_52FF: /* 0x152 */ 17885/* File: armv5te/ALT_STUB.S */ 17886/* 17887 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17888 * any interesting requests and then jump to the real instruction 17889 * handler. Note that the call to dvmCheckInst is done as a tail call. 17890 */ 17891 adrl lr, dvmAsmInstructionStart + (338 * 64) 17892 mov r0, rPC @ arg0 17893 mov r1, rSELF @ arg1 17894 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17895 17896/* ------------------------------ */ 17897 .balign 64 17898.L_ALT_OP_UNUSED_53FF: /* 0x153 */ 17899/* File: armv5te/ALT_STUB.S */ 17900/* 17901 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17902 * any interesting requests and then jump to the real instruction 17903 * handler. Note that the call to dvmCheckInst is done as a tail call. 17904 */ 17905 adrl lr, dvmAsmInstructionStart + (339 * 64) 17906 mov r0, rPC @ arg0 17907 mov r1, rSELF @ arg1 17908 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17909 17910/* ------------------------------ */ 17911 .balign 64 17912.L_ALT_OP_UNUSED_54FF: /* 0x154 */ 17913/* File: armv5te/ALT_STUB.S */ 17914/* 17915 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17916 * any interesting requests and then jump to the real instruction 17917 * handler. Note that the call to dvmCheckInst is done as a tail call. 17918 */ 17919 adrl lr, dvmAsmInstructionStart + (340 * 64) 17920 mov r0, rPC @ arg0 17921 mov r1, rSELF @ arg1 17922 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17923 17924/* ------------------------------ */ 17925 .balign 64 17926.L_ALT_OP_UNUSED_55FF: /* 0x155 */ 17927/* File: armv5te/ALT_STUB.S */ 17928/* 17929 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17930 * any interesting requests and then jump to the real instruction 17931 * handler. Note that the call to dvmCheckInst is done as a tail call. 17932 */ 17933 adrl lr, dvmAsmInstructionStart + (341 * 64) 17934 mov r0, rPC @ arg0 17935 mov r1, rSELF @ arg1 17936 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17937 17938/* ------------------------------ */ 17939 .balign 64 17940.L_ALT_OP_UNUSED_56FF: /* 0x156 */ 17941/* File: armv5te/ALT_STUB.S */ 17942/* 17943 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17944 * any interesting requests and then jump to the real instruction 17945 * handler. Note that the call to dvmCheckInst is done as a tail call. 17946 */ 17947 adrl lr, dvmAsmInstructionStart + (342 * 64) 17948 mov r0, rPC @ arg0 17949 mov r1, rSELF @ arg1 17950 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17951 17952/* ------------------------------ */ 17953 .balign 64 17954.L_ALT_OP_UNUSED_57FF: /* 0x157 */ 17955/* File: armv5te/ALT_STUB.S */ 17956/* 17957 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17958 * any interesting requests and then jump to the real instruction 17959 * handler. Note that the call to dvmCheckInst is done as a tail call. 17960 */ 17961 adrl lr, dvmAsmInstructionStart + (343 * 64) 17962 mov r0, rPC @ arg0 17963 mov r1, rSELF @ arg1 17964 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17965 17966/* ------------------------------ */ 17967 .balign 64 17968.L_ALT_OP_UNUSED_58FF: /* 0x158 */ 17969/* File: armv5te/ALT_STUB.S */ 17970/* 17971 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17972 * any interesting requests and then jump to the real instruction 17973 * handler. Note that the call to dvmCheckInst is done as a tail call. 17974 */ 17975 adrl lr, dvmAsmInstructionStart + (344 * 64) 17976 mov r0, rPC @ arg0 17977 mov r1, rSELF @ arg1 17978 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17979 17980/* ------------------------------ */ 17981 .balign 64 17982.L_ALT_OP_UNUSED_59FF: /* 0x159 */ 17983/* File: armv5te/ALT_STUB.S */ 17984/* 17985 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17986 * any interesting requests and then jump to the real instruction 17987 * handler. Note that the call to dvmCheckInst is done as a tail call. 17988 */ 17989 adrl lr, dvmAsmInstructionStart + (345 * 64) 17990 mov r0, rPC @ arg0 17991 mov r1, rSELF @ arg1 17992 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17993 17994/* ------------------------------ */ 17995 .balign 64 17996.L_ALT_OP_UNUSED_5AFF: /* 0x15a */ 17997/* File: armv5te/ALT_STUB.S */ 17998/* 17999 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18000 * any interesting requests and then jump to the real instruction 18001 * handler. Note that the call to dvmCheckInst is done as a tail call. 18002 */ 18003 adrl lr, dvmAsmInstructionStart + (346 * 64) 18004 mov r0, rPC @ arg0 18005 mov r1, rSELF @ arg1 18006 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18007 18008/* ------------------------------ */ 18009 .balign 64 18010.L_ALT_OP_UNUSED_5BFF: /* 0x15b */ 18011/* File: armv5te/ALT_STUB.S */ 18012/* 18013 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18014 * any interesting requests and then jump to the real instruction 18015 * handler. Note that the call to dvmCheckInst is done as a tail call. 18016 */ 18017 adrl lr, dvmAsmInstructionStart + (347 * 64) 18018 mov r0, rPC @ arg0 18019 mov r1, rSELF @ arg1 18020 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18021 18022/* ------------------------------ */ 18023 .balign 64 18024.L_ALT_OP_UNUSED_5CFF: /* 0x15c */ 18025/* File: armv5te/ALT_STUB.S */ 18026/* 18027 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18028 * any interesting requests and then jump to the real instruction 18029 * handler. Note that the call to dvmCheckInst is done as a tail call. 18030 */ 18031 adrl lr, dvmAsmInstructionStart + (348 * 64) 18032 mov r0, rPC @ arg0 18033 mov r1, rSELF @ arg1 18034 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18035 18036/* ------------------------------ */ 18037 .balign 64 18038.L_ALT_OP_UNUSED_5DFF: /* 0x15d */ 18039/* File: armv5te/ALT_STUB.S */ 18040/* 18041 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18042 * any interesting requests and then jump to the real instruction 18043 * handler. Note that the call to dvmCheckInst is done as a tail call. 18044 */ 18045 adrl lr, dvmAsmInstructionStart + (349 * 64) 18046 mov r0, rPC @ arg0 18047 mov r1, rSELF @ arg1 18048 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18049 18050/* ------------------------------ */ 18051 .balign 64 18052.L_ALT_OP_UNUSED_5EFF: /* 0x15e */ 18053/* File: armv5te/ALT_STUB.S */ 18054/* 18055 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18056 * any interesting requests and then jump to the real instruction 18057 * handler. Note that the call to dvmCheckInst is done as a tail call. 18058 */ 18059 adrl lr, dvmAsmInstructionStart + (350 * 64) 18060 mov r0, rPC @ arg0 18061 mov r1, rSELF @ arg1 18062 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18063 18064/* ------------------------------ */ 18065 .balign 64 18066.L_ALT_OP_UNUSED_5FFF: /* 0x15f */ 18067/* File: armv5te/ALT_STUB.S */ 18068/* 18069 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18070 * any interesting requests and then jump to the real instruction 18071 * handler. Note that the call to dvmCheckInst is done as a tail call. 18072 */ 18073 adrl lr, dvmAsmInstructionStart + (351 * 64) 18074 mov r0, rPC @ arg0 18075 mov r1, rSELF @ arg1 18076 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18077 18078/* ------------------------------ */ 18079 .balign 64 18080.L_ALT_OP_UNUSED_60FF: /* 0x160 */ 18081/* File: armv5te/ALT_STUB.S */ 18082/* 18083 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18084 * any interesting requests and then jump to the real instruction 18085 * handler. Note that the call to dvmCheckInst is done as a tail call. 18086 */ 18087 adrl lr, dvmAsmInstructionStart + (352 * 64) 18088 mov r0, rPC @ arg0 18089 mov r1, rSELF @ arg1 18090 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18091 18092/* ------------------------------ */ 18093 .balign 64 18094.L_ALT_OP_UNUSED_61FF: /* 0x161 */ 18095/* File: armv5te/ALT_STUB.S */ 18096/* 18097 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18098 * any interesting requests and then jump to the real instruction 18099 * handler. Note that the call to dvmCheckInst is done as a tail call. 18100 */ 18101 adrl lr, dvmAsmInstructionStart + (353 * 64) 18102 mov r0, rPC @ arg0 18103 mov r1, rSELF @ arg1 18104 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18105 18106/* ------------------------------ */ 18107 .balign 64 18108.L_ALT_OP_UNUSED_62FF: /* 0x162 */ 18109/* File: armv5te/ALT_STUB.S */ 18110/* 18111 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18112 * any interesting requests and then jump to the real instruction 18113 * handler. Note that the call to dvmCheckInst is done as a tail call. 18114 */ 18115 adrl lr, dvmAsmInstructionStart + (354 * 64) 18116 mov r0, rPC @ arg0 18117 mov r1, rSELF @ arg1 18118 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18119 18120/* ------------------------------ */ 18121 .balign 64 18122.L_ALT_OP_UNUSED_63FF: /* 0x163 */ 18123/* File: armv5te/ALT_STUB.S */ 18124/* 18125 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18126 * any interesting requests and then jump to the real instruction 18127 * handler. Note that the call to dvmCheckInst is done as a tail call. 18128 */ 18129 adrl lr, dvmAsmInstructionStart + (355 * 64) 18130 mov r0, rPC @ arg0 18131 mov r1, rSELF @ arg1 18132 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18133 18134/* ------------------------------ */ 18135 .balign 64 18136.L_ALT_OP_UNUSED_64FF: /* 0x164 */ 18137/* File: armv5te/ALT_STUB.S */ 18138/* 18139 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18140 * any interesting requests and then jump to the real instruction 18141 * handler. Note that the call to dvmCheckInst is done as a tail call. 18142 */ 18143 adrl lr, dvmAsmInstructionStart + (356 * 64) 18144 mov r0, rPC @ arg0 18145 mov r1, rSELF @ arg1 18146 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18147 18148/* ------------------------------ */ 18149 .balign 64 18150.L_ALT_OP_UNUSED_65FF: /* 0x165 */ 18151/* File: armv5te/ALT_STUB.S */ 18152/* 18153 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18154 * any interesting requests and then jump to the real instruction 18155 * handler. Note that the call to dvmCheckInst is done as a tail call. 18156 */ 18157 adrl lr, dvmAsmInstructionStart + (357 * 64) 18158 mov r0, rPC @ arg0 18159 mov r1, rSELF @ arg1 18160 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18161 18162/* ------------------------------ */ 18163 .balign 64 18164.L_ALT_OP_UNUSED_66FF: /* 0x166 */ 18165/* File: armv5te/ALT_STUB.S */ 18166/* 18167 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18168 * any interesting requests and then jump to the real instruction 18169 * handler. Note that the call to dvmCheckInst is done as a tail call. 18170 */ 18171 adrl lr, dvmAsmInstructionStart + (358 * 64) 18172 mov r0, rPC @ arg0 18173 mov r1, rSELF @ arg1 18174 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18175 18176/* ------------------------------ */ 18177 .balign 64 18178.L_ALT_OP_UNUSED_67FF: /* 0x167 */ 18179/* File: armv5te/ALT_STUB.S */ 18180/* 18181 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18182 * any interesting requests and then jump to the real instruction 18183 * handler. Note that the call to dvmCheckInst is done as a tail call. 18184 */ 18185 adrl lr, dvmAsmInstructionStart + (359 * 64) 18186 mov r0, rPC @ arg0 18187 mov r1, rSELF @ arg1 18188 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18189 18190/* ------------------------------ */ 18191 .balign 64 18192.L_ALT_OP_UNUSED_68FF: /* 0x168 */ 18193/* File: armv5te/ALT_STUB.S */ 18194/* 18195 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18196 * any interesting requests and then jump to the real instruction 18197 * handler. Note that the call to dvmCheckInst is done as a tail call. 18198 */ 18199 adrl lr, dvmAsmInstructionStart + (360 * 64) 18200 mov r0, rPC @ arg0 18201 mov r1, rSELF @ arg1 18202 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18203 18204/* ------------------------------ */ 18205 .balign 64 18206.L_ALT_OP_UNUSED_69FF: /* 0x169 */ 18207/* File: armv5te/ALT_STUB.S */ 18208/* 18209 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18210 * any interesting requests and then jump to the real instruction 18211 * handler. Note that the call to dvmCheckInst is done as a tail call. 18212 */ 18213 adrl lr, dvmAsmInstructionStart + (361 * 64) 18214 mov r0, rPC @ arg0 18215 mov r1, rSELF @ arg1 18216 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18217 18218/* ------------------------------ */ 18219 .balign 64 18220.L_ALT_OP_UNUSED_6AFF: /* 0x16a */ 18221/* File: armv5te/ALT_STUB.S */ 18222/* 18223 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18224 * any interesting requests and then jump to the real instruction 18225 * handler. Note that the call to dvmCheckInst is done as a tail call. 18226 */ 18227 adrl lr, dvmAsmInstructionStart + (362 * 64) 18228 mov r0, rPC @ arg0 18229 mov r1, rSELF @ arg1 18230 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18231 18232/* ------------------------------ */ 18233 .balign 64 18234.L_ALT_OP_UNUSED_6BFF: /* 0x16b */ 18235/* File: armv5te/ALT_STUB.S */ 18236/* 18237 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18238 * any interesting requests and then jump to the real instruction 18239 * handler. Note that the call to dvmCheckInst is done as a tail call. 18240 */ 18241 adrl lr, dvmAsmInstructionStart + (363 * 64) 18242 mov r0, rPC @ arg0 18243 mov r1, rSELF @ arg1 18244 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18245 18246/* ------------------------------ */ 18247 .balign 64 18248.L_ALT_OP_UNUSED_6CFF: /* 0x16c */ 18249/* File: armv5te/ALT_STUB.S */ 18250/* 18251 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18252 * any interesting requests and then jump to the real instruction 18253 * handler. Note that the call to dvmCheckInst is done as a tail call. 18254 */ 18255 adrl lr, dvmAsmInstructionStart + (364 * 64) 18256 mov r0, rPC @ arg0 18257 mov r1, rSELF @ arg1 18258 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18259 18260/* ------------------------------ */ 18261 .balign 64 18262.L_ALT_OP_UNUSED_6DFF: /* 0x16d */ 18263/* File: armv5te/ALT_STUB.S */ 18264/* 18265 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18266 * any interesting requests and then jump to the real instruction 18267 * handler. Note that the call to dvmCheckInst is done as a tail call. 18268 */ 18269 adrl lr, dvmAsmInstructionStart + (365 * 64) 18270 mov r0, rPC @ arg0 18271 mov r1, rSELF @ arg1 18272 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18273 18274/* ------------------------------ */ 18275 .balign 64 18276.L_ALT_OP_UNUSED_6EFF: /* 0x16e */ 18277/* File: armv5te/ALT_STUB.S */ 18278/* 18279 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18280 * any interesting requests and then jump to the real instruction 18281 * handler. Note that the call to dvmCheckInst is done as a tail call. 18282 */ 18283 adrl lr, dvmAsmInstructionStart + (366 * 64) 18284 mov r0, rPC @ arg0 18285 mov r1, rSELF @ arg1 18286 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18287 18288/* ------------------------------ */ 18289 .balign 64 18290.L_ALT_OP_UNUSED_6FFF: /* 0x16f */ 18291/* File: armv5te/ALT_STUB.S */ 18292/* 18293 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18294 * any interesting requests and then jump to the real instruction 18295 * handler. Note that the call to dvmCheckInst is done as a tail call. 18296 */ 18297 adrl lr, dvmAsmInstructionStart + (367 * 64) 18298 mov r0, rPC @ arg0 18299 mov r1, rSELF @ arg1 18300 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18301 18302/* ------------------------------ */ 18303 .balign 64 18304.L_ALT_OP_UNUSED_70FF: /* 0x170 */ 18305/* File: armv5te/ALT_STUB.S */ 18306/* 18307 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18308 * any interesting requests and then jump to the real instruction 18309 * handler. Note that the call to dvmCheckInst is done as a tail call. 18310 */ 18311 adrl lr, dvmAsmInstructionStart + (368 * 64) 18312 mov r0, rPC @ arg0 18313 mov r1, rSELF @ arg1 18314 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18315 18316/* ------------------------------ */ 18317 .balign 64 18318.L_ALT_OP_UNUSED_71FF: /* 0x171 */ 18319/* File: armv5te/ALT_STUB.S */ 18320/* 18321 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18322 * any interesting requests and then jump to the real instruction 18323 * handler. Note that the call to dvmCheckInst is done as a tail call. 18324 */ 18325 adrl lr, dvmAsmInstructionStart + (369 * 64) 18326 mov r0, rPC @ arg0 18327 mov r1, rSELF @ arg1 18328 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18329 18330/* ------------------------------ */ 18331 .balign 64 18332.L_ALT_OP_UNUSED_72FF: /* 0x172 */ 18333/* File: armv5te/ALT_STUB.S */ 18334/* 18335 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18336 * any interesting requests and then jump to the real instruction 18337 * handler. Note that the call to dvmCheckInst is done as a tail call. 18338 */ 18339 adrl lr, dvmAsmInstructionStart + (370 * 64) 18340 mov r0, rPC @ arg0 18341 mov r1, rSELF @ arg1 18342 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18343 18344/* ------------------------------ */ 18345 .balign 64 18346.L_ALT_OP_UNUSED_73FF: /* 0x173 */ 18347/* File: armv5te/ALT_STUB.S */ 18348/* 18349 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18350 * any interesting requests and then jump to the real instruction 18351 * handler. Note that the call to dvmCheckInst is done as a tail call. 18352 */ 18353 adrl lr, dvmAsmInstructionStart + (371 * 64) 18354 mov r0, rPC @ arg0 18355 mov r1, rSELF @ arg1 18356 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18357 18358/* ------------------------------ */ 18359 .balign 64 18360.L_ALT_OP_UNUSED_74FF: /* 0x174 */ 18361/* File: armv5te/ALT_STUB.S */ 18362/* 18363 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18364 * any interesting requests and then jump to the real instruction 18365 * handler. Note that the call to dvmCheckInst is done as a tail call. 18366 */ 18367 adrl lr, dvmAsmInstructionStart + (372 * 64) 18368 mov r0, rPC @ arg0 18369 mov r1, rSELF @ arg1 18370 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18371 18372/* ------------------------------ */ 18373 .balign 64 18374.L_ALT_OP_UNUSED_75FF: /* 0x175 */ 18375/* File: armv5te/ALT_STUB.S */ 18376/* 18377 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18378 * any interesting requests and then jump to the real instruction 18379 * handler. Note that the call to dvmCheckInst is done as a tail call. 18380 */ 18381 adrl lr, dvmAsmInstructionStart + (373 * 64) 18382 mov r0, rPC @ arg0 18383 mov r1, rSELF @ arg1 18384 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18385 18386/* ------------------------------ */ 18387 .balign 64 18388.L_ALT_OP_UNUSED_76FF: /* 0x176 */ 18389/* File: armv5te/ALT_STUB.S */ 18390/* 18391 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18392 * any interesting requests and then jump to the real instruction 18393 * handler. Note that the call to dvmCheckInst is done as a tail call. 18394 */ 18395 adrl lr, dvmAsmInstructionStart + (374 * 64) 18396 mov r0, rPC @ arg0 18397 mov r1, rSELF @ arg1 18398 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18399 18400/* ------------------------------ */ 18401 .balign 64 18402.L_ALT_OP_UNUSED_77FF: /* 0x177 */ 18403/* File: armv5te/ALT_STUB.S */ 18404/* 18405 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18406 * any interesting requests and then jump to the real instruction 18407 * handler. Note that the call to dvmCheckInst is done as a tail call. 18408 */ 18409 adrl lr, dvmAsmInstructionStart + (375 * 64) 18410 mov r0, rPC @ arg0 18411 mov r1, rSELF @ arg1 18412 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18413 18414/* ------------------------------ */ 18415 .balign 64 18416.L_ALT_OP_UNUSED_78FF: /* 0x178 */ 18417/* File: armv5te/ALT_STUB.S */ 18418/* 18419 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18420 * any interesting requests and then jump to the real instruction 18421 * handler. Note that the call to dvmCheckInst is done as a tail call. 18422 */ 18423 adrl lr, dvmAsmInstructionStart + (376 * 64) 18424 mov r0, rPC @ arg0 18425 mov r1, rSELF @ arg1 18426 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18427 18428/* ------------------------------ */ 18429 .balign 64 18430.L_ALT_OP_UNUSED_79FF: /* 0x179 */ 18431/* File: armv5te/ALT_STUB.S */ 18432/* 18433 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18434 * any interesting requests and then jump to the real instruction 18435 * handler. Note that the call to dvmCheckInst is done as a tail call. 18436 */ 18437 adrl lr, dvmAsmInstructionStart + (377 * 64) 18438 mov r0, rPC @ arg0 18439 mov r1, rSELF @ arg1 18440 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18441 18442/* ------------------------------ */ 18443 .balign 64 18444.L_ALT_OP_UNUSED_7AFF: /* 0x17a */ 18445/* File: armv5te/ALT_STUB.S */ 18446/* 18447 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18448 * any interesting requests and then jump to the real instruction 18449 * handler. Note that the call to dvmCheckInst is done as a tail call. 18450 */ 18451 adrl lr, dvmAsmInstructionStart + (378 * 64) 18452 mov r0, rPC @ arg0 18453 mov r1, rSELF @ arg1 18454 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18455 18456/* ------------------------------ */ 18457 .balign 64 18458.L_ALT_OP_UNUSED_7BFF: /* 0x17b */ 18459/* File: armv5te/ALT_STUB.S */ 18460/* 18461 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18462 * any interesting requests and then jump to the real instruction 18463 * handler. Note that the call to dvmCheckInst is done as a tail call. 18464 */ 18465 adrl lr, dvmAsmInstructionStart + (379 * 64) 18466 mov r0, rPC @ arg0 18467 mov r1, rSELF @ arg1 18468 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18469 18470/* ------------------------------ */ 18471 .balign 64 18472.L_ALT_OP_UNUSED_7CFF: /* 0x17c */ 18473/* File: armv5te/ALT_STUB.S */ 18474/* 18475 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18476 * any interesting requests and then jump to the real instruction 18477 * handler. Note that the call to dvmCheckInst is done as a tail call. 18478 */ 18479 adrl lr, dvmAsmInstructionStart + (380 * 64) 18480 mov r0, rPC @ arg0 18481 mov r1, rSELF @ arg1 18482 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18483 18484/* ------------------------------ */ 18485 .balign 64 18486.L_ALT_OP_UNUSED_7DFF: /* 0x17d */ 18487/* File: armv5te/ALT_STUB.S */ 18488/* 18489 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18490 * any interesting requests and then jump to the real instruction 18491 * handler. Note that the call to dvmCheckInst is done as a tail call. 18492 */ 18493 adrl lr, dvmAsmInstructionStart + (381 * 64) 18494 mov r0, rPC @ arg0 18495 mov r1, rSELF @ arg1 18496 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18497 18498/* ------------------------------ */ 18499 .balign 64 18500.L_ALT_OP_UNUSED_7EFF: /* 0x17e */ 18501/* File: armv5te/ALT_STUB.S */ 18502/* 18503 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18504 * any interesting requests and then jump to the real instruction 18505 * handler. Note that the call to dvmCheckInst is done as a tail call. 18506 */ 18507 adrl lr, dvmAsmInstructionStart + (382 * 64) 18508 mov r0, rPC @ arg0 18509 mov r1, rSELF @ arg1 18510 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18511 18512/* ------------------------------ */ 18513 .balign 64 18514.L_ALT_OP_UNUSED_7FFF: /* 0x17f */ 18515/* File: armv5te/ALT_STUB.S */ 18516/* 18517 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18518 * any interesting requests and then jump to the real instruction 18519 * handler. Note that the call to dvmCheckInst is done as a tail call. 18520 */ 18521 adrl lr, dvmAsmInstructionStart + (383 * 64) 18522 mov r0, rPC @ arg0 18523 mov r1, rSELF @ arg1 18524 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18525 18526/* ------------------------------ */ 18527 .balign 64 18528.L_ALT_OP_UNUSED_80FF: /* 0x180 */ 18529/* File: armv5te/ALT_STUB.S */ 18530/* 18531 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18532 * any interesting requests and then jump to the real instruction 18533 * handler. Note that the call to dvmCheckInst is done as a tail call. 18534 */ 18535 adrl lr, dvmAsmInstructionStart + (384 * 64) 18536 mov r0, rPC @ arg0 18537 mov r1, rSELF @ arg1 18538 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18539 18540/* ------------------------------ */ 18541 .balign 64 18542.L_ALT_OP_UNUSED_81FF: /* 0x181 */ 18543/* File: armv5te/ALT_STUB.S */ 18544/* 18545 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18546 * any interesting requests and then jump to the real instruction 18547 * handler. Note that the call to dvmCheckInst is done as a tail call. 18548 */ 18549 adrl lr, dvmAsmInstructionStart + (385 * 64) 18550 mov r0, rPC @ arg0 18551 mov r1, rSELF @ arg1 18552 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18553 18554/* ------------------------------ */ 18555 .balign 64 18556.L_ALT_OP_UNUSED_82FF: /* 0x182 */ 18557/* File: armv5te/ALT_STUB.S */ 18558/* 18559 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18560 * any interesting requests and then jump to the real instruction 18561 * handler. Note that the call to dvmCheckInst is done as a tail call. 18562 */ 18563 adrl lr, dvmAsmInstructionStart + (386 * 64) 18564 mov r0, rPC @ arg0 18565 mov r1, rSELF @ arg1 18566 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18567 18568/* ------------------------------ */ 18569 .balign 64 18570.L_ALT_OP_UNUSED_83FF: /* 0x183 */ 18571/* File: armv5te/ALT_STUB.S */ 18572/* 18573 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18574 * any interesting requests and then jump to the real instruction 18575 * handler. Note that the call to dvmCheckInst is done as a tail call. 18576 */ 18577 adrl lr, dvmAsmInstructionStart + (387 * 64) 18578 mov r0, rPC @ arg0 18579 mov r1, rSELF @ arg1 18580 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18581 18582/* ------------------------------ */ 18583 .balign 64 18584.L_ALT_OP_UNUSED_84FF: /* 0x184 */ 18585/* File: armv5te/ALT_STUB.S */ 18586/* 18587 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18588 * any interesting requests and then jump to the real instruction 18589 * handler. Note that the call to dvmCheckInst is done as a tail call. 18590 */ 18591 adrl lr, dvmAsmInstructionStart + (388 * 64) 18592 mov r0, rPC @ arg0 18593 mov r1, rSELF @ arg1 18594 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18595 18596/* ------------------------------ */ 18597 .balign 64 18598.L_ALT_OP_UNUSED_85FF: /* 0x185 */ 18599/* File: armv5te/ALT_STUB.S */ 18600/* 18601 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18602 * any interesting requests and then jump to the real instruction 18603 * handler. Note that the call to dvmCheckInst is done as a tail call. 18604 */ 18605 adrl lr, dvmAsmInstructionStart + (389 * 64) 18606 mov r0, rPC @ arg0 18607 mov r1, rSELF @ arg1 18608 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18609 18610/* ------------------------------ */ 18611 .balign 64 18612.L_ALT_OP_UNUSED_86FF: /* 0x186 */ 18613/* File: armv5te/ALT_STUB.S */ 18614/* 18615 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18616 * any interesting requests and then jump to the real instruction 18617 * handler. Note that the call to dvmCheckInst is done as a tail call. 18618 */ 18619 adrl lr, dvmAsmInstructionStart + (390 * 64) 18620 mov r0, rPC @ arg0 18621 mov r1, rSELF @ arg1 18622 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18623 18624/* ------------------------------ */ 18625 .balign 64 18626.L_ALT_OP_UNUSED_87FF: /* 0x187 */ 18627/* File: armv5te/ALT_STUB.S */ 18628/* 18629 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18630 * any interesting requests and then jump to the real instruction 18631 * handler. Note that the call to dvmCheckInst is done as a tail call. 18632 */ 18633 adrl lr, dvmAsmInstructionStart + (391 * 64) 18634 mov r0, rPC @ arg0 18635 mov r1, rSELF @ arg1 18636 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18637 18638/* ------------------------------ */ 18639 .balign 64 18640.L_ALT_OP_UNUSED_88FF: /* 0x188 */ 18641/* File: armv5te/ALT_STUB.S */ 18642/* 18643 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18644 * any interesting requests and then jump to the real instruction 18645 * handler. Note that the call to dvmCheckInst is done as a tail call. 18646 */ 18647 adrl lr, dvmAsmInstructionStart + (392 * 64) 18648 mov r0, rPC @ arg0 18649 mov r1, rSELF @ arg1 18650 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18651 18652/* ------------------------------ */ 18653 .balign 64 18654.L_ALT_OP_UNUSED_89FF: /* 0x189 */ 18655/* File: armv5te/ALT_STUB.S */ 18656/* 18657 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18658 * any interesting requests and then jump to the real instruction 18659 * handler. Note that the call to dvmCheckInst is done as a tail call. 18660 */ 18661 adrl lr, dvmAsmInstructionStart + (393 * 64) 18662 mov r0, rPC @ arg0 18663 mov r1, rSELF @ arg1 18664 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18665 18666/* ------------------------------ */ 18667 .balign 64 18668.L_ALT_OP_UNUSED_8AFF: /* 0x18a */ 18669/* File: armv5te/ALT_STUB.S */ 18670/* 18671 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18672 * any interesting requests and then jump to the real instruction 18673 * handler. Note that the call to dvmCheckInst is done as a tail call. 18674 */ 18675 adrl lr, dvmAsmInstructionStart + (394 * 64) 18676 mov r0, rPC @ arg0 18677 mov r1, rSELF @ arg1 18678 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18679 18680/* ------------------------------ */ 18681 .balign 64 18682.L_ALT_OP_UNUSED_8BFF: /* 0x18b */ 18683/* File: armv5te/ALT_STUB.S */ 18684/* 18685 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18686 * any interesting requests and then jump to the real instruction 18687 * handler. Note that the call to dvmCheckInst is done as a tail call. 18688 */ 18689 adrl lr, dvmAsmInstructionStart + (395 * 64) 18690 mov r0, rPC @ arg0 18691 mov r1, rSELF @ arg1 18692 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18693 18694/* ------------------------------ */ 18695 .balign 64 18696.L_ALT_OP_UNUSED_8CFF: /* 0x18c */ 18697/* File: armv5te/ALT_STUB.S */ 18698/* 18699 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18700 * any interesting requests and then jump to the real instruction 18701 * handler. Note that the call to dvmCheckInst is done as a tail call. 18702 */ 18703 adrl lr, dvmAsmInstructionStart + (396 * 64) 18704 mov r0, rPC @ arg0 18705 mov r1, rSELF @ arg1 18706 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18707 18708/* ------------------------------ */ 18709 .balign 64 18710.L_ALT_OP_UNUSED_8DFF: /* 0x18d */ 18711/* File: armv5te/ALT_STUB.S */ 18712/* 18713 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18714 * any interesting requests and then jump to the real instruction 18715 * handler. Note that the call to dvmCheckInst is done as a tail call. 18716 */ 18717 adrl lr, dvmAsmInstructionStart + (397 * 64) 18718 mov r0, rPC @ arg0 18719 mov r1, rSELF @ arg1 18720 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18721 18722/* ------------------------------ */ 18723 .balign 64 18724.L_ALT_OP_UNUSED_8EFF: /* 0x18e */ 18725/* File: armv5te/ALT_STUB.S */ 18726/* 18727 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18728 * any interesting requests and then jump to the real instruction 18729 * handler. Note that the call to dvmCheckInst is done as a tail call. 18730 */ 18731 adrl lr, dvmAsmInstructionStart + (398 * 64) 18732 mov r0, rPC @ arg0 18733 mov r1, rSELF @ arg1 18734 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18735 18736/* ------------------------------ */ 18737 .balign 64 18738.L_ALT_OP_UNUSED_8FFF: /* 0x18f */ 18739/* File: armv5te/ALT_STUB.S */ 18740/* 18741 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18742 * any interesting requests and then jump to the real instruction 18743 * handler. Note that the call to dvmCheckInst is done as a tail call. 18744 */ 18745 adrl lr, dvmAsmInstructionStart + (399 * 64) 18746 mov r0, rPC @ arg0 18747 mov r1, rSELF @ arg1 18748 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18749 18750/* ------------------------------ */ 18751 .balign 64 18752.L_ALT_OP_UNUSED_90FF: /* 0x190 */ 18753/* File: armv5te/ALT_STUB.S */ 18754/* 18755 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18756 * any interesting requests and then jump to the real instruction 18757 * handler. Note that the call to dvmCheckInst is done as a tail call. 18758 */ 18759 adrl lr, dvmAsmInstructionStart + (400 * 64) 18760 mov r0, rPC @ arg0 18761 mov r1, rSELF @ arg1 18762 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18763 18764/* ------------------------------ */ 18765 .balign 64 18766.L_ALT_OP_UNUSED_91FF: /* 0x191 */ 18767/* File: armv5te/ALT_STUB.S */ 18768/* 18769 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18770 * any interesting requests and then jump to the real instruction 18771 * handler. Note that the call to dvmCheckInst is done as a tail call. 18772 */ 18773 adrl lr, dvmAsmInstructionStart + (401 * 64) 18774 mov r0, rPC @ arg0 18775 mov r1, rSELF @ arg1 18776 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18777 18778/* ------------------------------ */ 18779 .balign 64 18780.L_ALT_OP_UNUSED_92FF: /* 0x192 */ 18781/* File: armv5te/ALT_STUB.S */ 18782/* 18783 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18784 * any interesting requests and then jump to the real instruction 18785 * handler. Note that the call to dvmCheckInst is done as a tail call. 18786 */ 18787 adrl lr, dvmAsmInstructionStart + (402 * 64) 18788 mov r0, rPC @ arg0 18789 mov r1, rSELF @ arg1 18790 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18791 18792/* ------------------------------ */ 18793 .balign 64 18794.L_ALT_OP_UNUSED_93FF: /* 0x193 */ 18795/* File: armv5te/ALT_STUB.S */ 18796/* 18797 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18798 * any interesting requests and then jump to the real instruction 18799 * handler. Note that the call to dvmCheckInst is done as a tail call. 18800 */ 18801 adrl lr, dvmAsmInstructionStart + (403 * 64) 18802 mov r0, rPC @ arg0 18803 mov r1, rSELF @ arg1 18804 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18805 18806/* ------------------------------ */ 18807 .balign 64 18808.L_ALT_OP_UNUSED_94FF: /* 0x194 */ 18809/* File: armv5te/ALT_STUB.S */ 18810/* 18811 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18812 * any interesting requests and then jump to the real instruction 18813 * handler. Note that the call to dvmCheckInst is done as a tail call. 18814 */ 18815 adrl lr, dvmAsmInstructionStart + (404 * 64) 18816 mov r0, rPC @ arg0 18817 mov r1, rSELF @ arg1 18818 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18819 18820/* ------------------------------ */ 18821 .balign 64 18822.L_ALT_OP_UNUSED_95FF: /* 0x195 */ 18823/* File: armv5te/ALT_STUB.S */ 18824/* 18825 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18826 * any interesting requests and then jump to the real instruction 18827 * handler. Note that the call to dvmCheckInst is done as a tail call. 18828 */ 18829 adrl lr, dvmAsmInstructionStart + (405 * 64) 18830 mov r0, rPC @ arg0 18831 mov r1, rSELF @ arg1 18832 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18833 18834/* ------------------------------ */ 18835 .balign 64 18836.L_ALT_OP_UNUSED_96FF: /* 0x196 */ 18837/* File: armv5te/ALT_STUB.S */ 18838/* 18839 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18840 * any interesting requests and then jump to the real instruction 18841 * handler. Note that the call to dvmCheckInst is done as a tail call. 18842 */ 18843 adrl lr, dvmAsmInstructionStart + (406 * 64) 18844 mov r0, rPC @ arg0 18845 mov r1, rSELF @ arg1 18846 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18847 18848/* ------------------------------ */ 18849 .balign 64 18850.L_ALT_OP_UNUSED_97FF: /* 0x197 */ 18851/* File: armv5te/ALT_STUB.S */ 18852/* 18853 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18854 * any interesting requests and then jump to the real instruction 18855 * handler. Note that the call to dvmCheckInst is done as a tail call. 18856 */ 18857 adrl lr, dvmAsmInstructionStart + (407 * 64) 18858 mov r0, rPC @ arg0 18859 mov r1, rSELF @ arg1 18860 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18861 18862/* ------------------------------ */ 18863 .balign 64 18864.L_ALT_OP_UNUSED_98FF: /* 0x198 */ 18865/* File: armv5te/ALT_STUB.S */ 18866/* 18867 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18868 * any interesting requests and then jump to the real instruction 18869 * handler. Note that the call to dvmCheckInst is done as a tail call. 18870 */ 18871 adrl lr, dvmAsmInstructionStart + (408 * 64) 18872 mov r0, rPC @ arg0 18873 mov r1, rSELF @ arg1 18874 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18875 18876/* ------------------------------ */ 18877 .balign 64 18878.L_ALT_OP_UNUSED_99FF: /* 0x199 */ 18879/* File: armv5te/ALT_STUB.S */ 18880/* 18881 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18882 * any interesting requests and then jump to the real instruction 18883 * handler. Note that the call to dvmCheckInst is done as a tail call. 18884 */ 18885 adrl lr, dvmAsmInstructionStart + (409 * 64) 18886 mov r0, rPC @ arg0 18887 mov r1, rSELF @ arg1 18888 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18889 18890/* ------------------------------ */ 18891 .balign 64 18892.L_ALT_OP_UNUSED_9AFF: /* 0x19a */ 18893/* File: armv5te/ALT_STUB.S */ 18894/* 18895 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18896 * any interesting requests and then jump to the real instruction 18897 * handler. Note that the call to dvmCheckInst is done as a tail call. 18898 */ 18899 adrl lr, dvmAsmInstructionStart + (410 * 64) 18900 mov r0, rPC @ arg0 18901 mov r1, rSELF @ arg1 18902 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18903 18904/* ------------------------------ */ 18905 .balign 64 18906.L_ALT_OP_UNUSED_9BFF: /* 0x19b */ 18907/* File: armv5te/ALT_STUB.S */ 18908/* 18909 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18910 * any interesting requests and then jump to the real instruction 18911 * handler. Note that the call to dvmCheckInst is done as a tail call. 18912 */ 18913 adrl lr, dvmAsmInstructionStart + (411 * 64) 18914 mov r0, rPC @ arg0 18915 mov r1, rSELF @ arg1 18916 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18917 18918/* ------------------------------ */ 18919 .balign 64 18920.L_ALT_OP_UNUSED_9CFF: /* 0x19c */ 18921/* File: armv5te/ALT_STUB.S */ 18922/* 18923 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18924 * any interesting requests and then jump to the real instruction 18925 * handler. Note that the call to dvmCheckInst is done as a tail call. 18926 */ 18927 adrl lr, dvmAsmInstructionStart + (412 * 64) 18928 mov r0, rPC @ arg0 18929 mov r1, rSELF @ arg1 18930 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18931 18932/* ------------------------------ */ 18933 .balign 64 18934.L_ALT_OP_UNUSED_9DFF: /* 0x19d */ 18935/* File: armv5te/ALT_STUB.S */ 18936/* 18937 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18938 * any interesting requests and then jump to the real instruction 18939 * handler. Note that the call to dvmCheckInst is done as a tail call. 18940 */ 18941 adrl lr, dvmAsmInstructionStart + (413 * 64) 18942 mov r0, rPC @ arg0 18943 mov r1, rSELF @ arg1 18944 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18945 18946/* ------------------------------ */ 18947 .balign 64 18948.L_ALT_OP_UNUSED_9EFF: /* 0x19e */ 18949/* File: armv5te/ALT_STUB.S */ 18950/* 18951 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18952 * any interesting requests and then jump to the real instruction 18953 * handler. Note that the call to dvmCheckInst is done as a tail call. 18954 */ 18955 adrl lr, dvmAsmInstructionStart + (414 * 64) 18956 mov r0, rPC @ arg0 18957 mov r1, rSELF @ arg1 18958 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18959 18960/* ------------------------------ */ 18961 .balign 64 18962.L_ALT_OP_UNUSED_9FFF: /* 0x19f */ 18963/* File: armv5te/ALT_STUB.S */ 18964/* 18965 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18966 * any interesting requests and then jump to the real instruction 18967 * handler. Note that the call to dvmCheckInst is done as a tail call. 18968 */ 18969 adrl lr, dvmAsmInstructionStart + (415 * 64) 18970 mov r0, rPC @ arg0 18971 mov r1, rSELF @ arg1 18972 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18973 18974/* ------------------------------ */ 18975 .balign 64 18976.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */ 18977/* File: armv5te/ALT_STUB.S */ 18978/* 18979 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18980 * any interesting requests and then jump to the real instruction 18981 * handler. Note that the call to dvmCheckInst is done as a tail call. 18982 */ 18983 adrl lr, dvmAsmInstructionStart + (416 * 64) 18984 mov r0, rPC @ arg0 18985 mov r1, rSELF @ arg1 18986 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18987 18988/* ------------------------------ */ 18989 .balign 64 18990.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */ 18991/* File: armv5te/ALT_STUB.S */ 18992/* 18993 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18994 * any interesting requests and then jump to the real instruction 18995 * handler. Note that the call to dvmCheckInst is done as a tail call. 18996 */ 18997 adrl lr, dvmAsmInstructionStart + (417 * 64) 18998 mov r0, rPC @ arg0 18999 mov r1, rSELF @ arg1 19000 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19001 19002/* ------------------------------ */ 19003 .balign 64 19004.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */ 19005/* File: armv5te/ALT_STUB.S */ 19006/* 19007 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19008 * any interesting requests and then jump to the real instruction 19009 * handler. Note that the call to dvmCheckInst is done as a tail call. 19010 */ 19011 adrl lr, dvmAsmInstructionStart + (418 * 64) 19012 mov r0, rPC @ arg0 19013 mov r1, rSELF @ arg1 19014 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19015 19016/* ------------------------------ */ 19017 .balign 64 19018.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */ 19019/* File: armv5te/ALT_STUB.S */ 19020/* 19021 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19022 * any interesting requests and then jump to the real instruction 19023 * handler. Note that the call to dvmCheckInst is done as a tail call. 19024 */ 19025 adrl lr, dvmAsmInstructionStart + (419 * 64) 19026 mov r0, rPC @ arg0 19027 mov r1, rSELF @ arg1 19028 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19029 19030/* ------------------------------ */ 19031 .balign 64 19032.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */ 19033/* File: armv5te/ALT_STUB.S */ 19034/* 19035 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19036 * any interesting requests and then jump to the real instruction 19037 * handler. Note that the call to dvmCheckInst is done as a tail call. 19038 */ 19039 adrl lr, dvmAsmInstructionStart + (420 * 64) 19040 mov r0, rPC @ arg0 19041 mov r1, rSELF @ arg1 19042 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19043 19044/* ------------------------------ */ 19045 .balign 64 19046.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */ 19047/* File: armv5te/ALT_STUB.S */ 19048/* 19049 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19050 * any interesting requests and then jump to the real instruction 19051 * handler. Note that the call to dvmCheckInst is done as a tail call. 19052 */ 19053 adrl lr, dvmAsmInstructionStart + (421 * 64) 19054 mov r0, rPC @ arg0 19055 mov r1, rSELF @ arg1 19056 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19057 19058/* ------------------------------ */ 19059 .balign 64 19060.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */ 19061/* File: armv5te/ALT_STUB.S */ 19062/* 19063 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19064 * any interesting requests and then jump to the real instruction 19065 * handler. Note that the call to dvmCheckInst is done as a tail call. 19066 */ 19067 adrl lr, dvmAsmInstructionStart + (422 * 64) 19068 mov r0, rPC @ arg0 19069 mov r1, rSELF @ arg1 19070 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19071 19072/* ------------------------------ */ 19073 .balign 64 19074.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */ 19075/* File: armv5te/ALT_STUB.S */ 19076/* 19077 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19078 * any interesting requests and then jump to the real instruction 19079 * handler. Note that the call to dvmCheckInst is done as a tail call. 19080 */ 19081 adrl lr, dvmAsmInstructionStart + (423 * 64) 19082 mov r0, rPC @ arg0 19083 mov r1, rSELF @ arg1 19084 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19085 19086/* ------------------------------ */ 19087 .balign 64 19088.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */ 19089/* File: armv5te/ALT_STUB.S */ 19090/* 19091 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19092 * any interesting requests and then jump to the real instruction 19093 * handler. Note that the call to dvmCheckInst is done as a tail call. 19094 */ 19095 adrl lr, dvmAsmInstructionStart + (424 * 64) 19096 mov r0, rPC @ arg0 19097 mov r1, rSELF @ arg1 19098 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19099 19100/* ------------------------------ */ 19101 .balign 64 19102.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */ 19103/* File: armv5te/ALT_STUB.S */ 19104/* 19105 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19106 * any interesting requests and then jump to the real instruction 19107 * handler. Note that the call to dvmCheckInst is done as a tail call. 19108 */ 19109 adrl lr, dvmAsmInstructionStart + (425 * 64) 19110 mov r0, rPC @ arg0 19111 mov r1, rSELF @ arg1 19112 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19113 19114/* ------------------------------ */ 19115 .balign 64 19116.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */ 19117/* File: armv5te/ALT_STUB.S */ 19118/* 19119 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19120 * any interesting requests and then jump to the real instruction 19121 * handler. Note that the call to dvmCheckInst is done as a tail call. 19122 */ 19123 adrl lr, dvmAsmInstructionStart + (426 * 64) 19124 mov r0, rPC @ arg0 19125 mov r1, rSELF @ arg1 19126 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19127 19128/* ------------------------------ */ 19129 .balign 64 19130.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */ 19131/* File: armv5te/ALT_STUB.S */ 19132/* 19133 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19134 * any interesting requests and then jump to the real instruction 19135 * handler. Note that the call to dvmCheckInst is done as a tail call. 19136 */ 19137 adrl lr, dvmAsmInstructionStart + (427 * 64) 19138 mov r0, rPC @ arg0 19139 mov r1, rSELF @ arg1 19140 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19141 19142/* ------------------------------ */ 19143 .balign 64 19144.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */ 19145/* File: armv5te/ALT_STUB.S */ 19146/* 19147 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19148 * any interesting requests and then jump to the real instruction 19149 * handler. Note that the call to dvmCheckInst is done as a tail call. 19150 */ 19151 adrl lr, dvmAsmInstructionStart + (428 * 64) 19152 mov r0, rPC @ arg0 19153 mov r1, rSELF @ arg1 19154 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19155 19156/* ------------------------------ */ 19157 .balign 64 19158.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */ 19159/* File: armv5te/ALT_STUB.S */ 19160/* 19161 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19162 * any interesting requests and then jump to the real instruction 19163 * handler. Note that the call to dvmCheckInst is done as a tail call. 19164 */ 19165 adrl lr, dvmAsmInstructionStart + (429 * 64) 19166 mov r0, rPC @ arg0 19167 mov r1, rSELF @ arg1 19168 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19169 19170/* ------------------------------ */ 19171 .balign 64 19172.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */ 19173/* File: armv5te/ALT_STUB.S */ 19174/* 19175 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19176 * any interesting requests and then jump to the real instruction 19177 * handler. Note that the call to dvmCheckInst is done as a tail call. 19178 */ 19179 adrl lr, dvmAsmInstructionStart + (430 * 64) 19180 mov r0, rPC @ arg0 19181 mov r1, rSELF @ arg1 19182 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19183 19184/* ------------------------------ */ 19185 .balign 64 19186.L_ALT_OP_UNUSED_AFFF: /* 0x1af */ 19187/* File: armv5te/ALT_STUB.S */ 19188/* 19189 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19190 * any interesting requests and then jump to the real instruction 19191 * handler. Note that the call to dvmCheckInst is done as a tail call. 19192 */ 19193 adrl lr, dvmAsmInstructionStart + (431 * 64) 19194 mov r0, rPC @ arg0 19195 mov r1, rSELF @ arg1 19196 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19197 19198/* ------------------------------ */ 19199 .balign 64 19200.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */ 19201/* File: armv5te/ALT_STUB.S */ 19202/* 19203 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19204 * any interesting requests and then jump to the real instruction 19205 * handler. Note that the call to dvmCheckInst is done as a tail call. 19206 */ 19207 adrl lr, dvmAsmInstructionStart + (432 * 64) 19208 mov r0, rPC @ arg0 19209 mov r1, rSELF @ arg1 19210 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19211 19212/* ------------------------------ */ 19213 .balign 64 19214.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */ 19215/* File: armv5te/ALT_STUB.S */ 19216/* 19217 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19218 * any interesting requests and then jump to the real instruction 19219 * handler. Note that the call to dvmCheckInst is done as a tail call. 19220 */ 19221 adrl lr, dvmAsmInstructionStart + (433 * 64) 19222 mov r0, rPC @ arg0 19223 mov r1, rSELF @ arg1 19224 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19225 19226/* ------------------------------ */ 19227 .balign 64 19228.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */ 19229/* File: armv5te/ALT_STUB.S */ 19230/* 19231 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19232 * any interesting requests and then jump to the real instruction 19233 * handler. Note that the call to dvmCheckInst is done as a tail call. 19234 */ 19235 adrl lr, dvmAsmInstructionStart + (434 * 64) 19236 mov r0, rPC @ arg0 19237 mov r1, rSELF @ arg1 19238 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19239 19240/* ------------------------------ */ 19241 .balign 64 19242.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */ 19243/* File: armv5te/ALT_STUB.S */ 19244/* 19245 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19246 * any interesting requests and then jump to the real instruction 19247 * handler. Note that the call to dvmCheckInst is done as a tail call. 19248 */ 19249 adrl lr, dvmAsmInstructionStart + (435 * 64) 19250 mov r0, rPC @ arg0 19251 mov r1, rSELF @ arg1 19252 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19253 19254/* ------------------------------ */ 19255 .balign 64 19256.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */ 19257/* File: armv5te/ALT_STUB.S */ 19258/* 19259 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19260 * any interesting requests and then jump to the real instruction 19261 * handler. Note that the call to dvmCheckInst is done as a tail call. 19262 */ 19263 adrl lr, dvmAsmInstructionStart + (436 * 64) 19264 mov r0, rPC @ arg0 19265 mov r1, rSELF @ arg1 19266 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19267 19268/* ------------------------------ */ 19269 .balign 64 19270.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */ 19271/* File: armv5te/ALT_STUB.S */ 19272/* 19273 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19274 * any interesting requests and then jump to the real instruction 19275 * handler. Note that the call to dvmCheckInst is done as a tail call. 19276 */ 19277 adrl lr, dvmAsmInstructionStart + (437 * 64) 19278 mov r0, rPC @ arg0 19279 mov r1, rSELF @ arg1 19280 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19281 19282/* ------------------------------ */ 19283 .balign 64 19284.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */ 19285/* File: armv5te/ALT_STUB.S */ 19286/* 19287 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19288 * any interesting requests and then jump to the real instruction 19289 * handler. Note that the call to dvmCheckInst is done as a tail call. 19290 */ 19291 adrl lr, dvmAsmInstructionStart + (438 * 64) 19292 mov r0, rPC @ arg0 19293 mov r1, rSELF @ arg1 19294 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19295 19296/* ------------------------------ */ 19297 .balign 64 19298.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */ 19299/* File: armv5te/ALT_STUB.S */ 19300/* 19301 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19302 * any interesting requests and then jump to the real instruction 19303 * handler. Note that the call to dvmCheckInst is done as a tail call. 19304 */ 19305 adrl lr, dvmAsmInstructionStart + (439 * 64) 19306 mov r0, rPC @ arg0 19307 mov r1, rSELF @ arg1 19308 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19309 19310/* ------------------------------ */ 19311 .balign 64 19312.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */ 19313/* File: armv5te/ALT_STUB.S */ 19314/* 19315 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19316 * any interesting requests and then jump to the real instruction 19317 * handler. Note that the call to dvmCheckInst is done as a tail call. 19318 */ 19319 adrl lr, dvmAsmInstructionStart + (440 * 64) 19320 mov r0, rPC @ arg0 19321 mov r1, rSELF @ arg1 19322 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19323 19324/* ------------------------------ */ 19325 .balign 64 19326.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */ 19327/* File: armv5te/ALT_STUB.S */ 19328/* 19329 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19330 * any interesting requests and then jump to the real instruction 19331 * handler. Note that the call to dvmCheckInst is done as a tail call. 19332 */ 19333 adrl lr, dvmAsmInstructionStart + (441 * 64) 19334 mov r0, rPC @ arg0 19335 mov r1, rSELF @ arg1 19336 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19337 19338/* ------------------------------ */ 19339 .balign 64 19340.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */ 19341/* File: armv5te/ALT_STUB.S */ 19342/* 19343 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19344 * any interesting requests and then jump to the real instruction 19345 * handler. Note that the call to dvmCheckInst is done as a tail call. 19346 */ 19347 adrl lr, dvmAsmInstructionStart + (442 * 64) 19348 mov r0, rPC @ arg0 19349 mov r1, rSELF @ arg1 19350 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19351 19352/* ------------------------------ */ 19353 .balign 64 19354.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */ 19355/* File: armv5te/ALT_STUB.S */ 19356/* 19357 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19358 * any interesting requests and then jump to the real instruction 19359 * handler. Note that the call to dvmCheckInst is done as a tail call. 19360 */ 19361 adrl lr, dvmAsmInstructionStart + (443 * 64) 19362 mov r0, rPC @ arg0 19363 mov r1, rSELF @ arg1 19364 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19365 19366/* ------------------------------ */ 19367 .balign 64 19368.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */ 19369/* File: armv5te/ALT_STUB.S */ 19370/* 19371 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19372 * any interesting requests and then jump to the real instruction 19373 * handler. Note that the call to dvmCheckInst is done as a tail call. 19374 */ 19375 adrl lr, dvmAsmInstructionStart + (444 * 64) 19376 mov r0, rPC @ arg0 19377 mov r1, rSELF @ arg1 19378 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19379 19380/* ------------------------------ */ 19381 .balign 64 19382.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */ 19383/* File: armv5te/ALT_STUB.S */ 19384/* 19385 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19386 * any interesting requests and then jump to the real instruction 19387 * handler. Note that the call to dvmCheckInst is done as a tail call. 19388 */ 19389 adrl lr, dvmAsmInstructionStart + (445 * 64) 19390 mov r0, rPC @ arg0 19391 mov r1, rSELF @ arg1 19392 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19393 19394/* ------------------------------ */ 19395 .balign 64 19396.L_ALT_OP_UNUSED_BEFF: /* 0x1be */ 19397/* File: armv5te/ALT_STUB.S */ 19398/* 19399 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19400 * any interesting requests and then jump to the real instruction 19401 * handler. Note that the call to dvmCheckInst is done as a tail call. 19402 */ 19403 adrl lr, dvmAsmInstructionStart + (446 * 64) 19404 mov r0, rPC @ arg0 19405 mov r1, rSELF @ arg1 19406 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19407 19408/* ------------------------------ */ 19409 .balign 64 19410.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */ 19411/* File: armv5te/ALT_STUB.S */ 19412/* 19413 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19414 * any interesting requests and then jump to the real instruction 19415 * handler. Note that the call to dvmCheckInst is done as a tail call. 19416 */ 19417 adrl lr, dvmAsmInstructionStart + (447 * 64) 19418 mov r0, rPC @ arg0 19419 mov r1, rSELF @ arg1 19420 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19421 19422/* ------------------------------ */ 19423 .balign 64 19424.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */ 19425/* File: armv5te/ALT_STUB.S */ 19426/* 19427 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19428 * any interesting requests and then jump to the real instruction 19429 * handler. Note that the call to dvmCheckInst is done as a tail call. 19430 */ 19431 adrl lr, dvmAsmInstructionStart + (448 * 64) 19432 mov r0, rPC @ arg0 19433 mov r1, rSELF @ arg1 19434 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19435 19436/* ------------------------------ */ 19437 .balign 64 19438.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */ 19439/* File: armv5te/ALT_STUB.S */ 19440/* 19441 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19442 * any interesting requests and then jump to the real instruction 19443 * handler. Note that the call to dvmCheckInst is done as a tail call. 19444 */ 19445 adrl lr, dvmAsmInstructionStart + (449 * 64) 19446 mov r0, rPC @ arg0 19447 mov r1, rSELF @ arg1 19448 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19449 19450/* ------------------------------ */ 19451 .balign 64 19452.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */ 19453/* File: armv5te/ALT_STUB.S */ 19454/* 19455 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19456 * any interesting requests and then jump to the real instruction 19457 * handler. Note that the call to dvmCheckInst is done as a tail call. 19458 */ 19459 adrl lr, dvmAsmInstructionStart + (450 * 64) 19460 mov r0, rPC @ arg0 19461 mov r1, rSELF @ arg1 19462 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19463 19464/* ------------------------------ */ 19465 .balign 64 19466.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */ 19467/* File: armv5te/ALT_STUB.S */ 19468/* 19469 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19470 * any interesting requests and then jump to the real instruction 19471 * handler. Note that the call to dvmCheckInst is done as a tail call. 19472 */ 19473 adrl lr, dvmAsmInstructionStart + (451 * 64) 19474 mov r0, rPC @ arg0 19475 mov r1, rSELF @ arg1 19476 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19477 19478/* ------------------------------ */ 19479 .balign 64 19480.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */ 19481/* File: armv5te/ALT_STUB.S */ 19482/* 19483 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19484 * any interesting requests and then jump to the real instruction 19485 * handler. Note that the call to dvmCheckInst is done as a tail call. 19486 */ 19487 adrl lr, dvmAsmInstructionStart + (452 * 64) 19488 mov r0, rPC @ arg0 19489 mov r1, rSELF @ arg1 19490 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19491 19492/* ------------------------------ */ 19493 .balign 64 19494.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */ 19495/* File: armv5te/ALT_STUB.S */ 19496/* 19497 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19498 * any interesting requests and then jump to the real instruction 19499 * handler. Note that the call to dvmCheckInst is done as a tail call. 19500 */ 19501 adrl lr, dvmAsmInstructionStart + (453 * 64) 19502 mov r0, rPC @ arg0 19503 mov r1, rSELF @ arg1 19504 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19505 19506/* ------------------------------ */ 19507 .balign 64 19508.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */ 19509/* File: armv5te/ALT_STUB.S */ 19510/* 19511 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19512 * any interesting requests and then jump to the real instruction 19513 * handler. Note that the call to dvmCheckInst is done as a tail call. 19514 */ 19515 adrl lr, dvmAsmInstructionStart + (454 * 64) 19516 mov r0, rPC @ arg0 19517 mov r1, rSELF @ arg1 19518 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19519 19520/* ------------------------------ */ 19521 .balign 64 19522.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */ 19523/* File: armv5te/ALT_STUB.S */ 19524/* 19525 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19526 * any interesting requests and then jump to the real instruction 19527 * handler. Note that the call to dvmCheckInst is done as a tail call. 19528 */ 19529 adrl lr, dvmAsmInstructionStart + (455 * 64) 19530 mov r0, rPC @ arg0 19531 mov r1, rSELF @ arg1 19532 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19533 19534/* ------------------------------ */ 19535 .balign 64 19536.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */ 19537/* File: armv5te/ALT_STUB.S */ 19538/* 19539 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19540 * any interesting requests and then jump to the real instruction 19541 * handler. Note that the call to dvmCheckInst is done as a tail call. 19542 */ 19543 adrl lr, dvmAsmInstructionStart + (456 * 64) 19544 mov r0, rPC @ arg0 19545 mov r1, rSELF @ arg1 19546 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19547 19548/* ------------------------------ */ 19549 .balign 64 19550.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */ 19551/* File: armv5te/ALT_STUB.S */ 19552/* 19553 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19554 * any interesting requests and then jump to the real instruction 19555 * handler. Note that the call to dvmCheckInst is done as a tail call. 19556 */ 19557 adrl lr, dvmAsmInstructionStart + (457 * 64) 19558 mov r0, rPC @ arg0 19559 mov r1, rSELF @ arg1 19560 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19561 19562/* ------------------------------ */ 19563 .balign 64 19564.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */ 19565/* File: armv5te/ALT_STUB.S */ 19566/* 19567 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19568 * any interesting requests and then jump to the real instruction 19569 * handler. Note that the call to dvmCheckInst is done as a tail call. 19570 */ 19571 adrl lr, dvmAsmInstructionStart + (458 * 64) 19572 mov r0, rPC @ arg0 19573 mov r1, rSELF @ arg1 19574 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19575 19576/* ------------------------------ */ 19577 .balign 64 19578.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */ 19579/* File: armv5te/ALT_STUB.S */ 19580/* 19581 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19582 * any interesting requests and then jump to the real instruction 19583 * handler. Note that the call to dvmCheckInst is done as a tail call. 19584 */ 19585 adrl lr, dvmAsmInstructionStart + (459 * 64) 19586 mov r0, rPC @ arg0 19587 mov r1, rSELF @ arg1 19588 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19589 19590/* ------------------------------ */ 19591 .balign 64 19592.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */ 19593/* File: armv5te/ALT_STUB.S */ 19594/* 19595 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19596 * any interesting requests and then jump to the real instruction 19597 * handler. Note that the call to dvmCheckInst is done as a tail call. 19598 */ 19599 adrl lr, dvmAsmInstructionStart + (460 * 64) 19600 mov r0, rPC @ arg0 19601 mov r1, rSELF @ arg1 19602 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19603 19604/* ------------------------------ */ 19605 .balign 64 19606.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */ 19607/* File: armv5te/ALT_STUB.S */ 19608/* 19609 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19610 * any interesting requests and then jump to the real instruction 19611 * handler. Note that the call to dvmCheckInst is done as a tail call. 19612 */ 19613 adrl lr, dvmAsmInstructionStart + (461 * 64) 19614 mov r0, rPC @ arg0 19615 mov r1, rSELF @ arg1 19616 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19617 19618/* ------------------------------ */ 19619 .balign 64 19620.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */ 19621/* File: armv5te/ALT_STUB.S */ 19622/* 19623 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19624 * any interesting requests and then jump to the real instruction 19625 * handler. Note that the call to dvmCheckInst is done as a tail call. 19626 */ 19627 adrl lr, dvmAsmInstructionStart + (462 * 64) 19628 mov r0, rPC @ arg0 19629 mov r1, rSELF @ arg1 19630 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19631 19632/* ------------------------------ */ 19633 .balign 64 19634.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */ 19635/* File: armv5te/ALT_STUB.S */ 19636/* 19637 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19638 * any interesting requests and then jump to the real instruction 19639 * handler. Note that the call to dvmCheckInst is done as a tail call. 19640 */ 19641 adrl lr, dvmAsmInstructionStart + (463 * 64) 19642 mov r0, rPC @ arg0 19643 mov r1, rSELF @ arg1 19644 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19645 19646/* ------------------------------ */ 19647 .balign 64 19648.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */ 19649/* File: armv5te/ALT_STUB.S */ 19650/* 19651 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19652 * any interesting requests and then jump to the real instruction 19653 * handler. Note that the call to dvmCheckInst is done as a tail call. 19654 */ 19655 adrl lr, dvmAsmInstructionStart + (464 * 64) 19656 mov r0, rPC @ arg0 19657 mov r1, rSELF @ arg1 19658 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19659 19660/* ------------------------------ */ 19661 .balign 64 19662.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */ 19663/* File: armv5te/ALT_STUB.S */ 19664/* 19665 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19666 * any interesting requests and then jump to the real instruction 19667 * handler. Note that the call to dvmCheckInst is done as a tail call. 19668 */ 19669 adrl lr, dvmAsmInstructionStart + (465 * 64) 19670 mov r0, rPC @ arg0 19671 mov r1, rSELF @ arg1 19672 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19673 19674/* ------------------------------ */ 19675 .balign 64 19676.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */ 19677/* File: armv5te/ALT_STUB.S */ 19678/* 19679 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19680 * any interesting requests and then jump to the real instruction 19681 * handler. Note that the call to dvmCheckInst is done as a tail call. 19682 */ 19683 adrl lr, dvmAsmInstructionStart + (466 * 64) 19684 mov r0, rPC @ arg0 19685 mov r1, rSELF @ arg1 19686 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19687 19688/* ------------------------------ */ 19689 .balign 64 19690.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */ 19691/* File: armv5te/ALT_STUB.S */ 19692/* 19693 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19694 * any interesting requests and then jump to the real instruction 19695 * handler. Note that the call to dvmCheckInst is done as a tail call. 19696 */ 19697 adrl lr, dvmAsmInstructionStart + (467 * 64) 19698 mov r0, rPC @ arg0 19699 mov r1, rSELF @ arg1 19700 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19701 19702/* ------------------------------ */ 19703 .balign 64 19704.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */ 19705/* File: armv5te/ALT_STUB.S */ 19706/* 19707 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19708 * any interesting requests and then jump to the real instruction 19709 * handler. Note that the call to dvmCheckInst is done as a tail call. 19710 */ 19711 adrl lr, dvmAsmInstructionStart + (468 * 64) 19712 mov r0, rPC @ arg0 19713 mov r1, rSELF @ arg1 19714 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19715 19716/* ------------------------------ */ 19717 .balign 64 19718.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */ 19719/* File: armv5te/ALT_STUB.S */ 19720/* 19721 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19722 * any interesting requests and then jump to the real instruction 19723 * handler. Note that the call to dvmCheckInst is done as a tail call. 19724 */ 19725 adrl lr, dvmAsmInstructionStart + (469 * 64) 19726 mov r0, rPC @ arg0 19727 mov r1, rSELF @ arg1 19728 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19729 19730/* ------------------------------ */ 19731 .balign 64 19732.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */ 19733/* File: armv5te/ALT_STUB.S */ 19734/* 19735 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19736 * any interesting requests and then jump to the real instruction 19737 * handler. Note that the call to dvmCheckInst is done as a tail call. 19738 */ 19739 adrl lr, dvmAsmInstructionStart + (470 * 64) 19740 mov r0, rPC @ arg0 19741 mov r1, rSELF @ arg1 19742 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19743 19744/* ------------------------------ */ 19745 .balign 64 19746.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */ 19747/* File: armv5te/ALT_STUB.S */ 19748/* 19749 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19750 * any interesting requests and then jump to the real instruction 19751 * handler. Note that the call to dvmCheckInst is done as a tail call. 19752 */ 19753 adrl lr, dvmAsmInstructionStart + (471 * 64) 19754 mov r0, rPC @ arg0 19755 mov r1, rSELF @ arg1 19756 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19757 19758/* ------------------------------ */ 19759 .balign 64 19760.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */ 19761/* File: armv5te/ALT_STUB.S */ 19762/* 19763 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19764 * any interesting requests and then jump to the real instruction 19765 * handler. Note that the call to dvmCheckInst is done as a tail call. 19766 */ 19767 adrl lr, dvmAsmInstructionStart + (472 * 64) 19768 mov r0, rPC @ arg0 19769 mov r1, rSELF @ arg1 19770 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19771 19772/* ------------------------------ */ 19773 .balign 64 19774.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */ 19775/* File: armv5te/ALT_STUB.S */ 19776/* 19777 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19778 * any interesting requests and then jump to the real instruction 19779 * handler. Note that the call to dvmCheckInst is done as a tail call. 19780 */ 19781 adrl lr, dvmAsmInstructionStart + (473 * 64) 19782 mov r0, rPC @ arg0 19783 mov r1, rSELF @ arg1 19784 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19785 19786/* ------------------------------ */ 19787 .balign 64 19788.L_ALT_OP_UNUSED_DAFF: /* 0x1da */ 19789/* File: armv5te/ALT_STUB.S */ 19790/* 19791 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19792 * any interesting requests and then jump to the real instruction 19793 * handler. Note that the call to dvmCheckInst is done as a tail call. 19794 */ 19795 adrl lr, dvmAsmInstructionStart + (474 * 64) 19796 mov r0, rPC @ arg0 19797 mov r1, rSELF @ arg1 19798 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19799 19800/* ------------------------------ */ 19801 .balign 64 19802.L_ALT_OP_UNUSED_DBFF: /* 0x1db */ 19803/* File: armv5te/ALT_STUB.S */ 19804/* 19805 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19806 * any interesting requests and then jump to the real instruction 19807 * handler. Note that the call to dvmCheckInst is done as a tail call. 19808 */ 19809 adrl lr, dvmAsmInstructionStart + (475 * 64) 19810 mov r0, rPC @ arg0 19811 mov r1, rSELF @ arg1 19812 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19813 19814/* ------------------------------ */ 19815 .balign 64 19816.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */ 19817/* File: armv5te/ALT_STUB.S */ 19818/* 19819 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19820 * any interesting requests and then jump to the real instruction 19821 * handler. Note that the call to dvmCheckInst is done as a tail call. 19822 */ 19823 adrl lr, dvmAsmInstructionStart + (476 * 64) 19824 mov r0, rPC @ arg0 19825 mov r1, rSELF @ arg1 19826 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19827 19828/* ------------------------------ */ 19829 .balign 64 19830.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */ 19831/* File: armv5te/ALT_STUB.S */ 19832/* 19833 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19834 * any interesting requests and then jump to the real instruction 19835 * handler. Note that the call to dvmCheckInst is done as a tail call. 19836 */ 19837 adrl lr, dvmAsmInstructionStart + (477 * 64) 19838 mov r0, rPC @ arg0 19839 mov r1, rSELF @ arg1 19840 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19841 19842/* ------------------------------ */ 19843 .balign 64 19844.L_ALT_OP_UNUSED_DEFF: /* 0x1de */ 19845/* File: armv5te/ALT_STUB.S */ 19846/* 19847 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19848 * any interesting requests and then jump to the real instruction 19849 * handler. Note that the call to dvmCheckInst is done as a tail call. 19850 */ 19851 adrl lr, dvmAsmInstructionStart + (478 * 64) 19852 mov r0, rPC @ arg0 19853 mov r1, rSELF @ arg1 19854 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19855 19856/* ------------------------------ */ 19857 .balign 64 19858.L_ALT_OP_UNUSED_DFFF: /* 0x1df */ 19859/* File: armv5te/ALT_STUB.S */ 19860/* 19861 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19862 * any interesting requests and then jump to the real instruction 19863 * handler. Note that the call to dvmCheckInst is done as a tail call. 19864 */ 19865 adrl lr, dvmAsmInstructionStart + (479 * 64) 19866 mov r0, rPC @ arg0 19867 mov r1, rSELF @ arg1 19868 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19869 19870/* ------------------------------ */ 19871 .balign 64 19872.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */ 19873/* File: armv5te/ALT_STUB.S */ 19874/* 19875 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19876 * any interesting requests and then jump to the real instruction 19877 * handler. Note that the call to dvmCheckInst is done as a tail call. 19878 */ 19879 adrl lr, dvmAsmInstructionStart + (480 * 64) 19880 mov r0, rPC @ arg0 19881 mov r1, rSELF @ arg1 19882 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19883 19884/* ------------------------------ */ 19885 .balign 64 19886.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */ 19887/* File: armv5te/ALT_STUB.S */ 19888/* 19889 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19890 * any interesting requests and then jump to the real instruction 19891 * handler. Note that the call to dvmCheckInst is done as a tail call. 19892 */ 19893 adrl lr, dvmAsmInstructionStart + (481 * 64) 19894 mov r0, rPC @ arg0 19895 mov r1, rSELF @ arg1 19896 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19897 19898/* ------------------------------ */ 19899 .balign 64 19900.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */ 19901/* File: armv5te/ALT_STUB.S */ 19902/* 19903 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19904 * any interesting requests and then jump to the real instruction 19905 * handler. Note that the call to dvmCheckInst is done as a tail call. 19906 */ 19907 adrl lr, dvmAsmInstructionStart + (482 * 64) 19908 mov r0, rPC @ arg0 19909 mov r1, rSELF @ arg1 19910 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19911 19912/* ------------------------------ */ 19913 .balign 64 19914.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */ 19915/* File: armv5te/ALT_STUB.S */ 19916/* 19917 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19918 * any interesting requests and then jump to the real instruction 19919 * handler. Note that the call to dvmCheckInst is done as a tail call. 19920 */ 19921 adrl lr, dvmAsmInstructionStart + (483 * 64) 19922 mov r0, rPC @ arg0 19923 mov r1, rSELF @ arg1 19924 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19925 19926/* ------------------------------ */ 19927 .balign 64 19928.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */ 19929/* File: armv5te/ALT_STUB.S */ 19930/* 19931 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19932 * any interesting requests and then jump to the real instruction 19933 * handler. Note that the call to dvmCheckInst is done as a tail call. 19934 */ 19935 adrl lr, dvmAsmInstructionStart + (484 * 64) 19936 mov r0, rPC @ arg0 19937 mov r1, rSELF @ arg1 19938 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19939 19940/* ------------------------------ */ 19941 .balign 64 19942.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */ 19943/* File: armv5te/ALT_STUB.S */ 19944/* 19945 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19946 * any interesting requests and then jump to the real instruction 19947 * handler. Note that the call to dvmCheckInst is done as a tail call. 19948 */ 19949 adrl lr, dvmAsmInstructionStart + (485 * 64) 19950 mov r0, rPC @ arg0 19951 mov r1, rSELF @ arg1 19952 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19953 19954/* ------------------------------ */ 19955 .balign 64 19956.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */ 19957/* File: armv5te/ALT_STUB.S */ 19958/* 19959 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19960 * any interesting requests and then jump to the real instruction 19961 * handler. Note that the call to dvmCheckInst is done as a tail call. 19962 */ 19963 adrl lr, dvmAsmInstructionStart + (486 * 64) 19964 mov r0, rPC @ arg0 19965 mov r1, rSELF @ arg1 19966 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19967 19968/* ------------------------------ */ 19969 .balign 64 19970.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */ 19971/* File: armv5te/ALT_STUB.S */ 19972/* 19973 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19974 * any interesting requests and then jump to the real instruction 19975 * handler. Note that the call to dvmCheckInst is done as a tail call. 19976 */ 19977 adrl lr, dvmAsmInstructionStart + (487 * 64) 19978 mov r0, rPC @ arg0 19979 mov r1, rSELF @ arg1 19980 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19981 19982/* ------------------------------ */ 19983 .balign 64 19984.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */ 19985/* File: armv5te/ALT_STUB.S */ 19986/* 19987 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19988 * any interesting requests and then jump to the real instruction 19989 * handler. Note that the call to dvmCheckInst is done as a tail call. 19990 */ 19991 adrl lr, dvmAsmInstructionStart + (488 * 64) 19992 mov r0, rPC @ arg0 19993 mov r1, rSELF @ arg1 19994 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19995 19996/* ------------------------------ */ 19997 .balign 64 19998.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */ 19999/* File: armv5te/ALT_STUB.S */ 20000/* 20001 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20002 * any interesting requests and then jump to the real instruction 20003 * handler. Note that the call to dvmCheckInst is done as a tail call. 20004 */ 20005 adrl lr, dvmAsmInstructionStart + (489 * 64) 20006 mov r0, rPC @ arg0 20007 mov r1, rSELF @ arg1 20008 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20009 20010/* ------------------------------ */ 20011 .balign 64 20012.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */ 20013/* File: armv5te/ALT_STUB.S */ 20014/* 20015 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20016 * any interesting requests and then jump to the real instruction 20017 * handler. Note that the call to dvmCheckInst is done as a tail call. 20018 */ 20019 adrl lr, dvmAsmInstructionStart + (490 * 64) 20020 mov r0, rPC @ arg0 20021 mov r1, rSELF @ arg1 20022 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20023 20024/* ------------------------------ */ 20025 .balign 64 20026.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */ 20027/* File: armv5te/ALT_STUB.S */ 20028/* 20029 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20030 * any interesting requests and then jump to the real instruction 20031 * handler. Note that the call to dvmCheckInst is done as a tail call. 20032 */ 20033 adrl lr, dvmAsmInstructionStart + (491 * 64) 20034 mov r0, rPC @ arg0 20035 mov r1, rSELF @ arg1 20036 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20037 20038/* ------------------------------ */ 20039 .balign 64 20040.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */ 20041/* File: armv5te/ALT_STUB.S */ 20042/* 20043 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20044 * any interesting requests and then jump to the real instruction 20045 * handler. Note that the call to dvmCheckInst is done as a tail call. 20046 */ 20047 adrl lr, dvmAsmInstructionStart + (492 * 64) 20048 mov r0, rPC @ arg0 20049 mov r1, rSELF @ arg1 20050 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20051 20052/* ------------------------------ */ 20053 .balign 64 20054.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */ 20055/* File: armv5te/ALT_STUB.S */ 20056/* 20057 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20058 * any interesting requests and then jump to the real instruction 20059 * handler. Note that the call to dvmCheckInst is done as a tail call. 20060 */ 20061 adrl lr, dvmAsmInstructionStart + (493 * 64) 20062 mov r0, rPC @ arg0 20063 mov r1, rSELF @ arg1 20064 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20065 20066/* ------------------------------ */ 20067 .balign 64 20068.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */ 20069/* File: armv5te/ALT_STUB.S */ 20070/* 20071 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20072 * any interesting requests and then jump to the real instruction 20073 * handler. Note that the call to dvmCheckInst is done as a tail call. 20074 */ 20075 adrl lr, dvmAsmInstructionStart + (494 * 64) 20076 mov r0, rPC @ arg0 20077 mov r1, rSELF @ arg1 20078 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20079 20080/* ------------------------------ */ 20081 .balign 64 20082.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */ 20083/* File: armv5te/ALT_STUB.S */ 20084/* 20085 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20086 * any interesting requests and then jump to the real instruction 20087 * handler. Note that the call to dvmCheckInst is done as a tail call. 20088 */ 20089 adrl lr, dvmAsmInstructionStart + (495 * 64) 20090 mov r0, rPC @ arg0 20091 mov r1, rSELF @ arg1 20092 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20093 20094/* ------------------------------ */ 20095 .balign 64 20096.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */ 20097/* File: armv5te/ALT_STUB.S */ 20098/* 20099 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20100 * any interesting requests and then jump to the real instruction 20101 * handler. Note that the call to dvmCheckInst is done as a tail call. 20102 */ 20103 adrl lr, dvmAsmInstructionStart + (496 * 64) 20104 mov r0, rPC @ arg0 20105 mov r1, rSELF @ arg1 20106 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20107 20108/* ------------------------------ */ 20109 .balign 64 20110.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */ 20111/* File: armv5te/ALT_STUB.S */ 20112/* 20113 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20114 * any interesting requests and then jump to the real instruction 20115 * handler. Note that the call to dvmCheckInst is done as a tail call. 20116 */ 20117 adrl lr, dvmAsmInstructionStart + (497 * 64) 20118 mov r0, rPC @ arg0 20119 mov r1, rSELF @ arg1 20120 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20121 20122/* ------------------------------ */ 20123 .balign 64 20124.L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */ 20125/* File: armv5te/ALT_STUB.S */ 20126/* 20127 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20128 * any interesting requests and then jump to the real instruction 20129 * handler. Note that the call to dvmCheckInst is done as a tail call. 20130 */ 20131 adrl lr, dvmAsmInstructionStart + (498 * 64) 20132 mov r0, rPC @ arg0 20133 mov r1, rSELF @ arg1 20134 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20135 20136/* ------------------------------ */ 20137 .balign 64 20138.L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */ 20139/* File: armv5te/ALT_STUB.S */ 20140/* 20141 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20142 * any interesting requests and then jump to the real instruction 20143 * handler. Note that the call to dvmCheckInst is done as a tail call. 20144 */ 20145 adrl lr, dvmAsmInstructionStart + (499 * 64) 20146 mov r0, rPC @ arg0 20147 mov r1, rSELF @ arg1 20148 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20149 20150/* ------------------------------ */ 20151 .balign 64 20152.L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */ 20153/* File: armv5te/ALT_STUB.S */ 20154/* 20155 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20156 * any interesting requests and then jump to the real instruction 20157 * handler. Note that the call to dvmCheckInst is done as a tail call. 20158 */ 20159 adrl lr, dvmAsmInstructionStart + (500 * 64) 20160 mov r0, rPC @ arg0 20161 mov r1, rSELF @ arg1 20162 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20163 20164/* ------------------------------ */ 20165 .balign 64 20166.L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */ 20167/* File: armv5te/ALT_STUB.S */ 20168/* 20169 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20170 * any interesting requests and then jump to the real instruction 20171 * handler. Note that the call to dvmCheckInst is done as a tail call. 20172 */ 20173 adrl lr, dvmAsmInstructionStart + (501 * 64) 20174 mov r0, rPC @ arg0 20175 mov r1, rSELF @ arg1 20176 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20177 20178/* ------------------------------ */ 20179 .balign 64 20180.L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */ 20181/* File: armv5te/ALT_STUB.S */ 20182/* 20183 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20184 * any interesting requests and then jump to the real instruction 20185 * handler. Note that the call to dvmCheckInst is done as a tail call. 20186 */ 20187 adrl lr, dvmAsmInstructionStart + (502 * 64) 20188 mov r0, rPC @ arg0 20189 mov r1, rSELF @ arg1 20190 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20191 20192/* ------------------------------ */ 20193 .balign 64 20194.L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */ 20195/* File: armv5te/ALT_STUB.S */ 20196/* 20197 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20198 * any interesting requests and then jump to the real instruction 20199 * handler. Note that the call to dvmCheckInst is done as a tail call. 20200 */ 20201 adrl lr, dvmAsmInstructionStart + (503 * 64) 20202 mov r0, rPC @ arg0 20203 mov r1, rSELF @ arg1 20204 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20205 20206/* ------------------------------ */ 20207 .balign 64 20208.L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */ 20209/* File: armv5te/ALT_STUB.S */ 20210/* 20211 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20212 * any interesting requests and then jump to the real instruction 20213 * handler. Note that the call to dvmCheckInst is done as a tail call. 20214 */ 20215 adrl lr, dvmAsmInstructionStart + (504 * 64) 20216 mov r0, rPC @ arg0 20217 mov r1, rSELF @ arg1 20218 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20219 20220/* ------------------------------ */ 20221 .balign 64 20222.L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */ 20223/* File: armv5te/ALT_STUB.S */ 20224/* 20225 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20226 * any interesting requests and then jump to the real instruction 20227 * handler. Note that the call to dvmCheckInst is done as a tail call. 20228 */ 20229 adrl lr, dvmAsmInstructionStart + (505 * 64) 20230 mov r0, rPC @ arg0 20231 mov r1, rSELF @ arg1 20232 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20233 20234/* ------------------------------ */ 20235 .balign 64 20236.L_ALT_OP_UNUSED_FAFF: /* 0x1fa */ 20237/* File: armv5te/ALT_STUB.S */ 20238/* 20239 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20240 * any interesting requests and then jump to the real instruction 20241 * handler. Note that the call to dvmCheckInst is done as a tail call. 20242 */ 20243 adrl lr, dvmAsmInstructionStart + (506 * 64) 20244 mov r0, rPC @ arg0 20245 mov r1, rSELF @ arg1 20246 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20247 20248/* ------------------------------ */ 20249 .balign 64 20250.L_ALT_OP_UNUSED_FBFF: /* 0x1fb */ 20251/* File: armv5te/ALT_STUB.S */ 20252/* 20253 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20254 * any interesting requests and then jump to the real instruction 20255 * handler. Note that the call to dvmCheckInst is done as a tail call. 20256 */ 20257 adrl lr, dvmAsmInstructionStart + (507 * 64) 20258 mov r0, rPC @ arg0 20259 mov r1, rSELF @ arg1 20260 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20261 20262/* ------------------------------ */ 20263 .balign 64 20264.L_ALT_OP_UNUSED_FCFF: /* 0x1fc */ 20265/* File: armv5te/ALT_STUB.S */ 20266/* 20267 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20268 * any interesting requests and then jump to the real instruction 20269 * handler. Note that the call to dvmCheckInst is done as a tail call. 20270 */ 20271 adrl lr, dvmAsmInstructionStart + (508 * 64) 20272 mov r0, rPC @ arg0 20273 mov r1, rSELF @ arg1 20274 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20275 20276/* ------------------------------ */ 20277 .balign 64 20278.L_ALT_OP_UNUSED_FDFF: /* 0x1fd */ 20279/* File: armv5te/ALT_STUB.S */ 20280/* 20281 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20282 * any interesting requests and then jump to the real instruction 20283 * handler. Note that the call to dvmCheckInst is done as a tail call. 20284 */ 20285 adrl lr, dvmAsmInstructionStart + (509 * 64) 20286 mov r0, rPC @ arg0 20287 mov r1, rSELF @ arg1 20288 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20289 20290/* ------------------------------ */ 20291 .balign 64 20292.L_ALT_OP_UNUSED_FEFF: /* 0x1fe */ 20293/* File: armv5te/ALT_STUB.S */ 20294/* 20295 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20296 * any interesting requests and then jump to the real instruction 20297 * handler. Note that the call to dvmCheckInst is done as a tail call. 20298 */ 20299 adrl lr, dvmAsmInstructionStart + (510 * 64) 20300 mov r0, rPC @ arg0 20301 mov r1, rSELF @ arg1 20302 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20303 20304/* ------------------------------ */ 20305 .balign 64 20306.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 20307/* File: armv5te/ALT_STUB.S */ 20308/* 20309 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20310 * any interesting requests and then jump to the real instruction 20311 * handler. Note that the call to dvmCheckInst is done as a tail call. 20312 */ 20313 adrl lr, dvmAsmInstructionStart + (511 * 64) 20314 mov r0, rPC @ arg0 20315 mov r1, rSELF @ arg1 20316 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20317 20318 .balign 64 20319 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart 20320 .global dvmAsmAltInstructionEnd 20321dvmAsmAltInstructionEnd: 20322/* File: armv5te/footer.S */ 20323 20324/* 20325 * =========================================================================== 20326 * Common subroutines and data 20327 * =========================================================================== 20328 */ 20329 20330 20331 20332 .text 20333 .align 2 20334 20335#if defined(WITH_JIT) 20336#if defined(WITH_SELF_VERIFICATION) 20337 .global dvmJitToInterpPunt 20338dvmJitToInterpPunt: 20339 mov r2,#kSVSPunt @ r2<- interpreter entry point 20340 mov r3, #0 20341 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20342 b jitSVShadowRunEnd @ doesn't return 20343 20344 .global dvmJitToInterpSingleStep 20345dvmJitToInterpSingleStep: 20346 str lr,[rSELF,#offThread_jitResumeNPC] 20347 str r1,[rSELF,#offThread_jitResumeDPC] 20348 mov r2,#kSVSSingleStep @ r2<- interpreter entry point 20349 b jitSVShadowRunEnd @ doesn't return 20350 20351 .global dvmJitToInterpNoChainNoProfile 20352dvmJitToInterpNoChainNoProfile: 20353 mov r0,rPC @ pass our target PC 20354 mov r2,#kSVSNoProfile @ r2<- interpreter entry point 20355 mov r3, #0 @ 0 means !inJitCodeCache 20356 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 20357 b jitSVShadowRunEnd @ doesn't return 20358 20359 .global dvmJitToInterpTraceSelectNoChain 20360dvmJitToInterpTraceSelectNoChain: 20361 mov r0,rPC @ pass our target PC 20362 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20363 mov r3, #0 @ 0 means !inJitCodeCache 20364 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20365 b jitSVShadowRunEnd @ doesn't return 20366 20367 .global dvmJitToInterpTraceSelect 20368dvmJitToInterpTraceSelect: 20369 ldr r0,[lr, #-1] @ pass our target PC 20370 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20371 mov r3, #0 @ 0 means !inJitCodeCache 20372 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20373 b jitSVShadowRunEnd @ doesn't return 20374 20375 .global dvmJitToInterpBackwardBranch 20376dvmJitToInterpBackwardBranch: 20377 ldr r0,[lr, #-1] @ pass our target PC 20378 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 20379 mov r3, #0 @ 0 means !inJitCodeCache 20380 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20381 b jitSVShadowRunEnd @ doesn't return 20382 20383 .global dvmJitToInterpNormal 20384dvmJitToInterpNormal: 20385 ldr r0,[lr, #-1] @ pass our target PC 20386 mov r2,#kSVSNormal @ r2<- interpreter entry point 20387 mov r3, #0 @ 0 means !inJitCodeCache 20388 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20389 b jitSVShadowRunEnd @ doesn't return 20390 20391 .global dvmJitToInterpNoChain 20392dvmJitToInterpNoChain: 20393 mov r0,rPC @ pass our target PC 20394 mov r2,#kSVSNoChain @ r2<- interpreter entry point 20395 mov r3, #0 @ 0 means !inJitCodeCache 20396 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20397 b jitSVShadowRunEnd @ doesn't return 20398#else 20399/* 20400 * Return from the translation cache to the interpreter when the compiler is 20401 * having issues translating/executing a Dalvik instruction. We have to skip 20402 * the code cache lookup otherwise it is possible to indefinitely bouce 20403 * between the interpreter and the code cache if the instruction that fails 20404 * to be compiled happens to be at a trace start. 20405 */ 20406 .global dvmJitToInterpPunt 20407dvmJitToInterpPunt: 20408 mov rPC, r0 20409#if defined(WITH_JIT_TUNING) 20410 mov r0,lr 20411 bl dvmBumpPunt; 20412#endif 20413 EXPORT_PC() 20414 mov r0, #0 20415 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20416 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20417 FETCH_INST() 20418 GET_INST_OPCODE(ip) 20419 GOTO_OPCODE(ip) 20420 20421/* 20422 * Return to the interpreter to handle a single instruction. 20423 * On entry: 20424 * r0 <= PC 20425 * r1 <= PC of resume instruction 20426 * lr <= resume point in translation 20427 */ 20428 .global dvmJitToInterpSingleStep 20429dvmJitToInterpSingleStep: 20430 str lr,[rSELF,#offThread_jitResumeNPC] 20431 str r1,[rSELF,#offThread_jitResumeDPC] 20432 mov r1,#kInterpEntryInstr 20433 @ enum is 4 byte in aapcs-EABI 20434 str r1, [rSELF, #offThread_entryPoint] 20435 mov rPC,r0 20436 EXPORT_PC() 20437 20438 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20439 mov r2,#kJitSingleStep @ Ask for single step and then revert 20440 str r2,[rSELF,#offThread_jitState] 20441 mov r1,#1 @ set changeInterp to bail to debug interp 20442 b common_gotoBail 20443 20444/* 20445 * Return from the translation cache and immediately request 20446 * a translation for the exit target. Commonly used for callees. 20447 */ 20448 .global dvmJitToInterpTraceSelectNoChain 20449dvmJitToInterpTraceSelectNoChain: 20450#if defined(WITH_JIT_TUNING) 20451 bl dvmBumpNoChain 20452#endif 20453 mov r0,rPC 20454 bl dvmJitGetTraceAddr @ Is there a translation? 20455 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20456 mov r1, rPC @ arg1 of translation may need this 20457 mov lr, #0 @ in case target is HANDLER_INTERPRET 20458 cmp r0,#0 @ !0 means translation exists 20459 bxne r0 @ continue native execution if so 20460 b 2f @ branch over to use the interpreter 20461 20462/* 20463 * Return from the translation cache and immediately request 20464 * a translation for the exit target. Commonly used following 20465 * invokes. 20466 */ 20467 .global dvmJitToInterpTraceSelect 20468dvmJitToInterpTraceSelect: 20469 ldr rPC,[lr, #-1] @ get our target PC 20470 add rINST,lr,#-5 @ save start of chain branch 20471 add rINST, #-4 @ .. which is 9 bytes back 20472 mov r0,rPC 20473 bl dvmJitGetTraceAddr @ Is there a translation? 20474 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20475 cmp r0,#0 20476 beq 2f 20477 mov r1,rINST 20478 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 20479 mov r1, rPC @ arg1 of translation may need this 20480 mov lr, #0 @ in case target is HANDLER_INTERPRET 20481 cmp r0,#0 @ successful chain? 20482 bxne r0 @ continue native execution 20483 b toInterpreter @ didn't chain - resume with interpreter 20484 20485/* No translation, so request one if profiling isn't disabled*/ 204862: 20487 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20488 GET_JIT_PROF_TABLE(r0) 20489 FETCH_INST() 20490 cmp r0, #0 20491 movne r2,#kJitTSelectRequestHot @ ask for trace selection 20492 bne common_selectTrace 20493 GET_INST_OPCODE(ip) 20494 GOTO_OPCODE(ip) 20495 20496/* 20497 * Return from the translation cache to the interpreter. 20498 * The return was done with a BLX from thumb mode, and 20499 * the following 32-bit word contains the target rPC value. 20500 * Note that lr (r14) will have its low-order bit set to denote 20501 * its thumb-mode origin. 20502 * 20503 * We'll need to stash our lr origin away, recover the new 20504 * target and then check to see if there is a translation available 20505 * for our new target. If so, we do a translation chain and 20506 * go back to native execution. Otherwise, it's back to the 20507 * interpreter (after treating this entry as a potential 20508 * trace start). 20509 */ 20510 .global dvmJitToInterpNormal 20511dvmJitToInterpNormal: 20512 ldr rPC,[lr, #-1] @ get our target PC 20513 add rINST,lr,#-5 @ save start of chain branch 20514 add rINST,#-4 @ .. which is 9 bytes back 20515#if defined(WITH_JIT_TUNING) 20516 bl dvmBumpNormal 20517#endif 20518 mov r0,rPC 20519 bl dvmJitGetTraceAddr @ Is there a translation? 20520 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20521 cmp r0,#0 20522 beq toInterpreter @ go if not, otherwise do chain 20523 mov r1,rINST 20524 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 20525 mov r1, rPC @ arg1 of translation may need this 20526 mov lr, #0 @ in case target is HANDLER_INTERPRET 20527 cmp r0,#0 @ successful chain? 20528 bxne r0 @ continue native execution 20529 b toInterpreter @ didn't chain - resume with interpreter 20530 20531/* 20532 * Return from the translation cache to the interpreter to do method invocation. 20533 * Check if translation exists for the callee, but don't chain to it. 20534 */ 20535 .global dvmJitToInterpNoChainNoProfile 20536dvmJitToInterpNoChainNoProfile: 20537#if defined(WITH_JIT_TUNING) 20538 bl dvmBumpNoChain 20539#endif 20540 mov r0,rPC 20541 bl dvmJitGetTraceAddr @ Is there a translation? 20542 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20543 mov r1, rPC @ arg1 of translation may need this 20544 mov lr, #0 @ in case target is HANDLER_INTERPRET 20545 cmp r0,#0 20546 bxne r0 @ continue native execution if so 20547 EXPORT_PC() 20548 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20549 FETCH_INST() 20550 GET_INST_OPCODE(ip) @ extract opcode from rINST 20551 GOTO_OPCODE(ip) @ jump to next instruction 20552 20553/* 20554 * Return from the translation cache to the interpreter to do method invocation. 20555 * Check if translation exists for the callee, but don't chain to it. 20556 */ 20557 .global dvmJitToInterpNoChain 20558dvmJitToInterpNoChain: 20559#if defined(WITH_JIT_TUNING) 20560 bl dvmBumpNoChain 20561#endif 20562 mov r0,rPC 20563 bl dvmJitGetTraceAddr @ Is there a translation? 20564 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20565 mov r1, rPC @ arg1 of translation may need this 20566 mov lr, #0 @ in case target is HANDLER_INTERPRET 20567 cmp r0,#0 20568 bxne r0 @ continue native execution if so 20569#endif 20570 20571/* 20572 * No translation, restore interpreter regs and start interpreting. 20573 * rSELF & rFP were preserved in the translated code, and rPC has 20574 * already been restored by the time we get here. We'll need to set 20575 * up rIBASE & rINST, and load the address of the JitTable into r0. 20576 */ 20577toInterpreter: 20578 EXPORT_PC() 20579 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20580 FETCH_INST() 20581 GET_JIT_PROF_TABLE(r0) 20582 @ NOTE: intended fallthrough 20583 20584/* 20585 * Common code to update potential trace start counter, and initiate 20586 * a trace-build if appropriate. On entry, rPC should point to the 20587 * next instruction to execute, and rINST should be already loaded with 20588 * the next opcode word, and r0 holds a pointer to the jit profile 20589 * table (pJitProfTable). 20590 */ 20591common_testUpdateProfile: 20592 cmp r0,#0 20593 GET_INST_OPCODE(ip) 20594 GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 20595 20596common_updateProfile: 20597 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 20598 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 20599 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 20600 GET_INST_OPCODE(ip) 20601 subs r1,r1,#1 @ decrement counter 20602 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 20603 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 20604 20605/* 20606 * Here, we switch to the debug interpreter to request 20607 * trace selection. First, though, check to see if there 20608 * is already a native translation in place (and, if so, 20609 * jump to it now). 20610 */ 20611 20612 GET_JIT_THRESHOLD(r1) 20613 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 20614 EXPORT_PC() 20615 mov r0,rPC 20616 bl dvmJitGetTraceAddr @ r0<- dvmJitGetTraceAddr(rPC) 20617 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20618 mov r1, rPC @ arg1 of translation may need this 20619 mov lr, #0 @ in case target is HANDLER_INTERPRET 20620 cmp r0,#0 20621#if !defined(WITH_SELF_VERIFICATION) 20622 bxne r0 @ jump to the translation 20623 mov r2,#kJitTSelectRequest @ ask for trace selection 20624 @ fall-through to common_selectTrace 20625#else 20626 moveq r2,#kJitTSelectRequest @ ask for trace selection 20627 beq common_selectTrace 20628 /* 20629 * At this point, we have a target translation. However, if 20630 * that translation is actually the interpret-only pseudo-translation 20631 * we want to treat it the same as no translation. 20632 */ 20633 mov r10, r0 @ save target 20634 bl dvmCompilerGetInterpretTemplate 20635 cmp r0, r10 @ special case? 20636 bne jitSVShadowRunStart @ set up self verification shadow space 20637 @ Need to clear the inJitCodeCache flag 20638 mov r3, #0 @ 0 means not in the JIT code cache 20639 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 20640 GET_INST_OPCODE(ip) 20641 GOTO_OPCODE(ip) 20642 /* no return */ 20643#endif 20644 20645/* 20646 * On entry: 20647 * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 20648 */ 20649common_selectTrace: 20650 20651 str r2,[rSELF,#offThread_jitState] 20652 mov r2,#kInterpEntryInstr @ normal entry reason 20653 str r2,[rSELF,#offThread_entryPoint] 20654 mov r1,#1 @ set changeInterp 20655 b common_gotoBail 20656 20657#if defined(WITH_SELF_VERIFICATION) 20658/* 20659 * Save PC and registers to shadow memory for self verification mode 20660 * before jumping to native translation. 20661 * On entry: 20662 * rPC, rFP, rSELF: the values that they should contain 20663 * r10: the address of the target translation. 20664 */ 20665jitSVShadowRunStart: 20666 mov r0,rPC @ r0<- program counter 20667 mov r1,rFP @ r1<- frame pointer 20668 mov r2,rSELF @ r2<- self (Thread) pointer 20669 mov r3,r10 @ r3<- target translation 20670 bl dvmSelfVerificationSaveState @ save registers to shadow space 20671 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 20672 bx r10 @ jump to the translation 20673 20674/* 20675 * Restore PC, registers, and interpreter state to original values 20676 * before jumping back to the interpreter. 20677 */ 20678jitSVShadowRunEnd: 20679 mov r1,rFP @ pass ending fp 20680 mov r3,rSELF @ pass self ptr for convenience 20681 bl dvmSelfVerificationRestoreState @ restore pc and fp values 20682 ldr rPC,[rSELF,#offThread_pc] @ restore PC 20683 ldr rFP,[rSELF,#offThread_fp] @ restore FP 20684 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 20685 cmp r1,#0 @ check for punt condition 20686 beq 1f 20687 mov r2,#kJitSelfVerification @ ask for self verification 20688 str r2,[rSELF,#offThread_jitState] 20689 mov r2,#kInterpEntryInstr @ normal entry reason 20690 str r2,[rSELF,#offThread_entryPoint] 20691 mov r1,#1 @ set changeInterp 20692 b common_gotoBail 20693 206941: @ exit to interpreter without check 20695 EXPORT_PC() 20696 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20697 FETCH_INST() 20698 GET_INST_OPCODE(ip) 20699 GOTO_OPCODE(ip) 20700#endif 20701 20702#endif 20703 20704/* 20705 * Common code when a backward branch is taken. 20706 * 20707 * TODO: we could avoid a branch by just setting r0 and falling through 20708 * into the common_periodicChecks code, and having a test on r0 at the 20709 * end determine if we should return to the caller or update & branch to 20710 * the next instr. 20711 * 20712 * On entry: 20713 * r9 is PC adjustment *in bytes* 20714 */ 20715common_backwardBranch: 20716 mov r0, #kInterpEntryInstr 20717 bl common_periodicChecks 20718#if defined(WITH_JIT) 20719 GET_JIT_PROF_TABLE(r0) 20720 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 20721 cmp r0,#0 20722 bne common_updateProfile 20723 GET_INST_OPCODE(ip) 20724 GOTO_OPCODE(ip) 20725#else 20726 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 20727 GET_INST_OPCODE(ip) @ extract opcode from rINST 20728 GOTO_OPCODE(ip) @ jump to next instruction 20729#endif 20730 20731 20732/* 20733 * Need to see if the thread needs to be suspended or debugger/profiler 20734 * activity has begun. If so, we suspend the thread or side-exit to 20735 * the debug interpreter as appropriate. 20736 * 20737 * The common case is no activity on any of these, so we want to figure 20738 * that out quickly. If something is up, we can then sort out what. 20739 * 20740 * We want to be fast if the VM was built without debugger or profiler 20741 * support, but we also need to recognize that the system is usually 20742 * shipped with both of these enabled. 20743 * 20744 * TODO: reduce this so we're just checking a single location. 20745 * 20746 * On entry: 20747 * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling) 20748 * r9 is trampoline PC adjustment *in bytes* 20749 */ 20750common_periodicChecks: 20751/* TUNING - make this a direct load when interpBreak moved to Thread */ 20752 ldr r1, [rSELF, #offThread_pInterpBreak] @ r3<- &interpBreak 20753 /* speculatively thread-specific suspend count */ 20754 ldr ip, [rSELF, #offThread_suspendCount] 20755 ldr r1, [r1] @ r1<- interpBreak 20756 cmp r1, #0 @ anything unusual? 20757 bxeq lr @ return if not 20758 /* 20759 * One or more interesting events have happened. Figure out what. 20760 * 20761 * r0 still holds the reentry type. 20762 */ 20763 cmp ip, #0 @ want suspend? 20764 beq 3f @ no, must be something else 20765 20766 stmfd sp!, {r0, lr} @ preserve r0 and lr 20767#if defined(WITH_JIT) 20768 /* 20769 * Refresh the Jit's cached copy of profile table pointer. This pointer 20770 * doubles as the Jit's on/off switch. 20771 */ 20772 ldr r3, [rSELF, #offThread_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 20773 mov r0, rSELF @ r0<- self 20774 ldr r3, [r3] @ r3 <- pJitProfTable 20775 EXPORT_PC() @ need for precise GC 20776 str r3, [rSELF, #offThread_pJitProfTable] @ refresh Jit's on/off switch 20777#else 20778 mov r0, rSELF @ r0<- self 20779 EXPORT_PC() @ need for precise GC 20780#endif 20781 bl dvmCheckSuspendPending @ do full check, suspend if necessary 20782 ldmfd sp!, {r0, lr} @ restore r0 and lr 20783 20784 /* 20785 * Reload the interpBreak flags - they may have changed while we 20786 * were suspended. 20787 */ 20788/* TUNING - direct load when InterpBreak moved to Thread */ 20789 ldr r1, [rSELF, #offThread_pInterpBreak] @ r1<- &interpBreak 20790 ldr r1, [r1] @ r1<- interpBreak 207913: 20792 /* 20793 * TODO: this code is too fragile. Need a general mechanism 20794 * to identify what actions to take by submode. Some profiling modes 20795 * (instruction count) need to single-step, while method tracing 20796 * may not. Debugging with breakpoints can run unfettered, but 20797 * source-level single-stepping requires Dalvik singlestepping. 20798 * GC may require a one-shot action and then full-speed resumption. 20799 */ 20800 ands r1, #(kSubModeDebuggerActive | kSubModeEmulatorTrace | kSubModeInstCounting) 20801 bxeq lr @ nothing to do, return 20802 20803 @ debugger/profiler enabled, bail out; self->entryPoint was set above 20804 str r0, [rSELF, #offThread_entryPoint] @ store r0, need for debug/prof 20805 add rPC, rPC, r9 @ update rPC 20806 mov r1, #1 @ "want switch" = true 20807 b common_gotoBail @ side exit 20808 20809 20810/* 20811 * The equivalent of "goto bail", this calls through the "bail handler". 20812 * 20813 * State registers will be saved to the "thread" area before bailing. 20814 * 20815 * On entry: 20816 * r1 is "bool changeInterp", indicating if we want to switch to the 20817 * other interpreter or just bail all the way out 20818 */ 20819common_gotoBail: 20820 SAVE_PC_FP_TO_SELF() @ export state to "thread" 20821 mov r0, rSELF @ r0<- self ptr 20822 b dvmMterpStdBail @ call(self, changeInterp) 20823 20824 @add r1, r1, #1 @ using (boolean+1) 20825 @add r0, rSELF, #offThread_jmpBuf @ r0<- &self->jmpBuf 20826 @bl _longjmp @ does not return 20827 @bl common_abort 20828 20829 20830/* 20831 * Common code for jumbo method invocation. 20832 * NOTE: this adjusts rPC to account for the difference in instruction width. 20833 * As a result, the savedPc in the stack frame will not be wholly accurate. So 20834 * long as that is only used for source file line number calculations, we're 20835 * okay. 20836 * 20837 * On entry: 20838 * r0 is "Method* methodToCall", the method we're trying to call 20839 */ 20840common_invokeMethodJumbo: 20841.LinvokeNewJumbo: 20842 @ prepare to copy args to "outs" area of current frame 20843 add rPC, rPC, #4 @ adjust pc to make return consistent 20844 FETCH(r2, 1) @ r2<- BBBB (arg count) 20845 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 20846 cmp r2, #0 @ no args? 20847 beq .LinvokeArgsDone @ if no args, skip the rest 20848 FETCH(r1, 2) @ r1<- CCCC 20849 b .LinvokeRangeArgs @ handle args like invoke range 20850 20851/* 20852 * Common code for method invocation with range. 20853 * 20854 * On entry: 20855 * r0 is "Method* methodToCall", the method we're trying to call 20856 */ 20857common_invokeMethodRange: 20858.LinvokeNewRange: 20859 @ prepare to copy args to "outs" area of current frame 20860 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 20861 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 20862 beq .LinvokeArgsDone @ if no args, skip the rest 20863 FETCH(r1, 2) @ r1<- CCCC 20864 20865.LinvokeRangeArgs: 20866 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 20867 @ (very few methods have > 10 args; could unroll for common cases) 20868 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 20869 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 208701: ldr r1, [r3], #4 @ val = *fp++ 20871 subs r2, r2, #1 @ count-- 20872 str r1, [r10], #4 @ *outs++ = val 20873 bne 1b @ ...while count != 0 20874 b .LinvokeArgsDone 20875 20876/* 20877 * Common code for method invocation without range. 20878 * 20879 * On entry: 20880 * r0 is "Method* methodToCall", the method we're trying to call 20881 */ 20882common_invokeMethodNoRange: 20883.LinvokeNewNoRange: 20884 @ prepare to copy args to "outs" area of current frame 20885 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 20886 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 20887 FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 20888 beq .LinvokeArgsDone 20889 20890 @ r0=methodToCall, r1=GFED, r2=count, r10=outs 20891.LinvokeNonRange: 20892 rsb r2, r2, #5 @ r2<- 5-r2 20893 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 20894 bl common_abort @ (skipped due to ARM prefetch) 208955: and ip, rINST, #0x0f00 @ isolate A 20896 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 20897 mov r0, r0 @ nop 20898 str r2, [r10, #-4]! @ *--outs = vA 208994: and ip, r1, #0xf000 @ isolate G 20900 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 20901 mov r0, r0 @ nop 20902 str r2, [r10, #-4]! @ *--outs = vG 209033: and ip, r1, #0x0f00 @ isolate F 20904 ldr r2, [rFP, ip, lsr #6] @ r2<- vF 20905 mov r0, r0 @ nop 20906 str r2, [r10, #-4]! @ *--outs = vF 209072: and ip, r1, #0x00f0 @ isolate E 20908 ldr r2, [rFP, ip, lsr #2] @ r2<- vE 20909 mov r0, r0 @ nop 20910 str r2, [r10, #-4]! @ *--outs = vE 209111: and ip, r1, #0x000f @ isolate D 20912 ldr r2, [rFP, ip, lsl #2] @ r2<- vD 20913 mov r0, r0 @ nop 20914 str r2, [r10, #-4]! @ *--outs = vD 209150: @ fall through to .LinvokeArgsDone 20916 20917.LinvokeArgsDone: @ r0=methodToCall 20918 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 20919 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 20920 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 20921 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 20922 @ find space for the new stack frame, check for overflow 20923 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 20924 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 20925 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 20926@ bl common_dumpRegs 20927 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd 20928 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 20929 cmp r3, r9 @ bottom < interpStackEnd? 20930 ldr lr, [rSELF, #offThread_pInterpBreak] 20931 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 20932 blo .LstackOverflow @ yes, this frame will overflow stack 20933 20934 @ set up newSaveArea 20935 ldr lr, [lr] @ lr<- active submodes 20936#ifdef EASY_GDB 20937 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 20938 str ip, [r10, #offStackSaveArea_prevSave] 20939#endif 20940 str rFP, [r10, #offStackSaveArea_prevFrame] 20941 str rPC, [r10, #offStackSaveArea_savedPc] 20942#if defined(WITH_JIT) 20943 mov r9, #0 20944 str r9, [r10, #offStackSaveArea_returnAddr] 20945#endif 20946 ands lr, #kSubModeMethodTrace @ method tracing? 20947 beq 1f @ skip if not 20948 stmfd sp!, {r0-r3} @ preserve r0-r3 20949 mov r1, r6 20950 @ r0=methodToCall, r1=rSELF 20951 bl dvmFastMethodTraceEnter 20952 ldmfd sp!, {r0-r3} @ restore r0-r3 209531: 20954 str r0, [r10, #offStackSaveArea_method] 20955 tst r3, #ACC_NATIVE 20956 bne .LinvokeNative 20957 20958 /* 20959 stmfd sp!, {r0-r3} 20960 bl common_printNewline 20961 mov r0, rFP 20962 mov r1, #0 20963 bl dvmDumpFp 20964 ldmfd sp!, {r0-r3} 20965 stmfd sp!, {r0-r3} 20966 mov r0, r1 20967 mov r1, r10 20968 bl dvmDumpFp 20969 bl common_printNewline 20970 ldmfd sp!, {r0-r3} 20971 */ 20972 20973 ldrh r9, [r2] @ r9 <- load INST from new PC 20974 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 20975 mov rPC, r2 @ publish new rPC 20976 20977 @ Update state values for the new method 20978 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST 20979 str r0, [rSELF, #offThread_method] @ self->method = methodToCall 20980 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ... 20981#if defined(WITH_JIT) 20982 GET_JIT_PROF_TABLE(r0) 20983 mov rFP, r1 @ fp = newFp 20984 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 20985 mov rINST, r9 @ publish new rINST 20986 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 20987 cmp r0,#0 20988 bne common_updateProfile 20989 GOTO_OPCODE(ip) @ jump to next instruction 20990#else 20991 mov rFP, r1 @ fp = newFp 20992 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 20993 mov rINST, r9 @ publish new rINST 20994 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 20995 GOTO_OPCODE(ip) @ jump to next instruction 20996#endif 20997 20998.LinvokeNative: 20999 @ Prep for the native call 21000 @ r0=methodToCall, r1=newFp, r10=newSaveArea 21001 ldr lr, [rSELF, #offThread_pInterpBreak] 21002 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->... 21003 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21004 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 21005 ldr lr, [lr] @ lr<- active submodes 21006 21007 mov r2, r0 @ r2<- methodToCall 21008 mov r0, r1 @ r0<- newFp (points to args) 21009 add r1, rSELF, #offThread_retval @ r1<- &retval 21010 mov r3, rSELF @ arg3<- self 21011 21012#ifdef ASSIST_DEBUGGER 21013 /* insert fake function header to help gdb find the stack frame */ 21014 b .Lskip 21015 .type dalvik_mterp, %function 21016dalvik_mterp: 21017 .fnstart 21018 MTERP_ENTRY1 21019 MTERP_ENTRY2 21020.Lskip: 21021#endif 21022 21023 ands lr, #kSubModeMethodTrace @ method tracing? 21024 beq 110f @ hop if not 21025 @ r2=JNIMethod, r6=rSELF 21026 stmfd sp!, {r2,r6} 21027 21028 mov lr, pc @ set return addr 21029 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 21030 21031 @ r0=JNIMethod, r1=rSELF 21032 ldmfd sp!, {r0-r1} 21033 bl dvmFastNativeMethodTraceExit 21034 b 220f 21035110: 21036 mov lr, pc @ set return addr 21037 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 21038220: 21039#if defined(WITH_JIT) 21040 ldr r3, [rSELF, #offThread_ppJitProfTable] @ Refresh Jit's on/off status 21041#endif 21042 21043 @ native return; r10=newSaveArea 21044 @ equivalent to dvmPopJniLocals 21045 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 21046 ldr r1, [rSELF, #offThread_exception] @ check for exception 21047#if defined(WITH_JIT) 21048 ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 21049#endif 21050 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21051 cmp r1, #0 @ null? 21052 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top 21053#if defined(WITH_JIT) 21054 str r3, [rSELF, #offThread_pJitProfTable] @ refresh cached on/off switch 21055#endif 21056 bne common_exceptionThrown @ no, handle exception 21057 21058 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 21059 GET_INST_OPCODE(ip) @ extract opcode from rINST 21060 GOTO_OPCODE(ip) @ jump to next instruction 21061 21062.LstackOverflow: @ r0=methodToCall 21063 mov r1, r0 @ r1<- methodToCall 21064 mov r0, rSELF @ r0<- self 21065 bl dvmHandleStackOverflow 21066 b common_exceptionThrown 21067#ifdef ASSIST_DEBUGGER 21068 .fnend 21069 .size dalvik_mterp, .-dalvik_mterp 21070#endif 21071 21072 21073 /* 21074 * Common code for method invocation, calling through "glue code". 21075 * 21076 * TODO: now that we have range and non-range invoke handlers, this 21077 * needs to be split into two. Maybe just create entry points 21078 * that set r9 and jump here? 21079 * 21080 * On entry: 21081 * r0 is "Method* methodToCall", the method we're trying to call 21082 * r9 is "bool methodCallRange", indicating if this is a /range variant 21083 */ 21084 .if 0 21085.LinvokeOld: 21086 sub sp, sp, #8 @ space for args + pad 21087 FETCH(ip, 2) @ ip<- FEDC or CCCC 21088 mov r2, r0 @ A2<- methodToCall 21089 mov r0, rSELF @ A0<- self 21090 SAVE_PC_FP_TO_SELF() @ export state to "self" 21091 mov r1, r9 @ A1<- methodCallRange 21092 mov r3, rINST, lsr #8 @ A3<- AA 21093 str ip, [sp, #0] @ A4<- ip 21094 bl dvmMterp_invokeMethod @ call the C invokeMethod 21095 add sp, sp, #8 @ remove arg area 21096 b common_resumeAfterGlueCall @ continue to next instruction 21097 .endif 21098 21099 21100 21101/* 21102 * Common code for handling a return instruction. 21103 * 21104 * This does not return. 21105 */ 21106common_returnFromMethod: 21107.LreturnNew: 21108 mov r0, #kInterpEntryReturn 21109 mov r9, #0 21110 bl common_periodicChecks 21111 21112 ldr lr, [rSELF, #offThread_pInterpBreak] 21113 SAVEAREA_FROM_FP(r0, rFP) 21114 ldr lr, [lr] @ lr<- active submodes 21115 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 21116 ands lr, #kSubModeMethodTrace @ method tracing? 21117 beq 333f 21118 stmfd sp!, {r0-r3} @ preserve r0-r3 21119 mov r0, r6 21120 @ r0=rSELF 21121 bl dvmFastJavaMethodTraceExit 21122 ldmfd sp!, {r0-r3} @ restore r0-r3 21123333: 21124 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 21125 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 21126 @ r2<- method we're returning to 21127 cmp r2, #0 @ is this a break frame? 21128#if defined(WORKAROUND_CORTEX_A9_745320) 21129 /* Don't use conditional loads if the HW defect exists */ 21130 beq 101f 21131 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21132101: 21133#else 21134 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21135#endif 21136 mov r1, #0 @ "want switch" = false 21137 beq common_gotoBail @ break frame, bail out completely 21138 21139 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 21140 str r2, [rSELF, #offThread_method]@ self->method = newSave->method 21141 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 21142 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21143#if defined(WITH_JIT) 21144 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 21145 mov rPC, r9 @ publish new rPC 21146 str r1, [rSELF, #offThread_methodClassDex] 21147 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land 21148 cmp r10, #0 @ caller is compiled code 21149 blxne r10 21150 GET_INST_OPCODE(ip) @ extract opcode from rINST 21151 GOTO_OPCODE(ip) @ jump to next instruction 21152#else 21153 GET_INST_OPCODE(ip) @ extract opcode from rINST 21154 mov rPC, r9 @ publish new rPC 21155 str r1, [rSELF, #offThread_methodClassDex] 21156 GOTO_OPCODE(ip) @ jump to next instruction 21157#endif 21158 21159 /* 21160 * Return handling, calls through "glue code". 21161 */ 21162 .if 0 21163.LreturnOld: 21164 SAVE_PC_FP_TO_SELF() @ export state 21165 mov r0, rSELF @ arg to function 21166 bl dvmMterp_returnFromMethod 21167 b common_resumeAfterGlueCall 21168 .endif 21169 21170 21171/* 21172 * Somebody has thrown an exception. Handle it. 21173 * 21174 * If the exception processing code returns to us (instead of falling 21175 * out of the interpreter), continue with whatever the next instruction 21176 * now happens to be. 21177 * 21178 * This does not return. 21179 */ 21180 .global dvmMterpCommonExceptionThrown 21181dvmMterpCommonExceptionThrown: 21182common_exceptionThrown: 21183.LexceptionNew: 21184 mov r0, #kInterpEntryThrow 21185 mov r9, #0 21186 bl common_periodicChecks 21187 21188 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception 21189 mov r1, rSELF @ r1<- self 21190 mov r0, r9 @ r0<- exception 21191 bl dvmAddTrackedAlloc @ don't let the exception be GCed 21192 mov r3, #0 @ r3<- NULL 21193 str r3, [rSELF, #offThread_exception] @ self->exception = NULL 21194 21195 /* set up args and a local for "&fp" */ 21196 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 21197 str rFP, [sp, #-4]! @ *--sp = fp 21198 mov ip, sp @ ip<- &fp 21199 mov r3, #0 @ r3<- false 21200 str ip, [sp, #-4]! @ *--sp = &fp 21201 ldr r1, [rSELF, #offThread_method] @ r1<- self->method 21202 mov r0, rSELF @ r0<- self 21203 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 21204 mov r2, r9 @ r2<- exception 21205 sub r1, rPC, r1 @ r1<- pc - method->insns 21206 mov r1, r1, asr #1 @ r1<- offset in code units 21207 21208 /* call, r0 gets catchRelPc (a code-unit offset) */ 21209 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 21210 21211 /* fix earlier stack overflow if necessary; may trash rFP */ 21212 ldrb r1, [rSELF, #offThread_stackOverflowed] 21213 cmp r1, #0 @ did we overflow earlier? 21214 beq 1f @ no, skip ahead 21215 mov rFP, r0 @ save relPc result in rFP 21216 mov r0, rSELF @ r0<- self 21217 mov r1, r9 @ r1<- exception 21218 bl dvmCleanupStackOverflow @ call(self) 21219 mov r0, rFP @ restore result 212201: 21221 21222 /* update frame pointer and check result from dvmFindCatchBlock */ 21223 ldr rFP, [sp, #4] @ retrieve the updated rFP 21224 cmp r0, #0 @ is catchRelPc < 0? 21225 add sp, sp, #8 @ restore stack 21226 bmi .LnotCaughtLocally 21227 21228 /* adjust locals to match self->curFrame and updated PC */ 21229 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 21230 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 21231 str r1, [rSELF, #offThread_method] @ self->method = new method 21232 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 21233 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 21234 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 21235 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 21236 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth... 21237 21238 /* release the tracked alloc on the exception */ 21239 mov r0, r9 @ r0<- exception 21240 mov r1, rSELF @ r1<- self 21241 bl dvmReleaseTrackedAlloc @ release the exception 21242 21243 /* restore the exception if the handler wants it */ 21244 FETCH_INST() @ load rINST from rPC 21245 GET_INST_OPCODE(ip) @ extract opcode from rINST 21246 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 21247 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception 21248 GOTO_OPCODE(ip) @ jump to next instruction 21249 21250.LnotCaughtLocally: @ r9=exception 21251 /* fix stack overflow if necessary */ 21252 ldrb r1, [rSELF, #offThread_stackOverflowed] 21253 cmp r1, #0 @ did we overflow earlier? 21254 movne r0, rSELF @ if yes: r0<- self 21255 movne r1, r9 @ if yes: r1<- exception 21256 blne dvmCleanupStackOverflow @ if yes: call(self) 21257 21258 @ may want to show "not caught locally" debug messages here 21259#if DVM_SHOW_EXCEPTION >= 2 21260 /* call __android_log_print(prio, tag, format, ...) */ 21261 /* "Exception %s from %s:%d not caught locally" */ 21262 @ dvmLineNumFromPC(method, pc - method->insns) 21263 ldr r0, [rSELF, #offThread_method] 21264 ldr r1, [r0, #offMethod_insns] 21265 sub r1, rPC, r1 21266 asr r1, r1, #1 21267 bl dvmLineNumFromPC 21268 str r0, [sp, #-4]! 21269 @ dvmGetMethodSourceFile(method) 21270 ldr r0, [rSELF, #offThread_method] 21271 bl dvmGetMethodSourceFile 21272 str r0, [sp, #-4]! 21273 @ exception->clazz->descriptor 21274 ldr r3, [r9, #offObject_clazz] 21275 ldr r3, [r3, #offClassObject_descriptor] 21276 @ 21277 ldr r2, strExceptionNotCaughtLocally 21278 ldr r1, strLogTag 21279 mov r0, #3 @ LOG_DEBUG 21280 bl __android_log_print 21281#endif 21282 str r9, [rSELF, #offThread_exception] @ restore exception 21283 mov r0, r9 @ r0<- exception 21284 mov r1, rSELF @ r1<- self 21285 bl dvmReleaseTrackedAlloc @ release the exception 21286 mov r1, #0 @ "want switch" = false 21287 b common_gotoBail @ bail out 21288 21289 21290 /* 21291 * Exception handling, calls through "glue code". 21292 */ 21293 .if 0 21294.LexceptionOld: 21295 SAVE_PC_FP_TO_SELF() @ export state 21296 mov r0, rSELF @ arg to function 21297 bl dvmMterp_exceptionThrown 21298 b common_resumeAfterGlueCall 21299 .endif 21300 21301 21302/* 21303 * After returning from a "glued" function, pull out the updated 21304 * values and start executing at the next instruction. 21305 */ 21306common_resumeAfterGlueCall: 21307 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread 21308 FETCH_INST() @ load rINST from rPC 21309 GET_INST_OPCODE(ip) @ extract opcode from rINST 21310 GOTO_OPCODE(ip) @ jump to next instruction 21311 21312/* 21313 * Invalid array index. Note that our calling convention is strange; we use r1 21314 * and r3 because those just happen to be the registers all our callers are 21315 * using. We shuffle them here before calling the C function. 21316 * r1: index 21317 * r3: size 21318 */ 21319common_errArrayIndex: 21320 EXPORT_PC() 21321 mov r0, r1 21322 mov r1, r3 21323 bl dvmThrowArrayIndexOutOfBoundsException 21324 b common_exceptionThrown 21325 21326/* 21327 * Integer divide or mod by zero. 21328 */ 21329common_errDivideByZero: 21330 EXPORT_PC() 21331 ldr r0, strDivideByZero 21332 bl dvmThrowArithmeticException 21333 b common_exceptionThrown 21334 21335/* 21336 * Attempt to allocate an array with a negative size. 21337 * On entry: length in r1 21338 */ 21339common_errNegativeArraySize: 21340 EXPORT_PC() 21341 mov r0, r1 @ arg0 <- len 21342 bl dvmThrowNegativeArraySizeException @ (len) 21343 b common_exceptionThrown 21344 21345/* 21346 * Invocation of a non-existent method. 21347 * On entry: method name in r1 21348 */ 21349common_errNoSuchMethod: 21350 EXPORT_PC() 21351 mov r0, r1 21352 bl dvmThrowNoSuchMethodError 21353 b common_exceptionThrown 21354 21355/* 21356 * We encountered a null object when we weren't expecting one. We 21357 * export the PC, throw a NullPointerException, and goto the exception 21358 * processing code. 21359 */ 21360common_errNullObject: 21361 EXPORT_PC() 21362 mov r0, #0 21363 bl dvmThrowNullPointerException 21364 b common_exceptionThrown 21365 21366/* 21367 * For debugging, cause an immediate fault. The source address will 21368 * be in lr (use a bl instruction to jump here). 21369 */ 21370common_abort: 21371 ldr pc, .LdeadFood 21372.LdeadFood: 21373 .word 0xdeadf00d 21374 21375/* 21376 * Spit out a "we were here", preserving all registers. (The attempt 21377 * to save ip won't work, but we need to save an even number of 21378 * registers for EABI 64-bit stack alignment.) 21379 */ 21380 .macro SQUEAK num 21381common_squeak\num: 21382 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21383 ldr r0, strSqueak 21384 mov r1, #\num 21385 bl printf 21386 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21387 bx lr 21388 .endm 21389 21390 SQUEAK 0 21391 SQUEAK 1 21392 SQUEAK 2 21393 SQUEAK 3 21394 SQUEAK 4 21395 SQUEAK 5 21396 21397/* 21398 * Spit out the number in r0, preserving registers. 21399 */ 21400common_printNum: 21401 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21402 mov r1, r0 21403 ldr r0, strSqueak 21404 bl printf 21405 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21406 bx lr 21407 21408/* 21409 * Print a newline, preserving registers. 21410 */ 21411common_printNewline: 21412 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21413 ldr r0, strNewline 21414 bl printf 21415 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21416 bx lr 21417 21418 /* 21419 * Print the 32-bit quantity in r0 as a hex value, preserving registers. 21420 */ 21421common_printHex: 21422 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21423 mov r1, r0 21424 ldr r0, strPrintHex 21425 bl printf 21426 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21427 bx lr 21428 21429/* 21430 * Print the 64-bit quantity in r0-r1, preserving registers. 21431 */ 21432common_printLong: 21433 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21434 mov r3, r1 21435 mov r2, r0 21436 ldr r0, strPrintLong 21437 bl printf 21438 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21439 bx lr 21440 21441/* 21442 * Print full method info. Pass the Method* in r0. Preserves regs. 21443 */ 21444common_printMethod: 21445 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21446 bl dvmMterpPrintMethod 21447 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21448 bx lr 21449 21450/* 21451 * Call a C helper function that dumps regs and possibly some 21452 * additional info. Requires the C function to be compiled in. 21453 */ 21454 .if 0 21455common_dumpRegs: 21456 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21457 bl dvmMterpDumpArmRegs 21458 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21459 bx lr 21460 .endif 21461 21462#if 0 21463/* 21464 * Experiment on VFP mode. 21465 * 21466 * uint32_t setFPSCR(uint32_t val, uint32_t mask) 21467 * 21468 * Updates the bits specified by "mask", setting them to the values in "val". 21469 */ 21470setFPSCR: 21471 and r0, r0, r1 @ make sure no stray bits are set 21472 fmrx r2, fpscr @ get VFP reg 21473 mvn r1, r1 @ bit-invert mask 21474 and r2, r2, r1 @ clear masked bits 21475 orr r2, r2, r0 @ set specified bits 21476 fmxr fpscr, r2 @ set VFP reg 21477 mov r0, r2 @ return new value 21478 bx lr 21479 21480 .align 2 21481 .global dvmConfigureFP 21482 .type dvmConfigureFP, %function 21483dvmConfigureFP: 21484 stmfd sp!, {ip, lr} 21485 /* 0x03000000 sets DN/FZ */ 21486 /* 0x00009f00 clears the six exception enable flags */ 21487 bl common_squeak0 21488 mov r0, #0x03000000 @ r0<- 0x03000000 21489 add r1, r0, #0x9f00 @ r1<- 0x03009f00 21490 bl setFPSCR 21491 ldmfd sp!, {ip, pc} 21492#endif 21493 21494 21495/* 21496 * String references, must be close to the code that uses them. 21497 */ 21498 .align 2 21499strDivideByZero: 21500 .word .LstrDivideByZero 21501strLogTag: 21502 .word .LstrLogTag 21503strExceptionNotCaughtLocally: 21504 .word .LstrExceptionNotCaughtLocally 21505 21506strNewline: 21507 .word .LstrNewline 21508strSqueak: 21509 .word .LstrSqueak 21510strPrintHex: 21511 .word .LstrPrintHex 21512strPrintLong: 21513 .word .LstrPrintLong 21514 21515/* 21516 * Zero-terminated ASCII string data. 21517 * 21518 * On ARM we have two choices: do like gcc does, and LDR from a .word 21519 * with the address, or use an ADR pseudo-op to get the address 21520 * directly. ADR saves 4 bytes and an indirection, but it's using a 21521 * PC-relative addressing mode and hence has a limited range, which 21522 * makes it not work well with mergeable string sections. 21523 */ 21524 .section .rodata.str1.4,"aMS",%progbits,1 21525 21526.LstrBadEntryPoint: 21527 .asciz "Bad entry point %d\n" 21528.LstrFilledNewArrayNotImpl: 21529 .asciz "filled-new-array only implemented for objects and 'int'" 21530.LstrDivideByZero: 21531 .asciz "divide by zero" 21532.LstrLogTag: 21533 .asciz "mterp" 21534.LstrExceptionNotCaughtLocally: 21535 .asciz "Exception %s from %s:%d not caught locally\n" 21536 21537.LstrNewline: 21538 .asciz "\n" 21539.LstrSqueak: 21540 .asciz "<%d>" 21541.LstrPrintHex: 21542 .asciz "<0x%x>" 21543.LstrPrintLong: 21544 .asciz "<%lld>" 21545 21546