InterpAsm-armv7-a.S revision 2ff04ab635eeba79c2dad82850c34188abcdfe62
1/* 2 * This file was generated automatically by gen-mterp.py for 'armv7-a'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: armv5te/header.S */ 8/* 9 * Copyright (C) 2008 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 * ARMv5 definitions and declarations. 26 */ 27 28/* 29ARM EABI general notes: 30 31r0-r3 hold first 4 args to a method; they are not preserved across method calls 32r4-r8 are available for general use 33r9 is given special treatment in some situations, but not for us 34r10 (sl) seems to be generally available 35r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36r12 (ip) is scratch -- not preserved across method calls 37r13 (sp) should be managed carefully in case a signal arrives 38r14 (lr) must be preserved 39r15 (pc) can be tinkered with directly 40 41r0 holds returns of <= 4 bytes 42r0-r1 hold returns of 8 bytes, low word in r0 43 44Callee must save/restore r4+ (except r12) if it modifies them. If VFP 45is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46s0-s15 (d0-d7, q0-a3) do not need to be. 47 48Stack is "full descending". Only the arguments that don't fit in the first 4 49registers are placed on the stack. "sp" points at the first stacked argument 50(i.e. the 5th arg). 51 52VFP: single-precision results in s0, double-precision results in d0. 53 54In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 5564-bit quantities (long long, double) must be 64-bit aligned. 56*/ 57 58/* 59Mterp and ARM notes: 60 61The following registers have fixed assignments: 62 63 reg nick purpose 64 r4 rPC interpreted program counter, used for fetching instructions 65 r5 rFP interpreted frame pointer, used for accessing locals and args 66 r6 rSELF self (Thread) pointer 67 r7 rINST first 16-bit code unit of current instruction 68 r8 rIBASE interpreted instruction base pointer, used for computed goto 69 70Macros are provided for common operations. Each macro MUST emit only 71one instruction to make instruction-counting easier. They MUST NOT alter 72unspecified registers or condition codes. 73*/ 74 75/* single-purpose registers, given names for clarity */ 76#define rPC r4 77#define rFP r5 78#define rSELF r6 79#define rINST r7 80#define rIBASE r8 81 82/* save/restore the PC and/or FP from the thread struct */ 83#define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc] 84#define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc] 85#define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_fp] 86#define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_fp] 87#define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP} 88#define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP} 89 90/* 91 * "export" the PC to the stack frame, f/b/o future exception objects. Must 92 * be done *before* something throws. 93 * 94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96 * 97 * It's okay to do this more than once. 98 */ 99#define EXPORT_PC() \ 100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101 102/* 103 * Given a frame pointer, find the stack save area. 104 * 105 * In C this is "((StackSaveArea*)(_fp) -1)". 106 */ 107#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108 sub _reg, _fpreg, #sizeofStackSaveArea 109 110/* 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112 */ 113#define FETCH_INST() ldrh rINST, [rPC] 114 115/* 116 * Fetch the next instruction from the specified offset. Advances rPC 117 * to point to the next instruction. "_count" is in 16-bit code units. 118 * 119 * Because of the limited size of immediate constants on ARM, this is only 120 * suitable for small forward movements (i.e. don't try to implement "goto" 121 * with this). 122 * 123 * This must come AFTER anything that can throw an exception, or the 124 * exception catch may miss. (This also implies that it must come after 125 * EXPORT_PC().) 126 */ 127#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 128 129/* 130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132 */ 133#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134 ldrh _dreg, [_sreg, #(_count*2)]! 135 136/* 137 * Fetch the next instruction from an offset specified by _reg. Updates 138 * rPC to point to the next instruction. "_reg" must specify the distance 139 * in bytes, *not* 16-bit code units, and may be a signed value. 140 * 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 142 * bits that hold the shift distance are used for the half/byte/sign flags. 143 * In some cases we can pre-double _reg for free, so we require a byte offset 144 * here. 145 */ 146#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147 148/* 149 * Fetch a half-word code unit from an offset past the current PC. The 150 * "_count" value is in 16-bit code units. Does not advance rPC. 151 * 152 * The "_S" variant works the same but treats the value as signed. 153 */ 154#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 155#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 156 157/* 158 * Fetch one byte from an offset past the current PC. Pass in the same 159 * "_count" as you would for FETCH, and an additional 0/1 indicating which 160 * byte of the halfword you want (lo/hi). 161 */ 162#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 163 164/* 165 * Put the instruction's opcode field into the specified register. 166 */ 167#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168 169/* 170 * Put the prefetched instruction's opcode field into the specified register. 171 */ 172#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173 174/* 175 * Begin executing the opcode in _reg. Because this only jumps within the 176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177 */ 178#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 180#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 181 182/* 183 * Get/set the 32-bit value from a Dalvik register. 184 */ 185#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 186#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 187 188#if defined(WITH_JIT) 189#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rSELF,#offThread_pJitProfTable] 190#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rSELF,#offThread_jitThreshold] 191#endif 192 193/* 194 * Convert a virtual register index into an address. 195 */ 196#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 197 add _reg, rFP, _vreg, lsl #2 198 199/* 200 * This is a #include, not a %include, because we want the C pre-processor 201 * to expand the macros into assembler assignment statements. 202 */ 203#include "../common/asm-constants.h" 204 205#if defined(WITH_JIT) 206#include "../common/jit-config.h" 207#endif 208 209/* File: armv7-a/platform.S */ 210/* 211 * =========================================================================== 212 * CPU-version-specific defines 213 * =========================================================================== 214 */ 215 216#if !defined(ANDROID_SMP) 217# error "Must define ANDROID_SMP" 218#endif 219 220/* 221 * Macro for data memory barrier. 222 */ 223.macro SMP_DMB 224#if ANDROID_SMP != 0 225 dmb 226#else 227 /* not SMP */ 228#endif 229.endm 230 231/* 232 * Macro for data memory barrier (store/store variant). 233 */ 234.macro SMP_DMB_ST 235#if ANDROID_SMP != 0 236 dmb st 237#else 238 /* not SMP */ 239#endif 240.endm 241 242/* File: armv5te/entry.S */ 243/* 244 * Copyright (C) 2008 The Android Open Source Project 245 * 246 * Licensed under the Apache License, Version 2.0 (the "License"); 247 * you may not use this file except in compliance with the License. 248 * You may obtain a copy of the License at 249 * 250 * http://www.apache.org/licenses/LICENSE-2.0 251 * 252 * Unless required by applicable law or agreed to in writing, software 253 * distributed under the License is distributed on an "AS IS" BASIS, 254 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 255 * See the License for the specific language governing permissions and 256 * limitations under the License. 257 */ 258/* 259 * Interpreter entry point. 260 */ 261 262/* 263 * We don't have formal stack frames, so gdb scans upward in the code 264 * to find the start of the function (a label with the %function type), 265 * and then looks at the next few instructions to figure out what 266 * got pushed onto the stack. From this it figures out how to restore 267 * the registers, including PC, for the previous stack frame. If gdb 268 * sees a non-function label, it stops scanning, so either we need to 269 * have nothing but assembler-local labels between the entry point and 270 * the break, or we need to fake it out. 271 * 272 * When this is defined, we add some stuff to make gdb less confused. 273 */ 274#define ASSIST_DEBUGGER 1 275 276 .text 277 .align 2 278 .global dvmMterpStdRun 279 .type dvmMterpStdRun, %function 280 281/* 282 * On entry: 283 * r0 Thread* self 284 * 285 * This function returns a boolean "changeInterp" value. The return comes 286 * via a call to dvmMterpStdBail(). 287 */ 288dvmMterpStdRun: 289#define MTERP_ENTRY1 \ 290 .save {r4-r10,fp,lr}; \ 291 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 292#define MTERP_ENTRY2 \ 293 .pad #4; \ 294 sub sp, sp, #4 @ align 64 295 296 .fnstart 297 MTERP_ENTRY1 298 MTERP_ENTRY2 299 300 /* save stack pointer, add magic word for debuggerd */ 301 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return 302 303 /* set up "named" registers, figure out entry point */ 304 mov rSELF, r0 @ set rSELF 305 ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI 306 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread" 307 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE 308 cmp r1, #kInterpEntryInstr @ usual case? 309 bne .Lnot_instr @ no, handle it 310 311#if defined(WITH_JIT) 312.LentryInstr: 313 /* Entry is always a possible trace start */ 314 GET_JIT_PROF_TABLE(r0) 315 FETCH_INST() 316 mov r1, #0 @ prepare the value for the new state 317 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 318 cmp r0,#0 @ is profiling disabled? 319#if !defined(WITH_SELF_VERIFICATION) 320 bne common_updateProfile @ profiling is enabled 321#else 322 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state 323 beq 1f @ profiling is disabled 324 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 325 cmp r3, #kSVSTraceSelect @ hot trace following? 326 moveq r2,#kJitTSelectRequestHot @ ask for trace selection 327 beq common_selectTrace @ go build the trace 328 cmp r3, #kSVSNoProfile @ don't profile the next instruction? 329 beq 1f @ intrepret the next instruction 330 b common_updateProfile @ collect profiles 331#endif 3321: 333 GET_INST_OPCODE(ip) 334 GOTO_OPCODE(ip) 335#else 336 /* start executing the instruction at rPC */ 337 FETCH_INST() @ load rINST from rPC 338 GET_INST_OPCODE(ip) @ extract opcode from rINST 339 GOTO_OPCODE(ip) @ jump to next instruction 340#endif 341 342.Lnot_instr: 343 cmp r1, #kInterpEntryReturn @ were we returning from a method? 344 beq common_returnFromMethod 345 346.Lnot_return: 347 cmp r1, #kInterpEntryThrow @ were we throwing an exception? 348 beq common_exceptionThrown 349 350#if defined(WITH_JIT) 351.Lnot_throw: 352 ldr r10,[rSELF, #offThread_jitResumeNPC] 353 ldr r2,[rSELF, #offThread_jitResumeDPC] 354 cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 355 bne .Lbad_arg 356 cmp rPC,r2 357 bne .LentryInstr @ must have branched, don't resume 358#if defined(WITH_SELF_VERIFICATION) 359 @ self->entryPoint will be set in dvmSelfVerificationSaveState 360 b jitSVShadowRunStart @ re-enter the translation after the 361 @ single-stepped instruction 362 @noreturn 363#endif 364 mov r1, #kInterpEntryInstr 365 str r1, [rSELF, #offThread_entryPoint] 366 bx r10 @ re-enter the translation 367#endif 368 369.Lbad_arg: 370 ldr r0, strBadEntryPoint 371 @ r1 holds value of entryPoint 372 bl printf 373 bl dvmAbort 374 .fnend 375 .size dvmMterpStdRun, .-dvmMterpStdRun 376 377 378 .global dvmMterpStdBail 379 .type dvmMterpStdBail, %function 380 381/* 382 * Restore the stack pointer and PC from the save point established on entry. 383 * This is essentially the same as a longjmp, but should be cheaper. The 384 * last instruction causes us to return to whoever called dvmMterpStdRun. 385 * 386 * We pushed some registers on the stack in dvmMterpStdRun, then saved 387 * SP and LR. Here we restore SP, restore the registers, and then restore 388 * LR to PC. 389 * 390 * On entry: 391 * r0 Thread* self 392 * r1 bool changeInterp 393 */ 394dvmMterpStdBail: 395 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP 396 mov r0, r1 @ return the changeInterp value 397 add sp, sp, #4 @ un-align 64 398 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return 399 400 401/* 402 * String references. 403 */ 404strBadEntryPoint: 405 .word .LstrBadEntryPoint 406 407 408 .global dvmAsmInstructionStart 409 .type dvmAsmInstructionStart, %function 410dvmAsmInstructionStart = .L_OP_NOP 411 .text 412 413/* ------------------------------ */ 414 .balign 64 415.L_OP_NOP: /* 0x00 */ 416/* File: armv5te/OP_NOP.S */ 417 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 418 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 419 GOTO_OPCODE(ip) @ execute it 420 421#ifdef ASSIST_DEBUGGER 422 /* insert fake function header to help gdb find the stack frame */ 423 .type dalvik_inst, %function 424dalvik_inst: 425 .fnstart 426 MTERP_ENTRY1 427 MTERP_ENTRY2 428 .fnend 429#endif 430 431/* ------------------------------ */ 432 .balign 64 433.L_OP_MOVE: /* 0x01 */ 434/* File: armv6t2/OP_MOVE.S */ 435 /* for move, move-object, long-to-int */ 436 /* op vA, vB */ 437 mov r1, rINST, lsr #12 @ r1<- B from 15:12 438 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 439 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 440 GET_VREG(r2, r1) @ r2<- fp[B] 441 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 442 SET_VREG(r2, r0) @ fp[A]<- r2 443 GOTO_OPCODE(ip) @ execute next instruction 444 445/* ------------------------------ */ 446 .balign 64 447.L_OP_MOVE_FROM16: /* 0x02 */ 448/* File: armv5te/OP_MOVE_FROM16.S */ 449 /* for: move/from16, move-object/from16 */ 450 /* op vAA, vBBBB */ 451 FETCH(r1, 1) @ r1<- BBBB 452 mov r0, rINST, lsr #8 @ r0<- AA 453 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 454 GET_VREG(r2, r1) @ r2<- fp[BBBB] 455 GET_INST_OPCODE(ip) @ extract opcode from rINST 456 SET_VREG(r2, r0) @ fp[AA]<- r2 457 GOTO_OPCODE(ip) @ jump to next instruction 458 459/* ------------------------------ */ 460 .balign 64 461.L_OP_MOVE_16: /* 0x03 */ 462/* File: armv5te/OP_MOVE_16.S */ 463 /* for: move/16, move-object/16 */ 464 /* op vAAAA, vBBBB */ 465 FETCH(r1, 2) @ r1<- BBBB 466 FETCH(r0, 1) @ r0<- AAAA 467 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 468 GET_VREG(r2, r1) @ r2<- fp[BBBB] 469 GET_INST_OPCODE(ip) @ extract opcode from rINST 470 SET_VREG(r2, r0) @ fp[AAAA]<- r2 471 GOTO_OPCODE(ip) @ jump to next instruction 472 473/* ------------------------------ */ 474 .balign 64 475.L_OP_MOVE_WIDE: /* 0x04 */ 476/* File: armv6t2/OP_MOVE_WIDE.S */ 477 /* move-wide vA, vB */ 478 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 479 mov r3, rINST, lsr #12 @ r3<- B 480 ubfx r2, rINST, #8, #4 @ r2<- A 481 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 482 add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 483 ldmia r3, {r0-r1} @ r0/r1<- fp[B] 484 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 485 GET_INST_OPCODE(ip) @ extract opcode from rINST 486 stmia r2, {r0-r1} @ fp[A]<- r0/r1 487 GOTO_OPCODE(ip) @ jump to next instruction 488 489/* ------------------------------ */ 490 .balign 64 491.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 492/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 493 /* move-wide/from16 vAA, vBBBB */ 494 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 495 FETCH(r3, 1) @ r3<- BBBB 496 mov r2, rINST, lsr #8 @ r2<- AA 497 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 498 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 499 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 501 GET_INST_OPCODE(ip) @ extract opcode from rINST 502 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 503 GOTO_OPCODE(ip) @ jump to next instruction 504 505/* ------------------------------ */ 506 .balign 64 507.L_OP_MOVE_WIDE_16: /* 0x06 */ 508/* File: armv5te/OP_MOVE_WIDE_16.S */ 509 /* move-wide/16 vAAAA, vBBBB */ 510 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 511 FETCH(r3, 2) @ r3<- BBBB 512 FETCH(r2, 1) @ r2<- AAAA 513 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 514 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 515 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 516 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 517 GET_INST_OPCODE(ip) @ extract opcode from rINST 518 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 519 GOTO_OPCODE(ip) @ jump to next instruction 520 521/* ------------------------------ */ 522 .balign 64 523.L_OP_MOVE_OBJECT: /* 0x07 */ 524/* File: armv5te/OP_MOVE_OBJECT.S */ 525/* File: armv5te/OP_MOVE.S */ 526 /* for move, move-object, long-to-int */ 527 /* op vA, vB */ 528 mov r1, rINST, lsr #12 @ r1<- B from 15:12 529 mov r0, rINST, lsr #8 @ r0<- A from 11:8 530 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 531 GET_VREG(r2, r1) @ r2<- fp[B] 532 and r0, r0, #15 533 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 534 SET_VREG(r2, r0) @ fp[A]<- r2 535 GOTO_OPCODE(ip) @ execute next instruction 536 537 538/* ------------------------------ */ 539 .balign 64 540.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 541/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 542/* File: armv5te/OP_MOVE_FROM16.S */ 543 /* for: move/from16, move-object/from16 */ 544 /* op vAA, vBBBB */ 545 FETCH(r1, 1) @ r1<- BBBB 546 mov r0, rINST, lsr #8 @ r0<- AA 547 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 548 GET_VREG(r2, r1) @ r2<- fp[BBBB] 549 GET_INST_OPCODE(ip) @ extract opcode from rINST 550 SET_VREG(r2, r0) @ fp[AA]<- r2 551 GOTO_OPCODE(ip) @ jump to next instruction 552 553 554/* ------------------------------ */ 555 .balign 64 556.L_OP_MOVE_OBJECT_16: /* 0x09 */ 557/* File: armv5te/OP_MOVE_OBJECT_16.S */ 558/* File: armv5te/OP_MOVE_16.S */ 559 /* for: move/16, move-object/16 */ 560 /* op vAAAA, vBBBB */ 561 FETCH(r1, 2) @ r1<- BBBB 562 FETCH(r0, 1) @ r0<- AAAA 563 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 564 GET_VREG(r2, r1) @ r2<- fp[BBBB] 565 GET_INST_OPCODE(ip) @ extract opcode from rINST 566 SET_VREG(r2, r0) @ fp[AAAA]<- r2 567 GOTO_OPCODE(ip) @ jump to next instruction 568 569 570/* ------------------------------ */ 571 .balign 64 572.L_OP_MOVE_RESULT: /* 0x0a */ 573/* File: armv5te/OP_MOVE_RESULT.S */ 574 /* for: move-result, move-result-object */ 575 /* op vAA */ 576 mov r2, rINST, lsr #8 @ r2<- AA 577 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 578 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 579 GET_INST_OPCODE(ip) @ extract opcode from rINST 580 SET_VREG(r0, r2) @ fp[AA]<- r0 581 GOTO_OPCODE(ip) @ jump to next instruction 582 583/* ------------------------------ */ 584 .balign 64 585.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 586/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 587 /* move-result-wide vAA */ 588 mov r2, rINST, lsr #8 @ r2<- AA 589 add r3, rSELF, #offThread_retval @ r3<- &self->retval 590 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 591 ldmia r3, {r0-r1} @ r0/r1<- retval.j 592 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 593 GET_INST_OPCODE(ip) @ extract opcode from rINST 594 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 595 GOTO_OPCODE(ip) @ jump to next instruction 596 597/* ------------------------------ */ 598 .balign 64 599.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 600/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 601/* File: armv5te/OP_MOVE_RESULT.S */ 602 /* for: move-result, move-result-object */ 603 /* op vAA */ 604 mov r2, rINST, lsr #8 @ r2<- AA 605 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 606 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 607 GET_INST_OPCODE(ip) @ extract opcode from rINST 608 SET_VREG(r0, r2) @ fp[AA]<- r0 609 GOTO_OPCODE(ip) @ jump to next instruction 610 611 612/* ------------------------------ */ 613 .balign 64 614.L_OP_MOVE_EXCEPTION: /* 0x0d */ 615/* File: armv5te/OP_MOVE_EXCEPTION.S */ 616 /* move-exception vAA */ 617 mov r2, rINST, lsr #8 @ r2<- AA 618 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass 619 mov r1, #0 @ r1<- 0 620 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 621 SET_VREG(r3, r2) @ fp[AA]<- exception obj 622 GET_INST_OPCODE(ip) @ extract opcode from rINST 623 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass 624 GOTO_OPCODE(ip) @ jump to next instruction 625 626/* ------------------------------ */ 627 .balign 64 628.L_OP_RETURN_VOID: /* 0x0e */ 629/* File: armv5te/OP_RETURN_VOID.S */ 630 b common_returnFromMethod 631 632/* ------------------------------ */ 633 .balign 64 634.L_OP_RETURN: /* 0x0f */ 635/* File: armv5te/OP_RETURN.S */ 636 /* 637 * Return a 32-bit value. Copies the return value into the "thread" 638 * structure, then jumps to the return handler. 639 * 640 * for: return, return-object 641 */ 642 /* op vAA */ 643 mov r2, rINST, lsr #8 @ r2<- AA 644 GET_VREG(r0, r2) @ r0<- vAA 645 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 646 b common_returnFromMethod 647 648/* ------------------------------ */ 649 .balign 64 650.L_OP_RETURN_WIDE: /* 0x10 */ 651/* File: armv5te/OP_RETURN_WIDE.S */ 652 /* 653 * Return a 64-bit value. Copies the return value into the "thread" 654 * structure, then jumps to the return handler. 655 */ 656 /* return-wide vAA */ 657 mov r2, rINST, lsr #8 @ r2<- AA 658 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 659 add r3, rSELF, #offThread_retval @ r3<- &self->retval 660 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 661 stmia r3, {r0-r1} @ retval<- r0/r1 662 b common_returnFromMethod 663 664/* ------------------------------ */ 665 .balign 64 666.L_OP_RETURN_OBJECT: /* 0x11 */ 667/* File: armv5te/OP_RETURN_OBJECT.S */ 668/* File: armv5te/OP_RETURN.S */ 669 /* 670 * Return a 32-bit value. Copies the return value into the "thread" 671 * structure, then jumps to the return handler. 672 * 673 * for: return, return-object 674 */ 675 /* op vAA */ 676 mov r2, rINST, lsr #8 @ r2<- AA 677 GET_VREG(r0, r2) @ r0<- vAA 678 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 679 b common_returnFromMethod 680 681 682/* ------------------------------ */ 683 .balign 64 684.L_OP_CONST_4: /* 0x12 */ 685/* File: armv6t2/OP_CONST_4.S */ 686 /* const/4 vA, #+B */ 687 mov r1, rINST, lsl #16 @ r1<- Bxxx0000 688 ubfx r0, rINST, #8, #4 @ r0<- A 689 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 690 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 691 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 692 SET_VREG(r1, r0) @ fp[A]<- r1 693 GOTO_OPCODE(ip) @ execute next instruction 694 695/* ------------------------------ */ 696 .balign 64 697.L_OP_CONST_16: /* 0x13 */ 698/* File: armv5te/OP_CONST_16.S */ 699 /* const/16 vAA, #+BBBB */ 700 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 701 mov r3, rINST, lsr #8 @ r3<- AA 702 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 703 SET_VREG(r0, r3) @ vAA<- r0 704 GET_INST_OPCODE(ip) @ extract opcode from rINST 705 GOTO_OPCODE(ip) @ jump to next instruction 706 707/* ------------------------------ */ 708 .balign 64 709.L_OP_CONST: /* 0x14 */ 710/* File: armv5te/OP_CONST.S */ 711 /* const vAA, #+BBBBbbbb */ 712 mov r3, rINST, lsr #8 @ r3<- AA 713 FETCH(r0, 1) @ r0<- bbbb (low) 714 FETCH(r1, 2) @ r1<- BBBB (high) 715 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 716 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 717 GET_INST_OPCODE(ip) @ extract opcode from rINST 718 SET_VREG(r0, r3) @ vAA<- r0 719 GOTO_OPCODE(ip) @ jump to next instruction 720 721/* ------------------------------ */ 722 .balign 64 723.L_OP_CONST_HIGH16: /* 0x15 */ 724/* File: armv5te/OP_CONST_HIGH16.S */ 725 /* const/high16 vAA, #+BBBB0000 */ 726 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 727 mov r3, rINST, lsr #8 @ r3<- AA 728 mov r0, r0, lsl #16 @ r0<- BBBB0000 729 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 730 SET_VREG(r0, r3) @ vAA<- r0 731 GET_INST_OPCODE(ip) @ extract opcode from rINST 732 GOTO_OPCODE(ip) @ jump to next instruction 733 734/* ------------------------------ */ 735 .balign 64 736.L_OP_CONST_WIDE_16: /* 0x16 */ 737/* File: armv5te/OP_CONST_WIDE_16.S */ 738 /* const-wide/16 vAA, #+BBBB */ 739 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 740 mov r3, rINST, lsr #8 @ r3<- AA 741 mov r1, r0, asr #31 @ r1<- ssssssss 742 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 743 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 744 GET_INST_OPCODE(ip) @ extract opcode from rINST 745 stmia r3, {r0-r1} @ vAA<- r0/r1 746 GOTO_OPCODE(ip) @ jump to next instruction 747 748/* ------------------------------ */ 749 .balign 64 750.L_OP_CONST_WIDE_32: /* 0x17 */ 751/* File: armv5te/OP_CONST_WIDE_32.S */ 752 /* const-wide/32 vAA, #+BBBBbbbb */ 753 FETCH(r0, 1) @ r0<- 0000bbbb (low) 754 mov r3, rINST, lsr #8 @ r3<- AA 755 FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 756 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 757 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 758 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 759 mov r1, r0, asr #31 @ r1<- ssssssss 760 GET_INST_OPCODE(ip) @ extract opcode from rINST 761 stmia r3, {r0-r1} @ vAA<- r0/r1 762 GOTO_OPCODE(ip) @ jump to next instruction 763 764/* ------------------------------ */ 765 .balign 64 766.L_OP_CONST_WIDE: /* 0x18 */ 767/* File: armv5te/OP_CONST_WIDE.S */ 768 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 769 FETCH(r0, 1) @ r0<- bbbb (low) 770 FETCH(r1, 2) @ r1<- BBBB (low middle) 771 FETCH(r2, 3) @ r2<- hhhh (high middle) 772 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 773 FETCH(r3, 4) @ r3<- HHHH (high) 774 mov r9, rINST, lsr #8 @ r9<- AA 775 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 776 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 777 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 778 GET_INST_OPCODE(ip) @ extract opcode from rINST 779 stmia r9, {r0-r1} @ vAA<- r0/r1 780 GOTO_OPCODE(ip) @ jump to next instruction 781 782/* ------------------------------ */ 783 .balign 64 784.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 785/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 786 /* const-wide/high16 vAA, #+BBBB000000000000 */ 787 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 788 mov r3, rINST, lsr #8 @ r3<- AA 789 mov r0, #0 @ r0<- 00000000 790 mov r1, r1, lsl #16 @ r1<- BBBB0000 791 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 792 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 793 GET_INST_OPCODE(ip) @ extract opcode from rINST 794 stmia r3, {r0-r1} @ vAA<- r0/r1 795 GOTO_OPCODE(ip) @ jump to next instruction 796 797/* ------------------------------ */ 798 .balign 64 799.L_OP_CONST_STRING: /* 0x1a */ 800/* File: armv5te/OP_CONST_STRING.S */ 801 /* const/string vAA, String@BBBB */ 802 FETCH(r1, 1) @ r1<- BBBB 803 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 804 mov r9, rINST, lsr #8 @ r9<- AA 805 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 806 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 807 cmp r0, #0 @ not yet resolved? 808 beq .LOP_CONST_STRING_resolve 809 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 810 GET_INST_OPCODE(ip) @ extract opcode from rINST 811 SET_VREG(r0, r9) @ vAA<- r0 812 GOTO_OPCODE(ip) @ jump to next instruction 813 814/* ------------------------------ */ 815 .balign 64 816.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 817/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 818 /* const/string vAA, String@BBBBBBBB */ 819 FETCH(r0, 1) @ r0<- bbbb (low) 820 FETCH(r1, 2) @ r1<- BBBB (high) 821 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 822 mov r9, rINST, lsr #8 @ r9<- AA 823 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 824 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 825 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 826 cmp r0, #0 827 beq .LOP_CONST_STRING_JUMBO_resolve 828 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 829 GET_INST_OPCODE(ip) @ extract opcode from rINST 830 SET_VREG(r0, r9) @ vAA<- r0 831 GOTO_OPCODE(ip) @ jump to next instruction 832 833/* ------------------------------ */ 834 .balign 64 835.L_OP_CONST_CLASS: /* 0x1c */ 836/* File: armv5te/OP_CONST_CLASS.S */ 837 /* const/class vAA, Class@BBBB */ 838 FETCH(r1, 1) @ r1<- BBBB 839 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 840 mov r9, rINST, lsr #8 @ r9<- AA 841 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 842 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 843 cmp r0, #0 @ not yet resolved? 844 beq .LOP_CONST_CLASS_resolve 845 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 846 GET_INST_OPCODE(ip) @ extract opcode from rINST 847 SET_VREG(r0, r9) @ vAA<- r0 848 GOTO_OPCODE(ip) @ jump to next instruction 849 850/* ------------------------------ */ 851 .balign 64 852.L_OP_MONITOR_ENTER: /* 0x1d */ 853/* File: armv5te/OP_MONITOR_ENTER.S */ 854 /* 855 * Synchronize on an object. 856 */ 857 /* monitor-enter vAA */ 858 mov r2, rINST, lsr #8 @ r2<- AA 859 GET_VREG(r1, r2) @ r1<- vAA (object) 860 mov r0, rSELF @ r0<- self 861 cmp r1, #0 @ null object? 862 EXPORT_PC() @ need for precise GC 863 beq common_errNullObject @ null object, throw an exception 864 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 865 bl dvmLockObject @ call(self, obj) 866 GET_INST_OPCODE(ip) @ extract opcode from rINST 867 GOTO_OPCODE(ip) @ jump to next instruction 868 869/* ------------------------------ */ 870 .balign 64 871.L_OP_MONITOR_EXIT: /* 0x1e */ 872/* File: armv5te/OP_MONITOR_EXIT.S */ 873 /* 874 * Unlock an object. 875 * 876 * Exceptions that occur when unlocking a monitor need to appear as 877 * if they happened at the following instruction. See the Dalvik 878 * instruction spec. 879 */ 880 /* monitor-exit vAA */ 881 mov r2, rINST, lsr #8 @ r2<- AA 882 EXPORT_PC() @ before fetch: export the PC 883 GET_VREG(r1, r2) @ r1<- vAA (object) 884 cmp r1, #0 @ null object? 885 beq 1f @ yes 886 mov r0, rSELF @ r0<- self 887 bl dvmUnlockObject @ r0<- success for unlock(self, obj) 888 cmp r0, #0 @ failed? 889 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 890 beq common_exceptionThrown @ yes, exception is pending 891 GET_INST_OPCODE(ip) @ extract opcode from rINST 892 GOTO_OPCODE(ip) @ jump to next instruction 8931: 894 FETCH_ADVANCE_INST(1) @ advance before throw 895 b common_errNullObject 896 897/* ------------------------------ */ 898 .balign 64 899.L_OP_CHECK_CAST: /* 0x1f */ 900/* File: armv5te/OP_CHECK_CAST.S */ 901 /* 902 * Check to see if a cast from one class to another is allowed. 903 */ 904 /* check-cast vAA, class@BBBB */ 905 mov r3, rINST, lsr #8 @ r3<- AA 906 FETCH(r2, 1) @ r2<- BBBB 907 GET_VREG(r9, r3) @ r9<- object 908 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 909 cmp r9, #0 @ is object null? 910 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 911 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 912 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 913 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 914 cmp r1, #0 @ have we resolved this before? 915 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 916.LOP_CHECK_CAST_resolved: 917 cmp r0, r1 @ same class (trivial success)? 918 bne .LOP_CHECK_CAST_fullcheck @ no, do full check 919.LOP_CHECK_CAST_okay: 920 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 921 GET_INST_OPCODE(ip) @ extract opcode from rINST 922 GOTO_OPCODE(ip) @ jump to next instruction 923 924/* ------------------------------ */ 925 .balign 64 926.L_OP_INSTANCE_OF: /* 0x20 */ 927/* File: armv5te/OP_INSTANCE_OF.S */ 928 /* 929 * Check to see if an object reference is an instance of a class. 930 * 931 * Most common situation is a non-null object, being compared against 932 * an already-resolved class. 933 */ 934 /* instance-of vA, vB, class@CCCC */ 935 mov r3, rINST, lsr #12 @ r3<- B 936 mov r9, rINST, lsr #8 @ r9<- A+ 937 GET_VREG(r0, r3) @ r0<- vB (object) 938 and r9, r9, #15 @ r9<- A 939 cmp r0, #0 @ is object null? 940 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 941 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 942 FETCH(r3, 1) @ r3<- CCCC 943 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 944 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 945 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 946 cmp r1, #0 @ have we resolved this before? 947 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 948.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 949 cmp r0, r1 @ same class (trivial success)? 950 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 951 b .LOP_INSTANCE_OF_fullcheck @ no, do full check 952 953/* ------------------------------ */ 954 .balign 64 955.L_OP_ARRAY_LENGTH: /* 0x21 */ 956/* File: armv6t2/OP_ARRAY_LENGTH.S */ 957 /* 958 * Return the length of an array. 959 */ 960 mov r1, rINST, lsr #12 @ r1<- B 961 ubfx r2, rINST, #8, #4 @ r2<- A 962 GET_VREG(r0, r1) @ r0<- vB (object ref) 963 cmp r0, #0 @ is object null? 964 beq common_errNullObject @ yup, fail 965 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 966 ldr r3, [r0, #offArrayObject_length] @ r3<- array length 967 GET_INST_OPCODE(ip) @ extract opcode from rINST 968 SET_VREG(r3, r2) @ vB<- length 969 GOTO_OPCODE(ip) @ jump to next instruction 970 971/* ------------------------------ */ 972 .balign 64 973.L_OP_NEW_INSTANCE: /* 0x22 */ 974/* File: armv5te/OP_NEW_INSTANCE.S */ 975 /* 976 * Create a new instance of a class. 977 */ 978 /* new-instance vAA, class@BBBB */ 979 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 980 FETCH(r1, 1) @ r1<- BBBB 981 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 982 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 983 EXPORT_PC() @ req'd for init, resolve, alloc 984 cmp r0, #0 @ already resolved? 985 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 986.LOP_NEW_INSTANCE_resolved: @ r0=class 987 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 988 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 989 bne .LOP_NEW_INSTANCE_needinit @ no, init class now 990.LOP_NEW_INSTANCE_initialized: @ r0=class 991 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 992 bl dvmAllocObject @ r0<- new object 993 b .LOP_NEW_INSTANCE_finish @ continue 994 995/* ------------------------------ */ 996 .balign 64 997.L_OP_NEW_ARRAY: /* 0x23 */ 998/* File: armv5te/OP_NEW_ARRAY.S */ 999 /* 1000 * Allocate an array of objects, specified with the array class 1001 * and a count. 1002 * 1003 * The verifier guarantees that this is an array class, so we don't 1004 * check for it here. 1005 */ 1006 /* new-array vA, vB, class@CCCC */ 1007 mov r0, rINST, lsr #12 @ r0<- B 1008 FETCH(r2, 1) @ r2<- CCCC 1009 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1010 GET_VREG(r1, r0) @ r1<- vB (array length) 1011 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1012 cmp r1, #0 @ check length 1013 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1014 bmi common_errNegativeArraySize @ negative length, bail - len in r1 1015 cmp r0, #0 @ already resolved? 1016 EXPORT_PC() @ req'd for resolve, alloc 1017 bne .LOP_NEW_ARRAY_finish @ resolved, continue 1018 b .LOP_NEW_ARRAY_resolve @ do resolve now 1019 1020/* ------------------------------ */ 1021 .balign 64 1022.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1023/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1024 /* 1025 * Create a new array with elements filled from registers. 1026 * 1027 * for: filled-new-array, filled-new-array/range 1028 */ 1029 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1030 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1031 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1032 FETCH(r1, 1) @ r1<- BBBB 1033 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1034 EXPORT_PC() @ need for resolve and alloc 1035 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1036 mov r10, rINST, lsr #8 @ r10<- AA or BA 1037 cmp r0, #0 @ already resolved? 1038 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 10398: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1040 mov r2, #0 @ r2<- false 1041 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1042 bl dvmResolveClass @ r0<- call(clazz, ref) 1043 cmp r0, #0 @ got null? 1044 beq common_exceptionThrown @ yes, handle exception 1045 b .LOP_FILLED_NEW_ARRAY_continue 1046 1047/* ------------------------------ */ 1048 .balign 64 1049.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1050/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1051/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1052 /* 1053 * Create a new array with elements filled from registers. 1054 * 1055 * for: filled-new-array, filled-new-array/range 1056 */ 1057 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1058 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1059 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1060 FETCH(r1, 1) @ r1<- BBBB 1061 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1062 EXPORT_PC() @ need for resolve and alloc 1063 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1064 mov r10, rINST, lsr #8 @ r10<- AA or BA 1065 cmp r0, #0 @ already resolved? 1066 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 10678: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1068 mov r2, #0 @ r2<- false 1069 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1070 bl dvmResolveClass @ r0<- call(clazz, ref) 1071 cmp r0, #0 @ got null? 1072 beq common_exceptionThrown @ yes, handle exception 1073 b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1074 1075 1076/* ------------------------------ */ 1077 .balign 64 1078.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1079/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1080 /* fill-array-data vAA, +BBBBBBBB */ 1081 FETCH(r0, 1) @ r0<- bbbb (lo) 1082 FETCH(r1, 2) @ r1<- BBBB (hi) 1083 mov r3, rINST, lsr #8 @ r3<- AA 1084 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1085 GET_VREG(r0, r3) @ r0<- vAA (array object) 1086 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1087 EXPORT_PC(); 1088 bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1089 cmp r0, #0 @ 0 means an exception is thrown 1090 beq common_exceptionThrown @ has exception 1091 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1092 GET_INST_OPCODE(ip) @ extract opcode from rINST 1093 GOTO_OPCODE(ip) @ jump to next instruction 1094 1095/* ------------------------------ */ 1096 .balign 64 1097.L_OP_THROW: /* 0x27 */ 1098/* File: armv5te/OP_THROW.S */ 1099 /* 1100 * Throw an exception object in the current thread. 1101 */ 1102 /* throw vAA */ 1103 mov r2, rINST, lsr #8 @ r2<- AA 1104 GET_VREG(r1, r2) @ r1<- vAA (exception object) 1105 EXPORT_PC() @ exception handler can throw 1106 cmp r1, #0 @ null object? 1107 beq common_errNullObject @ yes, throw an NPE instead 1108 @ bypass dvmSetException, just store it 1109 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj 1110 b common_exceptionThrown 1111 1112/* ------------------------------ */ 1113 .balign 64 1114.L_OP_GOTO: /* 0x28 */ 1115/* File: armv5te/OP_GOTO.S */ 1116 /* 1117 * Unconditional branch, 8-bit offset. 1118 * 1119 * The branch distance is a signed code-unit offset, which we need to 1120 * double to get a byte offset. 1121 */ 1122 /* goto +AA */ 1123 mov r0, rINST, lsl #16 @ r0<- AAxx0000 1124 movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1125 mov r9, r9, lsl #1 @ r9<- byte offset 1126 bmi common_backwardBranch @ backward branch, do periodic checks 1127#if defined(WITH_JIT) 1128 GET_JIT_PROF_TABLE(r0) 1129 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1130 cmp r0,#0 1131 bne common_updateProfile 1132 GET_INST_OPCODE(ip) @ extract opcode from rINST 1133 GOTO_OPCODE(ip) @ jump to next instruction 1134#else 1135 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1136 GET_INST_OPCODE(ip) @ extract opcode from rINST 1137 GOTO_OPCODE(ip) @ jump to next instruction 1138#endif 1139 1140/* ------------------------------ */ 1141 .balign 64 1142.L_OP_GOTO_16: /* 0x29 */ 1143/* File: armv5te/OP_GOTO_16.S */ 1144 /* 1145 * Unconditional branch, 16-bit offset. 1146 * 1147 * The branch distance is a signed code-unit offset, which we need to 1148 * double to get a byte offset. 1149 */ 1150 /* goto/16 +AAAA */ 1151 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1152 movs r9, r0, asl #1 @ r9<- byte offset, check sign 1153 bmi common_backwardBranch @ backward branch, do periodic checks 1154#if defined(WITH_JIT) 1155 GET_JIT_PROF_TABLE(r0) 1156 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1157 cmp r0,#0 1158 bne common_updateProfile 1159 GET_INST_OPCODE(ip) @ extract opcode from rINST 1160 GOTO_OPCODE(ip) @ jump to next instruction 1161#else 1162 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1163 GET_INST_OPCODE(ip) @ extract opcode from rINST 1164 GOTO_OPCODE(ip) @ jump to next instruction 1165#endif 1166 1167/* ------------------------------ */ 1168 .balign 64 1169.L_OP_GOTO_32: /* 0x2a */ 1170/* File: armv5te/OP_GOTO_32.S */ 1171 /* 1172 * Unconditional branch, 32-bit offset. 1173 * 1174 * The branch distance is a signed code-unit offset, which we need to 1175 * double to get a byte offset. 1176 * 1177 * Unlike most opcodes, this one is allowed to branch to itself, so 1178 * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1179 * instruction doesn't affect the V flag, so we need to clear it 1180 * explicitly. 1181 */ 1182 /* goto/32 +AAAAAAAA */ 1183 FETCH(r0, 1) @ r0<- aaaa (lo) 1184 FETCH(r1, 2) @ r1<- AAAA (hi) 1185 cmp ip, ip @ (clear V flag during stall) 1186 orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1187 mov r9, r0, asl #1 @ r9<- byte offset 1188 ble common_backwardBranch @ backward branch, do periodic checks 1189#if defined(WITH_JIT) 1190 GET_JIT_PROF_TABLE(r0) 1191 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1192 cmp r0,#0 1193 bne common_updateProfile 1194 GET_INST_OPCODE(ip) @ extract opcode from rINST 1195 GOTO_OPCODE(ip) @ jump to next instruction 1196#else 1197 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1198 GET_INST_OPCODE(ip) @ extract opcode from rINST 1199 GOTO_OPCODE(ip) @ jump to next instruction 1200#endif 1201 1202/* ------------------------------ */ 1203 .balign 64 1204.L_OP_PACKED_SWITCH: /* 0x2b */ 1205/* File: armv5te/OP_PACKED_SWITCH.S */ 1206 /* 1207 * Handle a packed-switch or sparse-switch instruction. In both cases 1208 * we decode it and hand it off to a helper function. 1209 * 1210 * We don't really expect backward branches in a switch statement, but 1211 * they're perfectly legal, so we check for them here. 1212 * 1213 * for: packed-switch, sparse-switch 1214 */ 1215 /* op vAA, +BBBB */ 1216 FETCH(r0, 1) @ r0<- bbbb (lo) 1217 FETCH(r1, 2) @ r1<- BBBB (hi) 1218 mov r3, rINST, lsr #8 @ r3<- AA 1219 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1220 GET_VREG(r1, r3) @ r1<- vAA 1221 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1222 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1223 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1224 bmi common_backwardBranch @ backward branch, do periodic checks 1225 beq common_backwardBranch @ (want to use BLE but V is unknown) 1226#if defined(WITH_JIT) 1227 GET_JIT_PROF_TABLE(r0) 1228 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1229 cmp r0,#0 1230 bne common_updateProfile 1231 GET_INST_OPCODE(ip) @ extract opcode from rINST 1232 GOTO_OPCODE(ip) @ jump to next instruction 1233#else 1234 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1235 GET_INST_OPCODE(ip) @ extract opcode from rINST 1236 GOTO_OPCODE(ip) @ jump to next instruction 1237#endif 1238 1239/* ------------------------------ */ 1240 .balign 64 1241.L_OP_SPARSE_SWITCH: /* 0x2c */ 1242/* File: armv5te/OP_SPARSE_SWITCH.S */ 1243/* File: armv5te/OP_PACKED_SWITCH.S */ 1244 /* 1245 * Handle a packed-switch or sparse-switch instruction. In both cases 1246 * we decode it and hand it off to a helper function. 1247 * 1248 * We don't really expect backward branches in a switch statement, but 1249 * they're perfectly legal, so we check for them here. 1250 * 1251 * for: packed-switch, sparse-switch 1252 */ 1253 /* op vAA, +BBBB */ 1254 FETCH(r0, 1) @ r0<- bbbb (lo) 1255 FETCH(r1, 2) @ r1<- BBBB (hi) 1256 mov r3, rINST, lsr #8 @ r3<- AA 1257 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1258 GET_VREG(r1, r3) @ r1<- vAA 1259 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1260 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1261 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1262 bmi common_backwardBranch @ backward branch, do periodic checks 1263 beq common_backwardBranch @ (want to use BLE but V is unknown) 1264#if defined(WITH_JIT) 1265 GET_JIT_PROF_TABLE(r0) 1266 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1267 cmp r0,#0 1268 bne common_updateProfile 1269 GET_INST_OPCODE(ip) @ extract opcode from rINST 1270 GOTO_OPCODE(ip) @ jump to next instruction 1271#else 1272 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1273 GET_INST_OPCODE(ip) @ extract opcode from rINST 1274 GOTO_OPCODE(ip) @ jump to next instruction 1275#endif 1276 1277 1278/* ------------------------------ */ 1279 .balign 64 1280.L_OP_CMPL_FLOAT: /* 0x2d */ 1281/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1282 /* 1283 * Compare two floating-point values. Puts 0, 1, or -1 into the 1284 * destination register based on the results of the comparison. 1285 * 1286 * int compare(x, y) { 1287 * if (x == y) { 1288 * return 0; 1289 * } else if (x > y) { 1290 * return 1; 1291 * } else if (x < y) { 1292 * return -1; 1293 * } else { 1294 * return -1; 1295 * } 1296 * } 1297 */ 1298 /* op vAA, vBB, vCC */ 1299 FETCH(r0, 1) @ r0<- CCBB 1300 mov r9, rINST, lsr #8 @ r9<- AA 1301 and r2, r0, #255 @ r2<- BB 1302 mov r3, r0, lsr #8 @ r3<- CC 1303 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1304 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1305 flds s0, [r2] @ s0<- vBB 1306 flds s1, [r3] @ s1<- vCC 1307 fcmpes s0, s1 @ compare (vBB, vCC) 1308 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1309 mvn r0, #0 @ r0<- -1 (default) 1310 GET_INST_OPCODE(ip) @ extract opcode from rINST 1311 fmstat @ export status flags 1312 movgt r0, #1 @ (greater than) r1<- 1 1313 moveq r0, #0 @ (equal) r1<- 0 1314 b .LOP_CMPL_FLOAT_finish @ argh 1315 1316 1317/* ------------------------------ */ 1318 .balign 64 1319.L_OP_CMPG_FLOAT: /* 0x2e */ 1320/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1321 /* 1322 * Compare two floating-point values. Puts 0, 1, or -1 into the 1323 * destination register based on the results of the comparison. 1324 * 1325 * int compare(x, y) { 1326 * if (x == y) { 1327 * return 0; 1328 * } else if (x < y) { 1329 * return -1; 1330 * } else if (x > y) { 1331 * return 1; 1332 * } else { 1333 * return 1; 1334 * } 1335 * } 1336 */ 1337 /* op vAA, vBB, vCC */ 1338 FETCH(r0, 1) @ r0<- CCBB 1339 mov r9, rINST, lsr #8 @ r9<- AA 1340 and r2, r0, #255 @ r2<- BB 1341 mov r3, r0, lsr #8 @ r3<- CC 1342 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1343 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1344 flds s0, [r2] @ s0<- vBB 1345 flds s1, [r3] @ s1<- vCC 1346 fcmpes s0, s1 @ compare (vBB, vCC) 1347 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1348 mov r0, #1 @ r0<- 1 (default) 1349 GET_INST_OPCODE(ip) @ extract opcode from rINST 1350 fmstat @ export status flags 1351 mvnmi r0, #0 @ (less than) r1<- -1 1352 moveq r0, #0 @ (equal) r1<- 0 1353 b .LOP_CMPG_FLOAT_finish @ argh 1354 1355 1356/* ------------------------------ */ 1357 .balign 64 1358.L_OP_CMPL_DOUBLE: /* 0x2f */ 1359/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1360 /* 1361 * Compare two floating-point values. Puts 0, 1, or -1 into the 1362 * destination register based on the results of the comparison. 1363 * 1364 * int compare(x, y) { 1365 * if (x == y) { 1366 * return 0; 1367 * } else if (x > y) { 1368 * return 1; 1369 * } else if (x < y) { 1370 * return -1; 1371 * } else { 1372 * return -1; 1373 * } 1374 * } 1375 */ 1376 /* op vAA, vBB, vCC */ 1377 FETCH(r0, 1) @ r0<- CCBB 1378 mov r9, rINST, lsr #8 @ r9<- AA 1379 and r2, r0, #255 @ r2<- BB 1380 mov r3, r0, lsr #8 @ r3<- CC 1381 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1382 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1383 fldd d0, [r2] @ d0<- vBB 1384 fldd d1, [r3] @ d1<- vCC 1385 fcmped d0, d1 @ compare (vBB, vCC) 1386 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1387 mvn r0, #0 @ r0<- -1 (default) 1388 GET_INST_OPCODE(ip) @ extract opcode from rINST 1389 fmstat @ export status flags 1390 movgt r0, #1 @ (greater than) r1<- 1 1391 moveq r0, #0 @ (equal) r1<- 0 1392 b .LOP_CMPL_DOUBLE_finish @ argh 1393 1394 1395/* ------------------------------ */ 1396 .balign 64 1397.L_OP_CMPG_DOUBLE: /* 0x30 */ 1398/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1399 /* 1400 * Compare two floating-point values. Puts 0, 1, or -1 into the 1401 * destination register based on the results of the comparison. 1402 * 1403 * int compare(x, y) { 1404 * if (x == y) { 1405 * return 0; 1406 * } else if (x < y) { 1407 * return -1; 1408 * } else if (x > y) { 1409 * return 1; 1410 * } else { 1411 * return 1; 1412 * } 1413 * } 1414 */ 1415 /* op vAA, vBB, vCC */ 1416 FETCH(r0, 1) @ r0<- CCBB 1417 mov r9, rINST, lsr #8 @ r9<- AA 1418 and r2, r0, #255 @ r2<- BB 1419 mov r3, r0, lsr #8 @ r3<- CC 1420 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1421 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1422 fldd d0, [r2] @ d0<- vBB 1423 fldd d1, [r3] @ d1<- vCC 1424 fcmped d0, d1 @ compare (vBB, vCC) 1425 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1426 mov r0, #1 @ r0<- 1 (default) 1427 GET_INST_OPCODE(ip) @ extract opcode from rINST 1428 fmstat @ export status flags 1429 mvnmi r0, #0 @ (less than) r1<- -1 1430 moveq r0, #0 @ (equal) r1<- 0 1431 b .LOP_CMPG_DOUBLE_finish @ argh 1432 1433 1434/* ------------------------------ */ 1435 .balign 64 1436.L_OP_CMP_LONG: /* 0x31 */ 1437/* File: armv5te/OP_CMP_LONG.S */ 1438 /* 1439 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1440 * register based on the results of the comparison. 1441 * 1442 * We load the full values with LDM, but in practice many values could 1443 * be resolved by only looking at the high word. This could be made 1444 * faster or slower by splitting the LDM into a pair of LDRs. 1445 * 1446 * If we just wanted to set condition flags, we could do this: 1447 * subs ip, r0, r2 1448 * sbcs ip, r1, r3 1449 * subeqs ip, r0, r2 1450 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1451 * integer value, which we can do with 2 conditional mov/mvn instructions 1452 * (set 1, set -1; if they're equal we already have 0 in ip), giving 1453 * us a constant 5-cycle path plus a branch at the end to the 1454 * instruction epilogue code. The multi-compare approach below needs 1455 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1456 * in the worst case (the 64-bit values are equal). 1457 */ 1458 /* cmp-long vAA, vBB, vCC */ 1459 FETCH(r0, 1) @ r0<- CCBB 1460 mov r9, rINST, lsr #8 @ r9<- AA 1461 and r2, r0, #255 @ r2<- BB 1462 mov r3, r0, lsr #8 @ r3<- CC 1463 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1464 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1465 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1466 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1467 cmp r1, r3 @ compare (vBB+1, vCC+1) 1468 blt .LOP_CMP_LONG_less @ signed compare on high part 1469 bgt .LOP_CMP_LONG_greater 1470 subs r1, r0, r2 @ r1<- r0 - r2 1471 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1472 bne .LOP_CMP_LONG_less 1473 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1474 1475/* ------------------------------ */ 1476 .balign 64 1477.L_OP_IF_EQ: /* 0x32 */ 1478/* File: armv6t2/OP_IF_EQ.S */ 1479/* File: armv6t2/bincmp.S */ 1480 /* 1481 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1482 * fragment that specifies the *reverse* comparison to perform, e.g. 1483 * for "if-le" you would use "gt". 1484 * 1485 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1486 */ 1487 /* if-cmp vA, vB, +CCCC */ 1488 mov r1, rINST, lsr #12 @ r1<- B 1489 ubfx r0, rINST, #8, #4 @ r0<- A 1490 GET_VREG(r3, r1) @ r3<- vB 1491 GET_VREG(r2, r0) @ r2<- vA 1492 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1493 cmp r2, r3 @ compare (vA, vB) 1494 bne 1f @ branch to 1 if comparison failed 1495 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1496 movs r9, r9, asl #1 @ convert to bytes, check sign 1497 bmi common_backwardBranch @ yes, do periodic checks 14981: 1499#if defined(WITH_JIT) 1500 GET_JIT_PROF_TABLE(r0) 1501 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1502 b common_testUpdateProfile 1503#else 1504 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1505 GET_INST_OPCODE(ip) @ extract opcode from rINST 1506 GOTO_OPCODE(ip) @ jump to next instruction 1507#endif 1508 1509 1510/* ------------------------------ */ 1511 .balign 64 1512.L_OP_IF_NE: /* 0x33 */ 1513/* File: armv6t2/OP_IF_NE.S */ 1514/* File: armv6t2/bincmp.S */ 1515 /* 1516 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1517 * fragment that specifies the *reverse* comparison to perform, e.g. 1518 * for "if-le" you would use "gt". 1519 * 1520 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1521 */ 1522 /* if-cmp vA, vB, +CCCC */ 1523 mov r1, rINST, lsr #12 @ r1<- B 1524 ubfx r0, rINST, #8, #4 @ r0<- A 1525 GET_VREG(r3, r1) @ r3<- vB 1526 GET_VREG(r2, r0) @ r2<- vA 1527 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1528 cmp r2, r3 @ compare (vA, vB) 1529 beq 1f @ branch to 1 if comparison failed 1530 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1531 movs r9, r9, asl #1 @ convert to bytes, check sign 1532 bmi common_backwardBranch @ yes, do periodic checks 15331: 1534#if defined(WITH_JIT) 1535 GET_JIT_PROF_TABLE(r0) 1536 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1537 b common_testUpdateProfile 1538#else 1539 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1540 GET_INST_OPCODE(ip) @ extract opcode from rINST 1541 GOTO_OPCODE(ip) @ jump to next instruction 1542#endif 1543 1544 1545/* ------------------------------ */ 1546 .balign 64 1547.L_OP_IF_LT: /* 0x34 */ 1548/* File: armv6t2/OP_IF_LT.S */ 1549/* File: armv6t2/bincmp.S */ 1550 /* 1551 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1552 * fragment that specifies the *reverse* comparison to perform, e.g. 1553 * for "if-le" you would use "gt". 1554 * 1555 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1556 */ 1557 /* if-cmp vA, vB, +CCCC */ 1558 mov r1, rINST, lsr #12 @ r1<- B 1559 ubfx r0, rINST, #8, #4 @ r0<- A 1560 GET_VREG(r3, r1) @ r3<- vB 1561 GET_VREG(r2, r0) @ r2<- vA 1562 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1563 cmp r2, r3 @ compare (vA, vB) 1564 bge 1f @ branch to 1 if comparison failed 1565 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1566 movs r9, r9, asl #1 @ convert to bytes, check sign 1567 bmi common_backwardBranch @ yes, do periodic checks 15681: 1569#if defined(WITH_JIT) 1570 GET_JIT_PROF_TABLE(r0) 1571 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1572 b common_testUpdateProfile 1573#else 1574 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1575 GET_INST_OPCODE(ip) @ extract opcode from rINST 1576 GOTO_OPCODE(ip) @ jump to next instruction 1577#endif 1578 1579 1580/* ------------------------------ */ 1581 .balign 64 1582.L_OP_IF_GE: /* 0x35 */ 1583/* File: armv6t2/OP_IF_GE.S */ 1584/* File: armv6t2/bincmp.S */ 1585 /* 1586 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1587 * fragment that specifies the *reverse* comparison to perform, e.g. 1588 * for "if-le" you would use "gt". 1589 * 1590 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1591 */ 1592 /* if-cmp vA, vB, +CCCC */ 1593 mov r1, rINST, lsr #12 @ r1<- B 1594 ubfx r0, rINST, #8, #4 @ r0<- A 1595 GET_VREG(r3, r1) @ r3<- vB 1596 GET_VREG(r2, r0) @ r2<- vA 1597 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1598 cmp r2, r3 @ compare (vA, vB) 1599 blt 1f @ branch to 1 if comparison failed 1600 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1601 movs r9, r9, asl #1 @ convert to bytes, check sign 1602 bmi common_backwardBranch @ yes, do periodic checks 16031: 1604#if defined(WITH_JIT) 1605 GET_JIT_PROF_TABLE(r0) 1606 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1607 b common_testUpdateProfile 1608#else 1609 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1610 GET_INST_OPCODE(ip) @ extract opcode from rINST 1611 GOTO_OPCODE(ip) @ jump to next instruction 1612#endif 1613 1614 1615/* ------------------------------ */ 1616 .balign 64 1617.L_OP_IF_GT: /* 0x36 */ 1618/* File: armv6t2/OP_IF_GT.S */ 1619/* File: armv6t2/bincmp.S */ 1620 /* 1621 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1622 * fragment that specifies the *reverse* comparison to perform, e.g. 1623 * for "if-le" you would use "gt". 1624 * 1625 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1626 */ 1627 /* if-cmp vA, vB, +CCCC */ 1628 mov r1, rINST, lsr #12 @ r1<- B 1629 ubfx r0, rINST, #8, #4 @ r0<- A 1630 GET_VREG(r3, r1) @ r3<- vB 1631 GET_VREG(r2, r0) @ r2<- vA 1632 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1633 cmp r2, r3 @ compare (vA, vB) 1634 ble 1f @ branch to 1 if comparison failed 1635 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1636 movs r9, r9, asl #1 @ convert to bytes, check sign 1637 bmi common_backwardBranch @ yes, do periodic checks 16381: 1639#if defined(WITH_JIT) 1640 GET_JIT_PROF_TABLE(r0) 1641 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1642 b common_testUpdateProfile 1643#else 1644 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1645 GET_INST_OPCODE(ip) @ extract opcode from rINST 1646 GOTO_OPCODE(ip) @ jump to next instruction 1647#endif 1648 1649 1650/* ------------------------------ */ 1651 .balign 64 1652.L_OP_IF_LE: /* 0x37 */ 1653/* File: armv6t2/OP_IF_LE.S */ 1654/* File: armv6t2/bincmp.S */ 1655 /* 1656 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1657 * fragment that specifies the *reverse* comparison to perform, e.g. 1658 * for "if-le" you would use "gt". 1659 * 1660 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1661 */ 1662 /* if-cmp vA, vB, +CCCC */ 1663 mov r1, rINST, lsr #12 @ r1<- B 1664 ubfx r0, rINST, #8, #4 @ r0<- A 1665 GET_VREG(r3, r1) @ r3<- vB 1666 GET_VREG(r2, r0) @ r2<- vA 1667 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1668 cmp r2, r3 @ compare (vA, vB) 1669 bgt 1f @ branch to 1 if comparison failed 1670 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1671 movs r9, r9, asl #1 @ convert to bytes, check sign 1672 bmi common_backwardBranch @ yes, do periodic checks 16731: 1674#if defined(WITH_JIT) 1675 GET_JIT_PROF_TABLE(r0) 1676 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1677 b common_testUpdateProfile 1678#else 1679 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1680 GET_INST_OPCODE(ip) @ extract opcode from rINST 1681 GOTO_OPCODE(ip) @ jump to next instruction 1682#endif 1683 1684 1685/* ------------------------------ */ 1686 .balign 64 1687.L_OP_IF_EQZ: /* 0x38 */ 1688/* File: armv5te/OP_IF_EQZ.S */ 1689/* File: armv5te/zcmp.S */ 1690 /* 1691 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1692 * fragment that specifies the *reverse* comparison to perform, e.g. 1693 * for "if-le" you would use "gt". 1694 * 1695 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1696 */ 1697 /* if-cmp vAA, +BBBB */ 1698 mov r0, rINST, lsr #8 @ r0<- AA 1699 GET_VREG(r2, r0) @ r2<- vAA 1700 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1701 cmp r2, #0 @ compare (vA, 0) 1702 bne 1f @ branch to 1 if comparison failed 1703 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1704 movs r9, r9, asl #1 @ convert to bytes, check sign 1705 bmi common_backwardBranch @ backward branch, do periodic checks 17061: 1707#if defined(WITH_JIT) 1708 GET_JIT_PROF_TABLE(r0) 1709 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1710 cmp r0,#0 1711 bne common_updateProfile 1712 GET_INST_OPCODE(ip) @ extract opcode from rINST 1713 GOTO_OPCODE(ip) @ jump to next instruction 1714#else 1715 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1716 GET_INST_OPCODE(ip) @ extract opcode from rINST 1717 GOTO_OPCODE(ip) @ jump to next instruction 1718#endif 1719 1720 1721/* ------------------------------ */ 1722 .balign 64 1723.L_OP_IF_NEZ: /* 0x39 */ 1724/* File: armv5te/OP_IF_NEZ.S */ 1725/* File: armv5te/zcmp.S */ 1726 /* 1727 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1728 * fragment that specifies the *reverse* comparison to perform, e.g. 1729 * for "if-le" you would use "gt". 1730 * 1731 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1732 */ 1733 /* if-cmp vAA, +BBBB */ 1734 mov r0, rINST, lsr #8 @ r0<- AA 1735 GET_VREG(r2, r0) @ r2<- vAA 1736 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1737 cmp r2, #0 @ compare (vA, 0) 1738 beq 1f @ branch to 1 if comparison failed 1739 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1740 movs r9, r9, asl #1 @ convert to bytes, check sign 1741 bmi common_backwardBranch @ backward branch, do periodic checks 17421: 1743#if defined(WITH_JIT) 1744 GET_JIT_PROF_TABLE(r0) 1745 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1746 cmp r0,#0 1747 bne common_updateProfile 1748 GET_INST_OPCODE(ip) @ extract opcode from rINST 1749 GOTO_OPCODE(ip) @ jump to next instruction 1750#else 1751 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1752 GET_INST_OPCODE(ip) @ extract opcode from rINST 1753 GOTO_OPCODE(ip) @ jump to next instruction 1754#endif 1755 1756 1757/* ------------------------------ */ 1758 .balign 64 1759.L_OP_IF_LTZ: /* 0x3a */ 1760/* File: armv5te/OP_IF_LTZ.S */ 1761/* File: armv5te/zcmp.S */ 1762 /* 1763 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1764 * fragment that specifies the *reverse* comparison to perform, e.g. 1765 * for "if-le" you would use "gt". 1766 * 1767 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1768 */ 1769 /* if-cmp vAA, +BBBB */ 1770 mov r0, rINST, lsr #8 @ r0<- AA 1771 GET_VREG(r2, r0) @ r2<- vAA 1772 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1773 cmp r2, #0 @ compare (vA, 0) 1774 bge 1f @ branch to 1 if comparison failed 1775 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1776 movs r9, r9, asl #1 @ convert to bytes, check sign 1777 bmi common_backwardBranch @ backward branch, do periodic checks 17781: 1779#if defined(WITH_JIT) 1780 GET_JIT_PROF_TABLE(r0) 1781 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1782 cmp r0,#0 1783 bne common_updateProfile 1784 GET_INST_OPCODE(ip) @ extract opcode from rINST 1785 GOTO_OPCODE(ip) @ jump to next instruction 1786#else 1787 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1788 GET_INST_OPCODE(ip) @ extract opcode from rINST 1789 GOTO_OPCODE(ip) @ jump to next instruction 1790#endif 1791 1792 1793/* ------------------------------ */ 1794 .balign 64 1795.L_OP_IF_GEZ: /* 0x3b */ 1796/* File: armv5te/OP_IF_GEZ.S */ 1797/* File: armv5te/zcmp.S */ 1798 /* 1799 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1800 * fragment that specifies the *reverse* comparison to perform, e.g. 1801 * for "if-le" you would use "gt". 1802 * 1803 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1804 */ 1805 /* if-cmp vAA, +BBBB */ 1806 mov r0, rINST, lsr #8 @ r0<- AA 1807 GET_VREG(r2, r0) @ r2<- vAA 1808 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1809 cmp r2, #0 @ compare (vA, 0) 1810 blt 1f @ branch to 1 if comparison failed 1811 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1812 movs r9, r9, asl #1 @ convert to bytes, check sign 1813 bmi common_backwardBranch @ backward branch, do periodic checks 18141: 1815#if defined(WITH_JIT) 1816 GET_JIT_PROF_TABLE(r0) 1817 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1818 cmp r0,#0 1819 bne common_updateProfile 1820 GET_INST_OPCODE(ip) @ extract opcode from rINST 1821 GOTO_OPCODE(ip) @ jump to next instruction 1822#else 1823 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1824 GET_INST_OPCODE(ip) @ extract opcode from rINST 1825 GOTO_OPCODE(ip) @ jump to next instruction 1826#endif 1827 1828 1829/* ------------------------------ */ 1830 .balign 64 1831.L_OP_IF_GTZ: /* 0x3c */ 1832/* File: armv5te/OP_IF_GTZ.S */ 1833/* File: armv5te/zcmp.S */ 1834 /* 1835 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1836 * fragment that specifies the *reverse* comparison to perform, e.g. 1837 * for "if-le" you would use "gt". 1838 * 1839 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1840 */ 1841 /* if-cmp vAA, +BBBB */ 1842 mov r0, rINST, lsr #8 @ r0<- AA 1843 GET_VREG(r2, r0) @ r2<- vAA 1844 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1845 cmp r2, #0 @ compare (vA, 0) 1846 ble 1f @ branch to 1 if comparison failed 1847 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1848 movs r9, r9, asl #1 @ convert to bytes, check sign 1849 bmi common_backwardBranch @ backward branch, do periodic checks 18501: 1851#if defined(WITH_JIT) 1852 GET_JIT_PROF_TABLE(r0) 1853 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1854 cmp r0,#0 1855 bne common_updateProfile 1856 GET_INST_OPCODE(ip) @ extract opcode from rINST 1857 GOTO_OPCODE(ip) @ jump to next instruction 1858#else 1859 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1860 GET_INST_OPCODE(ip) @ extract opcode from rINST 1861 GOTO_OPCODE(ip) @ jump to next instruction 1862#endif 1863 1864 1865/* ------------------------------ */ 1866 .balign 64 1867.L_OP_IF_LEZ: /* 0x3d */ 1868/* File: armv5te/OP_IF_LEZ.S */ 1869/* File: armv5te/zcmp.S */ 1870 /* 1871 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1872 * fragment that specifies the *reverse* comparison to perform, e.g. 1873 * for "if-le" you would use "gt". 1874 * 1875 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1876 */ 1877 /* if-cmp vAA, +BBBB */ 1878 mov r0, rINST, lsr #8 @ r0<- AA 1879 GET_VREG(r2, r0) @ r2<- vAA 1880 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1881 cmp r2, #0 @ compare (vA, 0) 1882 bgt 1f @ branch to 1 if comparison failed 1883 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1884 movs r9, r9, asl #1 @ convert to bytes, check sign 1885 bmi common_backwardBranch @ backward branch, do periodic checks 18861: 1887#if defined(WITH_JIT) 1888 GET_JIT_PROF_TABLE(r0) 1889 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1890 cmp r0,#0 1891 bne common_updateProfile 1892 GET_INST_OPCODE(ip) @ extract opcode from rINST 1893 GOTO_OPCODE(ip) @ jump to next instruction 1894#else 1895 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1896 GET_INST_OPCODE(ip) @ extract opcode from rINST 1897 GOTO_OPCODE(ip) @ jump to next instruction 1898#endif 1899 1900 1901/* ------------------------------ */ 1902 .balign 64 1903.L_OP_UNUSED_3E: /* 0x3e */ 1904/* File: armv5te/OP_UNUSED_3E.S */ 1905/* File: armv5te/unused.S */ 1906 bl common_abort 1907 1908 1909/* ------------------------------ */ 1910 .balign 64 1911.L_OP_UNUSED_3F: /* 0x3f */ 1912/* File: armv5te/OP_UNUSED_3F.S */ 1913/* File: armv5te/unused.S */ 1914 bl common_abort 1915 1916 1917/* ------------------------------ */ 1918 .balign 64 1919.L_OP_UNUSED_40: /* 0x40 */ 1920/* File: armv5te/OP_UNUSED_40.S */ 1921/* File: armv5te/unused.S */ 1922 bl common_abort 1923 1924 1925/* ------------------------------ */ 1926 .balign 64 1927.L_OP_UNUSED_41: /* 0x41 */ 1928/* File: armv5te/OP_UNUSED_41.S */ 1929/* File: armv5te/unused.S */ 1930 bl common_abort 1931 1932 1933/* ------------------------------ */ 1934 .balign 64 1935.L_OP_UNUSED_42: /* 0x42 */ 1936/* File: armv5te/OP_UNUSED_42.S */ 1937/* File: armv5te/unused.S */ 1938 bl common_abort 1939 1940 1941/* ------------------------------ */ 1942 .balign 64 1943.L_OP_UNUSED_43: /* 0x43 */ 1944/* File: armv5te/OP_UNUSED_43.S */ 1945/* File: armv5te/unused.S */ 1946 bl common_abort 1947 1948 1949/* ------------------------------ */ 1950 .balign 64 1951.L_OP_AGET: /* 0x44 */ 1952/* File: armv5te/OP_AGET.S */ 1953 /* 1954 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1955 * 1956 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1957 * instructions. We use a pair of FETCH_Bs instead. 1958 * 1959 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1960 */ 1961 /* op vAA, vBB, vCC */ 1962 FETCH_B(r2, 1, 0) @ r2<- BB 1963 mov r9, rINST, lsr #8 @ r9<- AA 1964 FETCH_B(r3, 1, 1) @ r3<- CC 1965 GET_VREG(r0, r2) @ r0<- vBB (array object) 1966 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1967 cmp r0, #0 @ null array object? 1968 beq common_errNullObject @ yes, bail 1969 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1970 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1971 cmp r1, r3 @ compare unsigned index, length 1972 bcs common_errArrayIndex @ index >= length, bail 1973 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1974 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 1975 GET_INST_OPCODE(ip) @ extract opcode from rINST 1976 SET_VREG(r2, r9) @ vAA<- r2 1977 GOTO_OPCODE(ip) @ jump to next instruction 1978 1979/* ------------------------------ */ 1980 .balign 64 1981.L_OP_AGET_WIDE: /* 0x45 */ 1982/* File: armv5te/OP_AGET_WIDE.S */ 1983 /* 1984 * Array get, 64 bits. vAA <- vBB[vCC]. 1985 * 1986 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 1987 */ 1988 /* aget-wide vAA, vBB, vCC */ 1989 FETCH(r0, 1) @ r0<- CCBB 1990 mov r9, rINST, lsr #8 @ r9<- AA 1991 and r2, r0, #255 @ r2<- BB 1992 mov r3, r0, lsr #8 @ r3<- CC 1993 GET_VREG(r0, r2) @ r0<- vBB (array object) 1994 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1995 cmp r0, #0 @ null array object? 1996 beq common_errNullObject @ yes, bail 1997 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1998 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 1999 cmp r1, r3 @ compare unsigned index, length 2000 bcc .LOP_AGET_WIDE_finish @ okay, continue below 2001 b common_errArrayIndex @ index >= length, bail 2002 @ May want to swap the order of these two branches depending on how the 2003 @ branch prediction (if any) handles conditional forward branches vs. 2004 @ unconditional forward branches. 2005 2006/* ------------------------------ */ 2007 .balign 64 2008.L_OP_AGET_OBJECT: /* 0x46 */ 2009/* File: armv5te/OP_AGET_OBJECT.S */ 2010/* File: armv5te/OP_AGET.S */ 2011 /* 2012 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2013 * 2014 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2015 * instructions. We use a pair of FETCH_Bs instead. 2016 * 2017 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2018 */ 2019 /* op vAA, vBB, vCC */ 2020 FETCH_B(r2, 1, 0) @ r2<- BB 2021 mov r9, rINST, lsr #8 @ r9<- AA 2022 FETCH_B(r3, 1, 1) @ r3<- CC 2023 GET_VREG(r0, r2) @ r0<- vBB (array object) 2024 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2025 cmp r0, #0 @ null array object? 2026 beq common_errNullObject @ yes, bail 2027 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2028 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2029 cmp r1, r3 @ compare unsigned index, length 2030 bcs common_errArrayIndex @ index >= length, bail 2031 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2032 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2033 GET_INST_OPCODE(ip) @ extract opcode from rINST 2034 SET_VREG(r2, r9) @ vAA<- r2 2035 GOTO_OPCODE(ip) @ jump to next instruction 2036 2037 2038/* ------------------------------ */ 2039 .balign 64 2040.L_OP_AGET_BOOLEAN: /* 0x47 */ 2041/* File: armv5te/OP_AGET_BOOLEAN.S */ 2042/* File: armv5te/OP_AGET.S */ 2043 /* 2044 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2045 * 2046 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2047 * instructions. We use a pair of FETCH_Bs instead. 2048 * 2049 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2050 */ 2051 /* op vAA, vBB, vCC */ 2052 FETCH_B(r2, 1, 0) @ r2<- BB 2053 mov r9, rINST, lsr #8 @ r9<- AA 2054 FETCH_B(r3, 1, 1) @ r3<- CC 2055 GET_VREG(r0, r2) @ r0<- vBB (array object) 2056 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2057 cmp r0, #0 @ null array object? 2058 beq common_errNullObject @ yes, bail 2059 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2060 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2061 cmp r1, r3 @ compare unsigned index, length 2062 bcs common_errArrayIndex @ index >= length, bail 2063 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2064 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2065 GET_INST_OPCODE(ip) @ extract opcode from rINST 2066 SET_VREG(r2, r9) @ vAA<- r2 2067 GOTO_OPCODE(ip) @ jump to next instruction 2068 2069 2070/* ------------------------------ */ 2071 .balign 64 2072.L_OP_AGET_BYTE: /* 0x48 */ 2073/* File: armv5te/OP_AGET_BYTE.S */ 2074/* File: armv5te/OP_AGET.S */ 2075 /* 2076 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2077 * 2078 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2079 * instructions. We use a pair of FETCH_Bs instead. 2080 * 2081 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2082 */ 2083 /* op vAA, vBB, vCC */ 2084 FETCH_B(r2, 1, 0) @ r2<- BB 2085 mov r9, rINST, lsr #8 @ r9<- AA 2086 FETCH_B(r3, 1, 1) @ r3<- CC 2087 GET_VREG(r0, r2) @ r0<- vBB (array object) 2088 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2089 cmp r0, #0 @ null array object? 2090 beq common_errNullObject @ yes, bail 2091 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2092 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2093 cmp r1, r3 @ compare unsigned index, length 2094 bcs common_errArrayIndex @ index >= length, bail 2095 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2096 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2097 GET_INST_OPCODE(ip) @ extract opcode from rINST 2098 SET_VREG(r2, r9) @ vAA<- r2 2099 GOTO_OPCODE(ip) @ jump to next instruction 2100 2101 2102/* ------------------------------ */ 2103 .balign 64 2104.L_OP_AGET_CHAR: /* 0x49 */ 2105/* File: armv5te/OP_AGET_CHAR.S */ 2106/* File: armv5te/OP_AGET.S */ 2107 /* 2108 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2109 * 2110 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2111 * instructions. We use a pair of FETCH_Bs instead. 2112 * 2113 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2114 */ 2115 /* op vAA, vBB, vCC */ 2116 FETCH_B(r2, 1, 0) @ r2<- BB 2117 mov r9, rINST, lsr #8 @ r9<- AA 2118 FETCH_B(r3, 1, 1) @ r3<- CC 2119 GET_VREG(r0, r2) @ r0<- vBB (array object) 2120 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2121 cmp r0, #0 @ null array object? 2122 beq common_errNullObject @ yes, bail 2123 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2124 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2125 cmp r1, r3 @ compare unsigned index, length 2126 bcs common_errArrayIndex @ index >= length, bail 2127 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2128 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2129 GET_INST_OPCODE(ip) @ extract opcode from rINST 2130 SET_VREG(r2, r9) @ vAA<- r2 2131 GOTO_OPCODE(ip) @ jump to next instruction 2132 2133 2134/* ------------------------------ */ 2135 .balign 64 2136.L_OP_AGET_SHORT: /* 0x4a */ 2137/* File: armv5te/OP_AGET_SHORT.S */ 2138/* File: armv5te/OP_AGET.S */ 2139 /* 2140 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2141 * 2142 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2143 * instructions. We use a pair of FETCH_Bs instead. 2144 * 2145 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2146 */ 2147 /* op vAA, vBB, vCC */ 2148 FETCH_B(r2, 1, 0) @ r2<- BB 2149 mov r9, rINST, lsr #8 @ r9<- AA 2150 FETCH_B(r3, 1, 1) @ r3<- CC 2151 GET_VREG(r0, r2) @ r0<- vBB (array object) 2152 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2153 cmp r0, #0 @ null array object? 2154 beq common_errNullObject @ yes, bail 2155 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2156 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2157 cmp r1, r3 @ compare unsigned index, length 2158 bcs common_errArrayIndex @ index >= length, bail 2159 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2160 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2161 GET_INST_OPCODE(ip) @ extract opcode from rINST 2162 SET_VREG(r2, r9) @ vAA<- r2 2163 GOTO_OPCODE(ip) @ jump to next instruction 2164 2165 2166/* ------------------------------ */ 2167 .balign 64 2168.L_OP_APUT: /* 0x4b */ 2169/* File: armv5te/OP_APUT.S */ 2170 /* 2171 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2172 * 2173 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2174 * instructions. We use a pair of FETCH_Bs instead. 2175 * 2176 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2177 */ 2178 /* op vAA, vBB, vCC */ 2179 FETCH_B(r2, 1, 0) @ r2<- BB 2180 mov r9, rINST, lsr #8 @ r9<- AA 2181 FETCH_B(r3, 1, 1) @ r3<- CC 2182 GET_VREG(r0, r2) @ r0<- vBB (array object) 2183 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2184 cmp r0, #0 @ null array object? 2185 beq common_errNullObject @ yes, bail 2186 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2187 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2188 cmp r1, r3 @ compare unsigned index, length 2189 bcs common_errArrayIndex @ index >= length, bail 2190 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2191 GET_VREG(r2, r9) @ r2<- vAA 2192 GET_INST_OPCODE(ip) @ extract opcode from rINST 2193 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2194 GOTO_OPCODE(ip) @ jump to next instruction 2195 2196/* ------------------------------ */ 2197 .balign 64 2198.L_OP_APUT_WIDE: /* 0x4c */ 2199/* File: armv5te/OP_APUT_WIDE.S */ 2200 /* 2201 * Array put, 64 bits. vBB[vCC] <- vAA. 2202 * 2203 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2204 */ 2205 /* aput-wide vAA, vBB, vCC */ 2206 FETCH(r0, 1) @ r0<- CCBB 2207 mov r9, rINST, lsr #8 @ r9<- AA 2208 and r2, r0, #255 @ r2<- BB 2209 mov r3, r0, lsr #8 @ r3<- CC 2210 GET_VREG(r0, r2) @ r0<- vBB (array object) 2211 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2212 cmp r0, #0 @ null array object? 2213 beq common_errNullObject @ yes, bail 2214 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2215 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2216 cmp r1, r3 @ compare unsigned index, length 2217 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2218 bcc .LOP_APUT_WIDE_finish @ okay, continue below 2219 b common_errArrayIndex @ index >= length, bail 2220 @ May want to swap the order of these two branches depending on how the 2221 @ branch prediction (if any) handles conditional forward branches vs. 2222 @ unconditional forward branches. 2223 2224/* ------------------------------ */ 2225 .balign 64 2226.L_OP_APUT_OBJECT: /* 0x4d */ 2227/* File: armv5te/OP_APUT_OBJECT.S */ 2228 /* 2229 * Store an object into an array. vBB[vCC] <- vAA. 2230 */ 2231 /* op vAA, vBB, vCC */ 2232 FETCH(r0, 1) @ r0<- CCBB 2233 mov r9, rINST, lsr #8 @ r9<- AA 2234 and r2, r0, #255 @ r2<- BB 2235 mov r3, r0, lsr #8 @ r3<- CC 2236 GET_VREG(rINST, r2) @ rINST<- vBB (array object) 2237 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2238 cmp rINST, #0 @ null array object? 2239 GET_VREG(r9, r9) @ r9<- vAA 2240 beq common_errNullObject @ yes, bail 2241 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length 2242 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width 2243 cmp r1, r3 @ compare unsigned index, length 2244 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2245 b common_errArrayIndex @ index >= length, bail 2246 2247 2248/* ------------------------------ */ 2249 .balign 64 2250.L_OP_APUT_BOOLEAN: /* 0x4e */ 2251/* File: armv5te/OP_APUT_BOOLEAN.S */ 2252/* File: armv5te/OP_APUT.S */ 2253 /* 2254 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2255 * 2256 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2257 * instructions. We use a pair of FETCH_Bs instead. 2258 * 2259 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2260 */ 2261 /* op vAA, vBB, vCC */ 2262 FETCH_B(r2, 1, 0) @ r2<- BB 2263 mov r9, rINST, lsr #8 @ r9<- AA 2264 FETCH_B(r3, 1, 1) @ r3<- CC 2265 GET_VREG(r0, r2) @ r0<- vBB (array object) 2266 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2267 cmp r0, #0 @ null array object? 2268 beq common_errNullObject @ yes, bail 2269 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2270 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2271 cmp r1, r3 @ compare unsigned index, length 2272 bcs common_errArrayIndex @ index >= length, bail 2273 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2274 GET_VREG(r2, r9) @ r2<- vAA 2275 GET_INST_OPCODE(ip) @ extract opcode from rINST 2276 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2277 GOTO_OPCODE(ip) @ jump to next instruction 2278 2279 2280/* ------------------------------ */ 2281 .balign 64 2282.L_OP_APUT_BYTE: /* 0x4f */ 2283/* File: armv5te/OP_APUT_BYTE.S */ 2284/* File: armv5te/OP_APUT.S */ 2285 /* 2286 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2287 * 2288 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2289 * instructions. We use a pair of FETCH_Bs instead. 2290 * 2291 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2292 */ 2293 /* op vAA, vBB, vCC */ 2294 FETCH_B(r2, 1, 0) @ r2<- BB 2295 mov r9, rINST, lsr #8 @ r9<- AA 2296 FETCH_B(r3, 1, 1) @ r3<- CC 2297 GET_VREG(r0, r2) @ r0<- vBB (array object) 2298 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2299 cmp r0, #0 @ null array object? 2300 beq common_errNullObject @ yes, bail 2301 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2302 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2303 cmp r1, r3 @ compare unsigned index, length 2304 bcs common_errArrayIndex @ index >= length, bail 2305 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2306 GET_VREG(r2, r9) @ r2<- vAA 2307 GET_INST_OPCODE(ip) @ extract opcode from rINST 2308 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2309 GOTO_OPCODE(ip) @ jump to next instruction 2310 2311 2312/* ------------------------------ */ 2313 .balign 64 2314.L_OP_APUT_CHAR: /* 0x50 */ 2315/* File: armv5te/OP_APUT_CHAR.S */ 2316/* File: armv5te/OP_APUT.S */ 2317 /* 2318 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2319 * 2320 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2321 * instructions. We use a pair of FETCH_Bs instead. 2322 * 2323 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2324 */ 2325 /* op vAA, vBB, vCC */ 2326 FETCH_B(r2, 1, 0) @ r2<- BB 2327 mov r9, rINST, lsr #8 @ r9<- AA 2328 FETCH_B(r3, 1, 1) @ r3<- CC 2329 GET_VREG(r0, r2) @ r0<- vBB (array object) 2330 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2331 cmp r0, #0 @ null array object? 2332 beq common_errNullObject @ yes, bail 2333 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2334 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2335 cmp r1, r3 @ compare unsigned index, length 2336 bcs common_errArrayIndex @ index >= length, bail 2337 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2338 GET_VREG(r2, r9) @ r2<- vAA 2339 GET_INST_OPCODE(ip) @ extract opcode from rINST 2340 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2341 GOTO_OPCODE(ip) @ jump to next instruction 2342 2343 2344/* ------------------------------ */ 2345 .balign 64 2346.L_OP_APUT_SHORT: /* 0x51 */ 2347/* File: armv5te/OP_APUT_SHORT.S */ 2348/* File: armv5te/OP_APUT.S */ 2349 /* 2350 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2351 * 2352 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2353 * instructions. We use a pair of FETCH_Bs instead. 2354 * 2355 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2356 */ 2357 /* op vAA, vBB, vCC */ 2358 FETCH_B(r2, 1, 0) @ r2<- BB 2359 mov r9, rINST, lsr #8 @ r9<- AA 2360 FETCH_B(r3, 1, 1) @ r3<- CC 2361 GET_VREG(r0, r2) @ r0<- vBB (array object) 2362 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2363 cmp r0, #0 @ null array object? 2364 beq common_errNullObject @ yes, bail 2365 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2366 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2367 cmp r1, r3 @ compare unsigned index, length 2368 bcs common_errArrayIndex @ index >= length, bail 2369 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2370 GET_VREG(r2, r9) @ r2<- vAA 2371 GET_INST_OPCODE(ip) @ extract opcode from rINST 2372 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2373 GOTO_OPCODE(ip) @ jump to next instruction 2374 2375 2376/* ------------------------------ */ 2377 .balign 64 2378.L_OP_IGET: /* 0x52 */ 2379/* File: armv6t2/OP_IGET.S */ 2380 /* 2381 * General 32-bit instance field get. 2382 * 2383 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2384 */ 2385 /* op vA, vB, field@CCCC */ 2386 mov r0, rINST, lsr #12 @ r0<- B 2387 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2388 FETCH(r1, 1) @ r1<- field ref CCCC 2389 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2390 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2391 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2392 cmp r0, #0 @ is resolved entry null? 2393 bne .LOP_IGET_finish @ no, already resolved 23948: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2395 EXPORT_PC() @ resolve() could throw 2396 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2397 bl dvmResolveInstField @ r0<- resolved InstField ptr 2398 cmp r0, #0 2399 bne .LOP_IGET_finish 2400 b common_exceptionThrown 2401 2402/* ------------------------------ */ 2403 .balign 64 2404.L_OP_IGET_WIDE: /* 0x53 */ 2405/* File: armv6t2/OP_IGET_WIDE.S */ 2406 /* 2407 * Wide 32-bit instance field get. 2408 */ 2409 /* iget-wide vA, vB, field@CCCC */ 2410 mov r0, rINST, lsr #12 @ r0<- B 2411 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2412 FETCH(r1, 1) @ r1<- field ref CCCC 2413 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2414 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2415 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2416 cmp r0, #0 @ is resolved entry null? 2417 bne .LOP_IGET_WIDE_finish @ no, already resolved 24188: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2419 EXPORT_PC() @ resolve() could throw 2420 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2421 bl dvmResolveInstField @ r0<- resolved InstField ptr 2422 cmp r0, #0 2423 bne .LOP_IGET_WIDE_finish 2424 b common_exceptionThrown 2425 2426/* ------------------------------ */ 2427 .balign 64 2428.L_OP_IGET_OBJECT: /* 0x54 */ 2429/* File: armv5te/OP_IGET_OBJECT.S */ 2430/* File: armv5te/OP_IGET.S */ 2431 /* 2432 * General 32-bit instance field get. 2433 * 2434 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2435 */ 2436 /* op vA, vB, field@CCCC */ 2437 mov r0, rINST, lsr #12 @ r0<- B 2438 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2439 FETCH(r1, 1) @ r1<- field ref CCCC 2440 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2441 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2442 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2443 cmp r0, #0 @ is resolved entry null? 2444 bne .LOP_IGET_OBJECT_finish @ no, already resolved 24458: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2446 EXPORT_PC() @ resolve() could throw 2447 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2448 bl dvmResolveInstField @ r0<- resolved InstField ptr 2449 cmp r0, #0 2450 bne .LOP_IGET_OBJECT_finish 2451 b common_exceptionThrown 2452 2453 2454/* ------------------------------ */ 2455 .balign 64 2456.L_OP_IGET_BOOLEAN: /* 0x55 */ 2457/* File: armv5te/OP_IGET_BOOLEAN.S */ 2458@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2459/* File: armv5te/OP_IGET.S */ 2460 /* 2461 * General 32-bit instance field get. 2462 * 2463 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2464 */ 2465 /* op vA, vB, field@CCCC */ 2466 mov r0, rINST, lsr #12 @ r0<- B 2467 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2468 FETCH(r1, 1) @ r1<- field ref CCCC 2469 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2470 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2471 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2472 cmp r0, #0 @ is resolved entry null? 2473 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 24748: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2475 EXPORT_PC() @ resolve() could throw 2476 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2477 bl dvmResolveInstField @ r0<- resolved InstField ptr 2478 cmp r0, #0 2479 bne .LOP_IGET_BOOLEAN_finish 2480 b common_exceptionThrown 2481 2482 2483/* ------------------------------ */ 2484 .balign 64 2485.L_OP_IGET_BYTE: /* 0x56 */ 2486/* File: armv5te/OP_IGET_BYTE.S */ 2487@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2488/* File: armv5te/OP_IGET.S */ 2489 /* 2490 * General 32-bit instance field get. 2491 * 2492 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2493 */ 2494 /* op vA, vB, field@CCCC */ 2495 mov r0, rINST, lsr #12 @ r0<- B 2496 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2497 FETCH(r1, 1) @ r1<- field ref CCCC 2498 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2499 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2500 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2501 cmp r0, #0 @ is resolved entry null? 2502 bne .LOP_IGET_BYTE_finish @ no, already resolved 25038: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2504 EXPORT_PC() @ resolve() could throw 2505 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2506 bl dvmResolveInstField @ r0<- resolved InstField ptr 2507 cmp r0, #0 2508 bne .LOP_IGET_BYTE_finish 2509 b common_exceptionThrown 2510 2511 2512/* ------------------------------ */ 2513 .balign 64 2514.L_OP_IGET_CHAR: /* 0x57 */ 2515/* File: armv5te/OP_IGET_CHAR.S */ 2516@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2517/* File: armv5te/OP_IGET.S */ 2518 /* 2519 * General 32-bit instance field get. 2520 * 2521 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2522 */ 2523 /* op vA, vB, field@CCCC */ 2524 mov r0, rINST, lsr #12 @ r0<- B 2525 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2526 FETCH(r1, 1) @ r1<- field ref CCCC 2527 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2528 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2529 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2530 cmp r0, #0 @ is resolved entry null? 2531 bne .LOP_IGET_CHAR_finish @ no, already resolved 25328: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2533 EXPORT_PC() @ resolve() could throw 2534 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2535 bl dvmResolveInstField @ r0<- resolved InstField ptr 2536 cmp r0, #0 2537 bne .LOP_IGET_CHAR_finish 2538 b common_exceptionThrown 2539 2540 2541/* ------------------------------ */ 2542 .balign 64 2543.L_OP_IGET_SHORT: /* 0x58 */ 2544/* File: armv5te/OP_IGET_SHORT.S */ 2545@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2546/* File: armv5te/OP_IGET.S */ 2547 /* 2548 * General 32-bit instance field get. 2549 * 2550 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2551 */ 2552 /* op vA, vB, field@CCCC */ 2553 mov r0, rINST, lsr #12 @ r0<- B 2554 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2555 FETCH(r1, 1) @ r1<- field ref CCCC 2556 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2557 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2558 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2559 cmp r0, #0 @ is resolved entry null? 2560 bne .LOP_IGET_SHORT_finish @ no, already resolved 25618: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2562 EXPORT_PC() @ resolve() could throw 2563 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2564 bl dvmResolveInstField @ r0<- resolved InstField ptr 2565 cmp r0, #0 2566 bne .LOP_IGET_SHORT_finish 2567 b common_exceptionThrown 2568 2569 2570/* ------------------------------ */ 2571 .balign 64 2572.L_OP_IPUT: /* 0x59 */ 2573/* File: armv6t2/OP_IPUT.S */ 2574 /* 2575 * General 32-bit instance field put. 2576 * 2577 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2578 */ 2579 /* op vA, vB, field@CCCC */ 2580 mov r0, rINST, lsr #12 @ r0<- B 2581 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2582 FETCH(r1, 1) @ r1<- field ref CCCC 2583 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2584 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2585 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2586 cmp r0, #0 @ is resolved entry null? 2587 bne .LOP_IPUT_finish @ no, already resolved 25888: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2589 EXPORT_PC() @ resolve() could throw 2590 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2591 bl dvmResolveInstField @ r0<- resolved InstField ptr 2592 cmp r0, #0 @ success? 2593 bne .LOP_IPUT_finish @ yes, finish up 2594 b common_exceptionThrown 2595 2596/* ------------------------------ */ 2597 .balign 64 2598.L_OP_IPUT_WIDE: /* 0x5a */ 2599/* File: armv6t2/OP_IPUT_WIDE.S */ 2600 /* iput-wide vA, vB, field@CCCC */ 2601 mov r0, rINST, lsr #12 @ r0<- B 2602 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2603 FETCH(r1, 1) @ r1<- field ref CCCC 2604 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2605 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2606 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2607 cmp r0, #0 @ is resolved entry null? 2608 bne .LOP_IPUT_WIDE_finish @ no, already resolved 26098: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2610 EXPORT_PC() @ resolve() could throw 2611 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2612 bl dvmResolveInstField @ r0<- resolved InstField ptr 2613 cmp r0, #0 @ success? 2614 bne .LOP_IPUT_WIDE_finish @ yes, finish up 2615 b common_exceptionThrown 2616 2617/* ------------------------------ */ 2618 .balign 64 2619.L_OP_IPUT_OBJECT: /* 0x5b */ 2620/* File: armv5te/OP_IPUT_OBJECT.S */ 2621 /* 2622 * 32-bit instance field put. 2623 * 2624 * for: iput-object, iput-object-volatile 2625 */ 2626 /* op vA, vB, field@CCCC */ 2627 mov r0, rINST, lsr #12 @ r0<- B 2628 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2629 FETCH(r1, 1) @ r1<- field ref CCCC 2630 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2631 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2632 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2633 cmp r0, #0 @ is resolved entry null? 2634 bne .LOP_IPUT_OBJECT_finish @ no, already resolved 26358: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2636 EXPORT_PC() @ resolve() could throw 2637 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2638 bl dvmResolveInstField @ r0<- resolved InstField ptr 2639 cmp r0, #0 @ success? 2640 bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2641 b common_exceptionThrown 2642 2643/* ------------------------------ */ 2644 .balign 64 2645.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2646/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2647@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2648/* File: armv5te/OP_IPUT.S */ 2649 /* 2650 * General 32-bit instance field put. 2651 * 2652 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2653 */ 2654 /* op vA, vB, field@CCCC */ 2655 mov r0, rINST, lsr #12 @ r0<- B 2656 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2657 FETCH(r1, 1) @ r1<- field ref CCCC 2658 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2659 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2660 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2661 cmp r0, #0 @ is resolved entry null? 2662 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 26638: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2664 EXPORT_PC() @ resolve() could throw 2665 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2666 bl dvmResolveInstField @ r0<- resolved InstField ptr 2667 cmp r0, #0 @ success? 2668 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2669 b common_exceptionThrown 2670 2671 2672/* ------------------------------ */ 2673 .balign 64 2674.L_OP_IPUT_BYTE: /* 0x5d */ 2675/* File: armv5te/OP_IPUT_BYTE.S */ 2676@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2677/* File: armv5te/OP_IPUT.S */ 2678 /* 2679 * General 32-bit instance field put. 2680 * 2681 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2682 */ 2683 /* op vA, vB, field@CCCC */ 2684 mov r0, rINST, lsr #12 @ r0<- B 2685 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2686 FETCH(r1, 1) @ r1<- field ref CCCC 2687 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2688 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2689 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2690 cmp r0, #0 @ is resolved entry null? 2691 bne .LOP_IPUT_BYTE_finish @ no, already resolved 26928: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2693 EXPORT_PC() @ resolve() could throw 2694 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2695 bl dvmResolveInstField @ r0<- resolved InstField ptr 2696 cmp r0, #0 @ success? 2697 bne .LOP_IPUT_BYTE_finish @ yes, finish up 2698 b common_exceptionThrown 2699 2700 2701/* ------------------------------ */ 2702 .balign 64 2703.L_OP_IPUT_CHAR: /* 0x5e */ 2704/* File: armv5te/OP_IPUT_CHAR.S */ 2705@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2706/* File: armv5te/OP_IPUT.S */ 2707 /* 2708 * General 32-bit instance field put. 2709 * 2710 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2711 */ 2712 /* op vA, vB, field@CCCC */ 2713 mov r0, rINST, lsr #12 @ r0<- B 2714 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2715 FETCH(r1, 1) @ r1<- field ref CCCC 2716 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2717 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2718 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2719 cmp r0, #0 @ is resolved entry null? 2720 bne .LOP_IPUT_CHAR_finish @ no, already resolved 27218: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2722 EXPORT_PC() @ resolve() could throw 2723 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2724 bl dvmResolveInstField @ r0<- resolved InstField ptr 2725 cmp r0, #0 @ success? 2726 bne .LOP_IPUT_CHAR_finish @ yes, finish up 2727 b common_exceptionThrown 2728 2729 2730/* ------------------------------ */ 2731 .balign 64 2732.L_OP_IPUT_SHORT: /* 0x5f */ 2733/* File: armv5te/OP_IPUT_SHORT.S */ 2734@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2735/* File: armv5te/OP_IPUT.S */ 2736 /* 2737 * General 32-bit instance field put. 2738 * 2739 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2740 */ 2741 /* op vA, vB, field@CCCC */ 2742 mov r0, rINST, lsr #12 @ r0<- B 2743 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2744 FETCH(r1, 1) @ r1<- field ref CCCC 2745 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2746 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2747 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2748 cmp r0, #0 @ is resolved entry null? 2749 bne .LOP_IPUT_SHORT_finish @ no, already resolved 27508: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2751 EXPORT_PC() @ resolve() could throw 2752 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2753 bl dvmResolveInstField @ r0<- resolved InstField ptr 2754 cmp r0, #0 @ success? 2755 bne .LOP_IPUT_SHORT_finish @ yes, finish up 2756 b common_exceptionThrown 2757 2758 2759/* ------------------------------ */ 2760 .balign 64 2761.L_OP_SGET: /* 0x60 */ 2762/* File: armv5te/OP_SGET.S */ 2763 /* 2764 * General 32-bit SGET handler. 2765 * 2766 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2767 */ 2768 /* op vAA, field@BBBB */ 2769 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2770 FETCH(r1, 1) @ r1<- field ref BBBB 2771 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2772 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2773 cmp r0, #0 @ is resolved entry null? 2774 beq .LOP_SGET_resolve @ yes, do resolve 2775.LOP_SGET_finish: @ field ptr in r0 2776 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2777 @ no-op @ acquiring load 2778 mov r2, rINST, lsr #8 @ r2<- AA 2779 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2780 SET_VREG(r1, r2) @ fp[AA]<- r1 2781 GET_INST_OPCODE(ip) @ extract opcode from rINST 2782 GOTO_OPCODE(ip) @ jump to next instruction 2783 2784/* ------------------------------ */ 2785 .balign 64 2786.L_OP_SGET_WIDE: /* 0x61 */ 2787/* File: armv5te/OP_SGET_WIDE.S */ 2788 /* 2789 * 64-bit SGET handler. 2790 */ 2791 /* sget-wide vAA, field@BBBB */ 2792 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2793 FETCH(r1, 1) @ r1<- field ref BBBB 2794 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2795 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2796 cmp r0, #0 @ is resolved entry null? 2797 beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2798.LOP_SGET_WIDE_finish: 2799 mov r9, rINST, lsr #8 @ r9<- AA 2800 .if 0 2801 add r0, r0, #offStaticField_value @ r0<- pointer to data 2802 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2803 .else 2804 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2805 .endif 2806 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2807 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2808 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2809 GET_INST_OPCODE(ip) @ extract opcode from rINST 2810 GOTO_OPCODE(ip) @ jump to next instruction 2811 2812/* ------------------------------ */ 2813 .balign 64 2814.L_OP_SGET_OBJECT: /* 0x62 */ 2815/* File: armv5te/OP_SGET_OBJECT.S */ 2816/* File: armv5te/OP_SGET.S */ 2817 /* 2818 * General 32-bit SGET handler. 2819 * 2820 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2821 */ 2822 /* op vAA, field@BBBB */ 2823 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2824 FETCH(r1, 1) @ r1<- field ref BBBB 2825 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2826 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2827 cmp r0, #0 @ is resolved entry null? 2828 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2829.LOP_SGET_OBJECT_finish: @ field ptr in r0 2830 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2831 @ no-op @ acquiring load 2832 mov r2, rINST, lsr #8 @ r2<- AA 2833 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2834 SET_VREG(r1, r2) @ fp[AA]<- r1 2835 GET_INST_OPCODE(ip) @ extract opcode from rINST 2836 GOTO_OPCODE(ip) @ jump to next instruction 2837 2838 2839/* ------------------------------ */ 2840 .balign 64 2841.L_OP_SGET_BOOLEAN: /* 0x63 */ 2842/* File: armv5te/OP_SGET_BOOLEAN.S */ 2843/* File: armv5te/OP_SGET.S */ 2844 /* 2845 * General 32-bit SGET handler. 2846 * 2847 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2848 */ 2849 /* op vAA, field@BBBB */ 2850 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2851 FETCH(r1, 1) @ r1<- field ref BBBB 2852 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2853 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2854 cmp r0, #0 @ is resolved entry null? 2855 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2856.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2857 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2858 @ no-op @ acquiring load 2859 mov r2, rINST, lsr #8 @ r2<- AA 2860 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2861 SET_VREG(r1, r2) @ fp[AA]<- r1 2862 GET_INST_OPCODE(ip) @ extract opcode from rINST 2863 GOTO_OPCODE(ip) @ jump to next instruction 2864 2865 2866/* ------------------------------ */ 2867 .balign 64 2868.L_OP_SGET_BYTE: /* 0x64 */ 2869/* File: armv5te/OP_SGET_BYTE.S */ 2870/* File: armv5te/OP_SGET.S */ 2871 /* 2872 * General 32-bit SGET handler. 2873 * 2874 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2875 */ 2876 /* op vAA, field@BBBB */ 2877 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2878 FETCH(r1, 1) @ r1<- field ref BBBB 2879 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2880 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2881 cmp r0, #0 @ is resolved entry null? 2882 beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2883.LOP_SGET_BYTE_finish: @ field ptr in r0 2884 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2885 @ no-op @ acquiring load 2886 mov r2, rINST, lsr #8 @ r2<- AA 2887 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2888 SET_VREG(r1, r2) @ fp[AA]<- r1 2889 GET_INST_OPCODE(ip) @ extract opcode from rINST 2890 GOTO_OPCODE(ip) @ jump to next instruction 2891 2892 2893/* ------------------------------ */ 2894 .balign 64 2895.L_OP_SGET_CHAR: /* 0x65 */ 2896/* File: armv5te/OP_SGET_CHAR.S */ 2897/* File: armv5te/OP_SGET.S */ 2898 /* 2899 * General 32-bit SGET handler. 2900 * 2901 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2902 */ 2903 /* op vAA, field@BBBB */ 2904 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2905 FETCH(r1, 1) @ r1<- field ref BBBB 2906 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2907 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2908 cmp r0, #0 @ is resolved entry null? 2909 beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2910.LOP_SGET_CHAR_finish: @ field ptr in r0 2911 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2912 @ no-op @ acquiring load 2913 mov r2, rINST, lsr #8 @ r2<- AA 2914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2915 SET_VREG(r1, r2) @ fp[AA]<- r1 2916 GET_INST_OPCODE(ip) @ extract opcode from rINST 2917 GOTO_OPCODE(ip) @ jump to next instruction 2918 2919 2920/* ------------------------------ */ 2921 .balign 64 2922.L_OP_SGET_SHORT: /* 0x66 */ 2923/* File: armv5te/OP_SGET_SHORT.S */ 2924/* File: armv5te/OP_SGET.S */ 2925 /* 2926 * General 32-bit SGET handler. 2927 * 2928 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2929 */ 2930 /* op vAA, field@BBBB */ 2931 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2932 FETCH(r1, 1) @ r1<- field ref BBBB 2933 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2934 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2935 cmp r0, #0 @ is resolved entry null? 2936 beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2937.LOP_SGET_SHORT_finish: @ field ptr in r0 2938 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2939 @ no-op @ acquiring load 2940 mov r2, rINST, lsr #8 @ r2<- AA 2941 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2942 SET_VREG(r1, r2) @ fp[AA]<- r1 2943 GET_INST_OPCODE(ip) @ extract opcode from rINST 2944 GOTO_OPCODE(ip) @ jump to next instruction 2945 2946 2947/* ------------------------------ */ 2948 .balign 64 2949.L_OP_SPUT: /* 0x67 */ 2950/* File: armv5te/OP_SPUT.S */ 2951 /* 2952 * General 32-bit SPUT handler. 2953 * 2954 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2955 */ 2956 /* op vAA, field@BBBB */ 2957 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2958 FETCH(r1, 1) @ r1<- field ref BBBB 2959 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2960 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2961 cmp r0, #0 @ is resolved entry null? 2962 beq .LOP_SPUT_resolve @ yes, do resolve 2963.LOP_SPUT_finish: @ field ptr in r0 2964 mov r2, rINST, lsr #8 @ r2<- AA 2965 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2966 GET_VREG(r1, r2) @ r1<- fp[AA] 2967 GET_INST_OPCODE(ip) @ extract opcode from rINST 2968 @ no-op @ releasing store 2969 str r1, [r0, #offStaticField_value] @ field<- vAA 2970 GOTO_OPCODE(ip) @ jump to next instruction 2971 2972/* ------------------------------ */ 2973 .balign 64 2974.L_OP_SPUT_WIDE: /* 0x68 */ 2975/* File: armv5te/OP_SPUT_WIDE.S */ 2976 /* 2977 * 64-bit SPUT handler. 2978 */ 2979 /* sput-wide vAA, field@BBBB */ 2980 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 2981 FETCH(r1, 1) @ r1<- field ref BBBB 2982 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 2983 mov r9, rINST, lsr #8 @ r9<- AA 2984 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 2985 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2986 cmp r2, #0 @ is resolved entry null? 2987 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 2988.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 2989 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2990 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 2991 GET_INST_OPCODE(r10) @ extract opcode from rINST 2992 .if 0 2993 add r2, r2, #offStaticField_value @ r2<- pointer to data 2994 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 2995 .else 2996 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 2997 .endif 2998 GOTO_OPCODE(r10) @ jump to next instruction 2999 3000/* ------------------------------ */ 3001 .balign 64 3002.L_OP_SPUT_OBJECT: /* 0x69 */ 3003/* File: armv5te/OP_SPUT_OBJECT.S */ 3004 /* 3005 * 32-bit SPUT handler for objects 3006 * 3007 * for: sput-object, sput-object-volatile 3008 */ 3009 /* op vAA, field@BBBB */ 3010 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3011 FETCH(r1, 1) @ r1<- field ref BBBB 3012 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3013 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3014 cmp r0, #0 @ is resolved entry null? 3015 bne .LOP_SPUT_OBJECT_finish @ no, continue 3016 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3017 EXPORT_PC() @ resolve() could throw, so export now 3018 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 3019 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 3020 cmp r0, #0 @ success? 3021 bne .LOP_SPUT_OBJECT_finish @ yes, finish 3022 b common_exceptionThrown @ no, handle exception 3023 3024 3025/* ------------------------------ */ 3026 .balign 64 3027.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3028/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3029/* File: armv5te/OP_SPUT.S */ 3030 /* 3031 * General 32-bit SPUT handler. 3032 * 3033 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3034 */ 3035 /* op vAA, field@BBBB */ 3036 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3037 FETCH(r1, 1) @ r1<- field ref BBBB 3038 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3039 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3040 cmp r0, #0 @ is resolved entry null? 3041 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3042.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3043 mov r2, rINST, lsr #8 @ r2<- AA 3044 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3045 GET_VREG(r1, r2) @ r1<- fp[AA] 3046 GET_INST_OPCODE(ip) @ extract opcode from rINST 3047 @ no-op @ releasing store 3048 str r1, [r0, #offStaticField_value] @ field<- vAA 3049 GOTO_OPCODE(ip) @ jump to next instruction 3050 3051 3052/* ------------------------------ */ 3053 .balign 64 3054.L_OP_SPUT_BYTE: /* 0x6b */ 3055/* File: armv5te/OP_SPUT_BYTE.S */ 3056/* File: armv5te/OP_SPUT.S */ 3057 /* 3058 * General 32-bit SPUT handler. 3059 * 3060 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3061 */ 3062 /* op vAA, field@BBBB */ 3063 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3064 FETCH(r1, 1) @ r1<- field ref BBBB 3065 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3066 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3067 cmp r0, #0 @ is resolved entry null? 3068 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3069.LOP_SPUT_BYTE_finish: @ field ptr in r0 3070 mov r2, rINST, lsr #8 @ r2<- AA 3071 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3072 GET_VREG(r1, r2) @ r1<- fp[AA] 3073 GET_INST_OPCODE(ip) @ extract opcode from rINST 3074 @ no-op @ releasing store 3075 str r1, [r0, #offStaticField_value] @ field<- vAA 3076 GOTO_OPCODE(ip) @ jump to next instruction 3077 3078 3079/* ------------------------------ */ 3080 .balign 64 3081.L_OP_SPUT_CHAR: /* 0x6c */ 3082/* File: armv5te/OP_SPUT_CHAR.S */ 3083/* File: armv5te/OP_SPUT.S */ 3084 /* 3085 * General 32-bit SPUT handler. 3086 * 3087 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3088 */ 3089 /* op vAA, field@BBBB */ 3090 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3091 FETCH(r1, 1) @ r1<- field ref BBBB 3092 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3093 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3094 cmp r0, #0 @ is resolved entry null? 3095 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3096.LOP_SPUT_CHAR_finish: @ field ptr in r0 3097 mov r2, rINST, lsr #8 @ r2<- AA 3098 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3099 GET_VREG(r1, r2) @ r1<- fp[AA] 3100 GET_INST_OPCODE(ip) @ extract opcode from rINST 3101 @ no-op @ releasing store 3102 str r1, [r0, #offStaticField_value] @ field<- vAA 3103 GOTO_OPCODE(ip) @ jump to next instruction 3104 3105 3106/* ------------------------------ */ 3107 .balign 64 3108.L_OP_SPUT_SHORT: /* 0x6d */ 3109/* File: armv5te/OP_SPUT_SHORT.S */ 3110/* File: armv5te/OP_SPUT.S */ 3111 /* 3112 * General 32-bit SPUT handler. 3113 * 3114 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3115 */ 3116 /* op vAA, field@BBBB */ 3117 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3118 FETCH(r1, 1) @ r1<- field ref BBBB 3119 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3120 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3121 cmp r0, #0 @ is resolved entry null? 3122 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3123.LOP_SPUT_SHORT_finish: @ field ptr in r0 3124 mov r2, rINST, lsr #8 @ r2<- AA 3125 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3126 GET_VREG(r1, r2) @ r1<- fp[AA] 3127 GET_INST_OPCODE(ip) @ extract opcode from rINST 3128 @ no-op @ releasing store 3129 str r1, [r0, #offStaticField_value] @ field<- vAA 3130 GOTO_OPCODE(ip) @ jump to next instruction 3131 3132 3133/* ------------------------------ */ 3134 .balign 64 3135.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3136/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3137 /* 3138 * Handle a virtual method call. 3139 * 3140 * for: invoke-virtual, invoke-virtual/range 3141 */ 3142 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3143 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3144 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3145 FETCH(r1, 1) @ r1<- BBBB 3146 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3147 FETCH(r10, 2) @ r10<- GFED or CCCC 3148 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3149 .if (!0) 3150 and r10, r10, #15 @ r10<- D (or stays CCCC) 3151 .endif 3152 cmp r0, #0 @ already resolved? 3153 EXPORT_PC() @ must export for invoke 3154 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3155 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3156 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3157 mov r2, #METHOD_VIRTUAL @ resolver method type 3158 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3159 cmp r0, #0 @ got null? 3160 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3161 b common_exceptionThrown @ yes, handle exception 3162 3163/* ------------------------------ */ 3164 .balign 64 3165.L_OP_INVOKE_SUPER: /* 0x6f */ 3166/* File: armv5te/OP_INVOKE_SUPER.S */ 3167 /* 3168 * Handle a "super" method call. 3169 * 3170 * for: invoke-super, invoke-super/range 3171 */ 3172 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3173 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3174 FETCH(r10, 2) @ r10<- GFED or CCCC 3175 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3176 .if (!0) 3177 and r10, r10, #15 @ r10<- D (or stays CCCC) 3178 .endif 3179 FETCH(r1, 1) @ r1<- BBBB 3180 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3181 GET_VREG(r2, r10) @ r2<- "this" ptr 3182 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3183 cmp r2, #0 @ null "this"? 3184 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3185 beq common_errNullObject @ null "this", throw exception 3186 cmp r0, #0 @ already resolved? 3187 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3188 EXPORT_PC() @ must export for invoke 3189 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3190 b .LOP_INVOKE_SUPER_resolve @ do resolve now 3191 3192/* ------------------------------ */ 3193 .balign 64 3194.L_OP_INVOKE_DIRECT: /* 0x70 */ 3195/* File: armv5te/OP_INVOKE_DIRECT.S */ 3196 /* 3197 * Handle a direct method call. 3198 * 3199 * (We could defer the "is 'this' pointer null" test to the common 3200 * method invocation code, and use a flag to indicate that static 3201 * calls don't count. If we do this as part of copying the arguments 3202 * out we could avoiding loading the first arg twice.) 3203 * 3204 * for: invoke-direct, invoke-direct/range 3205 */ 3206 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3207 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3208 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3209 FETCH(r1, 1) @ r1<- BBBB 3210 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3211 FETCH(r10, 2) @ r10<- GFED or CCCC 3212 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3213 .if (!0) 3214 and r10, r10, #15 @ r10<- D (or stays CCCC) 3215 .endif 3216 cmp r0, #0 @ already resolved? 3217 EXPORT_PC() @ must export for invoke 3218 GET_VREG(r2, r10) @ r2<- "this" ptr 3219 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3220.LOP_INVOKE_DIRECT_finish: 3221 cmp r2, #0 @ null "this" ref? 3222 bne common_invokeMethodNoRange @ no, continue on 3223 b common_errNullObject @ yes, throw exception 3224 3225/* ------------------------------ */ 3226 .balign 64 3227.L_OP_INVOKE_STATIC: /* 0x71 */ 3228/* File: armv5te/OP_INVOKE_STATIC.S */ 3229 /* 3230 * Handle a static method call. 3231 * 3232 * for: invoke-static, invoke-static/range 3233 */ 3234 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3235 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3236 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3237 FETCH(r1, 1) @ r1<- BBBB 3238 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3239 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3240 cmp r0, #0 @ already resolved? 3241 EXPORT_PC() @ must export for invoke 3242 bne common_invokeMethodNoRange @ yes, continue on 32430: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3244 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3245 mov r2, #METHOD_STATIC @ resolver method type 3246 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3247 cmp r0, #0 @ got null? 3248 bne common_invokeMethodNoRange @ no, continue 3249 b common_exceptionThrown @ yes, handle exception 3250 3251/* ------------------------------ */ 3252 .balign 64 3253.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3254/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3255 /* 3256 * Handle an interface method call. 3257 * 3258 * for: invoke-interface, invoke-interface/range 3259 */ 3260 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3261 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3262 FETCH(r2, 2) @ r2<- FEDC or CCCC 3263 FETCH(r1, 1) @ r1<- BBBB 3264 .if (!0) 3265 and r2, r2, #15 @ r2<- C (or stays CCCC) 3266 .endif 3267 EXPORT_PC() @ must export for invoke 3268 GET_VREG(r0, r2) @ r0<- first arg ("this") 3269 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3270 cmp r0, #0 @ null obj? 3271 ldr r2, [rSELF, #offThread_method] @ r2<- method 3272 beq common_errNullObject @ yes, fail 3273 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3274 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3275 cmp r0, #0 @ failed? 3276 beq common_exceptionThrown @ yes, handle exception 3277 b common_invokeMethodNoRange @ jump to common handler 3278 3279/* ------------------------------ */ 3280 .balign 64 3281.L_OP_UNUSED_73: /* 0x73 */ 3282/* File: armv5te/OP_UNUSED_73.S */ 3283/* File: armv5te/unused.S */ 3284 bl common_abort 3285 3286 3287/* ------------------------------ */ 3288 .balign 64 3289.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3290/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3291/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3292 /* 3293 * Handle a virtual method call. 3294 * 3295 * for: invoke-virtual, invoke-virtual/range 3296 */ 3297 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3298 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3299 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3300 FETCH(r1, 1) @ r1<- BBBB 3301 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3302 FETCH(r10, 2) @ r10<- GFED or CCCC 3303 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3304 .if (!1) 3305 and r10, r10, #15 @ r10<- D (or stays CCCC) 3306 .endif 3307 cmp r0, #0 @ already resolved? 3308 EXPORT_PC() @ must export for invoke 3309 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3310 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3311 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3312 mov r2, #METHOD_VIRTUAL @ resolver method type 3313 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3314 cmp r0, #0 @ got null? 3315 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3316 b common_exceptionThrown @ yes, handle exception 3317 3318 3319/* ------------------------------ */ 3320 .balign 64 3321.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3322/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3323/* File: armv5te/OP_INVOKE_SUPER.S */ 3324 /* 3325 * Handle a "super" method call. 3326 * 3327 * for: invoke-super, invoke-super/range 3328 */ 3329 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3330 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3331 FETCH(r10, 2) @ r10<- GFED or CCCC 3332 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3333 .if (!1) 3334 and r10, r10, #15 @ r10<- D (or stays CCCC) 3335 .endif 3336 FETCH(r1, 1) @ r1<- BBBB 3337 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3338 GET_VREG(r2, r10) @ r2<- "this" ptr 3339 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3340 cmp r2, #0 @ null "this"? 3341 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3342 beq common_errNullObject @ null "this", throw exception 3343 cmp r0, #0 @ already resolved? 3344 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3345 EXPORT_PC() @ must export for invoke 3346 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3347 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3348 3349 3350/* ------------------------------ */ 3351 .balign 64 3352.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3353/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3354/* File: armv5te/OP_INVOKE_DIRECT.S */ 3355 /* 3356 * Handle a direct method call. 3357 * 3358 * (We could defer the "is 'this' pointer null" test to the common 3359 * method invocation code, and use a flag to indicate that static 3360 * calls don't count. If we do this as part of copying the arguments 3361 * out we could avoiding loading the first arg twice.) 3362 * 3363 * for: invoke-direct, invoke-direct/range 3364 */ 3365 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3366 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3367 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3368 FETCH(r1, 1) @ r1<- BBBB 3369 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3370 FETCH(r10, 2) @ r10<- GFED or CCCC 3371 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3372 .if (!1) 3373 and r10, r10, #15 @ r10<- D (or stays CCCC) 3374 .endif 3375 cmp r0, #0 @ already resolved? 3376 EXPORT_PC() @ must export for invoke 3377 GET_VREG(r2, r10) @ r2<- "this" ptr 3378 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3379.LOP_INVOKE_DIRECT_RANGE_finish: 3380 cmp r2, #0 @ null "this" ref? 3381 bne common_invokeMethodRange @ no, continue on 3382 b common_errNullObject @ yes, throw exception 3383 3384 3385/* ------------------------------ */ 3386 .balign 64 3387.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3388/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3389/* File: armv5te/OP_INVOKE_STATIC.S */ 3390 /* 3391 * Handle a static method call. 3392 * 3393 * for: invoke-static, invoke-static/range 3394 */ 3395 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3396 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3397 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3398 FETCH(r1, 1) @ r1<- BBBB 3399 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3400 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3401 cmp r0, #0 @ already resolved? 3402 EXPORT_PC() @ must export for invoke 3403 bne common_invokeMethodRange @ yes, continue on 34040: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3405 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3406 mov r2, #METHOD_STATIC @ resolver method type 3407 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3408 cmp r0, #0 @ got null? 3409 bne common_invokeMethodRange @ no, continue 3410 b common_exceptionThrown @ yes, handle exception 3411 3412 3413/* ------------------------------ */ 3414 .balign 64 3415.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3416/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3417/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3418 /* 3419 * Handle an interface method call. 3420 * 3421 * for: invoke-interface, invoke-interface/range 3422 */ 3423 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3424 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3425 FETCH(r2, 2) @ r2<- FEDC or CCCC 3426 FETCH(r1, 1) @ r1<- BBBB 3427 .if (!1) 3428 and r2, r2, #15 @ r2<- C (or stays CCCC) 3429 .endif 3430 EXPORT_PC() @ must export for invoke 3431 GET_VREG(r0, r2) @ r0<- first arg ("this") 3432 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3433 cmp r0, #0 @ null obj? 3434 ldr r2, [rSELF, #offThread_method] @ r2<- method 3435 beq common_errNullObject @ yes, fail 3436 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3437 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3438 cmp r0, #0 @ failed? 3439 beq common_exceptionThrown @ yes, handle exception 3440 b common_invokeMethodRange @ jump to common handler 3441 3442 3443/* ------------------------------ */ 3444 .balign 64 3445.L_OP_UNUSED_79: /* 0x79 */ 3446/* File: armv5te/OP_UNUSED_79.S */ 3447/* File: armv5te/unused.S */ 3448 bl common_abort 3449 3450 3451/* ------------------------------ */ 3452 .balign 64 3453.L_OP_UNUSED_7A: /* 0x7a */ 3454/* File: armv5te/OP_UNUSED_7A.S */ 3455/* File: armv5te/unused.S */ 3456 bl common_abort 3457 3458 3459/* ------------------------------ */ 3460 .balign 64 3461.L_OP_NEG_INT: /* 0x7b */ 3462/* File: armv6t2/OP_NEG_INT.S */ 3463/* File: armv6t2/unop.S */ 3464 /* 3465 * Generic 32-bit unary operation. Provide an "instr" line that 3466 * specifies an instruction that performs "result = op r0". 3467 * This could be an ARM instruction or a function call. 3468 * 3469 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3470 * int-to-byte, int-to-char, int-to-short 3471 */ 3472 /* unop vA, vB */ 3473 mov r3, rINST, lsr #12 @ r3<- B 3474 ubfx r9, rINST, #8, #4 @ r9<- A 3475 GET_VREG(r0, r3) @ r0<- vB 3476 @ optional op; may set condition codes 3477 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3478 rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3479 GET_INST_OPCODE(ip) @ extract opcode from rINST 3480 SET_VREG(r0, r9) @ vAA<- r0 3481 GOTO_OPCODE(ip) @ jump to next instruction 3482 /* 8-9 instructions */ 3483 3484 3485/* ------------------------------ */ 3486 .balign 64 3487.L_OP_NOT_INT: /* 0x7c */ 3488/* File: armv6t2/OP_NOT_INT.S */ 3489/* File: armv6t2/unop.S */ 3490 /* 3491 * Generic 32-bit unary operation. Provide an "instr" line that 3492 * specifies an instruction that performs "result = op r0". 3493 * This could be an ARM instruction or a function call. 3494 * 3495 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3496 * int-to-byte, int-to-char, int-to-short 3497 */ 3498 /* unop vA, vB */ 3499 mov r3, rINST, lsr #12 @ r3<- B 3500 ubfx r9, rINST, #8, #4 @ r9<- A 3501 GET_VREG(r0, r3) @ r0<- vB 3502 @ optional op; may set condition codes 3503 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3504 mvn r0, r0 @ r0<- op, r0-r3 changed 3505 GET_INST_OPCODE(ip) @ extract opcode from rINST 3506 SET_VREG(r0, r9) @ vAA<- r0 3507 GOTO_OPCODE(ip) @ jump to next instruction 3508 /* 8-9 instructions */ 3509 3510 3511/* ------------------------------ */ 3512 .balign 64 3513.L_OP_NEG_LONG: /* 0x7d */ 3514/* File: armv6t2/OP_NEG_LONG.S */ 3515/* File: armv6t2/unopWide.S */ 3516 /* 3517 * Generic 64-bit unary operation. Provide an "instr" line that 3518 * specifies an instruction that performs "result = op r0/r1". 3519 * This could be an ARM instruction or a function call. 3520 * 3521 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3522 */ 3523 /* unop vA, vB */ 3524 mov r3, rINST, lsr #12 @ r3<- B 3525 ubfx r9, rINST, #8, #4 @ r9<- A 3526 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3527 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3528 ldmia r3, {r0-r1} @ r0/r1<- vAA 3529 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3530 rsbs r0, r0, #0 @ optional op; may set condition codes 3531 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3532 GET_INST_OPCODE(ip) @ extract opcode from rINST 3533 stmia r9, {r0-r1} @ vAA<- r0/r1 3534 GOTO_OPCODE(ip) @ jump to next instruction 3535 /* 10-11 instructions */ 3536 3537 3538/* ------------------------------ */ 3539 .balign 64 3540.L_OP_NOT_LONG: /* 0x7e */ 3541/* File: armv6t2/OP_NOT_LONG.S */ 3542/* File: armv6t2/unopWide.S */ 3543 /* 3544 * Generic 64-bit unary operation. Provide an "instr" line that 3545 * specifies an instruction that performs "result = op r0/r1". 3546 * This could be an ARM instruction or a function call. 3547 * 3548 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3549 */ 3550 /* unop vA, vB */ 3551 mov r3, rINST, lsr #12 @ r3<- B 3552 ubfx r9, rINST, #8, #4 @ r9<- A 3553 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3554 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3555 ldmia r3, {r0-r1} @ r0/r1<- vAA 3556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3557 mvn r0, r0 @ optional op; may set condition codes 3558 mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3559 GET_INST_OPCODE(ip) @ extract opcode from rINST 3560 stmia r9, {r0-r1} @ vAA<- r0/r1 3561 GOTO_OPCODE(ip) @ jump to next instruction 3562 /* 10-11 instructions */ 3563 3564 3565/* ------------------------------ */ 3566 .balign 64 3567.L_OP_NEG_FLOAT: /* 0x7f */ 3568/* File: armv6t2/OP_NEG_FLOAT.S */ 3569/* File: armv6t2/unop.S */ 3570 /* 3571 * Generic 32-bit unary operation. Provide an "instr" line that 3572 * specifies an instruction that performs "result = op r0". 3573 * This could be an ARM instruction or a function call. 3574 * 3575 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3576 * int-to-byte, int-to-char, int-to-short 3577 */ 3578 /* unop vA, vB */ 3579 mov r3, rINST, lsr #12 @ r3<- B 3580 ubfx r9, rINST, #8, #4 @ r9<- A 3581 GET_VREG(r0, r3) @ r0<- vB 3582 @ optional op; may set condition codes 3583 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3584 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3585 GET_INST_OPCODE(ip) @ extract opcode from rINST 3586 SET_VREG(r0, r9) @ vAA<- r0 3587 GOTO_OPCODE(ip) @ jump to next instruction 3588 /* 8-9 instructions */ 3589 3590 3591/* ------------------------------ */ 3592 .balign 64 3593.L_OP_NEG_DOUBLE: /* 0x80 */ 3594/* File: armv6t2/OP_NEG_DOUBLE.S */ 3595/* File: armv6t2/unopWide.S */ 3596 /* 3597 * Generic 64-bit unary operation. Provide an "instr" line that 3598 * specifies an instruction that performs "result = op r0/r1". 3599 * This could be an ARM instruction or a function call. 3600 * 3601 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3602 */ 3603 /* unop vA, vB */ 3604 mov r3, rINST, lsr #12 @ r3<- B 3605 ubfx r9, rINST, #8, #4 @ r9<- A 3606 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3607 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3608 ldmia r3, {r0-r1} @ r0/r1<- vAA 3609 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3610 @ optional op; may set condition codes 3611 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3612 GET_INST_OPCODE(ip) @ extract opcode from rINST 3613 stmia r9, {r0-r1} @ vAA<- r0/r1 3614 GOTO_OPCODE(ip) @ jump to next instruction 3615 /* 10-11 instructions */ 3616 3617 3618/* ------------------------------ */ 3619 .balign 64 3620.L_OP_INT_TO_LONG: /* 0x81 */ 3621/* File: armv6t2/OP_INT_TO_LONG.S */ 3622/* File: armv6t2/unopWider.S */ 3623 /* 3624 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3625 * that specifies an instruction that performs "result = op r0", where 3626 * "result" is a 64-bit quantity in r0/r1. 3627 * 3628 * For: int-to-long, int-to-double, float-to-long, float-to-double 3629 */ 3630 /* unop vA, vB */ 3631 mov r3, rINST, lsr #12 @ r3<- B 3632 ubfx r9, rINST, #8, #4 @ r9<- A 3633 GET_VREG(r0, r3) @ r0<- vB 3634 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3635 @ optional op; may set condition codes 3636 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3637 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3638 GET_INST_OPCODE(ip) @ extract opcode from rINST 3639 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3640 GOTO_OPCODE(ip) @ jump to next instruction 3641 /* 9-10 instructions */ 3642 3643 3644/* ------------------------------ */ 3645 .balign 64 3646.L_OP_INT_TO_FLOAT: /* 0x82 */ 3647/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3648/* File: arm-vfp/funop.S */ 3649 /* 3650 * Generic 32-bit unary floating-point operation. Provide an "instr" 3651 * line that specifies an instruction that performs "s1 = op s0". 3652 * 3653 * for: int-to-float, float-to-int 3654 */ 3655 /* unop vA, vB */ 3656 mov r3, rINST, lsr #12 @ r3<- B 3657 mov r9, rINST, lsr #8 @ r9<- A+ 3658 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3659 flds s0, [r3] @ s0<- vB 3660 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3661 and r9, r9, #15 @ r9<- A 3662 fsitos s1, s0 @ s1<- op 3663 GET_INST_OPCODE(ip) @ extract opcode from rINST 3664 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3665 fsts s1, [r9] @ vA<- s1 3666 GOTO_OPCODE(ip) @ jump to next instruction 3667 3668 3669/* ------------------------------ */ 3670 .balign 64 3671.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3672/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3673/* File: arm-vfp/funopWider.S */ 3674 /* 3675 * Generic 32bit-to-64bit floating point unary operation. Provide an 3676 * "instr" line that specifies an instruction that performs "d0 = op s0". 3677 * 3678 * For: int-to-double, float-to-double 3679 */ 3680 /* unop vA, vB */ 3681 mov r3, rINST, lsr #12 @ r3<- B 3682 mov r9, rINST, lsr #8 @ r9<- A+ 3683 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3684 flds s0, [r3] @ s0<- vB 3685 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3686 and r9, r9, #15 @ r9<- A 3687 fsitod d0, s0 @ d0<- op 3688 GET_INST_OPCODE(ip) @ extract opcode from rINST 3689 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3690 fstd d0, [r9] @ vA<- d0 3691 GOTO_OPCODE(ip) @ jump to next instruction 3692 3693 3694/* ------------------------------ */ 3695 .balign 64 3696.L_OP_LONG_TO_INT: /* 0x84 */ 3697/* File: armv5te/OP_LONG_TO_INT.S */ 3698/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3699/* File: armv5te/OP_MOVE.S */ 3700 /* for move, move-object, long-to-int */ 3701 /* op vA, vB */ 3702 mov r1, rINST, lsr #12 @ r1<- B from 15:12 3703 mov r0, rINST, lsr #8 @ r0<- A from 11:8 3704 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3705 GET_VREG(r2, r1) @ r2<- fp[B] 3706 and r0, r0, #15 3707 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3708 SET_VREG(r2, r0) @ fp[A]<- r2 3709 GOTO_OPCODE(ip) @ execute next instruction 3710 3711 3712/* ------------------------------ */ 3713 .balign 64 3714.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3715/* File: armv6t2/OP_LONG_TO_FLOAT.S */ 3716/* File: armv6t2/unopNarrower.S */ 3717 /* 3718 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3719 * that specifies an instruction that performs "result = op r0/r1", where 3720 * "result" is a 32-bit quantity in r0. 3721 * 3722 * For: long-to-float, double-to-int, double-to-float 3723 * 3724 * (This would work for long-to-int, but that instruction is actually 3725 * an exact match for OP_MOVE.) 3726 */ 3727 /* unop vA, vB */ 3728 mov r3, rINST, lsr #12 @ r3<- B 3729 ubfx r9, rINST, #8, #4 @ r9<- A 3730 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3731 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3732 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3733 @ optional op; may set condition codes 3734 bl __aeabi_l2f @ r0<- op, r0-r3 changed 3735 GET_INST_OPCODE(ip) @ extract opcode from rINST 3736 SET_VREG(r0, r9) @ vA<- r0 3737 GOTO_OPCODE(ip) @ jump to next instruction 3738 /* 9-10 instructions */ 3739 3740 3741/* ------------------------------ */ 3742 .balign 64 3743.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3744/* File: armv6t2/OP_LONG_TO_DOUBLE.S */ 3745/* File: armv6t2/unopWide.S */ 3746 /* 3747 * Generic 64-bit unary operation. Provide an "instr" line that 3748 * specifies an instruction that performs "result = op r0/r1". 3749 * This could be an ARM instruction or a function call. 3750 * 3751 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3752 */ 3753 /* unop vA, vB */ 3754 mov r3, rINST, lsr #12 @ r3<- B 3755 ubfx r9, rINST, #8, #4 @ r9<- A 3756 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3757 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3758 ldmia r3, {r0-r1} @ r0/r1<- vAA 3759 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3760 @ optional op; may set condition codes 3761 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3762 GET_INST_OPCODE(ip) @ extract opcode from rINST 3763 stmia r9, {r0-r1} @ vAA<- r0/r1 3764 GOTO_OPCODE(ip) @ jump to next instruction 3765 /* 10-11 instructions */ 3766 3767 3768/* ------------------------------ */ 3769 .balign 64 3770.L_OP_FLOAT_TO_INT: /* 0x87 */ 3771/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3772/* File: arm-vfp/funop.S */ 3773 /* 3774 * Generic 32-bit unary floating-point operation. Provide an "instr" 3775 * line that specifies an instruction that performs "s1 = op s0". 3776 * 3777 * for: int-to-float, float-to-int 3778 */ 3779 /* unop vA, vB */ 3780 mov r3, rINST, lsr #12 @ r3<- B 3781 mov r9, rINST, lsr #8 @ r9<- A+ 3782 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3783 flds s0, [r3] @ s0<- vB 3784 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3785 and r9, r9, #15 @ r9<- A 3786 ftosizs s1, s0 @ s1<- op 3787 GET_INST_OPCODE(ip) @ extract opcode from rINST 3788 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3789 fsts s1, [r9] @ vA<- s1 3790 GOTO_OPCODE(ip) @ jump to next instruction 3791 3792 3793/* ------------------------------ */ 3794 .balign 64 3795.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3796/* File: armv6t2/OP_FLOAT_TO_LONG.S */ 3797@include "armv6t2/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3798/* File: armv6t2/unopWider.S */ 3799 /* 3800 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3801 * that specifies an instruction that performs "result = op r0", where 3802 * "result" is a 64-bit quantity in r0/r1. 3803 * 3804 * For: int-to-long, int-to-double, float-to-long, float-to-double 3805 */ 3806 /* unop vA, vB */ 3807 mov r3, rINST, lsr #12 @ r3<- B 3808 ubfx r9, rINST, #8, #4 @ r9<- A 3809 GET_VREG(r0, r3) @ r0<- vB 3810 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3811 @ optional op; may set condition codes 3812 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3813 bl f2l_doconv @ r0<- op, r0-r3 changed 3814 GET_INST_OPCODE(ip) @ extract opcode from rINST 3815 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3816 GOTO_OPCODE(ip) @ jump to next instruction 3817 /* 9-10 instructions */ 3818 3819 3820 3821/* ------------------------------ */ 3822 .balign 64 3823.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3824/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3825/* File: arm-vfp/funopWider.S */ 3826 /* 3827 * Generic 32bit-to-64bit floating point unary operation. Provide an 3828 * "instr" line that specifies an instruction that performs "d0 = op s0". 3829 * 3830 * For: int-to-double, float-to-double 3831 */ 3832 /* unop vA, vB */ 3833 mov r3, rINST, lsr #12 @ r3<- B 3834 mov r9, rINST, lsr #8 @ r9<- A+ 3835 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3836 flds s0, [r3] @ s0<- vB 3837 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3838 and r9, r9, #15 @ r9<- A 3839 fcvtds d0, s0 @ d0<- op 3840 GET_INST_OPCODE(ip) @ extract opcode from rINST 3841 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3842 fstd d0, [r9] @ vA<- d0 3843 GOTO_OPCODE(ip) @ jump to next instruction 3844 3845 3846/* ------------------------------ */ 3847 .balign 64 3848.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3849/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3850/* File: arm-vfp/funopNarrower.S */ 3851 /* 3852 * Generic 64bit-to-32bit unary floating point operation. Provide an 3853 * "instr" line that specifies an instruction that performs "s0 = op d0". 3854 * 3855 * For: double-to-int, double-to-float 3856 */ 3857 /* unop vA, vB */ 3858 mov r3, rINST, lsr #12 @ r3<- B 3859 mov r9, rINST, lsr #8 @ r9<- A+ 3860 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3861 fldd d0, [r3] @ d0<- vB 3862 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3863 and r9, r9, #15 @ r9<- A 3864 ftosizd s0, d0 @ s0<- op 3865 GET_INST_OPCODE(ip) @ extract opcode from rINST 3866 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3867 fsts s0, [r9] @ vA<- s0 3868 GOTO_OPCODE(ip) @ jump to next instruction 3869 3870 3871/* ------------------------------ */ 3872 .balign 64 3873.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3874/* File: armv6t2/OP_DOUBLE_TO_LONG.S */ 3875@include "armv6t2/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3876/* File: armv6t2/unopWide.S */ 3877 /* 3878 * Generic 64-bit unary operation. Provide an "instr" line that 3879 * specifies an instruction that performs "result = op r0/r1". 3880 * This could be an ARM instruction or a function call. 3881 * 3882 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3883 */ 3884 /* unop vA, vB */ 3885 mov r3, rINST, lsr #12 @ r3<- B 3886 ubfx r9, rINST, #8, #4 @ r9<- A 3887 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3888 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3889 ldmia r3, {r0-r1} @ r0/r1<- vAA 3890 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3891 @ optional op; may set condition codes 3892 bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3893 GET_INST_OPCODE(ip) @ extract opcode from rINST 3894 stmia r9, {r0-r1} @ vAA<- r0/r1 3895 GOTO_OPCODE(ip) @ jump to next instruction 3896 /* 10-11 instructions */ 3897 3898 3899 3900/* ------------------------------ */ 3901 .balign 64 3902.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3903/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3904/* File: arm-vfp/funopNarrower.S */ 3905 /* 3906 * Generic 64bit-to-32bit unary floating point operation. Provide an 3907 * "instr" line that specifies an instruction that performs "s0 = op d0". 3908 * 3909 * For: double-to-int, double-to-float 3910 */ 3911 /* unop vA, vB */ 3912 mov r3, rINST, lsr #12 @ r3<- B 3913 mov r9, rINST, lsr #8 @ r9<- A+ 3914 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3915 fldd d0, [r3] @ d0<- vB 3916 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3917 and r9, r9, #15 @ r9<- A 3918 fcvtsd s0, d0 @ s0<- op 3919 GET_INST_OPCODE(ip) @ extract opcode from rINST 3920 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3921 fsts s0, [r9] @ vA<- s0 3922 GOTO_OPCODE(ip) @ jump to next instruction 3923 3924 3925/* ------------------------------ */ 3926 .balign 64 3927.L_OP_INT_TO_BYTE: /* 0x8d */ 3928/* File: armv6t2/OP_INT_TO_BYTE.S */ 3929/* File: armv6t2/unop.S */ 3930 /* 3931 * Generic 32-bit unary operation. Provide an "instr" line that 3932 * specifies an instruction that performs "result = op r0". 3933 * This could be an ARM instruction or a function call. 3934 * 3935 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3936 * int-to-byte, int-to-char, int-to-short 3937 */ 3938 /* unop vA, vB */ 3939 mov r3, rINST, lsr #12 @ r3<- B 3940 ubfx r9, rINST, #8, #4 @ r9<- A 3941 GET_VREG(r0, r3) @ r0<- vB 3942 @ optional op; may set condition codes 3943 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3944 sxtb r0, r0 @ r0<- op, r0-r3 changed 3945 GET_INST_OPCODE(ip) @ extract opcode from rINST 3946 SET_VREG(r0, r9) @ vAA<- r0 3947 GOTO_OPCODE(ip) @ jump to next instruction 3948 /* 8-9 instructions */ 3949 3950 3951/* ------------------------------ */ 3952 .balign 64 3953.L_OP_INT_TO_CHAR: /* 0x8e */ 3954/* File: armv6t2/OP_INT_TO_CHAR.S */ 3955/* File: armv6t2/unop.S */ 3956 /* 3957 * Generic 32-bit unary operation. Provide an "instr" line that 3958 * specifies an instruction that performs "result = op r0". 3959 * This could be an ARM instruction or a function call. 3960 * 3961 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3962 * int-to-byte, int-to-char, int-to-short 3963 */ 3964 /* unop vA, vB */ 3965 mov r3, rINST, lsr #12 @ r3<- B 3966 ubfx r9, rINST, #8, #4 @ r9<- A 3967 GET_VREG(r0, r3) @ r0<- vB 3968 @ optional op; may set condition codes 3969 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3970 uxth r0, r0 @ r0<- op, r0-r3 changed 3971 GET_INST_OPCODE(ip) @ extract opcode from rINST 3972 SET_VREG(r0, r9) @ vAA<- r0 3973 GOTO_OPCODE(ip) @ jump to next instruction 3974 /* 8-9 instructions */ 3975 3976 3977/* ------------------------------ */ 3978 .balign 64 3979.L_OP_INT_TO_SHORT: /* 0x8f */ 3980/* File: armv6t2/OP_INT_TO_SHORT.S */ 3981/* File: armv6t2/unop.S */ 3982 /* 3983 * Generic 32-bit unary operation. Provide an "instr" line that 3984 * specifies an instruction that performs "result = op r0". 3985 * This could be an ARM instruction or a function call. 3986 * 3987 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3988 * int-to-byte, int-to-char, int-to-short 3989 */ 3990 /* unop vA, vB */ 3991 mov r3, rINST, lsr #12 @ r3<- B 3992 ubfx r9, rINST, #8, #4 @ r9<- A 3993 GET_VREG(r0, r3) @ r0<- vB 3994 @ optional op; may set condition codes 3995 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3996 sxth r0, r0 @ r0<- op, r0-r3 changed 3997 GET_INST_OPCODE(ip) @ extract opcode from rINST 3998 SET_VREG(r0, r9) @ vAA<- r0 3999 GOTO_OPCODE(ip) @ jump to next instruction 4000 /* 8-9 instructions */ 4001 4002 4003/* ------------------------------ */ 4004 .balign 64 4005.L_OP_ADD_INT: /* 0x90 */ 4006/* File: armv5te/OP_ADD_INT.S */ 4007/* File: armv5te/binop.S */ 4008 /* 4009 * Generic 32-bit binary operation. Provide an "instr" line that 4010 * specifies an instruction that performs "result = r0 op r1". 4011 * This could be an ARM instruction or a function call. (If the result 4012 * comes back in a register other than r0, you can override "result".) 4013 * 4014 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4015 * vCC (r1). Useful for integer division and modulus. Note that we 4016 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4017 * handles it correctly. 4018 * 4019 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4020 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4021 * mul-float, div-float, rem-float 4022 */ 4023 /* binop vAA, vBB, vCC */ 4024 FETCH(r0, 1) @ r0<- CCBB 4025 mov r9, rINST, lsr #8 @ r9<- AA 4026 mov r3, r0, lsr #8 @ r3<- CC 4027 and r2, r0, #255 @ r2<- BB 4028 GET_VREG(r1, r3) @ r1<- vCC 4029 GET_VREG(r0, r2) @ r0<- vBB 4030 .if 0 4031 cmp r1, #0 @ is second operand zero? 4032 beq common_errDivideByZero 4033 .endif 4034 4035 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4036 @ optional op; may set condition codes 4037 add r0, r0, r1 @ r0<- op, r0-r3 changed 4038 GET_INST_OPCODE(ip) @ extract opcode from rINST 4039 SET_VREG(r0, r9) @ vAA<- r0 4040 GOTO_OPCODE(ip) @ jump to next instruction 4041 /* 11-14 instructions */ 4042 4043 4044/* ------------------------------ */ 4045 .balign 64 4046.L_OP_SUB_INT: /* 0x91 */ 4047/* File: armv5te/OP_SUB_INT.S */ 4048/* File: armv5te/binop.S */ 4049 /* 4050 * Generic 32-bit binary operation. Provide an "instr" line that 4051 * specifies an instruction that performs "result = r0 op r1". 4052 * This could be an ARM instruction or a function call. (If the result 4053 * comes back in a register other than r0, you can override "result".) 4054 * 4055 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4056 * vCC (r1). Useful for integer division and modulus. Note that we 4057 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4058 * handles it correctly. 4059 * 4060 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4061 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4062 * mul-float, div-float, rem-float 4063 */ 4064 /* binop vAA, vBB, vCC */ 4065 FETCH(r0, 1) @ r0<- CCBB 4066 mov r9, rINST, lsr #8 @ r9<- AA 4067 mov r3, r0, lsr #8 @ r3<- CC 4068 and r2, r0, #255 @ r2<- BB 4069 GET_VREG(r1, r3) @ r1<- vCC 4070 GET_VREG(r0, r2) @ r0<- vBB 4071 .if 0 4072 cmp r1, #0 @ is second operand zero? 4073 beq common_errDivideByZero 4074 .endif 4075 4076 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4077 @ optional op; may set condition codes 4078 sub r0, r0, r1 @ r0<- op, r0-r3 changed 4079 GET_INST_OPCODE(ip) @ extract opcode from rINST 4080 SET_VREG(r0, r9) @ vAA<- r0 4081 GOTO_OPCODE(ip) @ jump to next instruction 4082 /* 11-14 instructions */ 4083 4084 4085/* ------------------------------ */ 4086 .balign 64 4087.L_OP_MUL_INT: /* 0x92 */ 4088/* File: armv5te/OP_MUL_INT.S */ 4089/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4090/* File: armv5te/binop.S */ 4091 /* 4092 * Generic 32-bit binary operation. Provide an "instr" line that 4093 * specifies an instruction that performs "result = r0 op r1". 4094 * This could be an ARM instruction or a function call. (If the result 4095 * comes back in a register other than r0, you can override "result".) 4096 * 4097 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4098 * vCC (r1). Useful for integer division and modulus. Note that we 4099 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4100 * handles it correctly. 4101 * 4102 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4103 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4104 * mul-float, div-float, rem-float 4105 */ 4106 /* binop vAA, vBB, vCC */ 4107 FETCH(r0, 1) @ r0<- CCBB 4108 mov r9, rINST, lsr #8 @ r9<- AA 4109 mov r3, r0, lsr #8 @ r3<- CC 4110 and r2, r0, #255 @ r2<- BB 4111 GET_VREG(r1, r3) @ r1<- vCC 4112 GET_VREG(r0, r2) @ r0<- vBB 4113 .if 0 4114 cmp r1, #0 @ is second operand zero? 4115 beq common_errDivideByZero 4116 .endif 4117 4118 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4119 @ optional op; may set condition codes 4120 mul r0, r1, r0 @ r0<- op, r0-r3 changed 4121 GET_INST_OPCODE(ip) @ extract opcode from rINST 4122 SET_VREG(r0, r9) @ vAA<- r0 4123 GOTO_OPCODE(ip) @ jump to next instruction 4124 /* 11-14 instructions */ 4125 4126 4127/* ------------------------------ */ 4128 .balign 64 4129.L_OP_DIV_INT: /* 0x93 */ 4130/* File: armv5te/OP_DIV_INT.S */ 4131/* File: armv5te/binop.S */ 4132 /* 4133 * Generic 32-bit binary operation. Provide an "instr" line that 4134 * specifies an instruction that performs "result = r0 op r1". 4135 * This could be an ARM instruction or a function call. (If the result 4136 * comes back in a register other than r0, you can override "result".) 4137 * 4138 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4139 * vCC (r1). Useful for integer division and modulus. Note that we 4140 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4141 * handles it correctly. 4142 * 4143 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4144 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4145 * mul-float, div-float, rem-float 4146 */ 4147 /* binop vAA, vBB, vCC */ 4148 FETCH(r0, 1) @ r0<- CCBB 4149 mov r9, rINST, lsr #8 @ r9<- AA 4150 mov r3, r0, lsr #8 @ r3<- CC 4151 and r2, r0, #255 @ r2<- BB 4152 GET_VREG(r1, r3) @ r1<- vCC 4153 GET_VREG(r0, r2) @ r0<- vBB 4154 .if 1 4155 cmp r1, #0 @ is second operand zero? 4156 beq common_errDivideByZero 4157 .endif 4158 4159 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4160 @ optional op; may set condition codes 4161 bl __aeabi_idiv @ r0<- op, r0-r3 changed 4162 GET_INST_OPCODE(ip) @ extract opcode from rINST 4163 SET_VREG(r0, r9) @ vAA<- r0 4164 GOTO_OPCODE(ip) @ jump to next instruction 4165 /* 11-14 instructions */ 4166 4167 4168/* ------------------------------ */ 4169 .balign 64 4170.L_OP_REM_INT: /* 0x94 */ 4171/* File: armv5te/OP_REM_INT.S */ 4172/* idivmod returns quotient in r0 and remainder in r1 */ 4173/* File: armv5te/binop.S */ 4174 /* 4175 * Generic 32-bit binary operation. Provide an "instr" line that 4176 * specifies an instruction that performs "result = r0 op r1". 4177 * This could be an ARM instruction or a function call. (If the result 4178 * comes back in a register other than r0, you can override "result".) 4179 * 4180 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4181 * vCC (r1). Useful for integer division and modulus. Note that we 4182 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4183 * handles it correctly. 4184 * 4185 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4186 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4187 * mul-float, div-float, rem-float 4188 */ 4189 /* binop vAA, vBB, vCC */ 4190 FETCH(r0, 1) @ r0<- CCBB 4191 mov r9, rINST, lsr #8 @ r9<- AA 4192 mov r3, r0, lsr #8 @ r3<- CC 4193 and r2, r0, #255 @ r2<- BB 4194 GET_VREG(r1, r3) @ r1<- vCC 4195 GET_VREG(r0, r2) @ r0<- vBB 4196 .if 1 4197 cmp r1, #0 @ is second operand zero? 4198 beq common_errDivideByZero 4199 .endif 4200 4201 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4202 @ optional op; may set condition codes 4203 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4204 GET_INST_OPCODE(ip) @ extract opcode from rINST 4205 SET_VREG(r1, r9) @ vAA<- r1 4206 GOTO_OPCODE(ip) @ jump to next instruction 4207 /* 11-14 instructions */ 4208 4209 4210/* ------------------------------ */ 4211 .balign 64 4212.L_OP_AND_INT: /* 0x95 */ 4213/* File: armv5te/OP_AND_INT.S */ 4214/* File: armv5te/binop.S */ 4215 /* 4216 * Generic 32-bit binary operation. Provide an "instr" line that 4217 * specifies an instruction that performs "result = r0 op r1". 4218 * This could be an ARM instruction or a function call. (If the result 4219 * comes back in a register other than r0, you can override "result".) 4220 * 4221 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4222 * vCC (r1). Useful for integer division and modulus. Note that we 4223 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4224 * handles it correctly. 4225 * 4226 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4227 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4228 * mul-float, div-float, rem-float 4229 */ 4230 /* binop vAA, vBB, vCC */ 4231 FETCH(r0, 1) @ r0<- CCBB 4232 mov r9, rINST, lsr #8 @ r9<- AA 4233 mov r3, r0, lsr #8 @ r3<- CC 4234 and r2, r0, #255 @ r2<- BB 4235 GET_VREG(r1, r3) @ r1<- vCC 4236 GET_VREG(r0, r2) @ r0<- vBB 4237 .if 0 4238 cmp r1, #0 @ is second operand zero? 4239 beq common_errDivideByZero 4240 .endif 4241 4242 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4243 @ optional op; may set condition codes 4244 and r0, r0, r1 @ r0<- op, r0-r3 changed 4245 GET_INST_OPCODE(ip) @ extract opcode from rINST 4246 SET_VREG(r0, r9) @ vAA<- r0 4247 GOTO_OPCODE(ip) @ jump to next instruction 4248 /* 11-14 instructions */ 4249 4250 4251/* ------------------------------ */ 4252 .balign 64 4253.L_OP_OR_INT: /* 0x96 */ 4254/* File: armv5te/OP_OR_INT.S */ 4255/* File: armv5te/binop.S */ 4256 /* 4257 * Generic 32-bit binary operation. Provide an "instr" line that 4258 * specifies an instruction that performs "result = r0 op r1". 4259 * This could be an ARM instruction or a function call. (If the result 4260 * comes back in a register other than r0, you can override "result".) 4261 * 4262 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4263 * vCC (r1). Useful for integer division and modulus. Note that we 4264 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4265 * handles it correctly. 4266 * 4267 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4268 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4269 * mul-float, div-float, rem-float 4270 */ 4271 /* binop vAA, vBB, vCC */ 4272 FETCH(r0, 1) @ r0<- CCBB 4273 mov r9, rINST, lsr #8 @ r9<- AA 4274 mov r3, r0, lsr #8 @ r3<- CC 4275 and r2, r0, #255 @ r2<- BB 4276 GET_VREG(r1, r3) @ r1<- vCC 4277 GET_VREG(r0, r2) @ r0<- vBB 4278 .if 0 4279 cmp r1, #0 @ is second operand zero? 4280 beq common_errDivideByZero 4281 .endif 4282 4283 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4284 @ optional op; may set condition codes 4285 orr r0, r0, r1 @ r0<- op, r0-r3 changed 4286 GET_INST_OPCODE(ip) @ extract opcode from rINST 4287 SET_VREG(r0, r9) @ vAA<- r0 4288 GOTO_OPCODE(ip) @ jump to next instruction 4289 /* 11-14 instructions */ 4290 4291 4292/* ------------------------------ */ 4293 .balign 64 4294.L_OP_XOR_INT: /* 0x97 */ 4295/* File: armv5te/OP_XOR_INT.S */ 4296/* File: armv5te/binop.S */ 4297 /* 4298 * Generic 32-bit binary operation. Provide an "instr" line that 4299 * specifies an instruction that performs "result = r0 op r1". 4300 * This could be an ARM instruction or a function call. (If the result 4301 * comes back in a register other than r0, you can override "result".) 4302 * 4303 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4304 * vCC (r1). Useful for integer division and modulus. Note that we 4305 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4306 * handles it correctly. 4307 * 4308 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4309 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4310 * mul-float, div-float, rem-float 4311 */ 4312 /* binop vAA, vBB, vCC */ 4313 FETCH(r0, 1) @ r0<- CCBB 4314 mov r9, rINST, lsr #8 @ r9<- AA 4315 mov r3, r0, lsr #8 @ r3<- CC 4316 and r2, r0, #255 @ r2<- BB 4317 GET_VREG(r1, r3) @ r1<- vCC 4318 GET_VREG(r0, r2) @ r0<- vBB 4319 .if 0 4320 cmp r1, #0 @ is second operand zero? 4321 beq common_errDivideByZero 4322 .endif 4323 4324 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4325 @ optional op; may set condition codes 4326 eor r0, r0, r1 @ r0<- op, r0-r3 changed 4327 GET_INST_OPCODE(ip) @ extract opcode from rINST 4328 SET_VREG(r0, r9) @ vAA<- r0 4329 GOTO_OPCODE(ip) @ jump to next instruction 4330 /* 11-14 instructions */ 4331 4332 4333/* ------------------------------ */ 4334 .balign 64 4335.L_OP_SHL_INT: /* 0x98 */ 4336/* File: armv5te/OP_SHL_INT.S */ 4337/* File: armv5te/binop.S */ 4338 /* 4339 * Generic 32-bit binary operation. Provide an "instr" line that 4340 * specifies an instruction that performs "result = r0 op r1". 4341 * This could be an ARM instruction or a function call. (If the result 4342 * comes back in a register other than r0, you can override "result".) 4343 * 4344 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4345 * vCC (r1). Useful for integer division and modulus. Note that we 4346 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4347 * handles it correctly. 4348 * 4349 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4350 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4351 * mul-float, div-float, rem-float 4352 */ 4353 /* binop vAA, vBB, vCC */ 4354 FETCH(r0, 1) @ r0<- CCBB 4355 mov r9, rINST, lsr #8 @ r9<- AA 4356 mov r3, r0, lsr #8 @ r3<- CC 4357 and r2, r0, #255 @ r2<- BB 4358 GET_VREG(r1, r3) @ r1<- vCC 4359 GET_VREG(r0, r2) @ r0<- vBB 4360 .if 0 4361 cmp r1, #0 @ is second operand zero? 4362 beq common_errDivideByZero 4363 .endif 4364 4365 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4366 and r1, r1, #31 @ optional op; may set condition codes 4367 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4368 GET_INST_OPCODE(ip) @ extract opcode from rINST 4369 SET_VREG(r0, r9) @ vAA<- r0 4370 GOTO_OPCODE(ip) @ jump to next instruction 4371 /* 11-14 instructions */ 4372 4373 4374/* ------------------------------ */ 4375 .balign 64 4376.L_OP_SHR_INT: /* 0x99 */ 4377/* File: armv5te/OP_SHR_INT.S */ 4378/* File: armv5te/binop.S */ 4379 /* 4380 * Generic 32-bit binary operation. Provide an "instr" line that 4381 * specifies an instruction that performs "result = r0 op r1". 4382 * This could be an ARM instruction or a function call. (If the result 4383 * comes back in a register other than r0, you can override "result".) 4384 * 4385 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4386 * vCC (r1). Useful for integer division and modulus. Note that we 4387 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4388 * handles it correctly. 4389 * 4390 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4391 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4392 * mul-float, div-float, rem-float 4393 */ 4394 /* binop vAA, vBB, vCC */ 4395 FETCH(r0, 1) @ r0<- CCBB 4396 mov r9, rINST, lsr #8 @ r9<- AA 4397 mov r3, r0, lsr #8 @ r3<- CC 4398 and r2, r0, #255 @ r2<- BB 4399 GET_VREG(r1, r3) @ r1<- vCC 4400 GET_VREG(r0, r2) @ r0<- vBB 4401 .if 0 4402 cmp r1, #0 @ is second operand zero? 4403 beq common_errDivideByZero 4404 .endif 4405 4406 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4407 and r1, r1, #31 @ optional op; may set condition codes 4408 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4409 GET_INST_OPCODE(ip) @ extract opcode from rINST 4410 SET_VREG(r0, r9) @ vAA<- r0 4411 GOTO_OPCODE(ip) @ jump to next instruction 4412 /* 11-14 instructions */ 4413 4414 4415/* ------------------------------ */ 4416 .balign 64 4417.L_OP_USHR_INT: /* 0x9a */ 4418/* File: armv5te/OP_USHR_INT.S */ 4419/* File: armv5te/binop.S */ 4420 /* 4421 * Generic 32-bit binary operation. Provide an "instr" line that 4422 * specifies an instruction that performs "result = r0 op r1". 4423 * This could be an ARM instruction or a function call. (If the result 4424 * comes back in a register other than r0, you can override "result".) 4425 * 4426 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4427 * vCC (r1). Useful for integer division and modulus. Note that we 4428 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4429 * handles it correctly. 4430 * 4431 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4432 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4433 * mul-float, div-float, rem-float 4434 */ 4435 /* binop vAA, vBB, vCC */ 4436 FETCH(r0, 1) @ r0<- CCBB 4437 mov r9, rINST, lsr #8 @ r9<- AA 4438 mov r3, r0, lsr #8 @ r3<- CC 4439 and r2, r0, #255 @ r2<- BB 4440 GET_VREG(r1, r3) @ r1<- vCC 4441 GET_VREG(r0, r2) @ r0<- vBB 4442 .if 0 4443 cmp r1, #0 @ is second operand zero? 4444 beq common_errDivideByZero 4445 .endif 4446 4447 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4448 and r1, r1, #31 @ optional op; may set condition codes 4449 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4450 GET_INST_OPCODE(ip) @ extract opcode from rINST 4451 SET_VREG(r0, r9) @ vAA<- r0 4452 GOTO_OPCODE(ip) @ jump to next instruction 4453 /* 11-14 instructions */ 4454 4455 4456/* ------------------------------ */ 4457 .balign 64 4458.L_OP_ADD_LONG: /* 0x9b */ 4459/* File: armv5te/OP_ADD_LONG.S */ 4460/* File: armv5te/binopWide.S */ 4461 /* 4462 * Generic 64-bit binary operation. Provide an "instr" line that 4463 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4464 * This could be an ARM instruction or a function call. (If the result 4465 * comes back in a register other than r0, you can override "result".) 4466 * 4467 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4468 * vCC (r1). Useful for integer division and modulus. 4469 * 4470 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4471 * xor-long, add-double, sub-double, mul-double, div-double, 4472 * rem-double 4473 * 4474 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4475 */ 4476 /* binop vAA, vBB, vCC */ 4477 FETCH(r0, 1) @ r0<- CCBB 4478 mov r9, rINST, lsr #8 @ r9<- AA 4479 and r2, r0, #255 @ r2<- BB 4480 mov r3, r0, lsr #8 @ r3<- CC 4481 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4482 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4483 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4484 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4485 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4486 .if 0 4487 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4488 beq common_errDivideByZero 4489 .endif 4490 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4491 4492 adds r0, r0, r2 @ optional op; may set condition codes 4493 adc r1, r1, r3 @ result<- op, r0-r3 changed 4494 GET_INST_OPCODE(ip) @ extract opcode from rINST 4495 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4496 GOTO_OPCODE(ip) @ jump to next instruction 4497 /* 14-17 instructions */ 4498 4499 4500/* ------------------------------ */ 4501 .balign 64 4502.L_OP_SUB_LONG: /* 0x9c */ 4503/* File: armv5te/OP_SUB_LONG.S */ 4504/* File: armv5te/binopWide.S */ 4505 /* 4506 * Generic 64-bit binary operation. Provide an "instr" line that 4507 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4508 * This could be an ARM instruction or a function call. (If the result 4509 * comes back in a register other than r0, you can override "result".) 4510 * 4511 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4512 * vCC (r1). Useful for integer division and modulus. 4513 * 4514 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4515 * xor-long, add-double, sub-double, mul-double, div-double, 4516 * rem-double 4517 * 4518 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4519 */ 4520 /* binop vAA, vBB, vCC */ 4521 FETCH(r0, 1) @ r0<- CCBB 4522 mov r9, rINST, lsr #8 @ r9<- AA 4523 and r2, r0, #255 @ r2<- BB 4524 mov r3, r0, lsr #8 @ r3<- CC 4525 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4526 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4527 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4528 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4529 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4530 .if 0 4531 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4532 beq common_errDivideByZero 4533 .endif 4534 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4535 4536 subs r0, r0, r2 @ optional op; may set condition codes 4537 sbc r1, r1, r3 @ result<- op, r0-r3 changed 4538 GET_INST_OPCODE(ip) @ extract opcode from rINST 4539 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4540 GOTO_OPCODE(ip) @ jump to next instruction 4541 /* 14-17 instructions */ 4542 4543 4544/* ------------------------------ */ 4545 .balign 64 4546.L_OP_MUL_LONG: /* 0x9d */ 4547/* File: armv5te/OP_MUL_LONG.S */ 4548 /* 4549 * Signed 64-bit integer multiply. 4550 * 4551 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4552 * WX 4553 * x YZ 4554 * -------- 4555 * ZW ZX 4556 * YW YX 4557 * 4558 * The low word of the result holds ZX, the high word holds 4559 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4560 * it doesn't fit in the low 64 bits. 4561 * 4562 * Unlike most ARM math operations, multiply instructions have 4563 * restrictions on using the same register more than once (Rd and Rm 4564 * cannot be the same). 4565 */ 4566 /* mul-long vAA, vBB, vCC */ 4567 FETCH(r0, 1) @ r0<- CCBB 4568 and r2, r0, #255 @ r2<- BB 4569 mov r3, r0, lsr #8 @ r3<- CC 4570 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4571 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4572 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4573 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4574 mul ip, r2, r1 @ ip<- ZxW 4575 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4576 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4577 mov r0, rINST, lsr #8 @ r0<- AA 4578 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4579 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4580 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4581 b .LOP_MUL_LONG_finish 4582 4583/* ------------------------------ */ 4584 .balign 64 4585.L_OP_DIV_LONG: /* 0x9e */ 4586/* File: armv5te/OP_DIV_LONG.S */ 4587/* File: armv5te/binopWide.S */ 4588 /* 4589 * Generic 64-bit binary operation. Provide an "instr" line that 4590 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4591 * This could be an ARM instruction or a function call. (If the result 4592 * comes back in a register other than r0, you can override "result".) 4593 * 4594 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4595 * vCC (r1). Useful for integer division and modulus. 4596 * 4597 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4598 * xor-long, add-double, sub-double, mul-double, div-double, 4599 * rem-double 4600 * 4601 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4602 */ 4603 /* binop vAA, vBB, vCC */ 4604 FETCH(r0, 1) @ r0<- CCBB 4605 mov r9, rINST, lsr #8 @ r9<- AA 4606 and r2, r0, #255 @ r2<- BB 4607 mov r3, r0, lsr #8 @ r3<- CC 4608 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4609 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4610 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4611 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4612 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4613 .if 1 4614 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4615 beq common_errDivideByZero 4616 .endif 4617 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4618 4619 @ optional op; may set condition codes 4620 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4621 GET_INST_OPCODE(ip) @ extract opcode from rINST 4622 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4623 GOTO_OPCODE(ip) @ jump to next instruction 4624 /* 14-17 instructions */ 4625 4626 4627/* ------------------------------ */ 4628 .balign 64 4629.L_OP_REM_LONG: /* 0x9f */ 4630/* File: armv5te/OP_REM_LONG.S */ 4631/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4632/* File: armv5te/binopWide.S */ 4633 /* 4634 * Generic 64-bit binary operation. Provide an "instr" line that 4635 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4636 * This could be an ARM instruction or a function call. (If the result 4637 * comes back in a register other than r0, you can override "result".) 4638 * 4639 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4640 * vCC (r1). Useful for integer division and modulus. 4641 * 4642 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4643 * xor-long, add-double, sub-double, mul-double, div-double, 4644 * rem-double 4645 * 4646 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4647 */ 4648 /* binop vAA, vBB, vCC */ 4649 FETCH(r0, 1) @ r0<- CCBB 4650 mov r9, rINST, lsr #8 @ r9<- AA 4651 and r2, r0, #255 @ r2<- BB 4652 mov r3, r0, lsr #8 @ r3<- CC 4653 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4654 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4655 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4656 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4657 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4658 .if 1 4659 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4660 beq common_errDivideByZero 4661 .endif 4662 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4663 4664 @ optional op; may set condition codes 4665 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4666 GET_INST_OPCODE(ip) @ extract opcode from rINST 4667 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4668 GOTO_OPCODE(ip) @ jump to next instruction 4669 /* 14-17 instructions */ 4670 4671 4672/* ------------------------------ */ 4673 .balign 64 4674.L_OP_AND_LONG: /* 0xa0 */ 4675/* File: armv5te/OP_AND_LONG.S */ 4676/* File: armv5te/binopWide.S */ 4677 /* 4678 * Generic 64-bit binary operation. Provide an "instr" line that 4679 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4680 * This could be an ARM instruction or a function call. (If the result 4681 * comes back in a register other than r0, you can override "result".) 4682 * 4683 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4684 * vCC (r1). Useful for integer division and modulus. 4685 * 4686 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4687 * xor-long, add-double, sub-double, mul-double, div-double, 4688 * rem-double 4689 * 4690 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4691 */ 4692 /* binop vAA, vBB, vCC */ 4693 FETCH(r0, 1) @ r0<- CCBB 4694 mov r9, rINST, lsr #8 @ r9<- AA 4695 and r2, r0, #255 @ r2<- BB 4696 mov r3, r0, lsr #8 @ r3<- CC 4697 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4698 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4699 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4700 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4701 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4702 .if 0 4703 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4704 beq common_errDivideByZero 4705 .endif 4706 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4707 4708 and r0, r0, r2 @ optional op; may set condition codes 4709 and r1, r1, r3 @ result<- op, r0-r3 changed 4710 GET_INST_OPCODE(ip) @ extract opcode from rINST 4711 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4712 GOTO_OPCODE(ip) @ jump to next instruction 4713 /* 14-17 instructions */ 4714 4715 4716/* ------------------------------ */ 4717 .balign 64 4718.L_OP_OR_LONG: /* 0xa1 */ 4719/* File: armv5te/OP_OR_LONG.S */ 4720/* File: armv5te/binopWide.S */ 4721 /* 4722 * Generic 64-bit binary operation. Provide an "instr" line that 4723 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4724 * This could be an ARM instruction or a function call. (If the result 4725 * comes back in a register other than r0, you can override "result".) 4726 * 4727 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4728 * vCC (r1). Useful for integer division and modulus. 4729 * 4730 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4731 * xor-long, add-double, sub-double, mul-double, div-double, 4732 * rem-double 4733 * 4734 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4735 */ 4736 /* binop vAA, vBB, vCC */ 4737 FETCH(r0, 1) @ r0<- CCBB 4738 mov r9, rINST, lsr #8 @ r9<- AA 4739 and r2, r0, #255 @ r2<- BB 4740 mov r3, r0, lsr #8 @ r3<- CC 4741 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4742 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4743 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4744 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4745 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4746 .if 0 4747 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4748 beq common_errDivideByZero 4749 .endif 4750 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4751 4752 orr r0, r0, r2 @ optional op; may set condition codes 4753 orr r1, r1, r3 @ result<- op, r0-r3 changed 4754 GET_INST_OPCODE(ip) @ extract opcode from rINST 4755 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4756 GOTO_OPCODE(ip) @ jump to next instruction 4757 /* 14-17 instructions */ 4758 4759 4760/* ------------------------------ */ 4761 .balign 64 4762.L_OP_XOR_LONG: /* 0xa2 */ 4763/* File: armv5te/OP_XOR_LONG.S */ 4764/* File: armv5te/binopWide.S */ 4765 /* 4766 * Generic 64-bit binary operation. Provide an "instr" line that 4767 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4768 * This could be an ARM instruction or a function call. (If the result 4769 * comes back in a register other than r0, you can override "result".) 4770 * 4771 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4772 * vCC (r1). Useful for integer division and modulus. 4773 * 4774 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4775 * xor-long, add-double, sub-double, mul-double, div-double, 4776 * rem-double 4777 * 4778 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4779 */ 4780 /* binop vAA, vBB, vCC */ 4781 FETCH(r0, 1) @ r0<- CCBB 4782 mov r9, rINST, lsr #8 @ r9<- AA 4783 and r2, r0, #255 @ r2<- BB 4784 mov r3, r0, lsr #8 @ r3<- CC 4785 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4786 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4787 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4788 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4789 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4790 .if 0 4791 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4792 beq common_errDivideByZero 4793 .endif 4794 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4795 4796 eor r0, r0, r2 @ optional op; may set condition codes 4797 eor r1, r1, r3 @ result<- op, r0-r3 changed 4798 GET_INST_OPCODE(ip) @ extract opcode from rINST 4799 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4800 GOTO_OPCODE(ip) @ jump to next instruction 4801 /* 14-17 instructions */ 4802 4803 4804/* ------------------------------ */ 4805 .balign 64 4806.L_OP_SHL_LONG: /* 0xa3 */ 4807/* File: armv5te/OP_SHL_LONG.S */ 4808 /* 4809 * Long integer shift. This is different from the generic 32/64-bit 4810 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4811 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4812 * 6 bits of the shift distance. 4813 */ 4814 /* shl-long vAA, vBB, vCC */ 4815 FETCH(r0, 1) @ r0<- CCBB 4816 mov r9, rINST, lsr #8 @ r9<- AA 4817 and r3, r0, #255 @ r3<- BB 4818 mov r0, r0, lsr #8 @ r0<- CC 4819 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4820 GET_VREG(r2, r0) @ r2<- vCC 4821 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4822 and r2, r2, #63 @ r2<- r2 & 0x3f 4823 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4824 4825 mov r1, r1, asl r2 @ r1<- r1 << r2 4826 rsb r3, r2, #32 @ r3<- 32 - r2 4827 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4828 subs ip, r2, #32 @ ip<- r2 - 32 4829 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4830 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4831 b .LOP_SHL_LONG_finish 4832 4833/* ------------------------------ */ 4834 .balign 64 4835.L_OP_SHR_LONG: /* 0xa4 */ 4836/* File: armv5te/OP_SHR_LONG.S */ 4837 /* 4838 * Long integer shift. This is different from the generic 32/64-bit 4839 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4840 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4841 * 6 bits of the shift distance. 4842 */ 4843 /* shr-long vAA, vBB, vCC */ 4844 FETCH(r0, 1) @ r0<- CCBB 4845 mov r9, rINST, lsr #8 @ r9<- AA 4846 and r3, r0, #255 @ r3<- BB 4847 mov r0, r0, lsr #8 @ r0<- CC 4848 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4849 GET_VREG(r2, r0) @ r2<- vCC 4850 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4851 and r2, r2, #63 @ r0<- r0 & 0x3f 4852 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4853 4854 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4855 rsb r3, r2, #32 @ r3<- 32 - r2 4856 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4857 subs ip, r2, #32 @ ip<- r2 - 32 4858 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4859 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4860 b .LOP_SHR_LONG_finish 4861 4862/* ------------------------------ */ 4863 .balign 64 4864.L_OP_USHR_LONG: /* 0xa5 */ 4865/* File: armv5te/OP_USHR_LONG.S */ 4866 /* 4867 * Long integer shift. This is different from the generic 32/64-bit 4868 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4869 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4870 * 6 bits of the shift distance. 4871 */ 4872 /* ushr-long vAA, vBB, vCC */ 4873 FETCH(r0, 1) @ r0<- CCBB 4874 mov r9, rINST, lsr #8 @ r9<- AA 4875 and r3, r0, #255 @ r3<- BB 4876 mov r0, r0, lsr #8 @ r0<- CC 4877 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4878 GET_VREG(r2, r0) @ r2<- vCC 4879 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4880 and r2, r2, #63 @ r0<- r0 & 0x3f 4881 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4882 4883 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4884 rsb r3, r2, #32 @ r3<- 32 - r2 4885 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4886 subs ip, r2, #32 @ ip<- r2 - 32 4887 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4888 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4889 b .LOP_USHR_LONG_finish 4890 4891/* ------------------------------ */ 4892 .balign 64 4893.L_OP_ADD_FLOAT: /* 0xa6 */ 4894/* File: arm-vfp/OP_ADD_FLOAT.S */ 4895/* File: arm-vfp/fbinop.S */ 4896 /* 4897 * Generic 32-bit floating-point operation. Provide an "instr" line that 4898 * specifies an instruction that performs "s2 = s0 op s1". Because we 4899 * use the "softfp" ABI, this must be an instruction, not a function call. 4900 * 4901 * For: add-float, sub-float, mul-float, div-float 4902 */ 4903 /* floatop vAA, vBB, vCC */ 4904 FETCH(r0, 1) @ r0<- CCBB 4905 mov r9, rINST, lsr #8 @ r9<- AA 4906 mov r3, r0, lsr #8 @ r3<- CC 4907 and r2, r0, #255 @ r2<- BB 4908 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4909 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4910 flds s1, [r3] @ s1<- vCC 4911 flds s0, [r2] @ s0<- vBB 4912 4913 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4914 fadds s2, s0, s1 @ s2<- op 4915 GET_INST_OPCODE(ip) @ extract opcode from rINST 4916 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4917 fsts s2, [r9] @ vAA<- s2 4918 GOTO_OPCODE(ip) @ jump to next instruction 4919 4920 4921/* ------------------------------ */ 4922 .balign 64 4923.L_OP_SUB_FLOAT: /* 0xa7 */ 4924/* File: arm-vfp/OP_SUB_FLOAT.S */ 4925/* File: arm-vfp/fbinop.S */ 4926 /* 4927 * Generic 32-bit floating-point operation. Provide an "instr" line that 4928 * specifies an instruction that performs "s2 = s0 op s1". Because we 4929 * use the "softfp" ABI, this must be an instruction, not a function call. 4930 * 4931 * For: add-float, sub-float, mul-float, div-float 4932 */ 4933 /* floatop vAA, vBB, vCC */ 4934 FETCH(r0, 1) @ r0<- CCBB 4935 mov r9, rINST, lsr #8 @ r9<- AA 4936 mov r3, r0, lsr #8 @ r3<- CC 4937 and r2, r0, #255 @ r2<- BB 4938 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4939 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4940 flds s1, [r3] @ s1<- vCC 4941 flds s0, [r2] @ s0<- vBB 4942 4943 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4944 fsubs s2, s0, s1 @ s2<- op 4945 GET_INST_OPCODE(ip) @ extract opcode from rINST 4946 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4947 fsts s2, [r9] @ vAA<- s2 4948 GOTO_OPCODE(ip) @ jump to next instruction 4949 4950 4951/* ------------------------------ */ 4952 .balign 64 4953.L_OP_MUL_FLOAT: /* 0xa8 */ 4954/* File: arm-vfp/OP_MUL_FLOAT.S */ 4955/* File: arm-vfp/fbinop.S */ 4956 /* 4957 * Generic 32-bit floating-point operation. Provide an "instr" line that 4958 * specifies an instruction that performs "s2 = s0 op s1". Because we 4959 * use the "softfp" ABI, this must be an instruction, not a function call. 4960 * 4961 * For: add-float, sub-float, mul-float, div-float 4962 */ 4963 /* floatop vAA, vBB, vCC */ 4964 FETCH(r0, 1) @ r0<- CCBB 4965 mov r9, rINST, lsr #8 @ r9<- AA 4966 mov r3, r0, lsr #8 @ r3<- CC 4967 and r2, r0, #255 @ r2<- BB 4968 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4969 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4970 flds s1, [r3] @ s1<- vCC 4971 flds s0, [r2] @ s0<- vBB 4972 4973 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4974 fmuls s2, s0, s1 @ s2<- op 4975 GET_INST_OPCODE(ip) @ extract opcode from rINST 4976 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4977 fsts s2, [r9] @ vAA<- s2 4978 GOTO_OPCODE(ip) @ jump to next instruction 4979 4980 4981/* ------------------------------ */ 4982 .balign 64 4983.L_OP_DIV_FLOAT: /* 0xa9 */ 4984/* File: arm-vfp/OP_DIV_FLOAT.S */ 4985/* File: arm-vfp/fbinop.S */ 4986 /* 4987 * Generic 32-bit floating-point operation. Provide an "instr" line that 4988 * specifies an instruction that performs "s2 = s0 op s1". Because we 4989 * use the "softfp" ABI, this must be an instruction, not a function call. 4990 * 4991 * For: add-float, sub-float, mul-float, div-float 4992 */ 4993 /* floatop vAA, vBB, vCC */ 4994 FETCH(r0, 1) @ r0<- CCBB 4995 mov r9, rINST, lsr #8 @ r9<- AA 4996 mov r3, r0, lsr #8 @ r3<- CC 4997 and r2, r0, #255 @ r2<- BB 4998 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4999 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5000 flds s1, [r3] @ s1<- vCC 5001 flds s0, [r2] @ s0<- vBB 5002 5003 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5004 fdivs s2, s0, s1 @ s2<- op 5005 GET_INST_OPCODE(ip) @ extract opcode from rINST 5006 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5007 fsts s2, [r9] @ vAA<- s2 5008 GOTO_OPCODE(ip) @ jump to next instruction 5009 5010 5011/* ------------------------------ */ 5012 .balign 64 5013.L_OP_REM_FLOAT: /* 0xaa */ 5014/* File: armv5te/OP_REM_FLOAT.S */ 5015/* EABI doesn't define a float remainder function, but libm does */ 5016/* File: armv5te/binop.S */ 5017 /* 5018 * Generic 32-bit binary operation. Provide an "instr" line that 5019 * specifies an instruction that performs "result = r0 op r1". 5020 * This could be an ARM instruction or a function call. (If the result 5021 * comes back in a register other than r0, you can override "result".) 5022 * 5023 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5024 * vCC (r1). Useful for integer division and modulus. Note that we 5025 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5026 * handles it correctly. 5027 * 5028 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5029 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5030 * mul-float, div-float, rem-float 5031 */ 5032 /* binop vAA, vBB, vCC */ 5033 FETCH(r0, 1) @ r0<- CCBB 5034 mov r9, rINST, lsr #8 @ r9<- AA 5035 mov r3, r0, lsr #8 @ r3<- CC 5036 and r2, r0, #255 @ r2<- BB 5037 GET_VREG(r1, r3) @ r1<- vCC 5038 GET_VREG(r0, r2) @ r0<- vBB 5039 .if 0 5040 cmp r1, #0 @ is second operand zero? 5041 beq common_errDivideByZero 5042 .endif 5043 5044 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5045 @ optional op; may set condition codes 5046 bl fmodf @ r0<- op, r0-r3 changed 5047 GET_INST_OPCODE(ip) @ extract opcode from rINST 5048 SET_VREG(r0, r9) @ vAA<- r0 5049 GOTO_OPCODE(ip) @ jump to next instruction 5050 /* 11-14 instructions */ 5051 5052 5053/* ------------------------------ */ 5054 .balign 64 5055.L_OP_ADD_DOUBLE: /* 0xab */ 5056/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5057/* File: arm-vfp/fbinopWide.S */ 5058 /* 5059 * Generic 64-bit double-precision floating point binary operation. 5060 * Provide an "instr" line that specifies an instruction that performs 5061 * "d2 = d0 op d1". 5062 * 5063 * for: add-double, sub-double, mul-double, div-double 5064 */ 5065 /* doubleop vAA, vBB, vCC */ 5066 FETCH(r0, 1) @ r0<- CCBB 5067 mov r9, rINST, lsr #8 @ r9<- AA 5068 mov r3, r0, lsr #8 @ r3<- CC 5069 and r2, r0, #255 @ r2<- BB 5070 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5071 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5072 fldd d1, [r3] @ d1<- vCC 5073 fldd d0, [r2] @ d0<- vBB 5074 5075 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5076 faddd d2, d0, d1 @ s2<- op 5077 GET_INST_OPCODE(ip) @ extract opcode from rINST 5078 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5079 fstd d2, [r9] @ vAA<- d2 5080 GOTO_OPCODE(ip) @ jump to next instruction 5081 5082 5083/* ------------------------------ */ 5084 .balign 64 5085.L_OP_SUB_DOUBLE: /* 0xac */ 5086/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5087/* File: arm-vfp/fbinopWide.S */ 5088 /* 5089 * Generic 64-bit double-precision floating point binary operation. 5090 * Provide an "instr" line that specifies an instruction that performs 5091 * "d2 = d0 op d1". 5092 * 5093 * for: add-double, sub-double, mul-double, div-double 5094 */ 5095 /* doubleop vAA, vBB, vCC */ 5096 FETCH(r0, 1) @ r0<- CCBB 5097 mov r9, rINST, lsr #8 @ r9<- AA 5098 mov r3, r0, lsr #8 @ r3<- CC 5099 and r2, r0, #255 @ r2<- BB 5100 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5101 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5102 fldd d1, [r3] @ d1<- vCC 5103 fldd d0, [r2] @ d0<- vBB 5104 5105 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5106 fsubd d2, d0, d1 @ s2<- op 5107 GET_INST_OPCODE(ip) @ extract opcode from rINST 5108 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5109 fstd d2, [r9] @ vAA<- d2 5110 GOTO_OPCODE(ip) @ jump to next instruction 5111 5112 5113/* ------------------------------ */ 5114 .balign 64 5115.L_OP_MUL_DOUBLE: /* 0xad */ 5116/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5117/* File: arm-vfp/fbinopWide.S */ 5118 /* 5119 * Generic 64-bit double-precision floating point binary operation. 5120 * Provide an "instr" line that specifies an instruction that performs 5121 * "d2 = d0 op d1". 5122 * 5123 * for: add-double, sub-double, mul-double, div-double 5124 */ 5125 /* doubleop vAA, vBB, vCC */ 5126 FETCH(r0, 1) @ r0<- CCBB 5127 mov r9, rINST, lsr #8 @ r9<- AA 5128 mov r3, r0, lsr #8 @ r3<- CC 5129 and r2, r0, #255 @ r2<- BB 5130 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5131 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5132 fldd d1, [r3] @ d1<- vCC 5133 fldd d0, [r2] @ d0<- vBB 5134 5135 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5136 fmuld d2, d0, d1 @ s2<- op 5137 GET_INST_OPCODE(ip) @ extract opcode from rINST 5138 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5139 fstd d2, [r9] @ vAA<- d2 5140 GOTO_OPCODE(ip) @ jump to next instruction 5141 5142 5143/* ------------------------------ */ 5144 .balign 64 5145.L_OP_DIV_DOUBLE: /* 0xae */ 5146/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5147/* File: arm-vfp/fbinopWide.S */ 5148 /* 5149 * Generic 64-bit double-precision floating point binary operation. 5150 * Provide an "instr" line that specifies an instruction that performs 5151 * "d2 = d0 op d1". 5152 * 5153 * for: add-double, sub-double, mul-double, div-double 5154 */ 5155 /* doubleop vAA, vBB, vCC */ 5156 FETCH(r0, 1) @ r0<- CCBB 5157 mov r9, rINST, lsr #8 @ r9<- AA 5158 mov r3, r0, lsr #8 @ r3<- CC 5159 and r2, r0, #255 @ r2<- BB 5160 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5161 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5162 fldd d1, [r3] @ d1<- vCC 5163 fldd d0, [r2] @ d0<- vBB 5164 5165 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5166 fdivd d2, d0, d1 @ s2<- op 5167 GET_INST_OPCODE(ip) @ extract opcode from rINST 5168 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5169 fstd d2, [r9] @ vAA<- d2 5170 GOTO_OPCODE(ip) @ jump to next instruction 5171 5172 5173/* ------------------------------ */ 5174 .balign 64 5175.L_OP_REM_DOUBLE: /* 0xaf */ 5176/* File: armv5te/OP_REM_DOUBLE.S */ 5177/* EABI doesn't define a double remainder function, but libm does */ 5178/* File: armv5te/binopWide.S */ 5179 /* 5180 * Generic 64-bit binary operation. Provide an "instr" line that 5181 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5182 * This could be an ARM instruction or a function call. (If the result 5183 * comes back in a register other than r0, you can override "result".) 5184 * 5185 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5186 * vCC (r1). Useful for integer division and modulus. 5187 * 5188 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5189 * xor-long, add-double, sub-double, mul-double, div-double, 5190 * rem-double 5191 * 5192 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5193 */ 5194 /* binop vAA, vBB, vCC */ 5195 FETCH(r0, 1) @ r0<- CCBB 5196 mov r9, rINST, lsr #8 @ r9<- AA 5197 and r2, r0, #255 @ r2<- BB 5198 mov r3, r0, lsr #8 @ r3<- CC 5199 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5200 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5201 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5202 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5203 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5204 .if 0 5205 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5206 beq common_errDivideByZero 5207 .endif 5208 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5209 5210 @ optional op; may set condition codes 5211 bl fmod @ result<- op, r0-r3 changed 5212 GET_INST_OPCODE(ip) @ extract opcode from rINST 5213 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5214 GOTO_OPCODE(ip) @ jump to next instruction 5215 /* 14-17 instructions */ 5216 5217 5218/* ------------------------------ */ 5219 .balign 64 5220.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5221/* File: armv6t2/OP_ADD_INT_2ADDR.S */ 5222/* File: armv6t2/binop2addr.S */ 5223 /* 5224 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5225 * that specifies an instruction that performs "result = r0 op r1". 5226 * This could be an ARM instruction or a function call. (If the result 5227 * comes back in a register other than r0, you can override "result".) 5228 * 5229 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5230 * vCC (r1). Useful for integer division and modulus. 5231 * 5232 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5233 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5234 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5235 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5236 */ 5237 /* binop/2addr vA, vB */ 5238 mov r3, rINST, lsr #12 @ r3<- B 5239 ubfx r9, rINST, #8, #4 @ r9<- A 5240 GET_VREG(r1, r3) @ r1<- vB 5241 GET_VREG(r0, r9) @ r0<- vA 5242 .if 0 5243 cmp r1, #0 @ is second operand zero? 5244 beq common_errDivideByZero 5245 .endif 5246 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5247 5248 @ optional op; may set condition codes 5249 add r0, r0, r1 @ r0<- op, r0-r3 changed 5250 GET_INST_OPCODE(ip) @ extract opcode from rINST 5251 SET_VREG(r0, r9) @ vAA<- r0 5252 GOTO_OPCODE(ip) @ jump to next instruction 5253 /* 10-13 instructions */ 5254 5255 5256/* ------------------------------ */ 5257 .balign 64 5258.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5259/* File: armv6t2/OP_SUB_INT_2ADDR.S */ 5260/* File: armv6t2/binop2addr.S */ 5261 /* 5262 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5263 * that specifies an instruction that performs "result = r0 op r1". 5264 * This could be an ARM instruction or a function call. (If the result 5265 * comes back in a register other than r0, you can override "result".) 5266 * 5267 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5268 * vCC (r1). Useful for integer division and modulus. 5269 * 5270 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5271 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5272 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5273 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5274 */ 5275 /* binop/2addr vA, vB */ 5276 mov r3, rINST, lsr #12 @ r3<- B 5277 ubfx r9, rINST, #8, #4 @ r9<- A 5278 GET_VREG(r1, r3) @ r1<- vB 5279 GET_VREG(r0, r9) @ r0<- vA 5280 .if 0 5281 cmp r1, #0 @ is second operand zero? 5282 beq common_errDivideByZero 5283 .endif 5284 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5285 5286 @ optional op; may set condition codes 5287 sub r0, r0, r1 @ r0<- op, r0-r3 changed 5288 GET_INST_OPCODE(ip) @ extract opcode from rINST 5289 SET_VREG(r0, r9) @ vAA<- r0 5290 GOTO_OPCODE(ip) @ jump to next instruction 5291 /* 10-13 instructions */ 5292 5293 5294/* ------------------------------ */ 5295 .balign 64 5296.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5297/* File: armv6t2/OP_MUL_INT_2ADDR.S */ 5298/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5299/* File: armv6t2/binop2addr.S */ 5300 /* 5301 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5302 * that specifies an instruction that performs "result = r0 op r1". 5303 * This could be an ARM instruction or a function call. (If the result 5304 * comes back in a register other than r0, you can override "result".) 5305 * 5306 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5307 * vCC (r1). Useful for integer division and modulus. 5308 * 5309 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5310 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5311 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5312 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5313 */ 5314 /* binop/2addr vA, vB */ 5315 mov r3, rINST, lsr #12 @ r3<- B 5316 ubfx r9, rINST, #8, #4 @ r9<- A 5317 GET_VREG(r1, r3) @ r1<- vB 5318 GET_VREG(r0, r9) @ r0<- vA 5319 .if 0 5320 cmp r1, #0 @ is second operand zero? 5321 beq common_errDivideByZero 5322 .endif 5323 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5324 5325 @ optional op; may set condition codes 5326 mul r0, r1, r0 @ r0<- op, r0-r3 changed 5327 GET_INST_OPCODE(ip) @ extract opcode from rINST 5328 SET_VREG(r0, r9) @ vAA<- r0 5329 GOTO_OPCODE(ip) @ jump to next instruction 5330 /* 10-13 instructions */ 5331 5332 5333/* ------------------------------ */ 5334 .balign 64 5335.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5336/* File: armv6t2/OP_DIV_INT_2ADDR.S */ 5337/* File: armv6t2/binop2addr.S */ 5338 /* 5339 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5340 * that specifies an instruction that performs "result = r0 op r1". 5341 * This could be an ARM instruction or a function call. (If the result 5342 * comes back in a register other than r0, you can override "result".) 5343 * 5344 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5345 * vCC (r1). Useful for integer division and modulus. 5346 * 5347 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5348 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5349 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5350 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5351 */ 5352 /* binop/2addr vA, vB */ 5353 mov r3, rINST, lsr #12 @ r3<- B 5354 ubfx r9, rINST, #8, #4 @ r9<- A 5355 GET_VREG(r1, r3) @ r1<- vB 5356 GET_VREG(r0, r9) @ r0<- vA 5357 .if 1 5358 cmp r1, #0 @ is second operand zero? 5359 beq common_errDivideByZero 5360 .endif 5361 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5362 5363 @ optional op; may set condition codes 5364 bl __aeabi_idiv @ r0<- op, r0-r3 changed 5365 GET_INST_OPCODE(ip) @ extract opcode from rINST 5366 SET_VREG(r0, r9) @ vAA<- r0 5367 GOTO_OPCODE(ip) @ jump to next instruction 5368 /* 10-13 instructions */ 5369 5370 5371/* ------------------------------ */ 5372 .balign 64 5373.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5374/* File: armv6t2/OP_REM_INT_2ADDR.S */ 5375/* idivmod returns quotient in r0 and remainder in r1 */ 5376/* File: armv6t2/binop2addr.S */ 5377 /* 5378 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5379 * that specifies an instruction that performs "result = r0 op r1". 5380 * This could be an ARM instruction or a function call. (If the result 5381 * comes back in a register other than r0, you can override "result".) 5382 * 5383 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5384 * vCC (r1). Useful for integer division and modulus. 5385 * 5386 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5387 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5388 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5389 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5390 */ 5391 /* binop/2addr vA, vB */ 5392 mov r3, rINST, lsr #12 @ r3<- B 5393 ubfx r9, rINST, #8, #4 @ r9<- A 5394 GET_VREG(r1, r3) @ r1<- vB 5395 GET_VREG(r0, r9) @ r0<- vA 5396 .if 1 5397 cmp r1, #0 @ is second operand zero? 5398 beq common_errDivideByZero 5399 .endif 5400 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5401 5402 @ optional op; may set condition codes 5403 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5404 GET_INST_OPCODE(ip) @ extract opcode from rINST 5405 SET_VREG(r1, r9) @ vAA<- r1 5406 GOTO_OPCODE(ip) @ jump to next instruction 5407 /* 10-13 instructions */ 5408 5409 5410/* ------------------------------ */ 5411 .balign 64 5412.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5413/* File: armv6t2/OP_AND_INT_2ADDR.S */ 5414/* File: armv6t2/binop2addr.S */ 5415 /* 5416 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5417 * that specifies an instruction that performs "result = r0 op r1". 5418 * This could be an ARM instruction or a function call. (If the result 5419 * comes back in a register other than r0, you can override "result".) 5420 * 5421 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5422 * vCC (r1). Useful for integer division and modulus. 5423 * 5424 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5425 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5426 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5427 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5428 */ 5429 /* binop/2addr vA, vB */ 5430 mov r3, rINST, lsr #12 @ r3<- B 5431 ubfx r9, rINST, #8, #4 @ r9<- A 5432 GET_VREG(r1, r3) @ r1<- vB 5433 GET_VREG(r0, r9) @ r0<- vA 5434 .if 0 5435 cmp r1, #0 @ is second operand zero? 5436 beq common_errDivideByZero 5437 .endif 5438 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5439 5440 @ optional op; may set condition codes 5441 and r0, r0, r1 @ r0<- op, r0-r3 changed 5442 GET_INST_OPCODE(ip) @ extract opcode from rINST 5443 SET_VREG(r0, r9) @ vAA<- r0 5444 GOTO_OPCODE(ip) @ jump to next instruction 5445 /* 10-13 instructions */ 5446 5447 5448/* ------------------------------ */ 5449 .balign 64 5450.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5451/* File: armv6t2/OP_OR_INT_2ADDR.S */ 5452/* File: armv6t2/binop2addr.S */ 5453 /* 5454 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5455 * that specifies an instruction that performs "result = r0 op r1". 5456 * This could be an ARM instruction or a function call. (If the result 5457 * comes back in a register other than r0, you can override "result".) 5458 * 5459 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5460 * vCC (r1). Useful for integer division and modulus. 5461 * 5462 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5463 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5464 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5465 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5466 */ 5467 /* binop/2addr vA, vB */ 5468 mov r3, rINST, lsr #12 @ r3<- B 5469 ubfx r9, rINST, #8, #4 @ r9<- A 5470 GET_VREG(r1, r3) @ r1<- vB 5471 GET_VREG(r0, r9) @ r0<- vA 5472 .if 0 5473 cmp r1, #0 @ is second operand zero? 5474 beq common_errDivideByZero 5475 .endif 5476 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5477 5478 @ optional op; may set condition codes 5479 orr r0, r0, r1 @ r0<- op, r0-r3 changed 5480 GET_INST_OPCODE(ip) @ extract opcode from rINST 5481 SET_VREG(r0, r9) @ vAA<- r0 5482 GOTO_OPCODE(ip) @ jump to next instruction 5483 /* 10-13 instructions */ 5484 5485 5486/* ------------------------------ */ 5487 .balign 64 5488.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5489/* File: armv6t2/OP_XOR_INT_2ADDR.S */ 5490/* File: armv6t2/binop2addr.S */ 5491 /* 5492 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5493 * that specifies an instruction that performs "result = r0 op r1". 5494 * This could be an ARM instruction or a function call. (If the result 5495 * comes back in a register other than r0, you can override "result".) 5496 * 5497 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5498 * vCC (r1). Useful for integer division and modulus. 5499 * 5500 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5501 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5502 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5503 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5504 */ 5505 /* binop/2addr vA, vB */ 5506 mov r3, rINST, lsr #12 @ r3<- B 5507 ubfx r9, rINST, #8, #4 @ r9<- A 5508 GET_VREG(r1, r3) @ r1<- vB 5509 GET_VREG(r0, r9) @ r0<- vA 5510 .if 0 5511 cmp r1, #0 @ is second operand zero? 5512 beq common_errDivideByZero 5513 .endif 5514 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5515 5516 @ optional op; may set condition codes 5517 eor r0, r0, r1 @ r0<- op, r0-r3 changed 5518 GET_INST_OPCODE(ip) @ extract opcode from rINST 5519 SET_VREG(r0, r9) @ vAA<- r0 5520 GOTO_OPCODE(ip) @ jump to next instruction 5521 /* 10-13 instructions */ 5522 5523 5524/* ------------------------------ */ 5525 .balign 64 5526.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5527/* File: armv6t2/OP_SHL_INT_2ADDR.S */ 5528/* File: armv6t2/binop2addr.S */ 5529 /* 5530 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5531 * that specifies an instruction that performs "result = r0 op r1". 5532 * This could be an ARM instruction or a function call. (If the result 5533 * comes back in a register other than r0, you can override "result".) 5534 * 5535 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5536 * vCC (r1). Useful for integer division and modulus. 5537 * 5538 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5539 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5540 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5541 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5542 */ 5543 /* binop/2addr vA, vB */ 5544 mov r3, rINST, lsr #12 @ r3<- B 5545 ubfx r9, rINST, #8, #4 @ r9<- A 5546 GET_VREG(r1, r3) @ r1<- vB 5547 GET_VREG(r0, r9) @ r0<- vA 5548 .if 0 5549 cmp r1, #0 @ is second operand zero? 5550 beq common_errDivideByZero 5551 .endif 5552 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5553 5554 and r1, r1, #31 @ optional op; may set condition codes 5555 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5556 GET_INST_OPCODE(ip) @ extract opcode from rINST 5557 SET_VREG(r0, r9) @ vAA<- r0 5558 GOTO_OPCODE(ip) @ jump to next instruction 5559 /* 10-13 instructions */ 5560 5561 5562/* ------------------------------ */ 5563 .balign 64 5564.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5565/* File: armv6t2/OP_SHR_INT_2ADDR.S */ 5566/* File: armv6t2/binop2addr.S */ 5567 /* 5568 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5569 * that specifies an instruction that performs "result = r0 op r1". 5570 * This could be an ARM instruction or a function call. (If the result 5571 * comes back in a register other than r0, you can override "result".) 5572 * 5573 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5574 * vCC (r1). Useful for integer division and modulus. 5575 * 5576 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5577 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5578 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5579 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5580 */ 5581 /* binop/2addr vA, vB */ 5582 mov r3, rINST, lsr #12 @ r3<- B 5583 ubfx r9, rINST, #8, #4 @ r9<- A 5584 GET_VREG(r1, r3) @ r1<- vB 5585 GET_VREG(r0, r9) @ r0<- vA 5586 .if 0 5587 cmp r1, #0 @ is second operand zero? 5588 beq common_errDivideByZero 5589 .endif 5590 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5591 5592 and r1, r1, #31 @ optional op; may set condition codes 5593 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5594 GET_INST_OPCODE(ip) @ extract opcode from rINST 5595 SET_VREG(r0, r9) @ vAA<- r0 5596 GOTO_OPCODE(ip) @ jump to next instruction 5597 /* 10-13 instructions */ 5598 5599 5600/* ------------------------------ */ 5601 .balign 64 5602.L_OP_USHR_INT_2ADDR: /* 0xba */ 5603/* File: armv6t2/OP_USHR_INT_2ADDR.S */ 5604/* File: armv6t2/binop2addr.S */ 5605 /* 5606 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5607 * that specifies an instruction that performs "result = r0 op r1". 5608 * This could be an ARM instruction or a function call. (If the result 5609 * comes back in a register other than r0, you can override "result".) 5610 * 5611 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5612 * vCC (r1). Useful for integer division and modulus. 5613 * 5614 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5615 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5616 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5617 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5618 */ 5619 /* binop/2addr vA, vB */ 5620 mov r3, rINST, lsr #12 @ r3<- B 5621 ubfx r9, rINST, #8, #4 @ r9<- A 5622 GET_VREG(r1, r3) @ r1<- vB 5623 GET_VREG(r0, r9) @ r0<- vA 5624 .if 0 5625 cmp r1, #0 @ is second operand zero? 5626 beq common_errDivideByZero 5627 .endif 5628 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5629 5630 and r1, r1, #31 @ optional op; may set condition codes 5631 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5632 GET_INST_OPCODE(ip) @ extract opcode from rINST 5633 SET_VREG(r0, r9) @ vAA<- r0 5634 GOTO_OPCODE(ip) @ jump to next instruction 5635 /* 10-13 instructions */ 5636 5637 5638/* ------------------------------ */ 5639 .balign 64 5640.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5641/* File: armv6t2/OP_ADD_LONG_2ADDR.S */ 5642/* File: armv6t2/binopWide2addr.S */ 5643 /* 5644 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5645 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5646 * This could be an ARM instruction or a function call. (If the result 5647 * comes back in a register other than r0, you can override "result".) 5648 * 5649 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5650 * vCC (r1). Useful for integer division and modulus. 5651 * 5652 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5653 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5654 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5655 * rem-double/2addr 5656 */ 5657 /* binop/2addr vA, vB */ 5658 mov r1, rINST, lsr #12 @ r1<- B 5659 ubfx r9, rINST, #8, #4 @ r9<- A 5660 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5661 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5662 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5663 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5664 .if 0 5665 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5666 beq common_errDivideByZero 5667 .endif 5668 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5669 5670 adds r0, r0, r2 @ optional op; may set condition codes 5671 adc r1, r1, r3 @ result<- op, r0-r3 changed 5672 GET_INST_OPCODE(ip) @ extract opcode from rINST 5673 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5674 GOTO_OPCODE(ip) @ jump to next instruction 5675 /* 12-15 instructions */ 5676 5677 5678/* ------------------------------ */ 5679 .balign 64 5680.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5681/* File: armv6t2/OP_SUB_LONG_2ADDR.S */ 5682/* File: armv6t2/binopWide2addr.S */ 5683 /* 5684 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5685 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5686 * This could be an ARM instruction or a function call. (If the result 5687 * comes back in a register other than r0, you can override "result".) 5688 * 5689 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5690 * vCC (r1). Useful for integer division and modulus. 5691 * 5692 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5693 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5694 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5695 * rem-double/2addr 5696 */ 5697 /* binop/2addr vA, vB */ 5698 mov r1, rINST, lsr #12 @ r1<- B 5699 ubfx r9, rINST, #8, #4 @ r9<- A 5700 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5701 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5702 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5703 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5704 .if 0 5705 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5706 beq common_errDivideByZero 5707 .endif 5708 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5709 5710 subs r0, r0, r2 @ optional op; may set condition codes 5711 sbc r1, r1, r3 @ result<- op, r0-r3 changed 5712 GET_INST_OPCODE(ip) @ extract opcode from rINST 5713 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5714 GOTO_OPCODE(ip) @ jump to next instruction 5715 /* 12-15 instructions */ 5716 5717 5718/* ------------------------------ */ 5719 .balign 64 5720.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5721/* File: armv6t2/OP_MUL_LONG_2ADDR.S */ 5722 /* 5723 * Signed 64-bit integer multiply, "/2addr" version. 5724 * 5725 * See OP_MUL_LONG for an explanation. 5726 * 5727 * We get a little tight on registers, so to avoid looking up &fp[A] 5728 * again we stuff it into rINST. 5729 */ 5730 /* mul-long/2addr vA, vB */ 5731 mov r1, rINST, lsr #12 @ r1<- B 5732 ubfx r9, rINST, #8, #4 @ r9<- A 5733 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5734 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5735 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5736 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5737 mul ip, r2, r1 @ ip<- ZxW 5738 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5739 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5740 mov r0, rINST @ r0<- &fp[A] (free up rINST) 5741 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5742 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5743 GET_INST_OPCODE(ip) @ extract opcode from rINST 5744 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5745 GOTO_OPCODE(ip) @ jump to next instruction 5746 5747/* ------------------------------ */ 5748 .balign 64 5749.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5750/* File: armv6t2/OP_DIV_LONG_2ADDR.S */ 5751/* File: armv6t2/binopWide2addr.S */ 5752 /* 5753 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5754 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5755 * This could be an ARM instruction or a function call. (If the result 5756 * comes back in a register other than r0, you can override "result".) 5757 * 5758 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5759 * vCC (r1). Useful for integer division and modulus. 5760 * 5761 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5762 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5763 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5764 * rem-double/2addr 5765 */ 5766 /* binop/2addr vA, vB */ 5767 mov r1, rINST, lsr #12 @ r1<- B 5768 ubfx r9, rINST, #8, #4 @ r9<- A 5769 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5770 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5771 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5772 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5773 .if 1 5774 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5775 beq common_errDivideByZero 5776 .endif 5777 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5778 5779 @ optional op; may set condition codes 5780 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5781 GET_INST_OPCODE(ip) @ extract opcode from rINST 5782 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5783 GOTO_OPCODE(ip) @ jump to next instruction 5784 /* 12-15 instructions */ 5785 5786 5787/* ------------------------------ */ 5788 .balign 64 5789.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5790/* File: armv6t2/OP_REM_LONG_2ADDR.S */ 5791/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5792/* File: armv6t2/binopWide2addr.S */ 5793 /* 5794 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5795 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5796 * This could be an ARM instruction or a function call. (If the result 5797 * comes back in a register other than r0, you can override "result".) 5798 * 5799 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5800 * vCC (r1). Useful for integer division and modulus. 5801 * 5802 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5803 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5804 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5805 * rem-double/2addr 5806 */ 5807 /* binop/2addr vA, vB */ 5808 mov r1, rINST, lsr #12 @ r1<- B 5809 ubfx r9, rINST, #8, #4 @ r9<- A 5810 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5811 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5812 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5813 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5814 .if 1 5815 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5816 beq common_errDivideByZero 5817 .endif 5818 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5819 5820 @ optional op; may set condition codes 5821 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5822 GET_INST_OPCODE(ip) @ extract opcode from rINST 5823 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5824 GOTO_OPCODE(ip) @ jump to next instruction 5825 /* 12-15 instructions */ 5826 5827 5828/* ------------------------------ */ 5829 .balign 64 5830.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5831/* File: armv6t2/OP_AND_LONG_2ADDR.S */ 5832/* File: armv6t2/binopWide2addr.S */ 5833 /* 5834 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5835 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5836 * This could be an ARM instruction or a function call. (If the result 5837 * comes back in a register other than r0, you can override "result".) 5838 * 5839 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5840 * vCC (r1). Useful for integer division and modulus. 5841 * 5842 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5843 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5844 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5845 * rem-double/2addr 5846 */ 5847 /* binop/2addr vA, vB */ 5848 mov r1, rINST, lsr #12 @ r1<- B 5849 ubfx r9, rINST, #8, #4 @ r9<- A 5850 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5851 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5852 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5853 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5854 .if 0 5855 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5856 beq common_errDivideByZero 5857 .endif 5858 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5859 5860 and r0, r0, r2 @ optional op; may set condition codes 5861 and r1, r1, r3 @ result<- op, r0-r3 changed 5862 GET_INST_OPCODE(ip) @ extract opcode from rINST 5863 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5864 GOTO_OPCODE(ip) @ jump to next instruction 5865 /* 12-15 instructions */ 5866 5867 5868/* ------------------------------ */ 5869 .balign 64 5870.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5871/* File: armv6t2/OP_OR_LONG_2ADDR.S */ 5872/* File: armv6t2/binopWide2addr.S */ 5873 /* 5874 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5875 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5876 * This could be an ARM instruction or a function call. (If the result 5877 * comes back in a register other than r0, you can override "result".) 5878 * 5879 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5880 * vCC (r1). Useful for integer division and modulus. 5881 * 5882 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5883 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5884 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5885 * rem-double/2addr 5886 */ 5887 /* binop/2addr vA, vB */ 5888 mov r1, rINST, lsr #12 @ r1<- B 5889 ubfx r9, rINST, #8, #4 @ r9<- A 5890 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5891 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5892 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5893 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5894 .if 0 5895 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5896 beq common_errDivideByZero 5897 .endif 5898 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5899 5900 orr r0, r0, r2 @ optional op; may set condition codes 5901 orr r1, r1, r3 @ result<- op, r0-r3 changed 5902 GET_INST_OPCODE(ip) @ extract opcode from rINST 5903 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5904 GOTO_OPCODE(ip) @ jump to next instruction 5905 /* 12-15 instructions */ 5906 5907 5908/* ------------------------------ */ 5909 .balign 64 5910.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5911/* File: armv6t2/OP_XOR_LONG_2ADDR.S */ 5912/* File: armv6t2/binopWide2addr.S */ 5913 /* 5914 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5915 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5916 * This could be an ARM instruction or a function call. (If the result 5917 * comes back in a register other than r0, you can override "result".) 5918 * 5919 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5920 * vCC (r1). Useful for integer division and modulus. 5921 * 5922 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5923 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5924 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5925 * rem-double/2addr 5926 */ 5927 /* binop/2addr vA, vB */ 5928 mov r1, rINST, lsr #12 @ r1<- B 5929 ubfx r9, rINST, #8, #4 @ r9<- A 5930 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5931 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5932 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5933 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5934 .if 0 5935 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5936 beq common_errDivideByZero 5937 .endif 5938 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5939 5940 eor r0, r0, r2 @ optional op; may set condition codes 5941 eor r1, r1, r3 @ result<- op, r0-r3 changed 5942 GET_INST_OPCODE(ip) @ extract opcode from rINST 5943 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5944 GOTO_OPCODE(ip) @ jump to next instruction 5945 /* 12-15 instructions */ 5946 5947 5948/* ------------------------------ */ 5949 .balign 64 5950.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 5951/* File: armv6t2/OP_SHL_LONG_2ADDR.S */ 5952 /* 5953 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5954 * 32-bit shift distance. 5955 */ 5956 /* shl-long/2addr vA, vB */ 5957 mov r3, rINST, lsr #12 @ r3<- B 5958 ubfx r9, rINST, #8, #4 @ r9<- A 5959 GET_VREG(r2, r3) @ r2<- vB 5960 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5961 and r2, r2, #63 @ r2<- r2 & 0x3f 5962 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5963 5964 mov r1, r1, asl r2 @ r1<- r1 << r2 5965 rsb r3, r2, #32 @ r3<- 32 - r2 5966 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 5967 subs ip, r2, #32 @ ip<- r2 - 32 5968 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5969 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 5970 mov r0, r0, asl r2 @ r0<- r0 << r2 5971 b .LOP_SHL_LONG_2ADDR_finish 5972 5973/* ------------------------------ */ 5974 .balign 64 5975.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 5976/* File: armv6t2/OP_SHR_LONG_2ADDR.S */ 5977 /* 5978 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5979 * 32-bit shift distance. 5980 */ 5981 /* shr-long/2addr vA, vB */ 5982 mov r3, rINST, lsr #12 @ r3<- B 5983 ubfx r9, rINST, #8, #4 @ r9<- A 5984 GET_VREG(r2, r3) @ r2<- vB 5985 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5986 and r2, r2, #63 @ r2<- r2 & 0x3f 5987 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5988 5989 mov r0, r0, lsr r2 @ r0<- r2 >> r2 5990 rsb r3, r2, #32 @ r3<- 32 - r2 5991 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 5992 subs ip, r2, #32 @ ip<- r2 - 32 5993 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5994 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 5995 mov r1, r1, asr r2 @ r1<- r1 >> r2 5996 b .LOP_SHR_LONG_2ADDR_finish 5997 5998/* ------------------------------ */ 5999 .balign 64 6000.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6001/* File: armv6t2/OP_USHR_LONG_2ADDR.S */ 6002 /* 6003 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6004 * 32-bit shift distance. 6005 */ 6006 /* ushr-long/2addr vA, vB */ 6007 mov r3, rINST, lsr #12 @ r3<- B 6008 ubfx r9, rINST, #8, #4 @ r9<- A 6009 GET_VREG(r2, r3) @ r2<- vB 6010 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6011 and r2, r2, #63 @ r2<- r2 & 0x3f 6012 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6013 6014 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6015 rsb r3, r2, #32 @ r3<- 32 - r2 6016 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6017 subs ip, r2, #32 @ ip<- r2 - 32 6018 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6019 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6020 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6021 b .LOP_USHR_LONG_2ADDR_finish 6022 6023/* ------------------------------ */ 6024 .balign 64 6025.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6026/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6027/* File: arm-vfp/fbinop2addr.S */ 6028 /* 6029 * Generic 32-bit floating point "/2addr" binary operation. Provide 6030 * an "instr" line that specifies an instruction that performs 6031 * "s2 = s0 op s1". 6032 * 6033 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6034 */ 6035 /* binop/2addr vA, vB */ 6036 mov r3, rINST, lsr #12 @ r3<- B 6037 mov r9, rINST, lsr #8 @ r9<- A+ 6038 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6039 and r9, r9, #15 @ r9<- A 6040 flds s1, [r3] @ s1<- vB 6041 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6042 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6043 flds s0, [r9] @ s0<- vA 6044 6045 fadds s2, s0, s1 @ s2<- op 6046 GET_INST_OPCODE(ip) @ extract opcode from rINST 6047 fsts s2, [r9] @ vAA<- s2 6048 GOTO_OPCODE(ip) @ jump to next instruction 6049 6050 6051/* ------------------------------ */ 6052 .balign 64 6053.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6054/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6055/* File: arm-vfp/fbinop2addr.S */ 6056 /* 6057 * Generic 32-bit floating point "/2addr" binary operation. Provide 6058 * an "instr" line that specifies an instruction that performs 6059 * "s2 = s0 op s1". 6060 * 6061 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6062 */ 6063 /* binop/2addr vA, vB */ 6064 mov r3, rINST, lsr #12 @ r3<- B 6065 mov r9, rINST, lsr #8 @ r9<- A+ 6066 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6067 and r9, r9, #15 @ r9<- A 6068 flds s1, [r3] @ s1<- vB 6069 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6070 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6071 flds s0, [r9] @ s0<- vA 6072 6073 fsubs s2, s0, s1 @ s2<- op 6074 GET_INST_OPCODE(ip) @ extract opcode from rINST 6075 fsts s2, [r9] @ vAA<- s2 6076 GOTO_OPCODE(ip) @ jump to next instruction 6077 6078 6079/* ------------------------------ */ 6080 .balign 64 6081.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6082/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6083/* File: arm-vfp/fbinop2addr.S */ 6084 /* 6085 * Generic 32-bit floating point "/2addr" binary operation. Provide 6086 * an "instr" line that specifies an instruction that performs 6087 * "s2 = s0 op s1". 6088 * 6089 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6090 */ 6091 /* binop/2addr vA, vB */ 6092 mov r3, rINST, lsr #12 @ r3<- B 6093 mov r9, rINST, lsr #8 @ r9<- A+ 6094 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6095 and r9, r9, #15 @ r9<- A 6096 flds s1, [r3] @ s1<- vB 6097 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6098 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6099 flds s0, [r9] @ s0<- vA 6100 6101 fmuls s2, s0, s1 @ s2<- op 6102 GET_INST_OPCODE(ip) @ extract opcode from rINST 6103 fsts s2, [r9] @ vAA<- s2 6104 GOTO_OPCODE(ip) @ jump to next instruction 6105 6106 6107/* ------------------------------ */ 6108 .balign 64 6109.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6110/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6111/* File: arm-vfp/fbinop2addr.S */ 6112 /* 6113 * Generic 32-bit floating point "/2addr" binary operation. Provide 6114 * an "instr" line that specifies an instruction that performs 6115 * "s2 = s0 op s1". 6116 * 6117 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6118 */ 6119 /* binop/2addr vA, vB */ 6120 mov r3, rINST, lsr #12 @ r3<- B 6121 mov r9, rINST, lsr #8 @ r9<- A+ 6122 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6123 and r9, r9, #15 @ r9<- A 6124 flds s1, [r3] @ s1<- vB 6125 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6126 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6127 flds s0, [r9] @ s0<- vA 6128 6129 fdivs s2, s0, s1 @ s2<- op 6130 GET_INST_OPCODE(ip) @ extract opcode from rINST 6131 fsts s2, [r9] @ vAA<- s2 6132 GOTO_OPCODE(ip) @ jump to next instruction 6133 6134 6135/* ------------------------------ */ 6136 .balign 64 6137.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6138/* File: armv6t2/OP_REM_FLOAT_2ADDR.S */ 6139/* EABI doesn't define a float remainder function, but libm does */ 6140/* File: armv6t2/binop2addr.S */ 6141 /* 6142 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6143 * that specifies an instruction that performs "result = r0 op r1". 6144 * This could be an ARM instruction or a function call. (If the result 6145 * comes back in a register other than r0, you can override "result".) 6146 * 6147 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6148 * vCC (r1). Useful for integer division and modulus. 6149 * 6150 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6151 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6152 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6153 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6154 */ 6155 /* binop/2addr vA, vB */ 6156 mov r3, rINST, lsr #12 @ r3<- B 6157 ubfx r9, rINST, #8, #4 @ r9<- A 6158 GET_VREG(r1, r3) @ r1<- vB 6159 GET_VREG(r0, r9) @ r0<- vA 6160 .if 0 6161 cmp r1, #0 @ is second operand zero? 6162 beq common_errDivideByZero 6163 .endif 6164 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6165 6166 @ optional op; may set condition codes 6167 bl fmodf @ r0<- op, r0-r3 changed 6168 GET_INST_OPCODE(ip) @ extract opcode from rINST 6169 SET_VREG(r0, r9) @ vAA<- r0 6170 GOTO_OPCODE(ip) @ jump to next instruction 6171 /* 10-13 instructions */ 6172 6173 6174/* ------------------------------ */ 6175 .balign 64 6176.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6177/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6178/* File: arm-vfp/fbinopWide2addr.S */ 6179 /* 6180 * Generic 64-bit floating point "/2addr" binary operation. Provide 6181 * an "instr" line that specifies an instruction that performs 6182 * "d2 = d0 op d1". 6183 * 6184 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6185 * div-double/2addr 6186 */ 6187 /* binop/2addr vA, vB */ 6188 mov r3, rINST, lsr #12 @ r3<- B 6189 mov r9, rINST, lsr #8 @ r9<- A+ 6190 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6191 and r9, r9, #15 @ r9<- A 6192 fldd d1, [r3] @ d1<- vB 6193 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6194 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6195 fldd d0, [r9] @ d0<- vA 6196 6197 faddd d2, d0, d1 @ d2<- op 6198 GET_INST_OPCODE(ip) @ extract opcode from rINST 6199 fstd d2, [r9] @ vAA<- d2 6200 GOTO_OPCODE(ip) @ jump to next instruction 6201 6202 6203/* ------------------------------ */ 6204 .balign 64 6205.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6206/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6207/* File: arm-vfp/fbinopWide2addr.S */ 6208 /* 6209 * Generic 64-bit floating point "/2addr" binary operation. Provide 6210 * an "instr" line that specifies an instruction that performs 6211 * "d2 = d0 op d1". 6212 * 6213 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6214 * div-double/2addr 6215 */ 6216 /* binop/2addr vA, vB */ 6217 mov r3, rINST, lsr #12 @ r3<- B 6218 mov r9, rINST, lsr #8 @ r9<- A+ 6219 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6220 and r9, r9, #15 @ r9<- A 6221 fldd d1, [r3] @ d1<- vB 6222 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6223 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6224 fldd d0, [r9] @ d0<- vA 6225 6226 fsubd d2, d0, d1 @ d2<- op 6227 GET_INST_OPCODE(ip) @ extract opcode from rINST 6228 fstd d2, [r9] @ vAA<- d2 6229 GOTO_OPCODE(ip) @ jump to next instruction 6230 6231 6232/* ------------------------------ */ 6233 .balign 64 6234.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6235/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6236/* File: arm-vfp/fbinopWide2addr.S */ 6237 /* 6238 * Generic 64-bit floating point "/2addr" binary operation. Provide 6239 * an "instr" line that specifies an instruction that performs 6240 * "d2 = d0 op d1". 6241 * 6242 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6243 * div-double/2addr 6244 */ 6245 /* binop/2addr vA, vB */ 6246 mov r3, rINST, lsr #12 @ r3<- B 6247 mov r9, rINST, lsr #8 @ r9<- A+ 6248 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6249 and r9, r9, #15 @ r9<- A 6250 fldd d1, [r3] @ d1<- vB 6251 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6252 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6253 fldd d0, [r9] @ d0<- vA 6254 6255 fmuld d2, d0, d1 @ d2<- op 6256 GET_INST_OPCODE(ip) @ extract opcode from rINST 6257 fstd d2, [r9] @ vAA<- d2 6258 GOTO_OPCODE(ip) @ jump to next instruction 6259 6260 6261/* ------------------------------ */ 6262 .balign 64 6263.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6264/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6265/* File: arm-vfp/fbinopWide2addr.S */ 6266 /* 6267 * Generic 64-bit floating point "/2addr" binary operation. Provide 6268 * an "instr" line that specifies an instruction that performs 6269 * "d2 = d0 op d1". 6270 * 6271 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6272 * div-double/2addr 6273 */ 6274 /* binop/2addr vA, vB */ 6275 mov r3, rINST, lsr #12 @ r3<- B 6276 mov r9, rINST, lsr #8 @ r9<- A+ 6277 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6278 and r9, r9, #15 @ r9<- A 6279 fldd d1, [r3] @ d1<- vB 6280 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6281 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6282 fldd d0, [r9] @ d0<- vA 6283 6284 fdivd d2, d0, d1 @ d2<- op 6285 GET_INST_OPCODE(ip) @ extract opcode from rINST 6286 fstd d2, [r9] @ vAA<- d2 6287 GOTO_OPCODE(ip) @ jump to next instruction 6288 6289 6290/* ------------------------------ */ 6291 .balign 64 6292.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6293/* File: armv6t2/OP_REM_DOUBLE_2ADDR.S */ 6294/* EABI doesn't define a double remainder function, but libm does */ 6295/* File: armv6t2/binopWide2addr.S */ 6296 /* 6297 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6298 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6299 * This could be an ARM instruction or a function call. (If the result 6300 * comes back in a register other than r0, you can override "result".) 6301 * 6302 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6303 * vCC (r1). Useful for integer division and modulus. 6304 * 6305 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6306 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6307 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6308 * rem-double/2addr 6309 */ 6310 /* binop/2addr vA, vB */ 6311 mov r1, rINST, lsr #12 @ r1<- B 6312 ubfx r9, rINST, #8, #4 @ r9<- A 6313 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6314 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6315 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6316 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6317 .if 0 6318 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6319 beq common_errDivideByZero 6320 .endif 6321 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6322 6323 @ optional op; may set condition codes 6324 bl fmod @ result<- op, r0-r3 changed 6325 GET_INST_OPCODE(ip) @ extract opcode from rINST 6326 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6327 GOTO_OPCODE(ip) @ jump to next instruction 6328 /* 12-15 instructions */ 6329 6330 6331/* ------------------------------ */ 6332 .balign 64 6333.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6334/* File: armv6t2/OP_ADD_INT_LIT16.S */ 6335/* File: armv6t2/binopLit16.S */ 6336 /* 6337 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6338 * that specifies an instruction that performs "result = r0 op r1". 6339 * This could be an ARM instruction or a function call. (If the result 6340 * comes back in a register other than r0, you can override "result".) 6341 * 6342 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6343 * vCC (r1). Useful for integer division and modulus. 6344 * 6345 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6346 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6347 */ 6348 /* binop/lit16 vA, vB, #+CCCC */ 6349 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6350 mov r2, rINST, lsr #12 @ r2<- B 6351 ubfx r9, rINST, #8, #4 @ r9<- A 6352 GET_VREG(r0, r2) @ r0<- vB 6353 .if 0 6354 cmp r1, #0 @ is second operand zero? 6355 beq common_errDivideByZero 6356 .endif 6357 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6358 6359 add r0, r0, r1 @ r0<- op, r0-r3 changed 6360 GET_INST_OPCODE(ip) @ extract opcode from rINST 6361 SET_VREG(r0, r9) @ vAA<- r0 6362 GOTO_OPCODE(ip) @ jump to next instruction 6363 /* 10-13 instructions */ 6364 6365 6366/* ------------------------------ */ 6367 .balign 64 6368.L_OP_RSUB_INT: /* 0xd1 */ 6369/* File: armv6t2/OP_RSUB_INT.S */ 6370/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6371/* File: armv6t2/binopLit16.S */ 6372 /* 6373 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6374 * that specifies an instruction that performs "result = r0 op r1". 6375 * This could be an ARM instruction or a function call. (If the result 6376 * comes back in a register other than r0, you can override "result".) 6377 * 6378 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6379 * vCC (r1). Useful for integer division and modulus. 6380 * 6381 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6382 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6383 */ 6384 /* binop/lit16 vA, vB, #+CCCC */ 6385 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6386 mov r2, rINST, lsr #12 @ r2<- B 6387 ubfx r9, rINST, #8, #4 @ r9<- A 6388 GET_VREG(r0, r2) @ r0<- vB 6389 .if 0 6390 cmp r1, #0 @ is second operand zero? 6391 beq common_errDivideByZero 6392 .endif 6393 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6394 6395 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6396 GET_INST_OPCODE(ip) @ extract opcode from rINST 6397 SET_VREG(r0, r9) @ vAA<- r0 6398 GOTO_OPCODE(ip) @ jump to next instruction 6399 /* 10-13 instructions */ 6400 6401 6402/* ------------------------------ */ 6403 .balign 64 6404.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6405/* File: armv6t2/OP_MUL_INT_LIT16.S */ 6406/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6407/* File: armv6t2/binopLit16.S */ 6408 /* 6409 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6410 * that specifies an instruction that performs "result = r0 op r1". 6411 * This could be an ARM instruction or a function call. (If the result 6412 * comes back in a register other than r0, you can override "result".) 6413 * 6414 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6415 * vCC (r1). Useful for integer division and modulus. 6416 * 6417 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6418 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6419 */ 6420 /* binop/lit16 vA, vB, #+CCCC */ 6421 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6422 mov r2, rINST, lsr #12 @ r2<- B 6423 ubfx r9, rINST, #8, #4 @ r9<- A 6424 GET_VREG(r0, r2) @ r0<- vB 6425 .if 0 6426 cmp r1, #0 @ is second operand zero? 6427 beq common_errDivideByZero 6428 .endif 6429 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6430 6431 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6432 GET_INST_OPCODE(ip) @ extract opcode from rINST 6433 SET_VREG(r0, r9) @ vAA<- r0 6434 GOTO_OPCODE(ip) @ jump to next instruction 6435 /* 10-13 instructions */ 6436 6437 6438/* ------------------------------ */ 6439 .balign 64 6440.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6441/* File: armv6t2/OP_DIV_INT_LIT16.S */ 6442/* File: armv6t2/binopLit16.S */ 6443 /* 6444 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6445 * that specifies an instruction that performs "result = r0 op r1". 6446 * This could be an ARM instruction or a function call. (If the result 6447 * comes back in a register other than r0, you can override "result".) 6448 * 6449 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6450 * vCC (r1). Useful for integer division and modulus. 6451 * 6452 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6453 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6454 */ 6455 /* binop/lit16 vA, vB, #+CCCC */ 6456 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6457 mov r2, rINST, lsr #12 @ r2<- B 6458 ubfx r9, rINST, #8, #4 @ r9<- A 6459 GET_VREG(r0, r2) @ r0<- vB 6460 .if 1 6461 cmp r1, #0 @ is second operand zero? 6462 beq common_errDivideByZero 6463 .endif 6464 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6465 6466 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6467 GET_INST_OPCODE(ip) @ extract opcode from rINST 6468 SET_VREG(r0, r9) @ vAA<- r0 6469 GOTO_OPCODE(ip) @ jump to next instruction 6470 /* 10-13 instructions */ 6471 6472 6473/* ------------------------------ */ 6474 .balign 64 6475.L_OP_REM_INT_LIT16: /* 0xd4 */ 6476/* File: armv6t2/OP_REM_INT_LIT16.S */ 6477/* idivmod returns quotient in r0 and remainder in r1 */ 6478/* File: armv6t2/binopLit16.S */ 6479 /* 6480 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6481 * that specifies an instruction that performs "result = r0 op r1". 6482 * This could be an ARM instruction or a function call. (If the result 6483 * comes back in a register other than r0, you can override "result".) 6484 * 6485 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6486 * vCC (r1). Useful for integer division and modulus. 6487 * 6488 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6489 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6490 */ 6491 /* binop/lit16 vA, vB, #+CCCC */ 6492 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6493 mov r2, rINST, lsr #12 @ r2<- B 6494 ubfx r9, rINST, #8, #4 @ r9<- A 6495 GET_VREG(r0, r2) @ r0<- vB 6496 .if 1 6497 cmp r1, #0 @ is second operand zero? 6498 beq common_errDivideByZero 6499 .endif 6500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6501 6502 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6503 GET_INST_OPCODE(ip) @ extract opcode from rINST 6504 SET_VREG(r1, r9) @ vAA<- r1 6505 GOTO_OPCODE(ip) @ jump to next instruction 6506 /* 10-13 instructions */ 6507 6508 6509/* ------------------------------ */ 6510 .balign 64 6511.L_OP_AND_INT_LIT16: /* 0xd5 */ 6512/* File: armv6t2/OP_AND_INT_LIT16.S */ 6513/* File: armv6t2/binopLit16.S */ 6514 /* 6515 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6516 * that specifies an instruction that performs "result = r0 op r1". 6517 * This could be an ARM instruction or a function call. (If the result 6518 * comes back in a register other than r0, you can override "result".) 6519 * 6520 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6521 * vCC (r1). Useful for integer division and modulus. 6522 * 6523 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6524 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6525 */ 6526 /* binop/lit16 vA, vB, #+CCCC */ 6527 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6528 mov r2, rINST, lsr #12 @ r2<- B 6529 ubfx r9, rINST, #8, #4 @ r9<- A 6530 GET_VREG(r0, r2) @ r0<- vB 6531 .if 0 6532 cmp r1, #0 @ is second operand zero? 6533 beq common_errDivideByZero 6534 .endif 6535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6536 6537 and r0, r0, r1 @ r0<- op, r0-r3 changed 6538 GET_INST_OPCODE(ip) @ extract opcode from rINST 6539 SET_VREG(r0, r9) @ vAA<- r0 6540 GOTO_OPCODE(ip) @ jump to next instruction 6541 /* 10-13 instructions */ 6542 6543 6544/* ------------------------------ */ 6545 .balign 64 6546.L_OP_OR_INT_LIT16: /* 0xd6 */ 6547/* File: armv6t2/OP_OR_INT_LIT16.S */ 6548/* File: armv6t2/binopLit16.S */ 6549 /* 6550 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6551 * that specifies an instruction that performs "result = r0 op r1". 6552 * This could be an ARM instruction or a function call. (If the result 6553 * comes back in a register other than r0, you can override "result".) 6554 * 6555 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6556 * vCC (r1). Useful for integer division and modulus. 6557 * 6558 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6559 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6560 */ 6561 /* binop/lit16 vA, vB, #+CCCC */ 6562 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6563 mov r2, rINST, lsr #12 @ r2<- B 6564 ubfx r9, rINST, #8, #4 @ r9<- A 6565 GET_VREG(r0, r2) @ r0<- vB 6566 .if 0 6567 cmp r1, #0 @ is second operand zero? 6568 beq common_errDivideByZero 6569 .endif 6570 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6571 6572 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6573 GET_INST_OPCODE(ip) @ extract opcode from rINST 6574 SET_VREG(r0, r9) @ vAA<- r0 6575 GOTO_OPCODE(ip) @ jump to next instruction 6576 /* 10-13 instructions */ 6577 6578 6579/* ------------------------------ */ 6580 .balign 64 6581.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6582/* File: armv6t2/OP_XOR_INT_LIT16.S */ 6583/* File: armv6t2/binopLit16.S */ 6584 /* 6585 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6586 * that specifies an instruction that performs "result = r0 op r1". 6587 * This could be an ARM instruction or a function call. (If the result 6588 * comes back in a register other than r0, you can override "result".) 6589 * 6590 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6591 * vCC (r1). Useful for integer division and modulus. 6592 * 6593 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6594 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6595 */ 6596 /* binop/lit16 vA, vB, #+CCCC */ 6597 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6598 mov r2, rINST, lsr #12 @ r2<- B 6599 ubfx r9, rINST, #8, #4 @ r9<- A 6600 GET_VREG(r0, r2) @ r0<- vB 6601 .if 0 6602 cmp r1, #0 @ is second operand zero? 6603 beq common_errDivideByZero 6604 .endif 6605 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6606 6607 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6608 GET_INST_OPCODE(ip) @ extract opcode from rINST 6609 SET_VREG(r0, r9) @ vAA<- r0 6610 GOTO_OPCODE(ip) @ jump to next instruction 6611 /* 10-13 instructions */ 6612 6613 6614/* ------------------------------ */ 6615 .balign 64 6616.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6617/* File: armv5te/OP_ADD_INT_LIT8.S */ 6618/* File: armv5te/binopLit8.S */ 6619 /* 6620 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6621 * that specifies an instruction that performs "result = r0 op r1". 6622 * This could be an ARM instruction or a function call. (If the result 6623 * comes back in a register other than r0, you can override "result".) 6624 * 6625 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6626 * vCC (r1). Useful for integer division and modulus. 6627 * 6628 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6629 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6630 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6631 */ 6632 /* binop/lit8 vAA, vBB, #+CC */ 6633 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6634 mov r9, rINST, lsr #8 @ r9<- AA 6635 and r2, r3, #255 @ r2<- BB 6636 GET_VREG(r0, r2) @ r0<- vBB 6637 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6638 .if 0 6639 @cmp r1, #0 @ is second operand zero? 6640 beq common_errDivideByZero 6641 .endif 6642 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6643 6644 @ optional op; may set condition codes 6645 add r0, r0, r1 @ r0<- op, r0-r3 changed 6646 GET_INST_OPCODE(ip) @ extract opcode from rINST 6647 SET_VREG(r0, r9) @ vAA<- r0 6648 GOTO_OPCODE(ip) @ jump to next instruction 6649 /* 10-12 instructions */ 6650 6651 6652/* ------------------------------ */ 6653 .balign 64 6654.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6655/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6656/* File: armv5te/binopLit8.S */ 6657 /* 6658 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6659 * that specifies an instruction that performs "result = r0 op r1". 6660 * This could be an ARM instruction or a function call. (If the result 6661 * comes back in a register other than r0, you can override "result".) 6662 * 6663 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6664 * vCC (r1). Useful for integer division and modulus. 6665 * 6666 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6667 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6668 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6669 */ 6670 /* binop/lit8 vAA, vBB, #+CC */ 6671 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6672 mov r9, rINST, lsr #8 @ r9<- AA 6673 and r2, r3, #255 @ r2<- BB 6674 GET_VREG(r0, r2) @ r0<- vBB 6675 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6676 .if 0 6677 @cmp r1, #0 @ is second operand zero? 6678 beq common_errDivideByZero 6679 .endif 6680 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6681 6682 @ optional op; may set condition codes 6683 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6684 GET_INST_OPCODE(ip) @ extract opcode from rINST 6685 SET_VREG(r0, r9) @ vAA<- r0 6686 GOTO_OPCODE(ip) @ jump to next instruction 6687 /* 10-12 instructions */ 6688 6689 6690/* ------------------------------ */ 6691 .balign 64 6692.L_OP_MUL_INT_LIT8: /* 0xda */ 6693/* File: armv5te/OP_MUL_INT_LIT8.S */ 6694/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6695/* File: armv5te/binopLit8.S */ 6696 /* 6697 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6698 * that specifies an instruction that performs "result = r0 op r1". 6699 * This could be an ARM instruction or a function call. (If the result 6700 * comes back in a register other than r0, you can override "result".) 6701 * 6702 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6703 * vCC (r1). Useful for integer division and modulus. 6704 * 6705 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6706 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6707 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6708 */ 6709 /* binop/lit8 vAA, vBB, #+CC */ 6710 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6711 mov r9, rINST, lsr #8 @ r9<- AA 6712 and r2, r3, #255 @ r2<- BB 6713 GET_VREG(r0, r2) @ r0<- vBB 6714 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6715 .if 0 6716 @cmp r1, #0 @ is second operand zero? 6717 beq common_errDivideByZero 6718 .endif 6719 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6720 6721 @ optional op; may set condition codes 6722 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6723 GET_INST_OPCODE(ip) @ extract opcode from rINST 6724 SET_VREG(r0, r9) @ vAA<- r0 6725 GOTO_OPCODE(ip) @ jump to next instruction 6726 /* 10-12 instructions */ 6727 6728 6729/* ------------------------------ */ 6730 .balign 64 6731.L_OP_DIV_INT_LIT8: /* 0xdb */ 6732/* File: armv5te/OP_DIV_INT_LIT8.S */ 6733/* File: armv5te/binopLit8.S */ 6734 /* 6735 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6736 * that specifies an instruction that performs "result = r0 op r1". 6737 * This could be an ARM instruction or a function call. (If the result 6738 * comes back in a register other than r0, you can override "result".) 6739 * 6740 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6741 * vCC (r1). Useful for integer division and modulus. 6742 * 6743 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6744 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6745 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6746 */ 6747 /* binop/lit8 vAA, vBB, #+CC */ 6748 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6749 mov r9, rINST, lsr #8 @ r9<- AA 6750 and r2, r3, #255 @ r2<- BB 6751 GET_VREG(r0, r2) @ r0<- vBB 6752 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6753 .if 1 6754 @cmp r1, #0 @ is second operand zero? 6755 beq common_errDivideByZero 6756 .endif 6757 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6758 6759 @ optional op; may set condition codes 6760 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6761 GET_INST_OPCODE(ip) @ extract opcode from rINST 6762 SET_VREG(r0, r9) @ vAA<- r0 6763 GOTO_OPCODE(ip) @ jump to next instruction 6764 /* 10-12 instructions */ 6765 6766 6767/* ------------------------------ */ 6768 .balign 64 6769.L_OP_REM_INT_LIT8: /* 0xdc */ 6770/* File: armv5te/OP_REM_INT_LIT8.S */ 6771/* idivmod returns quotient in r0 and remainder in r1 */ 6772/* File: armv5te/binopLit8.S */ 6773 /* 6774 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6775 * that specifies an instruction that performs "result = r0 op r1". 6776 * This could be an ARM instruction or a function call. (If the result 6777 * comes back in a register other than r0, you can override "result".) 6778 * 6779 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6780 * vCC (r1). Useful for integer division and modulus. 6781 * 6782 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6783 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6784 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6785 */ 6786 /* binop/lit8 vAA, vBB, #+CC */ 6787 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6788 mov r9, rINST, lsr #8 @ r9<- AA 6789 and r2, r3, #255 @ r2<- BB 6790 GET_VREG(r0, r2) @ r0<- vBB 6791 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6792 .if 1 6793 @cmp r1, #0 @ is second operand zero? 6794 beq common_errDivideByZero 6795 .endif 6796 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6797 6798 @ optional op; may set condition codes 6799 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6800 GET_INST_OPCODE(ip) @ extract opcode from rINST 6801 SET_VREG(r1, r9) @ vAA<- r1 6802 GOTO_OPCODE(ip) @ jump to next instruction 6803 /* 10-12 instructions */ 6804 6805 6806/* ------------------------------ */ 6807 .balign 64 6808.L_OP_AND_INT_LIT8: /* 0xdd */ 6809/* File: armv5te/OP_AND_INT_LIT8.S */ 6810/* File: armv5te/binopLit8.S */ 6811 /* 6812 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6813 * that specifies an instruction that performs "result = r0 op r1". 6814 * This could be an ARM instruction or a function call. (If the result 6815 * comes back in a register other than r0, you can override "result".) 6816 * 6817 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6818 * vCC (r1). Useful for integer division and modulus. 6819 * 6820 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6821 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6822 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6823 */ 6824 /* binop/lit8 vAA, vBB, #+CC */ 6825 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6826 mov r9, rINST, lsr #8 @ r9<- AA 6827 and r2, r3, #255 @ r2<- BB 6828 GET_VREG(r0, r2) @ r0<- vBB 6829 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6830 .if 0 6831 @cmp r1, #0 @ is second operand zero? 6832 beq common_errDivideByZero 6833 .endif 6834 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6835 6836 @ optional op; may set condition codes 6837 and r0, r0, r1 @ r0<- op, r0-r3 changed 6838 GET_INST_OPCODE(ip) @ extract opcode from rINST 6839 SET_VREG(r0, r9) @ vAA<- r0 6840 GOTO_OPCODE(ip) @ jump to next instruction 6841 /* 10-12 instructions */ 6842 6843 6844/* ------------------------------ */ 6845 .balign 64 6846.L_OP_OR_INT_LIT8: /* 0xde */ 6847/* File: armv5te/OP_OR_INT_LIT8.S */ 6848/* File: armv5te/binopLit8.S */ 6849 /* 6850 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6851 * that specifies an instruction that performs "result = r0 op r1". 6852 * This could be an ARM instruction or a function call. (If the result 6853 * comes back in a register other than r0, you can override "result".) 6854 * 6855 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6856 * vCC (r1). Useful for integer division and modulus. 6857 * 6858 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6859 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6860 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6861 */ 6862 /* binop/lit8 vAA, vBB, #+CC */ 6863 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6864 mov r9, rINST, lsr #8 @ r9<- AA 6865 and r2, r3, #255 @ r2<- BB 6866 GET_VREG(r0, r2) @ r0<- vBB 6867 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6868 .if 0 6869 @cmp r1, #0 @ is second operand zero? 6870 beq common_errDivideByZero 6871 .endif 6872 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6873 6874 @ optional op; may set condition codes 6875 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6876 GET_INST_OPCODE(ip) @ extract opcode from rINST 6877 SET_VREG(r0, r9) @ vAA<- r0 6878 GOTO_OPCODE(ip) @ jump to next instruction 6879 /* 10-12 instructions */ 6880 6881 6882/* ------------------------------ */ 6883 .balign 64 6884.L_OP_XOR_INT_LIT8: /* 0xdf */ 6885/* File: armv5te/OP_XOR_INT_LIT8.S */ 6886/* File: armv5te/binopLit8.S */ 6887 /* 6888 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6889 * that specifies an instruction that performs "result = r0 op r1". 6890 * This could be an ARM instruction or a function call. (If the result 6891 * comes back in a register other than r0, you can override "result".) 6892 * 6893 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6894 * vCC (r1). Useful for integer division and modulus. 6895 * 6896 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6897 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6898 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6899 */ 6900 /* binop/lit8 vAA, vBB, #+CC */ 6901 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6902 mov r9, rINST, lsr #8 @ r9<- AA 6903 and r2, r3, #255 @ r2<- BB 6904 GET_VREG(r0, r2) @ r0<- vBB 6905 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6906 .if 0 6907 @cmp r1, #0 @ is second operand zero? 6908 beq common_errDivideByZero 6909 .endif 6910 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6911 6912 @ optional op; may set condition codes 6913 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6914 GET_INST_OPCODE(ip) @ extract opcode from rINST 6915 SET_VREG(r0, r9) @ vAA<- r0 6916 GOTO_OPCODE(ip) @ jump to next instruction 6917 /* 10-12 instructions */ 6918 6919 6920/* ------------------------------ */ 6921 .balign 64 6922.L_OP_SHL_INT_LIT8: /* 0xe0 */ 6923/* File: armv5te/OP_SHL_INT_LIT8.S */ 6924/* File: armv5te/binopLit8.S */ 6925 /* 6926 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6927 * that specifies an instruction that performs "result = r0 op r1". 6928 * This could be an ARM instruction or a function call. (If the result 6929 * comes back in a register other than r0, you can override "result".) 6930 * 6931 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6932 * vCC (r1). Useful for integer division and modulus. 6933 * 6934 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6935 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6936 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6937 */ 6938 /* binop/lit8 vAA, vBB, #+CC */ 6939 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6940 mov r9, rINST, lsr #8 @ r9<- AA 6941 and r2, r3, #255 @ r2<- BB 6942 GET_VREG(r0, r2) @ r0<- vBB 6943 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6944 .if 0 6945 @cmp r1, #0 @ is second operand zero? 6946 beq common_errDivideByZero 6947 .endif 6948 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6949 6950 and r1, r1, #31 @ optional op; may set condition codes 6951 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 6952 GET_INST_OPCODE(ip) @ extract opcode from rINST 6953 SET_VREG(r0, r9) @ vAA<- r0 6954 GOTO_OPCODE(ip) @ jump to next instruction 6955 /* 10-12 instructions */ 6956 6957 6958/* ------------------------------ */ 6959 .balign 64 6960.L_OP_SHR_INT_LIT8: /* 0xe1 */ 6961/* File: armv5te/OP_SHR_INT_LIT8.S */ 6962/* File: armv5te/binopLit8.S */ 6963 /* 6964 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6965 * that specifies an instruction that performs "result = r0 op r1". 6966 * This could be an ARM instruction or a function call. (If the result 6967 * comes back in a register other than r0, you can override "result".) 6968 * 6969 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6970 * vCC (r1). Useful for integer division and modulus. 6971 * 6972 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6973 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6974 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6975 */ 6976 /* binop/lit8 vAA, vBB, #+CC */ 6977 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6978 mov r9, rINST, lsr #8 @ r9<- AA 6979 and r2, r3, #255 @ r2<- BB 6980 GET_VREG(r0, r2) @ r0<- vBB 6981 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6982 .if 0 6983 @cmp r1, #0 @ is second operand zero? 6984 beq common_errDivideByZero 6985 .endif 6986 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6987 6988 and r1, r1, #31 @ optional op; may set condition codes 6989 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 6990 GET_INST_OPCODE(ip) @ extract opcode from rINST 6991 SET_VREG(r0, r9) @ vAA<- r0 6992 GOTO_OPCODE(ip) @ jump to next instruction 6993 /* 10-12 instructions */ 6994 6995 6996/* ------------------------------ */ 6997 .balign 64 6998.L_OP_USHR_INT_LIT8: /* 0xe2 */ 6999/* File: armv5te/OP_USHR_INT_LIT8.S */ 7000/* File: armv5te/binopLit8.S */ 7001 /* 7002 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7003 * that specifies an instruction that performs "result = r0 op r1". 7004 * This could be an ARM instruction or a function call. (If the result 7005 * comes back in a register other than r0, you can override "result".) 7006 * 7007 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7008 * vCC (r1). Useful for integer division and modulus. 7009 * 7010 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7011 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7012 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7013 */ 7014 /* binop/lit8 vAA, vBB, #+CC */ 7015 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7016 mov r9, rINST, lsr #8 @ r9<- AA 7017 and r2, r3, #255 @ r2<- BB 7018 GET_VREG(r0, r2) @ r0<- vBB 7019 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7020 .if 0 7021 @cmp r1, #0 @ is second operand zero? 7022 beq common_errDivideByZero 7023 .endif 7024 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7025 7026 and r1, r1, #31 @ optional op; may set condition codes 7027 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7028 GET_INST_OPCODE(ip) @ extract opcode from rINST 7029 SET_VREG(r0, r9) @ vAA<- r0 7030 GOTO_OPCODE(ip) @ jump to next instruction 7031 /* 10-12 instructions */ 7032 7033 7034/* ------------------------------ */ 7035 .balign 64 7036.L_OP_IGET_VOLATILE: /* 0xe3 */ 7037/* File: armv5te/OP_IGET_VOLATILE.S */ 7038/* File: armv5te/OP_IGET.S */ 7039 /* 7040 * General 32-bit instance field get. 7041 * 7042 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7043 */ 7044 /* op vA, vB, field@CCCC */ 7045 mov r0, rINST, lsr #12 @ r0<- B 7046 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7047 FETCH(r1, 1) @ r1<- field ref CCCC 7048 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7049 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7050 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7051 cmp r0, #0 @ is resolved entry null? 7052 bne .LOP_IGET_VOLATILE_finish @ no, already resolved 70538: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7054 EXPORT_PC() @ resolve() could throw 7055 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7056 bl dvmResolveInstField @ r0<- resolved InstField ptr 7057 cmp r0, #0 7058 bne .LOP_IGET_VOLATILE_finish 7059 b common_exceptionThrown 7060 7061 7062/* ------------------------------ */ 7063 .balign 64 7064.L_OP_IPUT_VOLATILE: /* 0xe4 */ 7065/* File: armv5te/OP_IPUT_VOLATILE.S */ 7066/* File: armv5te/OP_IPUT.S */ 7067 /* 7068 * General 32-bit instance field put. 7069 * 7070 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7071 */ 7072 /* op vA, vB, field@CCCC */ 7073 mov r0, rINST, lsr #12 @ r0<- B 7074 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7075 FETCH(r1, 1) @ r1<- field ref CCCC 7076 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7077 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7078 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7079 cmp r0, #0 @ is resolved entry null? 7080 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 70818: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7082 EXPORT_PC() @ resolve() could throw 7083 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7084 bl dvmResolveInstField @ r0<- resolved InstField ptr 7085 cmp r0, #0 @ success? 7086 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7087 b common_exceptionThrown 7088 7089 7090/* ------------------------------ */ 7091 .balign 64 7092.L_OP_SGET_VOLATILE: /* 0xe5 */ 7093/* File: armv5te/OP_SGET_VOLATILE.S */ 7094/* File: armv5te/OP_SGET.S */ 7095 /* 7096 * General 32-bit SGET handler. 7097 * 7098 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7099 */ 7100 /* op vAA, field@BBBB */ 7101 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7102 FETCH(r1, 1) @ r1<- field ref BBBB 7103 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7104 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7105 cmp r0, #0 @ is resolved entry null? 7106 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7107.LOP_SGET_VOLATILE_finish: @ field ptr in r0 7108 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7109 SMP_DMB @ acquiring load 7110 mov r2, rINST, lsr #8 @ r2<- AA 7111 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7112 SET_VREG(r1, r2) @ fp[AA]<- r1 7113 GET_INST_OPCODE(ip) @ extract opcode from rINST 7114 GOTO_OPCODE(ip) @ jump to next instruction 7115 7116 7117/* ------------------------------ */ 7118 .balign 64 7119.L_OP_SPUT_VOLATILE: /* 0xe6 */ 7120/* File: armv5te/OP_SPUT_VOLATILE.S */ 7121/* File: armv5te/OP_SPUT.S */ 7122 /* 7123 * General 32-bit SPUT handler. 7124 * 7125 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7126 */ 7127 /* op vAA, field@BBBB */ 7128 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7129 FETCH(r1, 1) @ r1<- field ref BBBB 7130 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7131 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7132 cmp r0, #0 @ is resolved entry null? 7133 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7134.LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7135 mov r2, rINST, lsr #8 @ r2<- AA 7136 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7137 GET_VREG(r1, r2) @ r1<- fp[AA] 7138 GET_INST_OPCODE(ip) @ extract opcode from rINST 7139 SMP_DMB @ releasing store 7140 str r1, [r0, #offStaticField_value] @ field<- vAA 7141 GOTO_OPCODE(ip) @ jump to next instruction 7142 7143 7144/* ------------------------------ */ 7145 .balign 64 7146.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7147/* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7148/* File: armv5te/OP_IGET.S */ 7149 /* 7150 * General 32-bit instance field get. 7151 * 7152 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7153 */ 7154 /* op vA, vB, field@CCCC */ 7155 mov r0, rINST, lsr #12 @ r0<- B 7156 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7157 FETCH(r1, 1) @ r1<- field ref CCCC 7158 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7159 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7160 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7161 cmp r0, #0 @ is resolved entry null? 7162 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 71638: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7164 EXPORT_PC() @ resolve() could throw 7165 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7166 bl dvmResolveInstField @ r0<- resolved InstField ptr 7167 cmp r0, #0 7168 bne .LOP_IGET_OBJECT_VOLATILE_finish 7169 b common_exceptionThrown 7170 7171 7172/* ------------------------------ */ 7173 .balign 64 7174.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 7175/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 7176/* File: armv5te/OP_IGET_WIDE.S */ 7177 /* 7178 * Wide 32-bit instance field get. 7179 */ 7180 /* iget-wide vA, vB, field@CCCC */ 7181 mov r0, rINST, lsr #12 @ r0<- B 7182 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7183 FETCH(r1, 1) @ r1<- field ref CCCC 7184 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7185 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7186 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7187 cmp r0, #0 @ is resolved entry null? 7188 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 71898: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7190 EXPORT_PC() @ resolve() could throw 7191 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7192 bl dvmResolveInstField @ r0<- resolved InstField ptr 7193 cmp r0, #0 7194 bne .LOP_IGET_WIDE_VOLATILE_finish 7195 b common_exceptionThrown 7196 7197 7198/* ------------------------------ */ 7199 .balign 64 7200.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 7201/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 7202/* File: armv5te/OP_IPUT_WIDE.S */ 7203 /* iput-wide vA, vB, field@CCCC */ 7204 mov r0, rINST, lsr #12 @ r0<- B 7205 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7206 FETCH(r1, 1) @ r1<- field ref CCCC 7207 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7208 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7209 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7210 cmp r0, #0 @ is resolved entry null? 7211 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 72128: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7213 EXPORT_PC() @ resolve() could throw 7214 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7215 bl dvmResolveInstField @ r0<- resolved InstField ptr 7216 cmp r0, #0 @ success? 7217 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 7218 b common_exceptionThrown 7219 7220 7221/* ------------------------------ */ 7222 .balign 64 7223.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 7224/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 7225/* File: armv5te/OP_SGET_WIDE.S */ 7226 /* 7227 * 64-bit SGET handler. 7228 */ 7229 /* sget-wide vAA, field@BBBB */ 7230 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7231 FETCH(r1, 1) @ r1<- field ref BBBB 7232 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7233 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7234 cmp r0, #0 @ is resolved entry null? 7235 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 7236.LOP_SGET_WIDE_VOLATILE_finish: 7237 mov r9, rINST, lsr #8 @ r9<- AA 7238 .if 1 7239 add r0, r0, #offStaticField_value @ r0<- pointer to data 7240 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7241 .else 7242 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7243 .endif 7244 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7245 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7246 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 7247 GET_INST_OPCODE(ip) @ extract opcode from rINST 7248 GOTO_OPCODE(ip) @ jump to next instruction 7249 7250 7251/* ------------------------------ */ 7252 .balign 64 7253.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 7254/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 7255/* File: armv5te/OP_SPUT_WIDE.S */ 7256 /* 7257 * 64-bit SPUT handler. 7258 */ 7259 /* sput-wide vAA, field@BBBB */ 7260 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 7261 FETCH(r1, 1) @ r1<- field ref BBBB 7262 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 7263 mov r9, rINST, lsr #8 @ r9<- AA 7264 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 7265 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7266 cmp r2, #0 @ is resolved entry null? 7267 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7268.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 7269 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7270 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7271 GET_INST_OPCODE(r10) @ extract opcode from rINST 7272 .if 1 7273 add r2, r2, #offStaticField_value @ r2<- pointer to data 7274 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 7275 .else 7276 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7277 .endif 7278 GOTO_OPCODE(r10) @ jump to next instruction 7279 7280 7281/* ------------------------------ */ 7282 .balign 64 7283.L_OP_BREAKPOINT: /* 0xec */ 7284/* File: armv5te/OP_BREAKPOINT.S */ 7285/* File: armv5te/unused.S */ 7286 bl common_abort 7287 7288 7289/* ------------------------------ */ 7290 .balign 64 7291.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7292/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7293 /* 7294 * Handle a throw-verification-error instruction. This throws an 7295 * exception for an error discovered during verification. The 7296 * exception is indicated by AA, with some detail provided by BBBB. 7297 */ 7298 /* op AA, ref@BBBB */ 7299 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 7300 FETCH(r2, 1) @ r2<- BBBB 7301 EXPORT_PC() @ export the PC 7302 mov r1, rINST, lsr #8 @ r1<- AA 7303 bl dvmThrowVerificationError @ always throws 7304 b common_exceptionThrown @ handle exception 7305 7306/* ------------------------------ */ 7307 .balign 64 7308.L_OP_EXECUTE_INLINE: /* 0xee */ 7309/* File: armv5te/OP_EXECUTE_INLINE.S */ 7310 /* 7311 * Execute a "native inline" instruction. 7312 * 7313 * We need to call an InlineOp4Func: 7314 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7315 * 7316 * The first four args are in r0-r3, pointer to return value storage 7317 * is on the stack. The function's return value is a flag that tells 7318 * us if an exception was thrown. 7319 */ 7320 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7321 FETCH(r10, 1) @ r10<- BBBB 7322 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7323 EXPORT_PC() @ can throw 7324 sub sp, sp, #8 @ make room for arg, +64 bit align 7325 mov r0, rINST, lsr #12 @ r0<- B 7326 str r1, [sp] @ push &self->retval 7327 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7328 add sp, sp, #8 @ pop stack 7329 cmp r0, #0 @ test boolean result of inline 7330 beq common_exceptionThrown @ returned false, handle exception 7331 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7332 GET_INST_OPCODE(ip) @ extract opcode from rINST 7333 GOTO_OPCODE(ip) @ jump to next instruction 7334 7335/* ------------------------------ */ 7336 .balign 64 7337.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7338/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7339 /* 7340 * Execute a "native inline" instruction, using "/range" semantics. 7341 * Same idea as execute-inline, but we get the args differently. 7342 * 7343 * We need to call an InlineOp4Func: 7344 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7345 * 7346 * The first four args are in r0-r3, pointer to return value storage 7347 * is on the stack. The function's return value is a flag that tells 7348 * us if an exception was thrown. 7349 */ 7350 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7351 FETCH(r10, 1) @ r10<- BBBB 7352 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7353 EXPORT_PC() @ can throw 7354 sub sp, sp, #8 @ make room for arg, +64 bit align 7355 mov r0, rINST, lsr #8 @ r0<- AA 7356 str r1, [sp] @ push &self->retval 7357 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7358 add sp, sp, #8 @ pop stack 7359 cmp r0, #0 @ test boolean result of inline 7360 beq common_exceptionThrown @ returned false, handle exception 7361 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7362 GET_INST_OPCODE(ip) @ extract opcode from rINST 7363 GOTO_OPCODE(ip) @ jump to next instruction 7364 7365/* ------------------------------ */ 7366 .balign 64 7367.L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 7368/* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */ 7369 /* 7370 * Invoke Object.<init> on an object. In practice we know that 7371 * Object's nullary constructor doesn't do anything, so we just 7372 * skip it (we know a debugger isn't active). 7373 */ 7374 FETCH(r1, 2) @ r1<- CCCC 7375 GET_VREG(r0, r1) @ r0<- "this" ptr 7376 cmp r0, #0 @ check for NULL 7377 beq common_errNullObject @ export PC and throw NPE 7378 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 7379 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 7380 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 7381 beq 1f @ nope, done 7382 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 73831: FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7384 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7385 GOTO_OPCODE(ip) @ execute it 7386 7387/* ------------------------------ */ 7388 .balign 64 7389.L_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 7390/* File: armv5te/OP_RETURN_VOID_BARRIER.S */ 7391 SMP_DMB_ST 7392 b common_returnFromMethod 7393 7394/* ------------------------------ */ 7395 .balign 64 7396.L_OP_IGET_QUICK: /* 0xf2 */ 7397/* File: armv6t2/OP_IGET_QUICK.S */ 7398 /* For: iget-quick, iget-object-quick */ 7399 /* op vA, vB, offset@CCCC */ 7400 mov r2, rINST, lsr #12 @ r2<- B 7401 FETCH(r1, 1) @ r1<- field byte offset 7402 GET_VREG(r3, r2) @ r3<- object we're operating on 7403 ubfx r2, rINST, #8, #4 @ r2<- A 7404 cmp r3, #0 @ check object for null 7405 beq common_errNullObject @ object was null 7406 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7407 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7408 GET_INST_OPCODE(ip) @ extract opcode from rINST 7409 SET_VREG(r0, r2) @ fp[A]<- r0 7410 GOTO_OPCODE(ip) @ jump to next instruction 7411 7412/* ------------------------------ */ 7413 .balign 64 7414.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7415/* File: armv6t2/OP_IGET_WIDE_QUICK.S */ 7416 /* iget-wide-quick vA, vB, offset@CCCC */ 7417 mov r2, rINST, lsr #12 @ r2<- B 7418 FETCH(ip, 1) @ ip<- field byte offset 7419 GET_VREG(r3, r2) @ r3<- object we're operating on 7420 ubfx r2, rINST, #8, #4 @ r2<- A 7421 cmp r3, #0 @ check object for null 7422 beq common_errNullObject @ object was null 7423 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7424 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7425 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7426 GET_INST_OPCODE(ip) @ extract opcode from rINST 7427 stmia r3, {r0-r1} @ fp[A]<- r0/r1 7428 GOTO_OPCODE(ip) @ jump to next instruction 7429 7430/* ------------------------------ */ 7431 .balign 64 7432.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7433/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7434/* File: armv5te/OP_IGET_QUICK.S */ 7435 /* For: iget-quick, iget-object-quick */ 7436 /* op vA, vB, offset@CCCC */ 7437 mov r2, rINST, lsr #12 @ r2<- B 7438 GET_VREG(r3, r2) @ r3<- object we're operating on 7439 FETCH(r1, 1) @ r1<- field byte offset 7440 cmp r3, #0 @ check object for null 7441 mov r2, rINST, lsr #8 @ r2<- A(+) 7442 beq common_errNullObject @ object was null 7443 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7444 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7445 and r2, r2, #15 7446 GET_INST_OPCODE(ip) @ extract opcode from rINST 7447 SET_VREG(r0, r2) @ fp[A]<- r0 7448 GOTO_OPCODE(ip) @ jump to next instruction 7449 7450 7451/* ------------------------------ */ 7452 .balign 64 7453.L_OP_IPUT_QUICK: /* 0xf5 */ 7454/* File: armv6t2/OP_IPUT_QUICK.S */ 7455 /* For: iput-quick, iput-object-quick */ 7456 /* op vA, vB, offset@CCCC */ 7457 mov r2, rINST, lsr #12 @ r2<- B 7458 FETCH(r1, 1) @ r1<- field byte offset 7459 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7460 ubfx r2, rINST, #8, #4 @ r2<- A 7461 cmp r3, #0 @ check object for null 7462 beq common_errNullObject @ object was null 7463 GET_VREG(r0, r2) @ r0<- fp[A] 7464 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7465 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7466 GET_INST_OPCODE(ip) @ extract opcode from rINST 7467 GOTO_OPCODE(ip) @ jump to next instruction 7468 7469/* ------------------------------ */ 7470 .balign 64 7471.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7472/* File: armv6t2/OP_IPUT_WIDE_QUICK.S */ 7473 /* iput-wide-quick vA, vB, offset@CCCC */ 7474 mov r1, rINST, lsr #12 @ r1<- B 7475 ubfx r0, rINST, #8, #4 @ r0<- A 7476 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7477 add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7478 cmp r2, #0 @ check object for null 7479 ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7480 beq common_errNullObject @ object was null 7481 FETCH(r3, 1) @ r3<- field byte offset 7482 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7483 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7484 GET_INST_OPCODE(ip) @ extract opcode from rINST 7485 GOTO_OPCODE(ip) @ jump to next instruction 7486 7487/* ------------------------------ */ 7488 .balign 64 7489.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7490/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7491 /* For: iput-object-quick */ 7492 /* op vA, vB, offset@CCCC */ 7493 mov r2, rINST, lsr #12 @ r2<- B 7494 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7495 FETCH(r1, 1) @ r1<- field byte offset 7496 cmp r3, #0 @ check object for null 7497 mov r2, rINST, lsr #8 @ r2<- A(+) 7498 beq common_errNullObject @ object was null 7499 and r2, r2, #15 7500 GET_VREG(r0, r2) @ r0<- fp[A] 7501 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 7502 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7503 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7504 cmp r0, #0 7505 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head 7506 GET_INST_OPCODE(ip) @ extract opcode from rINST 7507 GOTO_OPCODE(ip) @ jump to next instruction 7508 7509/* ------------------------------ */ 7510 .balign 64 7511.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7512/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7513 /* 7514 * Handle an optimized virtual method call. 7515 * 7516 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7517 */ 7518 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7519 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7520 FETCH(r3, 2) @ r3<- FEDC or CCCC 7521 FETCH(r1, 1) @ r1<- BBBB 7522 .if (!0) 7523 and r3, r3, #15 @ r3<- C (or stays CCCC) 7524 .endif 7525 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7526 cmp r2, #0 @ is "this" null? 7527 beq common_errNullObject @ null "this", throw exception 7528 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7529 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7530 EXPORT_PC() @ invoke must export 7531 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7532 bl common_invokeMethodNoRange @ continue on 7533 7534/* ------------------------------ */ 7535 .balign 64 7536.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7537/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7538/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7539 /* 7540 * Handle an optimized virtual method call. 7541 * 7542 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7543 */ 7544 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7545 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7546 FETCH(r3, 2) @ r3<- FEDC or CCCC 7547 FETCH(r1, 1) @ r1<- BBBB 7548 .if (!1) 7549 and r3, r3, #15 @ r3<- C (or stays CCCC) 7550 .endif 7551 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7552 cmp r2, #0 @ is "this" null? 7553 beq common_errNullObject @ null "this", throw exception 7554 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7555 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7556 EXPORT_PC() @ invoke must export 7557 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7558 bl common_invokeMethodRange @ continue on 7559 7560 7561/* ------------------------------ */ 7562 .balign 64 7563.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7564/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7565 /* 7566 * Handle an optimized "super" method call. 7567 * 7568 * for: [opt] invoke-super-quick, invoke-super-quick/range 7569 */ 7570 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7571 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7572 FETCH(r10, 2) @ r10<- GFED or CCCC 7573 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7574 .if (!0) 7575 and r10, r10, #15 @ r10<- D (or stays CCCC) 7576 .endif 7577 FETCH(r1, 1) @ r1<- BBBB 7578 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7579 EXPORT_PC() @ must export for invoke 7580 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7581 GET_VREG(r3, r10) @ r3<- "this" 7582 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7583 cmp r3, #0 @ null "this" ref? 7584 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7585 beq common_errNullObject @ "this" is null, throw exception 7586 bl common_invokeMethodNoRange @ continue on 7587 7588/* ------------------------------ */ 7589 .balign 64 7590.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7591/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7592/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7593 /* 7594 * Handle an optimized "super" method call. 7595 * 7596 * for: [opt] invoke-super-quick, invoke-super-quick/range 7597 */ 7598 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7599 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7600 FETCH(r10, 2) @ r10<- GFED or CCCC 7601 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7602 .if (!1) 7603 and r10, r10, #15 @ r10<- D (or stays CCCC) 7604 .endif 7605 FETCH(r1, 1) @ r1<- BBBB 7606 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7607 EXPORT_PC() @ must export for invoke 7608 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7609 GET_VREG(r3, r10) @ r3<- "this" 7610 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7611 cmp r3, #0 @ null "this" ref? 7612 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7613 beq common_errNullObject @ "this" is null, throw exception 7614 bl common_invokeMethodRange @ continue on 7615 7616 7617/* ------------------------------ */ 7618 .balign 64 7619.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7620/* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7621/* File: armv5te/OP_IPUT_OBJECT.S */ 7622 /* 7623 * 32-bit instance field put. 7624 * 7625 * for: iput-object, iput-object-volatile 7626 */ 7627 /* op vA, vB, field@CCCC */ 7628 mov r0, rINST, lsr #12 @ r0<- B 7629 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7630 FETCH(r1, 1) @ r1<- field ref CCCC 7631 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7632 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7633 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7634 cmp r0, #0 @ is resolved entry null? 7635 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 76368: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7637 EXPORT_PC() @ resolve() could throw 7638 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7639 bl dvmResolveInstField @ r0<- resolved InstField ptr 7640 cmp r0, #0 @ success? 7641 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 7642 b common_exceptionThrown 7643 7644 7645/* ------------------------------ */ 7646 .balign 64 7647.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 7648/* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 7649/* File: armv5te/OP_SGET.S */ 7650 /* 7651 * General 32-bit SGET handler. 7652 * 7653 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7654 */ 7655 /* op vAA, field@BBBB */ 7656 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7657 FETCH(r1, 1) @ r1<- field ref BBBB 7658 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7659 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7660 cmp r0, #0 @ is resolved entry null? 7661 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 7662.LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 7663 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7664 SMP_DMB @ acquiring load 7665 mov r2, rINST, lsr #8 @ r2<- AA 7666 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7667 SET_VREG(r1, r2) @ fp[AA]<- r1 7668 GET_INST_OPCODE(ip) @ extract opcode from rINST 7669 GOTO_OPCODE(ip) @ jump to next instruction 7670 7671 7672/* ------------------------------ */ 7673 .balign 64 7674.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 7675/* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 7676/* File: armv5te/OP_SPUT_OBJECT.S */ 7677 /* 7678 * 32-bit SPUT handler for objects 7679 * 7680 * for: sput-object, sput-object-volatile 7681 */ 7682 /* op vAA, field@BBBB */ 7683 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7684 FETCH(r1, 1) @ r1<- field ref BBBB 7685 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7686 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7687 cmp r0, #0 @ is resolved entry null? 7688 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue 7689 ldr r9, [rSELF, #offThread_method] @ r9<- current method 7690 EXPORT_PC() @ resolve() could throw, so export now 7691 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 7692 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 7693 cmp r0, #0 @ success? 7694 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish 7695 b common_exceptionThrown @ no, handle exception 7696 7697 7698 7699/* ------------------------------ */ 7700 .balign 64 7701.L_OP_DISPATCH_FF: /* 0xff */ 7702/* File: armv5te/OP_DISPATCH_FF.S */ 7703 mov ip, rINST, lsr #8 @ ip<- extended opcode 7704 add ip, ip, #256 @ add offset for extended opcodes 7705 GOTO_OPCODE(ip) @ go to proper extended handler 7706 7707 7708/* ------------------------------ */ 7709 .balign 64 7710.L_OP_CONST_CLASS_JUMBO: /* 0x100 */ 7711/* File: armv5te/OP_CONST_CLASS_JUMBO.S */ 7712 /* const-class/jumbo vBBBB, Class@AAAAAAAA */ 7713 FETCH(r0, 1) @ r0<- aaaa (lo) 7714 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex 7715 FETCH(r1, 2) @ r1<- AAAA (hi) 7716 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 7717 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7718 FETCH(r9, 3) @ r9<- BBBB 7719 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa] 7720 cmp r0, #0 @ not yet resolved? 7721 beq .LOP_CONST_CLASS_JUMBO_resolve 7722 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 7723 GET_INST_OPCODE(ip) @ extract opcode from rINST 7724 SET_VREG(r0, r9) @ vBBBB<- r0 7725 GOTO_OPCODE(ip) @ jump to next instruction 7726 7727/* ------------------------------ */ 7728 .balign 64 7729.L_OP_CHECK_CAST_JUMBO: /* 0x101 */ 7730/* File: armv5te/OP_CHECK_CAST_JUMBO.S */ 7731 /* 7732 * Check to see if a cast from one class to another is allowed. 7733 */ 7734 /* check-cast/jumbo vBBBB, class@AAAAAAAA */ 7735 FETCH(r0, 1) @ r0<- aaaa (lo) 7736 FETCH(r2, 2) @ r2<- AAAA (hi) 7737 FETCH(r3, 3) @ r3<- BBBB 7738 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa 7739 GET_VREG(r9, r3) @ r9<- object 7740 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 7741 cmp r9, #0 @ is object null? 7742 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 7743 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds 7744 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 7745 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7746 cmp r1, #0 @ have we resolved this before? 7747 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now 7748.LOP_CHECK_CAST_JUMBO_resolved: 7749 cmp r0, r1 @ same class (trivial success)? 7750 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check 7751 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up 7752 7753/* ------------------------------ */ 7754 .balign 64 7755.L_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 7756/* File: armv5te/OP_INSTANCE_OF_JUMBO.S */ 7757 /* 7758 * Check to see if an object reference is an instance of a class. 7759 * 7760 * Most common situation is a non-null object, being compared against 7761 * an already-resolved class. 7762 * 7763 * TODO: convert most of this into a common subroutine, shared with 7764 * OP_INSTANCE_OF.S. 7765 */ 7766 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7767 FETCH(r3, 4) @ r3<- vCCCC 7768 FETCH(r9, 3) @ r9<- vBBBB 7769 GET_VREG(r0, r3) @ r0<- vCCCC (object) 7770 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 7771 cmp r0, #0 @ is object null? 7772 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0 7773 FETCH(r1, 1) @ r1<- aaaa (lo) 7774 FETCH(r3, 2) @ r3<- AAAA (hi) 7775 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 7776 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa 7777 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 7778 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7779 cmp r1, #0 @ have we resolved this before? 7780 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now 7781 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue 7782 7783/* ------------------------------ */ 7784 .balign 64 7785.L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 7786/* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */ 7787 /* 7788 * Create a new instance of a class. 7789 */ 7790 /* new-instance/jumbo vBBBB, class@AAAAAAAA */ 7791 FETCH(r0, 1) @ r0<- aaaa (lo) 7792 FETCH(r1, 2) @ r1<- AAAA (hi) 7793 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7794 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7795 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7796 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7797 EXPORT_PC() @ req'd for init, resolve, alloc 7798 cmp r0, #0 @ already resolved? 7799 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now 7800.LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class 7801 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 7802 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 7803 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now 7804.LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class 7805 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 7806 bl dvmAllocObject @ r0<- new object 7807 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue 7808 7809/* ------------------------------ */ 7810 .balign 64 7811.L_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 7812/* File: armv5te/OP_NEW_ARRAY_JUMBO.S */ 7813 /* 7814 * Allocate an array of objects, specified with the array class 7815 * and a count. 7816 * 7817 * The verifier guarantees that this is an array class, so we don't 7818 * check for it here. 7819 */ 7820 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7821 FETCH(r2, 1) @ r2<- aaaa (lo) 7822 FETCH(r3, 2) @ r3<- AAAA (hi) 7823 FETCH(r0, 4) @ r0<- vCCCC 7824 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa 7825 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7826 GET_VREG(r1, r0) @ r1<- vCCCC (array length) 7827 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7828 cmp r1, #0 @ check length 7829 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 7830 bmi common_errNegativeArraySize @ negative length, bail - len in r1 7831 cmp r0, #0 @ already resolved? 7832 EXPORT_PC() @ req'd for resolve, alloc 7833 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue 7834 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now 7835 7836/* ------------------------------ */ 7837 .balign 64 7838.L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 7839/* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */ 7840 /* 7841 * Create a new array with elements filled from registers. 7842 * 7843 * TODO: convert most of this into a common subroutine, shared with 7844 * OP_FILLED_NEW_ARRAY.S. 7845 */ 7846 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */ 7847 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7848 FETCH(r0, 1) @ r0<- aaaa (lo) 7849 FETCH(r1, 2) @ r1<- AAAA (hi) 7850 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7851 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7852 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7853 EXPORT_PC() @ need for resolve and alloc 7854 cmp r0, #0 @ already resolved? 7855 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on 78568: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 7857 mov r2, #0 @ r2<- false 7858 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7859 bl dvmResolveClass @ r0<- call(clazz, ref) 7860 cmp r0, #0 @ got null? 7861 beq common_exceptionThrown @ yes, handle exception 7862 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue 7863 7864/* ------------------------------ */ 7865 .balign 64 7866.L_OP_IGET_JUMBO: /* 0x106 */ 7867/* File: armv5te/OP_IGET_JUMBO.S */ 7868 /* 7869 * Jumbo 32-bit instance field get. 7870 * 7871 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7872 * iget-char/jumbo, iget-short/jumbo 7873 */ 7874 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7875 FETCH(r1, 1) @ r1<- aaaa (lo) 7876 FETCH(r2, 2) @ r2<- AAAA (hi) 7877 FETCH(r0, 4) @ r0<- CCCC 7878 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7879 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7880 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7881 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7882 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7883 cmp r0, #0 @ is resolved entry null? 7884 bne .LOP_IGET_JUMBO_finish @ no, already resolved 78858: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7886 EXPORT_PC() @ resolve() could throw 7887 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7888 bl dvmResolveInstField @ r0<- resolved InstField ptr 7889 b .LOP_IGET_JUMBO_resolved @ resolved, continue 7890 7891/* ------------------------------ */ 7892 .balign 64 7893.L_OP_IGET_WIDE_JUMBO: /* 0x107 */ 7894/* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 7895 /* 7896 * Jumbo 64-bit instance field get. 7897 */ 7898 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 7899 FETCH(r1, 1) @ r1<- aaaa (lo) 7900 FETCH(r2, 2) @ r2<- AAAA (hi) 7901 FETCH(r0, 4) @ r0<- CCCC 7902 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7903 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7904 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7905 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7906 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7907 cmp r0, #0 @ is resolved entry null? 7908 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved 79098: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7910 EXPORT_PC() @ resolve() could throw 7911 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7912 bl dvmResolveInstField @ r0<- resolved InstField ptr 7913 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue 7914 7915/* ------------------------------ */ 7916 .balign 64 7917.L_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 7918/* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 7919/* File: armv5te/OP_IGET_JUMBO.S */ 7920 /* 7921 * Jumbo 32-bit instance field get. 7922 * 7923 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7924 * iget-char/jumbo, iget-short/jumbo 7925 */ 7926 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7927 FETCH(r1, 1) @ r1<- aaaa (lo) 7928 FETCH(r2, 2) @ r2<- AAAA (hi) 7929 FETCH(r0, 4) @ r0<- CCCC 7930 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7931 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7932 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7933 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7934 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7935 cmp r0, #0 @ is resolved entry null? 7936 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved 79378: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7938 EXPORT_PC() @ resolve() could throw 7939 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7940 bl dvmResolveInstField @ r0<- resolved InstField ptr 7941 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue 7942 7943 7944/* ------------------------------ */ 7945 .balign 64 7946.L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 7947/* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */ 7948@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" } 7949/* File: armv5te/OP_IGET_JUMBO.S */ 7950 /* 7951 * Jumbo 32-bit instance field get. 7952 * 7953 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7954 * iget-char/jumbo, iget-short/jumbo 7955 */ 7956 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7957 FETCH(r1, 1) @ r1<- aaaa (lo) 7958 FETCH(r2, 2) @ r2<- AAAA (hi) 7959 FETCH(r0, 4) @ r0<- CCCC 7960 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7961 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7962 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7963 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7964 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7965 cmp r0, #0 @ is resolved entry null? 7966 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved 79678: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7968 EXPORT_PC() @ resolve() could throw 7969 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7970 bl dvmResolveInstField @ r0<- resolved InstField ptr 7971 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue 7972 7973 7974/* ------------------------------ */ 7975 .balign 64 7976.L_OP_IGET_BYTE_JUMBO: /* 0x10a */ 7977/* File: armv5te/OP_IGET_BYTE_JUMBO.S */ 7978@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" } 7979/* File: armv5te/OP_IGET_JUMBO.S */ 7980 /* 7981 * Jumbo 32-bit instance field get. 7982 * 7983 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7984 * iget-char/jumbo, iget-short/jumbo 7985 */ 7986 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7987 FETCH(r1, 1) @ r1<- aaaa (lo) 7988 FETCH(r2, 2) @ r2<- AAAA (hi) 7989 FETCH(r0, 4) @ r0<- CCCC 7990 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7991 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7992 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7993 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7994 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7995 cmp r0, #0 @ is resolved entry null? 7996 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved 79978: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7998 EXPORT_PC() @ resolve() could throw 7999 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8000 bl dvmResolveInstField @ r0<- resolved InstField ptr 8001 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue 8002 8003 8004/* ------------------------------ */ 8005 .balign 64 8006.L_OP_IGET_CHAR_JUMBO: /* 0x10b */ 8007/* File: armv5te/OP_IGET_CHAR_JUMBO.S */ 8008@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" } 8009/* File: armv5te/OP_IGET_JUMBO.S */ 8010 /* 8011 * Jumbo 32-bit instance field get. 8012 * 8013 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8014 * iget-char/jumbo, iget-short/jumbo 8015 */ 8016 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8017 FETCH(r1, 1) @ r1<- aaaa (lo) 8018 FETCH(r2, 2) @ r2<- AAAA (hi) 8019 FETCH(r0, 4) @ r0<- CCCC 8020 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8021 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8022 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8023 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8024 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8025 cmp r0, #0 @ is resolved entry null? 8026 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved 80278: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8028 EXPORT_PC() @ resolve() could throw 8029 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8030 bl dvmResolveInstField @ r0<- resolved InstField ptr 8031 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue 8032 8033 8034/* ------------------------------ */ 8035 .balign 64 8036.L_OP_IGET_SHORT_JUMBO: /* 0x10c */ 8037/* File: armv5te/OP_IGET_SHORT_JUMBO.S */ 8038@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" } 8039/* File: armv5te/OP_IGET_JUMBO.S */ 8040 /* 8041 * Jumbo 32-bit instance field get. 8042 * 8043 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8044 * iget-char/jumbo, iget-short/jumbo 8045 */ 8046 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8047 FETCH(r1, 1) @ r1<- aaaa (lo) 8048 FETCH(r2, 2) @ r2<- AAAA (hi) 8049 FETCH(r0, 4) @ r0<- CCCC 8050 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8051 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8052 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8053 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8054 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8055 cmp r0, #0 @ is resolved entry null? 8056 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved 80578: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8058 EXPORT_PC() @ resolve() could throw 8059 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8060 bl dvmResolveInstField @ r0<- resolved InstField ptr 8061 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue 8062 8063 8064/* ------------------------------ */ 8065 .balign 64 8066.L_OP_IPUT_JUMBO: /* 0x10d */ 8067/* File: armv5te/OP_IPUT_JUMBO.S */ 8068 /* 8069 * Jumbo 32-bit instance field put. 8070 * 8071 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8072 * iput-short/jumbo 8073 */ 8074 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8075 FETCH(r1, 1) @ r1<- aaaa (lo) 8076 FETCH(r2, 2) @ r2<- AAAA (hi) 8077 FETCH(r0, 4) @ r0<- CCCC 8078 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8079 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8080 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8081 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8082 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8083 cmp r0, #0 @ is resolved entry null? 8084 bne .LOP_IPUT_JUMBO_finish @ no, already resolved 80858: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8086 EXPORT_PC() @ resolve() could throw 8087 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8088 bl dvmResolveInstField @ r0<- resolved InstField ptr 8089 b .LOP_IPUT_JUMBO_resolved @ resolved, continue 8090 8091/* ------------------------------ */ 8092 .balign 64 8093.L_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 8094/* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 8095 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8096 FETCH(r1, 1) @ r1<- aaaa (lo) 8097 FETCH(r2, 2) @ r2<- AAAA (hi) 8098 FETCH(r0, 4) @ r0<- CCCC 8099 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8100 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8101 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 8102 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 8103 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8104 cmp r0, #0 @ is resolved entry null? 8105 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved 81068: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8107 EXPORT_PC() @ resolve() could throw 8108 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8109 bl dvmResolveInstField @ r0<- resolved InstField ptr 8110 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue 8111 8112/* ------------------------------ */ 8113 .balign 64 8114.L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 8115/* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 8116 /* 8117 * Jumbo 32-bit instance field put. 8118 */ 8119 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8120 FETCH(r1, 1) @ r1<- aaaa (lo) 8121 FETCH(r2, 2) @ r2<- AAAA (hi) 8122 FETCH(r0, 4) @ r0<- CCCC 8123 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8124 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8125 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8126 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8127 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8128 cmp r0, #0 @ is resolved entry null? 8129 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved 81308: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8131 EXPORT_PC() @ resolve() could throw 8132 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8133 bl dvmResolveInstField @ r0<- resolved InstField ptr 8134 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue 8135 8136/* ------------------------------ */ 8137 .balign 64 8138.L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 8139/* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */ 8140@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" } 8141/* File: armv5te/OP_IPUT_JUMBO.S */ 8142 /* 8143 * Jumbo 32-bit instance field put. 8144 * 8145 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8146 * iput-short/jumbo 8147 */ 8148 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8149 FETCH(r1, 1) @ r1<- aaaa (lo) 8150 FETCH(r2, 2) @ r2<- AAAA (hi) 8151 FETCH(r0, 4) @ r0<- CCCC 8152 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8153 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8154 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8155 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8156 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8157 cmp r0, #0 @ is resolved entry null? 8158 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved 81598: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8160 EXPORT_PC() @ resolve() could throw 8161 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8162 bl dvmResolveInstField @ r0<- resolved InstField ptr 8163 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue 8164 8165 8166/* ------------------------------ */ 8167 .balign 64 8168.L_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 8169/* File: armv5te/OP_IPUT_BYTE_JUMBO.S */ 8170@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" } 8171/* File: armv5te/OP_IPUT_JUMBO.S */ 8172 /* 8173 * Jumbo 32-bit instance field put. 8174 * 8175 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8176 * iput-short/jumbo 8177 */ 8178 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8179 FETCH(r1, 1) @ r1<- aaaa (lo) 8180 FETCH(r2, 2) @ r2<- AAAA (hi) 8181 FETCH(r0, 4) @ r0<- CCCC 8182 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8183 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8184 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8185 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8186 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8187 cmp r0, #0 @ is resolved entry null? 8188 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved 81898: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8190 EXPORT_PC() @ resolve() could throw 8191 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8192 bl dvmResolveInstField @ r0<- resolved InstField ptr 8193 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue 8194 8195 8196/* ------------------------------ */ 8197 .balign 64 8198.L_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 8199/* File: armv5te/OP_IPUT_CHAR_JUMBO.S */ 8200@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" } 8201/* File: armv5te/OP_IPUT_JUMBO.S */ 8202 /* 8203 * Jumbo 32-bit instance field put. 8204 * 8205 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8206 * iput-short/jumbo 8207 */ 8208 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8209 FETCH(r1, 1) @ r1<- aaaa (lo) 8210 FETCH(r2, 2) @ r2<- AAAA (hi) 8211 FETCH(r0, 4) @ r0<- CCCC 8212 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8213 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8214 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8215 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8216 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8217 cmp r0, #0 @ is resolved entry null? 8218 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved 82198: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8220 EXPORT_PC() @ resolve() could throw 8221 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8222 bl dvmResolveInstField @ r0<- resolved InstField ptr 8223 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue 8224 8225 8226/* ------------------------------ */ 8227 .balign 64 8228.L_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 8229/* File: armv5te/OP_IPUT_SHORT_JUMBO.S */ 8230@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" } 8231/* File: armv5te/OP_IPUT_JUMBO.S */ 8232 /* 8233 * Jumbo 32-bit instance field put. 8234 * 8235 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8236 * iput-short/jumbo 8237 */ 8238 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8239 FETCH(r1, 1) @ r1<- aaaa (lo) 8240 FETCH(r2, 2) @ r2<- AAAA (hi) 8241 FETCH(r0, 4) @ r0<- CCCC 8242 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8243 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8244 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8245 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8246 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8247 cmp r0, #0 @ is resolved entry null? 8248 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved 82498: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8250 EXPORT_PC() @ resolve() could throw 8251 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8252 bl dvmResolveInstField @ r0<- resolved InstField ptr 8253 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue 8254 8255 8256/* ------------------------------ */ 8257 .balign 64 8258.L_OP_SGET_JUMBO: /* 0x114 */ 8259/* File: armv5te/OP_SGET_JUMBO.S */ 8260 /* 8261 * Jumbo 32-bit SGET handler. 8262 * 8263 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8264 * sget-char/jumbo, sget-short/jumbo 8265 */ 8266 /* exop vBBBB, field@AAAAAAAA */ 8267 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8268 FETCH(r0, 1) @ r0<- aaaa (lo) 8269 FETCH(r1, 2) @ r1<- AAAA (hi) 8270 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8271 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8272 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8273 cmp r0, #0 @ is resolved entry null? 8274 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve 8275.LOP_SGET_JUMBO_finish: @ field ptr in r0 8276 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8277 @ no-op @ acquiring load 8278 FETCH(r2, 3) @ r2<- BBBB 8279 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8280 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8281 GET_INST_OPCODE(ip) @ extract opcode from rINST 8282 GOTO_OPCODE(ip) @ jump to next instruction 8283 8284/* ------------------------------ */ 8285 .balign 64 8286.L_OP_SGET_WIDE_JUMBO: /* 0x115 */ 8287/* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 8288 /* 8289 * Jumbo 64-bit SGET handler. 8290 */ 8291 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 8292 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8293 FETCH(r0, 1) @ r0<- aaaa (lo) 8294 FETCH(r1, 2) @ r1<- AAAA (hi) 8295 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8296 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8297 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8298 cmp r0, #0 @ is resolved entry null? 8299 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve 8300.LOP_SGET_WIDE_JUMBO_finish: 8301 FETCH(r9, 3) @ r9<- BBBB 8302 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 8303 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8304 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8305 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 8306 GET_INST_OPCODE(ip) @ extract opcode from rINST 8307 GOTO_OPCODE(ip) @ jump to next instruction 8308 8309/* ------------------------------ */ 8310 .balign 64 8311.L_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 8312/* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 8313/* File: armv5te/OP_SGET_JUMBO.S */ 8314 /* 8315 * Jumbo 32-bit SGET handler. 8316 * 8317 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8318 * sget-char/jumbo, sget-short/jumbo 8319 */ 8320 /* exop vBBBB, field@AAAAAAAA */ 8321 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8322 FETCH(r0, 1) @ r0<- aaaa (lo) 8323 FETCH(r1, 2) @ r1<- AAAA (hi) 8324 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8325 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8326 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8327 cmp r0, #0 @ is resolved entry null? 8328 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve 8329.LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0 8330 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8331 @ no-op @ acquiring load 8332 FETCH(r2, 3) @ r2<- BBBB 8333 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8334 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8335 GET_INST_OPCODE(ip) @ extract opcode from rINST 8336 GOTO_OPCODE(ip) @ jump to next instruction 8337 8338 8339/* ------------------------------ */ 8340 .balign 64 8341.L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 8342/* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */ 8343/* File: armv5te/OP_SGET_JUMBO.S */ 8344 /* 8345 * Jumbo 32-bit SGET handler. 8346 * 8347 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8348 * sget-char/jumbo, sget-short/jumbo 8349 */ 8350 /* exop vBBBB, field@AAAAAAAA */ 8351 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8352 FETCH(r0, 1) @ r0<- aaaa (lo) 8353 FETCH(r1, 2) @ r1<- AAAA (hi) 8354 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8355 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8356 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8357 cmp r0, #0 @ is resolved entry null? 8358 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve 8359.LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0 8360 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8361 @ no-op @ acquiring load 8362 FETCH(r2, 3) @ r2<- BBBB 8363 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8364 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8365 GET_INST_OPCODE(ip) @ extract opcode from rINST 8366 GOTO_OPCODE(ip) @ jump to next instruction 8367 8368 8369/* ------------------------------ */ 8370 .balign 64 8371.L_OP_SGET_BYTE_JUMBO: /* 0x118 */ 8372/* File: armv5te/OP_SGET_BYTE_JUMBO.S */ 8373/* File: armv5te/OP_SGET_JUMBO.S */ 8374 /* 8375 * Jumbo 32-bit SGET handler. 8376 * 8377 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8378 * sget-char/jumbo, sget-short/jumbo 8379 */ 8380 /* exop vBBBB, field@AAAAAAAA */ 8381 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8382 FETCH(r0, 1) @ r0<- aaaa (lo) 8383 FETCH(r1, 2) @ r1<- AAAA (hi) 8384 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8385 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8386 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8387 cmp r0, #0 @ is resolved entry null? 8388 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve 8389.LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0 8390 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8391 @ no-op @ acquiring load 8392 FETCH(r2, 3) @ r2<- BBBB 8393 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8394 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8395 GET_INST_OPCODE(ip) @ extract opcode from rINST 8396 GOTO_OPCODE(ip) @ jump to next instruction 8397 8398 8399/* ------------------------------ */ 8400 .balign 64 8401.L_OP_SGET_CHAR_JUMBO: /* 0x119 */ 8402/* File: armv5te/OP_SGET_CHAR_JUMBO.S */ 8403/* File: armv5te/OP_SGET_JUMBO.S */ 8404 /* 8405 * Jumbo 32-bit SGET handler. 8406 * 8407 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8408 * sget-char/jumbo, sget-short/jumbo 8409 */ 8410 /* exop vBBBB, field@AAAAAAAA */ 8411 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8412 FETCH(r0, 1) @ r0<- aaaa (lo) 8413 FETCH(r1, 2) @ r1<- AAAA (hi) 8414 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8415 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8416 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8417 cmp r0, #0 @ is resolved entry null? 8418 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve 8419.LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0 8420 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8421 @ no-op @ acquiring load 8422 FETCH(r2, 3) @ r2<- BBBB 8423 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8424 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8425 GET_INST_OPCODE(ip) @ extract opcode from rINST 8426 GOTO_OPCODE(ip) @ jump to next instruction 8427 8428 8429/* ------------------------------ */ 8430 .balign 64 8431.L_OP_SGET_SHORT_JUMBO: /* 0x11a */ 8432/* File: armv5te/OP_SGET_SHORT_JUMBO.S */ 8433/* File: armv5te/OP_SGET_JUMBO.S */ 8434 /* 8435 * Jumbo 32-bit SGET handler. 8436 * 8437 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8438 * sget-char/jumbo, sget-short/jumbo 8439 */ 8440 /* exop vBBBB, field@AAAAAAAA */ 8441 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8442 FETCH(r0, 1) @ r0<- aaaa (lo) 8443 FETCH(r1, 2) @ r1<- AAAA (hi) 8444 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8445 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8446 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8447 cmp r0, #0 @ is resolved entry null? 8448 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve 8449.LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0 8450 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8451 @ no-op @ acquiring load 8452 FETCH(r2, 3) @ r2<- BBBB 8453 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8454 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8455 GET_INST_OPCODE(ip) @ extract opcode from rINST 8456 GOTO_OPCODE(ip) @ jump to next instruction 8457 8458 8459/* ------------------------------ */ 8460 .balign 64 8461.L_OP_SPUT_JUMBO: /* 0x11b */ 8462/* File: armv5te/OP_SPUT_JUMBO.S */ 8463 /* 8464 * Jumbo 32-bit SPUT handler. 8465 * 8466 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8467 * sput-short/jumbo 8468 */ 8469 /* exop vBBBB, field@AAAAAAAA */ 8470 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8471 FETCH(r0, 1) @ r0<- aaaa (lo) 8472 FETCH(r1, 2) @ r1<- AAAA (hi) 8473 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8474 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8475 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8476 cmp r0, #0 @ is resolved entry null? 8477 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve 8478.LOP_SPUT_JUMBO_finish: @ field ptr in r0 8479 FETCH(r2, 3) @ r2<- BBBB 8480 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8481 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8482 GET_INST_OPCODE(ip) @ extract opcode from rINST 8483 @ no-op @ releasing store 8484 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8485 GOTO_OPCODE(ip) @ jump to next instruction 8486 8487/* ------------------------------ */ 8488 .balign 64 8489.L_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 8490/* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 8491 /* 8492 * Jumbo 64-bit SPUT handler. 8493 */ 8494 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 8495 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 8496 FETCH(r1, 1) @ r1<- aaaa (lo) 8497 FETCH(r2, 2) @ r2<- AAAA (hi) 8498 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 8499 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8500 FETCH(r9, 3) @ r9<- BBBB 8501 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 8502 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8503 cmp r2, #0 @ is resolved entry null? 8504 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve 8505.LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9 8506 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8507 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 8508 GET_INST_OPCODE(r10) @ extract opcode from rINST 8509 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 8510 GOTO_OPCODE(r10) @ jump to next instruction 8511 8512/* ------------------------------ */ 8513 .balign 64 8514.L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 8515/* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 8516 /* 8517 * Jumbo 32-bit SPUT handler for objects 8518 */ 8519 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 8520 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8521 FETCH(r0, 1) @ r0<- aaaa (lo) 8522 FETCH(r1, 2) @ r1<- AAAA (hi) 8523 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8524 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8525 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8526 cmp r0, #0 @ is resolved entry null? 8527 bne .LOP_SPUT_OBJECT_JUMBO_finish @ no, continue 8528 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8529 EXPORT_PC() @ resolve() could throw, so export now 8530 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 8531 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8532 cmp r0, #0 @ success? 8533 bne .LOP_SPUT_OBJECT_JUMBO_finish @ yes, finish 8534 b common_exceptionThrown @ no, handle exception 8535 8536/* ------------------------------ */ 8537 .balign 64 8538.L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 8539/* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */ 8540/* File: armv5te/OP_SPUT_JUMBO.S */ 8541 /* 8542 * Jumbo 32-bit SPUT handler. 8543 * 8544 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8545 * sput-short/jumbo 8546 */ 8547 /* exop vBBBB, field@AAAAAAAA */ 8548 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8549 FETCH(r0, 1) @ r0<- aaaa (lo) 8550 FETCH(r1, 2) @ r1<- AAAA (hi) 8551 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8552 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8553 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8554 cmp r0, #0 @ is resolved entry null? 8555 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve 8556.LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0 8557 FETCH(r2, 3) @ r2<- BBBB 8558 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8559 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8560 GET_INST_OPCODE(ip) @ extract opcode from rINST 8561 @ no-op @ releasing store 8562 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8563 GOTO_OPCODE(ip) @ jump to next instruction 8564 8565 8566/* ------------------------------ */ 8567 .balign 64 8568.L_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 8569/* File: armv5te/OP_SPUT_BYTE_JUMBO.S */ 8570/* File: armv5te/OP_SPUT_JUMBO.S */ 8571 /* 8572 * Jumbo 32-bit SPUT handler. 8573 * 8574 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8575 * sput-short/jumbo 8576 */ 8577 /* exop vBBBB, field@AAAAAAAA */ 8578 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8579 FETCH(r0, 1) @ r0<- aaaa (lo) 8580 FETCH(r1, 2) @ r1<- AAAA (hi) 8581 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8582 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8583 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8584 cmp r0, #0 @ is resolved entry null? 8585 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve 8586.LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0 8587 FETCH(r2, 3) @ r2<- BBBB 8588 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8589 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8590 GET_INST_OPCODE(ip) @ extract opcode from rINST 8591 @ no-op @ releasing store 8592 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8593 GOTO_OPCODE(ip) @ jump to next instruction 8594 8595 8596/* ------------------------------ */ 8597 .balign 64 8598.L_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 8599/* File: armv5te/OP_SPUT_CHAR_JUMBO.S */ 8600/* File: armv5te/OP_SPUT_JUMBO.S */ 8601 /* 8602 * Jumbo 32-bit SPUT handler. 8603 * 8604 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8605 * sput-short/jumbo 8606 */ 8607 /* exop vBBBB, field@AAAAAAAA */ 8608 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8609 FETCH(r0, 1) @ r0<- aaaa (lo) 8610 FETCH(r1, 2) @ r1<- AAAA (hi) 8611 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8612 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8613 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8614 cmp r0, #0 @ is resolved entry null? 8615 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve 8616.LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0 8617 FETCH(r2, 3) @ r2<- BBBB 8618 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8619 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8620 GET_INST_OPCODE(ip) @ extract opcode from rINST 8621 @ no-op @ releasing store 8622 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8623 GOTO_OPCODE(ip) @ jump to next instruction 8624 8625 8626/* ------------------------------ */ 8627 .balign 64 8628.L_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 8629/* File: armv5te/OP_SPUT_SHORT_JUMBO.S */ 8630/* File: armv5te/OP_SPUT_JUMBO.S */ 8631 /* 8632 * Jumbo 32-bit SPUT handler. 8633 * 8634 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8635 * sput-short/jumbo 8636 */ 8637 /* exop vBBBB, field@AAAAAAAA */ 8638 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8639 FETCH(r0, 1) @ r0<- aaaa (lo) 8640 FETCH(r1, 2) @ r1<- AAAA (hi) 8641 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8642 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8643 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8644 cmp r0, #0 @ is resolved entry null? 8645 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve 8646.LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0 8647 FETCH(r2, 3) @ r2<- BBBB 8648 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8649 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8650 GET_INST_OPCODE(ip) @ extract opcode from rINST 8651 @ no-op @ releasing store 8652 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8653 GOTO_OPCODE(ip) @ jump to next instruction 8654 8655 8656/* ------------------------------ */ 8657 .balign 64 8658.L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 8659/* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */ 8660 /* 8661 * Handle a virtual method call. 8662 */ 8663 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8664 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8665 FETCH(r0, 1) @ r1<- aaaa (lo) 8666 FETCH(r1, 2) @ r1<- AAAA (hi) 8667 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8668 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8669 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8670 cmp r0, #0 @ already resolved? 8671 EXPORT_PC() @ must export for invoke 8672 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on 8673 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8674 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8675 mov r2, #METHOD_VIRTUAL @ resolver method type 8676 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8677 cmp r0, #0 @ got null? 8678 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue 8679 b common_exceptionThrown @ yes, handle exception 8680 8681/* ------------------------------ */ 8682 .balign 64 8683.L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 8684/* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */ 8685 /* 8686 * Handle a "super" method call. 8687 */ 8688 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8689 FETCH(r10, 4) @ r10<- CCCC 8690 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8691 FETCH(r0, 1) @ r1<- aaaa (lo) 8692 FETCH(r1, 2) @ r1<- AAAA (hi) 8693 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8694 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8695 GET_VREG(r2, r10) @ r2<- "this" ptr 8696 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8697 cmp r2, #0 @ null "this"? 8698 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8699 beq common_errNullObject @ null "this", throw exception 8700 cmp r0, #0 @ already resolved? 8701 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 8702 EXPORT_PC() @ must export for invoke 8703 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on 8704 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now 8705 8706/* ------------------------------ */ 8707 .balign 64 8708.L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 8709/* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */ 8710 /* 8711 * Handle a direct method call. 8712 * 8713 * (We could defer the "is 'this' pointer null" test to the common 8714 * method invocation code, and use a flag to indicate that static 8715 * calls don't count. If we do this as part of copying the arguments 8716 * out we could avoiding loading the first arg twice.) 8717 * 8718 */ 8719 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8720 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8721 FETCH(r0, 1) @ r1<- aaaa (lo) 8722 FETCH(r1, 2) @ r1<- AAAA (hi) 8723 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8724 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8725 FETCH(r10, 4) @ r10<- CCCC 8726 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8727 cmp r0, #0 @ already resolved? 8728 EXPORT_PC() @ must export for invoke 8729 GET_VREG(r2, r10) @ r2<- "this" ptr 8730 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now 8731.LOP_INVOKE_DIRECT_JUMBO_finish: 8732 cmp r2, #0 @ null "this" ref? 8733 bne common_invokeMethodJumbo @ no, continue on 8734 b common_errNullObject @ yes, throw exception 8735 8736/* ------------------------------ */ 8737 .balign 64 8738.L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 8739/* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */ 8740 /* 8741 * Handle a static method call. 8742 */ 8743 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8744 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8745 FETCH(r0, 1) @ r1<- aaaa (lo) 8746 FETCH(r1, 2) @ r1<- AAAA (hi) 8747 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8748 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8749 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8750 cmp r0, #0 @ already resolved? 8751 EXPORT_PC() @ must export for invoke 8752 bne common_invokeMethodJumbo @ yes, continue on 87530: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8754 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8755 mov r2, #METHOD_STATIC @ resolver method type 8756 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8757 cmp r0, #0 @ got null? 8758 bne common_invokeMethodJumbo @ no, continue 8759 b common_exceptionThrown @ yes, handle exception 8760 8761/* ------------------------------ */ 8762 .balign 64 8763.L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 8764/* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */ 8765 /* 8766 * Handle an interface method call. 8767 */ 8768 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8769 FETCH(r2, 4) @ r2<- CCCC 8770 FETCH(r0, 1) @ r0<- aaaa (lo) 8771 FETCH(r1, 2) @ r1<- AAAA (hi) 8772 EXPORT_PC() @ must export for invoke 8773 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8774 GET_VREG(r0, r2) @ r0<- first arg ("this") 8775 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 8776 cmp r0, #0 @ null obj? 8777 ldr r2, [rSELF, #offThread_method] @ r2<- method 8778 beq common_errNullObject @ yes, fail 8779 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 8780 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 8781 cmp r0, #0 @ failed? 8782 beq common_exceptionThrown @ yes, handle exception 8783 b common_invokeMethodJumbo @ jump to common handler 8784 8785/* ------------------------------ */ 8786 .balign 64 8787.L_OP_UNUSED_27FF: /* 0x127 */ 8788/* File: armv5te/OP_UNUSED_27FF.S */ 8789/* File: armv5te/unused.S */ 8790 bl common_abort 8791 8792 8793/* ------------------------------ */ 8794 .balign 64 8795.L_OP_UNUSED_28FF: /* 0x128 */ 8796/* File: armv5te/OP_UNUSED_28FF.S */ 8797/* File: armv5te/unused.S */ 8798 bl common_abort 8799 8800 8801/* ------------------------------ */ 8802 .balign 64 8803.L_OP_UNUSED_29FF: /* 0x129 */ 8804/* File: armv5te/OP_UNUSED_29FF.S */ 8805/* File: armv5te/unused.S */ 8806 bl common_abort 8807 8808 8809/* ------------------------------ */ 8810 .balign 64 8811.L_OP_UNUSED_2AFF: /* 0x12a */ 8812/* File: armv5te/OP_UNUSED_2AFF.S */ 8813/* File: armv5te/unused.S */ 8814 bl common_abort 8815 8816 8817/* ------------------------------ */ 8818 .balign 64 8819.L_OP_UNUSED_2BFF: /* 0x12b */ 8820/* File: armv5te/OP_UNUSED_2BFF.S */ 8821/* File: armv5te/unused.S */ 8822 bl common_abort 8823 8824 8825/* ------------------------------ */ 8826 .balign 64 8827.L_OP_UNUSED_2CFF: /* 0x12c */ 8828/* File: armv5te/OP_UNUSED_2CFF.S */ 8829/* File: armv5te/unused.S */ 8830 bl common_abort 8831 8832 8833/* ------------------------------ */ 8834 .balign 64 8835.L_OP_UNUSED_2DFF: /* 0x12d */ 8836/* File: armv5te/OP_UNUSED_2DFF.S */ 8837/* File: armv5te/unused.S */ 8838 bl common_abort 8839 8840 8841/* ------------------------------ */ 8842 .balign 64 8843.L_OP_UNUSED_2EFF: /* 0x12e */ 8844/* File: armv5te/OP_UNUSED_2EFF.S */ 8845/* File: armv5te/unused.S */ 8846 bl common_abort 8847 8848 8849/* ------------------------------ */ 8850 .balign 64 8851.L_OP_UNUSED_2FFF: /* 0x12f */ 8852/* File: armv5te/OP_UNUSED_2FFF.S */ 8853/* File: armv5te/unused.S */ 8854 bl common_abort 8855 8856 8857/* ------------------------------ */ 8858 .balign 64 8859.L_OP_UNUSED_30FF: /* 0x130 */ 8860/* File: armv5te/OP_UNUSED_30FF.S */ 8861/* File: armv5te/unused.S */ 8862 bl common_abort 8863 8864 8865/* ------------------------------ */ 8866 .balign 64 8867.L_OP_UNUSED_31FF: /* 0x131 */ 8868/* File: armv5te/OP_UNUSED_31FF.S */ 8869/* File: armv5te/unused.S */ 8870 bl common_abort 8871 8872 8873/* ------------------------------ */ 8874 .balign 64 8875.L_OP_UNUSED_32FF: /* 0x132 */ 8876/* File: armv5te/OP_UNUSED_32FF.S */ 8877/* File: armv5te/unused.S */ 8878 bl common_abort 8879 8880 8881/* ------------------------------ */ 8882 .balign 64 8883.L_OP_UNUSED_33FF: /* 0x133 */ 8884/* File: armv5te/OP_UNUSED_33FF.S */ 8885/* File: armv5te/unused.S */ 8886 bl common_abort 8887 8888 8889/* ------------------------------ */ 8890 .balign 64 8891.L_OP_UNUSED_34FF: /* 0x134 */ 8892/* File: armv5te/OP_UNUSED_34FF.S */ 8893/* File: armv5te/unused.S */ 8894 bl common_abort 8895 8896 8897/* ------------------------------ */ 8898 .balign 64 8899.L_OP_UNUSED_35FF: /* 0x135 */ 8900/* File: armv5te/OP_UNUSED_35FF.S */ 8901/* File: armv5te/unused.S */ 8902 bl common_abort 8903 8904 8905/* ------------------------------ */ 8906 .balign 64 8907.L_OP_UNUSED_36FF: /* 0x136 */ 8908/* File: armv5te/OP_UNUSED_36FF.S */ 8909/* File: armv5te/unused.S */ 8910 bl common_abort 8911 8912 8913/* ------------------------------ */ 8914 .balign 64 8915.L_OP_UNUSED_37FF: /* 0x137 */ 8916/* File: armv5te/OP_UNUSED_37FF.S */ 8917/* File: armv5te/unused.S */ 8918 bl common_abort 8919 8920 8921/* ------------------------------ */ 8922 .balign 64 8923.L_OP_UNUSED_38FF: /* 0x138 */ 8924/* File: armv5te/OP_UNUSED_38FF.S */ 8925/* File: armv5te/unused.S */ 8926 bl common_abort 8927 8928 8929/* ------------------------------ */ 8930 .balign 64 8931.L_OP_UNUSED_39FF: /* 0x139 */ 8932/* File: armv5te/OP_UNUSED_39FF.S */ 8933/* File: armv5te/unused.S */ 8934 bl common_abort 8935 8936 8937/* ------------------------------ */ 8938 .balign 64 8939.L_OP_UNUSED_3AFF: /* 0x13a */ 8940/* File: armv5te/OP_UNUSED_3AFF.S */ 8941/* File: armv5te/unused.S */ 8942 bl common_abort 8943 8944 8945/* ------------------------------ */ 8946 .balign 64 8947.L_OP_UNUSED_3BFF: /* 0x13b */ 8948/* File: armv5te/OP_UNUSED_3BFF.S */ 8949/* File: armv5te/unused.S */ 8950 bl common_abort 8951 8952 8953/* ------------------------------ */ 8954 .balign 64 8955.L_OP_UNUSED_3CFF: /* 0x13c */ 8956/* File: armv5te/OP_UNUSED_3CFF.S */ 8957/* File: armv5te/unused.S */ 8958 bl common_abort 8959 8960 8961/* ------------------------------ */ 8962 .balign 64 8963.L_OP_UNUSED_3DFF: /* 0x13d */ 8964/* File: armv5te/OP_UNUSED_3DFF.S */ 8965/* File: armv5te/unused.S */ 8966 bl common_abort 8967 8968 8969/* ------------------------------ */ 8970 .balign 64 8971.L_OP_UNUSED_3EFF: /* 0x13e */ 8972/* File: armv5te/OP_UNUSED_3EFF.S */ 8973/* File: armv5te/unused.S */ 8974 bl common_abort 8975 8976 8977/* ------------------------------ */ 8978 .balign 64 8979.L_OP_UNUSED_3FFF: /* 0x13f */ 8980/* File: armv5te/OP_UNUSED_3FFF.S */ 8981/* File: armv5te/unused.S */ 8982 bl common_abort 8983 8984 8985/* ------------------------------ */ 8986 .balign 64 8987.L_OP_UNUSED_40FF: /* 0x140 */ 8988/* File: armv5te/OP_UNUSED_40FF.S */ 8989/* File: armv5te/unused.S */ 8990 bl common_abort 8991 8992 8993/* ------------------------------ */ 8994 .balign 64 8995.L_OP_UNUSED_41FF: /* 0x141 */ 8996/* File: armv5te/OP_UNUSED_41FF.S */ 8997/* File: armv5te/unused.S */ 8998 bl common_abort 8999 9000 9001/* ------------------------------ */ 9002 .balign 64 9003.L_OP_UNUSED_42FF: /* 0x142 */ 9004/* File: armv5te/OP_UNUSED_42FF.S */ 9005/* File: armv5te/unused.S */ 9006 bl common_abort 9007 9008 9009/* ------------------------------ */ 9010 .balign 64 9011.L_OP_UNUSED_43FF: /* 0x143 */ 9012/* File: armv5te/OP_UNUSED_43FF.S */ 9013/* File: armv5te/unused.S */ 9014 bl common_abort 9015 9016 9017/* ------------------------------ */ 9018 .balign 64 9019.L_OP_UNUSED_44FF: /* 0x144 */ 9020/* File: armv5te/OP_UNUSED_44FF.S */ 9021/* File: armv5te/unused.S */ 9022 bl common_abort 9023 9024 9025/* ------------------------------ */ 9026 .balign 64 9027.L_OP_UNUSED_45FF: /* 0x145 */ 9028/* File: armv5te/OP_UNUSED_45FF.S */ 9029/* File: armv5te/unused.S */ 9030 bl common_abort 9031 9032 9033/* ------------------------------ */ 9034 .balign 64 9035.L_OP_UNUSED_46FF: /* 0x146 */ 9036/* File: armv5te/OP_UNUSED_46FF.S */ 9037/* File: armv5te/unused.S */ 9038 bl common_abort 9039 9040 9041/* ------------------------------ */ 9042 .balign 64 9043.L_OP_UNUSED_47FF: /* 0x147 */ 9044/* File: armv5te/OP_UNUSED_47FF.S */ 9045/* File: armv5te/unused.S */ 9046 bl common_abort 9047 9048 9049/* ------------------------------ */ 9050 .balign 64 9051.L_OP_UNUSED_48FF: /* 0x148 */ 9052/* File: armv5te/OP_UNUSED_48FF.S */ 9053/* File: armv5te/unused.S */ 9054 bl common_abort 9055 9056 9057/* ------------------------------ */ 9058 .balign 64 9059.L_OP_UNUSED_49FF: /* 0x149 */ 9060/* File: armv5te/OP_UNUSED_49FF.S */ 9061/* File: armv5te/unused.S */ 9062 bl common_abort 9063 9064 9065/* ------------------------------ */ 9066 .balign 64 9067.L_OP_UNUSED_4AFF: /* 0x14a */ 9068/* File: armv5te/OP_UNUSED_4AFF.S */ 9069/* File: armv5te/unused.S */ 9070 bl common_abort 9071 9072 9073/* ------------------------------ */ 9074 .balign 64 9075.L_OP_UNUSED_4BFF: /* 0x14b */ 9076/* File: armv5te/OP_UNUSED_4BFF.S */ 9077/* File: armv5te/unused.S */ 9078 bl common_abort 9079 9080 9081/* ------------------------------ */ 9082 .balign 64 9083.L_OP_UNUSED_4CFF: /* 0x14c */ 9084/* File: armv5te/OP_UNUSED_4CFF.S */ 9085/* File: armv5te/unused.S */ 9086 bl common_abort 9087 9088 9089/* ------------------------------ */ 9090 .balign 64 9091.L_OP_UNUSED_4DFF: /* 0x14d */ 9092/* File: armv5te/OP_UNUSED_4DFF.S */ 9093/* File: armv5te/unused.S */ 9094 bl common_abort 9095 9096 9097/* ------------------------------ */ 9098 .balign 64 9099.L_OP_UNUSED_4EFF: /* 0x14e */ 9100/* File: armv5te/OP_UNUSED_4EFF.S */ 9101/* File: armv5te/unused.S */ 9102 bl common_abort 9103 9104 9105/* ------------------------------ */ 9106 .balign 64 9107.L_OP_UNUSED_4FFF: /* 0x14f */ 9108/* File: armv5te/OP_UNUSED_4FFF.S */ 9109/* File: armv5te/unused.S */ 9110 bl common_abort 9111 9112 9113/* ------------------------------ */ 9114 .balign 64 9115.L_OP_UNUSED_50FF: /* 0x150 */ 9116/* File: armv5te/OP_UNUSED_50FF.S */ 9117/* File: armv5te/unused.S */ 9118 bl common_abort 9119 9120 9121/* ------------------------------ */ 9122 .balign 64 9123.L_OP_UNUSED_51FF: /* 0x151 */ 9124/* File: armv5te/OP_UNUSED_51FF.S */ 9125/* File: armv5te/unused.S */ 9126 bl common_abort 9127 9128 9129/* ------------------------------ */ 9130 .balign 64 9131.L_OP_UNUSED_52FF: /* 0x152 */ 9132/* File: armv5te/OP_UNUSED_52FF.S */ 9133/* File: armv5te/unused.S */ 9134 bl common_abort 9135 9136 9137/* ------------------------------ */ 9138 .balign 64 9139.L_OP_UNUSED_53FF: /* 0x153 */ 9140/* File: armv5te/OP_UNUSED_53FF.S */ 9141/* File: armv5te/unused.S */ 9142 bl common_abort 9143 9144 9145/* ------------------------------ */ 9146 .balign 64 9147.L_OP_UNUSED_54FF: /* 0x154 */ 9148/* File: armv5te/OP_UNUSED_54FF.S */ 9149/* File: armv5te/unused.S */ 9150 bl common_abort 9151 9152 9153/* ------------------------------ */ 9154 .balign 64 9155.L_OP_UNUSED_55FF: /* 0x155 */ 9156/* File: armv5te/OP_UNUSED_55FF.S */ 9157/* File: armv5te/unused.S */ 9158 bl common_abort 9159 9160 9161/* ------------------------------ */ 9162 .balign 64 9163.L_OP_UNUSED_56FF: /* 0x156 */ 9164/* File: armv5te/OP_UNUSED_56FF.S */ 9165/* File: armv5te/unused.S */ 9166 bl common_abort 9167 9168 9169/* ------------------------------ */ 9170 .balign 64 9171.L_OP_UNUSED_57FF: /* 0x157 */ 9172/* File: armv5te/OP_UNUSED_57FF.S */ 9173/* File: armv5te/unused.S */ 9174 bl common_abort 9175 9176 9177/* ------------------------------ */ 9178 .balign 64 9179.L_OP_UNUSED_58FF: /* 0x158 */ 9180/* File: armv5te/OP_UNUSED_58FF.S */ 9181/* File: armv5te/unused.S */ 9182 bl common_abort 9183 9184 9185/* ------------------------------ */ 9186 .balign 64 9187.L_OP_UNUSED_59FF: /* 0x159 */ 9188/* File: armv5te/OP_UNUSED_59FF.S */ 9189/* File: armv5te/unused.S */ 9190 bl common_abort 9191 9192 9193/* ------------------------------ */ 9194 .balign 64 9195.L_OP_UNUSED_5AFF: /* 0x15a */ 9196/* File: armv5te/OP_UNUSED_5AFF.S */ 9197/* File: armv5te/unused.S */ 9198 bl common_abort 9199 9200 9201/* ------------------------------ */ 9202 .balign 64 9203.L_OP_UNUSED_5BFF: /* 0x15b */ 9204/* File: armv5te/OP_UNUSED_5BFF.S */ 9205/* File: armv5te/unused.S */ 9206 bl common_abort 9207 9208 9209/* ------------------------------ */ 9210 .balign 64 9211.L_OP_UNUSED_5CFF: /* 0x15c */ 9212/* File: armv5te/OP_UNUSED_5CFF.S */ 9213/* File: armv5te/unused.S */ 9214 bl common_abort 9215 9216 9217/* ------------------------------ */ 9218 .balign 64 9219.L_OP_UNUSED_5DFF: /* 0x15d */ 9220/* File: armv5te/OP_UNUSED_5DFF.S */ 9221/* File: armv5te/unused.S */ 9222 bl common_abort 9223 9224 9225/* ------------------------------ */ 9226 .balign 64 9227.L_OP_UNUSED_5EFF: /* 0x15e */ 9228/* File: armv5te/OP_UNUSED_5EFF.S */ 9229/* File: armv5te/unused.S */ 9230 bl common_abort 9231 9232 9233/* ------------------------------ */ 9234 .balign 64 9235.L_OP_UNUSED_5FFF: /* 0x15f */ 9236/* File: armv5te/OP_UNUSED_5FFF.S */ 9237/* File: armv5te/unused.S */ 9238 bl common_abort 9239 9240 9241/* ------------------------------ */ 9242 .balign 64 9243.L_OP_UNUSED_60FF: /* 0x160 */ 9244/* File: armv5te/OP_UNUSED_60FF.S */ 9245/* File: armv5te/unused.S */ 9246 bl common_abort 9247 9248 9249/* ------------------------------ */ 9250 .balign 64 9251.L_OP_UNUSED_61FF: /* 0x161 */ 9252/* File: armv5te/OP_UNUSED_61FF.S */ 9253/* File: armv5te/unused.S */ 9254 bl common_abort 9255 9256 9257/* ------------------------------ */ 9258 .balign 64 9259.L_OP_UNUSED_62FF: /* 0x162 */ 9260/* File: armv5te/OP_UNUSED_62FF.S */ 9261/* File: armv5te/unused.S */ 9262 bl common_abort 9263 9264 9265/* ------------------------------ */ 9266 .balign 64 9267.L_OP_UNUSED_63FF: /* 0x163 */ 9268/* File: armv5te/OP_UNUSED_63FF.S */ 9269/* File: armv5te/unused.S */ 9270 bl common_abort 9271 9272 9273/* ------------------------------ */ 9274 .balign 64 9275.L_OP_UNUSED_64FF: /* 0x164 */ 9276/* File: armv5te/OP_UNUSED_64FF.S */ 9277/* File: armv5te/unused.S */ 9278 bl common_abort 9279 9280 9281/* ------------------------------ */ 9282 .balign 64 9283.L_OP_UNUSED_65FF: /* 0x165 */ 9284/* File: armv5te/OP_UNUSED_65FF.S */ 9285/* File: armv5te/unused.S */ 9286 bl common_abort 9287 9288 9289/* ------------------------------ */ 9290 .balign 64 9291.L_OP_UNUSED_66FF: /* 0x166 */ 9292/* File: armv5te/OP_UNUSED_66FF.S */ 9293/* File: armv5te/unused.S */ 9294 bl common_abort 9295 9296 9297/* ------------------------------ */ 9298 .balign 64 9299.L_OP_UNUSED_67FF: /* 0x167 */ 9300/* File: armv5te/OP_UNUSED_67FF.S */ 9301/* File: armv5te/unused.S */ 9302 bl common_abort 9303 9304 9305/* ------------------------------ */ 9306 .balign 64 9307.L_OP_UNUSED_68FF: /* 0x168 */ 9308/* File: armv5te/OP_UNUSED_68FF.S */ 9309/* File: armv5te/unused.S */ 9310 bl common_abort 9311 9312 9313/* ------------------------------ */ 9314 .balign 64 9315.L_OP_UNUSED_69FF: /* 0x169 */ 9316/* File: armv5te/OP_UNUSED_69FF.S */ 9317/* File: armv5te/unused.S */ 9318 bl common_abort 9319 9320 9321/* ------------------------------ */ 9322 .balign 64 9323.L_OP_UNUSED_6AFF: /* 0x16a */ 9324/* File: armv5te/OP_UNUSED_6AFF.S */ 9325/* File: armv5te/unused.S */ 9326 bl common_abort 9327 9328 9329/* ------------------------------ */ 9330 .balign 64 9331.L_OP_UNUSED_6BFF: /* 0x16b */ 9332/* File: armv5te/OP_UNUSED_6BFF.S */ 9333/* File: armv5te/unused.S */ 9334 bl common_abort 9335 9336 9337/* ------------------------------ */ 9338 .balign 64 9339.L_OP_UNUSED_6CFF: /* 0x16c */ 9340/* File: armv5te/OP_UNUSED_6CFF.S */ 9341/* File: armv5te/unused.S */ 9342 bl common_abort 9343 9344 9345/* ------------------------------ */ 9346 .balign 64 9347.L_OP_UNUSED_6DFF: /* 0x16d */ 9348/* File: armv5te/OP_UNUSED_6DFF.S */ 9349/* File: armv5te/unused.S */ 9350 bl common_abort 9351 9352 9353/* ------------------------------ */ 9354 .balign 64 9355.L_OP_UNUSED_6EFF: /* 0x16e */ 9356/* File: armv5te/OP_UNUSED_6EFF.S */ 9357/* File: armv5te/unused.S */ 9358 bl common_abort 9359 9360 9361/* ------------------------------ */ 9362 .balign 64 9363.L_OP_UNUSED_6FFF: /* 0x16f */ 9364/* File: armv5te/OP_UNUSED_6FFF.S */ 9365/* File: armv5te/unused.S */ 9366 bl common_abort 9367 9368 9369/* ------------------------------ */ 9370 .balign 64 9371.L_OP_UNUSED_70FF: /* 0x170 */ 9372/* File: armv5te/OP_UNUSED_70FF.S */ 9373/* File: armv5te/unused.S */ 9374 bl common_abort 9375 9376 9377/* ------------------------------ */ 9378 .balign 64 9379.L_OP_UNUSED_71FF: /* 0x171 */ 9380/* File: armv5te/OP_UNUSED_71FF.S */ 9381/* File: armv5te/unused.S */ 9382 bl common_abort 9383 9384 9385/* ------------------------------ */ 9386 .balign 64 9387.L_OP_UNUSED_72FF: /* 0x172 */ 9388/* File: armv5te/OP_UNUSED_72FF.S */ 9389/* File: armv5te/unused.S */ 9390 bl common_abort 9391 9392 9393/* ------------------------------ */ 9394 .balign 64 9395.L_OP_UNUSED_73FF: /* 0x173 */ 9396/* File: armv5te/OP_UNUSED_73FF.S */ 9397/* File: armv5te/unused.S */ 9398 bl common_abort 9399 9400 9401/* ------------------------------ */ 9402 .balign 64 9403.L_OP_UNUSED_74FF: /* 0x174 */ 9404/* File: armv5te/OP_UNUSED_74FF.S */ 9405/* File: armv5te/unused.S */ 9406 bl common_abort 9407 9408 9409/* ------------------------------ */ 9410 .balign 64 9411.L_OP_UNUSED_75FF: /* 0x175 */ 9412/* File: armv5te/OP_UNUSED_75FF.S */ 9413/* File: armv5te/unused.S */ 9414 bl common_abort 9415 9416 9417/* ------------------------------ */ 9418 .balign 64 9419.L_OP_UNUSED_76FF: /* 0x176 */ 9420/* File: armv5te/OP_UNUSED_76FF.S */ 9421/* File: armv5te/unused.S */ 9422 bl common_abort 9423 9424 9425/* ------------------------------ */ 9426 .balign 64 9427.L_OP_UNUSED_77FF: /* 0x177 */ 9428/* File: armv5te/OP_UNUSED_77FF.S */ 9429/* File: armv5te/unused.S */ 9430 bl common_abort 9431 9432 9433/* ------------------------------ */ 9434 .balign 64 9435.L_OP_UNUSED_78FF: /* 0x178 */ 9436/* File: armv5te/OP_UNUSED_78FF.S */ 9437/* File: armv5te/unused.S */ 9438 bl common_abort 9439 9440 9441/* ------------------------------ */ 9442 .balign 64 9443.L_OP_UNUSED_79FF: /* 0x179 */ 9444/* File: armv5te/OP_UNUSED_79FF.S */ 9445/* File: armv5te/unused.S */ 9446 bl common_abort 9447 9448 9449/* ------------------------------ */ 9450 .balign 64 9451.L_OP_UNUSED_7AFF: /* 0x17a */ 9452/* File: armv5te/OP_UNUSED_7AFF.S */ 9453/* File: armv5te/unused.S */ 9454 bl common_abort 9455 9456 9457/* ------------------------------ */ 9458 .balign 64 9459.L_OP_UNUSED_7BFF: /* 0x17b */ 9460/* File: armv5te/OP_UNUSED_7BFF.S */ 9461/* File: armv5te/unused.S */ 9462 bl common_abort 9463 9464 9465/* ------------------------------ */ 9466 .balign 64 9467.L_OP_UNUSED_7CFF: /* 0x17c */ 9468/* File: armv5te/OP_UNUSED_7CFF.S */ 9469/* File: armv5te/unused.S */ 9470 bl common_abort 9471 9472 9473/* ------------------------------ */ 9474 .balign 64 9475.L_OP_UNUSED_7DFF: /* 0x17d */ 9476/* File: armv5te/OP_UNUSED_7DFF.S */ 9477/* File: armv5te/unused.S */ 9478 bl common_abort 9479 9480 9481/* ------------------------------ */ 9482 .balign 64 9483.L_OP_UNUSED_7EFF: /* 0x17e */ 9484/* File: armv5te/OP_UNUSED_7EFF.S */ 9485/* File: armv5te/unused.S */ 9486 bl common_abort 9487 9488 9489/* ------------------------------ */ 9490 .balign 64 9491.L_OP_UNUSED_7FFF: /* 0x17f */ 9492/* File: armv5te/OP_UNUSED_7FFF.S */ 9493/* File: armv5te/unused.S */ 9494 bl common_abort 9495 9496 9497/* ------------------------------ */ 9498 .balign 64 9499.L_OP_UNUSED_80FF: /* 0x180 */ 9500/* File: armv5te/OP_UNUSED_80FF.S */ 9501/* File: armv5te/unused.S */ 9502 bl common_abort 9503 9504 9505/* ------------------------------ */ 9506 .balign 64 9507.L_OP_UNUSED_81FF: /* 0x181 */ 9508/* File: armv5te/OP_UNUSED_81FF.S */ 9509/* File: armv5te/unused.S */ 9510 bl common_abort 9511 9512 9513/* ------------------------------ */ 9514 .balign 64 9515.L_OP_UNUSED_82FF: /* 0x182 */ 9516/* File: armv5te/OP_UNUSED_82FF.S */ 9517/* File: armv5te/unused.S */ 9518 bl common_abort 9519 9520 9521/* ------------------------------ */ 9522 .balign 64 9523.L_OP_UNUSED_83FF: /* 0x183 */ 9524/* File: armv5te/OP_UNUSED_83FF.S */ 9525/* File: armv5te/unused.S */ 9526 bl common_abort 9527 9528 9529/* ------------------------------ */ 9530 .balign 64 9531.L_OP_UNUSED_84FF: /* 0x184 */ 9532/* File: armv5te/OP_UNUSED_84FF.S */ 9533/* File: armv5te/unused.S */ 9534 bl common_abort 9535 9536 9537/* ------------------------------ */ 9538 .balign 64 9539.L_OP_UNUSED_85FF: /* 0x185 */ 9540/* File: armv5te/OP_UNUSED_85FF.S */ 9541/* File: armv5te/unused.S */ 9542 bl common_abort 9543 9544 9545/* ------------------------------ */ 9546 .balign 64 9547.L_OP_UNUSED_86FF: /* 0x186 */ 9548/* File: armv5te/OP_UNUSED_86FF.S */ 9549/* File: armv5te/unused.S */ 9550 bl common_abort 9551 9552 9553/* ------------------------------ */ 9554 .balign 64 9555.L_OP_UNUSED_87FF: /* 0x187 */ 9556/* File: armv5te/OP_UNUSED_87FF.S */ 9557/* File: armv5te/unused.S */ 9558 bl common_abort 9559 9560 9561/* ------------------------------ */ 9562 .balign 64 9563.L_OP_UNUSED_88FF: /* 0x188 */ 9564/* File: armv5te/OP_UNUSED_88FF.S */ 9565/* File: armv5te/unused.S */ 9566 bl common_abort 9567 9568 9569/* ------------------------------ */ 9570 .balign 64 9571.L_OP_UNUSED_89FF: /* 0x189 */ 9572/* File: armv5te/OP_UNUSED_89FF.S */ 9573/* File: armv5te/unused.S */ 9574 bl common_abort 9575 9576 9577/* ------------------------------ */ 9578 .balign 64 9579.L_OP_UNUSED_8AFF: /* 0x18a */ 9580/* File: armv5te/OP_UNUSED_8AFF.S */ 9581/* File: armv5te/unused.S */ 9582 bl common_abort 9583 9584 9585/* ------------------------------ */ 9586 .balign 64 9587.L_OP_UNUSED_8BFF: /* 0x18b */ 9588/* File: armv5te/OP_UNUSED_8BFF.S */ 9589/* File: armv5te/unused.S */ 9590 bl common_abort 9591 9592 9593/* ------------------------------ */ 9594 .balign 64 9595.L_OP_UNUSED_8CFF: /* 0x18c */ 9596/* File: armv5te/OP_UNUSED_8CFF.S */ 9597/* File: armv5te/unused.S */ 9598 bl common_abort 9599 9600 9601/* ------------------------------ */ 9602 .balign 64 9603.L_OP_UNUSED_8DFF: /* 0x18d */ 9604/* File: armv5te/OP_UNUSED_8DFF.S */ 9605/* File: armv5te/unused.S */ 9606 bl common_abort 9607 9608 9609/* ------------------------------ */ 9610 .balign 64 9611.L_OP_UNUSED_8EFF: /* 0x18e */ 9612/* File: armv5te/OP_UNUSED_8EFF.S */ 9613/* File: armv5te/unused.S */ 9614 bl common_abort 9615 9616 9617/* ------------------------------ */ 9618 .balign 64 9619.L_OP_UNUSED_8FFF: /* 0x18f */ 9620/* File: armv5te/OP_UNUSED_8FFF.S */ 9621/* File: armv5te/unused.S */ 9622 bl common_abort 9623 9624 9625/* ------------------------------ */ 9626 .balign 64 9627.L_OP_UNUSED_90FF: /* 0x190 */ 9628/* File: armv5te/OP_UNUSED_90FF.S */ 9629/* File: armv5te/unused.S */ 9630 bl common_abort 9631 9632 9633/* ------------------------------ */ 9634 .balign 64 9635.L_OP_UNUSED_91FF: /* 0x191 */ 9636/* File: armv5te/OP_UNUSED_91FF.S */ 9637/* File: armv5te/unused.S */ 9638 bl common_abort 9639 9640 9641/* ------------------------------ */ 9642 .balign 64 9643.L_OP_UNUSED_92FF: /* 0x192 */ 9644/* File: armv5te/OP_UNUSED_92FF.S */ 9645/* File: armv5te/unused.S */ 9646 bl common_abort 9647 9648 9649/* ------------------------------ */ 9650 .balign 64 9651.L_OP_UNUSED_93FF: /* 0x193 */ 9652/* File: armv5te/OP_UNUSED_93FF.S */ 9653/* File: armv5te/unused.S */ 9654 bl common_abort 9655 9656 9657/* ------------------------------ */ 9658 .balign 64 9659.L_OP_UNUSED_94FF: /* 0x194 */ 9660/* File: armv5te/OP_UNUSED_94FF.S */ 9661/* File: armv5te/unused.S */ 9662 bl common_abort 9663 9664 9665/* ------------------------------ */ 9666 .balign 64 9667.L_OP_UNUSED_95FF: /* 0x195 */ 9668/* File: armv5te/OP_UNUSED_95FF.S */ 9669/* File: armv5te/unused.S */ 9670 bl common_abort 9671 9672 9673/* ------------------------------ */ 9674 .balign 64 9675.L_OP_UNUSED_96FF: /* 0x196 */ 9676/* File: armv5te/OP_UNUSED_96FF.S */ 9677/* File: armv5te/unused.S */ 9678 bl common_abort 9679 9680 9681/* ------------------------------ */ 9682 .balign 64 9683.L_OP_UNUSED_97FF: /* 0x197 */ 9684/* File: armv5te/OP_UNUSED_97FF.S */ 9685/* File: armv5te/unused.S */ 9686 bl common_abort 9687 9688 9689/* ------------------------------ */ 9690 .balign 64 9691.L_OP_UNUSED_98FF: /* 0x198 */ 9692/* File: armv5te/OP_UNUSED_98FF.S */ 9693/* File: armv5te/unused.S */ 9694 bl common_abort 9695 9696 9697/* ------------------------------ */ 9698 .balign 64 9699.L_OP_UNUSED_99FF: /* 0x199 */ 9700/* File: armv5te/OP_UNUSED_99FF.S */ 9701/* File: armv5te/unused.S */ 9702 bl common_abort 9703 9704 9705/* ------------------------------ */ 9706 .balign 64 9707.L_OP_UNUSED_9AFF: /* 0x19a */ 9708/* File: armv5te/OP_UNUSED_9AFF.S */ 9709/* File: armv5te/unused.S */ 9710 bl common_abort 9711 9712 9713/* ------------------------------ */ 9714 .balign 64 9715.L_OP_UNUSED_9BFF: /* 0x19b */ 9716/* File: armv5te/OP_UNUSED_9BFF.S */ 9717/* File: armv5te/unused.S */ 9718 bl common_abort 9719 9720 9721/* ------------------------------ */ 9722 .balign 64 9723.L_OP_UNUSED_9CFF: /* 0x19c */ 9724/* File: armv5te/OP_UNUSED_9CFF.S */ 9725/* File: armv5te/unused.S */ 9726 bl common_abort 9727 9728 9729/* ------------------------------ */ 9730 .balign 64 9731.L_OP_UNUSED_9DFF: /* 0x19d */ 9732/* File: armv5te/OP_UNUSED_9DFF.S */ 9733/* File: armv5te/unused.S */ 9734 bl common_abort 9735 9736 9737/* ------------------------------ */ 9738 .balign 64 9739.L_OP_UNUSED_9EFF: /* 0x19e */ 9740/* File: armv5te/OP_UNUSED_9EFF.S */ 9741/* File: armv5te/unused.S */ 9742 bl common_abort 9743 9744 9745/* ------------------------------ */ 9746 .balign 64 9747.L_OP_UNUSED_9FFF: /* 0x19f */ 9748/* File: armv5te/OP_UNUSED_9FFF.S */ 9749/* File: armv5te/unused.S */ 9750 bl common_abort 9751 9752 9753/* ------------------------------ */ 9754 .balign 64 9755.L_OP_UNUSED_A0FF: /* 0x1a0 */ 9756/* File: armv5te/OP_UNUSED_A0FF.S */ 9757/* File: armv5te/unused.S */ 9758 bl common_abort 9759 9760 9761/* ------------------------------ */ 9762 .balign 64 9763.L_OP_UNUSED_A1FF: /* 0x1a1 */ 9764/* File: armv5te/OP_UNUSED_A1FF.S */ 9765/* File: armv5te/unused.S */ 9766 bl common_abort 9767 9768 9769/* ------------------------------ */ 9770 .balign 64 9771.L_OP_UNUSED_A2FF: /* 0x1a2 */ 9772/* File: armv5te/OP_UNUSED_A2FF.S */ 9773/* File: armv5te/unused.S */ 9774 bl common_abort 9775 9776 9777/* ------------------------------ */ 9778 .balign 64 9779.L_OP_UNUSED_A3FF: /* 0x1a3 */ 9780/* File: armv5te/OP_UNUSED_A3FF.S */ 9781/* File: armv5te/unused.S */ 9782 bl common_abort 9783 9784 9785/* ------------------------------ */ 9786 .balign 64 9787.L_OP_UNUSED_A4FF: /* 0x1a4 */ 9788/* File: armv5te/OP_UNUSED_A4FF.S */ 9789/* File: armv5te/unused.S */ 9790 bl common_abort 9791 9792 9793/* ------------------------------ */ 9794 .balign 64 9795.L_OP_UNUSED_A5FF: /* 0x1a5 */ 9796/* File: armv5te/OP_UNUSED_A5FF.S */ 9797/* File: armv5te/unused.S */ 9798 bl common_abort 9799 9800 9801/* ------------------------------ */ 9802 .balign 64 9803.L_OP_UNUSED_A6FF: /* 0x1a6 */ 9804/* File: armv5te/OP_UNUSED_A6FF.S */ 9805/* File: armv5te/unused.S */ 9806 bl common_abort 9807 9808 9809/* ------------------------------ */ 9810 .balign 64 9811.L_OP_UNUSED_A7FF: /* 0x1a7 */ 9812/* File: armv5te/OP_UNUSED_A7FF.S */ 9813/* File: armv5te/unused.S */ 9814 bl common_abort 9815 9816 9817/* ------------------------------ */ 9818 .balign 64 9819.L_OP_UNUSED_A8FF: /* 0x1a8 */ 9820/* File: armv5te/OP_UNUSED_A8FF.S */ 9821/* File: armv5te/unused.S */ 9822 bl common_abort 9823 9824 9825/* ------------------------------ */ 9826 .balign 64 9827.L_OP_UNUSED_A9FF: /* 0x1a9 */ 9828/* File: armv5te/OP_UNUSED_A9FF.S */ 9829/* File: armv5te/unused.S */ 9830 bl common_abort 9831 9832 9833/* ------------------------------ */ 9834 .balign 64 9835.L_OP_UNUSED_AAFF: /* 0x1aa */ 9836/* File: armv5te/OP_UNUSED_AAFF.S */ 9837/* File: armv5te/unused.S */ 9838 bl common_abort 9839 9840 9841/* ------------------------------ */ 9842 .balign 64 9843.L_OP_UNUSED_ABFF: /* 0x1ab */ 9844/* File: armv5te/OP_UNUSED_ABFF.S */ 9845/* File: armv5te/unused.S */ 9846 bl common_abort 9847 9848 9849/* ------------------------------ */ 9850 .balign 64 9851.L_OP_UNUSED_ACFF: /* 0x1ac */ 9852/* File: armv5te/OP_UNUSED_ACFF.S */ 9853/* File: armv5te/unused.S */ 9854 bl common_abort 9855 9856 9857/* ------------------------------ */ 9858 .balign 64 9859.L_OP_UNUSED_ADFF: /* 0x1ad */ 9860/* File: armv5te/OP_UNUSED_ADFF.S */ 9861/* File: armv5te/unused.S */ 9862 bl common_abort 9863 9864 9865/* ------------------------------ */ 9866 .balign 64 9867.L_OP_UNUSED_AEFF: /* 0x1ae */ 9868/* File: armv5te/OP_UNUSED_AEFF.S */ 9869/* File: armv5te/unused.S */ 9870 bl common_abort 9871 9872 9873/* ------------------------------ */ 9874 .balign 64 9875.L_OP_UNUSED_AFFF: /* 0x1af */ 9876/* File: armv5te/OP_UNUSED_AFFF.S */ 9877/* File: armv5te/unused.S */ 9878 bl common_abort 9879 9880 9881/* ------------------------------ */ 9882 .balign 64 9883.L_OP_UNUSED_B0FF: /* 0x1b0 */ 9884/* File: armv5te/OP_UNUSED_B0FF.S */ 9885/* File: armv5te/unused.S */ 9886 bl common_abort 9887 9888 9889/* ------------------------------ */ 9890 .balign 64 9891.L_OP_UNUSED_B1FF: /* 0x1b1 */ 9892/* File: armv5te/OP_UNUSED_B1FF.S */ 9893/* File: armv5te/unused.S */ 9894 bl common_abort 9895 9896 9897/* ------------------------------ */ 9898 .balign 64 9899.L_OP_UNUSED_B2FF: /* 0x1b2 */ 9900/* File: armv5te/OP_UNUSED_B2FF.S */ 9901/* File: armv5te/unused.S */ 9902 bl common_abort 9903 9904 9905/* ------------------------------ */ 9906 .balign 64 9907.L_OP_UNUSED_B3FF: /* 0x1b3 */ 9908/* File: armv5te/OP_UNUSED_B3FF.S */ 9909/* File: armv5te/unused.S */ 9910 bl common_abort 9911 9912 9913/* ------------------------------ */ 9914 .balign 64 9915.L_OP_UNUSED_B4FF: /* 0x1b4 */ 9916/* File: armv5te/OP_UNUSED_B4FF.S */ 9917/* File: armv5te/unused.S */ 9918 bl common_abort 9919 9920 9921/* ------------------------------ */ 9922 .balign 64 9923.L_OP_UNUSED_B5FF: /* 0x1b5 */ 9924/* File: armv5te/OP_UNUSED_B5FF.S */ 9925/* File: armv5te/unused.S */ 9926 bl common_abort 9927 9928 9929/* ------------------------------ */ 9930 .balign 64 9931.L_OP_UNUSED_B6FF: /* 0x1b6 */ 9932/* File: armv5te/OP_UNUSED_B6FF.S */ 9933/* File: armv5te/unused.S */ 9934 bl common_abort 9935 9936 9937/* ------------------------------ */ 9938 .balign 64 9939.L_OP_UNUSED_B7FF: /* 0x1b7 */ 9940/* File: armv5te/OP_UNUSED_B7FF.S */ 9941/* File: armv5te/unused.S */ 9942 bl common_abort 9943 9944 9945/* ------------------------------ */ 9946 .balign 64 9947.L_OP_UNUSED_B8FF: /* 0x1b8 */ 9948/* File: armv5te/OP_UNUSED_B8FF.S */ 9949/* File: armv5te/unused.S */ 9950 bl common_abort 9951 9952 9953/* ------------------------------ */ 9954 .balign 64 9955.L_OP_UNUSED_B9FF: /* 0x1b9 */ 9956/* File: armv5te/OP_UNUSED_B9FF.S */ 9957/* File: armv5te/unused.S */ 9958 bl common_abort 9959 9960 9961/* ------------------------------ */ 9962 .balign 64 9963.L_OP_UNUSED_BAFF: /* 0x1ba */ 9964/* File: armv5te/OP_UNUSED_BAFF.S */ 9965/* File: armv5te/unused.S */ 9966 bl common_abort 9967 9968 9969/* ------------------------------ */ 9970 .balign 64 9971.L_OP_UNUSED_BBFF: /* 0x1bb */ 9972/* File: armv5te/OP_UNUSED_BBFF.S */ 9973/* File: armv5te/unused.S */ 9974 bl common_abort 9975 9976 9977/* ------------------------------ */ 9978 .balign 64 9979.L_OP_UNUSED_BCFF: /* 0x1bc */ 9980/* File: armv5te/OP_UNUSED_BCFF.S */ 9981/* File: armv5te/unused.S */ 9982 bl common_abort 9983 9984 9985/* ------------------------------ */ 9986 .balign 64 9987.L_OP_UNUSED_BDFF: /* 0x1bd */ 9988/* File: armv5te/OP_UNUSED_BDFF.S */ 9989/* File: armv5te/unused.S */ 9990 bl common_abort 9991 9992 9993/* ------------------------------ */ 9994 .balign 64 9995.L_OP_UNUSED_BEFF: /* 0x1be */ 9996/* File: armv5te/OP_UNUSED_BEFF.S */ 9997/* File: armv5te/unused.S */ 9998 bl common_abort 9999 10000 10001/* ------------------------------ */ 10002 .balign 64 10003.L_OP_UNUSED_BFFF: /* 0x1bf */ 10004/* File: armv5te/OP_UNUSED_BFFF.S */ 10005/* File: armv5te/unused.S */ 10006 bl common_abort 10007 10008 10009/* ------------------------------ */ 10010 .balign 64 10011.L_OP_UNUSED_C0FF: /* 0x1c0 */ 10012/* File: armv5te/OP_UNUSED_C0FF.S */ 10013/* File: armv5te/unused.S */ 10014 bl common_abort 10015 10016 10017/* ------------------------------ */ 10018 .balign 64 10019.L_OP_UNUSED_C1FF: /* 0x1c1 */ 10020/* File: armv5te/OP_UNUSED_C1FF.S */ 10021/* File: armv5te/unused.S */ 10022 bl common_abort 10023 10024 10025/* ------------------------------ */ 10026 .balign 64 10027.L_OP_UNUSED_C2FF: /* 0x1c2 */ 10028/* File: armv5te/OP_UNUSED_C2FF.S */ 10029/* File: armv5te/unused.S */ 10030 bl common_abort 10031 10032 10033/* ------------------------------ */ 10034 .balign 64 10035.L_OP_UNUSED_C3FF: /* 0x1c3 */ 10036/* File: armv5te/OP_UNUSED_C3FF.S */ 10037/* File: armv5te/unused.S */ 10038 bl common_abort 10039 10040 10041/* ------------------------------ */ 10042 .balign 64 10043.L_OP_UNUSED_C4FF: /* 0x1c4 */ 10044/* File: armv5te/OP_UNUSED_C4FF.S */ 10045/* File: armv5te/unused.S */ 10046 bl common_abort 10047 10048 10049/* ------------------------------ */ 10050 .balign 64 10051.L_OP_UNUSED_C5FF: /* 0x1c5 */ 10052/* File: armv5te/OP_UNUSED_C5FF.S */ 10053/* File: armv5te/unused.S */ 10054 bl common_abort 10055 10056 10057/* ------------------------------ */ 10058 .balign 64 10059.L_OP_UNUSED_C6FF: /* 0x1c6 */ 10060/* File: armv5te/OP_UNUSED_C6FF.S */ 10061/* File: armv5te/unused.S */ 10062 bl common_abort 10063 10064 10065/* ------------------------------ */ 10066 .balign 64 10067.L_OP_UNUSED_C7FF: /* 0x1c7 */ 10068/* File: armv5te/OP_UNUSED_C7FF.S */ 10069/* File: armv5te/unused.S */ 10070 bl common_abort 10071 10072 10073/* ------------------------------ */ 10074 .balign 64 10075.L_OP_UNUSED_C8FF: /* 0x1c8 */ 10076/* File: armv5te/OP_UNUSED_C8FF.S */ 10077/* File: armv5te/unused.S */ 10078 bl common_abort 10079 10080 10081/* ------------------------------ */ 10082 .balign 64 10083.L_OP_UNUSED_C9FF: /* 0x1c9 */ 10084/* File: armv5te/OP_UNUSED_C9FF.S */ 10085/* File: armv5te/unused.S */ 10086 bl common_abort 10087 10088 10089/* ------------------------------ */ 10090 .balign 64 10091.L_OP_UNUSED_CAFF: /* 0x1ca */ 10092/* File: armv5te/OP_UNUSED_CAFF.S */ 10093/* File: armv5te/unused.S */ 10094 bl common_abort 10095 10096 10097/* ------------------------------ */ 10098 .balign 64 10099.L_OP_UNUSED_CBFF: /* 0x1cb */ 10100/* File: armv5te/OP_UNUSED_CBFF.S */ 10101/* File: armv5te/unused.S */ 10102 bl common_abort 10103 10104 10105/* ------------------------------ */ 10106 .balign 64 10107.L_OP_UNUSED_CCFF: /* 0x1cc */ 10108/* File: armv5te/OP_UNUSED_CCFF.S */ 10109/* File: armv5te/unused.S */ 10110 bl common_abort 10111 10112 10113/* ------------------------------ */ 10114 .balign 64 10115.L_OP_UNUSED_CDFF: /* 0x1cd */ 10116/* File: armv5te/OP_UNUSED_CDFF.S */ 10117/* File: armv5te/unused.S */ 10118 bl common_abort 10119 10120 10121/* ------------------------------ */ 10122 .balign 64 10123.L_OP_UNUSED_CEFF: /* 0x1ce */ 10124/* File: armv5te/OP_UNUSED_CEFF.S */ 10125/* File: armv5te/unused.S */ 10126 bl common_abort 10127 10128 10129/* ------------------------------ */ 10130 .balign 64 10131.L_OP_UNUSED_CFFF: /* 0x1cf */ 10132/* File: armv5te/OP_UNUSED_CFFF.S */ 10133/* File: armv5te/unused.S */ 10134 bl common_abort 10135 10136 10137/* ------------------------------ */ 10138 .balign 64 10139.L_OP_UNUSED_D0FF: /* 0x1d0 */ 10140/* File: armv5te/OP_UNUSED_D0FF.S */ 10141/* File: armv5te/unused.S */ 10142 bl common_abort 10143 10144 10145/* ------------------------------ */ 10146 .balign 64 10147.L_OP_UNUSED_D1FF: /* 0x1d1 */ 10148/* File: armv5te/OP_UNUSED_D1FF.S */ 10149/* File: armv5te/unused.S */ 10150 bl common_abort 10151 10152 10153/* ------------------------------ */ 10154 .balign 64 10155.L_OP_UNUSED_D2FF: /* 0x1d2 */ 10156/* File: armv5te/OP_UNUSED_D2FF.S */ 10157/* File: armv5te/unused.S */ 10158 bl common_abort 10159 10160 10161/* ------------------------------ */ 10162 .balign 64 10163.L_OP_UNUSED_D3FF: /* 0x1d3 */ 10164/* File: armv5te/OP_UNUSED_D3FF.S */ 10165/* File: armv5te/unused.S */ 10166 bl common_abort 10167 10168 10169/* ------------------------------ */ 10170 .balign 64 10171.L_OP_UNUSED_D4FF: /* 0x1d4 */ 10172/* File: armv5te/OP_UNUSED_D4FF.S */ 10173/* File: armv5te/unused.S */ 10174 bl common_abort 10175 10176 10177/* ------------------------------ */ 10178 .balign 64 10179.L_OP_UNUSED_D5FF: /* 0x1d5 */ 10180/* File: armv5te/OP_UNUSED_D5FF.S */ 10181/* File: armv5te/unused.S */ 10182 bl common_abort 10183 10184 10185/* ------------------------------ */ 10186 .balign 64 10187.L_OP_UNUSED_D6FF: /* 0x1d6 */ 10188/* File: armv5te/OP_UNUSED_D6FF.S */ 10189/* File: armv5te/unused.S */ 10190 bl common_abort 10191 10192 10193/* ------------------------------ */ 10194 .balign 64 10195.L_OP_UNUSED_D7FF: /* 0x1d7 */ 10196/* File: armv5te/OP_UNUSED_D7FF.S */ 10197/* File: armv5te/unused.S */ 10198 bl common_abort 10199 10200 10201/* ------------------------------ */ 10202 .balign 64 10203.L_OP_UNUSED_D8FF: /* 0x1d8 */ 10204/* File: armv5te/OP_UNUSED_D8FF.S */ 10205/* File: armv5te/unused.S */ 10206 bl common_abort 10207 10208 10209/* ------------------------------ */ 10210 .balign 64 10211.L_OP_UNUSED_D9FF: /* 0x1d9 */ 10212/* File: armv5te/OP_UNUSED_D9FF.S */ 10213/* File: armv5te/unused.S */ 10214 bl common_abort 10215 10216 10217/* ------------------------------ */ 10218 .balign 64 10219.L_OP_UNUSED_DAFF: /* 0x1da */ 10220/* File: armv5te/OP_UNUSED_DAFF.S */ 10221/* File: armv5te/unused.S */ 10222 bl common_abort 10223 10224 10225/* ------------------------------ */ 10226 .balign 64 10227.L_OP_UNUSED_DBFF: /* 0x1db */ 10228/* File: armv5te/OP_UNUSED_DBFF.S */ 10229/* File: armv5te/unused.S */ 10230 bl common_abort 10231 10232 10233/* ------------------------------ */ 10234 .balign 64 10235.L_OP_UNUSED_DCFF: /* 0x1dc */ 10236/* File: armv5te/OP_UNUSED_DCFF.S */ 10237/* File: armv5te/unused.S */ 10238 bl common_abort 10239 10240 10241/* ------------------------------ */ 10242 .balign 64 10243.L_OP_UNUSED_DDFF: /* 0x1dd */ 10244/* File: armv5te/OP_UNUSED_DDFF.S */ 10245/* File: armv5te/unused.S */ 10246 bl common_abort 10247 10248 10249/* ------------------------------ */ 10250 .balign 64 10251.L_OP_UNUSED_DEFF: /* 0x1de */ 10252/* File: armv5te/OP_UNUSED_DEFF.S */ 10253/* File: armv5te/unused.S */ 10254 bl common_abort 10255 10256 10257/* ------------------------------ */ 10258 .balign 64 10259.L_OP_UNUSED_DFFF: /* 0x1df */ 10260/* File: armv5te/OP_UNUSED_DFFF.S */ 10261/* File: armv5te/unused.S */ 10262 bl common_abort 10263 10264 10265/* ------------------------------ */ 10266 .balign 64 10267.L_OP_UNUSED_E0FF: /* 0x1e0 */ 10268/* File: armv5te/OP_UNUSED_E0FF.S */ 10269/* File: armv5te/unused.S */ 10270 bl common_abort 10271 10272 10273/* ------------------------------ */ 10274 .balign 64 10275.L_OP_UNUSED_E1FF: /* 0x1e1 */ 10276/* File: armv5te/OP_UNUSED_E1FF.S */ 10277/* File: armv5te/unused.S */ 10278 bl common_abort 10279 10280 10281/* ------------------------------ */ 10282 .balign 64 10283.L_OP_UNUSED_E2FF: /* 0x1e2 */ 10284/* File: armv5te/OP_UNUSED_E2FF.S */ 10285/* File: armv5te/unused.S */ 10286 bl common_abort 10287 10288 10289/* ------------------------------ */ 10290 .balign 64 10291.L_OP_UNUSED_E3FF: /* 0x1e3 */ 10292/* File: armv5te/OP_UNUSED_E3FF.S */ 10293/* File: armv5te/unused.S */ 10294 bl common_abort 10295 10296 10297/* ------------------------------ */ 10298 .balign 64 10299.L_OP_UNUSED_E4FF: /* 0x1e4 */ 10300/* File: armv5te/OP_UNUSED_E4FF.S */ 10301/* File: armv5te/unused.S */ 10302 bl common_abort 10303 10304 10305/* ------------------------------ */ 10306 .balign 64 10307.L_OP_UNUSED_E5FF: /* 0x1e5 */ 10308/* File: armv5te/OP_UNUSED_E5FF.S */ 10309/* File: armv5te/unused.S */ 10310 bl common_abort 10311 10312 10313/* ------------------------------ */ 10314 .balign 64 10315.L_OP_UNUSED_E6FF: /* 0x1e6 */ 10316/* File: armv5te/OP_UNUSED_E6FF.S */ 10317/* File: armv5te/unused.S */ 10318 bl common_abort 10319 10320 10321/* ------------------------------ */ 10322 .balign 64 10323.L_OP_UNUSED_E7FF: /* 0x1e7 */ 10324/* File: armv5te/OP_UNUSED_E7FF.S */ 10325/* File: armv5te/unused.S */ 10326 bl common_abort 10327 10328 10329/* ------------------------------ */ 10330 .balign 64 10331.L_OP_UNUSED_E8FF: /* 0x1e8 */ 10332/* File: armv5te/OP_UNUSED_E8FF.S */ 10333/* File: armv5te/unused.S */ 10334 bl common_abort 10335 10336 10337/* ------------------------------ */ 10338 .balign 64 10339.L_OP_UNUSED_E9FF: /* 0x1e9 */ 10340/* File: armv5te/OP_UNUSED_E9FF.S */ 10341/* File: armv5te/unused.S */ 10342 bl common_abort 10343 10344 10345/* ------------------------------ */ 10346 .balign 64 10347.L_OP_UNUSED_EAFF: /* 0x1ea */ 10348/* File: armv5te/OP_UNUSED_EAFF.S */ 10349/* File: armv5te/unused.S */ 10350 bl common_abort 10351 10352 10353/* ------------------------------ */ 10354 .balign 64 10355.L_OP_UNUSED_EBFF: /* 0x1eb */ 10356/* File: armv5te/OP_UNUSED_EBFF.S */ 10357/* File: armv5te/unused.S */ 10358 bl common_abort 10359 10360 10361/* ------------------------------ */ 10362 .balign 64 10363.L_OP_UNUSED_ECFF: /* 0x1ec */ 10364/* File: armv5te/OP_UNUSED_ECFF.S */ 10365/* File: armv5te/unused.S */ 10366 bl common_abort 10367 10368 10369/* ------------------------------ */ 10370 .balign 64 10371.L_OP_UNUSED_EDFF: /* 0x1ed */ 10372/* File: armv5te/OP_UNUSED_EDFF.S */ 10373/* File: armv5te/unused.S */ 10374 bl common_abort 10375 10376 10377/* ------------------------------ */ 10378 .balign 64 10379.L_OP_UNUSED_EEFF: /* 0x1ee */ 10380/* File: armv5te/OP_UNUSED_EEFF.S */ 10381/* File: armv5te/unused.S */ 10382 bl common_abort 10383 10384 10385/* ------------------------------ */ 10386 .balign 64 10387.L_OP_UNUSED_EFFF: /* 0x1ef */ 10388/* File: armv5te/OP_UNUSED_EFFF.S */ 10389/* File: armv5te/unused.S */ 10390 bl common_abort 10391 10392 10393/* ------------------------------ */ 10394 .balign 64 10395.L_OP_UNUSED_F0FF: /* 0x1f0 */ 10396/* File: armv5te/OP_UNUSED_F0FF.S */ 10397/* File: armv5te/unused.S */ 10398 bl common_abort 10399 10400 10401/* ------------------------------ */ 10402 .balign 64 10403.L_OP_UNUSED_F1FF: /* 0x1f1 */ 10404/* File: armv5te/OP_UNUSED_F1FF.S */ 10405/* File: armv5te/unused.S */ 10406 bl common_abort 10407 10408 10409/* ------------------------------ */ 10410 .balign 64 10411.L_OP_UNUSED_F2FF: /* 0x1f2 */ 10412/* File: armv5te/OP_UNUSED_F2FF.S */ 10413/* File: armv5te/unused.S */ 10414 bl common_abort 10415 10416 10417/* ------------------------------ */ 10418 .balign 64 10419.L_OP_UNUSED_F3FF: /* 0x1f3 */ 10420/* File: armv5te/OP_UNUSED_F3FF.S */ 10421/* File: armv5te/unused.S */ 10422 bl common_abort 10423 10424 10425/* ------------------------------ */ 10426 .balign 64 10427.L_OP_UNUSED_F4FF: /* 0x1f4 */ 10428/* File: armv5te/OP_UNUSED_F4FF.S */ 10429/* File: armv5te/unused.S */ 10430 bl common_abort 10431 10432 10433/* ------------------------------ */ 10434 .balign 64 10435.L_OP_UNUSED_F5FF: /* 0x1f5 */ 10436/* File: armv5te/OP_UNUSED_F5FF.S */ 10437/* File: armv5te/unused.S */ 10438 bl common_abort 10439 10440 10441/* ------------------------------ */ 10442 .balign 64 10443.L_OP_UNUSED_F6FF: /* 0x1f6 */ 10444/* File: armv5te/OP_UNUSED_F6FF.S */ 10445/* File: armv5te/unused.S */ 10446 bl common_abort 10447 10448 10449/* ------------------------------ */ 10450 .balign 64 10451.L_OP_UNUSED_F7FF: /* 0x1f7 */ 10452/* File: armv5te/OP_UNUSED_F7FF.S */ 10453/* File: armv5te/unused.S */ 10454 bl common_abort 10455 10456 10457/* ------------------------------ */ 10458 .balign 64 10459.L_OP_UNUSED_F8FF: /* 0x1f8 */ 10460/* File: armv5te/OP_UNUSED_F8FF.S */ 10461/* File: armv5te/unused.S */ 10462 bl common_abort 10463 10464 10465/* ------------------------------ */ 10466 .balign 64 10467.L_OP_UNUSED_F9FF: /* 0x1f9 */ 10468/* File: armv5te/OP_UNUSED_F9FF.S */ 10469/* File: armv5te/unused.S */ 10470 bl common_abort 10471 10472 10473/* ------------------------------ */ 10474 .balign 64 10475.L_OP_UNUSED_FAFF: /* 0x1fa */ 10476/* File: armv5te/OP_UNUSED_FAFF.S */ 10477/* File: armv5te/unused.S */ 10478 bl common_abort 10479 10480 10481/* ------------------------------ */ 10482 .balign 64 10483.L_OP_UNUSED_FBFF: /* 0x1fb */ 10484/* File: armv5te/OP_UNUSED_FBFF.S */ 10485/* File: armv5te/unused.S */ 10486 bl common_abort 10487 10488 10489/* ------------------------------ */ 10490 .balign 64 10491.L_OP_UNUSED_FCFF: /* 0x1fc */ 10492/* File: armv5te/OP_UNUSED_FCFF.S */ 10493/* File: armv5te/unused.S */ 10494 bl common_abort 10495 10496 10497/* ------------------------------ */ 10498 .balign 64 10499.L_OP_UNUSED_FDFF: /* 0x1fd */ 10500/* File: armv5te/OP_UNUSED_FDFF.S */ 10501/* File: armv5te/unused.S */ 10502 bl common_abort 10503 10504 10505/* ------------------------------ */ 10506 .balign 64 10507.L_OP_UNUSED_FEFF: /* 0x1fe */ 10508/* File: armv5te/OP_UNUSED_FEFF.S */ 10509/* File: armv5te/unused.S */ 10510 bl common_abort 10511 10512 10513/* ------------------------------ */ 10514 .balign 64 10515.L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 10516/* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */ 10517 /* 10518 * Handle a jumbo throw-verification-error instruction. This throws an 10519 * exception for an error discovered during verification. The 10520 * exception is indicated by BBBB, with some detail provided by AAAAAAAA. 10521 */ 10522 /* exop BBBB, Class@AAAAAAAA */ 10523 FETCH(r1, 1) @ r1<- aaaa (lo) 10524 FETCH(r2, 2) @ r2<- AAAA (hi) 10525 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10526 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa 10527 EXPORT_PC() @ export the PC 10528 FETCH(r1, 3) @ r1<- BBBB 10529 bl dvmThrowVerificationError @ always throws 10530 b common_exceptionThrown @ handle exception 10531 10532 .balign 64 10533 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 10534 .global dvmAsmInstructionEnd 10535dvmAsmInstructionEnd: 10536 10537/* 10538 * =========================================================================== 10539 * Sister implementations 10540 * =========================================================================== 10541 */ 10542 .global dvmAsmSisterStart 10543 .type dvmAsmSisterStart, %function 10544 .text 10545 .balign 4 10546dvmAsmSisterStart: 10547 10548/* continuation for OP_CONST_STRING */ 10549 10550 /* 10551 * Continuation if the String has not yet been resolved. 10552 * r1: BBBB (String ref) 10553 * r9: target register 10554 */ 10555.LOP_CONST_STRING_resolve: 10556 EXPORT_PC() 10557 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10558 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10559 bl dvmResolveString @ r0<- String reference 10560 cmp r0, #0 @ failed? 10561 beq common_exceptionThrown @ yup, handle the exception 10562 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10563 GET_INST_OPCODE(ip) @ extract opcode from rINST 10564 SET_VREG(r0, r9) @ vAA<- r0 10565 GOTO_OPCODE(ip) @ jump to next instruction 10566 10567/* continuation for OP_CONST_STRING_JUMBO */ 10568 10569 /* 10570 * Continuation if the String has not yet been resolved. 10571 * r1: BBBBBBBB (String ref) 10572 * r9: target register 10573 */ 10574.LOP_CONST_STRING_JUMBO_resolve: 10575 EXPORT_PC() 10576 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10577 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10578 bl dvmResolveString @ r0<- String reference 10579 cmp r0, #0 @ failed? 10580 beq common_exceptionThrown @ yup, handle the exception 10581 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10582 GET_INST_OPCODE(ip) @ extract opcode from rINST 10583 SET_VREG(r0, r9) @ vAA<- r0 10584 GOTO_OPCODE(ip) @ jump to next instruction 10585 10586/* continuation for OP_CONST_CLASS */ 10587 10588 /* 10589 * Continuation if the Class has not yet been resolved. 10590 * r1: BBBB (Class ref) 10591 * r9: target register 10592 */ 10593.LOP_CONST_CLASS_resolve: 10594 EXPORT_PC() 10595 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10596 mov r2, #1 @ r2<- true 10597 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10598 bl dvmResolveClass @ r0<- Class reference 10599 cmp r0, #0 @ failed? 10600 beq common_exceptionThrown @ yup, handle the exception 10601 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10602 GET_INST_OPCODE(ip) @ extract opcode from rINST 10603 SET_VREG(r0, r9) @ vAA<- r0 10604 GOTO_OPCODE(ip) @ jump to next instruction 10605 10606/* continuation for OP_CHECK_CAST */ 10607 10608 /* 10609 * Trivial test failed, need to perform full check. This is common. 10610 * r0 holds obj->clazz 10611 * r1 holds desired class resolved from BBBB 10612 * r9 holds object 10613 */ 10614.LOP_CHECK_CAST_fullcheck: 10615 mov r10, r1 @ avoid ClassObject getting clobbered 10616 bl dvmInstanceofNonTrivial @ r0<- boolean result 10617 cmp r0, #0 @ failed? 10618 bne .LOP_CHECK_CAST_okay @ no, success 10619 10620 @ A cast has failed. We need to throw a ClassCastException. 10621 EXPORT_PC() @ about to throw 10622 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 10623 mov r1, r10 @ r1<- desired class 10624 bl dvmThrowClassCastException 10625 b common_exceptionThrown 10626 10627 /* 10628 * Resolution required. This is the least-likely path. 10629 * 10630 * r2 holds BBBB 10631 * r9 holds object 10632 */ 10633.LOP_CHECK_CAST_resolve: 10634 EXPORT_PC() @ resolve() could throw 10635 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10636 mov r1, r2 @ r1<- BBBB 10637 mov r2, #0 @ r2<- false 10638 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10639 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10640 cmp r0, #0 @ got null? 10641 beq common_exceptionThrown @ yes, handle exception 10642 mov r1, r0 @ r1<- class resolved from BBB 10643 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 10644 b .LOP_CHECK_CAST_resolved @ pick up where we left off 10645 10646/* continuation for OP_INSTANCE_OF */ 10647 10648 /* 10649 * Trivial test failed, need to perform full check. This is common. 10650 * r0 holds obj->clazz 10651 * r1 holds class resolved from BBBB 10652 * r9 holds A 10653 */ 10654.LOP_INSTANCE_OF_fullcheck: 10655 bl dvmInstanceofNonTrivial @ r0<- boolean result 10656 @ fall through to OP_INSTANCE_OF_store 10657 10658 /* 10659 * r0 holds boolean result 10660 * r9 holds A 10661 */ 10662.LOP_INSTANCE_OF_store: 10663 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10664 SET_VREG(r0, r9) @ vA<- r0 10665 GET_INST_OPCODE(ip) @ extract opcode from rINST 10666 GOTO_OPCODE(ip) @ jump to next instruction 10667 10668 /* 10669 * Trivial test succeeded, save and bail. 10670 * r9 holds A 10671 */ 10672.LOP_INSTANCE_OF_trivial: 10673 mov r0, #1 @ indicate success 10674 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 10675 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10676 SET_VREG(r0, r9) @ vA<- r0 10677 GET_INST_OPCODE(ip) @ extract opcode from rINST 10678 GOTO_OPCODE(ip) @ jump to next instruction 10679 10680 /* 10681 * Resolution required. This is the least-likely path. 10682 * 10683 * r3 holds BBBB 10684 * r9 holds A 10685 */ 10686.LOP_INSTANCE_OF_resolve: 10687 EXPORT_PC() @ resolve() could throw 10688 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10689 mov r1, r3 @ r1<- BBBB 10690 mov r2, #1 @ r2<- true 10691 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10692 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10693 cmp r0, #0 @ got null? 10694 beq common_exceptionThrown @ yes, handle exception 10695 mov r1, r0 @ r1<- class resolved from BBB 10696 mov r3, rINST, lsr #12 @ r3<- B 10697 GET_VREG(r0, r3) @ r0<- vB (object) 10698 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 10699 b .LOP_INSTANCE_OF_resolved @ pick up where we left off 10700 10701/* continuation for OP_NEW_INSTANCE */ 10702 10703 .balign 32 @ minimize cache lines 10704.LOP_NEW_INSTANCE_finish: @ r0=new object 10705 mov r3, rINST, lsr #8 @ r3<- AA 10706 cmp r0, #0 @ failed? 10707 beq common_exceptionThrown @ yes, handle the exception 10708 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10709 GET_INST_OPCODE(ip) @ extract opcode from rINST 10710 SET_VREG(r0, r3) @ vAA<- r0 10711 GOTO_OPCODE(ip) @ jump to next instruction 10712 10713 /* 10714 * Class initialization required. 10715 * 10716 * r0 holds class object 10717 */ 10718.LOP_NEW_INSTANCE_needinit: 10719 mov r9, r0 @ save r0 10720 bl dvmInitClass @ initialize class 10721 cmp r0, #0 @ check boolean result 10722 mov r0, r9 @ restore r0 10723 bne .LOP_NEW_INSTANCE_initialized @ success, continue 10724 b common_exceptionThrown @ failed, deal with init exception 10725 10726 /* 10727 * Resolution required. This is the least-likely path. 10728 * 10729 * r1 holds BBBB 10730 */ 10731.LOP_NEW_INSTANCE_resolve: 10732 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10733 mov r2, #0 @ r2<- false 10734 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10735 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10736 cmp r0, #0 @ got null? 10737 bne .LOP_NEW_INSTANCE_resolved @ no, continue 10738 b common_exceptionThrown @ yes, handle exception 10739 10740/* continuation for OP_NEW_ARRAY */ 10741 10742 10743 /* 10744 * Resolve class. (This is an uncommon case.) 10745 * 10746 * r1 holds array length 10747 * r2 holds class ref CCCC 10748 */ 10749.LOP_NEW_ARRAY_resolve: 10750 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10751 mov r9, r1 @ r9<- length (save) 10752 mov r1, r2 @ r1<- CCCC 10753 mov r2, #0 @ r2<- false 10754 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10755 bl dvmResolveClass @ r0<- call(clazz, ref) 10756 cmp r0, #0 @ got null? 10757 mov r1, r9 @ r1<- length (restore) 10758 beq common_exceptionThrown @ yes, handle exception 10759 @ fall through to OP_NEW_ARRAY_finish 10760 10761 /* 10762 * Finish allocation. 10763 * 10764 * r0 holds class 10765 * r1 holds array length 10766 */ 10767.LOP_NEW_ARRAY_finish: 10768 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 10769 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 10770 cmp r0, #0 @ failed? 10771 mov r2, rINST, lsr #8 @ r2<- A+ 10772 beq common_exceptionThrown @ yes, handle the exception 10773 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10774 and r2, r2, #15 @ r2<- A 10775 GET_INST_OPCODE(ip) @ extract opcode from rINST 10776 SET_VREG(r0, r2) @ vA<- r0 10777 GOTO_OPCODE(ip) @ jump to next instruction 10778 10779/* continuation for OP_FILLED_NEW_ARRAY */ 10780 10781 /* 10782 * On entry: 10783 * r0 holds array class 10784 * r10 holds AA or BA 10785 */ 10786.LOP_FILLED_NEW_ARRAY_continue: 10787 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 10788 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 10789 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 10790 .if 0 10791 mov r1, r10 @ r1<- AA (length) 10792 .else 10793 mov r1, r10, lsr #4 @ r1<- B (length) 10794 .endif 10795 cmp rINST, #'I' @ array of ints? 10796 cmpne rINST, #'L' @ array of objects? 10797 cmpne rINST, #'[' @ array of arrays? 10798 mov r9, r1 @ save length in r9 10799 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 10800 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 10801 cmp r0, #0 @ null return? 10802 beq common_exceptionThrown @ alloc failed, handle exception 10803 10804 FETCH(r1, 2) @ r1<- FEDC or CCCC 10805 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 10806 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 10807 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 10808 subs r9, r9, #1 @ length--, check for neg 10809 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 10810 bmi 2f @ was zero, bail 10811 10812 @ copy values from registers into the array 10813 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 10814 .if 0 10815 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 108161: ldr r3, [r2], #4 @ r3<- *r2++ 10817 subs r9, r9, #1 @ count-- 10818 str r3, [r0], #4 @ *contents++ = vX 10819 bpl 1b 10820 @ continue at 2 10821 .else 10822 cmp r9, #4 @ length was initially 5? 10823 and r2, r10, #15 @ r2<- A 10824 bne 1f @ <= 4 args, branch 10825 GET_VREG(r3, r2) @ r3<- vA 10826 sub r9, r9, #1 @ count-- 10827 str r3, [r0, #16] @ contents[4] = vA 108281: and r2, r1, #15 @ r2<- F/E/D/C 10829 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 10830 mov r1, r1, lsr #4 @ r1<- next reg in low 4 10831 subs r9, r9, #1 @ count-- 10832 str r3, [r0], #4 @ *contents++ = vX 10833 bpl 1b 10834 @ continue at 2 10835 .endif 10836 108372: 10838 ldr r0, [rSELF, #offThread_retval] @ r0<- object 10839 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 10840 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 10841 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 10842 cmp r1, #'I' @ Is int array? 10843 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 10844 GOTO_OPCODE(ip) @ execute it 10845 10846 /* 10847 * Throw an exception indicating that we have not implemented this 10848 * mode of filled-new-array. 10849 */ 10850.LOP_FILLED_NEW_ARRAY_notimpl: 10851 ldr r0, .L_strFilledNewArrayNotImpl 10852 bl dvmThrowInternalError 10853 b common_exceptionThrown 10854 10855 .if (!0) @ define in one or the other, not both 10856.L_strFilledNewArrayNotImpl: 10857 .word .LstrFilledNewArrayNotImpl 10858 .endif 10859 10860/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 10861 10862 /* 10863 * On entry: 10864 * r0 holds array class 10865 * r10 holds AA or BA 10866 */ 10867.LOP_FILLED_NEW_ARRAY_RANGE_continue: 10868 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 10869 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 10870 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 10871 .if 1 10872 mov r1, r10 @ r1<- AA (length) 10873 .else 10874 mov r1, r10, lsr #4 @ r1<- B (length) 10875 .endif 10876 cmp rINST, #'I' @ array of ints? 10877 cmpne rINST, #'L' @ array of objects? 10878 cmpne rINST, #'[' @ array of arrays? 10879 mov r9, r1 @ save length in r9 10880 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 10881 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 10882 cmp r0, #0 @ null return? 10883 beq common_exceptionThrown @ alloc failed, handle exception 10884 10885 FETCH(r1, 2) @ r1<- FEDC or CCCC 10886 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 10887 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 10888 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 10889 subs r9, r9, #1 @ length--, check for neg 10890 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 10891 bmi 2f @ was zero, bail 10892 10893 @ copy values from registers into the array 10894 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 10895 .if 1 10896 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 108971: ldr r3, [r2], #4 @ r3<- *r2++ 10898 subs r9, r9, #1 @ count-- 10899 str r3, [r0], #4 @ *contents++ = vX 10900 bpl 1b 10901 @ continue at 2 10902 .else 10903 cmp r9, #4 @ length was initially 5? 10904 and r2, r10, #15 @ r2<- A 10905 bne 1f @ <= 4 args, branch 10906 GET_VREG(r3, r2) @ r3<- vA 10907 sub r9, r9, #1 @ count-- 10908 str r3, [r0, #16] @ contents[4] = vA 109091: and r2, r1, #15 @ r2<- F/E/D/C 10910 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 10911 mov r1, r1, lsr #4 @ r1<- next reg in low 4 10912 subs r9, r9, #1 @ count-- 10913 str r3, [r0], #4 @ *contents++ = vX 10914 bpl 1b 10915 @ continue at 2 10916 .endif 10917 109182: 10919 ldr r0, [rSELF, #offThread_retval] @ r0<- object 10920 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 10921 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 10922 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 10923 cmp r1, #'I' @ Is int array? 10924 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 10925 GOTO_OPCODE(ip) @ execute it 10926 10927 /* 10928 * Throw an exception indicating that we have not implemented this 10929 * mode of filled-new-array. 10930 */ 10931.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 10932 ldr r0, .L_strFilledNewArrayNotImpl 10933 bl dvmThrowInternalError 10934 b common_exceptionThrown 10935 10936 .if (!1) @ define in one or the other, not both 10937.L_strFilledNewArrayNotImpl: 10938 .word .LstrFilledNewArrayNotImpl 10939 .endif 10940 10941/* continuation for OP_CMPL_FLOAT */ 10942.LOP_CMPL_FLOAT_finish: 10943 SET_VREG(r0, r9) @ vAA<- r0 10944 GOTO_OPCODE(ip) @ jump to next instruction 10945 10946/* continuation for OP_CMPG_FLOAT */ 10947.LOP_CMPG_FLOAT_finish: 10948 SET_VREG(r0, r9) @ vAA<- r0 10949 GOTO_OPCODE(ip) @ jump to next instruction 10950 10951/* continuation for OP_CMPL_DOUBLE */ 10952.LOP_CMPL_DOUBLE_finish: 10953 SET_VREG(r0, r9) @ vAA<- r0 10954 GOTO_OPCODE(ip) @ jump to next instruction 10955 10956/* continuation for OP_CMPG_DOUBLE */ 10957.LOP_CMPG_DOUBLE_finish: 10958 SET_VREG(r0, r9) @ vAA<- r0 10959 GOTO_OPCODE(ip) @ jump to next instruction 10960 10961/* continuation for OP_CMP_LONG */ 10962 10963.LOP_CMP_LONG_less: 10964 mvn r1, #0 @ r1<- -1 10965 @ Want to cond code the next mov so we can avoid branch, but don't see it; 10966 @ instead, we just replicate the tail end. 10967 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10968 SET_VREG(r1, r9) @ vAA<- r1 10969 GET_INST_OPCODE(ip) @ extract opcode from rINST 10970 GOTO_OPCODE(ip) @ jump to next instruction 10971 10972.LOP_CMP_LONG_greater: 10973 mov r1, #1 @ r1<- 1 10974 @ fall through to _finish 10975 10976.LOP_CMP_LONG_finish: 10977 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10978 SET_VREG(r1, r9) @ vAA<- r1 10979 GET_INST_OPCODE(ip) @ extract opcode from rINST 10980 GOTO_OPCODE(ip) @ jump to next instruction 10981 10982/* continuation for OP_AGET_WIDE */ 10983 10984.LOP_AGET_WIDE_finish: 10985 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10986 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 10987 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 10988 GET_INST_OPCODE(ip) @ extract opcode from rINST 10989 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 10990 GOTO_OPCODE(ip) @ jump to next instruction 10991 10992/* continuation for OP_APUT_WIDE */ 10993 10994.LOP_APUT_WIDE_finish: 10995 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10996 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 10997 GET_INST_OPCODE(ip) @ extract opcode from rINST 10998 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 10999 GOTO_OPCODE(ip) @ jump to next instruction 11000 11001/* continuation for OP_APUT_OBJECT */ 11002 /* 11003 * On entry: 11004 * rINST = vBB (arrayObj) 11005 * r9 = vAA (obj) 11006 * r10 = offset into array (vBB + vCC * width) 11007 */ 11008.LOP_APUT_OBJECT_finish: 11009 cmp r9, #0 @ storing null reference? 11010 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 11011 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 11012 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz 11013 bl dvmCanPutArrayElement @ test object type vs. array type 11014 cmp r0, #0 @ okay? 11015 beq .LOP_APUT_OBJECT_throw @ no 11016 mov r1, rINST @ r1<- arrayObj 11017 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11018 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base 11019 add r10, #offArrayObject_contents @ r0<- pointer to slot 11020 GET_INST_OPCODE(ip) @ extract opcode from rINST 11021 str r9, [r10] @ vBB[vCC]<- vAA 11022 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head 11023 GOTO_OPCODE(ip) @ jump to next instruction 11024.LOP_APUT_OBJECT_skip_check: 11025 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11026 GET_INST_OPCODE(ip) @ extract opcode from rINST 11027 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 11028 GOTO_OPCODE(ip) @ jump to next instruction 11029.LOP_APUT_OBJECT_throw: 11030 @ The types don't match. We need to throw an ArrayStoreException. 11031 ldr r0, [r9, #offObject_clazz] 11032 ldr r1, [rINST, #offObject_clazz] 11033 EXPORT_PC() 11034 bl dvmThrowArrayStoreException 11035 b common_exceptionThrown 11036 11037/* continuation for OP_IGET */ 11038 11039 /* 11040 * Currently: 11041 * r0 holds resolved field 11042 * r9 holds object 11043 */ 11044.LOP_IGET_finish: 11045 @bl common_squeak0 11046 cmp r9, #0 @ check object for null 11047 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11048 beq common_errNullObject @ object was null 11049 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11050 ubfx r2, rINST, #8, #4 @ r2<- A 11051 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11052 GET_INST_OPCODE(ip) @ extract opcode from rINST 11053 SET_VREG(r0, r2) @ fp[A]<- r0 11054 GOTO_OPCODE(ip) @ jump to next instruction 11055 11056/* continuation for OP_IGET_WIDE */ 11057 11058 /* 11059 * Currently: 11060 * r0 holds resolved field 11061 * r9 holds object 11062 */ 11063.LOP_IGET_WIDE_finish: 11064 cmp r9, #0 @ check object for null 11065 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11066 beq common_errNullObject @ object was null 11067 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11068 ubfx r2, rINST, #8, #4 @ r2<- A 11069 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11070 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11071 GET_INST_OPCODE(ip) @ extract opcode from rINST 11072 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11073 GOTO_OPCODE(ip) @ jump to next instruction 11074 11075/* continuation for OP_IGET_OBJECT */ 11076 11077 /* 11078 * Currently: 11079 * r0 holds resolved field 11080 * r9 holds object 11081 */ 11082.LOP_IGET_OBJECT_finish: 11083 @bl common_squeak0 11084 cmp r9, #0 @ check object for null 11085 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11086 beq common_errNullObject @ object was null 11087 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11088 @ no-op @ acquiring load 11089 mov r2, rINST, lsr #8 @ r2<- A+ 11090 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11091 and r2, r2, #15 @ r2<- A 11092 GET_INST_OPCODE(ip) @ extract opcode from rINST 11093 SET_VREG(r0, r2) @ fp[A]<- r0 11094 GOTO_OPCODE(ip) @ jump to next instruction 11095 11096/* continuation for OP_IGET_BOOLEAN */ 11097 11098 /* 11099 * Currently: 11100 * r0 holds resolved field 11101 * r9 holds object 11102 */ 11103.LOP_IGET_BOOLEAN_finish: 11104 @bl common_squeak1 11105 cmp r9, #0 @ check object for null 11106 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11107 beq common_errNullObject @ object was null 11108 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11109 @ no-op @ acquiring load 11110 mov r2, rINST, lsr #8 @ r2<- A+ 11111 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11112 and r2, r2, #15 @ r2<- A 11113 GET_INST_OPCODE(ip) @ extract opcode from rINST 11114 SET_VREG(r0, r2) @ fp[A]<- r0 11115 GOTO_OPCODE(ip) @ jump to next instruction 11116 11117/* continuation for OP_IGET_BYTE */ 11118 11119 /* 11120 * Currently: 11121 * r0 holds resolved field 11122 * r9 holds object 11123 */ 11124.LOP_IGET_BYTE_finish: 11125 @bl common_squeak2 11126 cmp r9, #0 @ check object for null 11127 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11128 beq common_errNullObject @ object was null 11129 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11130 @ no-op @ acquiring load 11131 mov r2, rINST, lsr #8 @ r2<- A+ 11132 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11133 and r2, r2, #15 @ r2<- A 11134 GET_INST_OPCODE(ip) @ extract opcode from rINST 11135 SET_VREG(r0, r2) @ fp[A]<- r0 11136 GOTO_OPCODE(ip) @ jump to next instruction 11137 11138/* continuation for OP_IGET_CHAR */ 11139 11140 /* 11141 * Currently: 11142 * r0 holds resolved field 11143 * r9 holds object 11144 */ 11145.LOP_IGET_CHAR_finish: 11146 @bl common_squeak3 11147 cmp r9, #0 @ check object for null 11148 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11149 beq common_errNullObject @ object was null 11150 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11151 @ no-op @ acquiring load 11152 mov r2, rINST, lsr #8 @ r2<- A+ 11153 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11154 and r2, r2, #15 @ r2<- A 11155 GET_INST_OPCODE(ip) @ extract opcode from rINST 11156 SET_VREG(r0, r2) @ fp[A]<- r0 11157 GOTO_OPCODE(ip) @ jump to next instruction 11158 11159/* continuation for OP_IGET_SHORT */ 11160 11161 /* 11162 * Currently: 11163 * r0 holds resolved field 11164 * r9 holds object 11165 */ 11166.LOP_IGET_SHORT_finish: 11167 @bl common_squeak4 11168 cmp r9, #0 @ check object for null 11169 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11170 beq common_errNullObject @ object was null 11171 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11172 @ no-op @ acquiring load 11173 mov r2, rINST, lsr #8 @ r2<- A+ 11174 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11175 and r2, r2, #15 @ r2<- A 11176 GET_INST_OPCODE(ip) @ extract opcode from rINST 11177 SET_VREG(r0, r2) @ fp[A]<- r0 11178 GOTO_OPCODE(ip) @ jump to next instruction 11179 11180/* continuation for OP_IPUT */ 11181 11182 /* 11183 * Currently: 11184 * r0 holds resolved field 11185 * r9 holds object 11186 */ 11187.LOP_IPUT_finish: 11188 @bl common_squeak0 11189 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11190 ubfx r1, rINST, #8, #4 @ r1<- A 11191 cmp r9, #0 @ check object for null 11192 GET_VREG(r0, r1) @ r0<- fp[A] 11193 beq common_errNullObject @ object was null 11194 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11195 GET_INST_OPCODE(ip) @ extract opcode from rINST 11196 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11197 GOTO_OPCODE(ip) @ jump to next instruction 11198 11199/* continuation for OP_IPUT_WIDE */ 11200 11201 /* 11202 * Currently: 11203 * r0 holds resolved field 11204 * r9 holds object 11205 */ 11206.LOP_IPUT_WIDE_finish: 11207 ubfx r2, rINST, #8, #4 @ r2<- A 11208 cmp r9, #0 @ check object for null 11209 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11210 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 11211 beq common_errNullObject @ object was null 11212 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11213 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 11214 GET_INST_OPCODE(ip) @ extract opcode from rINST 11215 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0 11216 GOTO_OPCODE(ip) @ jump to next instruction 11217 11218/* continuation for OP_IPUT_OBJECT */ 11219 11220 /* 11221 * Currently: 11222 * r0 holds resolved field 11223 * r9 holds object 11224 */ 11225.LOP_IPUT_OBJECT_finish: 11226 @bl common_squeak0 11227 mov r1, rINST, lsr #8 @ r1<- A+ 11228 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11229 and r1, r1, #15 @ r1<- A 11230 cmp r9, #0 @ check object for null 11231 GET_VREG(r0, r1) @ r0<- fp[A] 11232 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11233 beq common_errNullObject @ object was null 11234 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11235 GET_INST_OPCODE(ip) @ extract opcode from rINST 11236 @ no-op @ releasing store 11237 str r0, [r9, r3] @ obj.field (32 bits)<- r0 11238 cmp r0, #0 @ stored a null reference? 11239 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 11240 GOTO_OPCODE(ip) @ jump to next instruction 11241 11242/* continuation for OP_IPUT_BOOLEAN */ 11243 11244 /* 11245 * Currently: 11246 * r0 holds resolved field 11247 * r9 holds object 11248 */ 11249.LOP_IPUT_BOOLEAN_finish: 11250 @bl common_squeak1 11251 mov r1, rINST, lsr #8 @ r1<- A+ 11252 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11253 and r1, r1, #15 @ r1<- A 11254 cmp r9, #0 @ check object for null 11255 GET_VREG(r0, r1) @ r0<- fp[A] 11256 beq common_errNullObject @ object was null 11257 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11258 GET_INST_OPCODE(ip) @ extract opcode from rINST 11259 @ no-op @ releasing store 11260 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11261 GOTO_OPCODE(ip) @ jump to next instruction 11262 11263/* continuation for OP_IPUT_BYTE */ 11264 11265 /* 11266 * Currently: 11267 * r0 holds resolved field 11268 * r9 holds object 11269 */ 11270.LOP_IPUT_BYTE_finish: 11271 @bl common_squeak2 11272 mov r1, rINST, lsr #8 @ r1<- A+ 11273 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11274 and r1, r1, #15 @ r1<- A 11275 cmp r9, #0 @ check object for null 11276 GET_VREG(r0, r1) @ r0<- fp[A] 11277 beq common_errNullObject @ object was null 11278 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11279 GET_INST_OPCODE(ip) @ extract opcode from rINST 11280 @ no-op @ releasing store 11281 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11282 GOTO_OPCODE(ip) @ jump to next instruction 11283 11284/* continuation for OP_IPUT_CHAR */ 11285 11286 /* 11287 * Currently: 11288 * r0 holds resolved field 11289 * r9 holds object 11290 */ 11291.LOP_IPUT_CHAR_finish: 11292 @bl common_squeak3 11293 mov r1, rINST, lsr #8 @ r1<- A+ 11294 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11295 and r1, r1, #15 @ r1<- A 11296 cmp r9, #0 @ check object for null 11297 GET_VREG(r0, r1) @ r0<- fp[A] 11298 beq common_errNullObject @ object was null 11299 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11300 GET_INST_OPCODE(ip) @ extract opcode from rINST 11301 @ no-op @ releasing store 11302 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11303 GOTO_OPCODE(ip) @ jump to next instruction 11304 11305/* continuation for OP_IPUT_SHORT */ 11306 11307 /* 11308 * Currently: 11309 * r0 holds resolved field 11310 * r9 holds object 11311 */ 11312.LOP_IPUT_SHORT_finish: 11313 @bl common_squeak4 11314 mov r1, rINST, lsr #8 @ r1<- A+ 11315 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11316 and r1, r1, #15 @ r1<- A 11317 cmp r9, #0 @ check object for null 11318 GET_VREG(r0, r1) @ r0<- fp[A] 11319 beq common_errNullObject @ object was null 11320 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11321 GET_INST_OPCODE(ip) @ extract opcode from rINST 11322 @ no-op @ releasing store 11323 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11324 GOTO_OPCODE(ip) @ jump to next instruction 11325 11326/* continuation for OP_SGET */ 11327 11328 /* 11329 * Continuation if the field has not yet been resolved. 11330 * r1: BBBB field ref 11331 */ 11332.LOP_SGET_resolve: 11333 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11334 EXPORT_PC() @ resolve() could throw, so export now 11335 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11336 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11337 cmp r0, #0 @ success? 11338 bne .LOP_SGET_finish @ yes, finish 11339 b common_exceptionThrown @ no, handle exception 11340 11341/* continuation for OP_SGET_WIDE */ 11342 11343 /* 11344 * Continuation if the field has not yet been resolved. 11345 * r1: BBBB field ref 11346 * 11347 * Returns StaticField pointer in r0. 11348 */ 11349.LOP_SGET_WIDE_resolve: 11350 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11351 EXPORT_PC() @ resolve() could throw, so export now 11352 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11353 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11354 cmp r0, #0 @ success? 11355 bne .LOP_SGET_WIDE_finish @ yes, finish 11356 b common_exceptionThrown @ no, handle exception 11357 11358/* continuation for OP_SGET_OBJECT */ 11359 11360 /* 11361 * Continuation if the field has not yet been resolved. 11362 * r1: BBBB field ref 11363 */ 11364.LOP_SGET_OBJECT_resolve: 11365 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11366 EXPORT_PC() @ resolve() could throw, so export now 11367 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11368 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11369 cmp r0, #0 @ success? 11370 bne .LOP_SGET_OBJECT_finish @ yes, finish 11371 b common_exceptionThrown @ no, handle exception 11372 11373/* continuation for OP_SGET_BOOLEAN */ 11374 11375 /* 11376 * Continuation if the field has not yet been resolved. 11377 * r1: BBBB field ref 11378 */ 11379.LOP_SGET_BOOLEAN_resolve: 11380 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11381 EXPORT_PC() @ resolve() could throw, so export now 11382 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11383 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11384 cmp r0, #0 @ success? 11385 bne .LOP_SGET_BOOLEAN_finish @ yes, finish 11386 b common_exceptionThrown @ no, handle exception 11387 11388/* continuation for OP_SGET_BYTE */ 11389 11390 /* 11391 * Continuation if the field has not yet been resolved. 11392 * r1: BBBB field ref 11393 */ 11394.LOP_SGET_BYTE_resolve: 11395 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11396 EXPORT_PC() @ resolve() could throw, so export now 11397 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11398 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11399 cmp r0, #0 @ success? 11400 bne .LOP_SGET_BYTE_finish @ yes, finish 11401 b common_exceptionThrown @ no, handle exception 11402 11403/* continuation for OP_SGET_CHAR */ 11404 11405 /* 11406 * Continuation if the field has not yet been resolved. 11407 * r1: BBBB field ref 11408 */ 11409.LOP_SGET_CHAR_resolve: 11410 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11411 EXPORT_PC() @ resolve() could throw, so export now 11412 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11413 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11414 cmp r0, #0 @ success? 11415 bne .LOP_SGET_CHAR_finish @ yes, finish 11416 b common_exceptionThrown @ no, handle exception 11417 11418/* continuation for OP_SGET_SHORT */ 11419 11420 /* 11421 * Continuation if the field has not yet been resolved. 11422 * r1: BBBB field ref 11423 */ 11424.LOP_SGET_SHORT_resolve: 11425 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11426 EXPORT_PC() @ resolve() could throw, so export now 11427 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11428 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11429 cmp r0, #0 @ success? 11430 bne .LOP_SGET_SHORT_finish @ yes, finish 11431 b common_exceptionThrown @ no, handle exception 11432 11433/* continuation for OP_SPUT */ 11434 11435 /* 11436 * Continuation if the field has not yet been resolved. 11437 * r1: BBBB field ref 11438 */ 11439.LOP_SPUT_resolve: 11440 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11441 EXPORT_PC() @ resolve() could throw, so export now 11442 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11443 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11444 cmp r0, #0 @ success? 11445 bne .LOP_SPUT_finish @ yes, finish 11446 b common_exceptionThrown @ no, handle exception 11447 11448/* continuation for OP_SPUT_WIDE */ 11449 11450 /* 11451 * Continuation if the field has not yet been resolved. 11452 * r1: BBBB field ref 11453 * r9: &fp[AA] 11454 * 11455 * Returns StaticField pointer in r2. 11456 */ 11457.LOP_SPUT_WIDE_resolve: 11458 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11459 EXPORT_PC() @ resolve() could throw, so export now 11460 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11461 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11462 cmp r0, #0 @ success? 11463 mov r2, r0 @ copy to r2 11464 bne .LOP_SPUT_WIDE_finish @ yes, finish 11465 b common_exceptionThrown @ no, handle exception 11466 11467/* continuation for OP_SPUT_OBJECT */ 11468.LOP_SPUT_OBJECT_finish: @ field ptr in r0 11469 mov r2, rINST, lsr #8 @ r2<- AA 11470 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11471 GET_VREG(r1, r2) @ r1<- fp[AA] 11472 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11473 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 11474 GET_INST_OPCODE(ip) @ extract opcode from rINST 11475 @ no-op @ releasing store 11476 str r1, [r0, #offStaticField_value] @ field<- vAA 11477 cmp r1, #0 @ stored a null object? 11478 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 11479 GOTO_OPCODE(ip) @ jump to next instruction 11480 11481/* continuation for OP_SPUT_BOOLEAN */ 11482 11483 /* 11484 * Continuation if the field has not yet been resolved. 11485 * r1: BBBB field ref 11486 */ 11487.LOP_SPUT_BOOLEAN_resolve: 11488 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11489 EXPORT_PC() @ resolve() could throw, so export now 11490 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11491 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11492 cmp r0, #0 @ success? 11493 bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 11494 b common_exceptionThrown @ no, handle exception 11495 11496/* continuation for OP_SPUT_BYTE */ 11497 11498 /* 11499 * Continuation if the field has not yet been resolved. 11500 * r1: BBBB field ref 11501 */ 11502.LOP_SPUT_BYTE_resolve: 11503 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11504 EXPORT_PC() @ resolve() could throw, so export now 11505 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11506 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11507 cmp r0, #0 @ success? 11508 bne .LOP_SPUT_BYTE_finish @ yes, finish 11509 b common_exceptionThrown @ no, handle exception 11510 11511/* continuation for OP_SPUT_CHAR */ 11512 11513 /* 11514 * Continuation if the field has not yet been resolved. 11515 * r1: BBBB field ref 11516 */ 11517.LOP_SPUT_CHAR_resolve: 11518 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11519 EXPORT_PC() @ resolve() could throw, so export now 11520 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11521 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11522 cmp r0, #0 @ success? 11523 bne .LOP_SPUT_CHAR_finish @ yes, finish 11524 b common_exceptionThrown @ no, handle exception 11525 11526/* continuation for OP_SPUT_SHORT */ 11527 11528 /* 11529 * Continuation if the field has not yet been resolved. 11530 * r1: BBBB field ref 11531 */ 11532.LOP_SPUT_SHORT_resolve: 11533 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11534 EXPORT_PC() @ resolve() could throw, so export now 11535 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11536 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11537 cmp r0, #0 @ success? 11538 bne .LOP_SPUT_SHORT_finish @ yes, finish 11539 b common_exceptionThrown @ no, handle exception 11540 11541/* continuation for OP_INVOKE_VIRTUAL */ 11542 11543 /* 11544 * At this point: 11545 * r0 = resolved base method 11546 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11547 */ 11548.LOP_INVOKE_VIRTUAL_continue: 11549 GET_VREG(r1, r10) @ r1<- "this" ptr 11550 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11551 cmp r1, #0 @ is "this" null? 11552 beq common_errNullObject @ null "this", throw exception 11553 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11554 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11555 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11556 bl common_invokeMethodNoRange @ continue on 11557 11558/* continuation for OP_INVOKE_SUPER */ 11559 11560 /* 11561 * At this point: 11562 * r0 = resolved base method 11563 * r9 = method->clazz 11564 */ 11565.LOP_INVOKE_SUPER_continue: 11566 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11567 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11568 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11569 EXPORT_PC() @ must export for invoke 11570 cmp r2, r3 @ compare (methodIndex, vtableCount) 11571 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 11572 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11573 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11574 bl common_invokeMethodNoRange @ continue on 11575 11576.LOP_INVOKE_SUPER_resolve: 11577 mov r0, r9 @ r0<- method->clazz 11578 mov r2, #METHOD_VIRTUAL @ resolver method type 11579 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11580 cmp r0, #0 @ got null? 11581 bne .LOP_INVOKE_SUPER_continue @ no, continue 11582 b common_exceptionThrown @ yes, handle exception 11583 11584 /* 11585 * Throw a NoSuchMethodError with the method name as the message. 11586 * r0 = resolved base method 11587 */ 11588.LOP_INVOKE_SUPER_nsm: 11589 ldr r1, [r0, #offMethod_name] @ r1<- method name 11590 b common_errNoSuchMethod 11591 11592/* continuation for OP_INVOKE_DIRECT */ 11593 11594 /* 11595 * On entry: 11596 * r1 = reference (BBBB or CCCC) 11597 * r10 = "this" register 11598 */ 11599.LOP_INVOKE_DIRECT_resolve: 11600 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11601 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11602 mov r2, #METHOD_DIRECT @ resolver method type 11603 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11604 cmp r0, #0 @ got null? 11605 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 11606 bne .LOP_INVOKE_DIRECT_finish @ no, continue 11607 b common_exceptionThrown @ yes, handle exception 11608 11609/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 11610 11611 /* 11612 * At this point: 11613 * r0 = resolved base method 11614 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11615 */ 11616.LOP_INVOKE_VIRTUAL_RANGE_continue: 11617 GET_VREG(r1, r10) @ r1<- "this" ptr 11618 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11619 cmp r1, #0 @ is "this" null? 11620 beq common_errNullObject @ null "this", throw exception 11621 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11622 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11623 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11624 bl common_invokeMethodRange @ continue on 11625 11626/* continuation for OP_INVOKE_SUPER_RANGE */ 11627 11628 /* 11629 * At this point: 11630 * r0 = resolved base method 11631 * r9 = method->clazz 11632 */ 11633.LOP_INVOKE_SUPER_RANGE_continue: 11634 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11635 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11636 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11637 EXPORT_PC() @ must export for invoke 11638 cmp r2, r3 @ compare (methodIndex, vtableCount) 11639 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 11640 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11641 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11642 bl common_invokeMethodRange @ continue on 11643 11644.LOP_INVOKE_SUPER_RANGE_resolve: 11645 mov r0, r9 @ r0<- method->clazz 11646 mov r2, #METHOD_VIRTUAL @ resolver method type 11647 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11648 cmp r0, #0 @ got null? 11649 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 11650 b common_exceptionThrown @ yes, handle exception 11651 11652 /* 11653 * Throw a NoSuchMethodError with the method name as the message. 11654 * r0 = resolved base method 11655 */ 11656.LOP_INVOKE_SUPER_RANGE_nsm: 11657 ldr r1, [r0, #offMethod_name] @ r1<- method name 11658 b common_errNoSuchMethod 11659 11660/* continuation for OP_INVOKE_DIRECT_RANGE */ 11661 11662 /* 11663 * On entry: 11664 * r1 = reference (BBBB or CCCC) 11665 * r10 = "this" register 11666 */ 11667.LOP_INVOKE_DIRECT_RANGE_resolve: 11668 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11669 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11670 mov r2, #METHOD_DIRECT @ resolver method type 11671 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11672 cmp r0, #0 @ got null? 11673 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 11674 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 11675 b common_exceptionThrown @ yes, handle exception 11676 11677/* continuation for OP_FLOAT_TO_LONG */ 11678/* 11679 * Convert the float in r0 to a long in r0/r1. 11680 * 11681 * We have to clip values to long min/max per the specification. The 11682 * expected common case is a "reasonable" value that converts directly 11683 * to modest integer. The EABI convert function isn't doing this for us. 11684 */ 11685f2l_doconv: 11686 stmfd sp!, {r4, lr} 11687 mov r1, #0x5f000000 @ (float)maxlong 11688 mov r4, r0 11689 bl __aeabi_fcmpge @ is arg >= maxlong? 11690 cmp r0, #0 @ nonzero == yes 11691 mvnne r0, #0 @ return maxlong (7fffffff) 11692 mvnne r1, #0x80000000 11693 ldmnefd sp!, {r4, pc} 11694 11695 mov r0, r4 @ recover arg 11696 mov r1, #0xdf000000 @ (float)minlong 11697 bl __aeabi_fcmple @ is arg <= minlong? 11698 cmp r0, #0 @ nonzero == yes 11699 movne r0, #0 @ return minlong (80000000) 11700 movne r1, #0x80000000 11701 ldmnefd sp!, {r4, pc} 11702 11703 mov r0, r4 @ recover arg 11704 mov r1, r4 11705 bl __aeabi_fcmpeq @ is arg == self? 11706 cmp r0, #0 @ zero == no 11707 moveq r1, #0 @ return zero for NaN 11708 ldmeqfd sp!, {r4, pc} 11709 11710 mov r0, r4 @ recover arg 11711 bl __aeabi_f2lz @ convert float to long 11712 ldmfd sp!, {r4, pc} 11713 11714/* continuation for OP_DOUBLE_TO_LONG */ 11715/* 11716 * Convert the double in r0/r1 to a long in r0/r1. 11717 * 11718 * We have to clip values to long min/max per the specification. The 11719 * expected common case is a "reasonable" value that converts directly 11720 * to modest integer. The EABI convert function isn't doing this for us. 11721 */ 11722d2l_doconv: 11723 stmfd sp!, {r4, r5, lr} @ save regs 11724 mov r3, #0x43000000 @ maxlong, as a double (high word) 11725 add r3, #0x00e00000 @ 0x43e00000 11726 mov r2, #0 @ maxlong, as a double (low word) 11727 sub sp, sp, #4 @ align for EABI 11728 mov r4, r0 @ save a copy of r0 11729 mov r5, r1 @ and r1 11730 bl __aeabi_dcmpge @ is arg >= maxlong? 11731 cmp r0, #0 @ nonzero == yes 11732 mvnne r0, #0 @ return maxlong (7fffffffffffffff) 11733 mvnne r1, #0x80000000 11734 bne 1f 11735 11736 mov r0, r4 @ recover arg 11737 mov r1, r5 11738 mov r3, #0xc3000000 @ minlong, as a double (high word) 11739 add r3, #0x00e00000 @ 0xc3e00000 11740 mov r2, #0 @ minlong, as a double (low word) 11741 bl __aeabi_dcmple @ is arg <= minlong? 11742 cmp r0, #0 @ nonzero == yes 11743 movne r0, #0 @ return minlong (8000000000000000) 11744 movne r1, #0x80000000 11745 bne 1f 11746 11747 mov r0, r4 @ recover arg 11748 mov r1, r5 11749 mov r2, r4 @ compare against self 11750 mov r3, r5 11751 bl __aeabi_dcmpeq @ is arg == self? 11752 cmp r0, #0 @ zero == no 11753 moveq r1, #0 @ return zero for NaN 11754 beq 1f 11755 11756 mov r0, r4 @ recover arg 11757 mov r1, r5 11758 bl __aeabi_d2lz @ convert double to long 11759 117601: 11761 add sp, sp, #4 11762 ldmfd sp!, {r4, r5, pc} 11763 11764/* continuation for OP_MUL_LONG */ 11765 11766.LOP_MUL_LONG_finish: 11767 GET_INST_OPCODE(ip) @ extract opcode from rINST 11768 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 11769 GOTO_OPCODE(ip) @ jump to next instruction 11770 11771/* continuation for OP_SHL_LONG */ 11772 11773.LOP_SHL_LONG_finish: 11774 mov r0, r0, asl r2 @ r0<- r0 << r2 11775 GET_INST_OPCODE(ip) @ extract opcode from rINST 11776 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11777 GOTO_OPCODE(ip) @ jump to next instruction 11778 11779/* continuation for OP_SHR_LONG */ 11780 11781.LOP_SHR_LONG_finish: 11782 mov r1, r1, asr r2 @ r1<- r1 >> r2 11783 GET_INST_OPCODE(ip) @ extract opcode from rINST 11784 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11785 GOTO_OPCODE(ip) @ jump to next instruction 11786 11787/* continuation for OP_USHR_LONG */ 11788 11789.LOP_USHR_LONG_finish: 11790 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 11791 GET_INST_OPCODE(ip) @ extract opcode from rINST 11792 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11793 GOTO_OPCODE(ip) @ jump to next instruction 11794 11795/* continuation for OP_SHL_LONG_2ADDR */ 11796 11797.LOP_SHL_LONG_2ADDR_finish: 11798 GET_INST_OPCODE(ip) @ extract opcode from rINST 11799 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11800 GOTO_OPCODE(ip) @ jump to next instruction 11801 11802/* continuation for OP_SHR_LONG_2ADDR */ 11803 11804.LOP_SHR_LONG_2ADDR_finish: 11805 GET_INST_OPCODE(ip) @ extract opcode from rINST 11806 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11807 GOTO_OPCODE(ip) @ jump to next instruction 11808 11809/* continuation for OP_USHR_LONG_2ADDR */ 11810 11811.LOP_USHR_LONG_2ADDR_finish: 11812 GET_INST_OPCODE(ip) @ extract opcode from rINST 11813 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11814 GOTO_OPCODE(ip) @ jump to next instruction 11815 11816/* continuation for OP_IGET_VOLATILE */ 11817 11818 /* 11819 * Currently: 11820 * r0 holds resolved field 11821 * r9 holds object 11822 */ 11823.LOP_IGET_VOLATILE_finish: 11824 @bl common_squeak0 11825 cmp r9, #0 @ check object for null 11826 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11827 beq common_errNullObject @ object was null 11828 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11829 SMP_DMB @ acquiring load 11830 mov r2, rINST, lsr #8 @ r2<- A+ 11831 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11832 and r2, r2, #15 @ r2<- A 11833 GET_INST_OPCODE(ip) @ extract opcode from rINST 11834 SET_VREG(r0, r2) @ fp[A]<- r0 11835 GOTO_OPCODE(ip) @ jump to next instruction 11836 11837/* continuation for OP_IPUT_VOLATILE */ 11838 11839 /* 11840 * Currently: 11841 * r0 holds resolved field 11842 * r9 holds object 11843 */ 11844.LOP_IPUT_VOLATILE_finish: 11845 @bl common_squeak0 11846 mov r1, rINST, lsr #8 @ r1<- A+ 11847 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11848 and r1, r1, #15 @ r1<- A 11849 cmp r9, #0 @ check object for null 11850 GET_VREG(r0, r1) @ r0<- fp[A] 11851 beq common_errNullObject @ object was null 11852 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11853 GET_INST_OPCODE(ip) @ extract opcode from rINST 11854 SMP_DMB @ releasing store 11855 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11856 GOTO_OPCODE(ip) @ jump to next instruction 11857 11858/* continuation for OP_SGET_VOLATILE */ 11859 11860 /* 11861 * Continuation if the field has not yet been resolved. 11862 * r1: BBBB field ref 11863 */ 11864.LOP_SGET_VOLATILE_resolve: 11865 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11866 EXPORT_PC() @ resolve() could throw, so export now 11867 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11868 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11869 cmp r0, #0 @ success? 11870 bne .LOP_SGET_VOLATILE_finish @ yes, finish 11871 b common_exceptionThrown @ no, handle exception 11872 11873/* continuation for OP_SPUT_VOLATILE */ 11874 11875 /* 11876 * Continuation if the field has not yet been resolved. 11877 * r1: BBBB field ref 11878 */ 11879.LOP_SPUT_VOLATILE_resolve: 11880 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11881 EXPORT_PC() @ resolve() could throw, so export now 11882 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11883 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11884 cmp r0, #0 @ success? 11885 bne .LOP_SPUT_VOLATILE_finish @ yes, finish 11886 b common_exceptionThrown @ no, handle exception 11887 11888/* continuation for OP_IGET_OBJECT_VOLATILE */ 11889 11890 /* 11891 * Currently: 11892 * r0 holds resolved field 11893 * r9 holds object 11894 */ 11895.LOP_IGET_OBJECT_VOLATILE_finish: 11896 @bl common_squeak0 11897 cmp r9, #0 @ check object for null 11898 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11899 beq common_errNullObject @ object was null 11900 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11901 SMP_DMB @ acquiring load 11902 mov r2, rINST, lsr #8 @ r2<- A+ 11903 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11904 and r2, r2, #15 @ r2<- A 11905 GET_INST_OPCODE(ip) @ extract opcode from rINST 11906 SET_VREG(r0, r2) @ fp[A]<- r0 11907 GOTO_OPCODE(ip) @ jump to next instruction 11908 11909/* continuation for OP_IGET_WIDE_VOLATILE */ 11910 11911 /* 11912 * Currently: 11913 * r0 holds resolved field 11914 * r9 holds object 11915 */ 11916.LOP_IGET_WIDE_VOLATILE_finish: 11917 cmp r9, #0 @ check object for null 11918 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11919 beq common_errNullObject @ object was null 11920 .if 1 11921 add r0, r9, r3 @ r0<- address of field 11922 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 11923 .else 11924 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11925 .endif 11926 mov r2, rINST, lsr #8 @ r2<- A+ 11927 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11928 and r2, r2, #15 @ r2<- A 11929 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11930 GET_INST_OPCODE(ip) @ extract opcode from rINST 11931 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11932 GOTO_OPCODE(ip) @ jump to next instruction 11933 11934/* continuation for OP_IPUT_WIDE_VOLATILE */ 11935 11936 /* 11937 * Currently: 11938 * r0 holds resolved field 11939 * r9 holds object 11940 */ 11941.LOP_IPUT_WIDE_VOLATILE_finish: 11942 mov r2, rINST, lsr #8 @ r2<- A+ 11943 cmp r9, #0 @ check object for null 11944 and r2, r2, #15 @ r2<- A 11945 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11946 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 11947 beq common_errNullObject @ object was null 11948 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11949 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 11950 GET_INST_OPCODE(r10) @ extract opcode from rINST 11951 .if 1 11952 add r2, r9, r3 @ r2<- target address 11953 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 11954 .else 11955 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 11956 .endif 11957 GOTO_OPCODE(r10) @ jump to next instruction 11958 11959/* continuation for OP_SGET_WIDE_VOLATILE */ 11960 11961 /* 11962 * Continuation if the field has not yet been resolved. 11963 * r1: BBBB field ref 11964 * 11965 * Returns StaticField pointer in r0. 11966 */ 11967.LOP_SGET_WIDE_VOLATILE_resolve: 11968 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11969 EXPORT_PC() @ resolve() could throw, so export now 11970 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11971 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11972 cmp r0, #0 @ success? 11973 bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 11974 b common_exceptionThrown @ no, handle exception 11975 11976/* continuation for OP_SPUT_WIDE_VOLATILE */ 11977 11978 /* 11979 * Continuation if the field has not yet been resolved. 11980 * r1: BBBB field ref 11981 * r9: &fp[AA] 11982 * 11983 * Returns StaticField pointer in r2. 11984 */ 11985.LOP_SPUT_WIDE_VOLATILE_resolve: 11986 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11987 EXPORT_PC() @ resolve() could throw, so export now 11988 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11989 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11990 cmp r0, #0 @ success? 11991 mov r2, r0 @ copy to r2 11992 bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 11993 b common_exceptionThrown @ no, handle exception 11994 11995/* continuation for OP_EXECUTE_INLINE */ 11996 11997 /* 11998 * Extract args, call function. 11999 * r0 = #of args (0-4) 12000 * r10 = call index 12001 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12002 * 12003 * Other ideas: 12004 * - Use a jump table from the main piece to jump directly into the 12005 * AND/LDR pairs. Costs a data load, saves a branch. 12006 * - Have five separate pieces that do the loading, so we can work the 12007 * interleave a little better. Increases code size. 12008 */ 12009.LOP_EXECUTE_INLINE_continue: 12010 rsb r0, r0, #4 @ r0<- 4-r0 12011 FETCH(r9, 2) @ r9<- FEDC 12012 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12013 bl common_abort @ (skipped due to ARM prefetch) 120144: and ip, r9, #0xf000 @ isolate F 12015 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 120163: and ip, r9, #0x0f00 @ isolate E 12017 ldr r2, [rFP, ip, lsr #6] @ r2<- vE 120182: and ip, r9, #0x00f0 @ isolate D 12019 ldr r1, [rFP, ip, lsr #2] @ r1<- vD 120201: and ip, r9, #0x000f @ isolate C 12021 ldr r0, [rFP, ip, lsl #2] @ r0<- vC 120220: 12023 ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 12024 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12025 @ (not reached) 12026 12027.LOP_EXECUTE_INLINE_table: 12028 .word gDvmInlineOpsTable 12029 12030/* continuation for OP_EXECUTE_INLINE_RANGE */ 12031 12032 /* 12033 * Extract args, call function. 12034 * r0 = #of args (0-4) 12035 * r10 = call index 12036 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12037 */ 12038.LOP_EXECUTE_INLINE_RANGE_continue: 12039 rsb r0, r0, #4 @ r0<- 4-r0 12040 FETCH(r9, 2) @ r9<- CCCC 12041 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12042 bl common_abort @ (skipped due to ARM prefetch) 120434: add ip, r9, #3 @ base+3 12044 GET_VREG(r3, ip) @ r3<- vBase[3] 120453: add ip, r9, #2 @ base+2 12046 GET_VREG(r2, ip) @ r2<- vBase[2] 120472: add ip, r9, #1 @ base+1 12048 GET_VREG(r1, ip) @ r1<- vBase[1] 120491: add ip, r9, #0 @ (nop) 12050 GET_VREG(r0, ip) @ r0<- vBase[0] 120510: 12052 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 12053 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12054 @ (not reached) 12055 12056.LOP_EXECUTE_INLINE_RANGE_table: 12057 .word gDvmInlineOpsTable 12058 12059/* continuation for OP_IPUT_OBJECT_VOLATILE */ 12060 12061 /* 12062 * Currently: 12063 * r0 holds resolved field 12064 * r9 holds object 12065 */ 12066.LOP_IPUT_OBJECT_VOLATILE_finish: 12067 @bl common_squeak0 12068 mov r1, rINST, lsr #8 @ r1<- A+ 12069 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12070 and r1, r1, #15 @ r1<- A 12071 cmp r9, #0 @ check object for null 12072 GET_VREG(r0, r1) @ r0<- fp[A] 12073 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12074 beq common_errNullObject @ object was null 12075 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12076 GET_INST_OPCODE(ip) @ extract opcode from rINST 12077 SMP_DMB @ releasing store 12078 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12079 cmp r0, #0 @ stored a null reference? 12080 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12081 GOTO_OPCODE(ip) @ jump to next instruction 12082 12083/* continuation for OP_SGET_OBJECT_VOLATILE */ 12084 12085 /* 12086 * Continuation if the field has not yet been resolved. 12087 * r1: BBBB field ref 12088 */ 12089.LOP_SGET_OBJECT_VOLATILE_resolve: 12090 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12091 EXPORT_PC() @ resolve() could throw, so export now 12092 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12093 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12094 cmp r0, #0 @ success? 12095 bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish 12096 b common_exceptionThrown @ no, handle exception 12097 12098/* continuation for OP_SPUT_OBJECT_VOLATILE */ 12099.LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 12100 mov r2, rINST, lsr #8 @ r2<- AA 12101 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12102 GET_VREG(r1, r2) @ r1<- fp[AA] 12103 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12104 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 12105 GET_INST_OPCODE(ip) @ extract opcode from rINST 12106 SMP_DMB @ releasing store 12107 str r1, [r0, #offStaticField_value] @ field<- vAA 12108 cmp r1, #0 @ stored a null object? 12109 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12110 GOTO_OPCODE(ip) @ jump to next instruction 12111 12112/* continuation for OP_CONST_CLASS_JUMBO */ 12113 12114 /* 12115 * Continuation if the Class has not yet been resolved. 12116 * r1: AAAAAAAA (Class ref) 12117 * r9: target register 12118 */ 12119.LOP_CONST_CLASS_JUMBO_resolve: 12120 EXPORT_PC() 12121 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12122 mov r2, #1 @ r2<- true 12123 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12124 bl dvmResolveClass @ r0<- Class reference 12125 cmp r0, #0 @ failed? 12126 beq common_exceptionThrown @ yup, handle the exception 12127 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12128 GET_INST_OPCODE(ip) @ extract opcode from rINST 12129 SET_VREG(r0, r9) @ vBBBB<- r0 12130 GOTO_OPCODE(ip) @ jump to next instruction 12131 12132/* continuation for OP_CHECK_CAST_JUMBO */ 12133 12134 /* 12135 * Trivial test failed, need to perform full check. This is common. 12136 * r0 holds obj->clazz 12137 * r1 holds desired class resolved from AAAAAAAA 12138 * r9 holds object 12139 */ 12140.LOP_CHECK_CAST_JUMBO_fullcheck: 12141 mov r10, r1 @ avoid ClassObject getting clobbered 12142 bl dvmInstanceofNonTrivial @ r0<- boolean result 12143 cmp r0, #0 @ failed? 12144 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success 12145 12146 @ A cast has failed. We need to throw a ClassCastException. 12147 EXPORT_PC() @ about to throw 12148 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 12149 mov r1, r10 @ r1<- desired class 12150 bl dvmThrowClassCastException 12151 b common_exceptionThrown 12152 12153 /* 12154 * Advance PC and get the next opcode. 12155 */ 12156.LOP_CHECK_CAST_JUMBO_okay: 12157 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12158 GET_INST_OPCODE(ip) @ extract opcode from rINST 12159 GOTO_OPCODE(ip) @ jump to next instruction 12160 12161 /* 12162 * Resolution required. This is the least-likely path. 12163 * 12164 * r2 holds AAAAAAAA 12165 * r9 holds object 12166 */ 12167.LOP_CHECK_CAST_JUMBO_resolve: 12168 EXPORT_PC() @ resolve() could throw 12169 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12170 mov r1, r2 @ r1<- AAAAAAAA 12171 mov r2, #0 @ r2<- false 12172 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12173 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12174 cmp r0, #0 @ got null? 12175 beq common_exceptionThrown @ yes, handle exception 12176 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12177 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 12178 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off 12179 12180/* continuation for OP_INSTANCE_OF_JUMBO */ 12181 12182 /* 12183 * Class resolved, determine type of check necessary. This is common. 12184 * r0 holds obj->clazz 12185 * r1 holds class resolved from AAAAAAAA 12186 * r9 holds BBBB 12187 */ 12188.LOP_INSTANCE_OF_JUMBO_resolved: 12189 cmp r0, r1 @ same class (trivial success)? 12190 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish 12191 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck 12192 12193 /* 12194 * Trivial test failed, need to perform full check. This is common. 12195 * r0 holds obj->clazz 12196 * r1 holds class resolved from AAAAAAAA 12197 * r9 holds BBBB 12198 */ 12199.LOP_INSTANCE_OF_JUMBO_fullcheck: 12200 bl dvmInstanceofNonTrivial @ r0<- boolean result 12201 @ fall through to OP_INSTANCE_OF_JUMBO_store 12202 12203 /* 12204 * r0 holds boolean result 12205 * r9 holds BBBB 12206 */ 12207.LOP_INSTANCE_OF_JUMBO_store: 12208 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12209 SET_VREG(r0, r9) @ vBBBB<- r0 12210 GET_INST_OPCODE(ip) @ extract opcode from rINST 12211 GOTO_OPCODE(ip) @ jump to next instruction 12212 12213 /* 12214 * Trivial test succeeded, save and bail. 12215 * r9 holds BBBB 12216 */ 12217.LOP_INSTANCE_OF_JUMBO_trivial: 12218 mov r0, #1 @ indicate success 12219 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper 12220 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12221 SET_VREG(r0, r9) @ vBBBB<- r0 12222 GET_INST_OPCODE(ip) @ extract opcode from rINST 12223 GOTO_OPCODE(ip) @ jump to next instruction 12224 12225 /* 12226 * Resolution required. This is the least-likely path. 12227 * 12228 * r3 holds AAAAAAAA 12229 * r9 holds BBBB 12230 */ 12231 12232.LOP_INSTANCE_OF_JUMBO_resolve: 12233 EXPORT_PC() @ resolve() could throw 12234 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12235 mov r1, r3 @ r1<- AAAAAAAA 12236 mov r2, #1 @ r2<- true 12237 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12238 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12239 cmp r0, #0 @ got null? 12240 beq common_exceptionThrown @ yes, handle exception 12241 FETCH(r3, 4) @ r3<- vCCCC 12242 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12243 GET_VREG(r0, r3) @ r0<- vCCCC (object) 12244 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 12245 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off 12246 12247/* continuation for OP_NEW_INSTANCE_JUMBO */ 12248 12249 .balign 32 @ minimize cache lines 12250.LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object 12251 FETCH(r3, 3) @ r3<- BBBB 12252 cmp r0, #0 @ failed? 12253 beq common_exceptionThrown @ yes, handle the exception 12254 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12255 GET_INST_OPCODE(ip) @ extract opcode from rINST 12256 SET_VREG(r0, r3) @ vBBBB<- r0 12257 GOTO_OPCODE(ip) @ jump to next instruction 12258 12259 /* 12260 * Class initialization required. 12261 * 12262 * r0 holds class object 12263 */ 12264.LOP_NEW_INSTANCE_JUMBO_needinit: 12265 mov r9, r0 @ save r0 12266 bl dvmInitClass @ initialize class 12267 cmp r0, #0 @ check boolean result 12268 mov r0, r9 @ restore r0 12269 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue 12270 b common_exceptionThrown @ failed, deal with init exception 12271 12272 /* 12273 * Resolution required. This is the least-likely path. 12274 * 12275 * r1 holds AAAAAAAA 12276 */ 12277.LOP_NEW_INSTANCE_JUMBO_resolve: 12278 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12279 mov r2, #0 @ r2<- false 12280 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12281 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12282 cmp r0, #0 @ got null? 12283 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue 12284 b common_exceptionThrown @ yes, handle exception 12285 12286/* continuation for OP_NEW_ARRAY_JUMBO */ 12287 12288 12289 /* 12290 * Resolve class. (This is an uncommon case.) 12291 * 12292 * r1 holds array length 12293 * r2 holds class ref AAAAAAAA 12294 */ 12295.LOP_NEW_ARRAY_JUMBO_resolve: 12296 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12297 mov r9, r1 @ r9<- length (save) 12298 mov r1, r2 @ r1<- AAAAAAAA 12299 mov r2, #0 @ r2<- false 12300 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12301 bl dvmResolveClass @ r0<- call(clazz, ref) 12302 cmp r0, #0 @ got null? 12303 mov r1, r9 @ r1<- length (restore) 12304 beq common_exceptionThrown @ yes, handle exception 12305 @ fall through to OP_NEW_ARRAY_JUMBO_finish 12306 12307 /* 12308 * Finish allocation. 12309 * 12310 * r0 holds class 12311 * r1 holds array length 12312 */ 12313.LOP_NEW_ARRAY_JUMBO_finish: 12314 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 12315 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 12316 cmp r0, #0 @ failed? 12317 FETCH(r2, 3) @ r2<- vBBBB 12318 beq common_exceptionThrown @ yes, handle the exception 12319 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12320 GET_INST_OPCODE(ip) @ extract opcode from rINST 12321 SET_VREG(r0, r2) @ vBBBB<- r0 12322 GOTO_OPCODE(ip) @ jump to next instruction 12323 12324/* continuation for OP_FILLED_NEW_ARRAY_JUMBO */ 12325 12326 /* 12327 * On entry: 12328 * r0 holds array class 12329 */ 12330.LOP_FILLED_NEW_ARRAY_JUMBO_continue: 12331 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 12332 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 12333 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 12334 FETCH(r1, 3) @ r1<- BBBB (length) 12335 cmp rINST, #'I' @ array of ints? 12336 cmpne rINST, #'L' @ array of objects? 12337 cmpne rINST, #'[' @ array of arrays? 12338 mov r9, r1 @ save length in r9 12339 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet 12340 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 12341 cmp r0, #0 @ null return? 12342 beq common_exceptionThrown @ alloc failed, handle exception 12343 12344 FETCH(r1, 4) @ r1<- CCCC 12345 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 12346 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 12347 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 12348 subs r9, r9, #1 @ length--, check for neg 12349 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST 12350 bmi 2f @ was zero, bail 12351 12352 @ copy values from registers into the array 12353 @ r0=array, r1=CCCC, r9=BBBB (length) 12354 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 123551: ldr r3, [r2], #4 @ r3<- *r2++ 12356 subs r9, r9, #1 @ count-- 12357 str r3, [r0], #4 @ *contents++ = vX 12358 bpl 1b 12359 123602: ldr r0, [rSELF, #offThread_retval] @ r0<- object 12361 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 12362 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12363 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 12364 cmp r1, #'I' @ Is int array? 12365 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 12366 GOTO_OPCODE(ip) @ execute it 12367 12368 /* 12369 * Throw an exception indicating that we have not implemented this 12370 * mode of filled-new-array. 12371 */ 12372.LOP_FILLED_NEW_ARRAY_JUMBO_notimpl: 12373 ldr r0, .L_strFilledNewArrayNotImpl 12374 bl dvmThrowInternalError 12375 b common_exceptionThrown 12376 12377/* continuation for OP_IGET_JUMBO */ 12378 12379 /* 12380 * Currently: 12381 * r0 holds resolved field 12382 * r9 holds object 12383 */ 12384.LOP_IGET_JUMBO_resolved: 12385 cmp r0, #0 @ resolution unsuccessful? 12386 beq common_exceptionThrown @ yes, throw exception 12387 @ fall through to OP_IGET_JUMBO_finish 12388 12389 /* 12390 * Currently: 12391 * r0 holds resolved field 12392 * r9 holds object 12393 */ 12394.LOP_IGET_JUMBO_finish: 12395 @bl common_squeak0 12396 cmp r9, #0 @ check object for null 12397 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12398 beq common_errNullObject @ object was null 12399 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12400 @ no-op @ acquiring load 12401 FETCH(r2, 3) @ r2<- BBBB 12402 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12403 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12404 GET_INST_OPCODE(ip) @ extract opcode from rINST 12405 GOTO_OPCODE(ip) @ jump to next instruction 12406 12407/* continuation for OP_IGET_WIDE_JUMBO */ 12408 12409 /* 12410 * Currently: 12411 * r0 holds resolved field 12412 * r9 holds object 12413 */ 12414.LOP_IGET_WIDE_JUMBO_resolved: 12415 cmp r0, #0 @ resolution unsuccessful? 12416 beq common_exceptionThrown @ yes, throw exception 12417 @ fall through to OP_IGET_WIDE_JUMBO_finish 12418 12419 /* 12420 * Currently: 12421 * r0 holds resolved field 12422 * r9 holds object 12423 */ 12424.LOP_IGET_WIDE_JUMBO_finish: 12425 cmp r9, #0 @ check object for null 12426 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12427 beq common_errNullObject @ object was null 12428 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12429 FETCH(r2, 3) @ r2<- BBBB 12430 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12431 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12432 GET_INST_OPCODE(ip) @ extract opcode from rINST 12433 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 12434 GOTO_OPCODE(ip) @ jump to next instruction 12435 12436/* continuation for OP_IGET_OBJECT_JUMBO */ 12437 12438 /* 12439 * Currently: 12440 * r0 holds resolved field 12441 * r9 holds object 12442 */ 12443.LOP_IGET_OBJECT_JUMBO_resolved: 12444 cmp r0, #0 @ resolution unsuccessful? 12445 beq common_exceptionThrown @ yes, throw exception 12446 @ fall through to OP_IGET_OBJECT_JUMBO_finish 12447 12448 /* 12449 * Currently: 12450 * r0 holds resolved field 12451 * r9 holds object 12452 */ 12453.LOP_IGET_OBJECT_JUMBO_finish: 12454 @bl common_squeak0 12455 cmp r9, #0 @ check object for null 12456 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12457 beq common_errNullObject @ object was null 12458 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12459 @ no-op @ acquiring load 12460 FETCH(r2, 3) @ r2<- BBBB 12461 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12462 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12463 GET_INST_OPCODE(ip) @ extract opcode from rINST 12464 GOTO_OPCODE(ip) @ jump to next instruction 12465 12466/* continuation for OP_IGET_BOOLEAN_JUMBO */ 12467 12468 /* 12469 * Currently: 12470 * r0 holds resolved field 12471 * r9 holds object 12472 */ 12473.LOP_IGET_BOOLEAN_JUMBO_resolved: 12474 cmp r0, #0 @ resolution unsuccessful? 12475 beq common_exceptionThrown @ yes, throw exception 12476 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish 12477 12478 /* 12479 * Currently: 12480 * r0 holds resolved field 12481 * r9 holds object 12482 */ 12483.LOP_IGET_BOOLEAN_JUMBO_finish: 12484 @bl common_squeak1 12485 cmp r9, #0 @ check object for null 12486 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12487 beq common_errNullObject @ object was null 12488 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12489 @ no-op @ acquiring load 12490 FETCH(r2, 3) @ r2<- BBBB 12491 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12492 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12493 GET_INST_OPCODE(ip) @ extract opcode from rINST 12494 GOTO_OPCODE(ip) @ jump to next instruction 12495 12496/* continuation for OP_IGET_BYTE_JUMBO */ 12497 12498 /* 12499 * Currently: 12500 * r0 holds resolved field 12501 * r9 holds object 12502 */ 12503.LOP_IGET_BYTE_JUMBO_resolved: 12504 cmp r0, #0 @ resolution unsuccessful? 12505 beq common_exceptionThrown @ yes, throw exception 12506 @ fall through to OP_IGET_BYTE_JUMBO_finish 12507 12508 /* 12509 * Currently: 12510 * r0 holds resolved field 12511 * r9 holds object 12512 */ 12513.LOP_IGET_BYTE_JUMBO_finish: 12514 @bl common_squeak2 12515 cmp r9, #0 @ check object for null 12516 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12517 beq common_errNullObject @ object was null 12518 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12519 @ no-op @ acquiring load 12520 FETCH(r2, 3) @ r2<- BBBB 12521 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12522 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12523 GET_INST_OPCODE(ip) @ extract opcode from rINST 12524 GOTO_OPCODE(ip) @ jump to next instruction 12525 12526/* continuation for OP_IGET_CHAR_JUMBO */ 12527 12528 /* 12529 * Currently: 12530 * r0 holds resolved field 12531 * r9 holds object 12532 */ 12533.LOP_IGET_CHAR_JUMBO_resolved: 12534 cmp r0, #0 @ resolution unsuccessful? 12535 beq common_exceptionThrown @ yes, throw exception 12536 @ fall through to OP_IGET_CHAR_JUMBO_finish 12537 12538 /* 12539 * Currently: 12540 * r0 holds resolved field 12541 * r9 holds object 12542 */ 12543.LOP_IGET_CHAR_JUMBO_finish: 12544 @bl common_squeak3 12545 cmp r9, #0 @ check object for null 12546 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12547 beq common_errNullObject @ object was null 12548 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12549 @ no-op @ acquiring load 12550 FETCH(r2, 3) @ r2<- BBBB 12551 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12552 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12553 GET_INST_OPCODE(ip) @ extract opcode from rINST 12554 GOTO_OPCODE(ip) @ jump to next instruction 12555 12556/* continuation for OP_IGET_SHORT_JUMBO */ 12557 12558 /* 12559 * Currently: 12560 * r0 holds resolved field 12561 * r9 holds object 12562 */ 12563.LOP_IGET_SHORT_JUMBO_resolved: 12564 cmp r0, #0 @ resolution unsuccessful? 12565 beq common_exceptionThrown @ yes, throw exception 12566 @ fall through to OP_IGET_SHORT_JUMBO_finish 12567 12568 /* 12569 * Currently: 12570 * r0 holds resolved field 12571 * r9 holds object 12572 */ 12573.LOP_IGET_SHORT_JUMBO_finish: 12574 @bl common_squeak4 12575 cmp r9, #0 @ check object for null 12576 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12577 beq common_errNullObject @ object was null 12578 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12579 @ no-op @ acquiring load 12580 FETCH(r2, 3) @ r2<- BBBB 12581 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12582 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12583 GET_INST_OPCODE(ip) @ extract opcode from rINST 12584 GOTO_OPCODE(ip) @ jump to next instruction 12585 12586/* continuation for OP_IPUT_JUMBO */ 12587 12588 /* 12589 * Currently: 12590 * r0 holds resolved field 12591 * r9 holds object 12592 */ 12593.LOP_IPUT_JUMBO_resolved: 12594 cmp r0, #0 @ resolution unsuccessful? 12595 beq common_exceptionThrown @ yes, throw exception 12596 @ fall through to OP_IPUT_JUMBO_finish 12597 12598 /* 12599 * Currently: 12600 * r0 holds resolved field 12601 * r9 holds object 12602 */ 12603.LOP_IPUT_JUMBO_finish: 12604 @bl common_squeak0 12605 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12606 FETCH(r1, 3) @ r1<- BBBB 12607 cmp r9, #0 @ check object for null 12608 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12609 beq common_errNullObject @ object was null 12610 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12611 GET_INST_OPCODE(ip) @ extract opcode from rINST 12612 @ no-op @ releasing store 12613 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12614 GOTO_OPCODE(ip) @ jump to next instruction 12615 12616/* continuation for OP_IPUT_WIDE_JUMBO */ 12617 12618 /* 12619 * Currently: 12620 * r0 holds resolved field 12621 * r9 holds object 12622 */ 12623.LOP_IPUT_WIDE_JUMBO_resolved: 12624 cmp r0, #0 @ resolution unsuccessful? 12625 beq common_exceptionThrown @ yes, throw exception 12626 @ fall through to OP_IPUT_WIDE_JUMBO_finish 12627 12628 /* 12629 * Currently: 12630 * r0 holds resolved field 12631 * r9 holds object 12632 */ 12633.LOP_IPUT_WIDE_JUMBO_finish: 12634 cmp r9, #0 @ check object for null 12635 FETCH(r2, 3) @ r1<- BBBB 12636 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12637 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12638 beq common_errNullObject @ object was null 12639 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12640 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 12641 GET_INST_OPCODE(r10) @ extract opcode from rINST 12642 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12643 GOTO_OPCODE(r10) @ jump to next instruction 12644 12645/* continuation for OP_IPUT_OBJECT_JUMBO */ 12646 12647 /* 12648 * Currently: 12649 * r0 holds resolved field 12650 * r9 holds object 12651 */ 12652.LOP_IPUT_OBJECT_JUMBO_resolved: 12653 cmp r0, #0 @ resolution unsuccessful? 12654 beq common_exceptionThrown @ yes, throw exception 12655 @ fall through to OP_IPUT_OBJECT_JUMBO_finish 12656 12657 /* 12658 * Currently: 12659 * r0 holds resolved field 12660 * r9 holds object 12661 */ 12662.LOP_IPUT_OBJECT_JUMBO_finish: 12663 @bl common_squeak0 12664 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12665 FETCH(r1, 3) @ r1<- BBBB 12666 cmp r9, #0 @ check object for null 12667 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12668 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12669 beq common_errNullObject @ object was null 12670 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12671 GET_INST_OPCODE(ip) @ extract opcode from rINST 12672 @ no-op @ releasing store 12673 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12674 cmp r0, #0 @ stored a null reference? 12675 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12676 GOTO_OPCODE(ip) @ jump to next instruction 12677 12678/* continuation for OP_IPUT_BOOLEAN_JUMBO */ 12679 12680 /* 12681 * Currently: 12682 * r0 holds resolved field 12683 * r9 holds object 12684 */ 12685.LOP_IPUT_BOOLEAN_JUMBO_resolved: 12686 cmp r0, #0 @ resolution unsuccessful? 12687 beq common_exceptionThrown @ yes, throw exception 12688 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish 12689 12690 /* 12691 * Currently: 12692 * r0 holds resolved field 12693 * r9 holds object 12694 */ 12695.LOP_IPUT_BOOLEAN_JUMBO_finish: 12696 @bl common_squeak1 12697 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12698 FETCH(r1, 3) @ r1<- BBBB 12699 cmp r9, #0 @ check object for null 12700 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12701 beq common_errNullObject @ object was null 12702 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12703 GET_INST_OPCODE(ip) @ extract opcode from rINST 12704 @ no-op @ releasing store 12705 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12706 GOTO_OPCODE(ip) @ jump to next instruction 12707 12708/* continuation for OP_IPUT_BYTE_JUMBO */ 12709 12710 /* 12711 * Currently: 12712 * r0 holds resolved field 12713 * r9 holds object 12714 */ 12715.LOP_IPUT_BYTE_JUMBO_resolved: 12716 cmp r0, #0 @ resolution unsuccessful? 12717 beq common_exceptionThrown @ yes, throw exception 12718 @ fall through to OP_IPUT_BYTE_JUMBO_finish 12719 12720 /* 12721 * Currently: 12722 * r0 holds resolved field 12723 * r9 holds object 12724 */ 12725.LOP_IPUT_BYTE_JUMBO_finish: 12726 @bl common_squeak2 12727 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12728 FETCH(r1, 3) @ r1<- BBBB 12729 cmp r9, #0 @ check object for null 12730 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12731 beq common_errNullObject @ object was null 12732 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12733 GET_INST_OPCODE(ip) @ extract opcode from rINST 12734 @ no-op @ releasing store 12735 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12736 GOTO_OPCODE(ip) @ jump to next instruction 12737 12738/* continuation for OP_IPUT_CHAR_JUMBO */ 12739 12740 /* 12741 * Currently: 12742 * r0 holds resolved field 12743 * r9 holds object 12744 */ 12745.LOP_IPUT_CHAR_JUMBO_resolved: 12746 cmp r0, #0 @ resolution unsuccessful? 12747 beq common_exceptionThrown @ yes, throw exception 12748 @ fall through to OP_IPUT_CHAR_JUMBO_finish 12749 12750 /* 12751 * Currently: 12752 * r0 holds resolved field 12753 * r9 holds object 12754 */ 12755.LOP_IPUT_CHAR_JUMBO_finish: 12756 @bl common_squeak3 12757 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12758 FETCH(r1, 3) @ r1<- BBBB 12759 cmp r9, #0 @ check object for null 12760 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12761 beq common_errNullObject @ object was null 12762 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12763 GET_INST_OPCODE(ip) @ extract opcode from rINST 12764 @ no-op @ releasing store 12765 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12766 GOTO_OPCODE(ip) @ jump to next instruction 12767 12768/* continuation for OP_IPUT_SHORT_JUMBO */ 12769 12770 /* 12771 * Currently: 12772 * r0 holds resolved field 12773 * r9 holds object 12774 */ 12775.LOP_IPUT_SHORT_JUMBO_resolved: 12776 cmp r0, #0 @ resolution unsuccessful? 12777 beq common_exceptionThrown @ yes, throw exception 12778 @ fall through to OP_IPUT_SHORT_JUMBO_finish 12779 12780 /* 12781 * Currently: 12782 * r0 holds resolved field 12783 * r9 holds object 12784 */ 12785.LOP_IPUT_SHORT_JUMBO_finish: 12786 @bl common_squeak4 12787 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12788 FETCH(r1, 3) @ r1<- BBBB 12789 cmp r9, #0 @ check object for null 12790 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12791 beq common_errNullObject @ object was null 12792 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12793 GET_INST_OPCODE(ip) @ extract opcode from rINST 12794 @ no-op @ releasing store 12795 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12796 GOTO_OPCODE(ip) @ jump to next instruction 12797 12798/* continuation for OP_SGET_JUMBO */ 12799 12800 /* 12801 * Continuation if the field has not yet been resolved. 12802 * r1: AAAAAAAA field ref 12803 */ 12804.LOP_SGET_JUMBO_resolve: 12805 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12806 EXPORT_PC() @ resolve() could throw, so export now 12807 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12808 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12809 cmp r0, #0 @ success? 12810 bne .LOP_SGET_JUMBO_finish @ yes, finish 12811 b common_exceptionThrown @ no, handle exception 12812 12813/* continuation for OP_SGET_WIDE_JUMBO */ 12814 12815 /* 12816 * Continuation if the field has not yet been resolved. 12817 * r1: BBBB field ref 12818 * 12819 * Returns StaticField pointer in r0. 12820 */ 12821.LOP_SGET_WIDE_JUMBO_resolve: 12822 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12823 EXPORT_PC() @ resolve() could throw, so export now 12824 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12825 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12826 cmp r0, #0 @ success? 12827 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish 12828 b common_exceptionThrown @ no, handle exception 12829 12830/* continuation for OP_SGET_OBJECT_JUMBO */ 12831 12832 /* 12833 * Continuation if the field has not yet been resolved. 12834 * r1: AAAAAAAA field ref 12835 */ 12836.LOP_SGET_OBJECT_JUMBO_resolve: 12837 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12838 EXPORT_PC() @ resolve() could throw, so export now 12839 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12840 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12841 cmp r0, #0 @ success? 12842 bne .LOP_SGET_OBJECT_JUMBO_finish @ yes, finish 12843 b common_exceptionThrown @ no, handle exception 12844 12845/* continuation for OP_SGET_BOOLEAN_JUMBO */ 12846 12847 /* 12848 * Continuation if the field has not yet been resolved. 12849 * r1: AAAAAAAA field ref 12850 */ 12851.LOP_SGET_BOOLEAN_JUMBO_resolve: 12852 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12853 EXPORT_PC() @ resolve() could throw, so export now 12854 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12855 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12856 cmp r0, #0 @ success? 12857 bne .LOP_SGET_BOOLEAN_JUMBO_finish @ yes, finish 12858 b common_exceptionThrown @ no, handle exception 12859 12860/* continuation for OP_SGET_BYTE_JUMBO */ 12861 12862 /* 12863 * Continuation if the field has not yet been resolved. 12864 * r1: AAAAAAAA field ref 12865 */ 12866.LOP_SGET_BYTE_JUMBO_resolve: 12867 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12868 EXPORT_PC() @ resolve() could throw, so export now 12869 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12870 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12871 cmp r0, #0 @ success? 12872 bne .LOP_SGET_BYTE_JUMBO_finish @ yes, finish 12873 b common_exceptionThrown @ no, handle exception 12874 12875/* continuation for OP_SGET_CHAR_JUMBO */ 12876 12877 /* 12878 * Continuation if the field has not yet been resolved. 12879 * r1: AAAAAAAA field ref 12880 */ 12881.LOP_SGET_CHAR_JUMBO_resolve: 12882 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12883 EXPORT_PC() @ resolve() could throw, so export now 12884 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12885 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12886 cmp r0, #0 @ success? 12887 bne .LOP_SGET_CHAR_JUMBO_finish @ yes, finish 12888 b common_exceptionThrown @ no, handle exception 12889 12890/* continuation for OP_SGET_SHORT_JUMBO */ 12891 12892 /* 12893 * Continuation if the field has not yet been resolved. 12894 * r1: AAAAAAAA field ref 12895 */ 12896.LOP_SGET_SHORT_JUMBO_resolve: 12897 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12898 EXPORT_PC() @ resolve() could throw, so export now 12899 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12900 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12901 cmp r0, #0 @ success? 12902 bne .LOP_SGET_SHORT_JUMBO_finish @ yes, finish 12903 b common_exceptionThrown @ no, handle exception 12904 12905/* continuation for OP_SPUT_JUMBO */ 12906 12907 /* 12908 * Continuation if the field has not yet been resolved. 12909 * r1: AAAAAAAA field ref 12910 */ 12911.LOP_SPUT_JUMBO_resolve: 12912 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12913 EXPORT_PC() @ resolve() could throw, so export now 12914 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12915 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12916 cmp r0, #0 @ success? 12917 bne .LOP_SPUT_JUMBO_finish @ yes, finish 12918 b common_exceptionThrown @ no, handle exception 12919 12920/* continuation for OP_SPUT_WIDE_JUMBO */ 12921 12922 /* 12923 * Continuation if the field has not yet been resolved. 12924 * r1: BBBB field ref 12925 * r9: &fp[AA] 12926 * 12927 * Returns StaticField pointer in r2. 12928 */ 12929.LOP_SPUT_WIDE_JUMBO_resolve: 12930 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12931 EXPORT_PC() @ resolve() could throw, so export now 12932 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12933 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12934 cmp r0, #0 @ success? 12935 mov r2, r0 @ copy to r2 12936 bne .LOP_SPUT_WIDE_JUMBO_finish @ yes, finish 12937 b common_exceptionThrown @ no, handle exception 12938 12939/* continuation for OP_SPUT_OBJECT_JUMBO */ 12940 12941.LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0 12942 FETCH(r2, 3) @ r2<- BBBB 12943 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12944 GET_VREG(r1, r2) @ r1<- fp[BBBB] 12945 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12946 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 12947 GET_INST_OPCODE(ip) @ extract opcode from rINST 12948 @ no-op @ releasing store 12949 str r1, [r0, #offStaticField_value] @ field<- vBBBB 12950 cmp r1, #0 @ stored a null object? 12951 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12952 GOTO_OPCODE(ip) @ jump to next instruction 12953 12954/* continuation for OP_SPUT_BOOLEAN_JUMBO */ 12955 12956 /* 12957 * Continuation if the field has not yet been resolved. 12958 * r1: AAAAAAAA field ref 12959 */ 12960.LOP_SPUT_BOOLEAN_JUMBO_resolve: 12961 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12962 EXPORT_PC() @ resolve() could throw, so export now 12963 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12964 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12965 cmp r0, #0 @ success? 12966 bne .LOP_SPUT_BOOLEAN_JUMBO_finish @ yes, finish 12967 b common_exceptionThrown @ no, handle exception 12968 12969/* continuation for OP_SPUT_BYTE_JUMBO */ 12970 12971 /* 12972 * Continuation if the field has not yet been resolved. 12973 * r1: AAAAAAAA field ref 12974 */ 12975.LOP_SPUT_BYTE_JUMBO_resolve: 12976 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12977 EXPORT_PC() @ resolve() could throw, so export now 12978 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12979 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12980 cmp r0, #0 @ success? 12981 bne .LOP_SPUT_BYTE_JUMBO_finish @ yes, finish 12982 b common_exceptionThrown @ no, handle exception 12983 12984/* continuation for OP_SPUT_CHAR_JUMBO */ 12985 12986 /* 12987 * Continuation if the field has not yet been resolved. 12988 * r1: AAAAAAAA field ref 12989 */ 12990.LOP_SPUT_CHAR_JUMBO_resolve: 12991 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12992 EXPORT_PC() @ resolve() could throw, so export now 12993 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12994 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12995 cmp r0, #0 @ success? 12996 bne .LOP_SPUT_CHAR_JUMBO_finish @ yes, finish 12997 b common_exceptionThrown @ no, handle exception 12998 12999/* continuation for OP_SPUT_SHORT_JUMBO */ 13000 13001 /* 13002 * Continuation if the field has not yet been resolved. 13003 * r1: AAAAAAAA field ref 13004 */ 13005.LOP_SPUT_SHORT_JUMBO_resolve: 13006 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13007 EXPORT_PC() @ resolve() could throw, so export now 13008 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13009 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13010 cmp r0, #0 @ success? 13011 bne .LOP_SPUT_SHORT_JUMBO_finish @ yes, finish 13012 b common_exceptionThrown @ no, handle exception 13013 13014/* continuation for OP_INVOKE_VIRTUAL_JUMBO */ 13015 13016 /* 13017 * At this point: 13018 * r0 = resolved base method 13019 */ 13020.LOP_INVOKE_VIRTUAL_JUMBO_continue: 13021 FETCH(r10, 4) @ r10<- CCCC 13022 GET_VREG(r1, r10) @ r1<- "this" ptr 13023 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13024 cmp r1, #0 @ is "this" null? 13025 beq common_errNullObject @ null "this", throw exception 13026 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 13027 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 13028 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 13029 bl common_invokeMethodJumbo @ continue on 13030 13031/* continuation for OP_INVOKE_SUPER_JUMBO */ 13032 13033 /* 13034 * At this point: 13035 * r0 = resolved base method 13036 * r9 = method->clazz 13037 */ 13038.LOP_INVOKE_SUPER_JUMBO_continue: 13039 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 13040 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13041 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 13042 EXPORT_PC() @ must export for invoke 13043 cmp r2, r3 @ compare (methodIndex, vtableCount) 13044 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass 13045 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 13046 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 13047 bl common_invokeMethodJumbo @ continue on 13048 13049.LOP_INVOKE_SUPER_JUMBO_resolve: 13050 mov r0, r9 @ r0<- method->clazz 13051 mov r2, #METHOD_VIRTUAL @ resolver method type 13052 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13053 cmp r0, #0 @ got null? 13054 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue 13055 b common_exceptionThrown @ yes, handle exception 13056 13057 /* 13058 * Throw a NoSuchMethodError with the method name as the message. 13059 * r0 = resolved base method 13060 */ 13061.LOP_INVOKE_SUPER_JUMBO_nsm: 13062 ldr r1, [r0, #offMethod_name] @ r1<- method name 13063 b common_errNoSuchMethod 13064 13065/* continuation for OP_INVOKE_DIRECT_JUMBO */ 13066 13067 /* 13068 * On entry: 13069 * r1 = reference (CCCC) 13070 * r10 = "this" register 13071 */ 13072.LOP_INVOKE_DIRECT_JUMBO_resolve: 13073 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 13074 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 13075 mov r2, #METHOD_DIRECT @ resolver method type 13076 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13077 cmp r0, #0 @ got null? 13078 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 13079 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue 13080 b common_exceptionThrown @ yes, handle exception 13081 13082 .size dvmAsmSisterStart, .-dvmAsmSisterStart 13083 .global dvmAsmSisterEnd 13084dvmAsmSisterEnd: 13085 13086 13087 .global dvmAsmAltInstructionStart 13088 .type dvmAsmAltInstructionStart, %function 13089dvmAsmAltInstructionStart: 13090 .text 13091 13092/* ------------------------------ */ 13093 .balign 64 13094.L_ALT_OP_NOP: /* 0x00 */ 13095/* File: armv5te/alt_stub.S */ 13096/* 13097 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13098 * any interesting requests and then jump to the real instruction 13099 * handler. Note that the call to dvmCheckInst is done as a tail call. 13100 */ 13101 adrl lr, dvmAsmInstructionStart + (0 * 64) 13102 mov r0, rPC @ arg0 13103 mov r1, rSELF @ arg1 13104 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13105 13106/* ------------------------------ */ 13107 .balign 64 13108.L_ALT_OP_MOVE: /* 0x01 */ 13109/* File: armv5te/alt_stub.S */ 13110/* 13111 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13112 * any interesting requests and then jump to the real instruction 13113 * handler. Note that the call to dvmCheckInst is done as a tail call. 13114 */ 13115 adrl lr, dvmAsmInstructionStart + (1 * 64) 13116 mov r0, rPC @ arg0 13117 mov r1, rSELF @ arg1 13118 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13119 13120/* ------------------------------ */ 13121 .balign 64 13122.L_ALT_OP_MOVE_FROM16: /* 0x02 */ 13123/* File: armv5te/alt_stub.S */ 13124/* 13125 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13126 * any interesting requests and then jump to the real instruction 13127 * handler. Note that the call to dvmCheckInst is done as a tail call. 13128 */ 13129 adrl lr, dvmAsmInstructionStart + (2 * 64) 13130 mov r0, rPC @ arg0 13131 mov r1, rSELF @ arg1 13132 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13133 13134/* ------------------------------ */ 13135 .balign 64 13136.L_ALT_OP_MOVE_16: /* 0x03 */ 13137/* File: armv5te/alt_stub.S */ 13138/* 13139 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13140 * any interesting requests and then jump to the real instruction 13141 * handler. Note that the call to dvmCheckInst is done as a tail call. 13142 */ 13143 adrl lr, dvmAsmInstructionStart + (3 * 64) 13144 mov r0, rPC @ arg0 13145 mov r1, rSELF @ arg1 13146 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13147 13148/* ------------------------------ */ 13149 .balign 64 13150.L_ALT_OP_MOVE_WIDE: /* 0x04 */ 13151/* File: armv5te/alt_stub.S */ 13152/* 13153 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13154 * any interesting requests and then jump to the real instruction 13155 * handler. Note that the call to dvmCheckInst is done as a tail call. 13156 */ 13157 adrl lr, dvmAsmInstructionStart + (4 * 64) 13158 mov r0, rPC @ arg0 13159 mov r1, rSELF @ arg1 13160 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13161 13162/* ------------------------------ */ 13163 .balign 64 13164.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */ 13165/* File: armv5te/alt_stub.S */ 13166/* 13167 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13168 * any interesting requests and then jump to the real instruction 13169 * handler. Note that the call to dvmCheckInst is done as a tail call. 13170 */ 13171 adrl lr, dvmAsmInstructionStart + (5 * 64) 13172 mov r0, rPC @ arg0 13173 mov r1, rSELF @ arg1 13174 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13175 13176/* ------------------------------ */ 13177 .balign 64 13178.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */ 13179/* File: armv5te/alt_stub.S */ 13180/* 13181 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13182 * any interesting requests and then jump to the real instruction 13183 * handler. Note that the call to dvmCheckInst is done as a tail call. 13184 */ 13185 adrl lr, dvmAsmInstructionStart + (6 * 64) 13186 mov r0, rPC @ arg0 13187 mov r1, rSELF @ arg1 13188 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13189 13190/* ------------------------------ */ 13191 .balign 64 13192.L_ALT_OP_MOVE_OBJECT: /* 0x07 */ 13193/* File: armv5te/alt_stub.S */ 13194/* 13195 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13196 * any interesting requests and then jump to the real instruction 13197 * handler. Note that the call to dvmCheckInst is done as a tail call. 13198 */ 13199 adrl lr, dvmAsmInstructionStart + (7 * 64) 13200 mov r0, rPC @ arg0 13201 mov r1, rSELF @ arg1 13202 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13203 13204/* ------------------------------ */ 13205 .balign 64 13206.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 13207/* File: armv5te/alt_stub.S */ 13208/* 13209 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13210 * any interesting requests and then jump to the real instruction 13211 * handler. Note that the call to dvmCheckInst is done as a tail call. 13212 */ 13213 adrl lr, dvmAsmInstructionStart + (8 * 64) 13214 mov r0, rPC @ arg0 13215 mov r1, rSELF @ arg1 13216 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13217 13218/* ------------------------------ */ 13219 .balign 64 13220.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */ 13221/* File: armv5te/alt_stub.S */ 13222/* 13223 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13224 * any interesting requests and then jump to the real instruction 13225 * handler. Note that the call to dvmCheckInst is done as a tail call. 13226 */ 13227 adrl lr, dvmAsmInstructionStart + (9 * 64) 13228 mov r0, rPC @ arg0 13229 mov r1, rSELF @ arg1 13230 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13231 13232/* ------------------------------ */ 13233 .balign 64 13234.L_ALT_OP_MOVE_RESULT: /* 0x0a */ 13235/* File: armv5te/alt_stub.S */ 13236/* 13237 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13238 * any interesting requests and then jump to the real instruction 13239 * handler. Note that the call to dvmCheckInst is done as a tail call. 13240 */ 13241 adrl lr, dvmAsmInstructionStart + (10 * 64) 13242 mov r0, rPC @ arg0 13243 mov r1, rSELF @ arg1 13244 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13245 13246/* ------------------------------ */ 13247 .balign 64 13248.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */ 13249/* File: armv5te/alt_stub.S */ 13250/* 13251 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13252 * any interesting requests and then jump to the real instruction 13253 * handler. Note that the call to dvmCheckInst is done as a tail call. 13254 */ 13255 adrl lr, dvmAsmInstructionStart + (11 * 64) 13256 mov r0, rPC @ arg0 13257 mov r1, rSELF @ arg1 13258 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13259 13260/* ------------------------------ */ 13261 .balign 64 13262.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 13263/* File: armv5te/alt_stub.S */ 13264/* 13265 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13266 * any interesting requests and then jump to the real instruction 13267 * handler. Note that the call to dvmCheckInst is done as a tail call. 13268 */ 13269 adrl lr, dvmAsmInstructionStart + (12 * 64) 13270 mov r0, rPC @ arg0 13271 mov r1, rSELF @ arg1 13272 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13273 13274/* ------------------------------ */ 13275 .balign 64 13276.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */ 13277/* File: armv5te/alt_stub.S */ 13278/* 13279 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13280 * any interesting requests and then jump to the real instruction 13281 * handler. Note that the call to dvmCheckInst is done as a tail call. 13282 */ 13283 adrl lr, dvmAsmInstructionStart + (13 * 64) 13284 mov r0, rPC @ arg0 13285 mov r1, rSELF @ arg1 13286 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13287 13288/* ------------------------------ */ 13289 .balign 64 13290.L_ALT_OP_RETURN_VOID: /* 0x0e */ 13291/* File: armv5te/alt_stub.S */ 13292/* 13293 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13294 * any interesting requests and then jump to the real instruction 13295 * handler. Note that the call to dvmCheckInst is done as a tail call. 13296 */ 13297 adrl lr, dvmAsmInstructionStart + (14 * 64) 13298 mov r0, rPC @ arg0 13299 mov r1, rSELF @ arg1 13300 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13301 13302/* ------------------------------ */ 13303 .balign 64 13304.L_ALT_OP_RETURN: /* 0x0f */ 13305/* File: armv5te/alt_stub.S */ 13306/* 13307 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13308 * any interesting requests and then jump to the real instruction 13309 * handler. Note that the call to dvmCheckInst is done as a tail call. 13310 */ 13311 adrl lr, dvmAsmInstructionStart + (15 * 64) 13312 mov r0, rPC @ arg0 13313 mov r1, rSELF @ arg1 13314 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13315 13316/* ------------------------------ */ 13317 .balign 64 13318.L_ALT_OP_RETURN_WIDE: /* 0x10 */ 13319/* File: armv5te/alt_stub.S */ 13320/* 13321 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13322 * any interesting requests and then jump to the real instruction 13323 * handler. Note that the call to dvmCheckInst is done as a tail call. 13324 */ 13325 adrl lr, dvmAsmInstructionStart + (16 * 64) 13326 mov r0, rPC @ arg0 13327 mov r1, rSELF @ arg1 13328 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13329 13330/* ------------------------------ */ 13331 .balign 64 13332.L_ALT_OP_RETURN_OBJECT: /* 0x11 */ 13333/* File: armv5te/alt_stub.S */ 13334/* 13335 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13336 * any interesting requests and then jump to the real instruction 13337 * handler. Note that the call to dvmCheckInst is done as a tail call. 13338 */ 13339 adrl lr, dvmAsmInstructionStart + (17 * 64) 13340 mov r0, rPC @ arg0 13341 mov r1, rSELF @ arg1 13342 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13343 13344/* ------------------------------ */ 13345 .balign 64 13346.L_ALT_OP_CONST_4: /* 0x12 */ 13347/* File: armv5te/alt_stub.S */ 13348/* 13349 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13350 * any interesting requests and then jump to the real instruction 13351 * handler. Note that the call to dvmCheckInst is done as a tail call. 13352 */ 13353 adrl lr, dvmAsmInstructionStart + (18 * 64) 13354 mov r0, rPC @ arg0 13355 mov r1, rSELF @ arg1 13356 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13357 13358/* ------------------------------ */ 13359 .balign 64 13360.L_ALT_OP_CONST_16: /* 0x13 */ 13361/* File: armv5te/alt_stub.S */ 13362/* 13363 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13364 * any interesting requests and then jump to the real instruction 13365 * handler. Note that the call to dvmCheckInst is done as a tail call. 13366 */ 13367 adrl lr, dvmAsmInstructionStart + (19 * 64) 13368 mov r0, rPC @ arg0 13369 mov r1, rSELF @ arg1 13370 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13371 13372/* ------------------------------ */ 13373 .balign 64 13374.L_ALT_OP_CONST: /* 0x14 */ 13375/* File: armv5te/alt_stub.S */ 13376/* 13377 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13378 * any interesting requests and then jump to the real instruction 13379 * handler. Note that the call to dvmCheckInst is done as a tail call. 13380 */ 13381 adrl lr, dvmAsmInstructionStart + (20 * 64) 13382 mov r0, rPC @ arg0 13383 mov r1, rSELF @ arg1 13384 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13385 13386/* ------------------------------ */ 13387 .balign 64 13388.L_ALT_OP_CONST_HIGH16: /* 0x15 */ 13389/* File: armv5te/alt_stub.S */ 13390/* 13391 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13392 * any interesting requests and then jump to the real instruction 13393 * handler. Note that the call to dvmCheckInst is done as a tail call. 13394 */ 13395 adrl lr, dvmAsmInstructionStart + (21 * 64) 13396 mov r0, rPC @ arg0 13397 mov r1, rSELF @ arg1 13398 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13399 13400/* ------------------------------ */ 13401 .balign 64 13402.L_ALT_OP_CONST_WIDE_16: /* 0x16 */ 13403/* File: armv5te/alt_stub.S */ 13404/* 13405 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13406 * any interesting requests and then jump to the real instruction 13407 * handler. Note that the call to dvmCheckInst is done as a tail call. 13408 */ 13409 adrl lr, dvmAsmInstructionStart + (22 * 64) 13410 mov r0, rPC @ arg0 13411 mov r1, rSELF @ arg1 13412 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13413 13414/* ------------------------------ */ 13415 .balign 64 13416.L_ALT_OP_CONST_WIDE_32: /* 0x17 */ 13417/* File: armv5te/alt_stub.S */ 13418/* 13419 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13420 * any interesting requests and then jump to the real instruction 13421 * handler. Note that the call to dvmCheckInst is done as a tail call. 13422 */ 13423 adrl lr, dvmAsmInstructionStart + (23 * 64) 13424 mov r0, rPC @ arg0 13425 mov r1, rSELF @ arg1 13426 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13427 13428/* ------------------------------ */ 13429 .balign 64 13430.L_ALT_OP_CONST_WIDE: /* 0x18 */ 13431/* File: armv5te/alt_stub.S */ 13432/* 13433 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13434 * any interesting requests and then jump to the real instruction 13435 * handler. Note that the call to dvmCheckInst is done as a tail call. 13436 */ 13437 adrl lr, dvmAsmInstructionStart + (24 * 64) 13438 mov r0, rPC @ arg0 13439 mov r1, rSELF @ arg1 13440 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13441 13442/* ------------------------------ */ 13443 .balign 64 13444.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */ 13445/* File: armv5te/alt_stub.S */ 13446/* 13447 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13448 * any interesting requests and then jump to the real instruction 13449 * handler. Note that the call to dvmCheckInst is done as a tail call. 13450 */ 13451 adrl lr, dvmAsmInstructionStart + (25 * 64) 13452 mov r0, rPC @ arg0 13453 mov r1, rSELF @ arg1 13454 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13455 13456/* ------------------------------ */ 13457 .balign 64 13458.L_ALT_OP_CONST_STRING: /* 0x1a */ 13459/* File: armv5te/alt_stub.S */ 13460/* 13461 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13462 * any interesting requests and then jump to the real instruction 13463 * handler. Note that the call to dvmCheckInst is done as a tail call. 13464 */ 13465 adrl lr, dvmAsmInstructionStart + (26 * 64) 13466 mov r0, rPC @ arg0 13467 mov r1, rSELF @ arg1 13468 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13469 13470/* ------------------------------ */ 13471 .balign 64 13472.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */ 13473/* File: armv5te/alt_stub.S */ 13474/* 13475 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13476 * any interesting requests and then jump to the real instruction 13477 * handler. Note that the call to dvmCheckInst is done as a tail call. 13478 */ 13479 adrl lr, dvmAsmInstructionStart + (27 * 64) 13480 mov r0, rPC @ arg0 13481 mov r1, rSELF @ arg1 13482 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13483 13484/* ------------------------------ */ 13485 .balign 64 13486.L_ALT_OP_CONST_CLASS: /* 0x1c */ 13487/* File: armv5te/alt_stub.S */ 13488/* 13489 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13490 * any interesting requests and then jump to the real instruction 13491 * handler. Note that the call to dvmCheckInst is done as a tail call. 13492 */ 13493 adrl lr, dvmAsmInstructionStart + (28 * 64) 13494 mov r0, rPC @ arg0 13495 mov r1, rSELF @ arg1 13496 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13497 13498/* ------------------------------ */ 13499 .balign 64 13500.L_ALT_OP_MONITOR_ENTER: /* 0x1d */ 13501/* File: armv5te/alt_stub.S */ 13502/* 13503 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13504 * any interesting requests and then jump to the real instruction 13505 * handler. Note that the call to dvmCheckInst is done as a tail call. 13506 */ 13507 adrl lr, dvmAsmInstructionStart + (29 * 64) 13508 mov r0, rPC @ arg0 13509 mov r1, rSELF @ arg1 13510 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13511 13512/* ------------------------------ */ 13513 .balign 64 13514.L_ALT_OP_MONITOR_EXIT: /* 0x1e */ 13515/* File: armv5te/alt_stub.S */ 13516/* 13517 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13518 * any interesting requests and then jump to the real instruction 13519 * handler. Note that the call to dvmCheckInst is done as a tail call. 13520 */ 13521 adrl lr, dvmAsmInstructionStart + (30 * 64) 13522 mov r0, rPC @ arg0 13523 mov r1, rSELF @ arg1 13524 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13525 13526/* ------------------------------ */ 13527 .balign 64 13528.L_ALT_OP_CHECK_CAST: /* 0x1f */ 13529/* File: armv5te/alt_stub.S */ 13530/* 13531 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13532 * any interesting requests and then jump to the real instruction 13533 * handler. Note that the call to dvmCheckInst is done as a tail call. 13534 */ 13535 adrl lr, dvmAsmInstructionStart + (31 * 64) 13536 mov r0, rPC @ arg0 13537 mov r1, rSELF @ arg1 13538 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13539 13540/* ------------------------------ */ 13541 .balign 64 13542.L_ALT_OP_INSTANCE_OF: /* 0x20 */ 13543/* File: armv5te/alt_stub.S */ 13544/* 13545 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13546 * any interesting requests and then jump to the real instruction 13547 * handler. Note that the call to dvmCheckInst is done as a tail call. 13548 */ 13549 adrl lr, dvmAsmInstructionStart + (32 * 64) 13550 mov r0, rPC @ arg0 13551 mov r1, rSELF @ arg1 13552 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13553 13554/* ------------------------------ */ 13555 .balign 64 13556.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */ 13557/* File: armv5te/alt_stub.S */ 13558/* 13559 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13560 * any interesting requests and then jump to the real instruction 13561 * handler. Note that the call to dvmCheckInst is done as a tail call. 13562 */ 13563 adrl lr, dvmAsmInstructionStart + (33 * 64) 13564 mov r0, rPC @ arg0 13565 mov r1, rSELF @ arg1 13566 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13567 13568/* ------------------------------ */ 13569 .balign 64 13570.L_ALT_OP_NEW_INSTANCE: /* 0x22 */ 13571/* File: armv5te/alt_stub.S */ 13572/* 13573 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13574 * any interesting requests and then jump to the real instruction 13575 * handler. Note that the call to dvmCheckInst is done as a tail call. 13576 */ 13577 adrl lr, dvmAsmInstructionStart + (34 * 64) 13578 mov r0, rPC @ arg0 13579 mov r1, rSELF @ arg1 13580 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13581 13582/* ------------------------------ */ 13583 .balign 64 13584.L_ALT_OP_NEW_ARRAY: /* 0x23 */ 13585/* File: armv5te/alt_stub.S */ 13586/* 13587 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13588 * any interesting requests and then jump to the real instruction 13589 * handler. Note that the call to dvmCheckInst is done as a tail call. 13590 */ 13591 adrl lr, dvmAsmInstructionStart + (35 * 64) 13592 mov r0, rPC @ arg0 13593 mov r1, rSELF @ arg1 13594 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13595 13596/* ------------------------------ */ 13597 .balign 64 13598.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */ 13599/* File: armv5te/alt_stub.S */ 13600/* 13601 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13602 * any interesting requests and then jump to the real instruction 13603 * handler. Note that the call to dvmCheckInst is done as a tail call. 13604 */ 13605 adrl lr, dvmAsmInstructionStart + (36 * 64) 13606 mov r0, rPC @ arg0 13607 mov r1, rSELF @ arg1 13608 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13609 13610/* ------------------------------ */ 13611 .balign 64 13612.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 13613/* File: armv5te/alt_stub.S */ 13614/* 13615 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13616 * any interesting requests and then jump to the real instruction 13617 * handler. Note that the call to dvmCheckInst is done as a tail call. 13618 */ 13619 adrl lr, dvmAsmInstructionStart + (37 * 64) 13620 mov r0, rPC @ arg0 13621 mov r1, rSELF @ arg1 13622 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13623 13624/* ------------------------------ */ 13625 .balign 64 13626.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */ 13627/* File: armv5te/alt_stub.S */ 13628/* 13629 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13630 * any interesting requests and then jump to the real instruction 13631 * handler. Note that the call to dvmCheckInst is done as a tail call. 13632 */ 13633 adrl lr, dvmAsmInstructionStart + (38 * 64) 13634 mov r0, rPC @ arg0 13635 mov r1, rSELF @ arg1 13636 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13637 13638/* ------------------------------ */ 13639 .balign 64 13640.L_ALT_OP_THROW: /* 0x27 */ 13641/* File: armv5te/alt_stub.S */ 13642/* 13643 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13644 * any interesting requests and then jump to the real instruction 13645 * handler. Note that the call to dvmCheckInst is done as a tail call. 13646 */ 13647 adrl lr, dvmAsmInstructionStart + (39 * 64) 13648 mov r0, rPC @ arg0 13649 mov r1, rSELF @ arg1 13650 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13651 13652/* ------------------------------ */ 13653 .balign 64 13654.L_ALT_OP_GOTO: /* 0x28 */ 13655/* File: armv5te/alt_stub.S */ 13656/* 13657 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13658 * any interesting requests and then jump to the real instruction 13659 * handler. Note that the call to dvmCheckInst is done as a tail call. 13660 */ 13661 adrl lr, dvmAsmInstructionStart + (40 * 64) 13662 mov r0, rPC @ arg0 13663 mov r1, rSELF @ arg1 13664 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13665 13666/* ------------------------------ */ 13667 .balign 64 13668.L_ALT_OP_GOTO_16: /* 0x29 */ 13669/* File: armv5te/alt_stub.S */ 13670/* 13671 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13672 * any interesting requests and then jump to the real instruction 13673 * handler. Note that the call to dvmCheckInst is done as a tail call. 13674 */ 13675 adrl lr, dvmAsmInstructionStart + (41 * 64) 13676 mov r0, rPC @ arg0 13677 mov r1, rSELF @ arg1 13678 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13679 13680/* ------------------------------ */ 13681 .balign 64 13682.L_ALT_OP_GOTO_32: /* 0x2a */ 13683/* File: armv5te/alt_stub.S */ 13684/* 13685 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13686 * any interesting requests and then jump to the real instruction 13687 * handler. Note that the call to dvmCheckInst is done as a tail call. 13688 */ 13689 adrl lr, dvmAsmInstructionStart + (42 * 64) 13690 mov r0, rPC @ arg0 13691 mov r1, rSELF @ arg1 13692 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13693 13694/* ------------------------------ */ 13695 .balign 64 13696.L_ALT_OP_PACKED_SWITCH: /* 0x2b */ 13697/* File: armv5te/alt_stub.S */ 13698/* 13699 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13700 * any interesting requests and then jump to the real instruction 13701 * handler. Note that the call to dvmCheckInst is done as a tail call. 13702 */ 13703 adrl lr, dvmAsmInstructionStart + (43 * 64) 13704 mov r0, rPC @ arg0 13705 mov r1, rSELF @ arg1 13706 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13707 13708/* ------------------------------ */ 13709 .balign 64 13710.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */ 13711/* File: armv5te/alt_stub.S */ 13712/* 13713 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13714 * any interesting requests and then jump to the real instruction 13715 * handler. Note that the call to dvmCheckInst is done as a tail call. 13716 */ 13717 adrl lr, dvmAsmInstructionStart + (44 * 64) 13718 mov r0, rPC @ arg0 13719 mov r1, rSELF @ arg1 13720 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13721 13722/* ------------------------------ */ 13723 .balign 64 13724.L_ALT_OP_CMPL_FLOAT: /* 0x2d */ 13725/* File: armv5te/alt_stub.S */ 13726/* 13727 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13728 * any interesting requests and then jump to the real instruction 13729 * handler. Note that the call to dvmCheckInst is done as a tail call. 13730 */ 13731 adrl lr, dvmAsmInstructionStart + (45 * 64) 13732 mov r0, rPC @ arg0 13733 mov r1, rSELF @ arg1 13734 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13735 13736/* ------------------------------ */ 13737 .balign 64 13738.L_ALT_OP_CMPG_FLOAT: /* 0x2e */ 13739/* File: armv5te/alt_stub.S */ 13740/* 13741 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13742 * any interesting requests and then jump to the real instruction 13743 * handler. Note that the call to dvmCheckInst is done as a tail call. 13744 */ 13745 adrl lr, dvmAsmInstructionStart + (46 * 64) 13746 mov r0, rPC @ arg0 13747 mov r1, rSELF @ arg1 13748 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13749 13750/* ------------------------------ */ 13751 .balign 64 13752.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */ 13753/* File: armv5te/alt_stub.S */ 13754/* 13755 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13756 * any interesting requests and then jump to the real instruction 13757 * handler. Note that the call to dvmCheckInst is done as a tail call. 13758 */ 13759 adrl lr, dvmAsmInstructionStart + (47 * 64) 13760 mov r0, rPC @ arg0 13761 mov r1, rSELF @ arg1 13762 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13763 13764/* ------------------------------ */ 13765 .balign 64 13766.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */ 13767/* File: armv5te/alt_stub.S */ 13768/* 13769 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13770 * any interesting requests and then jump to the real instruction 13771 * handler. Note that the call to dvmCheckInst is done as a tail call. 13772 */ 13773 adrl lr, dvmAsmInstructionStart + (48 * 64) 13774 mov r0, rPC @ arg0 13775 mov r1, rSELF @ arg1 13776 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13777 13778/* ------------------------------ */ 13779 .balign 64 13780.L_ALT_OP_CMP_LONG: /* 0x31 */ 13781/* File: armv5te/alt_stub.S */ 13782/* 13783 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13784 * any interesting requests and then jump to the real instruction 13785 * handler. Note that the call to dvmCheckInst is done as a tail call. 13786 */ 13787 adrl lr, dvmAsmInstructionStart + (49 * 64) 13788 mov r0, rPC @ arg0 13789 mov r1, rSELF @ arg1 13790 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13791 13792/* ------------------------------ */ 13793 .balign 64 13794.L_ALT_OP_IF_EQ: /* 0x32 */ 13795/* File: armv5te/alt_stub.S */ 13796/* 13797 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13798 * any interesting requests and then jump to the real instruction 13799 * handler. Note that the call to dvmCheckInst is done as a tail call. 13800 */ 13801 adrl lr, dvmAsmInstructionStart + (50 * 64) 13802 mov r0, rPC @ arg0 13803 mov r1, rSELF @ arg1 13804 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13805 13806/* ------------------------------ */ 13807 .balign 64 13808.L_ALT_OP_IF_NE: /* 0x33 */ 13809/* File: armv5te/alt_stub.S */ 13810/* 13811 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13812 * any interesting requests and then jump to the real instruction 13813 * handler. Note that the call to dvmCheckInst is done as a tail call. 13814 */ 13815 adrl lr, dvmAsmInstructionStart + (51 * 64) 13816 mov r0, rPC @ arg0 13817 mov r1, rSELF @ arg1 13818 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13819 13820/* ------------------------------ */ 13821 .balign 64 13822.L_ALT_OP_IF_LT: /* 0x34 */ 13823/* File: armv5te/alt_stub.S */ 13824/* 13825 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13826 * any interesting requests and then jump to the real instruction 13827 * handler. Note that the call to dvmCheckInst is done as a tail call. 13828 */ 13829 adrl lr, dvmAsmInstructionStart + (52 * 64) 13830 mov r0, rPC @ arg0 13831 mov r1, rSELF @ arg1 13832 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13833 13834/* ------------------------------ */ 13835 .balign 64 13836.L_ALT_OP_IF_GE: /* 0x35 */ 13837/* File: armv5te/alt_stub.S */ 13838/* 13839 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13840 * any interesting requests and then jump to the real instruction 13841 * handler. Note that the call to dvmCheckInst is done as a tail call. 13842 */ 13843 adrl lr, dvmAsmInstructionStart + (53 * 64) 13844 mov r0, rPC @ arg0 13845 mov r1, rSELF @ arg1 13846 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13847 13848/* ------------------------------ */ 13849 .balign 64 13850.L_ALT_OP_IF_GT: /* 0x36 */ 13851/* File: armv5te/alt_stub.S */ 13852/* 13853 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13854 * any interesting requests and then jump to the real instruction 13855 * handler. Note that the call to dvmCheckInst is done as a tail call. 13856 */ 13857 adrl lr, dvmAsmInstructionStart + (54 * 64) 13858 mov r0, rPC @ arg0 13859 mov r1, rSELF @ arg1 13860 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13861 13862/* ------------------------------ */ 13863 .balign 64 13864.L_ALT_OP_IF_LE: /* 0x37 */ 13865/* File: armv5te/alt_stub.S */ 13866/* 13867 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13868 * any interesting requests and then jump to the real instruction 13869 * handler. Note that the call to dvmCheckInst is done as a tail call. 13870 */ 13871 adrl lr, dvmAsmInstructionStart + (55 * 64) 13872 mov r0, rPC @ arg0 13873 mov r1, rSELF @ arg1 13874 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13875 13876/* ------------------------------ */ 13877 .balign 64 13878.L_ALT_OP_IF_EQZ: /* 0x38 */ 13879/* File: armv5te/alt_stub.S */ 13880/* 13881 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13882 * any interesting requests and then jump to the real instruction 13883 * handler. Note that the call to dvmCheckInst is done as a tail call. 13884 */ 13885 adrl lr, dvmAsmInstructionStart + (56 * 64) 13886 mov r0, rPC @ arg0 13887 mov r1, rSELF @ arg1 13888 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13889 13890/* ------------------------------ */ 13891 .balign 64 13892.L_ALT_OP_IF_NEZ: /* 0x39 */ 13893/* File: armv5te/alt_stub.S */ 13894/* 13895 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13896 * any interesting requests and then jump to the real instruction 13897 * handler. Note that the call to dvmCheckInst is done as a tail call. 13898 */ 13899 adrl lr, dvmAsmInstructionStart + (57 * 64) 13900 mov r0, rPC @ arg0 13901 mov r1, rSELF @ arg1 13902 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13903 13904/* ------------------------------ */ 13905 .balign 64 13906.L_ALT_OP_IF_LTZ: /* 0x3a */ 13907/* File: armv5te/alt_stub.S */ 13908/* 13909 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13910 * any interesting requests and then jump to the real instruction 13911 * handler. Note that the call to dvmCheckInst is done as a tail call. 13912 */ 13913 adrl lr, dvmAsmInstructionStart + (58 * 64) 13914 mov r0, rPC @ arg0 13915 mov r1, rSELF @ arg1 13916 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13917 13918/* ------------------------------ */ 13919 .balign 64 13920.L_ALT_OP_IF_GEZ: /* 0x3b */ 13921/* File: armv5te/alt_stub.S */ 13922/* 13923 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13924 * any interesting requests and then jump to the real instruction 13925 * handler. Note that the call to dvmCheckInst is done as a tail call. 13926 */ 13927 adrl lr, dvmAsmInstructionStart + (59 * 64) 13928 mov r0, rPC @ arg0 13929 mov r1, rSELF @ arg1 13930 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13931 13932/* ------------------------------ */ 13933 .balign 64 13934.L_ALT_OP_IF_GTZ: /* 0x3c */ 13935/* File: armv5te/alt_stub.S */ 13936/* 13937 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13938 * any interesting requests and then jump to the real instruction 13939 * handler. Note that the call to dvmCheckInst is done as a tail call. 13940 */ 13941 adrl lr, dvmAsmInstructionStart + (60 * 64) 13942 mov r0, rPC @ arg0 13943 mov r1, rSELF @ arg1 13944 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13945 13946/* ------------------------------ */ 13947 .balign 64 13948.L_ALT_OP_IF_LEZ: /* 0x3d */ 13949/* File: armv5te/alt_stub.S */ 13950/* 13951 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13952 * any interesting requests and then jump to the real instruction 13953 * handler. Note that the call to dvmCheckInst is done as a tail call. 13954 */ 13955 adrl lr, dvmAsmInstructionStart + (61 * 64) 13956 mov r0, rPC @ arg0 13957 mov r1, rSELF @ arg1 13958 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13959 13960/* ------------------------------ */ 13961 .balign 64 13962.L_ALT_OP_UNUSED_3E: /* 0x3e */ 13963/* File: armv5te/alt_stub.S */ 13964/* 13965 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13966 * any interesting requests and then jump to the real instruction 13967 * handler. Note that the call to dvmCheckInst is done as a tail call. 13968 */ 13969 adrl lr, dvmAsmInstructionStart + (62 * 64) 13970 mov r0, rPC @ arg0 13971 mov r1, rSELF @ arg1 13972 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13973 13974/* ------------------------------ */ 13975 .balign 64 13976.L_ALT_OP_UNUSED_3F: /* 0x3f */ 13977/* File: armv5te/alt_stub.S */ 13978/* 13979 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13980 * any interesting requests and then jump to the real instruction 13981 * handler. Note that the call to dvmCheckInst is done as a tail call. 13982 */ 13983 adrl lr, dvmAsmInstructionStart + (63 * 64) 13984 mov r0, rPC @ arg0 13985 mov r1, rSELF @ arg1 13986 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13987 13988/* ------------------------------ */ 13989 .balign 64 13990.L_ALT_OP_UNUSED_40: /* 0x40 */ 13991/* File: armv5te/alt_stub.S */ 13992/* 13993 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13994 * any interesting requests and then jump to the real instruction 13995 * handler. Note that the call to dvmCheckInst is done as a tail call. 13996 */ 13997 adrl lr, dvmAsmInstructionStart + (64 * 64) 13998 mov r0, rPC @ arg0 13999 mov r1, rSELF @ arg1 14000 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14001 14002/* ------------------------------ */ 14003 .balign 64 14004.L_ALT_OP_UNUSED_41: /* 0x41 */ 14005/* File: armv5te/alt_stub.S */ 14006/* 14007 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14008 * any interesting requests and then jump to the real instruction 14009 * handler. Note that the call to dvmCheckInst is done as a tail call. 14010 */ 14011 adrl lr, dvmAsmInstructionStart + (65 * 64) 14012 mov r0, rPC @ arg0 14013 mov r1, rSELF @ arg1 14014 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14015 14016/* ------------------------------ */ 14017 .balign 64 14018.L_ALT_OP_UNUSED_42: /* 0x42 */ 14019/* File: armv5te/alt_stub.S */ 14020/* 14021 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14022 * any interesting requests and then jump to the real instruction 14023 * handler. Note that the call to dvmCheckInst is done as a tail call. 14024 */ 14025 adrl lr, dvmAsmInstructionStart + (66 * 64) 14026 mov r0, rPC @ arg0 14027 mov r1, rSELF @ arg1 14028 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14029 14030/* ------------------------------ */ 14031 .balign 64 14032.L_ALT_OP_UNUSED_43: /* 0x43 */ 14033/* File: armv5te/alt_stub.S */ 14034/* 14035 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14036 * any interesting requests and then jump to the real instruction 14037 * handler. Note that the call to dvmCheckInst is done as a tail call. 14038 */ 14039 adrl lr, dvmAsmInstructionStart + (67 * 64) 14040 mov r0, rPC @ arg0 14041 mov r1, rSELF @ arg1 14042 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14043 14044/* ------------------------------ */ 14045 .balign 64 14046.L_ALT_OP_AGET: /* 0x44 */ 14047/* File: armv5te/alt_stub.S */ 14048/* 14049 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14050 * any interesting requests and then jump to the real instruction 14051 * handler. Note that the call to dvmCheckInst is done as a tail call. 14052 */ 14053 adrl lr, dvmAsmInstructionStart + (68 * 64) 14054 mov r0, rPC @ arg0 14055 mov r1, rSELF @ arg1 14056 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14057 14058/* ------------------------------ */ 14059 .balign 64 14060.L_ALT_OP_AGET_WIDE: /* 0x45 */ 14061/* File: armv5te/alt_stub.S */ 14062/* 14063 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14064 * any interesting requests and then jump to the real instruction 14065 * handler. Note that the call to dvmCheckInst is done as a tail call. 14066 */ 14067 adrl lr, dvmAsmInstructionStart + (69 * 64) 14068 mov r0, rPC @ arg0 14069 mov r1, rSELF @ arg1 14070 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14071 14072/* ------------------------------ */ 14073 .balign 64 14074.L_ALT_OP_AGET_OBJECT: /* 0x46 */ 14075/* File: armv5te/alt_stub.S */ 14076/* 14077 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14078 * any interesting requests and then jump to the real instruction 14079 * handler. Note that the call to dvmCheckInst is done as a tail call. 14080 */ 14081 adrl lr, dvmAsmInstructionStart + (70 * 64) 14082 mov r0, rPC @ arg0 14083 mov r1, rSELF @ arg1 14084 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14085 14086/* ------------------------------ */ 14087 .balign 64 14088.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */ 14089/* File: armv5te/alt_stub.S */ 14090/* 14091 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14092 * any interesting requests and then jump to the real instruction 14093 * handler. Note that the call to dvmCheckInst is done as a tail call. 14094 */ 14095 adrl lr, dvmAsmInstructionStart + (71 * 64) 14096 mov r0, rPC @ arg0 14097 mov r1, rSELF @ arg1 14098 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14099 14100/* ------------------------------ */ 14101 .balign 64 14102.L_ALT_OP_AGET_BYTE: /* 0x48 */ 14103/* File: armv5te/alt_stub.S */ 14104/* 14105 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14106 * any interesting requests and then jump to the real instruction 14107 * handler. Note that the call to dvmCheckInst is done as a tail call. 14108 */ 14109 adrl lr, dvmAsmInstructionStart + (72 * 64) 14110 mov r0, rPC @ arg0 14111 mov r1, rSELF @ arg1 14112 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14113 14114/* ------------------------------ */ 14115 .balign 64 14116.L_ALT_OP_AGET_CHAR: /* 0x49 */ 14117/* File: armv5te/alt_stub.S */ 14118/* 14119 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14120 * any interesting requests and then jump to the real instruction 14121 * handler. Note that the call to dvmCheckInst is done as a tail call. 14122 */ 14123 adrl lr, dvmAsmInstructionStart + (73 * 64) 14124 mov r0, rPC @ arg0 14125 mov r1, rSELF @ arg1 14126 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14127 14128/* ------------------------------ */ 14129 .balign 64 14130.L_ALT_OP_AGET_SHORT: /* 0x4a */ 14131/* File: armv5te/alt_stub.S */ 14132/* 14133 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14134 * any interesting requests and then jump to the real instruction 14135 * handler. Note that the call to dvmCheckInst is done as a tail call. 14136 */ 14137 adrl lr, dvmAsmInstructionStart + (74 * 64) 14138 mov r0, rPC @ arg0 14139 mov r1, rSELF @ arg1 14140 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14141 14142/* ------------------------------ */ 14143 .balign 64 14144.L_ALT_OP_APUT: /* 0x4b */ 14145/* File: armv5te/alt_stub.S */ 14146/* 14147 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14148 * any interesting requests and then jump to the real instruction 14149 * handler. Note that the call to dvmCheckInst is done as a tail call. 14150 */ 14151 adrl lr, dvmAsmInstructionStart + (75 * 64) 14152 mov r0, rPC @ arg0 14153 mov r1, rSELF @ arg1 14154 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14155 14156/* ------------------------------ */ 14157 .balign 64 14158.L_ALT_OP_APUT_WIDE: /* 0x4c */ 14159/* File: armv5te/alt_stub.S */ 14160/* 14161 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14162 * any interesting requests and then jump to the real instruction 14163 * handler. Note that the call to dvmCheckInst is done as a tail call. 14164 */ 14165 adrl lr, dvmAsmInstructionStart + (76 * 64) 14166 mov r0, rPC @ arg0 14167 mov r1, rSELF @ arg1 14168 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14169 14170/* ------------------------------ */ 14171 .balign 64 14172.L_ALT_OP_APUT_OBJECT: /* 0x4d */ 14173/* File: armv5te/alt_stub.S */ 14174/* 14175 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14176 * any interesting requests and then jump to the real instruction 14177 * handler. Note that the call to dvmCheckInst is done as a tail call. 14178 */ 14179 adrl lr, dvmAsmInstructionStart + (77 * 64) 14180 mov r0, rPC @ arg0 14181 mov r1, rSELF @ arg1 14182 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14183 14184/* ------------------------------ */ 14185 .balign 64 14186.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */ 14187/* File: armv5te/alt_stub.S */ 14188/* 14189 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14190 * any interesting requests and then jump to the real instruction 14191 * handler. Note that the call to dvmCheckInst is done as a tail call. 14192 */ 14193 adrl lr, dvmAsmInstructionStart + (78 * 64) 14194 mov r0, rPC @ arg0 14195 mov r1, rSELF @ arg1 14196 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14197 14198/* ------------------------------ */ 14199 .balign 64 14200.L_ALT_OP_APUT_BYTE: /* 0x4f */ 14201/* File: armv5te/alt_stub.S */ 14202/* 14203 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14204 * any interesting requests and then jump to the real instruction 14205 * handler. Note that the call to dvmCheckInst is done as a tail call. 14206 */ 14207 adrl lr, dvmAsmInstructionStart + (79 * 64) 14208 mov r0, rPC @ arg0 14209 mov r1, rSELF @ arg1 14210 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14211 14212/* ------------------------------ */ 14213 .balign 64 14214.L_ALT_OP_APUT_CHAR: /* 0x50 */ 14215/* File: armv5te/alt_stub.S */ 14216/* 14217 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14218 * any interesting requests and then jump to the real instruction 14219 * handler. Note that the call to dvmCheckInst is done as a tail call. 14220 */ 14221 adrl lr, dvmAsmInstructionStart + (80 * 64) 14222 mov r0, rPC @ arg0 14223 mov r1, rSELF @ arg1 14224 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14225 14226/* ------------------------------ */ 14227 .balign 64 14228.L_ALT_OP_APUT_SHORT: /* 0x51 */ 14229/* File: armv5te/alt_stub.S */ 14230/* 14231 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14232 * any interesting requests and then jump to the real instruction 14233 * handler. Note that the call to dvmCheckInst is done as a tail call. 14234 */ 14235 adrl lr, dvmAsmInstructionStart + (81 * 64) 14236 mov r0, rPC @ arg0 14237 mov r1, rSELF @ arg1 14238 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14239 14240/* ------------------------------ */ 14241 .balign 64 14242.L_ALT_OP_IGET: /* 0x52 */ 14243/* File: armv5te/alt_stub.S */ 14244/* 14245 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14246 * any interesting requests and then jump to the real instruction 14247 * handler. Note that the call to dvmCheckInst is done as a tail call. 14248 */ 14249 adrl lr, dvmAsmInstructionStart + (82 * 64) 14250 mov r0, rPC @ arg0 14251 mov r1, rSELF @ arg1 14252 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14253 14254/* ------------------------------ */ 14255 .balign 64 14256.L_ALT_OP_IGET_WIDE: /* 0x53 */ 14257/* File: armv5te/alt_stub.S */ 14258/* 14259 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14260 * any interesting requests and then jump to the real instruction 14261 * handler. Note that the call to dvmCheckInst is done as a tail call. 14262 */ 14263 adrl lr, dvmAsmInstructionStart + (83 * 64) 14264 mov r0, rPC @ arg0 14265 mov r1, rSELF @ arg1 14266 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14267 14268/* ------------------------------ */ 14269 .balign 64 14270.L_ALT_OP_IGET_OBJECT: /* 0x54 */ 14271/* File: armv5te/alt_stub.S */ 14272/* 14273 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14274 * any interesting requests and then jump to the real instruction 14275 * handler. Note that the call to dvmCheckInst is done as a tail call. 14276 */ 14277 adrl lr, dvmAsmInstructionStart + (84 * 64) 14278 mov r0, rPC @ arg0 14279 mov r1, rSELF @ arg1 14280 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14281 14282/* ------------------------------ */ 14283 .balign 64 14284.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */ 14285/* File: armv5te/alt_stub.S */ 14286/* 14287 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14288 * any interesting requests and then jump to the real instruction 14289 * handler. Note that the call to dvmCheckInst is done as a tail call. 14290 */ 14291 adrl lr, dvmAsmInstructionStart + (85 * 64) 14292 mov r0, rPC @ arg0 14293 mov r1, rSELF @ arg1 14294 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14295 14296/* ------------------------------ */ 14297 .balign 64 14298.L_ALT_OP_IGET_BYTE: /* 0x56 */ 14299/* File: armv5te/alt_stub.S */ 14300/* 14301 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14302 * any interesting requests and then jump to the real instruction 14303 * handler. Note that the call to dvmCheckInst is done as a tail call. 14304 */ 14305 adrl lr, dvmAsmInstructionStart + (86 * 64) 14306 mov r0, rPC @ arg0 14307 mov r1, rSELF @ arg1 14308 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14309 14310/* ------------------------------ */ 14311 .balign 64 14312.L_ALT_OP_IGET_CHAR: /* 0x57 */ 14313/* File: armv5te/alt_stub.S */ 14314/* 14315 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14316 * any interesting requests and then jump to the real instruction 14317 * handler. Note that the call to dvmCheckInst is done as a tail call. 14318 */ 14319 adrl lr, dvmAsmInstructionStart + (87 * 64) 14320 mov r0, rPC @ arg0 14321 mov r1, rSELF @ arg1 14322 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14323 14324/* ------------------------------ */ 14325 .balign 64 14326.L_ALT_OP_IGET_SHORT: /* 0x58 */ 14327/* File: armv5te/alt_stub.S */ 14328/* 14329 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14330 * any interesting requests and then jump to the real instruction 14331 * handler. Note that the call to dvmCheckInst is done as a tail call. 14332 */ 14333 adrl lr, dvmAsmInstructionStart + (88 * 64) 14334 mov r0, rPC @ arg0 14335 mov r1, rSELF @ arg1 14336 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14337 14338/* ------------------------------ */ 14339 .balign 64 14340.L_ALT_OP_IPUT: /* 0x59 */ 14341/* File: armv5te/alt_stub.S */ 14342/* 14343 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14344 * any interesting requests and then jump to the real instruction 14345 * handler. Note that the call to dvmCheckInst is done as a tail call. 14346 */ 14347 adrl lr, dvmAsmInstructionStart + (89 * 64) 14348 mov r0, rPC @ arg0 14349 mov r1, rSELF @ arg1 14350 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14351 14352/* ------------------------------ */ 14353 .balign 64 14354.L_ALT_OP_IPUT_WIDE: /* 0x5a */ 14355/* File: armv5te/alt_stub.S */ 14356/* 14357 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14358 * any interesting requests and then jump to the real instruction 14359 * handler. Note that the call to dvmCheckInst is done as a tail call. 14360 */ 14361 adrl lr, dvmAsmInstructionStart + (90 * 64) 14362 mov r0, rPC @ arg0 14363 mov r1, rSELF @ arg1 14364 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14365 14366/* ------------------------------ */ 14367 .balign 64 14368.L_ALT_OP_IPUT_OBJECT: /* 0x5b */ 14369/* File: armv5te/alt_stub.S */ 14370/* 14371 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14372 * any interesting requests and then jump to the real instruction 14373 * handler. Note that the call to dvmCheckInst is done as a tail call. 14374 */ 14375 adrl lr, dvmAsmInstructionStart + (91 * 64) 14376 mov r0, rPC @ arg0 14377 mov r1, rSELF @ arg1 14378 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14379 14380/* ------------------------------ */ 14381 .balign 64 14382.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */ 14383/* File: armv5te/alt_stub.S */ 14384/* 14385 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14386 * any interesting requests and then jump to the real instruction 14387 * handler. Note that the call to dvmCheckInst is done as a tail call. 14388 */ 14389 adrl lr, dvmAsmInstructionStart + (92 * 64) 14390 mov r0, rPC @ arg0 14391 mov r1, rSELF @ arg1 14392 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14393 14394/* ------------------------------ */ 14395 .balign 64 14396.L_ALT_OP_IPUT_BYTE: /* 0x5d */ 14397/* File: armv5te/alt_stub.S */ 14398/* 14399 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14400 * any interesting requests and then jump to the real instruction 14401 * handler. Note that the call to dvmCheckInst is done as a tail call. 14402 */ 14403 adrl lr, dvmAsmInstructionStart + (93 * 64) 14404 mov r0, rPC @ arg0 14405 mov r1, rSELF @ arg1 14406 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14407 14408/* ------------------------------ */ 14409 .balign 64 14410.L_ALT_OP_IPUT_CHAR: /* 0x5e */ 14411/* File: armv5te/alt_stub.S */ 14412/* 14413 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14414 * any interesting requests and then jump to the real instruction 14415 * handler. Note that the call to dvmCheckInst is done as a tail call. 14416 */ 14417 adrl lr, dvmAsmInstructionStart + (94 * 64) 14418 mov r0, rPC @ arg0 14419 mov r1, rSELF @ arg1 14420 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14421 14422/* ------------------------------ */ 14423 .balign 64 14424.L_ALT_OP_IPUT_SHORT: /* 0x5f */ 14425/* File: armv5te/alt_stub.S */ 14426/* 14427 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14428 * any interesting requests and then jump to the real instruction 14429 * handler. Note that the call to dvmCheckInst is done as a tail call. 14430 */ 14431 adrl lr, dvmAsmInstructionStart + (95 * 64) 14432 mov r0, rPC @ arg0 14433 mov r1, rSELF @ arg1 14434 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14435 14436/* ------------------------------ */ 14437 .balign 64 14438.L_ALT_OP_SGET: /* 0x60 */ 14439/* File: armv5te/alt_stub.S */ 14440/* 14441 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14442 * any interesting requests and then jump to the real instruction 14443 * handler. Note that the call to dvmCheckInst is done as a tail call. 14444 */ 14445 adrl lr, dvmAsmInstructionStart + (96 * 64) 14446 mov r0, rPC @ arg0 14447 mov r1, rSELF @ arg1 14448 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14449 14450/* ------------------------------ */ 14451 .balign 64 14452.L_ALT_OP_SGET_WIDE: /* 0x61 */ 14453/* File: armv5te/alt_stub.S */ 14454/* 14455 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14456 * any interesting requests and then jump to the real instruction 14457 * handler. Note that the call to dvmCheckInst is done as a tail call. 14458 */ 14459 adrl lr, dvmAsmInstructionStart + (97 * 64) 14460 mov r0, rPC @ arg0 14461 mov r1, rSELF @ arg1 14462 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14463 14464/* ------------------------------ */ 14465 .balign 64 14466.L_ALT_OP_SGET_OBJECT: /* 0x62 */ 14467/* File: armv5te/alt_stub.S */ 14468/* 14469 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14470 * any interesting requests and then jump to the real instruction 14471 * handler. Note that the call to dvmCheckInst is done as a tail call. 14472 */ 14473 adrl lr, dvmAsmInstructionStart + (98 * 64) 14474 mov r0, rPC @ arg0 14475 mov r1, rSELF @ arg1 14476 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14477 14478/* ------------------------------ */ 14479 .balign 64 14480.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */ 14481/* File: armv5te/alt_stub.S */ 14482/* 14483 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14484 * any interesting requests and then jump to the real instruction 14485 * handler. Note that the call to dvmCheckInst is done as a tail call. 14486 */ 14487 adrl lr, dvmAsmInstructionStart + (99 * 64) 14488 mov r0, rPC @ arg0 14489 mov r1, rSELF @ arg1 14490 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14491 14492/* ------------------------------ */ 14493 .balign 64 14494.L_ALT_OP_SGET_BYTE: /* 0x64 */ 14495/* File: armv5te/alt_stub.S */ 14496/* 14497 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14498 * any interesting requests and then jump to the real instruction 14499 * handler. Note that the call to dvmCheckInst is done as a tail call. 14500 */ 14501 adrl lr, dvmAsmInstructionStart + (100 * 64) 14502 mov r0, rPC @ arg0 14503 mov r1, rSELF @ arg1 14504 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14505 14506/* ------------------------------ */ 14507 .balign 64 14508.L_ALT_OP_SGET_CHAR: /* 0x65 */ 14509/* File: armv5te/alt_stub.S */ 14510/* 14511 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14512 * any interesting requests and then jump to the real instruction 14513 * handler. Note that the call to dvmCheckInst is done as a tail call. 14514 */ 14515 adrl lr, dvmAsmInstructionStart + (101 * 64) 14516 mov r0, rPC @ arg0 14517 mov r1, rSELF @ arg1 14518 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14519 14520/* ------------------------------ */ 14521 .balign 64 14522.L_ALT_OP_SGET_SHORT: /* 0x66 */ 14523/* File: armv5te/alt_stub.S */ 14524/* 14525 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14526 * any interesting requests and then jump to the real instruction 14527 * handler. Note that the call to dvmCheckInst is done as a tail call. 14528 */ 14529 adrl lr, dvmAsmInstructionStart + (102 * 64) 14530 mov r0, rPC @ arg0 14531 mov r1, rSELF @ arg1 14532 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14533 14534/* ------------------------------ */ 14535 .balign 64 14536.L_ALT_OP_SPUT: /* 0x67 */ 14537/* File: armv5te/alt_stub.S */ 14538/* 14539 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14540 * any interesting requests and then jump to the real instruction 14541 * handler. Note that the call to dvmCheckInst is done as a tail call. 14542 */ 14543 adrl lr, dvmAsmInstructionStart + (103 * 64) 14544 mov r0, rPC @ arg0 14545 mov r1, rSELF @ arg1 14546 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14547 14548/* ------------------------------ */ 14549 .balign 64 14550.L_ALT_OP_SPUT_WIDE: /* 0x68 */ 14551/* File: armv5te/alt_stub.S */ 14552/* 14553 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14554 * any interesting requests and then jump to the real instruction 14555 * handler. Note that the call to dvmCheckInst is done as a tail call. 14556 */ 14557 adrl lr, dvmAsmInstructionStart + (104 * 64) 14558 mov r0, rPC @ arg0 14559 mov r1, rSELF @ arg1 14560 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14561 14562/* ------------------------------ */ 14563 .balign 64 14564.L_ALT_OP_SPUT_OBJECT: /* 0x69 */ 14565/* File: armv5te/alt_stub.S */ 14566/* 14567 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14568 * any interesting requests and then jump to the real instruction 14569 * handler. Note that the call to dvmCheckInst is done as a tail call. 14570 */ 14571 adrl lr, dvmAsmInstructionStart + (105 * 64) 14572 mov r0, rPC @ arg0 14573 mov r1, rSELF @ arg1 14574 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14575 14576/* ------------------------------ */ 14577 .balign 64 14578.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */ 14579/* File: armv5te/alt_stub.S */ 14580/* 14581 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14582 * any interesting requests and then jump to the real instruction 14583 * handler. Note that the call to dvmCheckInst is done as a tail call. 14584 */ 14585 adrl lr, dvmAsmInstructionStart + (106 * 64) 14586 mov r0, rPC @ arg0 14587 mov r1, rSELF @ arg1 14588 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14589 14590/* ------------------------------ */ 14591 .balign 64 14592.L_ALT_OP_SPUT_BYTE: /* 0x6b */ 14593/* File: armv5te/alt_stub.S */ 14594/* 14595 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14596 * any interesting requests and then jump to the real instruction 14597 * handler. Note that the call to dvmCheckInst is done as a tail call. 14598 */ 14599 adrl lr, dvmAsmInstructionStart + (107 * 64) 14600 mov r0, rPC @ arg0 14601 mov r1, rSELF @ arg1 14602 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14603 14604/* ------------------------------ */ 14605 .balign 64 14606.L_ALT_OP_SPUT_CHAR: /* 0x6c */ 14607/* File: armv5te/alt_stub.S */ 14608/* 14609 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14610 * any interesting requests and then jump to the real instruction 14611 * handler. Note that the call to dvmCheckInst is done as a tail call. 14612 */ 14613 adrl lr, dvmAsmInstructionStart + (108 * 64) 14614 mov r0, rPC @ arg0 14615 mov r1, rSELF @ arg1 14616 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14617 14618/* ------------------------------ */ 14619 .balign 64 14620.L_ALT_OP_SPUT_SHORT: /* 0x6d */ 14621/* File: armv5te/alt_stub.S */ 14622/* 14623 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14624 * any interesting requests and then jump to the real instruction 14625 * handler. Note that the call to dvmCheckInst is done as a tail call. 14626 */ 14627 adrl lr, dvmAsmInstructionStart + (109 * 64) 14628 mov r0, rPC @ arg0 14629 mov r1, rSELF @ arg1 14630 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14631 14632/* ------------------------------ */ 14633 .balign 64 14634.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */ 14635/* File: armv5te/alt_stub.S */ 14636/* 14637 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14638 * any interesting requests and then jump to the real instruction 14639 * handler. Note that the call to dvmCheckInst is done as a tail call. 14640 */ 14641 adrl lr, dvmAsmInstructionStart + (110 * 64) 14642 mov r0, rPC @ arg0 14643 mov r1, rSELF @ arg1 14644 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14645 14646/* ------------------------------ */ 14647 .balign 64 14648.L_ALT_OP_INVOKE_SUPER: /* 0x6f */ 14649/* File: armv5te/alt_stub.S */ 14650/* 14651 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14652 * any interesting requests and then jump to the real instruction 14653 * handler. Note that the call to dvmCheckInst is done as a tail call. 14654 */ 14655 adrl lr, dvmAsmInstructionStart + (111 * 64) 14656 mov r0, rPC @ arg0 14657 mov r1, rSELF @ arg1 14658 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14659 14660/* ------------------------------ */ 14661 .balign 64 14662.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */ 14663/* File: armv5te/alt_stub.S */ 14664/* 14665 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14666 * any interesting requests and then jump to the real instruction 14667 * handler. Note that the call to dvmCheckInst is done as a tail call. 14668 */ 14669 adrl lr, dvmAsmInstructionStart + (112 * 64) 14670 mov r0, rPC @ arg0 14671 mov r1, rSELF @ arg1 14672 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14673 14674/* ------------------------------ */ 14675 .balign 64 14676.L_ALT_OP_INVOKE_STATIC: /* 0x71 */ 14677/* File: armv5te/alt_stub.S */ 14678/* 14679 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14680 * any interesting requests and then jump to the real instruction 14681 * handler. Note that the call to dvmCheckInst is done as a tail call. 14682 */ 14683 adrl lr, dvmAsmInstructionStart + (113 * 64) 14684 mov r0, rPC @ arg0 14685 mov r1, rSELF @ arg1 14686 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14687 14688/* ------------------------------ */ 14689 .balign 64 14690.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */ 14691/* File: armv5te/alt_stub.S */ 14692/* 14693 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14694 * any interesting requests and then jump to the real instruction 14695 * handler. Note that the call to dvmCheckInst is done as a tail call. 14696 */ 14697 adrl lr, dvmAsmInstructionStart + (114 * 64) 14698 mov r0, rPC @ arg0 14699 mov r1, rSELF @ arg1 14700 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14701 14702/* ------------------------------ */ 14703 .balign 64 14704.L_ALT_OP_UNUSED_73: /* 0x73 */ 14705/* File: armv5te/alt_stub.S */ 14706/* 14707 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14708 * any interesting requests and then jump to the real instruction 14709 * handler. Note that the call to dvmCheckInst is done as a tail call. 14710 */ 14711 adrl lr, dvmAsmInstructionStart + (115 * 64) 14712 mov r0, rPC @ arg0 14713 mov r1, rSELF @ arg1 14714 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14715 14716/* ------------------------------ */ 14717 .balign 64 14718.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 14719/* File: armv5te/alt_stub.S */ 14720/* 14721 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14722 * any interesting requests and then jump to the real instruction 14723 * handler. Note that the call to dvmCheckInst is done as a tail call. 14724 */ 14725 adrl lr, dvmAsmInstructionStart + (116 * 64) 14726 mov r0, rPC @ arg0 14727 mov r1, rSELF @ arg1 14728 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14729 14730/* ------------------------------ */ 14731 .balign 64 14732.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 14733/* File: armv5te/alt_stub.S */ 14734/* 14735 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14736 * any interesting requests and then jump to the real instruction 14737 * handler. Note that the call to dvmCheckInst is done as a tail call. 14738 */ 14739 adrl lr, dvmAsmInstructionStart + (117 * 64) 14740 mov r0, rPC @ arg0 14741 mov r1, rSELF @ arg1 14742 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14743 14744/* ------------------------------ */ 14745 .balign 64 14746.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 14747/* File: armv5te/alt_stub.S */ 14748/* 14749 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14750 * any interesting requests and then jump to the real instruction 14751 * handler. Note that the call to dvmCheckInst is done as a tail call. 14752 */ 14753 adrl lr, dvmAsmInstructionStart + (118 * 64) 14754 mov r0, rPC @ arg0 14755 mov r1, rSELF @ arg1 14756 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14757 14758/* ------------------------------ */ 14759 .balign 64 14760.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 14761/* File: armv5te/alt_stub.S */ 14762/* 14763 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14764 * any interesting requests and then jump to the real instruction 14765 * handler. Note that the call to dvmCheckInst is done as a tail call. 14766 */ 14767 adrl lr, dvmAsmInstructionStart + (119 * 64) 14768 mov r0, rPC @ arg0 14769 mov r1, rSELF @ arg1 14770 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14771 14772/* ------------------------------ */ 14773 .balign 64 14774.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 14775/* File: armv5te/alt_stub.S */ 14776/* 14777 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14778 * any interesting requests and then jump to the real instruction 14779 * handler. Note that the call to dvmCheckInst is done as a tail call. 14780 */ 14781 adrl lr, dvmAsmInstructionStart + (120 * 64) 14782 mov r0, rPC @ arg0 14783 mov r1, rSELF @ arg1 14784 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14785 14786/* ------------------------------ */ 14787 .balign 64 14788.L_ALT_OP_UNUSED_79: /* 0x79 */ 14789/* File: armv5te/alt_stub.S */ 14790/* 14791 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14792 * any interesting requests and then jump to the real instruction 14793 * handler. Note that the call to dvmCheckInst is done as a tail call. 14794 */ 14795 adrl lr, dvmAsmInstructionStart + (121 * 64) 14796 mov r0, rPC @ arg0 14797 mov r1, rSELF @ arg1 14798 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14799 14800/* ------------------------------ */ 14801 .balign 64 14802.L_ALT_OP_UNUSED_7A: /* 0x7a */ 14803/* File: armv5te/alt_stub.S */ 14804/* 14805 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14806 * any interesting requests and then jump to the real instruction 14807 * handler. Note that the call to dvmCheckInst is done as a tail call. 14808 */ 14809 adrl lr, dvmAsmInstructionStart + (122 * 64) 14810 mov r0, rPC @ arg0 14811 mov r1, rSELF @ arg1 14812 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14813 14814/* ------------------------------ */ 14815 .balign 64 14816.L_ALT_OP_NEG_INT: /* 0x7b */ 14817/* File: armv5te/alt_stub.S */ 14818/* 14819 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14820 * any interesting requests and then jump to the real instruction 14821 * handler. Note that the call to dvmCheckInst is done as a tail call. 14822 */ 14823 adrl lr, dvmAsmInstructionStart + (123 * 64) 14824 mov r0, rPC @ arg0 14825 mov r1, rSELF @ arg1 14826 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14827 14828/* ------------------------------ */ 14829 .balign 64 14830.L_ALT_OP_NOT_INT: /* 0x7c */ 14831/* File: armv5te/alt_stub.S */ 14832/* 14833 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14834 * any interesting requests and then jump to the real instruction 14835 * handler. Note that the call to dvmCheckInst is done as a tail call. 14836 */ 14837 adrl lr, dvmAsmInstructionStart + (124 * 64) 14838 mov r0, rPC @ arg0 14839 mov r1, rSELF @ arg1 14840 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14841 14842/* ------------------------------ */ 14843 .balign 64 14844.L_ALT_OP_NEG_LONG: /* 0x7d */ 14845/* File: armv5te/alt_stub.S */ 14846/* 14847 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14848 * any interesting requests and then jump to the real instruction 14849 * handler. Note that the call to dvmCheckInst is done as a tail call. 14850 */ 14851 adrl lr, dvmAsmInstructionStart + (125 * 64) 14852 mov r0, rPC @ arg0 14853 mov r1, rSELF @ arg1 14854 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14855 14856/* ------------------------------ */ 14857 .balign 64 14858.L_ALT_OP_NOT_LONG: /* 0x7e */ 14859/* File: armv5te/alt_stub.S */ 14860/* 14861 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14862 * any interesting requests and then jump to the real instruction 14863 * handler. Note that the call to dvmCheckInst is done as a tail call. 14864 */ 14865 adrl lr, dvmAsmInstructionStart + (126 * 64) 14866 mov r0, rPC @ arg0 14867 mov r1, rSELF @ arg1 14868 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14869 14870/* ------------------------------ */ 14871 .balign 64 14872.L_ALT_OP_NEG_FLOAT: /* 0x7f */ 14873/* File: armv5te/alt_stub.S */ 14874/* 14875 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14876 * any interesting requests and then jump to the real instruction 14877 * handler. Note that the call to dvmCheckInst is done as a tail call. 14878 */ 14879 adrl lr, dvmAsmInstructionStart + (127 * 64) 14880 mov r0, rPC @ arg0 14881 mov r1, rSELF @ arg1 14882 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14883 14884/* ------------------------------ */ 14885 .balign 64 14886.L_ALT_OP_NEG_DOUBLE: /* 0x80 */ 14887/* File: armv5te/alt_stub.S */ 14888/* 14889 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14890 * any interesting requests and then jump to the real instruction 14891 * handler. Note that the call to dvmCheckInst is done as a tail call. 14892 */ 14893 adrl lr, dvmAsmInstructionStart + (128 * 64) 14894 mov r0, rPC @ arg0 14895 mov r1, rSELF @ arg1 14896 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14897 14898/* ------------------------------ */ 14899 .balign 64 14900.L_ALT_OP_INT_TO_LONG: /* 0x81 */ 14901/* File: armv5te/alt_stub.S */ 14902/* 14903 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14904 * any interesting requests and then jump to the real instruction 14905 * handler. Note that the call to dvmCheckInst is done as a tail call. 14906 */ 14907 adrl lr, dvmAsmInstructionStart + (129 * 64) 14908 mov r0, rPC @ arg0 14909 mov r1, rSELF @ arg1 14910 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14911 14912/* ------------------------------ */ 14913 .balign 64 14914.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */ 14915/* File: armv5te/alt_stub.S */ 14916/* 14917 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14918 * any interesting requests and then jump to the real instruction 14919 * handler. Note that the call to dvmCheckInst is done as a tail call. 14920 */ 14921 adrl lr, dvmAsmInstructionStart + (130 * 64) 14922 mov r0, rPC @ arg0 14923 mov r1, rSELF @ arg1 14924 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14925 14926/* ------------------------------ */ 14927 .balign 64 14928.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */ 14929/* File: armv5te/alt_stub.S */ 14930/* 14931 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14932 * any interesting requests and then jump to the real instruction 14933 * handler. Note that the call to dvmCheckInst is done as a tail call. 14934 */ 14935 adrl lr, dvmAsmInstructionStart + (131 * 64) 14936 mov r0, rPC @ arg0 14937 mov r1, rSELF @ arg1 14938 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14939 14940/* ------------------------------ */ 14941 .balign 64 14942.L_ALT_OP_LONG_TO_INT: /* 0x84 */ 14943/* File: armv5te/alt_stub.S */ 14944/* 14945 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14946 * any interesting requests and then jump to the real instruction 14947 * handler. Note that the call to dvmCheckInst is done as a tail call. 14948 */ 14949 adrl lr, dvmAsmInstructionStart + (132 * 64) 14950 mov r0, rPC @ arg0 14951 mov r1, rSELF @ arg1 14952 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14953 14954/* ------------------------------ */ 14955 .balign 64 14956.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */ 14957/* File: armv5te/alt_stub.S */ 14958/* 14959 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14960 * any interesting requests and then jump to the real instruction 14961 * handler. Note that the call to dvmCheckInst is done as a tail call. 14962 */ 14963 adrl lr, dvmAsmInstructionStart + (133 * 64) 14964 mov r0, rPC @ arg0 14965 mov r1, rSELF @ arg1 14966 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14967 14968/* ------------------------------ */ 14969 .balign 64 14970.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */ 14971/* File: armv5te/alt_stub.S */ 14972/* 14973 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14974 * any interesting requests and then jump to the real instruction 14975 * handler. Note that the call to dvmCheckInst is done as a tail call. 14976 */ 14977 adrl lr, dvmAsmInstructionStart + (134 * 64) 14978 mov r0, rPC @ arg0 14979 mov r1, rSELF @ arg1 14980 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14981 14982/* ------------------------------ */ 14983 .balign 64 14984.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */ 14985/* File: armv5te/alt_stub.S */ 14986/* 14987 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14988 * any interesting requests and then jump to the real instruction 14989 * handler. Note that the call to dvmCheckInst is done as a tail call. 14990 */ 14991 adrl lr, dvmAsmInstructionStart + (135 * 64) 14992 mov r0, rPC @ arg0 14993 mov r1, rSELF @ arg1 14994 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14995 14996/* ------------------------------ */ 14997 .balign 64 14998.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */ 14999/* File: armv5te/alt_stub.S */ 15000/* 15001 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15002 * any interesting requests and then jump to the real instruction 15003 * handler. Note that the call to dvmCheckInst is done as a tail call. 15004 */ 15005 adrl lr, dvmAsmInstructionStart + (136 * 64) 15006 mov r0, rPC @ arg0 15007 mov r1, rSELF @ arg1 15008 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15009 15010/* ------------------------------ */ 15011 .balign 64 15012.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 15013/* File: armv5te/alt_stub.S */ 15014/* 15015 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15016 * any interesting requests and then jump to the real instruction 15017 * handler. Note that the call to dvmCheckInst is done as a tail call. 15018 */ 15019 adrl lr, dvmAsmInstructionStart + (137 * 64) 15020 mov r0, rPC @ arg0 15021 mov r1, rSELF @ arg1 15022 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15023 15024/* ------------------------------ */ 15025 .balign 64 15026.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */ 15027/* File: armv5te/alt_stub.S */ 15028/* 15029 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15030 * any interesting requests and then jump to the real instruction 15031 * handler. Note that the call to dvmCheckInst is done as a tail call. 15032 */ 15033 adrl lr, dvmAsmInstructionStart + (138 * 64) 15034 mov r0, rPC @ arg0 15035 mov r1, rSELF @ arg1 15036 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15037 15038/* ------------------------------ */ 15039 .balign 64 15040.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */ 15041/* File: armv5te/alt_stub.S */ 15042/* 15043 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15044 * any interesting requests and then jump to the real instruction 15045 * handler. Note that the call to dvmCheckInst is done as a tail call. 15046 */ 15047 adrl lr, dvmAsmInstructionStart + (139 * 64) 15048 mov r0, rPC @ arg0 15049 mov r1, rSELF @ arg1 15050 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15051 15052/* ------------------------------ */ 15053 .balign 64 15054.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 15055/* File: armv5te/alt_stub.S */ 15056/* 15057 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15058 * any interesting requests and then jump to the real instruction 15059 * handler. Note that the call to dvmCheckInst is done as a tail call. 15060 */ 15061 adrl lr, dvmAsmInstructionStart + (140 * 64) 15062 mov r0, rPC @ arg0 15063 mov r1, rSELF @ arg1 15064 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15065 15066/* ------------------------------ */ 15067 .balign 64 15068.L_ALT_OP_INT_TO_BYTE: /* 0x8d */ 15069/* File: armv5te/alt_stub.S */ 15070/* 15071 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15072 * any interesting requests and then jump to the real instruction 15073 * handler. Note that the call to dvmCheckInst is done as a tail call. 15074 */ 15075 adrl lr, dvmAsmInstructionStart + (141 * 64) 15076 mov r0, rPC @ arg0 15077 mov r1, rSELF @ arg1 15078 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15079 15080/* ------------------------------ */ 15081 .balign 64 15082.L_ALT_OP_INT_TO_CHAR: /* 0x8e */ 15083/* File: armv5te/alt_stub.S */ 15084/* 15085 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15086 * any interesting requests and then jump to the real instruction 15087 * handler. Note that the call to dvmCheckInst is done as a tail call. 15088 */ 15089 adrl lr, dvmAsmInstructionStart + (142 * 64) 15090 mov r0, rPC @ arg0 15091 mov r1, rSELF @ arg1 15092 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15093 15094/* ------------------------------ */ 15095 .balign 64 15096.L_ALT_OP_INT_TO_SHORT: /* 0x8f */ 15097/* File: armv5te/alt_stub.S */ 15098/* 15099 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15100 * any interesting requests and then jump to the real instruction 15101 * handler. Note that the call to dvmCheckInst is done as a tail call. 15102 */ 15103 adrl lr, dvmAsmInstructionStart + (143 * 64) 15104 mov r0, rPC @ arg0 15105 mov r1, rSELF @ arg1 15106 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15107 15108/* ------------------------------ */ 15109 .balign 64 15110.L_ALT_OP_ADD_INT: /* 0x90 */ 15111/* File: armv5te/alt_stub.S */ 15112/* 15113 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15114 * any interesting requests and then jump to the real instruction 15115 * handler. Note that the call to dvmCheckInst is done as a tail call. 15116 */ 15117 adrl lr, dvmAsmInstructionStart + (144 * 64) 15118 mov r0, rPC @ arg0 15119 mov r1, rSELF @ arg1 15120 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15121 15122/* ------------------------------ */ 15123 .balign 64 15124.L_ALT_OP_SUB_INT: /* 0x91 */ 15125/* File: armv5te/alt_stub.S */ 15126/* 15127 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15128 * any interesting requests and then jump to the real instruction 15129 * handler. Note that the call to dvmCheckInst is done as a tail call. 15130 */ 15131 adrl lr, dvmAsmInstructionStart + (145 * 64) 15132 mov r0, rPC @ arg0 15133 mov r1, rSELF @ arg1 15134 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15135 15136/* ------------------------------ */ 15137 .balign 64 15138.L_ALT_OP_MUL_INT: /* 0x92 */ 15139/* File: armv5te/alt_stub.S */ 15140/* 15141 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15142 * any interesting requests and then jump to the real instruction 15143 * handler. Note that the call to dvmCheckInst is done as a tail call. 15144 */ 15145 adrl lr, dvmAsmInstructionStart + (146 * 64) 15146 mov r0, rPC @ arg0 15147 mov r1, rSELF @ arg1 15148 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15149 15150/* ------------------------------ */ 15151 .balign 64 15152.L_ALT_OP_DIV_INT: /* 0x93 */ 15153/* File: armv5te/alt_stub.S */ 15154/* 15155 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15156 * any interesting requests and then jump to the real instruction 15157 * handler. Note that the call to dvmCheckInst is done as a tail call. 15158 */ 15159 adrl lr, dvmAsmInstructionStart + (147 * 64) 15160 mov r0, rPC @ arg0 15161 mov r1, rSELF @ arg1 15162 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15163 15164/* ------------------------------ */ 15165 .balign 64 15166.L_ALT_OP_REM_INT: /* 0x94 */ 15167/* File: armv5te/alt_stub.S */ 15168/* 15169 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15170 * any interesting requests and then jump to the real instruction 15171 * handler. Note that the call to dvmCheckInst is done as a tail call. 15172 */ 15173 adrl lr, dvmAsmInstructionStart + (148 * 64) 15174 mov r0, rPC @ arg0 15175 mov r1, rSELF @ arg1 15176 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15177 15178/* ------------------------------ */ 15179 .balign 64 15180.L_ALT_OP_AND_INT: /* 0x95 */ 15181/* File: armv5te/alt_stub.S */ 15182/* 15183 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15184 * any interesting requests and then jump to the real instruction 15185 * handler. Note that the call to dvmCheckInst is done as a tail call. 15186 */ 15187 adrl lr, dvmAsmInstructionStart + (149 * 64) 15188 mov r0, rPC @ arg0 15189 mov r1, rSELF @ arg1 15190 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15191 15192/* ------------------------------ */ 15193 .balign 64 15194.L_ALT_OP_OR_INT: /* 0x96 */ 15195/* File: armv5te/alt_stub.S */ 15196/* 15197 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15198 * any interesting requests and then jump to the real instruction 15199 * handler. Note that the call to dvmCheckInst is done as a tail call. 15200 */ 15201 adrl lr, dvmAsmInstructionStart + (150 * 64) 15202 mov r0, rPC @ arg0 15203 mov r1, rSELF @ arg1 15204 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15205 15206/* ------------------------------ */ 15207 .balign 64 15208.L_ALT_OP_XOR_INT: /* 0x97 */ 15209/* File: armv5te/alt_stub.S */ 15210/* 15211 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15212 * any interesting requests and then jump to the real instruction 15213 * handler. Note that the call to dvmCheckInst is done as a tail call. 15214 */ 15215 adrl lr, dvmAsmInstructionStart + (151 * 64) 15216 mov r0, rPC @ arg0 15217 mov r1, rSELF @ arg1 15218 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15219 15220/* ------------------------------ */ 15221 .balign 64 15222.L_ALT_OP_SHL_INT: /* 0x98 */ 15223/* File: armv5te/alt_stub.S */ 15224/* 15225 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15226 * any interesting requests and then jump to the real instruction 15227 * handler. Note that the call to dvmCheckInst is done as a tail call. 15228 */ 15229 adrl lr, dvmAsmInstructionStart + (152 * 64) 15230 mov r0, rPC @ arg0 15231 mov r1, rSELF @ arg1 15232 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15233 15234/* ------------------------------ */ 15235 .balign 64 15236.L_ALT_OP_SHR_INT: /* 0x99 */ 15237/* File: armv5te/alt_stub.S */ 15238/* 15239 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15240 * any interesting requests and then jump to the real instruction 15241 * handler. Note that the call to dvmCheckInst is done as a tail call. 15242 */ 15243 adrl lr, dvmAsmInstructionStart + (153 * 64) 15244 mov r0, rPC @ arg0 15245 mov r1, rSELF @ arg1 15246 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15247 15248/* ------------------------------ */ 15249 .balign 64 15250.L_ALT_OP_USHR_INT: /* 0x9a */ 15251/* File: armv5te/alt_stub.S */ 15252/* 15253 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15254 * any interesting requests and then jump to the real instruction 15255 * handler. Note that the call to dvmCheckInst is done as a tail call. 15256 */ 15257 adrl lr, dvmAsmInstructionStart + (154 * 64) 15258 mov r0, rPC @ arg0 15259 mov r1, rSELF @ arg1 15260 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15261 15262/* ------------------------------ */ 15263 .balign 64 15264.L_ALT_OP_ADD_LONG: /* 0x9b */ 15265/* File: armv5te/alt_stub.S */ 15266/* 15267 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15268 * any interesting requests and then jump to the real instruction 15269 * handler. Note that the call to dvmCheckInst is done as a tail call. 15270 */ 15271 adrl lr, dvmAsmInstructionStart + (155 * 64) 15272 mov r0, rPC @ arg0 15273 mov r1, rSELF @ arg1 15274 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15275 15276/* ------------------------------ */ 15277 .balign 64 15278.L_ALT_OP_SUB_LONG: /* 0x9c */ 15279/* File: armv5te/alt_stub.S */ 15280/* 15281 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15282 * any interesting requests and then jump to the real instruction 15283 * handler. Note that the call to dvmCheckInst is done as a tail call. 15284 */ 15285 adrl lr, dvmAsmInstructionStart + (156 * 64) 15286 mov r0, rPC @ arg0 15287 mov r1, rSELF @ arg1 15288 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15289 15290/* ------------------------------ */ 15291 .balign 64 15292.L_ALT_OP_MUL_LONG: /* 0x9d */ 15293/* File: armv5te/alt_stub.S */ 15294/* 15295 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15296 * any interesting requests and then jump to the real instruction 15297 * handler. Note that the call to dvmCheckInst is done as a tail call. 15298 */ 15299 adrl lr, dvmAsmInstructionStart + (157 * 64) 15300 mov r0, rPC @ arg0 15301 mov r1, rSELF @ arg1 15302 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15303 15304/* ------------------------------ */ 15305 .balign 64 15306.L_ALT_OP_DIV_LONG: /* 0x9e */ 15307/* File: armv5te/alt_stub.S */ 15308/* 15309 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15310 * any interesting requests and then jump to the real instruction 15311 * handler. Note that the call to dvmCheckInst is done as a tail call. 15312 */ 15313 adrl lr, dvmAsmInstructionStart + (158 * 64) 15314 mov r0, rPC @ arg0 15315 mov r1, rSELF @ arg1 15316 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15317 15318/* ------------------------------ */ 15319 .balign 64 15320.L_ALT_OP_REM_LONG: /* 0x9f */ 15321/* File: armv5te/alt_stub.S */ 15322/* 15323 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15324 * any interesting requests and then jump to the real instruction 15325 * handler. Note that the call to dvmCheckInst is done as a tail call. 15326 */ 15327 adrl lr, dvmAsmInstructionStart + (159 * 64) 15328 mov r0, rPC @ arg0 15329 mov r1, rSELF @ arg1 15330 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15331 15332/* ------------------------------ */ 15333 .balign 64 15334.L_ALT_OP_AND_LONG: /* 0xa0 */ 15335/* File: armv5te/alt_stub.S */ 15336/* 15337 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15338 * any interesting requests and then jump to the real instruction 15339 * handler. Note that the call to dvmCheckInst is done as a tail call. 15340 */ 15341 adrl lr, dvmAsmInstructionStart + (160 * 64) 15342 mov r0, rPC @ arg0 15343 mov r1, rSELF @ arg1 15344 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15345 15346/* ------------------------------ */ 15347 .balign 64 15348.L_ALT_OP_OR_LONG: /* 0xa1 */ 15349/* File: armv5te/alt_stub.S */ 15350/* 15351 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15352 * any interesting requests and then jump to the real instruction 15353 * handler. Note that the call to dvmCheckInst is done as a tail call. 15354 */ 15355 adrl lr, dvmAsmInstructionStart + (161 * 64) 15356 mov r0, rPC @ arg0 15357 mov r1, rSELF @ arg1 15358 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15359 15360/* ------------------------------ */ 15361 .balign 64 15362.L_ALT_OP_XOR_LONG: /* 0xa2 */ 15363/* File: armv5te/alt_stub.S */ 15364/* 15365 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15366 * any interesting requests and then jump to the real instruction 15367 * handler. Note that the call to dvmCheckInst is done as a tail call. 15368 */ 15369 adrl lr, dvmAsmInstructionStart + (162 * 64) 15370 mov r0, rPC @ arg0 15371 mov r1, rSELF @ arg1 15372 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15373 15374/* ------------------------------ */ 15375 .balign 64 15376.L_ALT_OP_SHL_LONG: /* 0xa3 */ 15377/* File: armv5te/alt_stub.S */ 15378/* 15379 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15380 * any interesting requests and then jump to the real instruction 15381 * handler. Note that the call to dvmCheckInst is done as a tail call. 15382 */ 15383 adrl lr, dvmAsmInstructionStart + (163 * 64) 15384 mov r0, rPC @ arg0 15385 mov r1, rSELF @ arg1 15386 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15387 15388/* ------------------------------ */ 15389 .balign 64 15390.L_ALT_OP_SHR_LONG: /* 0xa4 */ 15391/* File: armv5te/alt_stub.S */ 15392/* 15393 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15394 * any interesting requests and then jump to the real instruction 15395 * handler. Note that the call to dvmCheckInst is done as a tail call. 15396 */ 15397 adrl lr, dvmAsmInstructionStart + (164 * 64) 15398 mov r0, rPC @ arg0 15399 mov r1, rSELF @ arg1 15400 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15401 15402/* ------------------------------ */ 15403 .balign 64 15404.L_ALT_OP_USHR_LONG: /* 0xa5 */ 15405/* File: armv5te/alt_stub.S */ 15406/* 15407 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15408 * any interesting requests and then jump to the real instruction 15409 * handler. Note that the call to dvmCheckInst is done as a tail call. 15410 */ 15411 adrl lr, dvmAsmInstructionStart + (165 * 64) 15412 mov r0, rPC @ arg0 15413 mov r1, rSELF @ arg1 15414 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15415 15416/* ------------------------------ */ 15417 .balign 64 15418.L_ALT_OP_ADD_FLOAT: /* 0xa6 */ 15419/* File: armv5te/alt_stub.S */ 15420/* 15421 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15422 * any interesting requests and then jump to the real instruction 15423 * handler. Note that the call to dvmCheckInst is done as a tail call. 15424 */ 15425 adrl lr, dvmAsmInstructionStart + (166 * 64) 15426 mov r0, rPC @ arg0 15427 mov r1, rSELF @ arg1 15428 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15429 15430/* ------------------------------ */ 15431 .balign 64 15432.L_ALT_OP_SUB_FLOAT: /* 0xa7 */ 15433/* File: armv5te/alt_stub.S */ 15434/* 15435 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15436 * any interesting requests and then jump to the real instruction 15437 * handler. Note that the call to dvmCheckInst is done as a tail call. 15438 */ 15439 adrl lr, dvmAsmInstructionStart + (167 * 64) 15440 mov r0, rPC @ arg0 15441 mov r1, rSELF @ arg1 15442 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15443 15444/* ------------------------------ */ 15445 .balign 64 15446.L_ALT_OP_MUL_FLOAT: /* 0xa8 */ 15447/* File: armv5te/alt_stub.S */ 15448/* 15449 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15450 * any interesting requests and then jump to the real instruction 15451 * handler. Note that the call to dvmCheckInst is done as a tail call. 15452 */ 15453 adrl lr, dvmAsmInstructionStart + (168 * 64) 15454 mov r0, rPC @ arg0 15455 mov r1, rSELF @ arg1 15456 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15457 15458/* ------------------------------ */ 15459 .balign 64 15460.L_ALT_OP_DIV_FLOAT: /* 0xa9 */ 15461/* File: armv5te/alt_stub.S */ 15462/* 15463 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15464 * any interesting requests and then jump to the real instruction 15465 * handler. Note that the call to dvmCheckInst is done as a tail call. 15466 */ 15467 adrl lr, dvmAsmInstructionStart + (169 * 64) 15468 mov r0, rPC @ arg0 15469 mov r1, rSELF @ arg1 15470 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15471 15472/* ------------------------------ */ 15473 .balign 64 15474.L_ALT_OP_REM_FLOAT: /* 0xaa */ 15475/* File: armv5te/alt_stub.S */ 15476/* 15477 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15478 * any interesting requests and then jump to the real instruction 15479 * handler. Note that the call to dvmCheckInst is done as a tail call. 15480 */ 15481 adrl lr, dvmAsmInstructionStart + (170 * 64) 15482 mov r0, rPC @ arg0 15483 mov r1, rSELF @ arg1 15484 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15485 15486/* ------------------------------ */ 15487 .balign 64 15488.L_ALT_OP_ADD_DOUBLE: /* 0xab */ 15489/* File: armv5te/alt_stub.S */ 15490/* 15491 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15492 * any interesting requests and then jump to the real instruction 15493 * handler. Note that the call to dvmCheckInst is done as a tail call. 15494 */ 15495 adrl lr, dvmAsmInstructionStart + (171 * 64) 15496 mov r0, rPC @ arg0 15497 mov r1, rSELF @ arg1 15498 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15499 15500/* ------------------------------ */ 15501 .balign 64 15502.L_ALT_OP_SUB_DOUBLE: /* 0xac */ 15503/* File: armv5te/alt_stub.S */ 15504/* 15505 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15506 * any interesting requests and then jump to the real instruction 15507 * handler. Note that the call to dvmCheckInst is done as a tail call. 15508 */ 15509 adrl lr, dvmAsmInstructionStart + (172 * 64) 15510 mov r0, rPC @ arg0 15511 mov r1, rSELF @ arg1 15512 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15513 15514/* ------------------------------ */ 15515 .balign 64 15516.L_ALT_OP_MUL_DOUBLE: /* 0xad */ 15517/* File: armv5te/alt_stub.S */ 15518/* 15519 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15520 * any interesting requests and then jump to the real instruction 15521 * handler. Note that the call to dvmCheckInst is done as a tail call. 15522 */ 15523 adrl lr, dvmAsmInstructionStart + (173 * 64) 15524 mov r0, rPC @ arg0 15525 mov r1, rSELF @ arg1 15526 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15527 15528/* ------------------------------ */ 15529 .balign 64 15530.L_ALT_OP_DIV_DOUBLE: /* 0xae */ 15531/* File: armv5te/alt_stub.S */ 15532/* 15533 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15534 * any interesting requests and then jump to the real instruction 15535 * handler. Note that the call to dvmCheckInst is done as a tail call. 15536 */ 15537 adrl lr, dvmAsmInstructionStart + (174 * 64) 15538 mov r0, rPC @ arg0 15539 mov r1, rSELF @ arg1 15540 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15541 15542/* ------------------------------ */ 15543 .balign 64 15544.L_ALT_OP_REM_DOUBLE: /* 0xaf */ 15545/* File: armv5te/alt_stub.S */ 15546/* 15547 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15548 * any interesting requests and then jump to the real instruction 15549 * handler. Note that the call to dvmCheckInst is done as a tail call. 15550 */ 15551 adrl lr, dvmAsmInstructionStart + (175 * 64) 15552 mov r0, rPC @ arg0 15553 mov r1, rSELF @ arg1 15554 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15555 15556/* ------------------------------ */ 15557 .balign 64 15558.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */ 15559/* File: armv5te/alt_stub.S */ 15560/* 15561 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15562 * any interesting requests and then jump to the real instruction 15563 * handler. Note that the call to dvmCheckInst is done as a tail call. 15564 */ 15565 adrl lr, dvmAsmInstructionStart + (176 * 64) 15566 mov r0, rPC @ arg0 15567 mov r1, rSELF @ arg1 15568 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15569 15570/* ------------------------------ */ 15571 .balign 64 15572.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */ 15573/* File: armv5te/alt_stub.S */ 15574/* 15575 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15576 * any interesting requests and then jump to the real instruction 15577 * handler. Note that the call to dvmCheckInst is done as a tail call. 15578 */ 15579 adrl lr, dvmAsmInstructionStart + (177 * 64) 15580 mov r0, rPC @ arg0 15581 mov r1, rSELF @ arg1 15582 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15583 15584/* ------------------------------ */ 15585 .balign 64 15586.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */ 15587/* File: armv5te/alt_stub.S */ 15588/* 15589 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15590 * any interesting requests and then jump to the real instruction 15591 * handler. Note that the call to dvmCheckInst is done as a tail call. 15592 */ 15593 adrl lr, dvmAsmInstructionStart + (178 * 64) 15594 mov r0, rPC @ arg0 15595 mov r1, rSELF @ arg1 15596 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15597 15598/* ------------------------------ */ 15599 .balign 64 15600.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */ 15601/* File: armv5te/alt_stub.S */ 15602/* 15603 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15604 * any interesting requests and then jump to the real instruction 15605 * handler. Note that the call to dvmCheckInst is done as a tail call. 15606 */ 15607 adrl lr, dvmAsmInstructionStart + (179 * 64) 15608 mov r0, rPC @ arg0 15609 mov r1, rSELF @ arg1 15610 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15611 15612/* ------------------------------ */ 15613 .balign 64 15614.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */ 15615/* File: armv5te/alt_stub.S */ 15616/* 15617 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15618 * any interesting requests and then jump to the real instruction 15619 * handler. Note that the call to dvmCheckInst is done as a tail call. 15620 */ 15621 adrl lr, dvmAsmInstructionStart + (180 * 64) 15622 mov r0, rPC @ arg0 15623 mov r1, rSELF @ arg1 15624 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15625 15626/* ------------------------------ */ 15627 .balign 64 15628.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */ 15629/* File: armv5te/alt_stub.S */ 15630/* 15631 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15632 * any interesting requests and then jump to the real instruction 15633 * handler. Note that the call to dvmCheckInst is done as a tail call. 15634 */ 15635 adrl lr, dvmAsmInstructionStart + (181 * 64) 15636 mov r0, rPC @ arg0 15637 mov r1, rSELF @ arg1 15638 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15639 15640/* ------------------------------ */ 15641 .balign 64 15642.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */ 15643/* File: armv5te/alt_stub.S */ 15644/* 15645 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15646 * any interesting requests and then jump to the real instruction 15647 * handler. Note that the call to dvmCheckInst is done as a tail call. 15648 */ 15649 adrl lr, dvmAsmInstructionStart + (182 * 64) 15650 mov r0, rPC @ arg0 15651 mov r1, rSELF @ arg1 15652 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15653 15654/* ------------------------------ */ 15655 .balign 64 15656.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */ 15657/* File: armv5te/alt_stub.S */ 15658/* 15659 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15660 * any interesting requests and then jump to the real instruction 15661 * handler. Note that the call to dvmCheckInst is done as a tail call. 15662 */ 15663 adrl lr, dvmAsmInstructionStart + (183 * 64) 15664 mov r0, rPC @ arg0 15665 mov r1, rSELF @ arg1 15666 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15667 15668/* ------------------------------ */ 15669 .balign 64 15670.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */ 15671/* File: armv5te/alt_stub.S */ 15672/* 15673 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15674 * any interesting requests and then jump to the real instruction 15675 * handler. Note that the call to dvmCheckInst is done as a tail call. 15676 */ 15677 adrl lr, dvmAsmInstructionStart + (184 * 64) 15678 mov r0, rPC @ arg0 15679 mov r1, rSELF @ arg1 15680 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15681 15682/* ------------------------------ */ 15683 .balign 64 15684.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */ 15685/* File: armv5te/alt_stub.S */ 15686/* 15687 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15688 * any interesting requests and then jump to the real instruction 15689 * handler. Note that the call to dvmCheckInst is done as a tail call. 15690 */ 15691 adrl lr, dvmAsmInstructionStart + (185 * 64) 15692 mov r0, rPC @ arg0 15693 mov r1, rSELF @ arg1 15694 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15695 15696/* ------------------------------ */ 15697 .balign 64 15698.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */ 15699/* File: armv5te/alt_stub.S */ 15700/* 15701 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15702 * any interesting requests and then jump to the real instruction 15703 * handler. Note that the call to dvmCheckInst is done as a tail call. 15704 */ 15705 adrl lr, dvmAsmInstructionStart + (186 * 64) 15706 mov r0, rPC @ arg0 15707 mov r1, rSELF @ arg1 15708 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15709 15710/* ------------------------------ */ 15711 .balign 64 15712.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */ 15713/* File: armv5te/alt_stub.S */ 15714/* 15715 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15716 * any interesting requests and then jump to the real instruction 15717 * handler. Note that the call to dvmCheckInst is done as a tail call. 15718 */ 15719 adrl lr, dvmAsmInstructionStart + (187 * 64) 15720 mov r0, rPC @ arg0 15721 mov r1, rSELF @ arg1 15722 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15723 15724/* ------------------------------ */ 15725 .balign 64 15726.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */ 15727/* File: armv5te/alt_stub.S */ 15728/* 15729 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15730 * any interesting requests and then jump to the real instruction 15731 * handler. Note that the call to dvmCheckInst is done as a tail call. 15732 */ 15733 adrl lr, dvmAsmInstructionStart + (188 * 64) 15734 mov r0, rPC @ arg0 15735 mov r1, rSELF @ arg1 15736 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15737 15738/* ------------------------------ */ 15739 .balign 64 15740.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */ 15741/* File: armv5te/alt_stub.S */ 15742/* 15743 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15744 * any interesting requests and then jump to the real instruction 15745 * handler. Note that the call to dvmCheckInst is done as a tail call. 15746 */ 15747 adrl lr, dvmAsmInstructionStart + (189 * 64) 15748 mov r0, rPC @ arg0 15749 mov r1, rSELF @ arg1 15750 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15751 15752/* ------------------------------ */ 15753 .balign 64 15754.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */ 15755/* File: armv5te/alt_stub.S */ 15756/* 15757 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15758 * any interesting requests and then jump to the real instruction 15759 * handler. Note that the call to dvmCheckInst is done as a tail call. 15760 */ 15761 adrl lr, dvmAsmInstructionStart + (190 * 64) 15762 mov r0, rPC @ arg0 15763 mov r1, rSELF @ arg1 15764 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15765 15766/* ------------------------------ */ 15767 .balign 64 15768.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */ 15769/* File: armv5te/alt_stub.S */ 15770/* 15771 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15772 * any interesting requests and then jump to the real instruction 15773 * handler. Note that the call to dvmCheckInst is done as a tail call. 15774 */ 15775 adrl lr, dvmAsmInstructionStart + (191 * 64) 15776 mov r0, rPC @ arg0 15777 mov r1, rSELF @ arg1 15778 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15779 15780/* ------------------------------ */ 15781 .balign 64 15782.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */ 15783/* File: armv5te/alt_stub.S */ 15784/* 15785 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15786 * any interesting requests and then jump to the real instruction 15787 * handler. Note that the call to dvmCheckInst is done as a tail call. 15788 */ 15789 adrl lr, dvmAsmInstructionStart + (192 * 64) 15790 mov r0, rPC @ arg0 15791 mov r1, rSELF @ arg1 15792 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15793 15794/* ------------------------------ */ 15795 .balign 64 15796.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */ 15797/* File: armv5te/alt_stub.S */ 15798/* 15799 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15800 * any interesting requests and then jump to the real instruction 15801 * handler. Note that the call to dvmCheckInst is done as a tail call. 15802 */ 15803 adrl lr, dvmAsmInstructionStart + (193 * 64) 15804 mov r0, rPC @ arg0 15805 mov r1, rSELF @ arg1 15806 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15807 15808/* ------------------------------ */ 15809 .balign 64 15810.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */ 15811/* File: armv5te/alt_stub.S */ 15812/* 15813 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15814 * any interesting requests and then jump to the real instruction 15815 * handler. Note that the call to dvmCheckInst is done as a tail call. 15816 */ 15817 adrl lr, dvmAsmInstructionStart + (194 * 64) 15818 mov r0, rPC @ arg0 15819 mov r1, rSELF @ arg1 15820 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15821 15822/* ------------------------------ */ 15823 .balign 64 15824.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */ 15825/* File: armv5te/alt_stub.S */ 15826/* 15827 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15828 * any interesting requests and then jump to the real instruction 15829 * handler. Note that the call to dvmCheckInst is done as a tail call. 15830 */ 15831 adrl lr, dvmAsmInstructionStart + (195 * 64) 15832 mov r0, rPC @ arg0 15833 mov r1, rSELF @ arg1 15834 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15835 15836/* ------------------------------ */ 15837 .balign 64 15838.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */ 15839/* File: armv5te/alt_stub.S */ 15840/* 15841 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15842 * any interesting requests and then jump to the real instruction 15843 * handler. Note that the call to dvmCheckInst is done as a tail call. 15844 */ 15845 adrl lr, dvmAsmInstructionStart + (196 * 64) 15846 mov r0, rPC @ arg0 15847 mov r1, rSELF @ arg1 15848 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15849 15850/* ------------------------------ */ 15851 .balign 64 15852.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */ 15853/* File: armv5te/alt_stub.S */ 15854/* 15855 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15856 * any interesting requests and then jump to the real instruction 15857 * handler. Note that the call to dvmCheckInst is done as a tail call. 15858 */ 15859 adrl lr, dvmAsmInstructionStart + (197 * 64) 15860 mov r0, rPC @ arg0 15861 mov r1, rSELF @ arg1 15862 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15863 15864/* ------------------------------ */ 15865 .balign 64 15866.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 15867/* File: armv5te/alt_stub.S */ 15868/* 15869 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15870 * any interesting requests and then jump to the real instruction 15871 * handler. Note that the call to dvmCheckInst is done as a tail call. 15872 */ 15873 adrl lr, dvmAsmInstructionStart + (198 * 64) 15874 mov r0, rPC @ arg0 15875 mov r1, rSELF @ arg1 15876 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15877 15878/* ------------------------------ */ 15879 .balign 64 15880.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 15881/* File: armv5te/alt_stub.S */ 15882/* 15883 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15884 * any interesting requests and then jump to the real instruction 15885 * handler. Note that the call to dvmCheckInst is done as a tail call. 15886 */ 15887 adrl lr, dvmAsmInstructionStart + (199 * 64) 15888 mov r0, rPC @ arg0 15889 mov r1, rSELF @ arg1 15890 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15891 15892/* ------------------------------ */ 15893 .balign 64 15894.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 15895/* File: armv5te/alt_stub.S */ 15896/* 15897 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15898 * any interesting requests and then jump to the real instruction 15899 * handler. Note that the call to dvmCheckInst is done as a tail call. 15900 */ 15901 adrl lr, dvmAsmInstructionStart + (200 * 64) 15902 mov r0, rPC @ arg0 15903 mov r1, rSELF @ arg1 15904 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15905 15906/* ------------------------------ */ 15907 .balign 64 15908.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 15909/* File: armv5te/alt_stub.S */ 15910/* 15911 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15912 * any interesting requests and then jump to the real instruction 15913 * handler. Note that the call to dvmCheckInst is done as a tail call. 15914 */ 15915 adrl lr, dvmAsmInstructionStart + (201 * 64) 15916 mov r0, rPC @ arg0 15917 mov r1, rSELF @ arg1 15918 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15919 15920/* ------------------------------ */ 15921 .balign 64 15922.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */ 15923/* File: armv5te/alt_stub.S */ 15924/* 15925 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15926 * any interesting requests and then jump to the real instruction 15927 * handler. Note that the call to dvmCheckInst is done as a tail call. 15928 */ 15929 adrl lr, dvmAsmInstructionStart + (202 * 64) 15930 mov r0, rPC @ arg0 15931 mov r1, rSELF @ arg1 15932 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15933 15934/* ------------------------------ */ 15935 .balign 64 15936.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 15937/* File: armv5te/alt_stub.S */ 15938/* 15939 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15940 * any interesting requests and then jump to the real instruction 15941 * handler. Note that the call to dvmCheckInst is done as a tail call. 15942 */ 15943 adrl lr, dvmAsmInstructionStart + (203 * 64) 15944 mov r0, rPC @ arg0 15945 mov r1, rSELF @ arg1 15946 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15947 15948/* ------------------------------ */ 15949 .balign 64 15950.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 15951/* File: armv5te/alt_stub.S */ 15952/* 15953 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15954 * any interesting requests and then jump to the real instruction 15955 * handler. Note that the call to dvmCheckInst is done as a tail call. 15956 */ 15957 adrl lr, dvmAsmInstructionStart + (204 * 64) 15958 mov r0, rPC @ arg0 15959 mov r1, rSELF @ arg1 15960 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15961 15962/* ------------------------------ */ 15963 .balign 64 15964.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 15965/* File: armv5te/alt_stub.S */ 15966/* 15967 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15968 * any interesting requests and then jump to the real instruction 15969 * handler. Note that the call to dvmCheckInst is done as a tail call. 15970 */ 15971 adrl lr, dvmAsmInstructionStart + (205 * 64) 15972 mov r0, rPC @ arg0 15973 mov r1, rSELF @ arg1 15974 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15975 15976/* ------------------------------ */ 15977 .balign 64 15978.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 15979/* File: armv5te/alt_stub.S */ 15980/* 15981 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15982 * any interesting requests and then jump to the real instruction 15983 * handler. Note that the call to dvmCheckInst is done as a tail call. 15984 */ 15985 adrl lr, dvmAsmInstructionStart + (206 * 64) 15986 mov r0, rPC @ arg0 15987 mov r1, rSELF @ arg1 15988 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15989 15990/* ------------------------------ */ 15991 .balign 64 15992.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 15993/* File: armv5te/alt_stub.S */ 15994/* 15995 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15996 * any interesting requests and then jump to the real instruction 15997 * handler. Note that the call to dvmCheckInst is done as a tail call. 15998 */ 15999 adrl lr, dvmAsmInstructionStart + (207 * 64) 16000 mov r0, rPC @ arg0 16001 mov r1, rSELF @ arg1 16002 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16003 16004/* ------------------------------ */ 16005 .balign 64 16006.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */ 16007/* File: armv5te/alt_stub.S */ 16008/* 16009 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16010 * any interesting requests and then jump to the real instruction 16011 * handler. Note that the call to dvmCheckInst is done as a tail call. 16012 */ 16013 adrl lr, dvmAsmInstructionStart + (208 * 64) 16014 mov r0, rPC @ arg0 16015 mov r1, rSELF @ arg1 16016 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16017 16018/* ------------------------------ */ 16019 .balign 64 16020.L_ALT_OP_RSUB_INT: /* 0xd1 */ 16021/* File: armv5te/alt_stub.S */ 16022/* 16023 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16024 * any interesting requests and then jump to the real instruction 16025 * handler. Note that the call to dvmCheckInst is done as a tail call. 16026 */ 16027 adrl lr, dvmAsmInstructionStart + (209 * 64) 16028 mov r0, rPC @ arg0 16029 mov r1, rSELF @ arg1 16030 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16031 16032/* ------------------------------ */ 16033 .balign 64 16034.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */ 16035/* File: armv5te/alt_stub.S */ 16036/* 16037 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16038 * any interesting requests and then jump to the real instruction 16039 * handler. Note that the call to dvmCheckInst is done as a tail call. 16040 */ 16041 adrl lr, dvmAsmInstructionStart + (210 * 64) 16042 mov r0, rPC @ arg0 16043 mov r1, rSELF @ arg1 16044 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16045 16046/* ------------------------------ */ 16047 .balign 64 16048.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */ 16049/* File: armv5te/alt_stub.S */ 16050/* 16051 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16052 * any interesting requests and then jump to the real instruction 16053 * handler. Note that the call to dvmCheckInst is done as a tail call. 16054 */ 16055 adrl lr, dvmAsmInstructionStart + (211 * 64) 16056 mov r0, rPC @ arg0 16057 mov r1, rSELF @ arg1 16058 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16059 16060/* ------------------------------ */ 16061 .balign 64 16062.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */ 16063/* File: armv5te/alt_stub.S */ 16064/* 16065 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16066 * any interesting requests and then jump to the real instruction 16067 * handler. Note that the call to dvmCheckInst is done as a tail call. 16068 */ 16069 adrl lr, dvmAsmInstructionStart + (212 * 64) 16070 mov r0, rPC @ arg0 16071 mov r1, rSELF @ arg1 16072 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16073 16074/* ------------------------------ */ 16075 .balign 64 16076.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */ 16077/* File: armv5te/alt_stub.S */ 16078/* 16079 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16080 * any interesting requests and then jump to the real instruction 16081 * handler. Note that the call to dvmCheckInst is done as a tail call. 16082 */ 16083 adrl lr, dvmAsmInstructionStart + (213 * 64) 16084 mov r0, rPC @ arg0 16085 mov r1, rSELF @ arg1 16086 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16087 16088/* ------------------------------ */ 16089 .balign 64 16090.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */ 16091/* File: armv5te/alt_stub.S */ 16092/* 16093 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16094 * any interesting requests and then jump to the real instruction 16095 * handler. Note that the call to dvmCheckInst is done as a tail call. 16096 */ 16097 adrl lr, dvmAsmInstructionStart + (214 * 64) 16098 mov r0, rPC @ arg0 16099 mov r1, rSELF @ arg1 16100 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16101 16102/* ------------------------------ */ 16103 .balign 64 16104.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */ 16105/* File: armv5te/alt_stub.S */ 16106/* 16107 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16108 * any interesting requests and then jump to the real instruction 16109 * handler. Note that the call to dvmCheckInst is done as a tail call. 16110 */ 16111 adrl lr, dvmAsmInstructionStart + (215 * 64) 16112 mov r0, rPC @ arg0 16113 mov r1, rSELF @ arg1 16114 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16115 16116/* ------------------------------ */ 16117 .balign 64 16118.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */ 16119/* File: armv5te/alt_stub.S */ 16120/* 16121 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16122 * any interesting requests and then jump to the real instruction 16123 * handler. Note that the call to dvmCheckInst is done as a tail call. 16124 */ 16125 adrl lr, dvmAsmInstructionStart + (216 * 64) 16126 mov r0, rPC @ arg0 16127 mov r1, rSELF @ arg1 16128 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16129 16130/* ------------------------------ */ 16131 .balign 64 16132.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */ 16133/* File: armv5te/alt_stub.S */ 16134/* 16135 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16136 * any interesting requests and then jump to the real instruction 16137 * handler. Note that the call to dvmCheckInst is done as a tail call. 16138 */ 16139 adrl lr, dvmAsmInstructionStart + (217 * 64) 16140 mov r0, rPC @ arg0 16141 mov r1, rSELF @ arg1 16142 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16143 16144/* ------------------------------ */ 16145 .balign 64 16146.L_ALT_OP_MUL_INT_LIT8: /* 0xda */ 16147/* File: armv5te/alt_stub.S */ 16148/* 16149 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16150 * any interesting requests and then jump to the real instruction 16151 * handler. Note that the call to dvmCheckInst is done as a tail call. 16152 */ 16153 adrl lr, dvmAsmInstructionStart + (218 * 64) 16154 mov r0, rPC @ arg0 16155 mov r1, rSELF @ arg1 16156 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16157 16158/* ------------------------------ */ 16159 .balign 64 16160.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */ 16161/* File: armv5te/alt_stub.S */ 16162/* 16163 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16164 * any interesting requests and then jump to the real instruction 16165 * handler. Note that the call to dvmCheckInst is done as a tail call. 16166 */ 16167 adrl lr, dvmAsmInstructionStart + (219 * 64) 16168 mov r0, rPC @ arg0 16169 mov r1, rSELF @ arg1 16170 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16171 16172/* ------------------------------ */ 16173 .balign 64 16174.L_ALT_OP_REM_INT_LIT8: /* 0xdc */ 16175/* File: armv5te/alt_stub.S */ 16176/* 16177 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16178 * any interesting requests and then jump to the real instruction 16179 * handler. Note that the call to dvmCheckInst is done as a tail call. 16180 */ 16181 adrl lr, dvmAsmInstructionStart + (220 * 64) 16182 mov r0, rPC @ arg0 16183 mov r1, rSELF @ arg1 16184 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16185 16186/* ------------------------------ */ 16187 .balign 64 16188.L_ALT_OP_AND_INT_LIT8: /* 0xdd */ 16189/* File: armv5te/alt_stub.S */ 16190/* 16191 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16192 * any interesting requests and then jump to the real instruction 16193 * handler. Note that the call to dvmCheckInst is done as a tail call. 16194 */ 16195 adrl lr, dvmAsmInstructionStart + (221 * 64) 16196 mov r0, rPC @ arg0 16197 mov r1, rSELF @ arg1 16198 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16199 16200/* ------------------------------ */ 16201 .balign 64 16202.L_ALT_OP_OR_INT_LIT8: /* 0xde */ 16203/* File: armv5te/alt_stub.S */ 16204/* 16205 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16206 * any interesting requests and then jump to the real instruction 16207 * handler. Note that the call to dvmCheckInst is done as a tail call. 16208 */ 16209 adrl lr, dvmAsmInstructionStart + (222 * 64) 16210 mov r0, rPC @ arg0 16211 mov r1, rSELF @ arg1 16212 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16213 16214/* ------------------------------ */ 16215 .balign 64 16216.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */ 16217/* File: armv5te/alt_stub.S */ 16218/* 16219 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16220 * any interesting requests and then jump to the real instruction 16221 * handler. Note that the call to dvmCheckInst is done as a tail call. 16222 */ 16223 adrl lr, dvmAsmInstructionStart + (223 * 64) 16224 mov r0, rPC @ arg0 16225 mov r1, rSELF @ arg1 16226 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16227 16228/* ------------------------------ */ 16229 .balign 64 16230.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */ 16231/* File: armv5te/alt_stub.S */ 16232/* 16233 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16234 * any interesting requests and then jump to the real instruction 16235 * handler. Note that the call to dvmCheckInst is done as a tail call. 16236 */ 16237 adrl lr, dvmAsmInstructionStart + (224 * 64) 16238 mov r0, rPC @ arg0 16239 mov r1, rSELF @ arg1 16240 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16241 16242/* ------------------------------ */ 16243 .balign 64 16244.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */ 16245/* File: armv5te/alt_stub.S */ 16246/* 16247 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16248 * any interesting requests and then jump to the real instruction 16249 * handler. Note that the call to dvmCheckInst is done as a tail call. 16250 */ 16251 adrl lr, dvmAsmInstructionStart + (225 * 64) 16252 mov r0, rPC @ arg0 16253 mov r1, rSELF @ arg1 16254 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16255 16256/* ------------------------------ */ 16257 .balign 64 16258.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */ 16259/* File: armv5te/alt_stub.S */ 16260/* 16261 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16262 * any interesting requests and then jump to the real instruction 16263 * handler. Note that the call to dvmCheckInst is done as a tail call. 16264 */ 16265 adrl lr, dvmAsmInstructionStart + (226 * 64) 16266 mov r0, rPC @ arg0 16267 mov r1, rSELF @ arg1 16268 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16269 16270/* ------------------------------ */ 16271 .balign 64 16272.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */ 16273/* File: armv5te/alt_stub.S */ 16274/* 16275 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16276 * any interesting requests and then jump to the real instruction 16277 * handler. Note that the call to dvmCheckInst is done as a tail call. 16278 */ 16279 adrl lr, dvmAsmInstructionStart + (227 * 64) 16280 mov r0, rPC @ arg0 16281 mov r1, rSELF @ arg1 16282 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16283 16284/* ------------------------------ */ 16285 .balign 64 16286.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */ 16287/* File: armv5te/alt_stub.S */ 16288/* 16289 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16290 * any interesting requests and then jump to the real instruction 16291 * handler. Note that the call to dvmCheckInst is done as a tail call. 16292 */ 16293 adrl lr, dvmAsmInstructionStart + (228 * 64) 16294 mov r0, rPC @ arg0 16295 mov r1, rSELF @ arg1 16296 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16297 16298/* ------------------------------ */ 16299 .balign 64 16300.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */ 16301/* File: armv5te/alt_stub.S */ 16302/* 16303 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16304 * any interesting requests and then jump to the real instruction 16305 * handler. Note that the call to dvmCheckInst is done as a tail call. 16306 */ 16307 adrl lr, dvmAsmInstructionStart + (229 * 64) 16308 mov r0, rPC @ arg0 16309 mov r1, rSELF @ arg1 16310 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16311 16312/* ------------------------------ */ 16313 .balign 64 16314.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */ 16315/* File: armv5te/alt_stub.S */ 16316/* 16317 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16318 * any interesting requests and then jump to the real instruction 16319 * handler. Note that the call to dvmCheckInst is done as a tail call. 16320 */ 16321 adrl lr, dvmAsmInstructionStart + (230 * 64) 16322 mov r0, rPC @ arg0 16323 mov r1, rSELF @ arg1 16324 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16325 16326/* ------------------------------ */ 16327 .balign 64 16328.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 16329/* File: armv5te/alt_stub.S */ 16330/* 16331 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16332 * any interesting requests and then jump to the real instruction 16333 * handler. Note that the call to dvmCheckInst is done as a tail call. 16334 */ 16335 adrl lr, dvmAsmInstructionStart + (231 * 64) 16336 mov r0, rPC @ arg0 16337 mov r1, rSELF @ arg1 16338 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16339 16340/* ------------------------------ */ 16341 .balign 64 16342.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 16343/* File: armv5te/alt_stub.S */ 16344/* 16345 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16346 * any interesting requests and then jump to the real instruction 16347 * handler. Note that the call to dvmCheckInst is done as a tail call. 16348 */ 16349 adrl lr, dvmAsmInstructionStart + (232 * 64) 16350 mov r0, rPC @ arg0 16351 mov r1, rSELF @ arg1 16352 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16353 16354/* ------------------------------ */ 16355 .balign 64 16356.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 16357/* File: armv5te/alt_stub.S */ 16358/* 16359 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16360 * any interesting requests and then jump to the real instruction 16361 * handler. Note that the call to dvmCheckInst is done as a tail call. 16362 */ 16363 adrl lr, dvmAsmInstructionStart + (233 * 64) 16364 mov r0, rPC @ arg0 16365 mov r1, rSELF @ arg1 16366 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16367 16368/* ------------------------------ */ 16369 .balign 64 16370.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */ 16371/* File: armv5te/alt_stub.S */ 16372/* 16373 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16374 * any interesting requests and then jump to the real instruction 16375 * handler. Note that the call to dvmCheckInst is done as a tail call. 16376 */ 16377 adrl lr, dvmAsmInstructionStart + (234 * 64) 16378 mov r0, rPC @ arg0 16379 mov r1, rSELF @ arg1 16380 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16381 16382/* ------------------------------ */ 16383 .balign 64 16384.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 16385/* File: armv5te/alt_stub.S */ 16386/* 16387 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16388 * any interesting requests and then jump to the real instruction 16389 * handler. Note that the call to dvmCheckInst is done as a tail call. 16390 */ 16391 adrl lr, dvmAsmInstructionStart + (235 * 64) 16392 mov r0, rPC @ arg0 16393 mov r1, rSELF @ arg1 16394 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16395 16396/* ------------------------------ */ 16397 .balign 64 16398.L_ALT_OP_BREAKPOINT: /* 0xec */ 16399/* File: armv5te/alt_stub.S */ 16400/* 16401 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16402 * any interesting requests and then jump to the real instruction 16403 * handler. Note that the call to dvmCheckInst is done as a tail call. 16404 */ 16405 adrl lr, dvmAsmInstructionStart + (236 * 64) 16406 mov r0, rPC @ arg0 16407 mov r1, rSELF @ arg1 16408 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16409 16410/* ------------------------------ */ 16411 .balign 64 16412.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 16413/* File: armv5te/alt_stub.S */ 16414/* 16415 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16416 * any interesting requests and then jump to the real instruction 16417 * handler. Note that the call to dvmCheckInst is done as a tail call. 16418 */ 16419 adrl lr, dvmAsmInstructionStart + (237 * 64) 16420 mov r0, rPC @ arg0 16421 mov r1, rSELF @ arg1 16422 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16423 16424/* ------------------------------ */ 16425 .balign 64 16426.L_ALT_OP_EXECUTE_INLINE: /* 0xee */ 16427/* File: armv5te/alt_stub.S */ 16428/* 16429 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16430 * any interesting requests and then jump to the real instruction 16431 * handler. Note that the call to dvmCheckInst is done as a tail call. 16432 */ 16433 adrl lr, dvmAsmInstructionStart + (238 * 64) 16434 mov r0, rPC @ arg0 16435 mov r1, rSELF @ arg1 16436 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16437 16438/* ------------------------------ */ 16439 .balign 64 16440.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 16441/* File: armv5te/alt_stub.S */ 16442/* 16443 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16444 * any interesting requests and then jump to the real instruction 16445 * handler. Note that the call to dvmCheckInst is done as a tail call. 16446 */ 16447 adrl lr, dvmAsmInstructionStart + (239 * 64) 16448 mov r0, rPC @ arg0 16449 mov r1, rSELF @ arg1 16450 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16451 16452/* ------------------------------ */ 16453 .balign 64 16454.L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 16455/* File: armv5te/alt_stub.S */ 16456/* 16457 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16458 * any interesting requests and then jump to the real instruction 16459 * handler. Note that the call to dvmCheckInst is done as a tail call. 16460 */ 16461 adrl lr, dvmAsmInstructionStart + (240 * 64) 16462 mov r0, rPC @ arg0 16463 mov r1, rSELF @ arg1 16464 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16465 16466/* ------------------------------ */ 16467 .balign 64 16468.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 16469/* File: armv5te/alt_stub.S */ 16470/* 16471 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16472 * any interesting requests and then jump to the real instruction 16473 * handler. Note that the call to dvmCheckInst is done as a tail call. 16474 */ 16475 adrl lr, dvmAsmInstructionStart + (241 * 64) 16476 mov r0, rPC @ arg0 16477 mov r1, rSELF @ arg1 16478 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16479 16480/* ------------------------------ */ 16481 .balign 64 16482.L_ALT_OP_IGET_QUICK: /* 0xf2 */ 16483/* File: armv5te/alt_stub.S */ 16484/* 16485 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16486 * any interesting requests and then jump to the real instruction 16487 * handler. Note that the call to dvmCheckInst is done as a tail call. 16488 */ 16489 adrl lr, dvmAsmInstructionStart + (242 * 64) 16490 mov r0, rPC @ arg0 16491 mov r1, rSELF @ arg1 16492 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16493 16494/* ------------------------------ */ 16495 .balign 64 16496.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */ 16497/* File: armv5te/alt_stub.S */ 16498/* 16499 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16500 * any interesting requests and then jump to the real instruction 16501 * handler. Note that the call to dvmCheckInst is done as a tail call. 16502 */ 16503 adrl lr, dvmAsmInstructionStart + (243 * 64) 16504 mov r0, rPC @ arg0 16505 mov r1, rSELF @ arg1 16506 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16507 16508/* ------------------------------ */ 16509 .balign 64 16510.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 16511/* File: armv5te/alt_stub.S */ 16512/* 16513 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16514 * any interesting requests and then jump to the real instruction 16515 * handler. Note that the call to dvmCheckInst is done as a tail call. 16516 */ 16517 adrl lr, dvmAsmInstructionStart + (244 * 64) 16518 mov r0, rPC @ arg0 16519 mov r1, rSELF @ arg1 16520 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16521 16522/* ------------------------------ */ 16523 .balign 64 16524.L_ALT_OP_IPUT_QUICK: /* 0xf5 */ 16525/* File: armv5te/alt_stub.S */ 16526/* 16527 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16528 * any interesting requests and then jump to the real instruction 16529 * handler. Note that the call to dvmCheckInst is done as a tail call. 16530 */ 16531 adrl lr, dvmAsmInstructionStart + (245 * 64) 16532 mov r0, rPC @ arg0 16533 mov r1, rSELF @ arg1 16534 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16535 16536/* ------------------------------ */ 16537 .balign 64 16538.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 16539/* File: armv5te/alt_stub.S */ 16540/* 16541 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16542 * any interesting requests and then jump to the real instruction 16543 * handler. Note that the call to dvmCheckInst is done as a tail call. 16544 */ 16545 adrl lr, dvmAsmInstructionStart + (246 * 64) 16546 mov r0, rPC @ arg0 16547 mov r1, rSELF @ arg1 16548 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16549 16550/* ------------------------------ */ 16551 .balign 64 16552.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 16553/* File: armv5te/alt_stub.S */ 16554/* 16555 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16556 * any interesting requests and then jump to the real instruction 16557 * handler. Note that the call to dvmCheckInst is done as a tail call. 16558 */ 16559 adrl lr, dvmAsmInstructionStart + (247 * 64) 16560 mov r0, rPC @ arg0 16561 mov r1, rSELF @ arg1 16562 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16563 16564/* ------------------------------ */ 16565 .balign 64 16566.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 16567/* File: armv5te/alt_stub.S */ 16568/* 16569 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16570 * any interesting requests and then jump to the real instruction 16571 * handler. Note that the call to dvmCheckInst is done as a tail call. 16572 */ 16573 adrl lr, dvmAsmInstructionStart + (248 * 64) 16574 mov r0, rPC @ arg0 16575 mov r1, rSELF @ arg1 16576 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16577 16578/* ------------------------------ */ 16579 .balign 64 16580.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 16581/* File: armv5te/alt_stub.S */ 16582/* 16583 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16584 * any interesting requests and then jump to the real instruction 16585 * handler. Note that the call to dvmCheckInst is done as a tail call. 16586 */ 16587 adrl lr, dvmAsmInstructionStart + (249 * 64) 16588 mov r0, rPC @ arg0 16589 mov r1, rSELF @ arg1 16590 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16591 16592/* ------------------------------ */ 16593 .balign 64 16594.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 16595/* File: armv5te/alt_stub.S */ 16596/* 16597 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16598 * any interesting requests and then jump to the real instruction 16599 * handler. Note that the call to dvmCheckInst is done as a tail call. 16600 */ 16601 adrl lr, dvmAsmInstructionStart + (250 * 64) 16602 mov r0, rPC @ arg0 16603 mov r1, rSELF @ arg1 16604 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16605 16606/* ------------------------------ */ 16607 .balign 64 16608.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 16609/* File: armv5te/alt_stub.S */ 16610/* 16611 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16612 * any interesting requests and then jump to the real instruction 16613 * handler. Note that the call to dvmCheckInst is done as a tail call. 16614 */ 16615 adrl lr, dvmAsmInstructionStart + (251 * 64) 16616 mov r0, rPC @ arg0 16617 mov r1, rSELF @ arg1 16618 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16619 16620/* ------------------------------ */ 16621 .balign 64 16622.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 16623/* File: armv5te/alt_stub.S */ 16624/* 16625 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16626 * any interesting requests and then jump to the real instruction 16627 * handler. Note that the call to dvmCheckInst is done as a tail call. 16628 */ 16629 adrl lr, dvmAsmInstructionStart + (252 * 64) 16630 mov r0, rPC @ arg0 16631 mov r1, rSELF @ arg1 16632 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16633 16634/* ------------------------------ */ 16635 .balign 64 16636.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 16637/* File: armv5te/alt_stub.S */ 16638/* 16639 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16640 * any interesting requests and then jump to the real instruction 16641 * handler. Note that the call to dvmCheckInst is done as a tail call. 16642 */ 16643 adrl lr, dvmAsmInstructionStart + (253 * 64) 16644 mov r0, rPC @ arg0 16645 mov r1, rSELF @ arg1 16646 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16647 16648/* ------------------------------ */ 16649 .balign 64 16650.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 16651/* File: armv5te/alt_stub.S */ 16652/* 16653 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16654 * any interesting requests and then jump to the real instruction 16655 * handler. Note that the call to dvmCheckInst is done as a tail call. 16656 */ 16657 adrl lr, dvmAsmInstructionStart + (254 * 64) 16658 mov r0, rPC @ arg0 16659 mov r1, rSELF @ arg1 16660 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16661 16662/* ------------------------------ */ 16663 .balign 64 16664.L_ALT_OP_DISPATCH_FF: /* 0xff */ 16665/* File: armv5te/alt_stub.S */ 16666/* 16667 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16668 * any interesting requests and then jump to the real instruction 16669 * handler. Note that the call to dvmCheckInst is done as a tail call. 16670 */ 16671 adrl lr, dvmAsmInstructionStart + (255 * 64) 16672 mov r0, rPC @ arg0 16673 mov r1, rSELF @ arg1 16674 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16675 16676/* ------------------------------ */ 16677 .balign 64 16678.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */ 16679/* File: armv5te/alt_stub.S */ 16680/* 16681 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16682 * any interesting requests and then jump to the real instruction 16683 * handler. Note that the call to dvmCheckInst is done as a tail call. 16684 */ 16685 adrl lr, dvmAsmInstructionStart + (256 * 64) 16686 mov r0, rPC @ arg0 16687 mov r1, rSELF @ arg1 16688 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16689 16690/* ------------------------------ */ 16691 .balign 64 16692.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */ 16693/* File: armv5te/alt_stub.S */ 16694/* 16695 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16696 * any interesting requests and then jump to the real instruction 16697 * handler. Note that the call to dvmCheckInst is done as a tail call. 16698 */ 16699 adrl lr, dvmAsmInstructionStart + (257 * 64) 16700 mov r0, rPC @ arg0 16701 mov r1, rSELF @ arg1 16702 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16703 16704/* ------------------------------ */ 16705 .balign 64 16706.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 16707/* File: armv5te/alt_stub.S */ 16708/* 16709 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16710 * any interesting requests and then jump to the real instruction 16711 * handler. Note that the call to dvmCheckInst is done as a tail call. 16712 */ 16713 adrl lr, dvmAsmInstructionStart + (258 * 64) 16714 mov r0, rPC @ arg0 16715 mov r1, rSELF @ arg1 16716 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16717 16718/* ------------------------------ */ 16719 .balign 64 16720.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 16721/* File: armv5te/alt_stub.S */ 16722/* 16723 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16724 * any interesting requests and then jump to the real instruction 16725 * handler. Note that the call to dvmCheckInst is done as a tail call. 16726 */ 16727 adrl lr, dvmAsmInstructionStart + (259 * 64) 16728 mov r0, rPC @ arg0 16729 mov r1, rSELF @ arg1 16730 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16731 16732/* ------------------------------ */ 16733 .balign 64 16734.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 16735/* File: armv5te/alt_stub.S */ 16736/* 16737 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16738 * any interesting requests and then jump to the real instruction 16739 * handler. Note that the call to dvmCheckInst is done as a tail call. 16740 */ 16741 adrl lr, dvmAsmInstructionStart + (260 * 64) 16742 mov r0, rPC @ arg0 16743 mov r1, rSELF @ arg1 16744 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16745 16746/* ------------------------------ */ 16747 .balign 64 16748.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 16749/* File: armv5te/alt_stub.S */ 16750/* 16751 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16752 * any interesting requests and then jump to the real instruction 16753 * handler. Note that the call to dvmCheckInst is done as a tail call. 16754 */ 16755 adrl lr, dvmAsmInstructionStart + (261 * 64) 16756 mov r0, rPC @ arg0 16757 mov r1, rSELF @ arg1 16758 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16759 16760/* ------------------------------ */ 16761 .balign 64 16762.L_ALT_OP_IGET_JUMBO: /* 0x106 */ 16763/* File: armv5te/alt_stub.S */ 16764/* 16765 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16766 * any interesting requests and then jump to the real instruction 16767 * handler. Note that the call to dvmCheckInst is done as a tail call. 16768 */ 16769 adrl lr, dvmAsmInstructionStart + (262 * 64) 16770 mov r0, rPC @ arg0 16771 mov r1, rSELF @ arg1 16772 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16773 16774/* ------------------------------ */ 16775 .balign 64 16776.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */ 16777/* File: armv5te/alt_stub.S */ 16778/* 16779 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16780 * any interesting requests and then jump to the real instruction 16781 * handler. Note that the call to dvmCheckInst is done as a tail call. 16782 */ 16783 adrl lr, dvmAsmInstructionStart + (263 * 64) 16784 mov r0, rPC @ arg0 16785 mov r1, rSELF @ arg1 16786 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16787 16788/* ------------------------------ */ 16789 .balign 64 16790.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 16791/* File: armv5te/alt_stub.S */ 16792/* 16793 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16794 * any interesting requests and then jump to the real instruction 16795 * handler. Note that the call to dvmCheckInst is done as a tail call. 16796 */ 16797 adrl lr, dvmAsmInstructionStart + (264 * 64) 16798 mov r0, rPC @ arg0 16799 mov r1, rSELF @ arg1 16800 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16801 16802/* ------------------------------ */ 16803 .balign 64 16804.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 16805/* File: armv5te/alt_stub.S */ 16806/* 16807 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16808 * any interesting requests and then jump to the real instruction 16809 * handler. Note that the call to dvmCheckInst is done as a tail call. 16810 */ 16811 adrl lr, dvmAsmInstructionStart + (265 * 64) 16812 mov r0, rPC @ arg0 16813 mov r1, rSELF @ arg1 16814 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16815 16816/* ------------------------------ */ 16817 .balign 64 16818.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */ 16819/* File: armv5te/alt_stub.S */ 16820/* 16821 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16822 * any interesting requests and then jump to the real instruction 16823 * handler. Note that the call to dvmCheckInst is done as a tail call. 16824 */ 16825 adrl lr, dvmAsmInstructionStart + (266 * 64) 16826 mov r0, rPC @ arg0 16827 mov r1, rSELF @ arg1 16828 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16829 16830/* ------------------------------ */ 16831 .balign 64 16832.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */ 16833/* File: armv5te/alt_stub.S */ 16834/* 16835 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16836 * any interesting requests and then jump to the real instruction 16837 * handler. Note that the call to dvmCheckInst is done as a tail call. 16838 */ 16839 adrl lr, dvmAsmInstructionStart + (267 * 64) 16840 mov r0, rPC @ arg0 16841 mov r1, rSELF @ arg1 16842 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16843 16844/* ------------------------------ */ 16845 .balign 64 16846.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */ 16847/* File: armv5te/alt_stub.S */ 16848/* 16849 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16850 * any interesting requests and then jump to the real instruction 16851 * handler. Note that the call to dvmCheckInst is done as a tail call. 16852 */ 16853 adrl lr, dvmAsmInstructionStart + (268 * 64) 16854 mov r0, rPC @ arg0 16855 mov r1, rSELF @ arg1 16856 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16857 16858/* ------------------------------ */ 16859 .balign 64 16860.L_ALT_OP_IPUT_JUMBO: /* 0x10d */ 16861/* File: armv5te/alt_stub.S */ 16862/* 16863 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16864 * any interesting requests and then jump to the real instruction 16865 * handler. Note that the call to dvmCheckInst is done as a tail call. 16866 */ 16867 adrl lr, dvmAsmInstructionStart + (269 * 64) 16868 mov r0, rPC @ arg0 16869 mov r1, rSELF @ arg1 16870 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16871 16872/* ------------------------------ */ 16873 .balign 64 16874.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 16875/* File: armv5te/alt_stub.S */ 16876/* 16877 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16878 * any interesting requests and then jump to the real instruction 16879 * handler. Note that the call to dvmCheckInst is done as a tail call. 16880 */ 16881 adrl lr, dvmAsmInstructionStart + (270 * 64) 16882 mov r0, rPC @ arg0 16883 mov r1, rSELF @ arg1 16884 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16885 16886/* ------------------------------ */ 16887 .balign 64 16888.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 16889/* File: armv5te/alt_stub.S */ 16890/* 16891 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16892 * any interesting requests and then jump to the real instruction 16893 * handler. Note that the call to dvmCheckInst is done as a tail call. 16894 */ 16895 adrl lr, dvmAsmInstructionStart + (271 * 64) 16896 mov r0, rPC @ arg0 16897 mov r1, rSELF @ arg1 16898 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16899 16900/* ------------------------------ */ 16901 .balign 64 16902.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 16903/* File: armv5te/alt_stub.S */ 16904/* 16905 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16906 * any interesting requests and then jump to the real instruction 16907 * handler. Note that the call to dvmCheckInst is done as a tail call. 16908 */ 16909 adrl lr, dvmAsmInstructionStart + (272 * 64) 16910 mov r0, rPC @ arg0 16911 mov r1, rSELF @ arg1 16912 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16913 16914/* ------------------------------ */ 16915 .balign 64 16916.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 16917/* File: armv5te/alt_stub.S */ 16918/* 16919 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16920 * any interesting requests and then jump to the real instruction 16921 * handler. Note that the call to dvmCheckInst is done as a tail call. 16922 */ 16923 adrl lr, dvmAsmInstructionStart + (273 * 64) 16924 mov r0, rPC @ arg0 16925 mov r1, rSELF @ arg1 16926 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16927 16928/* ------------------------------ */ 16929 .balign 64 16930.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 16931/* File: armv5te/alt_stub.S */ 16932/* 16933 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16934 * any interesting requests and then jump to the real instruction 16935 * handler. Note that the call to dvmCheckInst is done as a tail call. 16936 */ 16937 adrl lr, dvmAsmInstructionStart + (274 * 64) 16938 mov r0, rPC @ arg0 16939 mov r1, rSELF @ arg1 16940 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16941 16942/* ------------------------------ */ 16943 .balign 64 16944.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 16945/* File: armv5te/alt_stub.S */ 16946/* 16947 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16948 * any interesting requests and then jump to the real instruction 16949 * handler. Note that the call to dvmCheckInst is done as a tail call. 16950 */ 16951 adrl lr, dvmAsmInstructionStart + (275 * 64) 16952 mov r0, rPC @ arg0 16953 mov r1, rSELF @ arg1 16954 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16955 16956/* ------------------------------ */ 16957 .balign 64 16958.L_ALT_OP_SGET_JUMBO: /* 0x114 */ 16959/* File: armv5te/alt_stub.S */ 16960/* 16961 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16962 * any interesting requests and then jump to the real instruction 16963 * handler. Note that the call to dvmCheckInst is done as a tail call. 16964 */ 16965 adrl lr, dvmAsmInstructionStart + (276 * 64) 16966 mov r0, rPC @ arg0 16967 mov r1, rSELF @ arg1 16968 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16969 16970/* ------------------------------ */ 16971 .balign 64 16972.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */ 16973/* File: armv5te/alt_stub.S */ 16974/* 16975 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16976 * any interesting requests and then jump to the real instruction 16977 * handler. Note that the call to dvmCheckInst is done as a tail call. 16978 */ 16979 adrl lr, dvmAsmInstructionStart + (277 * 64) 16980 mov r0, rPC @ arg0 16981 mov r1, rSELF @ arg1 16982 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16983 16984/* ------------------------------ */ 16985 .balign 64 16986.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 16987/* File: armv5te/alt_stub.S */ 16988/* 16989 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16990 * any interesting requests and then jump to the real instruction 16991 * handler. Note that the call to dvmCheckInst is done as a tail call. 16992 */ 16993 adrl lr, dvmAsmInstructionStart + (278 * 64) 16994 mov r0, rPC @ arg0 16995 mov r1, rSELF @ arg1 16996 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16997 16998/* ------------------------------ */ 16999 .balign 64 17000.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 17001/* File: armv5te/alt_stub.S */ 17002/* 17003 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17004 * any interesting requests and then jump to the real instruction 17005 * handler. Note that the call to dvmCheckInst is done as a tail call. 17006 */ 17007 adrl lr, dvmAsmInstructionStart + (279 * 64) 17008 mov r0, rPC @ arg0 17009 mov r1, rSELF @ arg1 17010 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17011 17012/* ------------------------------ */ 17013 .balign 64 17014.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */ 17015/* File: armv5te/alt_stub.S */ 17016/* 17017 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17018 * any interesting requests and then jump to the real instruction 17019 * handler. Note that the call to dvmCheckInst is done as a tail call. 17020 */ 17021 adrl lr, dvmAsmInstructionStart + (280 * 64) 17022 mov r0, rPC @ arg0 17023 mov r1, rSELF @ arg1 17024 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17025 17026/* ------------------------------ */ 17027 .balign 64 17028.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */ 17029/* File: armv5te/alt_stub.S */ 17030/* 17031 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17032 * any interesting requests and then jump to the real instruction 17033 * handler. Note that the call to dvmCheckInst is done as a tail call. 17034 */ 17035 adrl lr, dvmAsmInstructionStart + (281 * 64) 17036 mov r0, rPC @ arg0 17037 mov r1, rSELF @ arg1 17038 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17039 17040/* ------------------------------ */ 17041 .balign 64 17042.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */ 17043/* File: armv5te/alt_stub.S */ 17044/* 17045 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17046 * any interesting requests and then jump to the real instruction 17047 * handler. Note that the call to dvmCheckInst is done as a tail call. 17048 */ 17049 adrl lr, dvmAsmInstructionStart + (282 * 64) 17050 mov r0, rPC @ arg0 17051 mov r1, rSELF @ arg1 17052 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17053 17054/* ------------------------------ */ 17055 .balign 64 17056.L_ALT_OP_SPUT_JUMBO: /* 0x11b */ 17057/* File: armv5te/alt_stub.S */ 17058/* 17059 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17060 * any interesting requests and then jump to the real instruction 17061 * handler. Note that the call to dvmCheckInst is done as a tail call. 17062 */ 17063 adrl lr, dvmAsmInstructionStart + (283 * 64) 17064 mov r0, rPC @ arg0 17065 mov r1, rSELF @ arg1 17066 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17067 17068/* ------------------------------ */ 17069 .balign 64 17070.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 17071/* File: armv5te/alt_stub.S */ 17072/* 17073 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17074 * any interesting requests and then jump to the real instruction 17075 * handler. Note that the call to dvmCheckInst is done as a tail call. 17076 */ 17077 adrl lr, dvmAsmInstructionStart + (284 * 64) 17078 mov r0, rPC @ arg0 17079 mov r1, rSELF @ arg1 17080 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17081 17082/* ------------------------------ */ 17083 .balign 64 17084.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 17085/* File: armv5te/alt_stub.S */ 17086/* 17087 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17088 * any interesting requests and then jump to the real instruction 17089 * handler. Note that the call to dvmCheckInst is done as a tail call. 17090 */ 17091 adrl lr, dvmAsmInstructionStart + (285 * 64) 17092 mov r0, rPC @ arg0 17093 mov r1, rSELF @ arg1 17094 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17095 17096/* ------------------------------ */ 17097 .balign 64 17098.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 17099/* File: armv5te/alt_stub.S */ 17100/* 17101 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17102 * any interesting requests and then jump to the real instruction 17103 * handler. Note that the call to dvmCheckInst is done as a tail call. 17104 */ 17105 adrl lr, dvmAsmInstructionStart + (286 * 64) 17106 mov r0, rPC @ arg0 17107 mov r1, rSELF @ arg1 17108 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17109 17110/* ------------------------------ */ 17111 .balign 64 17112.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 17113/* File: armv5te/alt_stub.S */ 17114/* 17115 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17116 * any interesting requests and then jump to the real instruction 17117 * handler. Note that the call to dvmCheckInst is done as a tail call. 17118 */ 17119 adrl lr, dvmAsmInstructionStart + (287 * 64) 17120 mov r0, rPC @ arg0 17121 mov r1, rSELF @ arg1 17122 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17123 17124/* ------------------------------ */ 17125 .balign 64 17126.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 17127/* File: armv5te/alt_stub.S */ 17128/* 17129 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17130 * any interesting requests and then jump to the real instruction 17131 * handler. Note that the call to dvmCheckInst is done as a tail call. 17132 */ 17133 adrl lr, dvmAsmInstructionStart + (288 * 64) 17134 mov r0, rPC @ arg0 17135 mov r1, rSELF @ arg1 17136 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17137 17138/* ------------------------------ */ 17139 .balign 64 17140.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 17141/* File: armv5te/alt_stub.S */ 17142/* 17143 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17144 * any interesting requests and then jump to the real instruction 17145 * handler. Note that the call to dvmCheckInst is done as a tail call. 17146 */ 17147 adrl lr, dvmAsmInstructionStart + (289 * 64) 17148 mov r0, rPC @ arg0 17149 mov r1, rSELF @ arg1 17150 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17151 17152/* ------------------------------ */ 17153 .balign 64 17154.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 17155/* File: armv5te/alt_stub.S */ 17156/* 17157 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17158 * any interesting requests and then jump to the real instruction 17159 * handler. Note that the call to dvmCheckInst is done as a tail call. 17160 */ 17161 adrl lr, dvmAsmInstructionStart + (290 * 64) 17162 mov r0, rPC @ arg0 17163 mov r1, rSELF @ arg1 17164 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17165 17166/* ------------------------------ */ 17167 .balign 64 17168.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 17169/* File: armv5te/alt_stub.S */ 17170/* 17171 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17172 * any interesting requests and then jump to the real instruction 17173 * handler. Note that the call to dvmCheckInst is done as a tail call. 17174 */ 17175 adrl lr, dvmAsmInstructionStart + (291 * 64) 17176 mov r0, rPC @ arg0 17177 mov r1, rSELF @ arg1 17178 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17179 17180/* ------------------------------ */ 17181 .balign 64 17182.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 17183/* File: armv5te/alt_stub.S */ 17184/* 17185 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17186 * any interesting requests and then jump to the real instruction 17187 * handler. Note that the call to dvmCheckInst is done as a tail call. 17188 */ 17189 adrl lr, dvmAsmInstructionStart + (292 * 64) 17190 mov r0, rPC @ arg0 17191 mov r1, rSELF @ arg1 17192 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17193 17194/* ------------------------------ */ 17195 .balign 64 17196.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 17197/* File: armv5te/alt_stub.S */ 17198/* 17199 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17200 * any interesting requests and then jump to the real instruction 17201 * handler. Note that the call to dvmCheckInst is done as a tail call. 17202 */ 17203 adrl lr, dvmAsmInstructionStart + (293 * 64) 17204 mov r0, rPC @ arg0 17205 mov r1, rSELF @ arg1 17206 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17207 17208/* ------------------------------ */ 17209 .balign 64 17210.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 17211/* File: armv5te/alt_stub.S */ 17212/* 17213 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17214 * any interesting requests and then jump to the real instruction 17215 * handler. Note that the call to dvmCheckInst is done as a tail call. 17216 */ 17217 adrl lr, dvmAsmInstructionStart + (294 * 64) 17218 mov r0, rPC @ arg0 17219 mov r1, rSELF @ arg1 17220 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17221 17222/* ------------------------------ */ 17223 .balign 64 17224.L_ALT_OP_UNUSED_27FF: /* 0x127 */ 17225/* File: armv5te/alt_stub.S */ 17226/* 17227 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17228 * any interesting requests and then jump to the real instruction 17229 * handler. Note that the call to dvmCheckInst is done as a tail call. 17230 */ 17231 adrl lr, dvmAsmInstructionStart + (295 * 64) 17232 mov r0, rPC @ arg0 17233 mov r1, rSELF @ arg1 17234 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17235 17236/* ------------------------------ */ 17237 .balign 64 17238.L_ALT_OP_UNUSED_28FF: /* 0x128 */ 17239/* File: armv5te/alt_stub.S */ 17240/* 17241 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17242 * any interesting requests and then jump to the real instruction 17243 * handler. Note that the call to dvmCheckInst is done as a tail call. 17244 */ 17245 adrl lr, dvmAsmInstructionStart + (296 * 64) 17246 mov r0, rPC @ arg0 17247 mov r1, rSELF @ arg1 17248 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17249 17250/* ------------------------------ */ 17251 .balign 64 17252.L_ALT_OP_UNUSED_29FF: /* 0x129 */ 17253/* File: armv5te/alt_stub.S */ 17254/* 17255 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17256 * any interesting requests and then jump to the real instruction 17257 * handler. Note that the call to dvmCheckInst is done as a tail call. 17258 */ 17259 adrl lr, dvmAsmInstructionStart + (297 * 64) 17260 mov r0, rPC @ arg0 17261 mov r1, rSELF @ arg1 17262 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17263 17264/* ------------------------------ */ 17265 .balign 64 17266.L_ALT_OP_UNUSED_2AFF: /* 0x12a */ 17267/* File: armv5te/alt_stub.S */ 17268/* 17269 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17270 * any interesting requests and then jump to the real instruction 17271 * handler. Note that the call to dvmCheckInst is done as a tail call. 17272 */ 17273 adrl lr, dvmAsmInstructionStart + (298 * 64) 17274 mov r0, rPC @ arg0 17275 mov r1, rSELF @ arg1 17276 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17277 17278/* ------------------------------ */ 17279 .balign 64 17280.L_ALT_OP_UNUSED_2BFF: /* 0x12b */ 17281/* File: armv5te/alt_stub.S */ 17282/* 17283 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17284 * any interesting requests and then jump to the real instruction 17285 * handler. Note that the call to dvmCheckInst is done as a tail call. 17286 */ 17287 adrl lr, dvmAsmInstructionStart + (299 * 64) 17288 mov r0, rPC @ arg0 17289 mov r1, rSELF @ arg1 17290 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17291 17292/* ------------------------------ */ 17293 .balign 64 17294.L_ALT_OP_UNUSED_2CFF: /* 0x12c */ 17295/* File: armv5te/alt_stub.S */ 17296/* 17297 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17298 * any interesting requests and then jump to the real instruction 17299 * handler. Note that the call to dvmCheckInst is done as a tail call. 17300 */ 17301 adrl lr, dvmAsmInstructionStart + (300 * 64) 17302 mov r0, rPC @ arg0 17303 mov r1, rSELF @ arg1 17304 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17305 17306/* ------------------------------ */ 17307 .balign 64 17308.L_ALT_OP_UNUSED_2DFF: /* 0x12d */ 17309/* File: armv5te/alt_stub.S */ 17310/* 17311 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17312 * any interesting requests and then jump to the real instruction 17313 * handler. Note that the call to dvmCheckInst is done as a tail call. 17314 */ 17315 adrl lr, dvmAsmInstructionStart + (301 * 64) 17316 mov r0, rPC @ arg0 17317 mov r1, rSELF @ arg1 17318 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17319 17320/* ------------------------------ */ 17321 .balign 64 17322.L_ALT_OP_UNUSED_2EFF: /* 0x12e */ 17323/* File: armv5te/alt_stub.S */ 17324/* 17325 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17326 * any interesting requests and then jump to the real instruction 17327 * handler. Note that the call to dvmCheckInst is done as a tail call. 17328 */ 17329 adrl lr, dvmAsmInstructionStart + (302 * 64) 17330 mov r0, rPC @ arg0 17331 mov r1, rSELF @ arg1 17332 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17333 17334/* ------------------------------ */ 17335 .balign 64 17336.L_ALT_OP_UNUSED_2FFF: /* 0x12f */ 17337/* File: armv5te/alt_stub.S */ 17338/* 17339 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17340 * any interesting requests and then jump to the real instruction 17341 * handler. Note that the call to dvmCheckInst is done as a tail call. 17342 */ 17343 adrl lr, dvmAsmInstructionStart + (303 * 64) 17344 mov r0, rPC @ arg0 17345 mov r1, rSELF @ arg1 17346 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17347 17348/* ------------------------------ */ 17349 .balign 64 17350.L_ALT_OP_UNUSED_30FF: /* 0x130 */ 17351/* File: armv5te/alt_stub.S */ 17352/* 17353 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17354 * any interesting requests and then jump to the real instruction 17355 * handler. Note that the call to dvmCheckInst is done as a tail call. 17356 */ 17357 adrl lr, dvmAsmInstructionStart + (304 * 64) 17358 mov r0, rPC @ arg0 17359 mov r1, rSELF @ arg1 17360 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17361 17362/* ------------------------------ */ 17363 .balign 64 17364.L_ALT_OP_UNUSED_31FF: /* 0x131 */ 17365/* File: armv5te/alt_stub.S */ 17366/* 17367 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17368 * any interesting requests and then jump to the real instruction 17369 * handler. Note that the call to dvmCheckInst is done as a tail call. 17370 */ 17371 adrl lr, dvmAsmInstructionStart + (305 * 64) 17372 mov r0, rPC @ arg0 17373 mov r1, rSELF @ arg1 17374 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17375 17376/* ------------------------------ */ 17377 .balign 64 17378.L_ALT_OP_UNUSED_32FF: /* 0x132 */ 17379/* File: armv5te/alt_stub.S */ 17380/* 17381 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17382 * any interesting requests and then jump to the real instruction 17383 * handler. Note that the call to dvmCheckInst is done as a tail call. 17384 */ 17385 adrl lr, dvmAsmInstructionStart + (306 * 64) 17386 mov r0, rPC @ arg0 17387 mov r1, rSELF @ arg1 17388 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17389 17390/* ------------------------------ */ 17391 .balign 64 17392.L_ALT_OP_UNUSED_33FF: /* 0x133 */ 17393/* File: armv5te/alt_stub.S */ 17394/* 17395 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17396 * any interesting requests and then jump to the real instruction 17397 * handler. Note that the call to dvmCheckInst is done as a tail call. 17398 */ 17399 adrl lr, dvmAsmInstructionStart + (307 * 64) 17400 mov r0, rPC @ arg0 17401 mov r1, rSELF @ arg1 17402 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17403 17404/* ------------------------------ */ 17405 .balign 64 17406.L_ALT_OP_UNUSED_34FF: /* 0x134 */ 17407/* File: armv5te/alt_stub.S */ 17408/* 17409 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17410 * any interesting requests and then jump to the real instruction 17411 * handler. Note that the call to dvmCheckInst is done as a tail call. 17412 */ 17413 adrl lr, dvmAsmInstructionStart + (308 * 64) 17414 mov r0, rPC @ arg0 17415 mov r1, rSELF @ arg1 17416 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17417 17418/* ------------------------------ */ 17419 .balign 64 17420.L_ALT_OP_UNUSED_35FF: /* 0x135 */ 17421/* File: armv5te/alt_stub.S */ 17422/* 17423 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17424 * any interesting requests and then jump to the real instruction 17425 * handler. Note that the call to dvmCheckInst is done as a tail call. 17426 */ 17427 adrl lr, dvmAsmInstructionStart + (309 * 64) 17428 mov r0, rPC @ arg0 17429 mov r1, rSELF @ arg1 17430 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17431 17432/* ------------------------------ */ 17433 .balign 64 17434.L_ALT_OP_UNUSED_36FF: /* 0x136 */ 17435/* File: armv5te/alt_stub.S */ 17436/* 17437 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17438 * any interesting requests and then jump to the real instruction 17439 * handler. Note that the call to dvmCheckInst is done as a tail call. 17440 */ 17441 adrl lr, dvmAsmInstructionStart + (310 * 64) 17442 mov r0, rPC @ arg0 17443 mov r1, rSELF @ arg1 17444 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17445 17446/* ------------------------------ */ 17447 .balign 64 17448.L_ALT_OP_UNUSED_37FF: /* 0x137 */ 17449/* File: armv5te/alt_stub.S */ 17450/* 17451 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17452 * any interesting requests and then jump to the real instruction 17453 * handler. Note that the call to dvmCheckInst is done as a tail call. 17454 */ 17455 adrl lr, dvmAsmInstructionStart + (311 * 64) 17456 mov r0, rPC @ arg0 17457 mov r1, rSELF @ arg1 17458 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17459 17460/* ------------------------------ */ 17461 .balign 64 17462.L_ALT_OP_UNUSED_38FF: /* 0x138 */ 17463/* File: armv5te/alt_stub.S */ 17464/* 17465 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17466 * any interesting requests and then jump to the real instruction 17467 * handler. Note that the call to dvmCheckInst is done as a tail call. 17468 */ 17469 adrl lr, dvmAsmInstructionStart + (312 * 64) 17470 mov r0, rPC @ arg0 17471 mov r1, rSELF @ arg1 17472 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17473 17474/* ------------------------------ */ 17475 .balign 64 17476.L_ALT_OP_UNUSED_39FF: /* 0x139 */ 17477/* File: armv5te/alt_stub.S */ 17478/* 17479 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17480 * any interesting requests and then jump to the real instruction 17481 * handler. Note that the call to dvmCheckInst is done as a tail call. 17482 */ 17483 adrl lr, dvmAsmInstructionStart + (313 * 64) 17484 mov r0, rPC @ arg0 17485 mov r1, rSELF @ arg1 17486 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17487 17488/* ------------------------------ */ 17489 .balign 64 17490.L_ALT_OP_UNUSED_3AFF: /* 0x13a */ 17491/* File: armv5te/alt_stub.S */ 17492/* 17493 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17494 * any interesting requests and then jump to the real instruction 17495 * handler. Note that the call to dvmCheckInst is done as a tail call. 17496 */ 17497 adrl lr, dvmAsmInstructionStart + (314 * 64) 17498 mov r0, rPC @ arg0 17499 mov r1, rSELF @ arg1 17500 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17501 17502/* ------------------------------ */ 17503 .balign 64 17504.L_ALT_OP_UNUSED_3BFF: /* 0x13b */ 17505/* File: armv5te/alt_stub.S */ 17506/* 17507 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17508 * any interesting requests and then jump to the real instruction 17509 * handler. Note that the call to dvmCheckInst is done as a tail call. 17510 */ 17511 adrl lr, dvmAsmInstructionStart + (315 * 64) 17512 mov r0, rPC @ arg0 17513 mov r1, rSELF @ arg1 17514 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17515 17516/* ------------------------------ */ 17517 .balign 64 17518.L_ALT_OP_UNUSED_3CFF: /* 0x13c */ 17519/* File: armv5te/alt_stub.S */ 17520/* 17521 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17522 * any interesting requests and then jump to the real instruction 17523 * handler. Note that the call to dvmCheckInst is done as a tail call. 17524 */ 17525 adrl lr, dvmAsmInstructionStart + (316 * 64) 17526 mov r0, rPC @ arg0 17527 mov r1, rSELF @ arg1 17528 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17529 17530/* ------------------------------ */ 17531 .balign 64 17532.L_ALT_OP_UNUSED_3DFF: /* 0x13d */ 17533/* File: armv5te/alt_stub.S */ 17534/* 17535 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17536 * any interesting requests and then jump to the real instruction 17537 * handler. Note that the call to dvmCheckInst is done as a tail call. 17538 */ 17539 adrl lr, dvmAsmInstructionStart + (317 * 64) 17540 mov r0, rPC @ arg0 17541 mov r1, rSELF @ arg1 17542 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17543 17544/* ------------------------------ */ 17545 .balign 64 17546.L_ALT_OP_UNUSED_3EFF: /* 0x13e */ 17547/* File: armv5te/alt_stub.S */ 17548/* 17549 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17550 * any interesting requests and then jump to the real instruction 17551 * handler. Note that the call to dvmCheckInst is done as a tail call. 17552 */ 17553 adrl lr, dvmAsmInstructionStart + (318 * 64) 17554 mov r0, rPC @ arg0 17555 mov r1, rSELF @ arg1 17556 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17557 17558/* ------------------------------ */ 17559 .balign 64 17560.L_ALT_OP_UNUSED_3FFF: /* 0x13f */ 17561/* File: armv5te/alt_stub.S */ 17562/* 17563 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17564 * any interesting requests and then jump to the real instruction 17565 * handler. Note that the call to dvmCheckInst is done as a tail call. 17566 */ 17567 adrl lr, dvmAsmInstructionStart + (319 * 64) 17568 mov r0, rPC @ arg0 17569 mov r1, rSELF @ arg1 17570 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17571 17572/* ------------------------------ */ 17573 .balign 64 17574.L_ALT_OP_UNUSED_40FF: /* 0x140 */ 17575/* File: armv5te/alt_stub.S */ 17576/* 17577 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17578 * any interesting requests and then jump to the real instruction 17579 * handler. Note that the call to dvmCheckInst is done as a tail call. 17580 */ 17581 adrl lr, dvmAsmInstructionStart + (320 * 64) 17582 mov r0, rPC @ arg0 17583 mov r1, rSELF @ arg1 17584 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17585 17586/* ------------------------------ */ 17587 .balign 64 17588.L_ALT_OP_UNUSED_41FF: /* 0x141 */ 17589/* File: armv5te/alt_stub.S */ 17590/* 17591 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17592 * any interesting requests and then jump to the real instruction 17593 * handler. Note that the call to dvmCheckInst is done as a tail call. 17594 */ 17595 adrl lr, dvmAsmInstructionStart + (321 * 64) 17596 mov r0, rPC @ arg0 17597 mov r1, rSELF @ arg1 17598 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17599 17600/* ------------------------------ */ 17601 .balign 64 17602.L_ALT_OP_UNUSED_42FF: /* 0x142 */ 17603/* File: armv5te/alt_stub.S */ 17604/* 17605 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17606 * any interesting requests and then jump to the real instruction 17607 * handler. Note that the call to dvmCheckInst is done as a tail call. 17608 */ 17609 adrl lr, dvmAsmInstructionStart + (322 * 64) 17610 mov r0, rPC @ arg0 17611 mov r1, rSELF @ arg1 17612 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17613 17614/* ------------------------------ */ 17615 .balign 64 17616.L_ALT_OP_UNUSED_43FF: /* 0x143 */ 17617/* File: armv5te/alt_stub.S */ 17618/* 17619 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17620 * any interesting requests and then jump to the real instruction 17621 * handler. Note that the call to dvmCheckInst is done as a tail call. 17622 */ 17623 adrl lr, dvmAsmInstructionStart + (323 * 64) 17624 mov r0, rPC @ arg0 17625 mov r1, rSELF @ arg1 17626 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17627 17628/* ------------------------------ */ 17629 .balign 64 17630.L_ALT_OP_UNUSED_44FF: /* 0x144 */ 17631/* File: armv5te/alt_stub.S */ 17632/* 17633 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17634 * any interesting requests and then jump to the real instruction 17635 * handler. Note that the call to dvmCheckInst is done as a tail call. 17636 */ 17637 adrl lr, dvmAsmInstructionStart + (324 * 64) 17638 mov r0, rPC @ arg0 17639 mov r1, rSELF @ arg1 17640 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17641 17642/* ------------------------------ */ 17643 .balign 64 17644.L_ALT_OP_UNUSED_45FF: /* 0x145 */ 17645/* File: armv5te/alt_stub.S */ 17646/* 17647 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17648 * any interesting requests and then jump to the real instruction 17649 * handler. Note that the call to dvmCheckInst is done as a tail call. 17650 */ 17651 adrl lr, dvmAsmInstructionStart + (325 * 64) 17652 mov r0, rPC @ arg0 17653 mov r1, rSELF @ arg1 17654 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17655 17656/* ------------------------------ */ 17657 .balign 64 17658.L_ALT_OP_UNUSED_46FF: /* 0x146 */ 17659/* File: armv5te/alt_stub.S */ 17660/* 17661 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17662 * any interesting requests and then jump to the real instruction 17663 * handler. Note that the call to dvmCheckInst is done as a tail call. 17664 */ 17665 adrl lr, dvmAsmInstructionStart + (326 * 64) 17666 mov r0, rPC @ arg0 17667 mov r1, rSELF @ arg1 17668 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17669 17670/* ------------------------------ */ 17671 .balign 64 17672.L_ALT_OP_UNUSED_47FF: /* 0x147 */ 17673/* File: armv5te/alt_stub.S */ 17674/* 17675 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17676 * any interesting requests and then jump to the real instruction 17677 * handler. Note that the call to dvmCheckInst is done as a tail call. 17678 */ 17679 adrl lr, dvmAsmInstructionStart + (327 * 64) 17680 mov r0, rPC @ arg0 17681 mov r1, rSELF @ arg1 17682 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17683 17684/* ------------------------------ */ 17685 .balign 64 17686.L_ALT_OP_UNUSED_48FF: /* 0x148 */ 17687/* File: armv5te/alt_stub.S */ 17688/* 17689 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17690 * any interesting requests and then jump to the real instruction 17691 * handler. Note that the call to dvmCheckInst is done as a tail call. 17692 */ 17693 adrl lr, dvmAsmInstructionStart + (328 * 64) 17694 mov r0, rPC @ arg0 17695 mov r1, rSELF @ arg1 17696 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17697 17698/* ------------------------------ */ 17699 .balign 64 17700.L_ALT_OP_UNUSED_49FF: /* 0x149 */ 17701/* File: armv5te/alt_stub.S */ 17702/* 17703 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17704 * any interesting requests and then jump to the real instruction 17705 * handler. Note that the call to dvmCheckInst is done as a tail call. 17706 */ 17707 adrl lr, dvmAsmInstructionStart + (329 * 64) 17708 mov r0, rPC @ arg0 17709 mov r1, rSELF @ arg1 17710 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17711 17712/* ------------------------------ */ 17713 .balign 64 17714.L_ALT_OP_UNUSED_4AFF: /* 0x14a */ 17715/* File: armv5te/alt_stub.S */ 17716/* 17717 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17718 * any interesting requests and then jump to the real instruction 17719 * handler. Note that the call to dvmCheckInst is done as a tail call. 17720 */ 17721 adrl lr, dvmAsmInstructionStart + (330 * 64) 17722 mov r0, rPC @ arg0 17723 mov r1, rSELF @ arg1 17724 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17725 17726/* ------------------------------ */ 17727 .balign 64 17728.L_ALT_OP_UNUSED_4BFF: /* 0x14b */ 17729/* File: armv5te/alt_stub.S */ 17730/* 17731 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17732 * any interesting requests and then jump to the real instruction 17733 * handler. Note that the call to dvmCheckInst is done as a tail call. 17734 */ 17735 adrl lr, dvmAsmInstructionStart + (331 * 64) 17736 mov r0, rPC @ arg0 17737 mov r1, rSELF @ arg1 17738 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17739 17740/* ------------------------------ */ 17741 .balign 64 17742.L_ALT_OP_UNUSED_4CFF: /* 0x14c */ 17743/* File: armv5te/alt_stub.S */ 17744/* 17745 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17746 * any interesting requests and then jump to the real instruction 17747 * handler. Note that the call to dvmCheckInst is done as a tail call. 17748 */ 17749 adrl lr, dvmAsmInstructionStart + (332 * 64) 17750 mov r0, rPC @ arg0 17751 mov r1, rSELF @ arg1 17752 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17753 17754/* ------------------------------ */ 17755 .balign 64 17756.L_ALT_OP_UNUSED_4DFF: /* 0x14d */ 17757/* File: armv5te/alt_stub.S */ 17758/* 17759 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17760 * any interesting requests and then jump to the real instruction 17761 * handler. Note that the call to dvmCheckInst is done as a tail call. 17762 */ 17763 adrl lr, dvmAsmInstructionStart + (333 * 64) 17764 mov r0, rPC @ arg0 17765 mov r1, rSELF @ arg1 17766 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17767 17768/* ------------------------------ */ 17769 .balign 64 17770.L_ALT_OP_UNUSED_4EFF: /* 0x14e */ 17771/* File: armv5te/alt_stub.S */ 17772/* 17773 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17774 * any interesting requests and then jump to the real instruction 17775 * handler. Note that the call to dvmCheckInst is done as a tail call. 17776 */ 17777 adrl lr, dvmAsmInstructionStart + (334 * 64) 17778 mov r0, rPC @ arg0 17779 mov r1, rSELF @ arg1 17780 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17781 17782/* ------------------------------ */ 17783 .balign 64 17784.L_ALT_OP_UNUSED_4FFF: /* 0x14f */ 17785/* File: armv5te/alt_stub.S */ 17786/* 17787 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17788 * any interesting requests and then jump to the real instruction 17789 * handler. Note that the call to dvmCheckInst is done as a tail call. 17790 */ 17791 adrl lr, dvmAsmInstructionStart + (335 * 64) 17792 mov r0, rPC @ arg0 17793 mov r1, rSELF @ arg1 17794 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17795 17796/* ------------------------------ */ 17797 .balign 64 17798.L_ALT_OP_UNUSED_50FF: /* 0x150 */ 17799/* File: armv5te/alt_stub.S */ 17800/* 17801 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17802 * any interesting requests and then jump to the real instruction 17803 * handler. Note that the call to dvmCheckInst is done as a tail call. 17804 */ 17805 adrl lr, dvmAsmInstructionStart + (336 * 64) 17806 mov r0, rPC @ arg0 17807 mov r1, rSELF @ arg1 17808 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17809 17810/* ------------------------------ */ 17811 .balign 64 17812.L_ALT_OP_UNUSED_51FF: /* 0x151 */ 17813/* File: armv5te/alt_stub.S */ 17814/* 17815 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17816 * any interesting requests and then jump to the real instruction 17817 * handler. Note that the call to dvmCheckInst is done as a tail call. 17818 */ 17819 adrl lr, dvmAsmInstructionStart + (337 * 64) 17820 mov r0, rPC @ arg0 17821 mov r1, rSELF @ arg1 17822 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17823 17824/* ------------------------------ */ 17825 .balign 64 17826.L_ALT_OP_UNUSED_52FF: /* 0x152 */ 17827/* File: armv5te/alt_stub.S */ 17828/* 17829 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17830 * any interesting requests and then jump to the real instruction 17831 * handler. Note that the call to dvmCheckInst is done as a tail call. 17832 */ 17833 adrl lr, dvmAsmInstructionStart + (338 * 64) 17834 mov r0, rPC @ arg0 17835 mov r1, rSELF @ arg1 17836 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17837 17838/* ------------------------------ */ 17839 .balign 64 17840.L_ALT_OP_UNUSED_53FF: /* 0x153 */ 17841/* File: armv5te/alt_stub.S */ 17842/* 17843 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17844 * any interesting requests and then jump to the real instruction 17845 * handler. Note that the call to dvmCheckInst is done as a tail call. 17846 */ 17847 adrl lr, dvmAsmInstructionStart + (339 * 64) 17848 mov r0, rPC @ arg0 17849 mov r1, rSELF @ arg1 17850 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17851 17852/* ------------------------------ */ 17853 .balign 64 17854.L_ALT_OP_UNUSED_54FF: /* 0x154 */ 17855/* File: armv5te/alt_stub.S */ 17856/* 17857 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17858 * any interesting requests and then jump to the real instruction 17859 * handler. Note that the call to dvmCheckInst is done as a tail call. 17860 */ 17861 adrl lr, dvmAsmInstructionStart + (340 * 64) 17862 mov r0, rPC @ arg0 17863 mov r1, rSELF @ arg1 17864 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17865 17866/* ------------------------------ */ 17867 .balign 64 17868.L_ALT_OP_UNUSED_55FF: /* 0x155 */ 17869/* File: armv5te/alt_stub.S */ 17870/* 17871 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17872 * any interesting requests and then jump to the real instruction 17873 * handler. Note that the call to dvmCheckInst is done as a tail call. 17874 */ 17875 adrl lr, dvmAsmInstructionStart + (341 * 64) 17876 mov r0, rPC @ arg0 17877 mov r1, rSELF @ arg1 17878 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17879 17880/* ------------------------------ */ 17881 .balign 64 17882.L_ALT_OP_UNUSED_56FF: /* 0x156 */ 17883/* File: armv5te/alt_stub.S */ 17884/* 17885 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17886 * any interesting requests and then jump to the real instruction 17887 * handler. Note that the call to dvmCheckInst is done as a tail call. 17888 */ 17889 adrl lr, dvmAsmInstructionStart + (342 * 64) 17890 mov r0, rPC @ arg0 17891 mov r1, rSELF @ arg1 17892 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17893 17894/* ------------------------------ */ 17895 .balign 64 17896.L_ALT_OP_UNUSED_57FF: /* 0x157 */ 17897/* File: armv5te/alt_stub.S */ 17898/* 17899 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17900 * any interesting requests and then jump to the real instruction 17901 * handler. Note that the call to dvmCheckInst is done as a tail call. 17902 */ 17903 adrl lr, dvmAsmInstructionStart + (343 * 64) 17904 mov r0, rPC @ arg0 17905 mov r1, rSELF @ arg1 17906 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17907 17908/* ------------------------------ */ 17909 .balign 64 17910.L_ALT_OP_UNUSED_58FF: /* 0x158 */ 17911/* File: armv5te/alt_stub.S */ 17912/* 17913 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17914 * any interesting requests and then jump to the real instruction 17915 * handler. Note that the call to dvmCheckInst is done as a tail call. 17916 */ 17917 adrl lr, dvmAsmInstructionStart + (344 * 64) 17918 mov r0, rPC @ arg0 17919 mov r1, rSELF @ arg1 17920 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17921 17922/* ------------------------------ */ 17923 .balign 64 17924.L_ALT_OP_UNUSED_59FF: /* 0x159 */ 17925/* File: armv5te/alt_stub.S */ 17926/* 17927 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17928 * any interesting requests and then jump to the real instruction 17929 * handler. Note that the call to dvmCheckInst is done as a tail call. 17930 */ 17931 adrl lr, dvmAsmInstructionStart + (345 * 64) 17932 mov r0, rPC @ arg0 17933 mov r1, rSELF @ arg1 17934 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17935 17936/* ------------------------------ */ 17937 .balign 64 17938.L_ALT_OP_UNUSED_5AFF: /* 0x15a */ 17939/* File: armv5te/alt_stub.S */ 17940/* 17941 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17942 * any interesting requests and then jump to the real instruction 17943 * handler. Note that the call to dvmCheckInst is done as a tail call. 17944 */ 17945 adrl lr, dvmAsmInstructionStart + (346 * 64) 17946 mov r0, rPC @ arg0 17947 mov r1, rSELF @ arg1 17948 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17949 17950/* ------------------------------ */ 17951 .balign 64 17952.L_ALT_OP_UNUSED_5BFF: /* 0x15b */ 17953/* File: armv5te/alt_stub.S */ 17954/* 17955 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17956 * any interesting requests and then jump to the real instruction 17957 * handler. Note that the call to dvmCheckInst is done as a tail call. 17958 */ 17959 adrl lr, dvmAsmInstructionStart + (347 * 64) 17960 mov r0, rPC @ arg0 17961 mov r1, rSELF @ arg1 17962 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17963 17964/* ------------------------------ */ 17965 .balign 64 17966.L_ALT_OP_UNUSED_5CFF: /* 0x15c */ 17967/* File: armv5te/alt_stub.S */ 17968/* 17969 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17970 * any interesting requests and then jump to the real instruction 17971 * handler. Note that the call to dvmCheckInst is done as a tail call. 17972 */ 17973 adrl lr, dvmAsmInstructionStart + (348 * 64) 17974 mov r0, rPC @ arg0 17975 mov r1, rSELF @ arg1 17976 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17977 17978/* ------------------------------ */ 17979 .balign 64 17980.L_ALT_OP_UNUSED_5DFF: /* 0x15d */ 17981/* File: armv5te/alt_stub.S */ 17982/* 17983 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17984 * any interesting requests and then jump to the real instruction 17985 * handler. Note that the call to dvmCheckInst is done as a tail call. 17986 */ 17987 adrl lr, dvmAsmInstructionStart + (349 * 64) 17988 mov r0, rPC @ arg0 17989 mov r1, rSELF @ arg1 17990 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17991 17992/* ------------------------------ */ 17993 .balign 64 17994.L_ALT_OP_UNUSED_5EFF: /* 0x15e */ 17995/* File: armv5te/alt_stub.S */ 17996/* 17997 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17998 * any interesting requests and then jump to the real instruction 17999 * handler. Note that the call to dvmCheckInst is done as a tail call. 18000 */ 18001 adrl lr, dvmAsmInstructionStart + (350 * 64) 18002 mov r0, rPC @ arg0 18003 mov r1, rSELF @ arg1 18004 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18005 18006/* ------------------------------ */ 18007 .balign 64 18008.L_ALT_OP_UNUSED_5FFF: /* 0x15f */ 18009/* File: armv5te/alt_stub.S */ 18010/* 18011 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18012 * any interesting requests and then jump to the real instruction 18013 * handler. Note that the call to dvmCheckInst is done as a tail call. 18014 */ 18015 adrl lr, dvmAsmInstructionStart + (351 * 64) 18016 mov r0, rPC @ arg0 18017 mov r1, rSELF @ arg1 18018 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18019 18020/* ------------------------------ */ 18021 .balign 64 18022.L_ALT_OP_UNUSED_60FF: /* 0x160 */ 18023/* File: armv5te/alt_stub.S */ 18024/* 18025 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18026 * any interesting requests and then jump to the real instruction 18027 * handler. Note that the call to dvmCheckInst is done as a tail call. 18028 */ 18029 adrl lr, dvmAsmInstructionStart + (352 * 64) 18030 mov r0, rPC @ arg0 18031 mov r1, rSELF @ arg1 18032 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18033 18034/* ------------------------------ */ 18035 .balign 64 18036.L_ALT_OP_UNUSED_61FF: /* 0x161 */ 18037/* File: armv5te/alt_stub.S */ 18038/* 18039 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18040 * any interesting requests and then jump to the real instruction 18041 * handler. Note that the call to dvmCheckInst is done as a tail call. 18042 */ 18043 adrl lr, dvmAsmInstructionStart + (353 * 64) 18044 mov r0, rPC @ arg0 18045 mov r1, rSELF @ arg1 18046 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18047 18048/* ------------------------------ */ 18049 .balign 64 18050.L_ALT_OP_UNUSED_62FF: /* 0x162 */ 18051/* File: armv5te/alt_stub.S */ 18052/* 18053 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18054 * any interesting requests and then jump to the real instruction 18055 * handler. Note that the call to dvmCheckInst is done as a tail call. 18056 */ 18057 adrl lr, dvmAsmInstructionStart + (354 * 64) 18058 mov r0, rPC @ arg0 18059 mov r1, rSELF @ arg1 18060 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18061 18062/* ------------------------------ */ 18063 .balign 64 18064.L_ALT_OP_UNUSED_63FF: /* 0x163 */ 18065/* File: armv5te/alt_stub.S */ 18066/* 18067 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18068 * any interesting requests and then jump to the real instruction 18069 * handler. Note that the call to dvmCheckInst is done as a tail call. 18070 */ 18071 adrl lr, dvmAsmInstructionStart + (355 * 64) 18072 mov r0, rPC @ arg0 18073 mov r1, rSELF @ arg1 18074 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18075 18076/* ------------------------------ */ 18077 .balign 64 18078.L_ALT_OP_UNUSED_64FF: /* 0x164 */ 18079/* File: armv5te/alt_stub.S */ 18080/* 18081 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18082 * any interesting requests and then jump to the real instruction 18083 * handler. Note that the call to dvmCheckInst is done as a tail call. 18084 */ 18085 adrl lr, dvmAsmInstructionStart + (356 * 64) 18086 mov r0, rPC @ arg0 18087 mov r1, rSELF @ arg1 18088 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18089 18090/* ------------------------------ */ 18091 .balign 64 18092.L_ALT_OP_UNUSED_65FF: /* 0x165 */ 18093/* File: armv5te/alt_stub.S */ 18094/* 18095 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18096 * any interesting requests and then jump to the real instruction 18097 * handler. Note that the call to dvmCheckInst is done as a tail call. 18098 */ 18099 adrl lr, dvmAsmInstructionStart + (357 * 64) 18100 mov r0, rPC @ arg0 18101 mov r1, rSELF @ arg1 18102 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18103 18104/* ------------------------------ */ 18105 .balign 64 18106.L_ALT_OP_UNUSED_66FF: /* 0x166 */ 18107/* File: armv5te/alt_stub.S */ 18108/* 18109 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18110 * any interesting requests and then jump to the real instruction 18111 * handler. Note that the call to dvmCheckInst is done as a tail call. 18112 */ 18113 adrl lr, dvmAsmInstructionStart + (358 * 64) 18114 mov r0, rPC @ arg0 18115 mov r1, rSELF @ arg1 18116 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18117 18118/* ------------------------------ */ 18119 .balign 64 18120.L_ALT_OP_UNUSED_67FF: /* 0x167 */ 18121/* File: armv5te/alt_stub.S */ 18122/* 18123 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18124 * any interesting requests and then jump to the real instruction 18125 * handler. Note that the call to dvmCheckInst is done as a tail call. 18126 */ 18127 adrl lr, dvmAsmInstructionStart + (359 * 64) 18128 mov r0, rPC @ arg0 18129 mov r1, rSELF @ arg1 18130 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18131 18132/* ------------------------------ */ 18133 .balign 64 18134.L_ALT_OP_UNUSED_68FF: /* 0x168 */ 18135/* File: armv5te/alt_stub.S */ 18136/* 18137 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18138 * any interesting requests and then jump to the real instruction 18139 * handler. Note that the call to dvmCheckInst is done as a tail call. 18140 */ 18141 adrl lr, dvmAsmInstructionStart + (360 * 64) 18142 mov r0, rPC @ arg0 18143 mov r1, rSELF @ arg1 18144 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18145 18146/* ------------------------------ */ 18147 .balign 64 18148.L_ALT_OP_UNUSED_69FF: /* 0x169 */ 18149/* File: armv5te/alt_stub.S */ 18150/* 18151 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18152 * any interesting requests and then jump to the real instruction 18153 * handler. Note that the call to dvmCheckInst is done as a tail call. 18154 */ 18155 adrl lr, dvmAsmInstructionStart + (361 * 64) 18156 mov r0, rPC @ arg0 18157 mov r1, rSELF @ arg1 18158 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18159 18160/* ------------------------------ */ 18161 .balign 64 18162.L_ALT_OP_UNUSED_6AFF: /* 0x16a */ 18163/* File: armv5te/alt_stub.S */ 18164/* 18165 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18166 * any interesting requests and then jump to the real instruction 18167 * handler. Note that the call to dvmCheckInst is done as a tail call. 18168 */ 18169 adrl lr, dvmAsmInstructionStart + (362 * 64) 18170 mov r0, rPC @ arg0 18171 mov r1, rSELF @ arg1 18172 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18173 18174/* ------------------------------ */ 18175 .balign 64 18176.L_ALT_OP_UNUSED_6BFF: /* 0x16b */ 18177/* File: armv5te/alt_stub.S */ 18178/* 18179 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18180 * any interesting requests and then jump to the real instruction 18181 * handler. Note that the call to dvmCheckInst is done as a tail call. 18182 */ 18183 adrl lr, dvmAsmInstructionStart + (363 * 64) 18184 mov r0, rPC @ arg0 18185 mov r1, rSELF @ arg1 18186 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18187 18188/* ------------------------------ */ 18189 .balign 64 18190.L_ALT_OP_UNUSED_6CFF: /* 0x16c */ 18191/* File: armv5te/alt_stub.S */ 18192/* 18193 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18194 * any interesting requests and then jump to the real instruction 18195 * handler. Note that the call to dvmCheckInst is done as a tail call. 18196 */ 18197 adrl lr, dvmAsmInstructionStart + (364 * 64) 18198 mov r0, rPC @ arg0 18199 mov r1, rSELF @ arg1 18200 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18201 18202/* ------------------------------ */ 18203 .balign 64 18204.L_ALT_OP_UNUSED_6DFF: /* 0x16d */ 18205/* File: armv5te/alt_stub.S */ 18206/* 18207 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18208 * any interesting requests and then jump to the real instruction 18209 * handler. Note that the call to dvmCheckInst is done as a tail call. 18210 */ 18211 adrl lr, dvmAsmInstructionStart + (365 * 64) 18212 mov r0, rPC @ arg0 18213 mov r1, rSELF @ arg1 18214 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18215 18216/* ------------------------------ */ 18217 .balign 64 18218.L_ALT_OP_UNUSED_6EFF: /* 0x16e */ 18219/* File: armv5te/alt_stub.S */ 18220/* 18221 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18222 * any interesting requests and then jump to the real instruction 18223 * handler. Note that the call to dvmCheckInst is done as a tail call. 18224 */ 18225 adrl lr, dvmAsmInstructionStart + (366 * 64) 18226 mov r0, rPC @ arg0 18227 mov r1, rSELF @ arg1 18228 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18229 18230/* ------------------------------ */ 18231 .balign 64 18232.L_ALT_OP_UNUSED_6FFF: /* 0x16f */ 18233/* File: armv5te/alt_stub.S */ 18234/* 18235 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18236 * any interesting requests and then jump to the real instruction 18237 * handler. Note that the call to dvmCheckInst is done as a tail call. 18238 */ 18239 adrl lr, dvmAsmInstructionStart + (367 * 64) 18240 mov r0, rPC @ arg0 18241 mov r1, rSELF @ arg1 18242 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18243 18244/* ------------------------------ */ 18245 .balign 64 18246.L_ALT_OP_UNUSED_70FF: /* 0x170 */ 18247/* File: armv5te/alt_stub.S */ 18248/* 18249 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18250 * any interesting requests and then jump to the real instruction 18251 * handler. Note that the call to dvmCheckInst is done as a tail call. 18252 */ 18253 adrl lr, dvmAsmInstructionStart + (368 * 64) 18254 mov r0, rPC @ arg0 18255 mov r1, rSELF @ arg1 18256 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18257 18258/* ------------------------------ */ 18259 .balign 64 18260.L_ALT_OP_UNUSED_71FF: /* 0x171 */ 18261/* File: armv5te/alt_stub.S */ 18262/* 18263 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18264 * any interesting requests and then jump to the real instruction 18265 * handler. Note that the call to dvmCheckInst is done as a tail call. 18266 */ 18267 adrl lr, dvmAsmInstructionStart + (369 * 64) 18268 mov r0, rPC @ arg0 18269 mov r1, rSELF @ arg1 18270 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18271 18272/* ------------------------------ */ 18273 .balign 64 18274.L_ALT_OP_UNUSED_72FF: /* 0x172 */ 18275/* File: armv5te/alt_stub.S */ 18276/* 18277 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18278 * any interesting requests and then jump to the real instruction 18279 * handler. Note that the call to dvmCheckInst is done as a tail call. 18280 */ 18281 adrl lr, dvmAsmInstructionStart + (370 * 64) 18282 mov r0, rPC @ arg0 18283 mov r1, rSELF @ arg1 18284 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18285 18286/* ------------------------------ */ 18287 .balign 64 18288.L_ALT_OP_UNUSED_73FF: /* 0x173 */ 18289/* File: armv5te/alt_stub.S */ 18290/* 18291 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18292 * any interesting requests and then jump to the real instruction 18293 * handler. Note that the call to dvmCheckInst is done as a tail call. 18294 */ 18295 adrl lr, dvmAsmInstructionStart + (371 * 64) 18296 mov r0, rPC @ arg0 18297 mov r1, rSELF @ arg1 18298 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18299 18300/* ------------------------------ */ 18301 .balign 64 18302.L_ALT_OP_UNUSED_74FF: /* 0x174 */ 18303/* File: armv5te/alt_stub.S */ 18304/* 18305 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18306 * any interesting requests and then jump to the real instruction 18307 * handler. Note that the call to dvmCheckInst is done as a tail call. 18308 */ 18309 adrl lr, dvmAsmInstructionStart + (372 * 64) 18310 mov r0, rPC @ arg0 18311 mov r1, rSELF @ arg1 18312 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18313 18314/* ------------------------------ */ 18315 .balign 64 18316.L_ALT_OP_UNUSED_75FF: /* 0x175 */ 18317/* File: armv5te/alt_stub.S */ 18318/* 18319 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18320 * any interesting requests and then jump to the real instruction 18321 * handler. Note that the call to dvmCheckInst is done as a tail call. 18322 */ 18323 adrl lr, dvmAsmInstructionStart + (373 * 64) 18324 mov r0, rPC @ arg0 18325 mov r1, rSELF @ arg1 18326 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18327 18328/* ------------------------------ */ 18329 .balign 64 18330.L_ALT_OP_UNUSED_76FF: /* 0x176 */ 18331/* File: armv5te/alt_stub.S */ 18332/* 18333 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18334 * any interesting requests and then jump to the real instruction 18335 * handler. Note that the call to dvmCheckInst is done as a tail call. 18336 */ 18337 adrl lr, dvmAsmInstructionStart + (374 * 64) 18338 mov r0, rPC @ arg0 18339 mov r1, rSELF @ arg1 18340 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18341 18342/* ------------------------------ */ 18343 .balign 64 18344.L_ALT_OP_UNUSED_77FF: /* 0x177 */ 18345/* File: armv5te/alt_stub.S */ 18346/* 18347 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18348 * any interesting requests and then jump to the real instruction 18349 * handler. Note that the call to dvmCheckInst is done as a tail call. 18350 */ 18351 adrl lr, dvmAsmInstructionStart + (375 * 64) 18352 mov r0, rPC @ arg0 18353 mov r1, rSELF @ arg1 18354 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18355 18356/* ------------------------------ */ 18357 .balign 64 18358.L_ALT_OP_UNUSED_78FF: /* 0x178 */ 18359/* File: armv5te/alt_stub.S */ 18360/* 18361 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18362 * any interesting requests and then jump to the real instruction 18363 * handler. Note that the call to dvmCheckInst is done as a tail call. 18364 */ 18365 adrl lr, dvmAsmInstructionStart + (376 * 64) 18366 mov r0, rPC @ arg0 18367 mov r1, rSELF @ arg1 18368 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18369 18370/* ------------------------------ */ 18371 .balign 64 18372.L_ALT_OP_UNUSED_79FF: /* 0x179 */ 18373/* File: armv5te/alt_stub.S */ 18374/* 18375 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18376 * any interesting requests and then jump to the real instruction 18377 * handler. Note that the call to dvmCheckInst is done as a tail call. 18378 */ 18379 adrl lr, dvmAsmInstructionStart + (377 * 64) 18380 mov r0, rPC @ arg0 18381 mov r1, rSELF @ arg1 18382 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18383 18384/* ------------------------------ */ 18385 .balign 64 18386.L_ALT_OP_UNUSED_7AFF: /* 0x17a */ 18387/* File: armv5te/alt_stub.S */ 18388/* 18389 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18390 * any interesting requests and then jump to the real instruction 18391 * handler. Note that the call to dvmCheckInst is done as a tail call. 18392 */ 18393 adrl lr, dvmAsmInstructionStart + (378 * 64) 18394 mov r0, rPC @ arg0 18395 mov r1, rSELF @ arg1 18396 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18397 18398/* ------------------------------ */ 18399 .balign 64 18400.L_ALT_OP_UNUSED_7BFF: /* 0x17b */ 18401/* File: armv5te/alt_stub.S */ 18402/* 18403 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18404 * any interesting requests and then jump to the real instruction 18405 * handler. Note that the call to dvmCheckInst is done as a tail call. 18406 */ 18407 adrl lr, dvmAsmInstructionStart + (379 * 64) 18408 mov r0, rPC @ arg0 18409 mov r1, rSELF @ arg1 18410 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18411 18412/* ------------------------------ */ 18413 .balign 64 18414.L_ALT_OP_UNUSED_7CFF: /* 0x17c */ 18415/* File: armv5te/alt_stub.S */ 18416/* 18417 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18418 * any interesting requests and then jump to the real instruction 18419 * handler. Note that the call to dvmCheckInst is done as a tail call. 18420 */ 18421 adrl lr, dvmAsmInstructionStart + (380 * 64) 18422 mov r0, rPC @ arg0 18423 mov r1, rSELF @ arg1 18424 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18425 18426/* ------------------------------ */ 18427 .balign 64 18428.L_ALT_OP_UNUSED_7DFF: /* 0x17d */ 18429/* File: armv5te/alt_stub.S */ 18430/* 18431 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18432 * any interesting requests and then jump to the real instruction 18433 * handler. Note that the call to dvmCheckInst is done as a tail call. 18434 */ 18435 adrl lr, dvmAsmInstructionStart + (381 * 64) 18436 mov r0, rPC @ arg0 18437 mov r1, rSELF @ arg1 18438 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18439 18440/* ------------------------------ */ 18441 .balign 64 18442.L_ALT_OP_UNUSED_7EFF: /* 0x17e */ 18443/* File: armv5te/alt_stub.S */ 18444/* 18445 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18446 * any interesting requests and then jump to the real instruction 18447 * handler. Note that the call to dvmCheckInst is done as a tail call. 18448 */ 18449 adrl lr, dvmAsmInstructionStart + (382 * 64) 18450 mov r0, rPC @ arg0 18451 mov r1, rSELF @ arg1 18452 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18453 18454/* ------------------------------ */ 18455 .balign 64 18456.L_ALT_OP_UNUSED_7FFF: /* 0x17f */ 18457/* File: armv5te/alt_stub.S */ 18458/* 18459 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18460 * any interesting requests and then jump to the real instruction 18461 * handler. Note that the call to dvmCheckInst is done as a tail call. 18462 */ 18463 adrl lr, dvmAsmInstructionStart + (383 * 64) 18464 mov r0, rPC @ arg0 18465 mov r1, rSELF @ arg1 18466 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18467 18468/* ------------------------------ */ 18469 .balign 64 18470.L_ALT_OP_UNUSED_80FF: /* 0x180 */ 18471/* File: armv5te/alt_stub.S */ 18472/* 18473 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18474 * any interesting requests and then jump to the real instruction 18475 * handler. Note that the call to dvmCheckInst is done as a tail call. 18476 */ 18477 adrl lr, dvmAsmInstructionStart + (384 * 64) 18478 mov r0, rPC @ arg0 18479 mov r1, rSELF @ arg1 18480 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18481 18482/* ------------------------------ */ 18483 .balign 64 18484.L_ALT_OP_UNUSED_81FF: /* 0x181 */ 18485/* File: armv5te/alt_stub.S */ 18486/* 18487 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18488 * any interesting requests and then jump to the real instruction 18489 * handler. Note that the call to dvmCheckInst is done as a tail call. 18490 */ 18491 adrl lr, dvmAsmInstructionStart + (385 * 64) 18492 mov r0, rPC @ arg0 18493 mov r1, rSELF @ arg1 18494 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18495 18496/* ------------------------------ */ 18497 .balign 64 18498.L_ALT_OP_UNUSED_82FF: /* 0x182 */ 18499/* File: armv5te/alt_stub.S */ 18500/* 18501 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18502 * any interesting requests and then jump to the real instruction 18503 * handler. Note that the call to dvmCheckInst is done as a tail call. 18504 */ 18505 adrl lr, dvmAsmInstructionStart + (386 * 64) 18506 mov r0, rPC @ arg0 18507 mov r1, rSELF @ arg1 18508 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18509 18510/* ------------------------------ */ 18511 .balign 64 18512.L_ALT_OP_UNUSED_83FF: /* 0x183 */ 18513/* File: armv5te/alt_stub.S */ 18514/* 18515 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18516 * any interesting requests and then jump to the real instruction 18517 * handler. Note that the call to dvmCheckInst is done as a tail call. 18518 */ 18519 adrl lr, dvmAsmInstructionStart + (387 * 64) 18520 mov r0, rPC @ arg0 18521 mov r1, rSELF @ arg1 18522 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18523 18524/* ------------------------------ */ 18525 .balign 64 18526.L_ALT_OP_UNUSED_84FF: /* 0x184 */ 18527/* File: armv5te/alt_stub.S */ 18528/* 18529 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18530 * any interesting requests and then jump to the real instruction 18531 * handler. Note that the call to dvmCheckInst is done as a tail call. 18532 */ 18533 adrl lr, dvmAsmInstructionStart + (388 * 64) 18534 mov r0, rPC @ arg0 18535 mov r1, rSELF @ arg1 18536 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18537 18538/* ------------------------------ */ 18539 .balign 64 18540.L_ALT_OP_UNUSED_85FF: /* 0x185 */ 18541/* File: armv5te/alt_stub.S */ 18542/* 18543 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18544 * any interesting requests and then jump to the real instruction 18545 * handler. Note that the call to dvmCheckInst is done as a tail call. 18546 */ 18547 adrl lr, dvmAsmInstructionStart + (389 * 64) 18548 mov r0, rPC @ arg0 18549 mov r1, rSELF @ arg1 18550 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18551 18552/* ------------------------------ */ 18553 .balign 64 18554.L_ALT_OP_UNUSED_86FF: /* 0x186 */ 18555/* File: armv5te/alt_stub.S */ 18556/* 18557 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18558 * any interesting requests and then jump to the real instruction 18559 * handler. Note that the call to dvmCheckInst is done as a tail call. 18560 */ 18561 adrl lr, dvmAsmInstructionStart + (390 * 64) 18562 mov r0, rPC @ arg0 18563 mov r1, rSELF @ arg1 18564 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18565 18566/* ------------------------------ */ 18567 .balign 64 18568.L_ALT_OP_UNUSED_87FF: /* 0x187 */ 18569/* File: armv5te/alt_stub.S */ 18570/* 18571 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18572 * any interesting requests and then jump to the real instruction 18573 * handler. Note that the call to dvmCheckInst is done as a tail call. 18574 */ 18575 adrl lr, dvmAsmInstructionStart + (391 * 64) 18576 mov r0, rPC @ arg0 18577 mov r1, rSELF @ arg1 18578 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18579 18580/* ------------------------------ */ 18581 .balign 64 18582.L_ALT_OP_UNUSED_88FF: /* 0x188 */ 18583/* File: armv5te/alt_stub.S */ 18584/* 18585 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18586 * any interesting requests and then jump to the real instruction 18587 * handler. Note that the call to dvmCheckInst is done as a tail call. 18588 */ 18589 adrl lr, dvmAsmInstructionStart + (392 * 64) 18590 mov r0, rPC @ arg0 18591 mov r1, rSELF @ arg1 18592 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18593 18594/* ------------------------------ */ 18595 .balign 64 18596.L_ALT_OP_UNUSED_89FF: /* 0x189 */ 18597/* File: armv5te/alt_stub.S */ 18598/* 18599 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18600 * any interesting requests and then jump to the real instruction 18601 * handler. Note that the call to dvmCheckInst is done as a tail call. 18602 */ 18603 adrl lr, dvmAsmInstructionStart + (393 * 64) 18604 mov r0, rPC @ arg0 18605 mov r1, rSELF @ arg1 18606 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18607 18608/* ------------------------------ */ 18609 .balign 64 18610.L_ALT_OP_UNUSED_8AFF: /* 0x18a */ 18611/* File: armv5te/alt_stub.S */ 18612/* 18613 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18614 * any interesting requests and then jump to the real instruction 18615 * handler. Note that the call to dvmCheckInst is done as a tail call. 18616 */ 18617 adrl lr, dvmAsmInstructionStart + (394 * 64) 18618 mov r0, rPC @ arg0 18619 mov r1, rSELF @ arg1 18620 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18621 18622/* ------------------------------ */ 18623 .balign 64 18624.L_ALT_OP_UNUSED_8BFF: /* 0x18b */ 18625/* File: armv5te/alt_stub.S */ 18626/* 18627 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18628 * any interesting requests and then jump to the real instruction 18629 * handler. Note that the call to dvmCheckInst is done as a tail call. 18630 */ 18631 adrl lr, dvmAsmInstructionStart + (395 * 64) 18632 mov r0, rPC @ arg0 18633 mov r1, rSELF @ arg1 18634 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18635 18636/* ------------------------------ */ 18637 .balign 64 18638.L_ALT_OP_UNUSED_8CFF: /* 0x18c */ 18639/* File: armv5te/alt_stub.S */ 18640/* 18641 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18642 * any interesting requests and then jump to the real instruction 18643 * handler. Note that the call to dvmCheckInst is done as a tail call. 18644 */ 18645 adrl lr, dvmAsmInstructionStart + (396 * 64) 18646 mov r0, rPC @ arg0 18647 mov r1, rSELF @ arg1 18648 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18649 18650/* ------------------------------ */ 18651 .balign 64 18652.L_ALT_OP_UNUSED_8DFF: /* 0x18d */ 18653/* File: armv5te/alt_stub.S */ 18654/* 18655 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18656 * any interesting requests and then jump to the real instruction 18657 * handler. Note that the call to dvmCheckInst is done as a tail call. 18658 */ 18659 adrl lr, dvmAsmInstructionStart + (397 * 64) 18660 mov r0, rPC @ arg0 18661 mov r1, rSELF @ arg1 18662 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18663 18664/* ------------------------------ */ 18665 .balign 64 18666.L_ALT_OP_UNUSED_8EFF: /* 0x18e */ 18667/* File: armv5te/alt_stub.S */ 18668/* 18669 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18670 * any interesting requests and then jump to the real instruction 18671 * handler. Note that the call to dvmCheckInst is done as a tail call. 18672 */ 18673 adrl lr, dvmAsmInstructionStart + (398 * 64) 18674 mov r0, rPC @ arg0 18675 mov r1, rSELF @ arg1 18676 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18677 18678/* ------------------------------ */ 18679 .balign 64 18680.L_ALT_OP_UNUSED_8FFF: /* 0x18f */ 18681/* File: armv5te/alt_stub.S */ 18682/* 18683 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18684 * any interesting requests and then jump to the real instruction 18685 * handler. Note that the call to dvmCheckInst is done as a tail call. 18686 */ 18687 adrl lr, dvmAsmInstructionStart + (399 * 64) 18688 mov r0, rPC @ arg0 18689 mov r1, rSELF @ arg1 18690 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18691 18692/* ------------------------------ */ 18693 .balign 64 18694.L_ALT_OP_UNUSED_90FF: /* 0x190 */ 18695/* File: armv5te/alt_stub.S */ 18696/* 18697 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18698 * any interesting requests and then jump to the real instruction 18699 * handler. Note that the call to dvmCheckInst is done as a tail call. 18700 */ 18701 adrl lr, dvmAsmInstructionStart + (400 * 64) 18702 mov r0, rPC @ arg0 18703 mov r1, rSELF @ arg1 18704 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18705 18706/* ------------------------------ */ 18707 .balign 64 18708.L_ALT_OP_UNUSED_91FF: /* 0x191 */ 18709/* File: armv5te/alt_stub.S */ 18710/* 18711 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18712 * any interesting requests and then jump to the real instruction 18713 * handler. Note that the call to dvmCheckInst is done as a tail call. 18714 */ 18715 adrl lr, dvmAsmInstructionStart + (401 * 64) 18716 mov r0, rPC @ arg0 18717 mov r1, rSELF @ arg1 18718 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18719 18720/* ------------------------------ */ 18721 .balign 64 18722.L_ALT_OP_UNUSED_92FF: /* 0x192 */ 18723/* File: armv5te/alt_stub.S */ 18724/* 18725 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18726 * any interesting requests and then jump to the real instruction 18727 * handler. Note that the call to dvmCheckInst is done as a tail call. 18728 */ 18729 adrl lr, dvmAsmInstructionStart + (402 * 64) 18730 mov r0, rPC @ arg0 18731 mov r1, rSELF @ arg1 18732 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18733 18734/* ------------------------------ */ 18735 .balign 64 18736.L_ALT_OP_UNUSED_93FF: /* 0x193 */ 18737/* File: armv5te/alt_stub.S */ 18738/* 18739 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18740 * any interesting requests and then jump to the real instruction 18741 * handler. Note that the call to dvmCheckInst is done as a tail call. 18742 */ 18743 adrl lr, dvmAsmInstructionStart + (403 * 64) 18744 mov r0, rPC @ arg0 18745 mov r1, rSELF @ arg1 18746 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18747 18748/* ------------------------------ */ 18749 .balign 64 18750.L_ALT_OP_UNUSED_94FF: /* 0x194 */ 18751/* File: armv5te/alt_stub.S */ 18752/* 18753 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18754 * any interesting requests and then jump to the real instruction 18755 * handler. Note that the call to dvmCheckInst is done as a tail call. 18756 */ 18757 adrl lr, dvmAsmInstructionStart + (404 * 64) 18758 mov r0, rPC @ arg0 18759 mov r1, rSELF @ arg1 18760 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18761 18762/* ------------------------------ */ 18763 .balign 64 18764.L_ALT_OP_UNUSED_95FF: /* 0x195 */ 18765/* File: armv5te/alt_stub.S */ 18766/* 18767 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18768 * any interesting requests and then jump to the real instruction 18769 * handler. Note that the call to dvmCheckInst is done as a tail call. 18770 */ 18771 adrl lr, dvmAsmInstructionStart + (405 * 64) 18772 mov r0, rPC @ arg0 18773 mov r1, rSELF @ arg1 18774 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18775 18776/* ------------------------------ */ 18777 .balign 64 18778.L_ALT_OP_UNUSED_96FF: /* 0x196 */ 18779/* File: armv5te/alt_stub.S */ 18780/* 18781 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18782 * any interesting requests and then jump to the real instruction 18783 * handler. Note that the call to dvmCheckInst is done as a tail call. 18784 */ 18785 adrl lr, dvmAsmInstructionStart + (406 * 64) 18786 mov r0, rPC @ arg0 18787 mov r1, rSELF @ arg1 18788 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18789 18790/* ------------------------------ */ 18791 .balign 64 18792.L_ALT_OP_UNUSED_97FF: /* 0x197 */ 18793/* File: armv5te/alt_stub.S */ 18794/* 18795 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18796 * any interesting requests and then jump to the real instruction 18797 * handler. Note that the call to dvmCheckInst is done as a tail call. 18798 */ 18799 adrl lr, dvmAsmInstructionStart + (407 * 64) 18800 mov r0, rPC @ arg0 18801 mov r1, rSELF @ arg1 18802 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18803 18804/* ------------------------------ */ 18805 .balign 64 18806.L_ALT_OP_UNUSED_98FF: /* 0x198 */ 18807/* File: armv5te/alt_stub.S */ 18808/* 18809 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18810 * any interesting requests and then jump to the real instruction 18811 * handler. Note that the call to dvmCheckInst is done as a tail call. 18812 */ 18813 adrl lr, dvmAsmInstructionStart + (408 * 64) 18814 mov r0, rPC @ arg0 18815 mov r1, rSELF @ arg1 18816 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18817 18818/* ------------------------------ */ 18819 .balign 64 18820.L_ALT_OP_UNUSED_99FF: /* 0x199 */ 18821/* File: armv5te/alt_stub.S */ 18822/* 18823 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18824 * any interesting requests and then jump to the real instruction 18825 * handler. Note that the call to dvmCheckInst is done as a tail call. 18826 */ 18827 adrl lr, dvmAsmInstructionStart + (409 * 64) 18828 mov r0, rPC @ arg0 18829 mov r1, rSELF @ arg1 18830 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18831 18832/* ------------------------------ */ 18833 .balign 64 18834.L_ALT_OP_UNUSED_9AFF: /* 0x19a */ 18835/* File: armv5te/alt_stub.S */ 18836/* 18837 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18838 * any interesting requests and then jump to the real instruction 18839 * handler. Note that the call to dvmCheckInst is done as a tail call. 18840 */ 18841 adrl lr, dvmAsmInstructionStart + (410 * 64) 18842 mov r0, rPC @ arg0 18843 mov r1, rSELF @ arg1 18844 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18845 18846/* ------------------------------ */ 18847 .balign 64 18848.L_ALT_OP_UNUSED_9BFF: /* 0x19b */ 18849/* File: armv5te/alt_stub.S */ 18850/* 18851 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18852 * any interesting requests and then jump to the real instruction 18853 * handler. Note that the call to dvmCheckInst is done as a tail call. 18854 */ 18855 adrl lr, dvmAsmInstructionStart + (411 * 64) 18856 mov r0, rPC @ arg0 18857 mov r1, rSELF @ arg1 18858 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18859 18860/* ------------------------------ */ 18861 .balign 64 18862.L_ALT_OP_UNUSED_9CFF: /* 0x19c */ 18863/* File: armv5te/alt_stub.S */ 18864/* 18865 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18866 * any interesting requests and then jump to the real instruction 18867 * handler. Note that the call to dvmCheckInst is done as a tail call. 18868 */ 18869 adrl lr, dvmAsmInstructionStart + (412 * 64) 18870 mov r0, rPC @ arg0 18871 mov r1, rSELF @ arg1 18872 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18873 18874/* ------------------------------ */ 18875 .balign 64 18876.L_ALT_OP_UNUSED_9DFF: /* 0x19d */ 18877/* File: armv5te/alt_stub.S */ 18878/* 18879 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18880 * any interesting requests and then jump to the real instruction 18881 * handler. Note that the call to dvmCheckInst is done as a tail call. 18882 */ 18883 adrl lr, dvmAsmInstructionStart + (413 * 64) 18884 mov r0, rPC @ arg0 18885 mov r1, rSELF @ arg1 18886 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18887 18888/* ------------------------------ */ 18889 .balign 64 18890.L_ALT_OP_UNUSED_9EFF: /* 0x19e */ 18891/* File: armv5te/alt_stub.S */ 18892/* 18893 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18894 * any interesting requests and then jump to the real instruction 18895 * handler. Note that the call to dvmCheckInst is done as a tail call. 18896 */ 18897 adrl lr, dvmAsmInstructionStart + (414 * 64) 18898 mov r0, rPC @ arg0 18899 mov r1, rSELF @ arg1 18900 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18901 18902/* ------------------------------ */ 18903 .balign 64 18904.L_ALT_OP_UNUSED_9FFF: /* 0x19f */ 18905/* File: armv5te/alt_stub.S */ 18906/* 18907 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18908 * any interesting requests and then jump to the real instruction 18909 * handler. Note that the call to dvmCheckInst is done as a tail call. 18910 */ 18911 adrl lr, dvmAsmInstructionStart + (415 * 64) 18912 mov r0, rPC @ arg0 18913 mov r1, rSELF @ arg1 18914 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18915 18916/* ------------------------------ */ 18917 .balign 64 18918.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */ 18919/* File: armv5te/alt_stub.S */ 18920/* 18921 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18922 * any interesting requests and then jump to the real instruction 18923 * handler. Note that the call to dvmCheckInst is done as a tail call. 18924 */ 18925 adrl lr, dvmAsmInstructionStart + (416 * 64) 18926 mov r0, rPC @ arg0 18927 mov r1, rSELF @ arg1 18928 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18929 18930/* ------------------------------ */ 18931 .balign 64 18932.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */ 18933/* File: armv5te/alt_stub.S */ 18934/* 18935 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18936 * any interesting requests and then jump to the real instruction 18937 * handler. Note that the call to dvmCheckInst is done as a tail call. 18938 */ 18939 adrl lr, dvmAsmInstructionStart + (417 * 64) 18940 mov r0, rPC @ arg0 18941 mov r1, rSELF @ arg1 18942 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18943 18944/* ------------------------------ */ 18945 .balign 64 18946.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */ 18947/* File: armv5te/alt_stub.S */ 18948/* 18949 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18950 * any interesting requests and then jump to the real instruction 18951 * handler. Note that the call to dvmCheckInst is done as a tail call. 18952 */ 18953 adrl lr, dvmAsmInstructionStart + (418 * 64) 18954 mov r0, rPC @ arg0 18955 mov r1, rSELF @ arg1 18956 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18957 18958/* ------------------------------ */ 18959 .balign 64 18960.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */ 18961/* File: armv5te/alt_stub.S */ 18962/* 18963 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18964 * any interesting requests and then jump to the real instruction 18965 * handler. Note that the call to dvmCheckInst is done as a tail call. 18966 */ 18967 adrl lr, dvmAsmInstructionStart + (419 * 64) 18968 mov r0, rPC @ arg0 18969 mov r1, rSELF @ arg1 18970 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18971 18972/* ------------------------------ */ 18973 .balign 64 18974.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */ 18975/* File: armv5te/alt_stub.S */ 18976/* 18977 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18978 * any interesting requests and then jump to the real instruction 18979 * handler. Note that the call to dvmCheckInst is done as a tail call. 18980 */ 18981 adrl lr, dvmAsmInstructionStart + (420 * 64) 18982 mov r0, rPC @ arg0 18983 mov r1, rSELF @ arg1 18984 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18985 18986/* ------------------------------ */ 18987 .balign 64 18988.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */ 18989/* File: armv5te/alt_stub.S */ 18990/* 18991 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18992 * any interesting requests and then jump to the real instruction 18993 * handler. Note that the call to dvmCheckInst is done as a tail call. 18994 */ 18995 adrl lr, dvmAsmInstructionStart + (421 * 64) 18996 mov r0, rPC @ arg0 18997 mov r1, rSELF @ arg1 18998 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18999 19000/* ------------------------------ */ 19001 .balign 64 19002.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */ 19003/* File: armv5te/alt_stub.S */ 19004/* 19005 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19006 * any interesting requests and then jump to the real instruction 19007 * handler. Note that the call to dvmCheckInst is done as a tail call. 19008 */ 19009 adrl lr, dvmAsmInstructionStart + (422 * 64) 19010 mov r0, rPC @ arg0 19011 mov r1, rSELF @ arg1 19012 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19013 19014/* ------------------------------ */ 19015 .balign 64 19016.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */ 19017/* File: armv5te/alt_stub.S */ 19018/* 19019 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19020 * any interesting requests and then jump to the real instruction 19021 * handler. Note that the call to dvmCheckInst is done as a tail call. 19022 */ 19023 adrl lr, dvmAsmInstructionStart + (423 * 64) 19024 mov r0, rPC @ arg0 19025 mov r1, rSELF @ arg1 19026 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19027 19028/* ------------------------------ */ 19029 .balign 64 19030.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */ 19031/* File: armv5te/alt_stub.S */ 19032/* 19033 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19034 * any interesting requests and then jump to the real instruction 19035 * handler. Note that the call to dvmCheckInst is done as a tail call. 19036 */ 19037 adrl lr, dvmAsmInstructionStart + (424 * 64) 19038 mov r0, rPC @ arg0 19039 mov r1, rSELF @ arg1 19040 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19041 19042/* ------------------------------ */ 19043 .balign 64 19044.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */ 19045/* File: armv5te/alt_stub.S */ 19046/* 19047 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19048 * any interesting requests and then jump to the real instruction 19049 * handler. Note that the call to dvmCheckInst is done as a tail call. 19050 */ 19051 adrl lr, dvmAsmInstructionStart + (425 * 64) 19052 mov r0, rPC @ arg0 19053 mov r1, rSELF @ arg1 19054 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19055 19056/* ------------------------------ */ 19057 .balign 64 19058.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */ 19059/* File: armv5te/alt_stub.S */ 19060/* 19061 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19062 * any interesting requests and then jump to the real instruction 19063 * handler. Note that the call to dvmCheckInst is done as a tail call. 19064 */ 19065 adrl lr, dvmAsmInstructionStart + (426 * 64) 19066 mov r0, rPC @ arg0 19067 mov r1, rSELF @ arg1 19068 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19069 19070/* ------------------------------ */ 19071 .balign 64 19072.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */ 19073/* File: armv5te/alt_stub.S */ 19074/* 19075 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19076 * any interesting requests and then jump to the real instruction 19077 * handler. Note that the call to dvmCheckInst is done as a tail call. 19078 */ 19079 adrl lr, dvmAsmInstructionStart + (427 * 64) 19080 mov r0, rPC @ arg0 19081 mov r1, rSELF @ arg1 19082 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19083 19084/* ------------------------------ */ 19085 .balign 64 19086.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */ 19087/* File: armv5te/alt_stub.S */ 19088/* 19089 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19090 * any interesting requests and then jump to the real instruction 19091 * handler. Note that the call to dvmCheckInst is done as a tail call. 19092 */ 19093 adrl lr, dvmAsmInstructionStart + (428 * 64) 19094 mov r0, rPC @ arg0 19095 mov r1, rSELF @ arg1 19096 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19097 19098/* ------------------------------ */ 19099 .balign 64 19100.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */ 19101/* File: armv5te/alt_stub.S */ 19102/* 19103 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19104 * any interesting requests and then jump to the real instruction 19105 * handler. Note that the call to dvmCheckInst is done as a tail call. 19106 */ 19107 adrl lr, dvmAsmInstructionStart + (429 * 64) 19108 mov r0, rPC @ arg0 19109 mov r1, rSELF @ arg1 19110 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19111 19112/* ------------------------------ */ 19113 .balign 64 19114.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */ 19115/* File: armv5te/alt_stub.S */ 19116/* 19117 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19118 * any interesting requests and then jump to the real instruction 19119 * handler. Note that the call to dvmCheckInst is done as a tail call. 19120 */ 19121 adrl lr, dvmAsmInstructionStart + (430 * 64) 19122 mov r0, rPC @ arg0 19123 mov r1, rSELF @ arg1 19124 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19125 19126/* ------------------------------ */ 19127 .balign 64 19128.L_ALT_OP_UNUSED_AFFF: /* 0x1af */ 19129/* File: armv5te/alt_stub.S */ 19130/* 19131 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19132 * any interesting requests and then jump to the real instruction 19133 * handler. Note that the call to dvmCheckInst is done as a tail call. 19134 */ 19135 adrl lr, dvmAsmInstructionStart + (431 * 64) 19136 mov r0, rPC @ arg0 19137 mov r1, rSELF @ arg1 19138 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19139 19140/* ------------------------------ */ 19141 .balign 64 19142.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */ 19143/* File: armv5te/alt_stub.S */ 19144/* 19145 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19146 * any interesting requests and then jump to the real instruction 19147 * handler. Note that the call to dvmCheckInst is done as a tail call. 19148 */ 19149 adrl lr, dvmAsmInstructionStart + (432 * 64) 19150 mov r0, rPC @ arg0 19151 mov r1, rSELF @ arg1 19152 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19153 19154/* ------------------------------ */ 19155 .balign 64 19156.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */ 19157/* File: armv5te/alt_stub.S */ 19158/* 19159 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19160 * any interesting requests and then jump to the real instruction 19161 * handler. Note that the call to dvmCheckInst is done as a tail call. 19162 */ 19163 adrl lr, dvmAsmInstructionStart + (433 * 64) 19164 mov r0, rPC @ arg0 19165 mov r1, rSELF @ arg1 19166 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19167 19168/* ------------------------------ */ 19169 .balign 64 19170.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */ 19171/* File: armv5te/alt_stub.S */ 19172/* 19173 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19174 * any interesting requests and then jump to the real instruction 19175 * handler. Note that the call to dvmCheckInst is done as a tail call. 19176 */ 19177 adrl lr, dvmAsmInstructionStart + (434 * 64) 19178 mov r0, rPC @ arg0 19179 mov r1, rSELF @ arg1 19180 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19181 19182/* ------------------------------ */ 19183 .balign 64 19184.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */ 19185/* File: armv5te/alt_stub.S */ 19186/* 19187 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19188 * any interesting requests and then jump to the real instruction 19189 * handler. Note that the call to dvmCheckInst is done as a tail call. 19190 */ 19191 adrl lr, dvmAsmInstructionStart + (435 * 64) 19192 mov r0, rPC @ arg0 19193 mov r1, rSELF @ arg1 19194 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19195 19196/* ------------------------------ */ 19197 .balign 64 19198.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */ 19199/* File: armv5te/alt_stub.S */ 19200/* 19201 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19202 * any interesting requests and then jump to the real instruction 19203 * handler. Note that the call to dvmCheckInst is done as a tail call. 19204 */ 19205 adrl lr, dvmAsmInstructionStart + (436 * 64) 19206 mov r0, rPC @ arg0 19207 mov r1, rSELF @ arg1 19208 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19209 19210/* ------------------------------ */ 19211 .balign 64 19212.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */ 19213/* File: armv5te/alt_stub.S */ 19214/* 19215 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19216 * any interesting requests and then jump to the real instruction 19217 * handler. Note that the call to dvmCheckInst is done as a tail call. 19218 */ 19219 adrl lr, dvmAsmInstructionStart + (437 * 64) 19220 mov r0, rPC @ arg0 19221 mov r1, rSELF @ arg1 19222 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19223 19224/* ------------------------------ */ 19225 .balign 64 19226.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */ 19227/* File: armv5te/alt_stub.S */ 19228/* 19229 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19230 * any interesting requests and then jump to the real instruction 19231 * handler. Note that the call to dvmCheckInst is done as a tail call. 19232 */ 19233 adrl lr, dvmAsmInstructionStart + (438 * 64) 19234 mov r0, rPC @ arg0 19235 mov r1, rSELF @ arg1 19236 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19237 19238/* ------------------------------ */ 19239 .balign 64 19240.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */ 19241/* File: armv5te/alt_stub.S */ 19242/* 19243 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19244 * any interesting requests and then jump to the real instruction 19245 * handler. Note that the call to dvmCheckInst is done as a tail call. 19246 */ 19247 adrl lr, dvmAsmInstructionStart + (439 * 64) 19248 mov r0, rPC @ arg0 19249 mov r1, rSELF @ arg1 19250 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19251 19252/* ------------------------------ */ 19253 .balign 64 19254.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */ 19255/* File: armv5te/alt_stub.S */ 19256/* 19257 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19258 * any interesting requests and then jump to the real instruction 19259 * handler. Note that the call to dvmCheckInst is done as a tail call. 19260 */ 19261 adrl lr, dvmAsmInstructionStart + (440 * 64) 19262 mov r0, rPC @ arg0 19263 mov r1, rSELF @ arg1 19264 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19265 19266/* ------------------------------ */ 19267 .balign 64 19268.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */ 19269/* File: armv5te/alt_stub.S */ 19270/* 19271 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19272 * any interesting requests and then jump to the real instruction 19273 * handler. Note that the call to dvmCheckInst is done as a tail call. 19274 */ 19275 adrl lr, dvmAsmInstructionStart + (441 * 64) 19276 mov r0, rPC @ arg0 19277 mov r1, rSELF @ arg1 19278 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19279 19280/* ------------------------------ */ 19281 .balign 64 19282.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */ 19283/* File: armv5te/alt_stub.S */ 19284/* 19285 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19286 * any interesting requests and then jump to the real instruction 19287 * handler. Note that the call to dvmCheckInst is done as a tail call. 19288 */ 19289 adrl lr, dvmAsmInstructionStart + (442 * 64) 19290 mov r0, rPC @ arg0 19291 mov r1, rSELF @ arg1 19292 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19293 19294/* ------------------------------ */ 19295 .balign 64 19296.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */ 19297/* File: armv5te/alt_stub.S */ 19298/* 19299 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19300 * any interesting requests and then jump to the real instruction 19301 * handler. Note that the call to dvmCheckInst is done as a tail call. 19302 */ 19303 adrl lr, dvmAsmInstructionStart + (443 * 64) 19304 mov r0, rPC @ arg0 19305 mov r1, rSELF @ arg1 19306 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19307 19308/* ------------------------------ */ 19309 .balign 64 19310.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */ 19311/* File: armv5te/alt_stub.S */ 19312/* 19313 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19314 * any interesting requests and then jump to the real instruction 19315 * handler. Note that the call to dvmCheckInst is done as a tail call. 19316 */ 19317 adrl lr, dvmAsmInstructionStart + (444 * 64) 19318 mov r0, rPC @ arg0 19319 mov r1, rSELF @ arg1 19320 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19321 19322/* ------------------------------ */ 19323 .balign 64 19324.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */ 19325/* File: armv5te/alt_stub.S */ 19326/* 19327 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19328 * any interesting requests and then jump to the real instruction 19329 * handler. Note that the call to dvmCheckInst is done as a tail call. 19330 */ 19331 adrl lr, dvmAsmInstructionStart + (445 * 64) 19332 mov r0, rPC @ arg0 19333 mov r1, rSELF @ arg1 19334 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19335 19336/* ------------------------------ */ 19337 .balign 64 19338.L_ALT_OP_UNUSED_BEFF: /* 0x1be */ 19339/* File: armv5te/alt_stub.S */ 19340/* 19341 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19342 * any interesting requests and then jump to the real instruction 19343 * handler. Note that the call to dvmCheckInst is done as a tail call. 19344 */ 19345 adrl lr, dvmAsmInstructionStart + (446 * 64) 19346 mov r0, rPC @ arg0 19347 mov r1, rSELF @ arg1 19348 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19349 19350/* ------------------------------ */ 19351 .balign 64 19352.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */ 19353/* File: armv5te/alt_stub.S */ 19354/* 19355 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19356 * any interesting requests and then jump to the real instruction 19357 * handler. Note that the call to dvmCheckInst is done as a tail call. 19358 */ 19359 adrl lr, dvmAsmInstructionStart + (447 * 64) 19360 mov r0, rPC @ arg0 19361 mov r1, rSELF @ arg1 19362 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19363 19364/* ------------------------------ */ 19365 .balign 64 19366.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */ 19367/* File: armv5te/alt_stub.S */ 19368/* 19369 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19370 * any interesting requests and then jump to the real instruction 19371 * handler. Note that the call to dvmCheckInst is done as a tail call. 19372 */ 19373 adrl lr, dvmAsmInstructionStart + (448 * 64) 19374 mov r0, rPC @ arg0 19375 mov r1, rSELF @ arg1 19376 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19377 19378/* ------------------------------ */ 19379 .balign 64 19380.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */ 19381/* File: armv5te/alt_stub.S */ 19382/* 19383 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19384 * any interesting requests and then jump to the real instruction 19385 * handler. Note that the call to dvmCheckInst is done as a tail call. 19386 */ 19387 adrl lr, dvmAsmInstructionStart + (449 * 64) 19388 mov r0, rPC @ arg0 19389 mov r1, rSELF @ arg1 19390 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19391 19392/* ------------------------------ */ 19393 .balign 64 19394.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */ 19395/* File: armv5te/alt_stub.S */ 19396/* 19397 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19398 * any interesting requests and then jump to the real instruction 19399 * handler. Note that the call to dvmCheckInst is done as a tail call. 19400 */ 19401 adrl lr, dvmAsmInstructionStart + (450 * 64) 19402 mov r0, rPC @ arg0 19403 mov r1, rSELF @ arg1 19404 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19405 19406/* ------------------------------ */ 19407 .balign 64 19408.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */ 19409/* File: armv5te/alt_stub.S */ 19410/* 19411 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19412 * any interesting requests and then jump to the real instruction 19413 * handler. Note that the call to dvmCheckInst is done as a tail call. 19414 */ 19415 adrl lr, dvmAsmInstructionStart + (451 * 64) 19416 mov r0, rPC @ arg0 19417 mov r1, rSELF @ arg1 19418 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19419 19420/* ------------------------------ */ 19421 .balign 64 19422.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */ 19423/* File: armv5te/alt_stub.S */ 19424/* 19425 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19426 * any interesting requests and then jump to the real instruction 19427 * handler. Note that the call to dvmCheckInst is done as a tail call. 19428 */ 19429 adrl lr, dvmAsmInstructionStart + (452 * 64) 19430 mov r0, rPC @ arg0 19431 mov r1, rSELF @ arg1 19432 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19433 19434/* ------------------------------ */ 19435 .balign 64 19436.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */ 19437/* File: armv5te/alt_stub.S */ 19438/* 19439 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19440 * any interesting requests and then jump to the real instruction 19441 * handler. Note that the call to dvmCheckInst is done as a tail call. 19442 */ 19443 adrl lr, dvmAsmInstructionStart + (453 * 64) 19444 mov r0, rPC @ arg0 19445 mov r1, rSELF @ arg1 19446 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19447 19448/* ------------------------------ */ 19449 .balign 64 19450.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */ 19451/* File: armv5te/alt_stub.S */ 19452/* 19453 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19454 * any interesting requests and then jump to the real instruction 19455 * handler. Note that the call to dvmCheckInst is done as a tail call. 19456 */ 19457 adrl lr, dvmAsmInstructionStart + (454 * 64) 19458 mov r0, rPC @ arg0 19459 mov r1, rSELF @ arg1 19460 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19461 19462/* ------------------------------ */ 19463 .balign 64 19464.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */ 19465/* File: armv5te/alt_stub.S */ 19466/* 19467 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19468 * any interesting requests and then jump to the real instruction 19469 * handler. Note that the call to dvmCheckInst is done as a tail call. 19470 */ 19471 adrl lr, dvmAsmInstructionStart + (455 * 64) 19472 mov r0, rPC @ arg0 19473 mov r1, rSELF @ arg1 19474 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19475 19476/* ------------------------------ */ 19477 .balign 64 19478.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */ 19479/* File: armv5te/alt_stub.S */ 19480/* 19481 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19482 * any interesting requests and then jump to the real instruction 19483 * handler. Note that the call to dvmCheckInst is done as a tail call. 19484 */ 19485 adrl lr, dvmAsmInstructionStart + (456 * 64) 19486 mov r0, rPC @ arg0 19487 mov r1, rSELF @ arg1 19488 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19489 19490/* ------------------------------ */ 19491 .balign 64 19492.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */ 19493/* File: armv5te/alt_stub.S */ 19494/* 19495 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19496 * any interesting requests and then jump to the real instruction 19497 * handler. Note that the call to dvmCheckInst is done as a tail call. 19498 */ 19499 adrl lr, dvmAsmInstructionStart + (457 * 64) 19500 mov r0, rPC @ arg0 19501 mov r1, rSELF @ arg1 19502 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19503 19504/* ------------------------------ */ 19505 .balign 64 19506.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */ 19507/* File: armv5te/alt_stub.S */ 19508/* 19509 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19510 * any interesting requests and then jump to the real instruction 19511 * handler. Note that the call to dvmCheckInst is done as a tail call. 19512 */ 19513 adrl lr, dvmAsmInstructionStart + (458 * 64) 19514 mov r0, rPC @ arg0 19515 mov r1, rSELF @ arg1 19516 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19517 19518/* ------------------------------ */ 19519 .balign 64 19520.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */ 19521/* File: armv5te/alt_stub.S */ 19522/* 19523 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19524 * any interesting requests and then jump to the real instruction 19525 * handler. Note that the call to dvmCheckInst is done as a tail call. 19526 */ 19527 adrl lr, dvmAsmInstructionStart + (459 * 64) 19528 mov r0, rPC @ arg0 19529 mov r1, rSELF @ arg1 19530 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19531 19532/* ------------------------------ */ 19533 .balign 64 19534.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */ 19535/* File: armv5te/alt_stub.S */ 19536/* 19537 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19538 * any interesting requests and then jump to the real instruction 19539 * handler. Note that the call to dvmCheckInst is done as a tail call. 19540 */ 19541 adrl lr, dvmAsmInstructionStart + (460 * 64) 19542 mov r0, rPC @ arg0 19543 mov r1, rSELF @ arg1 19544 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19545 19546/* ------------------------------ */ 19547 .balign 64 19548.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */ 19549/* File: armv5te/alt_stub.S */ 19550/* 19551 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19552 * any interesting requests and then jump to the real instruction 19553 * handler. Note that the call to dvmCheckInst is done as a tail call. 19554 */ 19555 adrl lr, dvmAsmInstructionStart + (461 * 64) 19556 mov r0, rPC @ arg0 19557 mov r1, rSELF @ arg1 19558 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19559 19560/* ------------------------------ */ 19561 .balign 64 19562.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */ 19563/* File: armv5te/alt_stub.S */ 19564/* 19565 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19566 * any interesting requests and then jump to the real instruction 19567 * handler. Note that the call to dvmCheckInst is done as a tail call. 19568 */ 19569 adrl lr, dvmAsmInstructionStart + (462 * 64) 19570 mov r0, rPC @ arg0 19571 mov r1, rSELF @ arg1 19572 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19573 19574/* ------------------------------ */ 19575 .balign 64 19576.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */ 19577/* File: armv5te/alt_stub.S */ 19578/* 19579 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19580 * any interesting requests and then jump to the real instruction 19581 * handler. Note that the call to dvmCheckInst is done as a tail call. 19582 */ 19583 adrl lr, dvmAsmInstructionStart + (463 * 64) 19584 mov r0, rPC @ arg0 19585 mov r1, rSELF @ arg1 19586 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19587 19588/* ------------------------------ */ 19589 .balign 64 19590.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */ 19591/* File: armv5te/alt_stub.S */ 19592/* 19593 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19594 * any interesting requests and then jump to the real instruction 19595 * handler. Note that the call to dvmCheckInst is done as a tail call. 19596 */ 19597 adrl lr, dvmAsmInstructionStart + (464 * 64) 19598 mov r0, rPC @ arg0 19599 mov r1, rSELF @ arg1 19600 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19601 19602/* ------------------------------ */ 19603 .balign 64 19604.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */ 19605/* File: armv5te/alt_stub.S */ 19606/* 19607 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19608 * any interesting requests and then jump to the real instruction 19609 * handler. Note that the call to dvmCheckInst is done as a tail call. 19610 */ 19611 adrl lr, dvmAsmInstructionStart + (465 * 64) 19612 mov r0, rPC @ arg0 19613 mov r1, rSELF @ arg1 19614 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19615 19616/* ------------------------------ */ 19617 .balign 64 19618.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */ 19619/* File: armv5te/alt_stub.S */ 19620/* 19621 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19622 * any interesting requests and then jump to the real instruction 19623 * handler. Note that the call to dvmCheckInst is done as a tail call. 19624 */ 19625 adrl lr, dvmAsmInstructionStart + (466 * 64) 19626 mov r0, rPC @ arg0 19627 mov r1, rSELF @ arg1 19628 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19629 19630/* ------------------------------ */ 19631 .balign 64 19632.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */ 19633/* File: armv5te/alt_stub.S */ 19634/* 19635 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19636 * any interesting requests and then jump to the real instruction 19637 * handler. Note that the call to dvmCheckInst is done as a tail call. 19638 */ 19639 adrl lr, dvmAsmInstructionStart + (467 * 64) 19640 mov r0, rPC @ arg0 19641 mov r1, rSELF @ arg1 19642 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19643 19644/* ------------------------------ */ 19645 .balign 64 19646.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */ 19647/* File: armv5te/alt_stub.S */ 19648/* 19649 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19650 * any interesting requests and then jump to the real instruction 19651 * handler. Note that the call to dvmCheckInst is done as a tail call. 19652 */ 19653 adrl lr, dvmAsmInstructionStart + (468 * 64) 19654 mov r0, rPC @ arg0 19655 mov r1, rSELF @ arg1 19656 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19657 19658/* ------------------------------ */ 19659 .balign 64 19660.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */ 19661/* File: armv5te/alt_stub.S */ 19662/* 19663 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19664 * any interesting requests and then jump to the real instruction 19665 * handler. Note that the call to dvmCheckInst is done as a tail call. 19666 */ 19667 adrl lr, dvmAsmInstructionStart + (469 * 64) 19668 mov r0, rPC @ arg0 19669 mov r1, rSELF @ arg1 19670 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19671 19672/* ------------------------------ */ 19673 .balign 64 19674.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */ 19675/* File: armv5te/alt_stub.S */ 19676/* 19677 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19678 * any interesting requests and then jump to the real instruction 19679 * handler. Note that the call to dvmCheckInst is done as a tail call. 19680 */ 19681 adrl lr, dvmAsmInstructionStart + (470 * 64) 19682 mov r0, rPC @ arg0 19683 mov r1, rSELF @ arg1 19684 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19685 19686/* ------------------------------ */ 19687 .balign 64 19688.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */ 19689/* File: armv5te/alt_stub.S */ 19690/* 19691 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19692 * any interesting requests and then jump to the real instruction 19693 * handler. Note that the call to dvmCheckInst is done as a tail call. 19694 */ 19695 adrl lr, dvmAsmInstructionStart + (471 * 64) 19696 mov r0, rPC @ arg0 19697 mov r1, rSELF @ arg1 19698 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19699 19700/* ------------------------------ */ 19701 .balign 64 19702.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */ 19703/* File: armv5te/alt_stub.S */ 19704/* 19705 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19706 * any interesting requests and then jump to the real instruction 19707 * handler. Note that the call to dvmCheckInst is done as a tail call. 19708 */ 19709 adrl lr, dvmAsmInstructionStart + (472 * 64) 19710 mov r0, rPC @ arg0 19711 mov r1, rSELF @ arg1 19712 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19713 19714/* ------------------------------ */ 19715 .balign 64 19716.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */ 19717/* File: armv5te/alt_stub.S */ 19718/* 19719 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19720 * any interesting requests and then jump to the real instruction 19721 * handler. Note that the call to dvmCheckInst is done as a tail call. 19722 */ 19723 adrl lr, dvmAsmInstructionStart + (473 * 64) 19724 mov r0, rPC @ arg0 19725 mov r1, rSELF @ arg1 19726 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19727 19728/* ------------------------------ */ 19729 .balign 64 19730.L_ALT_OP_UNUSED_DAFF: /* 0x1da */ 19731/* File: armv5te/alt_stub.S */ 19732/* 19733 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19734 * any interesting requests and then jump to the real instruction 19735 * handler. Note that the call to dvmCheckInst is done as a tail call. 19736 */ 19737 adrl lr, dvmAsmInstructionStart + (474 * 64) 19738 mov r0, rPC @ arg0 19739 mov r1, rSELF @ arg1 19740 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19741 19742/* ------------------------------ */ 19743 .balign 64 19744.L_ALT_OP_UNUSED_DBFF: /* 0x1db */ 19745/* File: armv5te/alt_stub.S */ 19746/* 19747 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19748 * any interesting requests and then jump to the real instruction 19749 * handler. Note that the call to dvmCheckInst is done as a tail call. 19750 */ 19751 adrl lr, dvmAsmInstructionStart + (475 * 64) 19752 mov r0, rPC @ arg0 19753 mov r1, rSELF @ arg1 19754 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19755 19756/* ------------------------------ */ 19757 .balign 64 19758.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */ 19759/* File: armv5te/alt_stub.S */ 19760/* 19761 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19762 * any interesting requests and then jump to the real instruction 19763 * handler. Note that the call to dvmCheckInst is done as a tail call. 19764 */ 19765 adrl lr, dvmAsmInstructionStart + (476 * 64) 19766 mov r0, rPC @ arg0 19767 mov r1, rSELF @ arg1 19768 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19769 19770/* ------------------------------ */ 19771 .balign 64 19772.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */ 19773/* File: armv5te/alt_stub.S */ 19774/* 19775 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19776 * any interesting requests and then jump to the real instruction 19777 * handler. Note that the call to dvmCheckInst is done as a tail call. 19778 */ 19779 adrl lr, dvmAsmInstructionStart + (477 * 64) 19780 mov r0, rPC @ arg0 19781 mov r1, rSELF @ arg1 19782 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19783 19784/* ------------------------------ */ 19785 .balign 64 19786.L_ALT_OP_UNUSED_DEFF: /* 0x1de */ 19787/* File: armv5te/alt_stub.S */ 19788/* 19789 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19790 * any interesting requests and then jump to the real instruction 19791 * handler. Note that the call to dvmCheckInst is done as a tail call. 19792 */ 19793 adrl lr, dvmAsmInstructionStart + (478 * 64) 19794 mov r0, rPC @ arg0 19795 mov r1, rSELF @ arg1 19796 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19797 19798/* ------------------------------ */ 19799 .balign 64 19800.L_ALT_OP_UNUSED_DFFF: /* 0x1df */ 19801/* File: armv5te/alt_stub.S */ 19802/* 19803 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19804 * any interesting requests and then jump to the real instruction 19805 * handler. Note that the call to dvmCheckInst is done as a tail call. 19806 */ 19807 adrl lr, dvmAsmInstructionStart + (479 * 64) 19808 mov r0, rPC @ arg0 19809 mov r1, rSELF @ arg1 19810 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19811 19812/* ------------------------------ */ 19813 .balign 64 19814.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */ 19815/* File: armv5te/alt_stub.S */ 19816/* 19817 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19818 * any interesting requests and then jump to the real instruction 19819 * handler. Note that the call to dvmCheckInst is done as a tail call. 19820 */ 19821 adrl lr, dvmAsmInstructionStart + (480 * 64) 19822 mov r0, rPC @ arg0 19823 mov r1, rSELF @ arg1 19824 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19825 19826/* ------------------------------ */ 19827 .balign 64 19828.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */ 19829/* File: armv5te/alt_stub.S */ 19830/* 19831 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19832 * any interesting requests and then jump to the real instruction 19833 * handler. Note that the call to dvmCheckInst is done as a tail call. 19834 */ 19835 adrl lr, dvmAsmInstructionStart + (481 * 64) 19836 mov r0, rPC @ arg0 19837 mov r1, rSELF @ arg1 19838 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19839 19840/* ------------------------------ */ 19841 .balign 64 19842.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */ 19843/* File: armv5te/alt_stub.S */ 19844/* 19845 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19846 * any interesting requests and then jump to the real instruction 19847 * handler. Note that the call to dvmCheckInst is done as a tail call. 19848 */ 19849 adrl lr, dvmAsmInstructionStart + (482 * 64) 19850 mov r0, rPC @ arg0 19851 mov r1, rSELF @ arg1 19852 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19853 19854/* ------------------------------ */ 19855 .balign 64 19856.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */ 19857/* File: armv5te/alt_stub.S */ 19858/* 19859 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19860 * any interesting requests and then jump to the real instruction 19861 * handler. Note that the call to dvmCheckInst is done as a tail call. 19862 */ 19863 adrl lr, dvmAsmInstructionStart + (483 * 64) 19864 mov r0, rPC @ arg0 19865 mov r1, rSELF @ arg1 19866 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19867 19868/* ------------------------------ */ 19869 .balign 64 19870.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */ 19871/* File: armv5te/alt_stub.S */ 19872/* 19873 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19874 * any interesting requests and then jump to the real instruction 19875 * handler. Note that the call to dvmCheckInst is done as a tail call. 19876 */ 19877 adrl lr, dvmAsmInstructionStart + (484 * 64) 19878 mov r0, rPC @ arg0 19879 mov r1, rSELF @ arg1 19880 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19881 19882/* ------------------------------ */ 19883 .balign 64 19884.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */ 19885/* File: armv5te/alt_stub.S */ 19886/* 19887 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19888 * any interesting requests and then jump to the real instruction 19889 * handler. Note that the call to dvmCheckInst is done as a tail call. 19890 */ 19891 adrl lr, dvmAsmInstructionStart + (485 * 64) 19892 mov r0, rPC @ arg0 19893 mov r1, rSELF @ arg1 19894 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19895 19896/* ------------------------------ */ 19897 .balign 64 19898.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */ 19899/* File: armv5te/alt_stub.S */ 19900/* 19901 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19902 * any interesting requests and then jump to the real instruction 19903 * handler. Note that the call to dvmCheckInst is done as a tail call. 19904 */ 19905 adrl lr, dvmAsmInstructionStart + (486 * 64) 19906 mov r0, rPC @ arg0 19907 mov r1, rSELF @ arg1 19908 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19909 19910/* ------------------------------ */ 19911 .balign 64 19912.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */ 19913/* File: armv5te/alt_stub.S */ 19914/* 19915 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19916 * any interesting requests and then jump to the real instruction 19917 * handler. Note that the call to dvmCheckInst is done as a tail call. 19918 */ 19919 adrl lr, dvmAsmInstructionStart + (487 * 64) 19920 mov r0, rPC @ arg0 19921 mov r1, rSELF @ arg1 19922 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19923 19924/* ------------------------------ */ 19925 .balign 64 19926.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */ 19927/* File: armv5te/alt_stub.S */ 19928/* 19929 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19930 * any interesting requests and then jump to the real instruction 19931 * handler. Note that the call to dvmCheckInst is done as a tail call. 19932 */ 19933 adrl lr, dvmAsmInstructionStart + (488 * 64) 19934 mov r0, rPC @ arg0 19935 mov r1, rSELF @ arg1 19936 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19937 19938/* ------------------------------ */ 19939 .balign 64 19940.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */ 19941/* File: armv5te/alt_stub.S */ 19942/* 19943 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19944 * any interesting requests and then jump to the real instruction 19945 * handler. Note that the call to dvmCheckInst is done as a tail call. 19946 */ 19947 adrl lr, dvmAsmInstructionStart + (489 * 64) 19948 mov r0, rPC @ arg0 19949 mov r1, rSELF @ arg1 19950 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19951 19952/* ------------------------------ */ 19953 .balign 64 19954.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */ 19955/* File: armv5te/alt_stub.S */ 19956/* 19957 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19958 * any interesting requests and then jump to the real instruction 19959 * handler. Note that the call to dvmCheckInst is done as a tail call. 19960 */ 19961 adrl lr, dvmAsmInstructionStart + (490 * 64) 19962 mov r0, rPC @ arg0 19963 mov r1, rSELF @ arg1 19964 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19965 19966/* ------------------------------ */ 19967 .balign 64 19968.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */ 19969/* File: armv5te/alt_stub.S */ 19970/* 19971 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19972 * any interesting requests and then jump to the real instruction 19973 * handler. Note that the call to dvmCheckInst is done as a tail call. 19974 */ 19975 adrl lr, dvmAsmInstructionStart + (491 * 64) 19976 mov r0, rPC @ arg0 19977 mov r1, rSELF @ arg1 19978 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19979 19980/* ------------------------------ */ 19981 .balign 64 19982.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */ 19983/* File: armv5te/alt_stub.S */ 19984/* 19985 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19986 * any interesting requests and then jump to the real instruction 19987 * handler. Note that the call to dvmCheckInst is done as a tail call. 19988 */ 19989 adrl lr, dvmAsmInstructionStart + (492 * 64) 19990 mov r0, rPC @ arg0 19991 mov r1, rSELF @ arg1 19992 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19993 19994/* ------------------------------ */ 19995 .balign 64 19996.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */ 19997/* File: armv5te/alt_stub.S */ 19998/* 19999 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20000 * any interesting requests and then jump to the real instruction 20001 * handler. Note that the call to dvmCheckInst is done as a tail call. 20002 */ 20003 adrl lr, dvmAsmInstructionStart + (493 * 64) 20004 mov r0, rPC @ arg0 20005 mov r1, rSELF @ arg1 20006 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20007 20008/* ------------------------------ */ 20009 .balign 64 20010.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */ 20011/* File: armv5te/alt_stub.S */ 20012/* 20013 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20014 * any interesting requests and then jump to the real instruction 20015 * handler. Note that the call to dvmCheckInst is done as a tail call. 20016 */ 20017 adrl lr, dvmAsmInstructionStart + (494 * 64) 20018 mov r0, rPC @ arg0 20019 mov r1, rSELF @ arg1 20020 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20021 20022/* ------------------------------ */ 20023 .balign 64 20024.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */ 20025/* File: armv5te/alt_stub.S */ 20026/* 20027 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20028 * any interesting requests and then jump to the real instruction 20029 * handler. Note that the call to dvmCheckInst is done as a tail call. 20030 */ 20031 adrl lr, dvmAsmInstructionStart + (495 * 64) 20032 mov r0, rPC @ arg0 20033 mov r1, rSELF @ arg1 20034 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20035 20036/* ------------------------------ */ 20037 .balign 64 20038.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */ 20039/* File: armv5te/alt_stub.S */ 20040/* 20041 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20042 * any interesting requests and then jump to the real instruction 20043 * handler. Note that the call to dvmCheckInst is done as a tail call. 20044 */ 20045 adrl lr, dvmAsmInstructionStart + (496 * 64) 20046 mov r0, rPC @ arg0 20047 mov r1, rSELF @ arg1 20048 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20049 20050/* ------------------------------ */ 20051 .balign 64 20052.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */ 20053/* File: armv5te/alt_stub.S */ 20054/* 20055 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20056 * any interesting requests and then jump to the real instruction 20057 * handler. Note that the call to dvmCheckInst is done as a tail call. 20058 */ 20059 adrl lr, dvmAsmInstructionStart + (497 * 64) 20060 mov r0, rPC @ arg0 20061 mov r1, rSELF @ arg1 20062 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20063 20064/* ------------------------------ */ 20065 .balign 64 20066.L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */ 20067/* File: armv5te/alt_stub.S */ 20068/* 20069 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20070 * any interesting requests and then jump to the real instruction 20071 * handler. Note that the call to dvmCheckInst is done as a tail call. 20072 */ 20073 adrl lr, dvmAsmInstructionStart + (498 * 64) 20074 mov r0, rPC @ arg0 20075 mov r1, rSELF @ arg1 20076 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20077 20078/* ------------------------------ */ 20079 .balign 64 20080.L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */ 20081/* File: armv5te/alt_stub.S */ 20082/* 20083 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20084 * any interesting requests and then jump to the real instruction 20085 * handler. Note that the call to dvmCheckInst is done as a tail call. 20086 */ 20087 adrl lr, dvmAsmInstructionStart + (499 * 64) 20088 mov r0, rPC @ arg0 20089 mov r1, rSELF @ arg1 20090 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20091 20092/* ------------------------------ */ 20093 .balign 64 20094.L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */ 20095/* File: armv5te/alt_stub.S */ 20096/* 20097 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20098 * any interesting requests and then jump to the real instruction 20099 * handler. Note that the call to dvmCheckInst is done as a tail call. 20100 */ 20101 adrl lr, dvmAsmInstructionStart + (500 * 64) 20102 mov r0, rPC @ arg0 20103 mov r1, rSELF @ arg1 20104 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20105 20106/* ------------------------------ */ 20107 .balign 64 20108.L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */ 20109/* File: armv5te/alt_stub.S */ 20110/* 20111 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20112 * any interesting requests and then jump to the real instruction 20113 * handler. Note that the call to dvmCheckInst is done as a tail call. 20114 */ 20115 adrl lr, dvmAsmInstructionStart + (501 * 64) 20116 mov r0, rPC @ arg0 20117 mov r1, rSELF @ arg1 20118 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20119 20120/* ------------------------------ */ 20121 .balign 64 20122.L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */ 20123/* File: armv5te/alt_stub.S */ 20124/* 20125 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20126 * any interesting requests and then jump to the real instruction 20127 * handler. Note that the call to dvmCheckInst is done as a tail call. 20128 */ 20129 adrl lr, dvmAsmInstructionStart + (502 * 64) 20130 mov r0, rPC @ arg0 20131 mov r1, rSELF @ arg1 20132 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20133 20134/* ------------------------------ */ 20135 .balign 64 20136.L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */ 20137/* File: armv5te/alt_stub.S */ 20138/* 20139 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20140 * any interesting requests and then jump to the real instruction 20141 * handler. Note that the call to dvmCheckInst is done as a tail call. 20142 */ 20143 adrl lr, dvmAsmInstructionStart + (503 * 64) 20144 mov r0, rPC @ arg0 20145 mov r1, rSELF @ arg1 20146 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20147 20148/* ------------------------------ */ 20149 .balign 64 20150.L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */ 20151/* File: armv5te/alt_stub.S */ 20152/* 20153 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20154 * any interesting requests and then jump to the real instruction 20155 * handler. Note that the call to dvmCheckInst is done as a tail call. 20156 */ 20157 adrl lr, dvmAsmInstructionStart + (504 * 64) 20158 mov r0, rPC @ arg0 20159 mov r1, rSELF @ arg1 20160 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20161 20162/* ------------------------------ */ 20163 .balign 64 20164.L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */ 20165/* File: armv5te/alt_stub.S */ 20166/* 20167 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20168 * any interesting requests and then jump to the real instruction 20169 * handler. Note that the call to dvmCheckInst is done as a tail call. 20170 */ 20171 adrl lr, dvmAsmInstructionStart + (505 * 64) 20172 mov r0, rPC @ arg0 20173 mov r1, rSELF @ arg1 20174 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20175 20176/* ------------------------------ */ 20177 .balign 64 20178.L_ALT_OP_UNUSED_FAFF: /* 0x1fa */ 20179/* File: armv5te/alt_stub.S */ 20180/* 20181 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20182 * any interesting requests and then jump to the real instruction 20183 * handler. Note that the call to dvmCheckInst is done as a tail call. 20184 */ 20185 adrl lr, dvmAsmInstructionStart + (506 * 64) 20186 mov r0, rPC @ arg0 20187 mov r1, rSELF @ arg1 20188 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20189 20190/* ------------------------------ */ 20191 .balign 64 20192.L_ALT_OP_UNUSED_FBFF: /* 0x1fb */ 20193/* File: armv5te/alt_stub.S */ 20194/* 20195 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20196 * any interesting requests and then jump to the real instruction 20197 * handler. Note that the call to dvmCheckInst is done as a tail call. 20198 */ 20199 adrl lr, dvmAsmInstructionStart + (507 * 64) 20200 mov r0, rPC @ arg0 20201 mov r1, rSELF @ arg1 20202 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20203 20204/* ------------------------------ */ 20205 .balign 64 20206.L_ALT_OP_UNUSED_FCFF: /* 0x1fc */ 20207/* File: armv5te/alt_stub.S */ 20208/* 20209 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20210 * any interesting requests and then jump to the real instruction 20211 * handler. Note that the call to dvmCheckInst is done as a tail call. 20212 */ 20213 adrl lr, dvmAsmInstructionStart + (508 * 64) 20214 mov r0, rPC @ arg0 20215 mov r1, rSELF @ arg1 20216 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20217 20218/* ------------------------------ */ 20219 .balign 64 20220.L_ALT_OP_UNUSED_FDFF: /* 0x1fd */ 20221/* File: armv5te/alt_stub.S */ 20222/* 20223 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20224 * any interesting requests and then jump to the real instruction 20225 * handler. Note that the call to dvmCheckInst is done as a tail call. 20226 */ 20227 adrl lr, dvmAsmInstructionStart + (509 * 64) 20228 mov r0, rPC @ arg0 20229 mov r1, rSELF @ arg1 20230 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20231 20232/* ------------------------------ */ 20233 .balign 64 20234.L_ALT_OP_UNUSED_FEFF: /* 0x1fe */ 20235/* File: armv5te/alt_stub.S */ 20236/* 20237 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20238 * any interesting requests and then jump to the real instruction 20239 * handler. Note that the call to dvmCheckInst is done as a tail call. 20240 */ 20241 adrl lr, dvmAsmInstructionStart + (510 * 64) 20242 mov r0, rPC @ arg0 20243 mov r1, rSELF @ arg1 20244 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20245 20246/* ------------------------------ */ 20247 .balign 64 20248.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 20249/* File: armv5te/alt_stub.S */ 20250/* 20251 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20252 * any interesting requests and then jump to the real instruction 20253 * handler. Note that the call to dvmCheckInst is done as a tail call. 20254 */ 20255 adrl lr, dvmAsmInstructionStart + (511 * 64) 20256 mov r0, rPC @ arg0 20257 mov r1, rSELF @ arg1 20258 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20259 20260 .balign 64 20261 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart 20262 .global dvmAsmAltInstructionEnd 20263dvmAsmAltInstructionEnd: 20264/* File: armv5te/footer.S */ 20265 20266/* 20267 * =========================================================================== 20268 * Common subroutines and data 20269 * =========================================================================== 20270 */ 20271 20272 20273 20274 .text 20275 .align 2 20276 20277#if defined(WITH_JIT) 20278#if defined(WITH_SELF_VERIFICATION) 20279 .global dvmJitToInterpPunt 20280dvmJitToInterpPunt: 20281 mov r2,#kSVSPunt @ r2<- interpreter entry point 20282 mov r3, #0 20283 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20284 b jitSVShadowRunEnd @ doesn't return 20285 20286 .global dvmJitToInterpSingleStep 20287dvmJitToInterpSingleStep: 20288 str lr,[rSELF,#offThread_jitResumeNPC] 20289 str r1,[rSELF,#offThread_jitResumeDPC] 20290 mov r2,#kSVSSingleStep @ r2<- interpreter entry point 20291 b jitSVShadowRunEnd @ doesn't return 20292 20293 .global dvmJitToInterpNoChainNoProfile 20294dvmJitToInterpNoChainNoProfile: 20295 mov r0,rPC @ pass our target PC 20296 mov r2,#kSVSNoProfile @ r2<- interpreter entry point 20297 mov r3, #0 @ 0 means !inJitCodeCache 20298 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 20299 b jitSVShadowRunEnd @ doesn't return 20300 20301 .global dvmJitToInterpTraceSelectNoChain 20302dvmJitToInterpTraceSelectNoChain: 20303 mov r0,rPC @ pass our target PC 20304 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20305 mov r3, #0 @ 0 means !inJitCodeCache 20306 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20307 b jitSVShadowRunEnd @ doesn't return 20308 20309 .global dvmJitToInterpTraceSelect 20310dvmJitToInterpTraceSelect: 20311 ldr r0,[lr, #-1] @ pass our target PC 20312 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20313 mov r3, #0 @ 0 means !inJitCodeCache 20314 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20315 b jitSVShadowRunEnd @ doesn't return 20316 20317 .global dvmJitToInterpBackwardBranch 20318dvmJitToInterpBackwardBranch: 20319 ldr r0,[lr, #-1] @ pass our target PC 20320 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 20321 mov r3, #0 @ 0 means !inJitCodeCache 20322 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20323 b jitSVShadowRunEnd @ doesn't return 20324 20325 .global dvmJitToInterpNormal 20326dvmJitToInterpNormal: 20327 ldr r0,[lr, #-1] @ pass our target PC 20328 mov r2,#kSVSNormal @ r2<- interpreter entry point 20329 mov r3, #0 @ 0 means !inJitCodeCache 20330 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20331 b jitSVShadowRunEnd @ doesn't return 20332 20333 .global dvmJitToInterpNoChain 20334dvmJitToInterpNoChain: 20335 mov r0,rPC @ pass our target PC 20336 mov r2,#kSVSNoChain @ r2<- interpreter entry point 20337 mov r3, #0 @ 0 means !inJitCodeCache 20338 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20339 b jitSVShadowRunEnd @ doesn't return 20340#else 20341/* 20342 * Return from the translation cache to the interpreter when the compiler is 20343 * having issues translating/executing a Dalvik instruction. We have to skip 20344 * the code cache lookup otherwise it is possible to indefinitely bouce 20345 * between the interpreter and the code cache if the instruction that fails 20346 * to be compiled happens to be at a trace start. 20347 */ 20348 .global dvmJitToInterpPunt 20349dvmJitToInterpPunt: 20350 mov rPC, r0 20351#if defined(WITH_JIT_TUNING) 20352 mov r0,lr 20353 bl dvmBumpPunt; 20354#endif 20355 EXPORT_PC() 20356 mov r0, #0 20357 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20358 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20359 FETCH_INST() 20360 GET_INST_OPCODE(ip) 20361 GOTO_OPCODE(ip) 20362 20363/* 20364 * Return to the interpreter to handle a single instruction. 20365 * On entry: 20366 * r0 <= PC 20367 * r1 <= PC of resume instruction 20368 * lr <= resume point in translation 20369 */ 20370 .global dvmJitToInterpSingleStep 20371dvmJitToInterpSingleStep: 20372 str lr,[rSELF,#offThread_jitResumeNPC] 20373 str r1,[rSELF,#offThread_jitResumeDPC] 20374 mov r1,#kInterpEntryInstr 20375 @ enum is 4 byte in aapcs-EABI 20376 str r1, [rSELF, #offThread_entryPoint] 20377 mov rPC,r0 20378 EXPORT_PC() 20379 20380 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20381 mov r2,#kJitSingleStep @ Ask for single step and then revert 20382 str r2,[rSELF,#offThread_jitState] 20383 mov r1,#1 @ set changeInterp to bail to debug interp 20384 b common_gotoBail 20385 20386/* 20387 * Return from the translation cache and immediately request 20388 * a translation for the exit target. Commonly used for callees. 20389 */ 20390 .global dvmJitToInterpTraceSelectNoChain 20391dvmJitToInterpTraceSelectNoChain: 20392#if defined(WITH_JIT_TUNING) 20393 bl dvmBumpNoChain 20394#endif 20395 mov r0,rPC 20396 bl dvmJitGetTraceAddr @ Is there a translation? 20397 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20398 mov r1, rPC @ arg1 of translation may need this 20399 mov lr, #0 @ in case target is HANDLER_INTERPRET 20400 cmp r0,#0 @ !0 means translation exists 20401 bxne r0 @ continue native execution if so 20402 b 2f @ branch over to use the interpreter 20403 20404/* 20405 * Return from the translation cache and immediately request 20406 * a translation for the exit target. Commonly used following 20407 * invokes. 20408 */ 20409 .global dvmJitToInterpTraceSelect 20410dvmJitToInterpTraceSelect: 20411 ldr rPC,[lr, #-1] @ get our target PC 20412 add rINST,lr,#-5 @ save start of chain branch 20413 add rINST, #-4 @ .. which is 9 bytes back 20414 mov r0,rPC 20415 bl dvmJitGetTraceAddr @ Is there a translation? 20416 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20417 cmp r0,#0 20418 beq 2f 20419 mov r1,rINST 20420 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 20421 mov r1, rPC @ arg1 of translation may need this 20422 mov lr, #0 @ in case target is HANDLER_INTERPRET 20423 cmp r0,#0 @ successful chain? 20424 bxne r0 @ continue native execution 20425 b toInterpreter @ didn't chain - resume with interpreter 20426 20427/* No translation, so request one if profiling isn't disabled*/ 204282: 20429 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20430 GET_JIT_PROF_TABLE(r0) 20431 FETCH_INST() 20432 cmp r0, #0 20433 movne r2,#kJitTSelectRequestHot @ ask for trace selection 20434 bne common_selectTrace 20435 GET_INST_OPCODE(ip) 20436 GOTO_OPCODE(ip) 20437 20438/* 20439 * Return from the translation cache to the interpreter. 20440 * The return was done with a BLX from thumb mode, and 20441 * the following 32-bit word contains the target rPC value. 20442 * Note that lr (r14) will have its low-order bit set to denote 20443 * its thumb-mode origin. 20444 * 20445 * We'll need to stash our lr origin away, recover the new 20446 * target and then check to see if there is a translation available 20447 * for our new target. If so, we do a translation chain and 20448 * go back to native execution. Otherwise, it's back to the 20449 * interpreter (after treating this entry as a potential 20450 * trace start). 20451 */ 20452 .global dvmJitToInterpNormal 20453dvmJitToInterpNormal: 20454 ldr rPC,[lr, #-1] @ get our target PC 20455 add rINST,lr,#-5 @ save start of chain branch 20456 add rINST,#-4 @ .. which is 9 bytes back 20457#if defined(WITH_JIT_TUNING) 20458 bl dvmBumpNormal 20459#endif 20460 mov r0,rPC 20461 bl dvmJitGetTraceAddr @ Is there a translation? 20462 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20463 cmp r0,#0 20464 beq toInterpreter @ go if not, otherwise do chain 20465 mov r1,rINST 20466 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 20467 mov r1, rPC @ arg1 of translation may need this 20468 mov lr, #0 @ in case target is HANDLER_INTERPRET 20469 cmp r0,#0 @ successful chain? 20470 bxne r0 @ continue native execution 20471 b toInterpreter @ didn't chain - resume with interpreter 20472 20473/* 20474 * Return from the translation cache to the interpreter to do method invocation. 20475 * Check if translation exists for the callee, but don't chain to it. 20476 */ 20477 .global dvmJitToInterpNoChainNoProfile 20478dvmJitToInterpNoChainNoProfile: 20479#if defined(WITH_JIT_TUNING) 20480 bl dvmBumpNoChain 20481#endif 20482 mov r0,rPC 20483 bl dvmJitGetTraceAddr @ Is there a translation? 20484 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20485 mov r1, rPC @ arg1 of translation may need this 20486 mov lr, #0 @ in case target is HANDLER_INTERPRET 20487 cmp r0,#0 20488 bxne r0 @ continue native execution if so 20489 EXPORT_PC() 20490 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20491 FETCH_INST() 20492 GET_INST_OPCODE(ip) @ extract opcode from rINST 20493 GOTO_OPCODE(ip) @ jump to next instruction 20494 20495/* 20496 * Return from the translation cache to the interpreter to do method invocation. 20497 * Check if translation exists for the callee, but don't chain to it. 20498 */ 20499 .global dvmJitToInterpNoChain 20500dvmJitToInterpNoChain: 20501#if defined(WITH_JIT_TUNING) 20502 bl dvmBumpNoChain 20503#endif 20504 mov r0,rPC 20505 bl dvmJitGetTraceAddr @ Is there a translation? 20506 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20507 mov r1, rPC @ arg1 of translation may need this 20508 mov lr, #0 @ in case target is HANDLER_INTERPRET 20509 cmp r0,#0 20510 bxne r0 @ continue native execution if so 20511#endif 20512 20513/* 20514 * No translation, restore interpreter regs and start interpreting. 20515 * rSELF & rFP were preserved in the translated code, and rPC has 20516 * already been restored by the time we get here. We'll need to set 20517 * up rIBASE & rINST, and load the address of the JitTable into r0. 20518 */ 20519toInterpreter: 20520 EXPORT_PC() 20521 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20522 FETCH_INST() 20523 GET_JIT_PROF_TABLE(r0) 20524 @ NOTE: intended fallthrough 20525 20526/* 20527 * Common code to update potential trace start counter, and initiate 20528 * a trace-build if appropriate. On entry, rPC should point to the 20529 * next instruction to execute, and rINST should be already loaded with 20530 * the next opcode word, and r0 holds a pointer to the jit profile 20531 * table (pJitProfTable). 20532 */ 20533common_testUpdateProfile: 20534 cmp r0,#0 20535 GET_INST_OPCODE(ip) 20536 GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 20537 20538common_updateProfile: 20539 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 20540 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 20541 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 20542 GET_INST_OPCODE(ip) 20543 subs r1,r1,#1 @ decrement counter 20544 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 20545 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 20546 20547/* 20548 * Here, we switch to the debug interpreter to request 20549 * trace selection. First, though, check to see if there 20550 * is already a native translation in place (and, if so, 20551 * jump to it now). 20552 */ 20553 20554 GET_JIT_THRESHOLD(r1) 20555 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 20556 EXPORT_PC() 20557 mov r0,rPC 20558 bl dvmJitGetTraceAddr @ r0<- dvmJitGetTraceAddr(rPC) 20559 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20560 mov r1, rPC @ arg1 of translation may need this 20561 mov lr, #0 @ in case target is HANDLER_INTERPRET 20562 cmp r0,#0 20563#if !defined(WITH_SELF_VERIFICATION) 20564 bxne r0 @ jump to the translation 20565 mov r2,#kJitTSelectRequest @ ask for trace selection 20566 @ fall-through to common_selectTrace 20567#else 20568 moveq r2,#kJitTSelectRequest @ ask for trace selection 20569 beq common_selectTrace 20570 /* 20571 * At this point, we have a target translation. However, if 20572 * that translation is actually the interpret-only pseudo-translation 20573 * we want to treat it the same as no translation. 20574 */ 20575 mov r10, r0 @ save target 20576 bl dvmCompilerGetInterpretTemplate 20577 cmp r0, r10 @ special case? 20578 bne jitSVShadowRunStart @ set up self verification shadow space 20579 @ Need to clear the inJitCodeCache flag 20580 mov r3, #0 @ 0 means not in the JIT code cache 20581 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 20582 GET_INST_OPCODE(ip) 20583 GOTO_OPCODE(ip) 20584 /* no return */ 20585#endif 20586 20587/* 20588 * On entry: 20589 * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 20590 */ 20591common_selectTrace: 20592 20593 str r2,[rSELF,#offThread_jitState] 20594 mov r2,#kInterpEntryInstr @ normal entry reason 20595 str r2,[rSELF,#offThread_entryPoint] 20596 mov r1,#1 @ set changeInterp 20597 b common_gotoBail 20598 20599#if defined(WITH_SELF_VERIFICATION) 20600/* 20601 * Save PC and registers to shadow memory for self verification mode 20602 * before jumping to native translation. 20603 * On entry: 20604 * rPC, rFP, rSELF: the values that they should contain 20605 * r10: the address of the target translation. 20606 */ 20607jitSVShadowRunStart: 20608 mov r0,rPC @ r0<- program counter 20609 mov r1,rFP @ r1<- frame pointer 20610 mov r2,rSELF @ r2<- self (Thread) pointer 20611 mov r3,r10 @ r3<- target translation 20612 bl dvmSelfVerificationSaveState @ save registers to shadow space 20613 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 20614 bx r10 @ jump to the translation 20615 20616/* 20617 * Restore PC, registers, and interpreter state to original values 20618 * before jumping back to the interpreter. 20619 */ 20620jitSVShadowRunEnd: 20621 mov r1,rFP @ pass ending fp 20622 mov r3,rSELF @ pass self ptr for convenience 20623 bl dvmSelfVerificationRestoreState @ restore pc and fp values 20624 ldr rPC,[rSELF,#offThread_pc] @ restore PC 20625 ldr rFP,[rSELF,#offThread_fp] @ restore FP 20626 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 20627 cmp r1,#0 @ check for punt condition 20628 beq 1f 20629 mov r2,#kJitSelfVerification @ ask for self verification 20630 str r2,[rSELF,#offThread_jitState] 20631 mov r2,#kInterpEntryInstr @ normal entry reason 20632 str r2,[rSELF,#offThread_entryPoint] 20633 mov r1,#1 @ set changeInterp 20634 b common_gotoBail 20635 206361: @ exit to interpreter without check 20637 EXPORT_PC() 20638 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20639 FETCH_INST() 20640 GET_INST_OPCODE(ip) 20641 GOTO_OPCODE(ip) 20642#endif 20643 20644#endif 20645 20646/* 20647 * Common code when a backward branch is taken. 20648 * 20649 * TODO: we could avoid a branch by just setting r0 and falling through 20650 * into the common_periodicChecks code, and having a test on r0 at the 20651 * end determine if we should return to the caller or update & branch to 20652 * the next instr. 20653 * 20654 * On entry: 20655 * r9 is PC adjustment *in bytes* 20656 */ 20657common_backwardBranch: 20658 mov r0, #kInterpEntryInstr 20659 bl common_periodicChecks 20660#if defined(WITH_JIT) 20661 GET_JIT_PROF_TABLE(r0) 20662 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 20663 cmp r0,#0 20664 bne common_updateProfile 20665 GET_INST_OPCODE(ip) 20666 GOTO_OPCODE(ip) 20667#else 20668 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 20669 GET_INST_OPCODE(ip) @ extract opcode from rINST 20670 GOTO_OPCODE(ip) @ jump to next instruction 20671#endif 20672 20673 20674/* 20675 * Need to see if the thread needs to be suspended or debugger/profiler 20676 * activity has begun. If so, we suspend the thread or side-exit to 20677 * the debug interpreter as appropriate. 20678 * 20679 * The common case is no activity on any of these, so we want to figure 20680 * that out quickly. If something is up, we can then sort out what. 20681 * 20682 * We want to be fast if the VM was built without debugger or profiler 20683 * support, but we also need to recognize that the system is usually 20684 * shipped with both of these enabled. 20685 * 20686 * TODO: reduce this so we're just checking a single location. 20687 * 20688 * On entry: 20689 * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling) 20690 * r9 is trampoline PC adjustment *in bytes* 20691 */ 20692common_periodicChecks: 20693/* TUNING - make this a direct load when interpBreak moved to Thread */ 20694 ldr r1, [rSELF, #offThread_pInterpBreak] @ r3<- &interpBreak 20695 /* speculatively thread-specific suspend count */ 20696 ldr ip, [rSELF, #offThread_suspendCount] 20697 ldr r1, [r1] @ r1<- interpBreak 20698 cmp r1, #0 @ anything unusual? 20699 bxeq lr @ return if not 20700 /* 20701 * One or more interesting events have happened. Figure out what. 20702 * 20703 * r0 still holds the reentry type. 20704 */ 20705 cmp ip, #0 @ want suspend? 20706 beq 3f @ no, must be something else 20707 20708 stmfd sp!, {r0, lr} @ preserve r0 and lr 20709#if defined(WITH_JIT) 20710 /* 20711 * Refresh the Jit's cached copy of profile table pointer. This pointer 20712 * doubles as the Jit's on/off switch. 20713 */ 20714 ldr r3, [rSELF, #offThread_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 20715 mov r0, rSELF @ r0<- self 20716 ldr r3, [r3] @ r3 <- pJitProfTable 20717 EXPORT_PC() @ need for precise GC 20718 str r3, [rSELF, #offThread_pJitProfTable] @ refresh Jit's on/off switch 20719#else 20720 mov r0, rSELF @ r0<- self 20721 EXPORT_PC() @ need for precise GC 20722#endif 20723 bl dvmCheckSuspendPending @ do full check, suspend if necessary 20724 ldmfd sp!, {r0, lr} @ restore r0 and lr 20725 20726 /* 20727 * Reload the interpBreak flags - they may have changed while we 20728 * were suspended. 20729 */ 20730/* TUNING - direct load when InterpBreak moved to Thread */ 20731 ldr r1, [rSELF, #offThread_pInterpBreak] @ r1<- &interpBreak 20732 ldr r1, [r1] @ r1<- interpBreak 207333: 20734 /* 20735 * TODO: this code is too fragile. Need a general mechanism 20736 * to identify what actions to take by submode. Some profiling modes 20737 * (instruction count) need to single-step, while method tracing 20738 * may not. Debugging with breakpoints can run unfettered, but 20739 * source-level single-stepping requires Dalvik singlestepping. 20740 * GC may require a one-shot action and then full-speed resumption. 20741 */ 20742 ands r1, #(kSubModeDebuggerActive | kSubModeEmulatorTrace | kSubModeInstCounting) 20743 bxeq lr @ nothing to do, return 20744 20745 @ debugger/profiler enabled, bail out; self->entryPoint was set above 20746 str r0, [rSELF, #offThread_entryPoint] @ store r0, need for debug/prof 20747 add rPC, rPC, r9 @ update rPC 20748 mov r1, #1 @ "want switch" = true 20749 b common_gotoBail @ side exit 20750 20751 20752/* 20753 * The equivalent of "goto bail", this calls through the "bail handler". 20754 * 20755 * State registers will be saved to the "thread" area before bailing. 20756 * 20757 * On entry: 20758 * r1 is "bool changeInterp", indicating if we want to switch to the 20759 * other interpreter or just bail all the way out 20760 */ 20761common_gotoBail: 20762 SAVE_PC_FP_TO_SELF() @ export state to "thread" 20763 mov r0, rSELF @ r0<- self ptr 20764 b dvmMterpStdBail @ call(self, changeInterp) 20765 20766 @add r1, r1, #1 @ using (boolean+1) 20767 @add r0, rSELF, #offThread_jmpBuf @ r0<- &self->jmpBuf 20768 @bl _longjmp @ does not return 20769 @bl common_abort 20770 20771 20772/* 20773 * Common code for jumbo method invocation. 20774 * NOTE: this adjusts rPC to account for the difference in instruction width. 20775 * As a result, the savedPc in the stack frame will not be wholly accurate. So 20776 * long as that is only used for source file line number calculations, we're 20777 * okay. 20778 * 20779 * On entry: 20780 * r0 is "Method* methodToCall", the method we're trying to call 20781 */ 20782common_invokeMethodJumbo: 20783.LinvokeNewJumbo: 20784 @ prepare to copy args to "outs" area of current frame 20785 add rPC, rPC, #4 @ adjust pc to make return consistent 20786 FETCH(r2, 1) @ r2<- BBBB (arg count) 20787 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 20788 cmp r2, #0 @ no args? 20789 beq .LinvokeArgsDone @ if no args, skip the rest 20790 FETCH(r1, 2) @ r1<- CCCC 20791 b .LinvokeRangeArgs @ handle args like invoke range 20792 20793/* 20794 * Common code for method invocation with range. 20795 * 20796 * On entry: 20797 * r0 is "Method* methodToCall", the method we're trying to call 20798 */ 20799common_invokeMethodRange: 20800.LinvokeNewRange: 20801 @ prepare to copy args to "outs" area of current frame 20802 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 20803 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 20804 beq .LinvokeArgsDone @ if no args, skip the rest 20805 FETCH(r1, 2) @ r1<- CCCC 20806 20807.LinvokeRangeArgs: 20808 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 20809 @ (very few methods have > 10 args; could unroll for common cases) 20810 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 20811 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 208121: ldr r1, [r3], #4 @ val = *fp++ 20813 subs r2, r2, #1 @ count-- 20814 str r1, [r10], #4 @ *outs++ = val 20815 bne 1b @ ...while count != 0 20816 b .LinvokeArgsDone 20817 20818/* 20819 * Common code for method invocation without range. 20820 * 20821 * On entry: 20822 * r0 is "Method* methodToCall", the method we're trying to call 20823 */ 20824common_invokeMethodNoRange: 20825.LinvokeNewNoRange: 20826 @ prepare to copy args to "outs" area of current frame 20827 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 20828 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 20829 FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 20830 beq .LinvokeArgsDone 20831 20832 @ r0=methodToCall, r1=GFED, r2=count, r10=outs 20833.LinvokeNonRange: 20834 rsb r2, r2, #5 @ r2<- 5-r2 20835 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 20836 bl common_abort @ (skipped due to ARM prefetch) 208375: and ip, rINST, #0x0f00 @ isolate A 20838 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 20839 mov r0, r0 @ nop 20840 str r2, [r10, #-4]! @ *--outs = vA 208414: and ip, r1, #0xf000 @ isolate G 20842 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 20843 mov r0, r0 @ nop 20844 str r2, [r10, #-4]! @ *--outs = vG 208453: and ip, r1, #0x0f00 @ isolate F 20846 ldr r2, [rFP, ip, lsr #6] @ r2<- vF 20847 mov r0, r0 @ nop 20848 str r2, [r10, #-4]! @ *--outs = vF 208492: and ip, r1, #0x00f0 @ isolate E 20850 ldr r2, [rFP, ip, lsr #2] @ r2<- vE 20851 mov r0, r0 @ nop 20852 str r2, [r10, #-4]! @ *--outs = vE 208531: and ip, r1, #0x000f @ isolate D 20854 ldr r2, [rFP, ip, lsl #2] @ r2<- vD 20855 mov r0, r0 @ nop 20856 str r2, [r10, #-4]! @ *--outs = vD 208570: @ fall through to .LinvokeArgsDone 20858 20859.LinvokeArgsDone: @ r0=methodToCall 20860 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 20861 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 20862 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 20863 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 20864 @ find space for the new stack frame, check for overflow 20865 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 20866 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 20867 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 20868@ bl common_dumpRegs 20869 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd 20870 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 20871 cmp r3, r9 @ bottom < interpStackEnd? 20872 ldr lr, [rSELF, #offThread_pInterpBreak] 20873 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 20874 blo .LstackOverflow @ yes, this frame will overflow stack 20875 20876 @ set up newSaveArea 20877 ldr lr, [lr] @ lr<- active submodes 20878#ifdef EASY_GDB 20879 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 20880 str ip, [r10, #offStackSaveArea_prevSave] 20881#endif 20882 str rFP, [r10, #offStackSaveArea_prevFrame] 20883 str rPC, [r10, #offStackSaveArea_savedPc] 20884#if defined(WITH_JIT) 20885 mov r9, #0 20886 str r9, [r10, #offStackSaveArea_returnAddr] 20887#endif 20888 ands lr, #kSubModeMethodTrace @ method tracing? 20889 beq 1f @ skip if not 20890 stmfd sp!, {r0-r3} @ preserve r0-r3 20891 mov r1, rSELF 20892 @ r0=methodToCall, r1=rSELF 20893 bl dvmFastMethodTraceEnter 20894 ldmfd sp!, {r0-r3} @ restore r0-r3 208951: 20896 str r0, [r10, #offStackSaveArea_method] 20897 tst r3, #ACC_NATIVE 20898 bne .LinvokeNative 20899 20900 /* 20901 stmfd sp!, {r0-r3} 20902 bl common_printNewline 20903 mov r0, rFP 20904 mov r1, #0 20905 bl dvmDumpFp 20906 ldmfd sp!, {r0-r3} 20907 stmfd sp!, {r0-r3} 20908 mov r0, r1 20909 mov r1, r10 20910 bl dvmDumpFp 20911 bl common_printNewline 20912 ldmfd sp!, {r0-r3} 20913 */ 20914 20915 ldrh r9, [r2] @ r9 <- load INST from new PC 20916 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 20917 mov rPC, r2 @ publish new rPC 20918 20919 @ Update state values for the new method 20920 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST 20921 str r0, [rSELF, #offThread_method] @ self->method = methodToCall 20922 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ... 20923#if defined(WITH_JIT) 20924 GET_JIT_PROF_TABLE(r0) 20925 mov rFP, r1 @ fp = newFp 20926 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 20927 mov rINST, r9 @ publish new rINST 20928 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 20929 cmp r0,#0 20930 bne common_updateProfile 20931 GOTO_OPCODE(ip) @ jump to next instruction 20932#else 20933 mov rFP, r1 @ fp = newFp 20934 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 20935 mov rINST, r9 @ publish new rINST 20936 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 20937 GOTO_OPCODE(ip) @ jump to next instruction 20938#endif 20939 20940.LinvokeNative: 20941 @ Prep for the native call 20942 @ r0=methodToCall, r1=newFp, r10=newSaveArea 20943 ldr lr, [rSELF, #offThread_pInterpBreak] 20944 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->... 20945 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 20946 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 20947 ldr lr, [lr] @ lr<- active submodes 20948 20949 mov r2, r0 @ r2<- methodToCall 20950 mov r0, r1 @ r0<- newFp (points to args) 20951 add r1, rSELF, #offThread_retval @ r1<- &retval 20952 mov r3, rSELF @ arg3<- self 20953 20954#ifdef ASSIST_DEBUGGER 20955 /* insert fake function header to help gdb find the stack frame */ 20956 b .Lskip 20957 .type dalvik_mterp, %function 20958dalvik_mterp: 20959 .fnstart 20960 MTERP_ENTRY1 20961 MTERP_ENTRY2 20962.Lskip: 20963#endif 20964 20965 ands lr, #kSubModeMethodTrace @ method tracing? 20966 bne 330f @ hop if so 20967 mov lr, pc @ set return addr 20968 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 20969220: 20970#if defined(WITH_JIT) 20971 ldr r3, [rSELF, #offThread_ppJitProfTable] @ Refresh Jit's on/off status 20972#endif 20973 20974 @ native return; r10=newSaveArea 20975 @ equivalent to dvmPopJniLocals 20976 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 20977 ldr r1, [rSELF, #offThread_exception] @ check for exception 20978#if defined(WITH_JIT) 20979 ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 20980#endif 20981 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 20982 cmp r1, #0 @ null? 20983 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top 20984#if defined(WITH_JIT) 20985 str r3, [rSELF, #offThread_pJitProfTable] @ refresh cached on/off switch 20986#endif 20987 bne common_exceptionThrown @ no, handle exception 20988 20989 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 20990 GET_INST_OPCODE(ip) @ extract opcode from rINST 20991 GOTO_OPCODE(ip) @ jump to next instruction 20992 20993330: 20994 @ r2=JNIMethod, r6=rSELF 20995 stmfd sp!, {r2,r6} 20996 20997 mov lr, pc @ set return addr 20998 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 20999 21000 @ r0=JNIMethod, r1=rSELF 21001 ldmfd sp!, {r0-r1} 21002 bl dvmFastNativeMethodTraceExit 21003 b 220b 21004 21005.LstackOverflow: @ r0=methodToCall 21006 mov r1, r0 @ r1<- methodToCall 21007 mov r0, rSELF @ r0<- self 21008 bl dvmHandleStackOverflow 21009 b common_exceptionThrown 21010#ifdef ASSIST_DEBUGGER 21011 .fnend 21012 .size dalvik_mterp, .-dalvik_mterp 21013#endif 21014 21015 21016 /* 21017 * Common code for method invocation, calling through "glue code". 21018 * 21019 * TODO: now that we have range and non-range invoke handlers, this 21020 * needs to be split into two. Maybe just create entry points 21021 * that set r9 and jump here? 21022 * 21023 * On entry: 21024 * r0 is "Method* methodToCall", the method we're trying to call 21025 * r9 is "bool methodCallRange", indicating if this is a /range variant 21026 */ 21027 .if 0 21028.LinvokeOld: 21029 sub sp, sp, #8 @ space for args + pad 21030 FETCH(ip, 2) @ ip<- FEDC or CCCC 21031 mov r2, r0 @ A2<- methodToCall 21032 mov r0, rSELF @ A0<- self 21033 SAVE_PC_FP_TO_SELF() @ export state to "self" 21034 mov r1, r9 @ A1<- methodCallRange 21035 mov r3, rINST, lsr #8 @ A3<- AA 21036 str ip, [sp, #0] @ A4<- ip 21037 bl dvmMterp_invokeMethod @ call the C invokeMethod 21038 add sp, sp, #8 @ remove arg area 21039 b common_resumeAfterGlueCall @ continue to next instruction 21040 .endif 21041 21042 21043 21044/* 21045 * Common code for handling a return instruction. 21046 * 21047 * This does not return. 21048 */ 21049common_returnFromMethod: 21050.LreturnNew: 21051 mov r0, #kInterpEntryReturn 21052 mov r9, #0 21053 bl common_periodicChecks 21054 21055 ldr lr, [rSELF, #offThread_pInterpBreak] 21056 SAVEAREA_FROM_FP(r0, rFP) 21057 ldr lr, [lr] @ lr<- active submodes 21058 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 21059 ands lr, #kSubModeMethodTrace @ method tracing? 21060 beq 333f 21061 stmfd sp!, {r0-r3} @ preserve r0-r3 21062 mov r0, rSELF 21063 @ r0=rSELF 21064 bl dvmFastJavaMethodTraceExit 21065 ldmfd sp!, {r0-r3} @ restore r0-r3 21066333: 21067 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 21068 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 21069 @ r2<- method we're returning to 21070 cmp r2, #0 @ is this a break frame? 21071#if defined(WORKAROUND_CORTEX_A9_745320) 21072 /* Don't use conditional loads if the HW defect exists */ 21073 beq 101f 21074 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21075101: 21076#else 21077 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21078#endif 21079 mov r1, #0 @ "want switch" = false 21080 beq common_gotoBail @ break frame, bail out completely 21081 21082 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 21083 str r2, [rSELF, #offThread_method]@ self->method = newSave->method 21084 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 21085 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21086#if defined(WITH_JIT) 21087 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 21088 mov rPC, r9 @ publish new rPC 21089 str r1, [rSELF, #offThread_methodClassDex] 21090 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land 21091 cmp r10, #0 @ caller is compiled code 21092 blxne r10 21093 GET_INST_OPCODE(ip) @ extract opcode from rINST 21094 GOTO_OPCODE(ip) @ jump to next instruction 21095#else 21096 GET_INST_OPCODE(ip) @ extract opcode from rINST 21097 mov rPC, r9 @ publish new rPC 21098 str r1, [rSELF, #offThread_methodClassDex] 21099 GOTO_OPCODE(ip) @ jump to next instruction 21100#endif 21101 21102 /* 21103 * Return handling, calls through "glue code". 21104 */ 21105 .if 0 21106.LreturnOld: 21107 SAVE_PC_FP_TO_SELF() @ export state 21108 mov r0, rSELF @ arg to function 21109 bl dvmMterp_returnFromMethod 21110 b common_resumeAfterGlueCall 21111 .endif 21112 21113 21114/* 21115 * Somebody has thrown an exception. Handle it. 21116 * 21117 * If the exception processing code returns to us (instead of falling 21118 * out of the interpreter), continue with whatever the next instruction 21119 * now happens to be. 21120 * 21121 * This does not return. 21122 */ 21123 .global dvmMterpCommonExceptionThrown 21124dvmMterpCommonExceptionThrown: 21125common_exceptionThrown: 21126.LexceptionNew: 21127 mov r0, #kInterpEntryThrow 21128 mov r9, #0 21129 bl common_periodicChecks 21130 21131 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception 21132 mov r1, rSELF @ r1<- self 21133 mov r0, r9 @ r0<- exception 21134 bl dvmAddTrackedAlloc @ don't let the exception be GCed 21135 mov r3, #0 @ r3<- NULL 21136 str r3, [rSELF, #offThread_exception] @ self->exception = NULL 21137 21138 /* set up args and a local for "&fp" */ 21139 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 21140 str rFP, [sp, #-4]! @ *--sp = fp 21141 mov ip, sp @ ip<- &fp 21142 mov r3, #0 @ r3<- false 21143 str ip, [sp, #-4]! @ *--sp = &fp 21144 ldr r1, [rSELF, #offThread_method] @ r1<- self->method 21145 mov r0, rSELF @ r0<- self 21146 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 21147 mov r2, r9 @ r2<- exception 21148 sub r1, rPC, r1 @ r1<- pc - method->insns 21149 mov r1, r1, asr #1 @ r1<- offset in code units 21150 21151 /* call, r0 gets catchRelPc (a code-unit offset) */ 21152 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 21153 21154 /* fix earlier stack overflow if necessary; may trash rFP */ 21155 ldrb r1, [rSELF, #offThread_stackOverflowed] 21156 cmp r1, #0 @ did we overflow earlier? 21157 beq 1f @ no, skip ahead 21158 mov rFP, r0 @ save relPc result in rFP 21159 mov r0, rSELF @ r0<- self 21160 mov r1, r9 @ r1<- exception 21161 bl dvmCleanupStackOverflow @ call(self) 21162 mov r0, rFP @ restore result 211631: 21164 21165 /* update frame pointer and check result from dvmFindCatchBlock */ 21166 ldr rFP, [sp, #4] @ retrieve the updated rFP 21167 cmp r0, #0 @ is catchRelPc < 0? 21168 add sp, sp, #8 @ restore stack 21169 bmi .LnotCaughtLocally 21170 21171 /* adjust locals to match self->curFrame and updated PC */ 21172 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 21173 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 21174 str r1, [rSELF, #offThread_method] @ self->method = new method 21175 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 21176 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 21177 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 21178 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 21179 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth... 21180 21181 /* release the tracked alloc on the exception */ 21182 mov r0, r9 @ r0<- exception 21183 mov r1, rSELF @ r1<- self 21184 bl dvmReleaseTrackedAlloc @ release the exception 21185 21186 /* restore the exception if the handler wants it */ 21187 FETCH_INST() @ load rINST from rPC 21188 GET_INST_OPCODE(ip) @ extract opcode from rINST 21189 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 21190 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception 21191 GOTO_OPCODE(ip) @ jump to next instruction 21192 21193.LnotCaughtLocally: @ r9=exception 21194 /* fix stack overflow if necessary */ 21195 ldrb r1, [rSELF, #offThread_stackOverflowed] 21196 cmp r1, #0 @ did we overflow earlier? 21197 movne r0, rSELF @ if yes: r0<- self 21198 movne r1, r9 @ if yes: r1<- exception 21199 blne dvmCleanupStackOverflow @ if yes: call(self) 21200 21201 @ may want to show "not caught locally" debug messages here 21202#if DVM_SHOW_EXCEPTION >= 2 21203 /* call __android_log_print(prio, tag, format, ...) */ 21204 /* "Exception %s from %s:%d not caught locally" */ 21205 @ dvmLineNumFromPC(method, pc - method->insns) 21206 ldr r0, [rSELF, #offThread_method] 21207 ldr r1, [r0, #offMethod_insns] 21208 sub r1, rPC, r1 21209 asr r1, r1, #1 21210 bl dvmLineNumFromPC 21211 str r0, [sp, #-4]! 21212 @ dvmGetMethodSourceFile(method) 21213 ldr r0, [rSELF, #offThread_method] 21214 bl dvmGetMethodSourceFile 21215 str r0, [sp, #-4]! 21216 @ exception->clazz->descriptor 21217 ldr r3, [r9, #offObject_clazz] 21218 ldr r3, [r3, #offClassObject_descriptor] 21219 @ 21220 ldr r2, strExceptionNotCaughtLocally 21221 ldr r1, strLogTag 21222 mov r0, #3 @ LOG_DEBUG 21223 bl __android_log_print 21224#endif 21225 str r9, [rSELF, #offThread_exception] @ restore exception 21226 mov r0, r9 @ r0<- exception 21227 mov r1, rSELF @ r1<- self 21228 bl dvmReleaseTrackedAlloc @ release the exception 21229 mov r1, #0 @ "want switch" = false 21230 b common_gotoBail @ bail out 21231 21232 21233 /* 21234 * Exception handling, calls through "glue code". 21235 */ 21236 .if 0 21237.LexceptionOld: 21238 SAVE_PC_FP_TO_SELF() @ export state 21239 mov r0, rSELF @ arg to function 21240 bl dvmMterp_exceptionThrown 21241 b common_resumeAfterGlueCall 21242 .endif 21243 21244 21245/* 21246 * After returning from a "glued" function, pull out the updated 21247 * values and start executing at the next instruction. 21248 */ 21249common_resumeAfterGlueCall: 21250 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread 21251 FETCH_INST() @ load rINST from rPC 21252 GET_INST_OPCODE(ip) @ extract opcode from rINST 21253 GOTO_OPCODE(ip) @ jump to next instruction 21254 21255/* 21256 * Invalid array index. Note that our calling convention is strange; we use r1 21257 * and r3 because those just happen to be the registers all our callers are 21258 * using. We move r3 before calling the C function, but r1 happens to match. 21259 * r1: index 21260 * r3: size 21261 */ 21262common_errArrayIndex: 21263 EXPORT_PC() 21264 mov r0, r3 21265 bl dvmThrowArrayIndexOutOfBoundsException 21266 b common_exceptionThrown 21267 21268/* 21269 * Integer divide or mod by zero. 21270 */ 21271common_errDivideByZero: 21272 EXPORT_PC() 21273 ldr r0, strDivideByZero 21274 bl dvmThrowArithmeticException 21275 b common_exceptionThrown 21276 21277/* 21278 * Attempt to allocate an array with a negative size. 21279 * On entry: length in r1 21280 */ 21281common_errNegativeArraySize: 21282 EXPORT_PC() 21283 mov r0, r1 @ arg0 <- len 21284 bl dvmThrowNegativeArraySizeException @ (len) 21285 b common_exceptionThrown 21286 21287/* 21288 * Invocation of a non-existent method. 21289 * On entry: method name in r1 21290 */ 21291common_errNoSuchMethod: 21292 EXPORT_PC() 21293 mov r0, r1 21294 bl dvmThrowNoSuchMethodError 21295 b common_exceptionThrown 21296 21297/* 21298 * We encountered a null object when we weren't expecting one. We 21299 * export the PC, throw a NullPointerException, and goto the exception 21300 * processing code. 21301 */ 21302common_errNullObject: 21303 EXPORT_PC() 21304 mov r0, #0 21305 bl dvmThrowNullPointerException 21306 b common_exceptionThrown 21307 21308/* 21309 * For debugging, cause an immediate fault. The source address will 21310 * be in lr (use a bl instruction to jump here). 21311 */ 21312common_abort: 21313 ldr pc, .LdeadFood 21314.LdeadFood: 21315 .word 0xdeadf00d 21316 21317/* 21318 * Spit out a "we were here", preserving all registers. (The attempt 21319 * to save ip won't work, but we need to save an even number of 21320 * registers for EABI 64-bit stack alignment.) 21321 */ 21322 .macro SQUEAK num 21323common_squeak\num: 21324 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21325 ldr r0, strSqueak 21326 mov r1, #\num 21327 bl printf 21328 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21329 bx lr 21330 .endm 21331 21332 SQUEAK 0 21333 SQUEAK 1 21334 SQUEAK 2 21335 SQUEAK 3 21336 SQUEAK 4 21337 SQUEAK 5 21338 21339/* 21340 * Spit out the number in r0, preserving registers. 21341 */ 21342common_printNum: 21343 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21344 mov r1, r0 21345 ldr r0, strSqueak 21346 bl printf 21347 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21348 bx lr 21349 21350/* 21351 * Print a newline, preserving registers. 21352 */ 21353common_printNewline: 21354 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21355 ldr r0, strNewline 21356 bl printf 21357 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21358 bx lr 21359 21360 /* 21361 * Print the 32-bit quantity in r0 as a hex value, preserving registers. 21362 */ 21363common_printHex: 21364 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21365 mov r1, r0 21366 ldr r0, strPrintHex 21367 bl printf 21368 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21369 bx lr 21370 21371/* 21372 * Print the 64-bit quantity in r0-r1, preserving registers. 21373 */ 21374common_printLong: 21375 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21376 mov r3, r1 21377 mov r2, r0 21378 ldr r0, strPrintLong 21379 bl printf 21380 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21381 bx lr 21382 21383/* 21384 * Print full method info. Pass the Method* in r0. Preserves regs. 21385 */ 21386common_printMethod: 21387 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21388 bl dvmMterpPrintMethod 21389 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21390 bx lr 21391 21392/* 21393 * Call a C helper function that dumps regs and possibly some 21394 * additional info. Requires the C function to be compiled in. 21395 */ 21396 .if 0 21397common_dumpRegs: 21398 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21399 bl dvmMterpDumpArmRegs 21400 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21401 bx lr 21402 .endif 21403 21404#if 0 21405/* 21406 * Experiment on VFP mode. 21407 * 21408 * uint32_t setFPSCR(uint32_t val, uint32_t mask) 21409 * 21410 * Updates the bits specified by "mask", setting them to the values in "val". 21411 */ 21412setFPSCR: 21413 and r0, r0, r1 @ make sure no stray bits are set 21414 fmrx r2, fpscr @ get VFP reg 21415 mvn r1, r1 @ bit-invert mask 21416 and r2, r2, r1 @ clear masked bits 21417 orr r2, r2, r0 @ set specified bits 21418 fmxr fpscr, r2 @ set VFP reg 21419 mov r0, r2 @ return new value 21420 bx lr 21421 21422 .align 2 21423 .global dvmConfigureFP 21424 .type dvmConfigureFP, %function 21425dvmConfigureFP: 21426 stmfd sp!, {ip, lr} 21427 /* 0x03000000 sets DN/FZ */ 21428 /* 0x00009f00 clears the six exception enable flags */ 21429 bl common_squeak0 21430 mov r0, #0x03000000 @ r0<- 0x03000000 21431 add r1, r0, #0x9f00 @ r1<- 0x03009f00 21432 bl setFPSCR 21433 ldmfd sp!, {ip, pc} 21434#endif 21435 21436 21437/* 21438 * String references, must be close to the code that uses them. 21439 */ 21440 .align 2 21441strDivideByZero: 21442 .word .LstrDivideByZero 21443strLogTag: 21444 .word .LstrLogTag 21445strExceptionNotCaughtLocally: 21446 .word .LstrExceptionNotCaughtLocally 21447 21448strNewline: 21449 .word .LstrNewline 21450strSqueak: 21451 .word .LstrSqueak 21452strPrintHex: 21453 .word .LstrPrintHex 21454strPrintLong: 21455 .word .LstrPrintLong 21456 21457/* 21458 * Zero-terminated ASCII string data. 21459 * 21460 * On ARM we have two choices: do like gcc does, and LDR from a .word 21461 * with the address, or use an ADR pseudo-op to get the address 21462 * directly. ADR saves 4 bytes and an indirection, but it's using a 21463 * PC-relative addressing mode and hence has a limited range, which 21464 * makes it not work well with mergeable string sections. 21465 */ 21466 .section .rodata.str1.4,"aMS",%progbits,1 21467 21468.LstrBadEntryPoint: 21469 .asciz "Bad entry point %d\n" 21470.LstrFilledNewArrayNotImpl: 21471 .asciz "filled-new-array only implemented for objects and 'int'" 21472.LstrDivideByZero: 21473 .asciz "divide by zero" 21474.LstrLogTag: 21475 .asciz "mterp" 21476.LstrExceptionNotCaughtLocally: 21477 .asciz "Exception %s from %s:%d not caught locally\n" 21478 21479.LstrNewline: 21480 .asciz "\n" 21481.LstrSqueak: 21482 .asciz "<%d>" 21483.LstrPrintHex: 21484 .asciz "<0x%x>" 21485.LstrPrintLong: 21486 .asciz "<%lld>" 21487 21488