InterpAsm-armv7-a.S revision 3d054be0780e2bee9553711d409608495cc2c19e
1/* 2 * This file was generated automatically by gen-mterp.py for 'armv7-a'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: armv5te/header.S */ 8/* 9 * Copyright (C) 2008 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 * ARMv5 definitions and declarations. 26 */ 27 28/* 29ARM EABI general notes: 30 31r0-r3 hold first 4 args to a method; they are not preserved across method calls 32r4-r8 are available for general use 33r9 is given special treatment in some situations, but not for us 34r10 (sl) seems to be generally available 35r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36r12 (ip) is scratch -- not preserved across method calls 37r13 (sp) should be managed carefully in case a signal arrives 38r14 (lr) must be preserved 39r15 (pc) can be tinkered with directly 40 41r0 holds returns of <= 4 bytes 42r0-r1 hold returns of 8 bytes, low word in r0 43 44Callee must save/restore r4+ (except r12) if it modifies them. If VFP 45is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46s0-s15 (d0-d7, q0-a3) do not need to be. 47 48Stack is "full descending". Only the arguments that don't fit in the first 4 49registers are placed on the stack. "sp" points at the first stacked argument 50(i.e. the 5th arg). 51 52VFP: single-precision results in s0, double-precision results in d0. 53 54In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 5564-bit quantities (long long, double) must be 64-bit aligned. 56*/ 57 58/* 59Mterp and ARM notes: 60 61The following registers have fixed assignments: 62 63 reg nick purpose 64 r4 rPC interpreted program counter, used for fetching instructions 65 r5 rFP interpreted frame pointer, used for accessing locals and args 66 r6 rSELF self (Thread) pointer 67 r7 rINST first 16-bit code unit of current instruction 68 r8 rIBASE interpreted instruction base pointer, used for computed goto 69 70Macros are provided for common operations. Each macro MUST emit only 71one instruction to make instruction-counting easier. They MUST NOT alter 72unspecified registers or condition codes. 73*/ 74 75/* single-purpose registers, given names for clarity */ 76#define rPC r4 77#define rFP r5 78#define rSELF r6 79#define rINST r7 80#define rIBASE r8 81 82/* save/restore the PC and/or FP from the thread struct */ 83#define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc] 84#define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc] 85#define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_fp] 86#define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_fp] 87#define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP} 88#define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP} 89 90/* 91 * "export" the PC to the stack frame, f/b/o future exception objects. Must 92 * be done *before* something throws. 93 * 94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96 * 97 * It's okay to do this more than once. 98 */ 99#define EXPORT_PC() \ 100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101 102/* 103 * Given a frame pointer, find the stack save area. 104 * 105 * In C this is "((StackSaveArea*)(_fp) -1)". 106 */ 107#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108 sub _reg, _fpreg, #sizeofStackSaveArea 109 110/* 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112 */ 113#define FETCH_INST() ldrh rINST, [rPC] 114 115/* 116 * Fetch the next instruction from the specified offset. Advances rPC 117 * to point to the next instruction. "_count" is in 16-bit code units. 118 * 119 * Because of the limited size of immediate constants on ARM, this is only 120 * suitable for small forward movements (i.e. don't try to implement "goto" 121 * with this). 122 * 123 * This must come AFTER anything that can throw an exception, or the 124 * exception catch may miss. (This also implies that it must come after 125 * EXPORT_PC().) 126 */ 127#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 128 129/* 130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132 */ 133#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134 ldrh _dreg, [_sreg, #(_count*2)]! 135 136/* 137 * Fetch the next instruction from an offset specified by _reg. Updates 138 * rPC to point to the next instruction. "_reg" must specify the distance 139 * in bytes, *not* 16-bit code units, and may be a signed value. 140 * 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 142 * bits that hold the shift distance are used for the half/byte/sign flags. 143 * In some cases we can pre-double _reg for free, so we require a byte offset 144 * here. 145 */ 146#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147 148/* 149 * Fetch a half-word code unit from an offset past the current PC. The 150 * "_count" value is in 16-bit code units. Does not advance rPC. 151 * 152 * The "_S" variant works the same but treats the value as signed. 153 */ 154#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 155#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 156 157/* 158 * Fetch one byte from an offset past the current PC. Pass in the same 159 * "_count" as you would for FETCH, and an additional 0/1 indicating which 160 * byte of the halfword you want (lo/hi). 161 */ 162#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 163 164/* 165 * Put the instruction's opcode field into the specified register. 166 */ 167#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168 169/* 170 * Put the prefetched instruction's opcode field into the specified register. 171 */ 172#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173 174/* 175 * Begin executing the opcode in _reg. Because this only jumps within the 176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177 */ 178#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 180#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 181 182/* 183 * Get/set the 32-bit value from a Dalvik register. 184 */ 185#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 186#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 187 188#if defined(WITH_JIT) 189#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rSELF,#offThread_pJitProfTable] 190#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rSELF,#offThread_jitThreshold] 191#endif 192 193/* 194 * Convert a virtual register index into an address. 195 */ 196#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 197 add _reg, rFP, _vreg, lsl #2 198 199/* 200 * This is a #include, not a %include, because we want the C pre-processor 201 * to expand the macros into assembler assignment statements. 202 */ 203#include "../common/asm-constants.h" 204 205#if defined(WITH_JIT) 206#include "../common/jit-config.h" 207#endif 208 209/* File: armv7-a/platform.S */ 210/* 211 * =========================================================================== 212 * CPU-version-specific defines 213 * =========================================================================== 214 */ 215 216#if !defined(ANDROID_SMP) 217# error "Must define ANDROID_SMP" 218#endif 219 220/* 221 * Macro for data memory barrier. 222 */ 223.macro SMP_DMB 224#if ANDROID_SMP != 0 225 dmb 226#else 227 /* not SMP */ 228#endif 229.endm 230 231/* 232 * Macro for data memory barrier (store/store variant). 233 */ 234.macro SMP_DMB_ST 235#if ANDROID_SMP != 0 236 dmb st 237#else 238 /* not SMP */ 239#endif 240.endm 241 242/* File: armv5te/entry.S */ 243/* 244 * Copyright (C) 2008 The Android Open Source Project 245 * 246 * Licensed under the Apache License, Version 2.0 (the "License"); 247 * you may not use this file except in compliance with the License. 248 * You may obtain a copy of the License at 249 * 250 * http://www.apache.org/licenses/LICENSE-2.0 251 * 252 * Unless required by applicable law or agreed to in writing, software 253 * distributed under the License is distributed on an "AS IS" BASIS, 254 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 255 * See the License for the specific language governing permissions and 256 * limitations under the License. 257 */ 258/* 259 * Interpreter entry point. 260 */ 261 262/* 263 * We don't have formal stack frames, so gdb scans upward in the code 264 * to find the start of the function (a label with the %function type), 265 * and then looks at the next few instructions to figure out what 266 * got pushed onto the stack. From this it figures out how to restore 267 * the registers, including PC, for the previous stack frame. If gdb 268 * sees a non-function label, it stops scanning, so either we need to 269 * have nothing but assembler-local labels between the entry point and 270 * the break, or we need to fake it out. 271 * 272 * When this is defined, we add some stuff to make gdb less confused. 273 */ 274#define ASSIST_DEBUGGER 1 275 276 .text 277 .align 2 278 .global dvmMterpStdRun 279 .type dvmMterpStdRun, %function 280 281/* 282 * On entry: 283 * r0 Thread* self 284 * 285 * This function returns a boolean "changeInterp" value. The return comes 286 * via a call to dvmMterpStdBail(). 287 */ 288dvmMterpStdRun: 289#define MTERP_ENTRY1 \ 290 .save {r4-r10,fp,lr}; \ 291 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 292#define MTERP_ENTRY2 \ 293 .pad #4; \ 294 sub sp, sp, #4 @ align 64 295 296 .fnstart 297 MTERP_ENTRY1 298 MTERP_ENTRY2 299 300 /* save stack pointer, add magic word for debuggerd */ 301 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return 302 303 /* set up "named" registers, figure out entry point */ 304 mov rSELF, r0 @ set rSELF 305 ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI 306 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread" 307 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE 308 cmp r1, #kInterpEntryInstr @ usual case? 309 bne .Lnot_instr @ no, handle it 310 311#if defined(WITH_JIT) 312.LentryInstr: 313 /* Entry is always a possible trace start */ 314 GET_JIT_PROF_TABLE(r0) 315 FETCH_INST() 316 mov r1, #0 @ prepare the value for the new state 317 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 318 cmp r0,#0 @ is profiling disabled? 319#if !defined(WITH_SELF_VERIFICATION) 320 bne common_updateProfile @ profiling is enabled 321#else 322 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state 323 beq 1f @ profiling is disabled 324 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 325 cmp r3, #kSVSTraceSelect @ hot trace following? 326 moveq r2,#kJitTSelectRequestHot @ ask for trace selection 327 beq common_selectTrace @ go build the trace 328 cmp r3, #kSVSNoProfile @ don't profile the next instruction? 329 beq 1f @ intrepret the next instruction 330 b common_updateProfile @ collect profiles 331#endif 3321: 333 GET_INST_OPCODE(ip) 334 GOTO_OPCODE(ip) 335#else 336 /* start executing the instruction at rPC */ 337 FETCH_INST() @ load rINST from rPC 338 GET_INST_OPCODE(ip) @ extract opcode from rINST 339 GOTO_OPCODE(ip) @ jump to next instruction 340#endif 341 342.Lnot_instr: 343 cmp r1, #kInterpEntryReturn @ were we returning from a method? 344 beq common_returnFromMethod 345 346.Lnot_return: 347 cmp r1, #kInterpEntryThrow @ were we throwing an exception? 348 beq common_exceptionThrown 349 350#if defined(WITH_JIT) 351.Lnot_throw: 352 ldr r10,[rSELF, #offThread_jitResumeNPC] 353 ldr r2,[rSELF, #offThread_jitResumeDPC] 354 cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 355 bne .Lbad_arg 356 cmp rPC,r2 357 bne .LentryInstr @ must have branched, don't resume 358#if defined(WITH_SELF_VERIFICATION) 359 @ self->entryPoint will be set in dvmSelfVerificationSaveState 360 b jitSVShadowRunStart @ re-enter the translation after the 361 @ single-stepped instruction 362 @noreturn 363#endif 364 mov r1, #kInterpEntryInstr 365 str r1, [rSELF, #offThread_entryPoint] 366 bx r10 @ re-enter the translation 367#endif 368 369.Lbad_arg: 370 ldr r0, strBadEntryPoint 371 @ r1 holds value of entryPoint 372 bl printf 373 bl dvmAbort 374 .fnend 375 .size dvmMterpStdRun, .-dvmMterpStdRun 376 377 378 .global dvmMterpStdBail 379 .type dvmMterpStdBail, %function 380 381/* 382 * Restore the stack pointer and PC from the save point established on entry. 383 * This is essentially the same as a longjmp, but should be cheaper. The 384 * last instruction causes us to return to whoever called dvmMterpStdRun. 385 * 386 * We pushed some registers on the stack in dvmMterpStdRun, then saved 387 * SP and LR. Here we restore SP, restore the registers, and then restore 388 * LR to PC. 389 * 390 * On entry: 391 * r0 Thread* self 392 * r1 bool changeInterp 393 */ 394dvmMterpStdBail: 395 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP 396 mov r0, r1 @ return the changeInterp value 397 add sp, sp, #4 @ un-align 64 398 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return 399 400 401/* 402 * String references. 403 */ 404strBadEntryPoint: 405 .word .LstrBadEntryPoint 406 407 408 .global dvmAsmInstructionStart 409 .type dvmAsmInstructionStart, %function 410dvmAsmInstructionStart = .L_OP_NOP 411 .text 412 413/* ------------------------------ */ 414 .balign 64 415.L_OP_NOP: /* 0x00 */ 416/* File: armv5te/OP_NOP.S */ 417 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 418 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 419 GOTO_OPCODE(ip) @ execute it 420 421#ifdef ASSIST_DEBUGGER 422 /* insert fake function header to help gdb find the stack frame */ 423 .type dalvik_inst, %function 424dalvik_inst: 425 .fnstart 426 MTERP_ENTRY1 427 MTERP_ENTRY2 428 .fnend 429#endif 430 431/* ------------------------------ */ 432 .balign 64 433.L_OP_MOVE: /* 0x01 */ 434/* File: armv6t2/OP_MOVE.S */ 435 /* for move, move-object, long-to-int */ 436 /* op vA, vB */ 437 mov r1, rINST, lsr #12 @ r1<- B from 15:12 438 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 439 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 440 GET_VREG(r2, r1) @ r2<- fp[B] 441 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 442 SET_VREG(r2, r0) @ fp[A]<- r2 443 GOTO_OPCODE(ip) @ execute next instruction 444 445/* ------------------------------ */ 446 .balign 64 447.L_OP_MOVE_FROM16: /* 0x02 */ 448/* File: armv5te/OP_MOVE_FROM16.S */ 449 /* for: move/from16, move-object/from16 */ 450 /* op vAA, vBBBB */ 451 FETCH(r1, 1) @ r1<- BBBB 452 mov r0, rINST, lsr #8 @ r0<- AA 453 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 454 GET_VREG(r2, r1) @ r2<- fp[BBBB] 455 GET_INST_OPCODE(ip) @ extract opcode from rINST 456 SET_VREG(r2, r0) @ fp[AA]<- r2 457 GOTO_OPCODE(ip) @ jump to next instruction 458 459/* ------------------------------ */ 460 .balign 64 461.L_OP_MOVE_16: /* 0x03 */ 462/* File: armv5te/OP_MOVE_16.S */ 463 /* for: move/16, move-object/16 */ 464 /* op vAAAA, vBBBB */ 465 FETCH(r1, 2) @ r1<- BBBB 466 FETCH(r0, 1) @ r0<- AAAA 467 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 468 GET_VREG(r2, r1) @ r2<- fp[BBBB] 469 GET_INST_OPCODE(ip) @ extract opcode from rINST 470 SET_VREG(r2, r0) @ fp[AAAA]<- r2 471 GOTO_OPCODE(ip) @ jump to next instruction 472 473/* ------------------------------ */ 474 .balign 64 475.L_OP_MOVE_WIDE: /* 0x04 */ 476/* File: armv6t2/OP_MOVE_WIDE.S */ 477 /* move-wide vA, vB */ 478 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 479 mov r3, rINST, lsr #12 @ r3<- B 480 ubfx r2, rINST, #8, #4 @ r2<- A 481 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 482 add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 483 ldmia r3, {r0-r1} @ r0/r1<- fp[B] 484 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 485 GET_INST_OPCODE(ip) @ extract opcode from rINST 486 stmia r2, {r0-r1} @ fp[A]<- r0/r1 487 GOTO_OPCODE(ip) @ jump to next instruction 488 489/* ------------------------------ */ 490 .balign 64 491.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 492/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 493 /* move-wide/from16 vAA, vBBBB */ 494 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 495 FETCH(r3, 1) @ r3<- BBBB 496 mov r2, rINST, lsr #8 @ r2<- AA 497 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 498 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 499 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 501 GET_INST_OPCODE(ip) @ extract opcode from rINST 502 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 503 GOTO_OPCODE(ip) @ jump to next instruction 504 505/* ------------------------------ */ 506 .balign 64 507.L_OP_MOVE_WIDE_16: /* 0x06 */ 508/* File: armv5te/OP_MOVE_WIDE_16.S */ 509 /* move-wide/16 vAAAA, vBBBB */ 510 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 511 FETCH(r3, 2) @ r3<- BBBB 512 FETCH(r2, 1) @ r2<- AAAA 513 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 514 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 515 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 516 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 517 GET_INST_OPCODE(ip) @ extract opcode from rINST 518 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 519 GOTO_OPCODE(ip) @ jump to next instruction 520 521/* ------------------------------ */ 522 .balign 64 523.L_OP_MOVE_OBJECT: /* 0x07 */ 524/* File: armv5te/OP_MOVE_OBJECT.S */ 525/* File: armv5te/OP_MOVE.S */ 526 /* for move, move-object, long-to-int */ 527 /* op vA, vB */ 528 mov r1, rINST, lsr #12 @ r1<- B from 15:12 529 mov r0, rINST, lsr #8 @ r0<- A from 11:8 530 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 531 GET_VREG(r2, r1) @ r2<- fp[B] 532 and r0, r0, #15 533 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 534 SET_VREG(r2, r0) @ fp[A]<- r2 535 GOTO_OPCODE(ip) @ execute next instruction 536 537 538/* ------------------------------ */ 539 .balign 64 540.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 541/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 542/* File: armv5te/OP_MOVE_FROM16.S */ 543 /* for: move/from16, move-object/from16 */ 544 /* op vAA, vBBBB */ 545 FETCH(r1, 1) @ r1<- BBBB 546 mov r0, rINST, lsr #8 @ r0<- AA 547 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 548 GET_VREG(r2, r1) @ r2<- fp[BBBB] 549 GET_INST_OPCODE(ip) @ extract opcode from rINST 550 SET_VREG(r2, r0) @ fp[AA]<- r2 551 GOTO_OPCODE(ip) @ jump to next instruction 552 553 554/* ------------------------------ */ 555 .balign 64 556.L_OP_MOVE_OBJECT_16: /* 0x09 */ 557/* File: armv5te/OP_MOVE_OBJECT_16.S */ 558/* File: armv5te/OP_MOVE_16.S */ 559 /* for: move/16, move-object/16 */ 560 /* op vAAAA, vBBBB */ 561 FETCH(r1, 2) @ r1<- BBBB 562 FETCH(r0, 1) @ r0<- AAAA 563 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 564 GET_VREG(r2, r1) @ r2<- fp[BBBB] 565 GET_INST_OPCODE(ip) @ extract opcode from rINST 566 SET_VREG(r2, r0) @ fp[AAAA]<- r2 567 GOTO_OPCODE(ip) @ jump to next instruction 568 569 570/* ------------------------------ */ 571 .balign 64 572.L_OP_MOVE_RESULT: /* 0x0a */ 573/* File: armv5te/OP_MOVE_RESULT.S */ 574 /* for: move-result, move-result-object */ 575 /* op vAA */ 576 mov r2, rINST, lsr #8 @ r2<- AA 577 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 578 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 579 GET_INST_OPCODE(ip) @ extract opcode from rINST 580 SET_VREG(r0, r2) @ fp[AA]<- r0 581 GOTO_OPCODE(ip) @ jump to next instruction 582 583/* ------------------------------ */ 584 .balign 64 585.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 586/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 587 /* move-result-wide vAA */ 588 mov r2, rINST, lsr #8 @ r2<- AA 589 add r3, rSELF, #offThread_retval @ r3<- &self->retval 590 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 591 ldmia r3, {r0-r1} @ r0/r1<- retval.j 592 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 593 GET_INST_OPCODE(ip) @ extract opcode from rINST 594 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 595 GOTO_OPCODE(ip) @ jump to next instruction 596 597/* ------------------------------ */ 598 .balign 64 599.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 600/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 601/* File: armv5te/OP_MOVE_RESULT.S */ 602 /* for: move-result, move-result-object */ 603 /* op vAA */ 604 mov r2, rINST, lsr #8 @ r2<- AA 605 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 606 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 607 GET_INST_OPCODE(ip) @ extract opcode from rINST 608 SET_VREG(r0, r2) @ fp[AA]<- r0 609 GOTO_OPCODE(ip) @ jump to next instruction 610 611 612/* ------------------------------ */ 613 .balign 64 614.L_OP_MOVE_EXCEPTION: /* 0x0d */ 615/* File: armv5te/OP_MOVE_EXCEPTION.S */ 616 /* move-exception vAA */ 617 mov r2, rINST, lsr #8 @ r2<- AA 618 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass 619 mov r1, #0 @ r1<- 0 620 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 621 SET_VREG(r3, r2) @ fp[AA]<- exception obj 622 GET_INST_OPCODE(ip) @ extract opcode from rINST 623 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass 624 GOTO_OPCODE(ip) @ jump to next instruction 625 626/* ------------------------------ */ 627 .balign 64 628.L_OP_RETURN_VOID: /* 0x0e */ 629/* File: armv5te/OP_RETURN_VOID.S */ 630 b common_returnFromMethod 631 632/* ------------------------------ */ 633 .balign 64 634.L_OP_RETURN: /* 0x0f */ 635/* File: armv5te/OP_RETURN.S */ 636 /* 637 * Return a 32-bit value. Copies the return value into the "thread" 638 * structure, then jumps to the return handler. 639 * 640 * for: return, return-object 641 */ 642 /* op vAA */ 643 mov r2, rINST, lsr #8 @ r2<- AA 644 GET_VREG(r0, r2) @ r0<- vAA 645 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 646 b common_returnFromMethod 647 648/* ------------------------------ */ 649 .balign 64 650.L_OP_RETURN_WIDE: /* 0x10 */ 651/* File: armv5te/OP_RETURN_WIDE.S */ 652 /* 653 * Return a 64-bit value. Copies the return value into the "thread" 654 * structure, then jumps to the return handler. 655 */ 656 /* return-wide vAA */ 657 mov r2, rINST, lsr #8 @ r2<- AA 658 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 659 add r3, rSELF, #offThread_retval @ r3<- &self->retval 660 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 661 stmia r3, {r0-r1} @ retval<- r0/r1 662 b common_returnFromMethod 663 664/* ------------------------------ */ 665 .balign 64 666.L_OP_RETURN_OBJECT: /* 0x11 */ 667/* File: armv5te/OP_RETURN_OBJECT.S */ 668/* File: armv5te/OP_RETURN.S */ 669 /* 670 * Return a 32-bit value. Copies the return value into the "thread" 671 * structure, then jumps to the return handler. 672 * 673 * for: return, return-object 674 */ 675 /* op vAA */ 676 mov r2, rINST, lsr #8 @ r2<- AA 677 GET_VREG(r0, r2) @ r0<- vAA 678 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 679 b common_returnFromMethod 680 681 682/* ------------------------------ */ 683 .balign 64 684.L_OP_CONST_4: /* 0x12 */ 685/* File: armv6t2/OP_CONST_4.S */ 686 /* const/4 vA, #+B */ 687 mov r1, rINST, lsl #16 @ r1<- Bxxx0000 688 ubfx r0, rINST, #8, #4 @ r0<- A 689 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 690 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 691 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 692 SET_VREG(r1, r0) @ fp[A]<- r1 693 GOTO_OPCODE(ip) @ execute next instruction 694 695/* ------------------------------ */ 696 .balign 64 697.L_OP_CONST_16: /* 0x13 */ 698/* File: armv5te/OP_CONST_16.S */ 699 /* const/16 vAA, #+BBBB */ 700 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 701 mov r3, rINST, lsr #8 @ r3<- AA 702 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 703 SET_VREG(r0, r3) @ vAA<- r0 704 GET_INST_OPCODE(ip) @ extract opcode from rINST 705 GOTO_OPCODE(ip) @ jump to next instruction 706 707/* ------------------------------ */ 708 .balign 64 709.L_OP_CONST: /* 0x14 */ 710/* File: armv5te/OP_CONST.S */ 711 /* const vAA, #+BBBBbbbb */ 712 mov r3, rINST, lsr #8 @ r3<- AA 713 FETCH(r0, 1) @ r0<- bbbb (low) 714 FETCH(r1, 2) @ r1<- BBBB (high) 715 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 716 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 717 GET_INST_OPCODE(ip) @ extract opcode from rINST 718 SET_VREG(r0, r3) @ vAA<- r0 719 GOTO_OPCODE(ip) @ jump to next instruction 720 721/* ------------------------------ */ 722 .balign 64 723.L_OP_CONST_HIGH16: /* 0x15 */ 724/* File: armv5te/OP_CONST_HIGH16.S */ 725 /* const/high16 vAA, #+BBBB0000 */ 726 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 727 mov r3, rINST, lsr #8 @ r3<- AA 728 mov r0, r0, lsl #16 @ r0<- BBBB0000 729 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 730 SET_VREG(r0, r3) @ vAA<- r0 731 GET_INST_OPCODE(ip) @ extract opcode from rINST 732 GOTO_OPCODE(ip) @ jump to next instruction 733 734/* ------------------------------ */ 735 .balign 64 736.L_OP_CONST_WIDE_16: /* 0x16 */ 737/* File: armv5te/OP_CONST_WIDE_16.S */ 738 /* const-wide/16 vAA, #+BBBB */ 739 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 740 mov r3, rINST, lsr #8 @ r3<- AA 741 mov r1, r0, asr #31 @ r1<- ssssssss 742 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 743 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 744 GET_INST_OPCODE(ip) @ extract opcode from rINST 745 stmia r3, {r0-r1} @ vAA<- r0/r1 746 GOTO_OPCODE(ip) @ jump to next instruction 747 748/* ------------------------------ */ 749 .balign 64 750.L_OP_CONST_WIDE_32: /* 0x17 */ 751/* File: armv5te/OP_CONST_WIDE_32.S */ 752 /* const-wide/32 vAA, #+BBBBbbbb */ 753 FETCH(r0, 1) @ r0<- 0000bbbb (low) 754 mov r3, rINST, lsr #8 @ r3<- AA 755 FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 756 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 757 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 758 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 759 mov r1, r0, asr #31 @ r1<- ssssssss 760 GET_INST_OPCODE(ip) @ extract opcode from rINST 761 stmia r3, {r0-r1} @ vAA<- r0/r1 762 GOTO_OPCODE(ip) @ jump to next instruction 763 764/* ------------------------------ */ 765 .balign 64 766.L_OP_CONST_WIDE: /* 0x18 */ 767/* File: armv5te/OP_CONST_WIDE.S */ 768 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 769 FETCH(r0, 1) @ r0<- bbbb (low) 770 FETCH(r1, 2) @ r1<- BBBB (low middle) 771 FETCH(r2, 3) @ r2<- hhhh (high middle) 772 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 773 FETCH(r3, 4) @ r3<- HHHH (high) 774 mov r9, rINST, lsr #8 @ r9<- AA 775 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 776 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 777 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 778 GET_INST_OPCODE(ip) @ extract opcode from rINST 779 stmia r9, {r0-r1} @ vAA<- r0/r1 780 GOTO_OPCODE(ip) @ jump to next instruction 781 782/* ------------------------------ */ 783 .balign 64 784.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 785/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 786 /* const-wide/high16 vAA, #+BBBB000000000000 */ 787 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 788 mov r3, rINST, lsr #8 @ r3<- AA 789 mov r0, #0 @ r0<- 00000000 790 mov r1, r1, lsl #16 @ r1<- BBBB0000 791 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 792 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 793 GET_INST_OPCODE(ip) @ extract opcode from rINST 794 stmia r3, {r0-r1} @ vAA<- r0/r1 795 GOTO_OPCODE(ip) @ jump to next instruction 796 797/* ------------------------------ */ 798 .balign 64 799.L_OP_CONST_STRING: /* 0x1a */ 800/* File: armv5te/OP_CONST_STRING.S */ 801 /* const/string vAA, String@BBBB */ 802 FETCH(r1, 1) @ r1<- BBBB 803 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 804 mov r9, rINST, lsr #8 @ r9<- AA 805 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 806 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 807 cmp r0, #0 @ not yet resolved? 808 beq .LOP_CONST_STRING_resolve 809 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 810 GET_INST_OPCODE(ip) @ extract opcode from rINST 811 SET_VREG(r0, r9) @ vAA<- r0 812 GOTO_OPCODE(ip) @ jump to next instruction 813 814/* ------------------------------ */ 815 .balign 64 816.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 817/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 818 /* const/string vAA, String@BBBBBBBB */ 819 FETCH(r0, 1) @ r0<- bbbb (low) 820 FETCH(r1, 2) @ r1<- BBBB (high) 821 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 822 mov r9, rINST, lsr #8 @ r9<- AA 823 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 824 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 825 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 826 cmp r0, #0 827 beq .LOP_CONST_STRING_JUMBO_resolve 828 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 829 GET_INST_OPCODE(ip) @ extract opcode from rINST 830 SET_VREG(r0, r9) @ vAA<- r0 831 GOTO_OPCODE(ip) @ jump to next instruction 832 833/* ------------------------------ */ 834 .balign 64 835.L_OP_CONST_CLASS: /* 0x1c */ 836/* File: armv5te/OP_CONST_CLASS.S */ 837 /* const/class vAA, Class@BBBB */ 838 FETCH(r1, 1) @ r1<- BBBB 839 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 840 mov r9, rINST, lsr #8 @ r9<- AA 841 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 842 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 843 cmp r0, #0 @ not yet resolved? 844 beq .LOP_CONST_CLASS_resolve 845 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 846 GET_INST_OPCODE(ip) @ extract opcode from rINST 847 SET_VREG(r0, r9) @ vAA<- r0 848 GOTO_OPCODE(ip) @ jump to next instruction 849 850/* ------------------------------ */ 851 .balign 64 852.L_OP_MONITOR_ENTER: /* 0x1d */ 853/* File: armv5te/OP_MONITOR_ENTER.S */ 854 /* 855 * Synchronize on an object. 856 */ 857 /* monitor-enter vAA */ 858 mov r2, rINST, lsr #8 @ r2<- AA 859 GET_VREG(r1, r2) @ r1<- vAA (object) 860 mov r0, rSELF @ r0<- self 861 cmp r1, #0 @ null object? 862 EXPORT_PC() @ need for precise GC 863 beq common_errNullObject @ null object, throw an exception 864 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 865 bl dvmLockObject @ call(self, obj) 866 GET_INST_OPCODE(ip) @ extract opcode from rINST 867 GOTO_OPCODE(ip) @ jump to next instruction 868 869/* ------------------------------ */ 870 .balign 64 871.L_OP_MONITOR_EXIT: /* 0x1e */ 872/* File: armv5te/OP_MONITOR_EXIT.S */ 873 /* 874 * Unlock an object. 875 * 876 * Exceptions that occur when unlocking a monitor need to appear as 877 * if they happened at the following instruction. See the Dalvik 878 * instruction spec. 879 */ 880 /* monitor-exit vAA */ 881 mov r2, rINST, lsr #8 @ r2<- AA 882 EXPORT_PC() @ before fetch: export the PC 883 GET_VREG(r1, r2) @ r1<- vAA (object) 884 cmp r1, #0 @ null object? 885 beq 1f @ yes 886 mov r0, rSELF @ r0<- self 887 bl dvmUnlockObject @ r0<- success for unlock(self, obj) 888 cmp r0, #0 @ failed? 889 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 890 beq common_exceptionThrown @ yes, exception is pending 891 GET_INST_OPCODE(ip) @ extract opcode from rINST 892 GOTO_OPCODE(ip) @ jump to next instruction 8931: 894 FETCH_ADVANCE_INST(1) @ advance before throw 895 b common_errNullObject 896 897/* ------------------------------ */ 898 .balign 64 899.L_OP_CHECK_CAST: /* 0x1f */ 900/* File: armv5te/OP_CHECK_CAST.S */ 901 /* 902 * Check to see if a cast from one class to another is allowed. 903 */ 904 /* check-cast vAA, class@BBBB */ 905 mov r3, rINST, lsr #8 @ r3<- AA 906 FETCH(r2, 1) @ r2<- BBBB 907 GET_VREG(r9, r3) @ r9<- object 908 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 909 cmp r9, #0 @ is object null? 910 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 911 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 912 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 913 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 914 cmp r1, #0 @ have we resolved this before? 915 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 916.LOP_CHECK_CAST_resolved: 917 cmp r0, r1 @ same class (trivial success)? 918 bne .LOP_CHECK_CAST_fullcheck @ no, do full check 919.LOP_CHECK_CAST_okay: 920 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 921 GET_INST_OPCODE(ip) @ extract opcode from rINST 922 GOTO_OPCODE(ip) @ jump to next instruction 923 924/* ------------------------------ */ 925 .balign 64 926.L_OP_INSTANCE_OF: /* 0x20 */ 927/* File: armv5te/OP_INSTANCE_OF.S */ 928 /* 929 * Check to see if an object reference is an instance of a class. 930 * 931 * Most common situation is a non-null object, being compared against 932 * an already-resolved class. 933 */ 934 /* instance-of vA, vB, class@CCCC */ 935 mov r3, rINST, lsr #12 @ r3<- B 936 mov r9, rINST, lsr #8 @ r9<- A+ 937 GET_VREG(r0, r3) @ r0<- vB (object) 938 and r9, r9, #15 @ r9<- A 939 cmp r0, #0 @ is object null? 940 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 941 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 942 FETCH(r3, 1) @ r3<- CCCC 943 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 944 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 945 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 946 cmp r1, #0 @ have we resolved this before? 947 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 948.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 949 cmp r0, r1 @ same class (trivial success)? 950 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 951 b .LOP_INSTANCE_OF_fullcheck @ no, do full check 952 953/* ------------------------------ */ 954 .balign 64 955.L_OP_ARRAY_LENGTH: /* 0x21 */ 956/* File: armv6t2/OP_ARRAY_LENGTH.S */ 957 /* 958 * Return the length of an array. 959 */ 960 mov r1, rINST, lsr #12 @ r1<- B 961 ubfx r2, rINST, #8, #4 @ r2<- A 962 GET_VREG(r0, r1) @ r0<- vB (object ref) 963 cmp r0, #0 @ is object null? 964 beq common_errNullObject @ yup, fail 965 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 966 ldr r3, [r0, #offArrayObject_length] @ r3<- array length 967 GET_INST_OPCODE(ip) @ extract opcode from rINST 968 SET_VREG(r3, r2) @ vB<- length 969 GOTO_OPCODE(ip) @ jump to next instruction 970 971/* ------------------------------ */ 972 .balign 64 973.L_OP_NEW_INSTANCE: /* 0x22 */ 974/* File: armv5te/OP_NEW_INSTANCE.S */ 975 /* 976 * Create a new instance of a class. 977 */ 978 /* new-instance vAA, class@BBBB */ 979 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 980 FETCH(r1, 1) @ r1<- BBBB 981 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 982 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 983 EXPORT_PC() @ req'd for init, resolve, alloc 984 cmp r0, #0 @ already resolved? 985 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 986.LOP_NEW_INSTANCE_resolved: @ r0=class 987 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 988 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 989 bne .LOP_NEW_INSTANCE_needinit @ no, init class now 990.LOP_NEW_INSTANCE_initialized: @ r0=class 991 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 992 bl dvmAllocObject @ r0<- new object 993 b .LOP_NEW_INSTANCE_finish @ continue 994 995/* ------------------------------ */ 996 .balign 64 997.L_OP_NEW_ARRAY: /* 0x23 */ 998/* File: armv5te/OP_NEW_ARRAY.S */ 999 /* 1000 * Allocate an array of objects, specified with the array class 1001 * and a count. 1002 * 1003 * The verifier guarantees that this is an array class, so we don't 1004 * check for it here. 1005 */ 1006 /* new-array vA, vB, class@CCCC */ 1007 mov r0, rINST, lsr #12 @ r0<- B 1008 FETCH(r2, 1) @ r2<- CCCC 1009 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1010 GET_VREG(r1, r0) @ r1<- vB (array length) 1011 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1012 cmp r1, #0 @ check length 1013 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1014 bmi common_errNegativeArraySize @ negative length, bail - len in r1 1015 cmp r0, #0 @ already resolved? 1016 EXPORT_PC() @ req'd for resolve, alloc 1017 bne .LOP_NEW_ARRAY_finish @ resolved, continue 1018 b .LOP_NEW_ARRAY_resolve @ do resolve now 1019 1020/* ------------------------------ */ 1021 .balign 64 1022.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1023/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1024 /* 1025 * Create a new array with elements filled from registers. 1026 * 1027 * for: filled-new-array, filled-new-array/range 1028 */ 1029 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1030 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1031 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1032 FETCH(r1, 1) @ r1<- BBBB 1033 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1034 EXPORT_PC() @ need for resolve and alloc 1035 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1036 mov r10, rINST, lsr #8 @ r10<- AA or BA 1037 cmp r0, #0 @ already resolved? 1038 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 10398: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1040 mov r2, #0 @ r2<- false 1041 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1042 bl dvmResolveClass @ r0<- call(clazz, ref) 1043 cmp r0, #0 @ got null? 1044 beq common_exceptionThrown @ yes, handle exception 1045 b .LOP_FILLED_NEW_ARRAY_continue 1046 1047/* ------------------------------ */ 1048 .balign 64 1049.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1050/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1051/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1052 /* 1053 * Create a new array with elements filled from registers. 1054 * 1055 * for: filled-new-array, filled-new-array/range 1056 */ 1057 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1058 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1059 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1060 FETCH(r1, 1) @ r1<- BBBB 1061 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1062 EXPORT_PC() @ need for resolve and alloc 1063 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1064 mov r10, rINST, lsr #8 @ r10<- AA or BA 1065 cmp r0, #0 @ already resolved? 1066 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 10678: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1068 mov r2, #0 @ r2<- false 1069 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1070 bl dvmResolveClass @ r0<- call(clazz, ref) 1071 cmp r0, #0 @ got null? 1072 beq common_exceptionThrown @ yes, handle exception 1073 b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1074 1075 1076/* ------------------------------ */ 1077 .balign 64 1078.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1079/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1080 /* fill-array-data vAA, +BBBBBBBB */ 1081 FETCH(r0, 1) @ r0<- bbbb (lo) 1082 FETCH(r1, 2) @ r1<- BBBB (hi) 1083 mov r3, rINST, lsr #8 @ r3<- AA 1084 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1085 GET_VREG(r0, r3) @ r0<- vAA (array object) 1086 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1087 EXPORT_PC(); 1088 bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1089 cmp r0, #0 @ 0 means an exception is thrown 1090 beq common_exceptionThrown @ has exception 1091 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1092 GET_INST_OPCODE(ip) @ extract opcode from rINST 1093 GOTO_OPCODE(ip) @ jump to next instruction 1094 1095/* ------------------------------ */ 1096 .balign 64 1097.L_OP_THROW: /* 0x27 */ 1098/* File: armv5te/OP_THROW.S */ 1099 /* 1100 * Throw an exception object in the current thread. 1101 */ 1102 /* throw vAA */ 1103 mov r2, rINST, lsr #8 @ r2<- AA 1104 GET_VREG(r1, r2) @ r1<- vAA (exception object) 1105 EXPORT_PC() @ exception handler can throw 1106 cmp r1, #0 @ null object? 1107 beq common_errNullObject @ yes, throw an NPE instead 1108 @ bypass dvmSetException, just store it 1109 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj 1110 b common_exceptionThrown 1111 1112/* ------------------------------ */ 1113 .balign 64 1114.L_OP_GOTO: /* 0x28 */ 1115/* File: armv5te/OP_GOTO.S */ 1116 /* 1117 * Unconditional branch, 8-bit offset. 1118 * 1119 * The branch distance is a signed code-unit offset, which we need to 1120 * double to get a byte offset. 1121 */ 1122 /* goto +AA */ 1123 mov r0, rINST, lsl #16 @ r0<- AAxx0000 1124 movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1125 mov r9, r9, lsl #1 @ r9<- byte offset 1126 bmi common_backwardBranch @ backward branch, do periodic checks 1127#if defined(WITH_JIT) 1128 GET_JIT_PROF_TABLE(r0) 1129 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1130 cmp r0,#0 1131 bne common_updateProfile 1132 GET_INST_OPCODE(ip) @ extract opcode from rINST 1133 GOTO_OPCODE(ip) @ jump to next instruction 1134#else 1135 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1136 GET_INST_OPCODE(ip) @ extract opcode from rINST 1137 GOTO_OPCODE(ip) @ jump to next instruction 1138#endif 1139 1140/* ------------------------------ */ 1141 .balign 64 1142.L_OP_GOTO_16: /* 0x29 */ 1143/* File: armv5te/OP_GOTO_16.S */ 1144 /* 1145 * Unconditional branch, 16-bit offset. 1146 * 1147 * The branch distance is a signed code-unit offset, which we need to 1148 * double to get a byte offset. 1149 */ 1150 /* goto/16 +AAAA */ 1151 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1152 movs r9, r0, asl #1 @ r9<- byte offset, check sign 1153 bmi common_backwardBranch @ backward branch, do periodic checks 1154#if defined(WITH_JIT) 1155 GET_JIT_PROF_TABLE(r0) 1156 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1157 cmp r0,#0 1158 bne common_updateProfile 1159 GET_INST_OPCODE(ip) @ extract opcode from rINST 1160 GOTO_OPCODE(ip) @ jump to next instruction 1161#else 1162 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1163 GET_INST_OPCODE(ip) @ extract opcode from rINST 1164 GOTO_OPCODE(ip) @ jump to next instruction 1165#endif 1166 1167/* ------------------------------ */ 1168 .balign 64 1169.L_OP_GOTO_32: /* 0x2a */ 1170/* File: armv5te/OP_GOTO_32.S */ 1171 /* 1172 * Unconditional branch, 32-bit offset. 1173 * 1174 * The branch distance is a signed code-unit offset, which we need to 1175 * double to get a byte offset. 1176 * 1177 * Unlike most opcodes, this one is allowed to branch to itself, so 1178 * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1179 * instruction doesn't affect the V flag, so we need to clear it 1180 * explicitly. 1181 */ 1182 /* goto/32 +AAAAAAAA */ 1183 FETCH(r0, 1) @ r0<- aaaa (lo) 1184 FETCH(r1, 2) @ r1<- AAAA (hi) 1185 cmp ip, ip @ (clear V flag during stall) 1186 orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1187 mov r9, r0, asl #1 @ r9<- byte offset 1188 ble common_backwardBranch @ backward branch, do periodic checks 1189#if defined(WITH_JIT) 1190 GET_JIT_PROF_TABLE(r0) 1191 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1192 cmp r0,#0 1193 bne common_updateProfile 1194 GET_INST_OPCODE(ip) @ extract opcode from rINST 1195 GOTO_OPCODE(ip) @ jump to next instruction 1196#else 1197 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1198 GET_INST_OPCODE(ip) @ extract opcode from rINST 1199 GOTO_OPCODE(ip) @ jump to next instruction 1200#endif 1201 1202/* ------------------------------ */ 1203 .balign 64 1204.L_OP_PACKED_SWITCH: /* 0x2b */ 1205/* File: armv5te/OP_PACKED_SWITCH.S */ 1206 /* 1207 * Handle a packed-switch or sparse-switch instruction. In both cases 1208 * we decode it and hand it off to a helper function. 1209 * 1210 * We don't really expect backward branches in a switch statement, but 1211 * they're perfectly legal, so we check for them here. 1212 * 1213 * for: packed-switch, sparse-switch 1214 */ 1215 /* op vAA, +BBBB */ 1216 FETCH(r0, 1) @ r0<- bbbb (lo) 1217 FETCH(r1, 2) @ r1<- BBBB (hi) 1218 mov r3, rINST, lsr #8 @ r3<- AA 1219 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1220 GET_VREG(r1, r3) @ r1<- vAA 1221 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1222 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1223 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1224 bmi common_backwardBranch @ backward branch, do periodic checks 1225 beq common_backwardBranch @ (want to use BLE but V is unknown) 1226#if defined(WITH_JIT) 1227 GET_JIT_PROF_TABLE(r0) 1228 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1229 cmp r0,#0 1230 bne common_updateProfile 1231 GET_INST_OPCODE(ip) @ extract opcode from rINST 1232 GOTO_OPCODE(ip) @ jump to next instruction 1233#else 1234 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1235 GET_INST_OPCODE(ip) @ extract opcode from rINST 1236 GOTO_OPCODE(ip) @ jump to next instruction 1237#endif 1238 1239/* ------------------------------ */ 1240 .balign 64 1241.L_OP_SPARSE_SWITCH: /* 0x2c */ 1242/* File: armv5te/OP_SPARSE_SWITCH.S */ 1243/* File: armv5te/OP_PACKED_SWITCH.S */ 1244 /* 1245 * Handle a packed-switch or sparse-switch instruction. In both cases 1246 * we decode it and hand it off to a helper function. 1247 * 1248 * We don't really expect backward branches in a switch statement, but 1249 * they're perfectly legal, so we check for them here. 1250 * 1251 * for: packed-switch, sparse-switch 1252 */ 1253 /* op vAA, +BBBB */ 1254 FETCH(r0, 1) @ r0<- bbbb (lo) 1255 FETCH(r1, 2) @ r1<- BBBB (hi) 1256 mov r3, rINST, lsr #8 @ r3<- AA 1257 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1258 GET_VREG(r1, r3) @ r1<- vAA 1259 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1260 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1261 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1262 bmi common_backwardBranch @ backward branch, do periodic checks 1263 beq common_backwardBranch @ (want to use BLE but V is unknown) 1264#if defined(WITH_JIT) 1265 GET_JIT_PROF_TABLE(r0) 1266 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1267 cmp r0,#0 1268 bne common_updateProfile 1269 GET_INST_OPCODE(ip) @ extract opcode from rINST 1270 GOTO_OPCODE(ip) @ jump to next instruction 1271#else 1272 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1273 GET_INST_OPCODE(ip) @ extract opcode from rINST 1274 GOTO_OPCODE(ip) @ jump to next instruction 1275#endif 1276 1277 1278/* ------------------------------ */ 1279 .balign 64 1280.L_OP_CMPL_FLOAT: /* 0x2d */ 1281/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1282 /* 1283 * Compare two floating-point values. Puts 0, 1, or -1 into the 1284 * destination register based on the results of the comparison. 1285 * 1286 * int compare(x, y) { 1287 * if (x == y) { 1288 * return 0; 1289 * } else if (x > y) { 1290 * return 1; 1291 * } else if (x < y) { 1292 * return -1; 1293 * } else { 1294 * return -1; 1295 * } 1296 * } 1297 */ 1298 /* op vAA, vBB, vCC */ 1299 FETCH(r0, 1) @ r0<- CCBB 1300 mov r9, rINST, lsr #8 @ r9<- AA 1301 and r2, r0, #255 @ r2<- BB 1302 mov r3, r0, lsr #8 @ r3<- CC 1303 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1304 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1305 flds s0, [r2] @ s0<- vBB 1306 flds s1, [r3] @ s1<- vCC 1307 fcmpes s0, s1 @ compare (vBB, vCC) 1308 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1309 mvn r0, #0 @ r0<- -1 (default) 1310 GET_INST_OPCODE(ip) @ extract opcode from rINST 1311 fmstat @ export status flags 1312 movgt r0, #1 @ (greater than) r1<- 1 1313 moveq r0, #0 @ (equal) r1<- 0 1314 b .LOP_CMPL_FLOAT_finish @ argh 1315 1316 1317/* ------------------------------ */ 1318 .balign 64 1319.L_OP_CMPG_FLOAT: /* 0x2e */ 1320/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1321 /* 1322 * Compare two floating-point values. Puts 0, 1, or -1 into the 1323 * destination register based on the results of the comparison. 1324 * 1325 * int compare(x, y) { 1326 * if (x == y) { 1327 * return 0; 1328 * } else if (x < y) { 1329 * return -1; 1330 * } else if (x > y) { 1331 * return 1; 1332 * } else { 1333 * return 1; 1334 * } 1335 * } 1336 */ 1337 /* op vAA, vBB, vCC */ 1338 FETCH(r0, 1) @ r0<- CCBB 1339 mov r9, rINST, lsr #8 @ r9<- AA 1340 and r2, r0, #255 @ r2<- BB 1341 mov r3, r0, lsr #8 @ r3<- CC 1342 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1343 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1344 flds s0, [r2] @ s0<- vBB 1345 flds s1, [r3] @ s1<- vCC 1346 fcmpes s0, s1 @ compare (vBB, vCC) 1347 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1348 mov r0, #1 @ r0<- 1 (default) 1349 GET_INST_OPCODE(ip) @ extract opcode from rINST 1350 fmstat @ export status flags 1351 mvnmi r0, #0 @ (less than) r1<- -1 1352 moveq r0, #0 @ (equal) r1<- 0 1353 b .LOP_CMPG_FLOAT_finish @ argh 1354 1355 1356/* ------------------------------ */ 1357 .balign 64 1358.L_OP_CMPL_DOUBLE: /* 0x2f */ 1359/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1360 /* 1361 * Compare two floating-point values. Puts 0, 1, or -1 into the 1362 * destination register based on the results of the comparison. 1363 * 1364 * int compare(x, y) { 1365 * if (x == y) { 1366 * return 0; 1367 * } else if (x > y) { 1368 * return 1; 1369 * } else if (x < y) { 1370 * return -1; 1371 * } else { 1372 * return -1; 1373 * } 1374 * } 1375 */ 1376 /* op vAA, vBB, vCC */ 1377 FETCH(r0, 1) @ r0<- CCBB 1378 mov r9, rINST, lsr #8 @ r9<- AA 1379 and r2, r0, #255 @ r2<- BB 1380 mov r3, r0, lsr #8 @ r3<- CC 1381 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1382 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1383 fldd d0, [r2] @ d0<- vBB 1384 fldd d1, [r3] @ d1<- vCC 1385 fcmped d0, d1 @ compare (vBB, vCC) 1386 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1387 mvn r0, #0 @ r0<- -1 (default) 1388 GET_INST_OPCODE(ip) @ extract opcode from rINST 1389 fmstat @ export status flags 1390 movgt r0, #1 @ (greater than) r1<- 1 1391 moveq r0, #0 @ (equal) r1<- 0 1392 b .LOP_CMPL_DOUBLE_finish @ argh 1393 1394 1395/* ------------------------------ */ 1396 .balign 64 1397.L_OP_CMPG_DOUBLE: /* 0x30 */ 1398/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1399 /* 1400 * Compare two floating-point values. Puts 0, 1, or -1 into the 1401 * destination register based on the results of the comparison. 1402 * 1403 * int compare(x, y) { 1404 * if (x == y) { 1405 * return 0; 1406 * } else if (x < y) { 1407 * return -1; 1408 * } else if (x > y) { 1409 * return 1; 1410 * } else { 1411 * return 1; 1412 * } 1413 * } 1414 */ 1415 /* op vAA, vBB, vCC */ 1416 FETCH(r0, 1) @ r0<- CCBB 1417 mov r9, rINST, lsr #8 @ r9<- AA 1418 and r2, r0, #255 @ r2<- BB 1419 mov r3, r0, lsr #8 @ r3<- CC 1420 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1421 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1422 fldd d0, [r2] @ d0<- vBB 1423 fldd d1, [r3] @ d1<- vCC 1424 fcmped d0, d1 @ compare (vBB, vCC) 1425 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1426 mov r0, #1 @ r0<- 1 (default) 1427 GET_INST_OPCODE(ip) @ extract opcode from rINST 1428 fmstat @ export status flags 1429 mvnmi r0, #0 @ (less than) r1<- -1 1430 moveq r0, #0 @ (equal) r1<- 0 1431 b .LOP_CMPG_DOUBLE_finish @ argh 1432 1433 1434/* ------------------------------ */ 1435 .balign 64 1436.L_OP_CMP_LONG: /* 0x31 */ 1437/* File: armv5te/OP_CMP_LONG.S */ 1438 /* 1439 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1440 * register based on the results of the comparison. 1441 * 1442 * We load the full values with LDM, but in practice many values could 1443 * be resolved by only looking at the high word. This could be made 1444 * faster or slower by splitting the LDM into a pair of LDRs. 1445 * 1446 * If we just wanted to set condition flags, we could do this: 1447 * subs ip, r0, r2 1448 * sbcs ip, r1, r3 1449 * subeqs ip, r0, r2 1450 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1451 * integer value, which we can do with 2 conditional mov/mvn instructions 1452 * (set 1, set -1; if they're equal we already have 0 in ip), giving 1453 * us a constant 5-cycle path plus a branch at the end to the 1454 * instruction epilogue code. The multi-compare approach below needs 1455 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1456 * in the worst case (the 64-bit values are equal). 1457 */ 1458 /* cmp-long vAA, vBB, vCC */ 1459 FETCH(r0, 1) @ r0<- CCBB 1460 mov r9, rINST, lsr #8 @ r9<- AA 1461 and r2, r0, #255 @ r2<- BB 1462 mov r3, r0, lsr #8 @ r3<- CC 1463 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1464 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1465 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1466 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1467 cmp r1, r3 @ compare (vBB+1, vCC+1) 1468 blt .LOP_CMP_LONG_less @ signed compare on high part 1469 bgt .LOP_CMP_LONG_greater 1470 subs r1, r0, r2 @ r1<- r0 - r2 1471 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1472 bne .LOP_CMP_LONG_less 1473 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1474 1475/* ------------------------------ */ 1476 .balign 64 1477.L_OP_IF_EQ: /* 0x32 */ 1478/* File: armv6t2/OP_IF_EQ.S */ 1479/* File: armv6t2/bincmp.S */ 1480 /* 1481 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1482 * fragment that specifies the *reverse* comparison to perform, e.g. 1483 * for "if-le" you would use "gt". 1484 * 1485 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1486 */ 1487 /* if-cmp vA, vB, +CCCC */ 1488 mov r1, rINST, lsr #12 @ r1<- B 1489 ubfx r0, rINST, #8, #4 @ r0<- A 1490 GET_VREG(r3, r1) @ r3<- vB 1491 GET_VREG(r2, r0) @ r2<- vA 1492 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1493 cmp r2, r3 @ compare (vA, vB) 1494 bne 1f @ branch to 1 if comparison failed 1495 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1496 movs r9, r9, asl #1 @ convert to bytes, check sign 1497 bmi common_backwardBranch @ yes, do periodic checks 14981: 1499#if defined(WITH_JIT) 1500 GET_JIT_PROF_TABLE(r0) 1501 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1502 b common_testUpdateProfile 1503#else 1504 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1505 GET_INST_OPCODE(ip) @ extract opcode from rINST 1506 GOTO_OPCODE(ip) @ jump to next instruction 1507#endif 1508 1509 1510/* ------------------------------ */ 1511 .balign 64 1512.L_OP_IF_NE: /* 0x33 */ 1513/* File: armv6t2/OP_IF_NE.S */ 1514/* File: armv6t2/bincmp.S */ 1515 /* 1516 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1517 * fragment that specifies the *reverse* comparison to perform, e.g. 1518 * for "if-le" you would use "gt". 1519 * 1520 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1521 */ 1522 /* if-cmp vA, vB, +CCCC */ 1523 mov r1, rINST, lsr #12 @ r1<- B 1524 ubfx r0, rINST, #8, #4 @ r0<- A 1525 GET_VREG(r3, r1) @ r3<- vB 1526 GET_VREG(r2, r0) @ r2<- vA 1527 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1528 cmp r2, r3 @ compare (vA, vB) 1529 beq 1f @ branch to 1 if comparison failed 1530 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1531 movs r9, r9, asl #1 @ convert to bytes, check sign 1532 bmi common_backwardBranch @ yes, do periodic checks 15331: 1534#if defined(WITH_JIT) 1535 GET_JIT_PROF_TABLE(r0) 1536 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1537 b common_testUpdateProfile 1538#else 1539 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1540 GET_INST_OPCODE(ip) @ extract opcode from rINST 1541 GOTO_OPCODE(ip) @ jump to next instruction 1542#endif 1543 1544 1545/* ------------------------------ */ 1546 .balign 64 1547.L_OP_IF_LT: /* 0x34 */ 1548/* File: armv6t2/OP_IF_LT.S */ 1549/* File: armv6t2/bincmp.S */ 1550 /* 1551 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1552 * fragment that specifies the *reverse* comparison to perform, e.g. 1553 * for "if-le" you would use "gt". 1554 * 1555 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1556 */ 1557 /* if-cmp vA, vB, +CCCC */ 1558 mov r1, rINST, lsr #12 @ r1<- B 1559 ubfx r0, rINST, #8, #4 @ r0<- A 1560 GET_VREG(r3, r1) @ r3<- vB 1561 GET_VREG(r2, r0) @ r2<- vA 1562 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1563 cmp r2, r3 @ compare (vA, vB) 1564 bge 1f @ branch to 1 if comparison failed 1565 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1566 movs r9, r9, asl #1 @ convert to bytes, check sign 1567 bmi common_backwardBranch @ yes, do periodic checks 15681: 1569#if defined(WITH_JIT) 1570 GET_JIT_PROF_TABLE(r0) 1571 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1572 b common_testUpdateProfile 1573#else 1574 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1575 GET_INST_OPCODE(ip) @ extract opcode from rINST 1576 GOTO_OPCODE(ip) @ jump to next instruction 1577#endif 1578 1579 1580/* ------------------------------ */ 1581 .balign 64 1582.L_OP_IF_GE: /* 0x35 */ 1583/* File: armv6t2/OP_IF_GE.S */ 1584/* File: armv6t2/bincmp.S */ 1585 /* 1586 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1587 * fragment that specifies the *reverse* comparison to perform, e.g. 1588 * for "if-le" you would use "gt". 1589 * 1590 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1591 */ 1592 /* if-cmp vA, vB, +CCCC */ 1593 mov r1, rINST, lsr #12 @ r1<- B 1594 ubfx r0, rINST, #8, #4 @ r0<- A 1595 GET_VREG(r3, r1) @ r3<- vB 1596 GET_VREG(r2, r0) @ r2<- vA 1597 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1598 cmp r2, r3 @ compare (vA, vB) 1599 blt 1f @ branch to 1 if comparison failed 1600 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1601 movs r9, r9, asl #1 @ convert to bytes, check sign 1602 bmi common_backwardBranch @ yes, do periodic checks 16031: 1604#if defined(WITH_JIT) 1605 GET_JIT_PROF_TABLE(r0) 1606 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1607 b common_testUpdateProfile 1608#else 1609 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1610 GET_INST_OPCODE(ip) @ extract opcode from rINST 1611 GOTO_OPCODE(ip) @ jump to next instruction 1612#endif 1613 1614 1615/* ------------------------------ */ 1616 .balign 64 1617.L_OP_IF_GT: /* 0x36 */ 1618/* File: armv6t2/OP_IF_GT.S */ 1619/* File: armv6t2/bincmp.S */ 1620 /* 1621 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1622 * fragment that specifies the *reverse* comparison to perform, e.g. 1623 * for "if-le" you would use "gt". 1624 * 1625 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1626 */ 1627 /* if-cmp vA, vB, +CCCC */ 1628 mov r1, rINST, lsr #12 @ r1<- B 1629 ubfx r0, rINST, #8, #4 @ r0<- A 1630 GET_VREG(r3, r1) @ r3<- vB 1631 GET_VREG(r2, r0) @ r2<- vA 1632 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1633 cmp r2, r3 @ compare (vA, vB) 1634 ble 1f @ branch to 1 if comparison failed 1635 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1636 movs r9, r9, asl #1 @ convert to bytes, check sign 1637 bmi common_backwardBranch @ yes, do periodic checks 16381: 1639#if defined(WITH_JIT) 1640 GET_JIT_PROF_TABLE(r0) 1641 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1642 b common_testUpdateProfile 1643#else 1644 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1645 GET_INST_OPCODE(ip) @ extract opcode from rINST 1646 GOTO_OPCODE(ip) @ jump to next instruction 1647#endif 1648 1649 1650/* ------------------------------ */ 1651 .balign 64 1652.L_OP_IF_LE: /* 0x37 */ 1653/* File: armv6t2/OP_IF_LE.S */ 1654/* File: armv6t2/bincmp.S */ 1655 /* 1656 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1657 * fragment that specifies the *reverse* comparison to perform, e.g. 1658 * for "if-le" you would use "gt". 1659 * 1660 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1661 */ 1662 /* if-cmp vA, vB, +CCCC */ 1663 mov r1, rINST, lsr #12 @ r1<- B 1664 ubfx r0, rINST, #8, #4 @ r0<- A 1665 GET_VREG(r3, r1) @ r3<- vB 1666 GET_VREG(r2, r0) @ r2<- vA 1667 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1668 cmp r2, r3 @ compare (vA, vB) 1669 bgt 1f @ branch to 1 if comparison failed 1670 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1671 movs r9, r9, asl #1 @ convert to bytes, check sign 1672 bmi common_backwardBranch @ yes, do periodic checks 16731: 1674#if defined(WITH_JIT) 1675 GET_JIT_PROF_TABLE(r0) 1676 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1677 b common_testUpdateProfile 1678#else 1679 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1680 GET_INST_OPCODE(ip) @ extract opcode from rINST 1681 GOTO_OPCODE(ip) @ jump to next instruction 1682#endif 1683 1684 1685/* ------------------------------ */ 1686 .balign 64 1687.L_OP_IF_EQZ: /* 0x38 */ 1688/* File: armv5te/OP_IF_EQZ.S */ 1689/* File: armv5te/zcmp.S */ 1690 /* 1691 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1692 * fragment that specifies the *reverse* comparison to perform, e.g. 1693 * for "if-le" you would use "gt". 1694 * 1695 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1696 */ 1697 /* if-cmp vAA, +BBBB */ 1698 mov r0, rINST, lsr #8 @ r0<- AA 1699 GET_VREG(r2, r0) @ r2<- vAA 1700 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1701 cmp r2, #0 @ compare (vA, 0) 1702 bne 1f @ branch to 1 if comparison failed 1703 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1704 movs r9, r9, asl #1 @ convert to bytes, check sign 1705 bmi common_backwardBranch @ backward branch, do periodic checks 17061: 1707#if defined(WITH_JIT) 1708 GET_JIT_PROF_TABLE(r0) 1709 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1710 cmp r0,#0 1711 bne common_updateProfile 1712 GET_INST_OPCODE(ip) @ extract opcode from rINST 1713 GOTO_OPCODE(ip) @ jump to next instruction 1714#else 1715 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1716 GET_INST_OPCODE(ip) @ extract opcode from rINST 1717 GOTO_OPCODE(ip) @ jump to next instruction 1718#endif 1719 1720 1721/* ------------------------------ */ 1722 .balign 64 1723.L_OP_IF_NEZ: /* 0x39 */ 1724/* File: armv5te/OP_IF_NEZ.S */ 1725/* File: armv5te/zcmp.S */ 1726 /* 1727 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1728 * fragment that specifies the *reverse* comparison to perform, e.g. 1729 * for "if-le" you would use "gt". 1730 * 1731 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1732 */ 1733 /* if-cmp vAA, +BBBB */ 1734 mov r0, rINST, lsr #8 @ r0<- AA 1735 GET_VREG(r2, r0) @ r2<- vAA 1736 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1737 cmp r2, #0 @ compare (vA, 0) 1738 beq 1f @ branch to 1 if comparison failed 1739 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1740 movs r9, r9, asl #1 @ convert to bytes, check sign 1741 bmi common_backwardBranch @ backward branch, do periodic checks 17421: 1743#if defined(WITH_JIT) 1744 GET_JIT_PROF_TABLE(r0) 1745 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1746 cmp r0,#0 1747 bne common_updateProfile 1748 GET_INST_OPCODE(ip) @ extract opcode from rINST 1749 GOTO_OPCODE(ip) @ jump to next instruction 1750#else 1751 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1752 GET_INST_OPCODE(ip) @ extract opcode from rINST 1753 GOTO_OPCODE(ip) @ jump to next instruction 1754#endif 1755 1756 1757/* ------------------------------ */ 1758 .balign 64 1759.L_OP_IF_LTZ: /* 0x3a */ 1760/* File: armv5te/OP_IF_LTZ.S */ 1761/* File: armv5te/zcmp.S */ 1762 /* 1763 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1764 * fragment that specifies the *reverse* comparison to perform, e.g. 1765 * for "if-le" you would use "gt". 1766 * 1767 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1768 */ 1769 /* if-cmp vAA, +BBBB */ 1770 mov r0, rINST, lsr #8 @ r0<- AA 1771 GET_VREG(r2, r0) @ r2<- vAA 1772 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1773 cmp r2, #0 @ compare (vA, 0) 1774 bge 1f @ branch to 1 if comparison failed 1775 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1776 movs r9, r9, asl #1 @ convert to bytes, check sign 1777 bmi common_backwardBranch @ backward branch, do periodic checks 17781: 1779#if defined(WITH_JIT) 1780 GET_JIT_PROF_TABLE(r0) 1781 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1782 cmp r0,#0 1783 bne common_updateProfile 1784 GET_INST_OPCODE(ip) @ extract opcode from rINST 1785 GOTO_OPCODE(ip) @ jump to next instruction 1786#else 1787 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1788 GET_INST_OPCODE(ip) @ extract opcode from rINST 1789 GOTO_OPCODE(ip) @ jump to next instruction 1790#endif 1791 1792 1793/* ------------------------------ */ 1794 .balign 64 1795.L_OP_IF_GEZ: /* 0x3b */ 1796/* File: armv5te/OP_IF_GEZ.S */ 1797/* File: armv5te/zcmp.S */ 1798 /* 1799 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1800 * fragment that specifies the *reverse* comparison to perform, e.g. 1801 * for "if-le" you would use "gt". 1802 * 1803 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1804 */ 1805 /* if-cmp vAA, +BBBB */ 1806 mov r0, rINST, lsr #8 @ r0<- AA 1807 GET_VREG(r2, r0) @ r2<- vAA 1808 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1809 cmp r2, #0 @ compare (vA, 0) 1810 blt 1f @ branch to 1 if comparison failed 1811 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1812 movs r9, r9, asl #1 @ convert to bytes, check sign 1813 bmi common_backwardBranch @ backward branch, do periodic checks 18141: 1815#if defined(WITH_JIT) 1816 GET_JIT_PROF_TABLE(r0) 1817 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1818 cmp r0,#0 1819 bne common_updateProfile 1820 GET_INST_OPCODE(ip) @ extract opcode from rINST 1821 GOTO_OPCODE(ip) @ jump to next instruction 1822#else 1823 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1824 GET_INST_OPCODE(ip) @ extract opcode from rINST 1825 GOTO_OPCODE(ip) @ jump to next instruction 1826#endif 1827 1828 1829/* ------------------------------ */ 1830 .balign 64 1831.L_OP_IF_GTZ: /* 0x3c */ 1832/* File: armv5te/OP_IF_GTZ.S */ 1833/* File: armv5te/zcmp.S */ 1834 /* 1835 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1836 * fragment that specifies the *reverse* comparison to perform, e.g. 1837 * for "if-le" you would use "gt". 1838 * 1839 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1840 */ 1841 /* if-cmp vAA, +BBBB */ 1842 mov r0, rINST, lsr #8 @ r0<- AA 1843 GET_VREG(r2, r0) @ r2<- vAA 1844 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1845 cmp r2, #0 @ compare (vA, 0) 1846 ble 1f @ branch to 1 if comparison failed 1847 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1848 movs r9, r9, asl #1 @ convert to bytes, check sign 1849 bmi common_backwardBranch @ backward branch, do periodic checks 18501: 1851#if defined(WITH_JIT) 1852 GET_JIT_PROF_TABLE(r0) 1853 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1854 cmp r0,#0 1855 bne common_updateProfile 1856 GET_INST_OPCODE(ip) @ extract opcode from rINST 1857 GOTO_OPCODE(ip) @ jump to next instruction 1858#else 1859 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1860 GET_INST_OPCODE(ip) @ extract opcode from rINST 1861 GOTO_OPCODE(ip) @ jump to next instruction 1862#endif 1863 1864 1865/* ------------------------------ */ 1866 .balign 64 1867.L_OP_IF_LEZ: /* 0x3d */ 1868/* File: armv5te/OP_IF_LEZ.S */ 1869/* File: armv5te/zcmp.S */ 1870 /* 1871 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1872 * fragment that specifies the *reverse* comparison to perform, e.g. 1873 * for "if-le" you would use "gt". 1874 * 1875 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1876 */ 1877 /* if-cmp vAA, +BBBB */ 1878 mov r0, rINST, lsr #8 @ r0<- AA 1879 GET_VREG(r2, r0) @ r2<- vAA 1880 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1881 cmp r2, #0 @ compare (vA, 0) 1882 bgt 1f @ branch to 1 if comparison failed 1883 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1884 movs r9, r9, asl #1 @ convert to bytes, check sign 1885 bmi common_backwardBranch @ backward branch, do periodic checks 18861: 1887#if defined(WITH_JIT) 1888 GET_JIT_PROF_TABLE(r0) 1889 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1890 cmp r0,#0 1891 bne common_updateProfile 1892 GET_INST_OPCODE(ip) @ extract opcode from rINST 1893 GOTO_OPCODE(ip) @ jump to next instruction 1894#else 1895 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1896 GET_INST_OPCODE(ip) @ extract opcode from rINST 1897 GOTO_OPCODE(ip) @ jump to next instruction 1898#endif 1899 1900 1901/* ------------------------------ */ 1902 .balign 64 1903.L_OP_UNUSED_3E: /* 0x3e */ 1904/* File: armv5te/OP_UNUSED_3E.S */ 1905/* File: armv5te/unused.S */ 1906 bl common_abort 1907 1908 1909/* ------------------------------ */ 1910 .balign 64 1911.L_OP_UNUSED_3F: /* 0x3f */ 1912/* File: armv5te/OP_UNUSED_3F.S */ 1913/* File: armv5te/unused.S */ 1914 bl common_abort 1915 1916 1917/* ------------------------------ */ 1918 .balign 64 1919.L_OP_UNUSED_40: /* 0x40 */ 1920/* File: armv5te/OP_UNUSED_40.S */ 1921/* File: armv5te/unused.S */ 1922 bl common_abort 1923 1924 1925/* ------------------------------ */ 1926 .balign 64 1927.L_OP_UNUSED_41: /* 0x41 */ 1928/* File: armv5te/OP_UNUSED_41.S */ 1929/* File: armv5te/unused.S */ 1930 bl common_abort 1931 1932 1933/* ------------------------------ */ 1934 .balign 64 1935.L_OP_UNUSED_42: /* 0x42 */ 1936/* File: armv5te/OP_UNUSED_42.S */ 1937/* File: armv5te/unused.S */ 1938 bl common_abort 1939 1940 1941/* ------------------------------ */ 1942 .balign 64 1943.L_OP_UNUSED_43: /* 0x43 */ 1944/* File: armv5te/OP_UNUSED_43.S */ 1945/* File: armv5te/unused.S */ 1946 bl common_abort 1947 1948 1949/* ------------------------------ */ 1950 .balign 64 1951.L_OP_AGET: /* 0x44 */ 1952/* File: armv5te/OP_AGET.S */ 1953 /* 1954 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1955 * 1956 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1957 * instructions. We use a pair of FETCH_Bs instead. 1958 * 1959 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1960 */ 1961 /* op vAA, vBB, vCC */ 1962 FETCH_B(r2, 1, 0) @ r2<- BB 1963 mov r9, rINST, lsr #8 @ r9<- AA 1964 FETCH_B(r3, 1, 1) @ r3<- CC 1965 GET_VREG(r0, r2) @ r0<- vBB (array object) 1966 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1967 cmp r0, #0 @ null array object? 1968 beq common_errNullObject @ yes, bail 1969 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1970 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1971 cmp r1, r3 @ compare unsigned index, length 1972 bcs common_errArrayIndex @ index >= length, bail 1973 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1974 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 1975 GET_INST_OPCODE(ip) @ extract opcode from rINST 1976 SET_VREG(r2, r9) @ vAA<- r2 1977 GOTO_OPCODE(ip) @ jump to next instruction 1978 1979/* ------------------------------ */ 1980 .balign 64 1981.L_OP_AGET_WIDE: /* 0x45 */ 1982/* File: armv5te/OP_AGET_WIDE.S */ 1983 /* 1984 * Array get, 64 bits. vAA <- vBB[vCC]. 1985 * 1986 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 1987 */ 1988 /* aget-wide vAA, vBB, vCC */ 1989 FETCH(r0, 1) @ r0<- CCBB 1990 mov r9, rINST, lsr #8 @ r9<- AA 1991 and r2, r0, #255 @ r2<- BB 1992 mov r3, r0, lsr #8 @ r3<- CC 1993 GET_VREG(r0, r2) @ r0<- vBB (array object) 1994 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1995 cmp r0, #0 @ null array object? 1996 beq common_errNullObject @ yes, bail 1997 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1998 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 1999 cmp r1, r3 @ compare unsigned index, length 2000 bcc .LOP_AGET_WIDE_finish @ okay, continue below 2001 b common_errArrayIndex @ index >= length, bail 2002 @ May want to swap the order of these two branches depending on how the 2003 @ branch prediction (if any) handles conditional forward branches vs. 2004 @ unconditional forward branches. 2005 2006/* ------------------------------ */ 2007 .balign 64 2008.L_OP_AGET_OBJECT: /* 0x46 */ 2009/* File: armv5te/OP_AGET_OBJECT.S */ 2010/* File: armv5te/OP_AGET.S */ 2011 /* 2012 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2013 * 2014 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2015 * instructions. We use a pair of FETCH_Bs instead. 2016 * 2017 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2018 */ 2019 /* op vAA, vBB, vCC */ 2020 FETCH_B(r2, 1, 0) @ r2<- BB 2021 mov r9, rINST, lsr #8 @ r9<- AA 2022 FETCH_B(r3, 1, 1) @ r3<- CC 2023 GET_VREG(r0, r2) @ r0<- vBB (array object) 2024 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2025 cmp r0, #0 @ null array object? 2026 beq common_errNullObject @ yes, bail 2027 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2028 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2029 cmp r1, r3 @ compare unsigned index, length 2030 bcs common_errArrayIndex @ index >= length, bail 2031 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2032 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2033 GET_INST_OPCODE(ip) @ extract opcode from rINST 2034 SET_VREG(r2, r9) @ vAA<- r2 2035 GOTO_OPCODE(ip) @ jump to next instruction 2036 2037 2038/* ------------------------------ */ 2039 .balign 64 2040.L_OP_AGET_BOOLEAN: /* 0x47 */ 2041/* File: armv5te/OP_AGET_BOOLEAN.S */ 2042/* File: armv5te/OP_AGET.S */ 2043 /* 2044 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2045 * 2046 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2047 * instructions. We use a pair of FETCH_Bs instead. 2048 * 2049 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2050 */ 2051 /* op vAA, vBB, vCC */ 2052 FETCH_B(r2, 1, 0) @ r2<- BB 2053 mov r9, rINST, lsr #8 @ r9<- AA 2054 FETCH_B(r3, 1, 1) @ r3<- CC 2055 GET_VREG(r0, r2) @ r0<- vBB (array object) 2056 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2057 cmp r0, #0 @ null array object? 2058 beq common_errNullObject @ yes, bail 2059 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2060 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2061 cmp r1, r3 @ compare unsigned index, length 2062 bcs common_errArrayIndex @ index >= length, bail 2063 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2064 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2065 GET_INST_OPCODE(ip) @ extract opcode from rINST 2066 SET_VREG(r2, r9) @ vAA<- r2 2067 GOTO_OPCODE(ip) @ jump to next instruction 2068 2069 2070/* ------------------------------ */ 2071 .balign 64 2072.L_OP_AGET_BYTE: /* 0x48 */ 2073/* File: armv5te/OP_AGET_BYTE.S */ 2074/* File: armv5te/OP_AGET.S */ 2075 /* 2076 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2077 * 2078 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2079 * instructions. We use a pair of FETCH_Bs instead. 2080 * 2081 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2082 */ 2083 /* op vAA, vBB, vCC */ 2084 FETCH_B(r2, 1, 0) @ r2<- BB 2085 mov r9, rINST, lsr #8 @ r9<- AA 2086 FETCH_B(r3, 1, 1) @ r3<- CC 2087 GET_VREG(r0, r2) @ r0<- vBB (array object) 2088 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2089 cmp r0, #0 @ null array object? 2090 beq common_errNullObject @ yes, bail 2091 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2092 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2093 cmp r1, r3 @ compare unsigned index, length 2094 bcs common_errArrayIndex @ index >= length, bail 2095 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2096 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2097 GET_INST_OPCODE(ip) @ extract opcode from rINST 2098 SET_VREG(r2, r9) @ vAA<- r2 2099 GOTO_OPCODE(ip) @ jump to next instruction 2100 2101 2102/* ------------------------------ */ 2103 .balign 64 2104.L_OP_AGET_CHAR: /* 0x49 */ 2105/* File: armv5te/OP_AGET_CHAR.S */ 2106/* File: armv5te/OP_AGET.S */ 2107 /* 2108 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2109 * 2110 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2111 * instructions. We use a pair of FETCH_Bs instead. 2112 * 2113 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2114 */ 2115 /* op vAA, vBB, vCC */ 2116 FETCH_B(r2, 1, 0) @ r2<- BB 2117 mov r9, rINST, lsr #8 @ r9<- AA 2118 FETCH_B(r3, 1, 1) @ r3<- CC 2119 GET_VREG(r0, r2) @ r0<- vBB (array object) 2120 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2121 cmp r0, #0 @ null array object? 2122 beq common_errNullObject @ yes, bail 2123 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2124 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2125 cmp r1, r3 @ compare unsigned index, length 2126 bcs common_errArrayIndex @ index >= length, bail 2127 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2128 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2129 GET_INST_OPCODE(ip) @ extract opcode from rINST 2130 SET_VREG(r2, r9) @ vAA<- r2 2131 GOTO_OPCODE(ip) @ jump to next instruction 2132 2133 2134/* ------------------------------ */ 2135 .balign 64 2136.L_OP_AGET_SHORT: /* 0x4a */ 2137/* File: armv5te/OP_AGET_SHORT.S */ 2138/* File: armv5te/OP_AGET.S */ 2139 /* 2140 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2141 * 2142 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2143 * instructions. We use a pair of FETCH_Bs instead. 2144 * 2145 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2146 */ 2147 /* op vAA, vBB, vCC */ 2148 FETCH_B(r2, 1, 0) @ r2<- BB 2149 mov r9, rINST, lsr #8 @ r9<- AA 2150 FETCH_B(r3, 1, 1) @ r3<- CC 2151 GET_VREG(r0, r2) @ r0<- vBB (array object) 2152 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2153 cmp r0, #0 @ null array object? 2154 beq common_errNullObject @ yes, bail 2155 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2156 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2157 cmp r1, r3 @ compare unsigned index, length 2158 bcs common_errArrayIndex @ index >= length, bail 2159 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2160 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2161 GET_INST_OPCODE(ip) @ extract opcode from rINST 2162 SET_VREG(r2, r9) @ vAA<- r2 2163 GOTO_OPCODE(ip) @ jump to next instruction 2164 2165 2166/* ------------------------------ */ 2167 .balign 64 2168.L_OP_APUT: /* 0x4b */ 2169/* File: armv5te/OP_APUT.S */ 2170 /* 2171 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2172 * 2173 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2174 * instructions. We use a pair of FETCH_Bs instead. 2175 * 2176 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2177 */ 2178 /* op vAA, vBB, vCC */ 2179 FETCH_B(r2, 1, 0) @ r2<- BB 2180 mov r9, rINST, lsr #8 @ r9<- AA 2181 FETCH_B(r3, 1, 1) @ r3<- CC 2182 GET_VREG(r0, r2) @ r0<- vBB (array object) 2183 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2184 cmp r0, #0 @ null array object? 2185 beq common_errNullObject @ yes, bail 2186 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2187 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2188 cmp r1, r3 @ compare unsigned index, length 2189 bcs common_errArrayIndex @ index >= length, bail 2190 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2191 GET_VREG(r2, r9) @ r2<- vAA 2192 GET_INST_OPCODE(ip) @ extract opcode from rINST 2193 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2194 GOTO_OPCODE(ip) @ jump to next instruction 2195 2196/* ------------------------------ */ 2197 .balign 64 2198.L_OP_APUT_WIDE: /* 0x4c */ 2199/* File: armv5te/OP_APUT_WIDE.S */ 2200 /* 2201 * Array put, 64 bits. vBB[vCC] <- vAA. 2202 * 2203 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2204 */ 2205 /* aput-wide vAA, vBB, vCC */ 2206 FETCH(r0, 1) @ r0<- CCBB 2207 mov r9, rINST, lsr #8 @ r9<- AA 2208 and r2, r0, #255 @ r2<- BB 2209 mov r3, r0, lsr #8 @ r3<- CC 2210 GET_VREG(r0, r2) @ r0<- vBB (array object) 2211 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2212 cmp r0, #0 @ null array object? 2213 beq common_errNullObject @ yes, bail 2214 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2215 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2216 cmp r1, r3 @ compare unsigned index, length 2217 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2218 bcc .LOP_APUT_WIDE_finish @ okay, continue below 2219 b common_errArrayIndex @ index >= length, bail 2220 @ May want to swap the order of these two branches depending on how the 2221 @ branch prediction (if any) handles conditional forward branches vs. 2222 @ unconditional forward branches. 2223 2224/* ------------------------------ */ 2225 .balign 64 2226.L_OP_APUT_OBJECT: /* 0x4d */ 2227/* File: armv5te/OP_APUT_OBJECT.S */ 2228 /* 2229 * Store an object into an array. vBB[vCC] <- vAA. 2230 */ 2231 /* op vAA, vBB, vCC */ 2232 FETCH(r0, 1) @ r0<- CCBB 2233 mov r9, rINST, lsr #8 @ r9<- AA 2234 and r2, r0, #255 @ r2<- BB 2235 mov r3, r0, lsr #8 @ r3<- CC 2236 GET_VREG(rINST, r2) @ rINST<- vBB (array object) 2237 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2238 cmp rINST, #0 @ null array object? 2239 GET_VREG(r9, r9) @ r9<- vAA 2240 beq common_errNullObject @ yes, bail 2241 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length 2242 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width 2243 cmp r1, r3 @ compare unsigned index, length 2244 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2245 b common_errArrayIndex @ index >= length, bail 2246 2247 2248/* ------------------------------ */ 2249 .balign 64 2250.L_OP_APUT_BOOLEAN: /* 0x4e */ 2251/* File: armv5te/OP_APUT_BOOLEAN.S */ 2252/* File: armv5te/OP_APUT.S */ 2253 /* 2254 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2255 * 2256 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2257 * instructions. We use a pair of FETCH_Bs instead. 2258 * 2259 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2260 */ 2261 /* op vAA, vBB, vCC */ 2262 FETCH_B(r2, 1, 0) @ r2<- BB 2263 mov r9, rINST, lsr #8 @ r9<- AA 2264 FETCH_B(r3, 1, 1) @ r3<- CC 2265 GET_VREG(r0, r2) @ r0<- vBB (array object) 2266 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2267 cmp r0, #0 @ null array object? 2268 beq common_errNullObject @ yes, bail 2269 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2270 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2271 cmp r1, r3 @ compare unsigned index, length 2272 bcs common_errArrayIndex @ index >= length, bail 2273 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2274 GET_VREG(r2, r9) @ r2<- vAA 2275 GET_INST_OPCODE(ip) @ extract opcode from rINST 2276 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2277 GOTO_OPCODE(ip) @ jump to next instruction 2278 2279 2280/* ------------------------------ */ 2281 .balign 64 2282.L_OP_APUT_BYTE: /* 0x4f */ 2283/* File: armv5te/OP_APUT_BYTE.S */ 2284/* File: armv5te/OP_APUT.S */ 2285 /* 2286 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2287 * 2288 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2289 * instructions. We use a pair of FETCH_Bs instead. 2290 * 2291 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2292 */ 2293 /* op vAA, vBB, vCC */ 2294 FETCH_B(r2, 1, 0) @ r2<- BB 2295 mov r9, rINST, lsr #8 @ r9<- AA 2296 FETCH_B(r3, 1, 1) @ r3<- CC 2297 GET_VREG(r0, r2) @ r0<- vBB (array object) 2298 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2299 cmp r0, #0 @ null array object? 2300 beq common_errNullObject @ yes, bail 2301 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2302 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2303 cmp r1, r3 @ compare unsigned index, length 2304 bcs common_errArrayIndex @ index >= length, bail 2305 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2306 GET_VREG(r2, r9) @ r2<- vAA 2307 GET_INST_OPCODE(ip) @ extract opcode from rINST 2308 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2309 GOTO_OPCODE(ip) @ jump to next instruction 2310 2311 2312/* ------------------------------ */ 2313 .balign 64 2314.L_OP_APUT_CHAR: /* 0x50 */ 2315/* File: armv5te/OP_APUT_CHAR.S */ 2316/* File: armv5te/OP_APUT.S */ 2317 /* 2318 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2319 * 2320 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2321 * instructions. We use a pair of FETCH_Bs instead. 2322 * 2323 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2324 */ 2325 /* op vAA, vBB, vCC */ 2326 FETCH_B(r2, 1, 0) @ r2<- BB 2327 mov r9, rINST, lsr #8 @ r9<- AA 2328 FETCH_B(r3, 1, 1) @ r3<- CC 2329 GET_VREG(r0, r2) @ r0<- vBB (array object) 2330 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2331 cmp r0, #0 @ null array object? 2332 beq common_errNullObject @ yes, bail 2333 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2334 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2335 cmp r1, r3 @ compare unsigned index, length 2336 bcs common_errArrayIndex @ index >= length, bail 2337 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2338 GET_VREG(r2, r9) @ r2<- vAA 2339 GET_INST_OPCODE(ip) @ extract opcode from rINST 2340 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2341 GOTO_OPCODE(ip) @ jump to next instruction 2342 2343 2344/* ------------------------------ */ 2345 .balign 64 2346.L_OP_APUT_SHORT: /* 0x51 */ 2347/* File: armv5te/OP_APUT_SHORT.S */ 2348/* File: armv5te/OP_APUT.S */ 2349 /* 2350 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2351 * 2352 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2353 * instructions. We use a pair of FETCH_Bs instead. 2354 * 2355 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2356 */ 2357 /* op vAA, vBB, vCC */ 2358 FETCH_B(r2, 1, 0) @ r2<- BB 2359 mov r9, rINST, lsr #8 @ r9<- AA 2360 FETCH_B(r3, 1, 1) @ r3<- CC 2361 GET_VREG(r0, r2) @ r0<- vBB (array object) 2362 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2363 cmp r0, #0 @ null array object? 2364 beq common_errNullObject @ yes, bail 2365 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2366 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2367 cmp r1, r3 @ compare unsigned index, length 2368 bcs common_errArrayIndex @ index >= length, bail 2369 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2370 GET_VREG(r2, r9) @ r2<- vAA 2371 GET_INST_OPCODE(ip) @ extract opcode from rINST 2372 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2373 GOTO_OPCODE(ip) @ jump to next instruction 2374 2375 2376/* ------------------------------ */ 2377 .balign 64 2378.L_OP_IGET: /* 0x52 */ 2379/* File: armv6t2/OP_IGET.S */ 2380 /* 2381 * General 32-bit instance field get. 2382 * 2383 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2384 */ 2385 /* op vA, vB, field@CCCC */ 2386 mov r0, rINST, lsr #12 @ r0<- B 2387 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2388 FETCH(r1, 1) @ r1<- field ref CCCC 2389 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2390 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2391 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2392 cmp r0, #0 @ is resolved entry null? 2393 bne .LOP_IGET_finish @ no, already resolved 23948: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2395 EXPORT_PC() @ resolve() could throw 2396 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2397 bl dvmResolveInstField @ r0<- resolved InstField ptr 2398 cmp r0, #0 2399 bne .LOP_IGET_finish 2400 b common_exceptionThrown 2401 2402/* ------------------------------ */ 2403 .balign 64 2404.L_OP_IGET_WIDE: /* 0x53 */ 2405/* File: armv6t2/OP_IGET_WIDE.S */ 2406 /* 2407 * Wide 32-bit instance field get. 2408 */ 2409 /* iget-wide vA, vB, field@CCCC */ 2410 mov r0, rINST, lsr #12 @ r0<- B 2411 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2412 FETCH(r1, 1) @ r1<- field ref CCCC 2413 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2414 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2415 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2416 cmp r0, #0 @ is resolved entry null? 2417 bne .LOP_IGET_WIDE_finish @ no, already resolved 24188: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2419 EXPORT_PC() @ resolve() could throw 2420 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2421 bl dvmResolveInstField @ r0<- resolved InstField ptr 2422 cmp r0, #0 2423 bne .LOP_IGET_WIDE_finish 2424 b common_exceptionThrown 2425 2426/* ------------------------------ */ 2427 .balign 64 2428.L_OP_IGET_OBJECT: /* 0x54 */ 2429/* File: armv5te/OP_IGET_OBJECT.S */ 2430/* File: armv5te/OP_IGET.S */ 2431 /* 2432 * General 32-bit instance field get. 2433 * 2434 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2435 */ 2436 /* op vA, vB, field@CCCC */ 2437 mov r0, rINST, lsr #12 @ r0<- B 2438 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2439 FETCH(r1, 1) @ r1<- field ref CCCC 2440 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2441 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2442 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2443 cmp r0, #0 @ is resolved entry null? 2444 bne .LOP_IGET_OBJECT_finish @ no, already resolved 24458: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2446 EXPORT_PC() @ resolve() could throw 2447 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2448 bl dvmResolveInstField @ r0<- resolved InstField ptr 2449 cmp r0, #0 2450 bne .LOP_IGET_OBJECT_finish 2451 b common_exceptionThrown 2452 2453 2454/* ------------------------------ */ 2455 .balign 64 2456.L_OP_IGET_BOOLEAN: /* 0x55 */ 2457/* File: armv5te/OP_IGET_BOOLEAN.S */ 2458@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2459/* File: armv5te/OP_IGET.S */ 2460 /* 2461 * General 32-bit instance field get. 2462 * 2463 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2464 */ 2465 /* op vA, vB, field@CCCC */ 2466 mov r0, rINST, lsr #12 @ r0<- B 2467 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2468 FETCH(r1, 1) @ r1<- field ref CCCC 2469 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2470 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2471 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2472 cmp r0, #0 @ is resolved entry null? 2473 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 24748: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2475 EXPORT_PC() @ resolve() could throw 2476 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2477 bl dvmResolveInstField @ r0<- resolved InstField ptr 2478 cmp r0, #0 2479 bne .LOP_IGET_BOOLEAN_finish 2480 b common_exceptionThrown 2481 2482 2483/* ------------------------------ */ 2484 .balign 64 2485.L_OP_IGET_BYTE: /* 0x56 */ 2486/* File: armv5te/OP_IGET_BYTE.S */ 2487@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2488/* File: armv5te/OP_IGET.S */ 2489 /* 2490 * General 32-bit instance field get. 2491 * 2492 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2493 */ 2494 /* op vA, vB, field@CCCC */ 2495 mov r0, rINST, lsr #12 @ r0<- B 2496 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2497 FETCH(r1, 1) @ r1<- field ref CCCC 2498 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2499 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2500 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2501 cmp r0, #0 @ is resolved entry null? 2502 bne .LOP_IGET_BYTE_finish @ no, already resolved 25038: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2504 EXPORT_PC() @ resolve() could throw 2505 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2506 bl dvmResolveInstField @ r0<- resolved InstField ptr 2507 cmp r0, #0 2508 bne .LOP_IGET_BYTE_finish 2509 b common_exceptionThrown 2510 2511 2512/* ------------------------------ */ 2513 .balign 64 2514.L_OP_IGET_CHAR: /* 0x57 */ 2515/* File: armv5te/OP_IGET_CHAR.S */ 2516@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2517/* File: armv5te/OP_IGET.S */ 2518 /* 2519 * General 32-bit instance field get. 2520 * 2521 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2522 */ 2523 /* op vA, vB, field@CCCC */ 2524 mov r0, rINST, lsr #12 @ r0<- B 2525 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2526 FETCH(r1, 1) @ r1<- field ref CCCC 2527 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2528 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2529 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2530 cmp r0, #0 @ is resolved entry null? 2531 bne .LOP_IGET_CHAR_finish @ no, already resolved 25328: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2533 EXPORT_PC() @ resolve() could throw 2534 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2535 bl dvmResolveInstField @ r0<- resolved InstField ptr 2536 cmp r0, #0 2537 bne .LOP_IGET_CHAR_finish 2538 b common_exceptionThrown 2539 2540 2541/* ------------------------------ */ 2542 .balign 64 2543.L_OP_IGET_SHORT: /* 0x58 */ 2544/* File: armv5te/OP_IGET_SHORT.S */ 2545@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2546/* File: armv5te/OP_IGET.S */ 2547 /* 2548 * General 32-bit instance field get. 2549 * 2550 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2551 */ 2552 /* op vA, vB, field@CCCC */ 2553 mov r0, rINST, lsr #12 @ r0<- B 2554 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2555 FETCH(r1, 1) @ r1<- field ref CCCC 2556 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2557 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2558 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2559 cmp r0, #0 @ is resolved entry null? 2560 bne .LOP_IGET_SHORT_finish @ no, already resolved 25618: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2562 EXPORT_PC() @ resolve() could throw 2563 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2564 bl dvmResolveInstField @ r0<- resolved InstField ptr 2565 cmp r0, #0 2566 bne .LOP_IGET_SHORT_finish 2567 b common_exceptionThrown 2568 2569 2570/* ------------------------------ */ 2571 .balign 64 2572.L_OP_IPUT: /* 0x59 */ 2573/* File: armv6t2/OP_IPUT.S */ 2574 /* 2575 * General 32-bit instance field put. 2576 * 2577 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2578 */ 2579 /* op vA, vB, field@CCCC */ 2580 mov r0, rINST, lsr #12 @ r0<- B 2581 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2582 FETCH(r1, 1) @ r1<- field ref CCCC 2583 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2584 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2585 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2586 cmp r0, #0 @ is resolved entry null? 2587 bne .LOP_IPUT_finish @ no, already resolved 25888: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2589 EXPORT_PC() @ resolve() could throw 2590 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2591 bl dvmResolveInstField @ r0<- resolved InstField ptr 2592 cmp r0, #0 @ success? 2593 bne .LOP_IPUT_finish @ yes, finish up 2594 b common_exceptionThrown 2595 2596/* ------------------------------ */ 2597 .balign 64 2598.L_OP_IPUT_WIDE: /* 0x5a */ 2599/* File: armv6t2/OP_IPUT_WIDE.S */ 2600 /* iput-wide vA, vB, field@CCCC */ 2601 mov r0, rINST, lsr #12 @ r0<- B 2602 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2603 FETCH(r1, 1) @ r1<- field ref CCCC 2604 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2605 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2606 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2607 cmp r0, #0 @ is resolved entry null? 2608 bne .LOP_IPUT_WIDE_finish @ no, already resolved 26098: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2610 EXPORT_PC() @ resolve() could throw 2611 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2612 bl dvmResolveInstField @ r0<- resolved InstField ptr 2613 cmp r0, #0 @ success? 2614 bne .LOP_IPUT_WIDE_finish @ yes, finish up 2615 b common_exceptionThrown 2616 2617/* ------------------------------ */ 2618 .balign 64 2619.L_OP_IPUT_OBJECT: /* 0x5b */ 2620/* File: armv5te/OP_IPUT_OBJECT.S */ 2621 /* 2622 * 32-bit instance field put. 2623 * 2624 * for: iput-object, iput-object-volatile 2625 */ 2626 /* op vA, vB, field@CCCC */ 2627 mov r0, rINST, lsr #12 @ r0<- B 2628 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2629 FETCH(r1, 1) @ r1<- field ref CCCC 2630 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2631 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2632 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2633 cmp r0, #0 @ is resolved entry null? 2634 bne .LOP_IPUT_OBJECT_finish @ no, already resolved 26358: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2636 EXPORT_PC() @ resolve() could throw 2637 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2638 bl dvmResolveInstField @ r0<- resolved InstField ptr 2639 cmp r0, #0 @ success? 2640 bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2641 b common_exceptionThrown 2642 2643/* ------------------------------ */ 2644 .balign 64 2645.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2646/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2647@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2648/* File: armv5te/OP_IPUT.S */ 2649 /* 2650 * General 32-bit instance field put. 2651 * 2652 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2653 */ 2654 /* op vA, vB, field@CCCC */ 2655 mov r0, rINST, lsr #12 @ r0<- B 2656 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2657 FETCH(r1, 1) @ r1<- field ref CCCC 2658 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2659 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2660 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2661 cmp r0, #0 @ is resolved entry null? 2662 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 26638: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2664 EXPORT_PC() @ resolve() could throw 2665 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2666 bl dvmResolveInstField @ r0<- resolved InstField ptr 2667 cmp r0, #0 @ success? 2668 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2669 b common_exceptionThrown 2670 2671 2672/* ------------------------------ */ 2673 .balign 64 2674.L_OP_IPUT_BYTE: /* 0x5d */ 2675/* File: armv5te/OP_IPUT_BYTE.S */ 2676@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2677/* File: armv5te/OP_IPUT.S */ 2678 /* 2679 * General 32-bit instance field put. 2680 * 2681 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2682 */ 2683 /* op vA, vB, field@CCCC */ 2684 mov r0, rINST, lsr #12 @ r0<- B 2685 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2686 FETCH(r1, 1) @ r1<- field ref CCCC 2687 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2688 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2689 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2690 cmp r0, #0 @ is resolved entry null? 2691 bne .LOP_IPUT_BYTE_finish @ no, already resolved 26928: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2693 EXPORT_PC() @ resolve() could throw 2694 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2695 bl dvmResolveInstField @ r0<- resolved InstField ptr 2696 cmp r0, #0 @ success? 2697 bne .LOP_IPUT_BYTE_finish @ yes, finish up 2698 b common_exceptionThrown 2699 2700 2701/* ------------------------------ */ 2702 .balign 64 2703.L_OP_IPUT_CHAR: /* 0x5e */ 2704/* File: armv5te/OP_IPUT_CHAR.S */ 2705@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2706/* File: armv5te/OP_IPUT.S */ 2707 /* 2708 * General 32-bit instance field put. 2709 * 2710 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2711 */ 2712 /* op vA, vB, field@CCCC */ 2713 mov r0, rINST, lsr #12 @ r0<- B 2714 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2715 FETCH(r1, 1) @ r1<- field ref CCCC 2716 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2717 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2718 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2719 cmp r0, #0 @ is resolved entry null? 2720 bne .LOP_IPUT_CHAR_finish @ no, already resolved 27218: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2722 EXPORT_PC() @ resolve() could throw 2723 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2724 bl dvmResolveInstField @ r0<- resolved InstField ptr 2725 cmp r0, #0 @ success? 2726 bne .LOP_IPUT_CHAR_finish @ yes, finish up 2727 b common_exceptionThrown 2728 2729 2730/* ------------------------------ */ 2731 .balign 64 2732.L_OP_IPUT_SHORT: /* 0x5f */ 2733/* File: armv5te/OP_IPUT_SHORT.S */ 2734@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2735/* File: armv5te/OP_IPUT.S */ 2736 /* 2737 * General 32-bit instance field put. 2738 * 2739 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2740 */ 2741 /* op vA, vB, field@CCCC */ 2742 mov r0, rINST, lsr #12 @ r0<- B 2743 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2744 FETCH(r1, 1) @ r1<- field ref CCCC 2745 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2746 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2747 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2748 cmp r0, #0 @ is resolved entry null? 2749 bne .LOP_IPUT_SHORT_finish @ no, already resolved 27508: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2751 EXPORT_PC() @ resolve() could throw 2752 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2753 bl dvmResolveInstField @ r0<- resolved InstField ptr 2754 cmp r0, #0 @ success? 2755 bne .LOP_IPUT_SHORT_finish @ yes, finish up 2756 b common_exceptionThrown 2757 2758 2759/* ------------------------------ */ 2760 .balign 64 2761.L_OP_SGET: /* 0x60 */ 2762/* File: armv5te/OP_SGET.S */ 2763 /* 2764 * General 32-bit SGET handler. 2765 * 2766 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2767 */ 2768 /* op vAA, field@BBBB */ 2769 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2770 FETCH(r1, 1) @ r1<- field ref BBBB 2771 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2772 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2773 cmp r0, #0 @ is resolved entry null? 2774 beq .LOP_SGET_resolve @ yes, do resolve 2775.LOP_SGET_finish: @ field ptr in r0 2776 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2777 @ no-op @ acquiring load 2778 mov r2, rINST, lsr #8 @ r2<- AA 2779 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2780 SET_VREG(r1, r2) @ fp[AA]<- r1 2781 GET_INST_OPCODE(ip) @ extract opcode from rINST 2782 GOTO_OPCODE(ip) @ jump to next instruction 2783 2784/* ------------------------------ */ 2785 .balign 64 2786.L_OP_SGET_WIDE: /* 0x61 */ 2787/* File: armv5te/OP_SGET_WIDE.S */ 2788 /* 2789 * 64-bit SGET handler. 2790 */ 2791 /* sget-wide vAA, field@BBBB */ 2792 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2793 FETCH(r1, 1) @ r1<- field ref BBBB 2794 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2795 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2796 cmp r0, #0 @ is resolved entry null? 2797 beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2798.LOP_SGET_WIDE_finish: 2799 mov r9, rINST, lsr #8 @ r9<- AA 2800 .if 0 2801 add r0, r0, #offStaticField_value @ r0<- pointer to data 2802 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2803 .else 2804 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2805 .endif 2806 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2807 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2808 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2809 GET_INST_OPCODE(ip) @ extract opcode from rINST 2810 GOTO_OPCODE(ip) @ jump to next instruction 2811 2812/* ------------------------------ */ 2813 .balign 64 2814.L_OP_SGET_OBJECT: /* 0x62 */ 2815/* File: armv5te/OP_SGET_OBJECT.S */ 2816/* File: armv5te/OP_SGET.S */ 2817 /* 2818 * General 32-bit SGET handler. 2819 * 2820 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2821 */ 2822 /* op vAA, field@BBBB */ 2823 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2824 FETCH(r1, 1) @ r1<- field ref BBBB 2825 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2826 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2827 cmp r0, #0 @ is resolved entry null? 2828 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2829.LOP_SGET_OBJECT_finish: @ field ptr in r0 2830 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2831 @ no-op @ acquiring load 2832 mov r2, rINST, lsr #8 @ r2<- AA 2833 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2834 SET_VREG(r1, r2) @ fp[AA]<- r1 2835 GET_INST_OPCODE(ip) @ extract opcode from rINST 2836 GOTO_OPCODE(ip) @ jump to next instruction 2837 2838 2839/* ------------------------------ */ 2840 .balign 64 2841.L_OP_SGET_BOOLEAN: /* 0x63 */ 2842/* File: armv5te/OP_SGET_BOOLEAN.S */ 2843/* File: armv5te/OP_SGET.S */ 2844 /* 2845 * General 32-bit SGET handler. 2846 * 2847 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2848 */ 2849 /* op vAA, field@BBBB */ 2850 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2851 FETCH(r1, 1) @ r1<- field ref BBBB 2852 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2853 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2854 cmp r0, #0 @ is resolved entry null? 2855 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2856.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2857 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2858 @ no-op @ acquiring load 2859 mov r2, rINST, lsr #8 @ r2<- AA 2860 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2861 SET_VREG(r1, r2) @ fp[AA]<- r1 2862 GET_INST_OPCODE(ip) @ extract opcode from rINST 2863 GOTO_OPCODE(ip) @ jump to next instruction 2864 2865 2866/* ------------------------------ */ 2867 .balign 64 2868.L_OP_SGET_BYTE: /* 0x64 */ 2869/* File: armv5te/OP_SGET_BYTE.S */ 2870/* File: armv5te/OP_SGET.S */ 2871 /* 2872 * General 32-bit SGET handler. 2873 * 2874 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2875 */ 2876 /* op vAA, field@BBBB */ 2877 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2878 FETCH(r1, 1) @ r1<- field ref BBBB 2879 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2880 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2881 cmp r0, #0 @ is resolved entry null? 2882 beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2883.LOP_SGET_BYTE_finish: @ field ptr in r0 2884 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2885 @ no-op @ acquiring load 2886 mov r2, rINST, lsr #8 @ r2<- AA 2887 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2888 SET_VREG(r1, r2) @ fp[AA]<- r1 2889 GET_INST_OPCODE(ip) @ extract opcode from rINST 2890 GOTO_OPCODE(ip) @ jump to next instruction 2891 2892 2893/* ------------------------------ */ 2894 .balign 64 2895.L_OP_SGET_CHAR: /* 0x65 */ 2896/* File: armv5te/OP_SGET_CHAR.S */ 2897/* File: armv5te/OP_SGET.S */ 2898 /* 2899 * General 32-bit SGET handler. 2900 * 2901 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2902 */ 2903 /* op vAA, field@BBBB */ 2904 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2905 FETCH(r1, 1) @ r1<- field ref BBBB 2906 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2907 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2908 cmp r0, #0 @ is resolved entry null? 2909 beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2910.LOP_SGET_CHAR_finish: @ field ptr in r0 2911 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2912 @ no-op @ acquiring load 2913 mov r2, rINST, lsr #8 @ r2<- AA 2914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2915 SET_VREG(r1, r2) @ fp[AA]<- r1 2916 GET_INST_OPCODE(ip) @ extract opcode from rINST 2917 GOTO_OPCODE(ip) @ jump to next instruction 2918 2919 2920/* ------------------------------ */ 2921 .balign 64 2922.L_OP_SGET_SHORT: /* 0x66 */ 2923/* File: armv5te/OP_SGET_SHORT.S */ 2924/* File: armv5te/OP_SGET.S */ 2925 /* 2926 * General 32-bit SGET handler. 2927 * 2928 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2929 */ 2930 /* op vAA, field@BBBB */ 2931 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2932 FETCH(r1, 1) @ r1<- field ref BBBB 2933 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2934 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2935 cmp r0, #0 @ is resolved entry null? 2936 beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2937.LOP_SGET_SHORT_finish: @ field ptr in r0 2938 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2939 @ no-op @ acquiring load 2940 mov r2, rINST, lsr #8 @ r2<- AA 2941 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2942 SET_VREG(r1, r2) @ fp[AA]<- r1 2943 GET_INST_OPCODE(ip) @ extract opcode from rINST 2944 GOTO_OPCODE(ip) @ jump to next instruction 2945 2946 2947/* ------------------------------ */ 2948 .balign 64 2949.L_OP_SPUT: /* 0x67 */ 2950/* File: armv5te/OP_SPUT.S */ 2951 /* 2952 * General 32-bit SPUT handler. 2953 * 2954 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2955 */ 2956 /* op vAA, field@BBBB */ 2957 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2958 FETCH(r1, 1) @ r1<- field ref BBBB 2959 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2960 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2961 cmp r0, #0 @ is resolved entry null? 2962 beq .LOP_SPUT_resolve @ yes, do resolve 2963.LOP_SPUT_finish: @ field ptr in r0 2964 mov r2, rINST, lsr #8 @ r2<- AA 2965 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2966 GET_VREG(r1, r2) @ r1<- fp[AA] 2967 GET_INST_OPCODE(ip) @ extract opcode from rINST 2968 @ no-op @ releasing store 2969 str r1, [r0, #offStaticField_value] @ field<- vAA 2970 GOTO_OPCODE(ip) @ jump to next instruction 2971 2972/* ------------------------------ */ 2973 .balign 64 2974.L_OP_SPUT_WIDE: /* 0x68 */ 2975/* File: armv5te/OP_SPUT_WIDE.S */ 2976 /* 2977 * 64-bit SPUT handler. 2978 */ 2979 /* sput-wide vAA, field@BBBB */ 2980 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 2981 FETCH(r1, 1) @ r1<- field ref BBBB 2982 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 2983 mov r9, rINST, lsr #8 @ r9<- AA 2984 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 2985 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2986 cmp r2, #0 @ is resolved entry null? 2987 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 2988.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 2989 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2990 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 2991 GET_INST_OPCODE(r10) @ extract opcode from rINST 2992 .if 0 2993 add r2, r2, #offStaticField_value @ r2<- pointer to data 2994 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 2995 .else 2996 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 2997 .endif 2998 GOTO_OPCODE(r10) @ jump to next instruction 2999 3000/* ------------------------------ */ 3001 .balign 64 3002.L_OP_SPUT_OBJECT: /* 0x69 */ 3003/* File: armv5te/OP_SPUT_OBJECT.S */ 3004 /* 3005 * 32-bit SPUT handler for objects 3006 * 3007 * for: sput-object, sput-object-volatile 3008 */ 3009 /* op vAA, field@BBBB */ 3010 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3011 FETCH(r1, 1) @ r1<- field ref BBBB 3012 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3013 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3014 cmp r0, #0 @ is resolved entry null? 3015 bne .LOP_SPUT_OBJECT_finish @ no, continue 3016 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3017 EXPORT_PC() @ resolve() could throw, so export now 3018 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 3019 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 3020 cmp r0, #0 @ success? 3021 bne .LOP_SPUT_OBJECT_finish @ yes, finish 3022 b common_exceptionThrown @ no, handle exception 3023 3024 3025/* ------------------------------ */ 3026 .balign 64 3027.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3028/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3029/* File: armv5te/OP_SPUT.S */ 3030 /* 3031 * General 32-bit SPUT handler. 3032 * 3033 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3034 */ 3035 /* op vAA, field@BBBB */ 3036 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3037 FETCH(r1, 1) @ r1<- field ref BBBB 3038 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3039 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3040 cmp r0, #0 @ is resolved entry null? 3041 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3042.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3043 mov r2, rINST, lsr #8 @ r2<- AA 3044 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3045 GET_VREG(r1, r2) @ r1<- fp[AA] 3046 GET_INST_OPCODE(ip) @ extract opcode from rINST 3047 @ no-op @ releasing store 3048 str r1, [r0, #offStaticField_value] @ field<- vAA 3049 GOTO_OPCODE(ip) @ jump to next instruction 3050 3051 3052/* ------------------------------ */ 3053 .balign 64 3054.L_OP_SPUT_BYTE: /* 0x6b */ 3055/* File: armv5te/OP_SPUT_BYTE.S */ 3056/* File: armv5te/OP_SPUT.S */ 3057 /* 3058 * General 32-bit SPUT handler. 3059 * 3060 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3061 */ 3062 /* op vAA, field@BBBB */ 3063 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3064 FETCH(r1, 1) @ r1<- field ref BBBB 3065 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3066 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3067 cmp r0, #0 @ is resolved entry null? 3068 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3069.LOP_SPUT_BYTE_finish: @ field ptr in r0 3070 mov r2, rINST, lsr #8 @ r2<- AA 3071 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3072 GET_VREG(r1, r2) @ r1<- fp[AA] 3073 GET_INST_OPCODE(ip) @ extract opcode from rINST 3074 @ no-op @ releasing store 3075 str r1, [r0, #offStaticField_value] @ field<- vAA 3076 GOTO_OPCODE(ip) @ jump to next instruction 3077 3078 3079/* ------------------------------ */ 3080 .balign 64 3081.L_OP_SPUT_CHAR: /* 0x6c */ 3082/* File: armv5te/OP_SPUT_CHAR.S */ 3083/* File: armv5te/OP_SPUT.S */ 3084 /* 3085 * General 32-bit SPUT handler. 3086 * 3087 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3088 */ 3089 /* op vAA, field@BBBB */ 3090 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3091 FETCH(r1, 1) @ r1<- field ref BBBB 3092 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3093 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3094 cmp r0, #0 @ is resolved entry null? 3095 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3096.LOP_SPUT_CHAR_finish: @ field ptr in r0 3097 mov r2, rINST, lsr #8 @ r2<- AA 3098 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3099 GET_VREG(r1, r2) @ r1<- fp[AA] 3100 GET_INST_OPCODE(ip) @ extract opcode from rINST 3101 @ no-op @ releasing store 3102 str r1, [r0, #offStaticField_value] @ field<- vAA 3103 GOTO_OPCODE(ip) @ jump to next instruction 3104 3105 3106/* ------------------------------ */ 3107 .balign 64 3108.L_OP_SPUT_SHORT: /* 0x6d */ 3109/* File: armv5te/OP_SPUT_SHORT.S */ 3110/* File: armv5te/OP_SPUT.S */ 3111 /* 3112 * General 32-bit SPUT handler. 3113 * 3114 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3115 */ 3116 /* op vAA, field@BBBB */ 3117 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3118 FETCH(r1, 1) @ r1<- field ref BBBB 3119 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3120 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3121 cmp r0, #0 @ is resolved entry null? 3122 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3123.LOP_SPUT_SHORT_finish: @ field ptr in r0 3124 mov r2, rINST, lsr #8 @ r2<- AA 3125 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3126 GET_VREG(r1, r2) @ r1<- fp[AA] 3127 GET_INST_OPCODE(ip) @ extract opcode from rINST 3128 @ no-op @ releasing store 3129 str r1, [r0, #offStaticField_value] @ field<- vAA 3130 GOTO_OPCODE(ip) @ jump to next instruction 3131 3132 3133/* ------------------------------ */ 3134 .balign 64 3135.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3136/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3137 /* 3138 * Handle a virtual method call. 3139 * 3140 * for: invoke-virtual, invoke-virtual/range 3141 */ 3142 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3143 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3144 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3145 FETCH(r1, 1) @ r1<- BBBB 3146 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3147 FETCH(r10, 2) @ r10<- GFED or CCCC 3148 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3149 .if (!0) 3150 and r10, r10, #15 @ r10<- D (or stays CCCC) 3151 .endif 3152 cmp r0, #0 @ already resolved? 3153 EXPORT_PC() @ must export for invoke 3154 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3155 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3156 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3157 mov r2, #METHOD_VIRTUAL @ resolver method type 3158 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3159 cmp r0, #0 @ got null? 3160 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3161 b common_exceptionThrown @ yes, handle exception 3162 3163/* ------------------------------ */ 3164 .balign 64 3165.L_OP_INVOKE_SUPER: /* 0x6f */ 3166/* File: armv5te/OP_INVOKE_SUPER.S */ 3167 /* 3168 * Handle a "super" method call. 3169 * 3170 * for: invoke-super, invoke-super/range 3171 */ 3172 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3173 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3174 FETCH(r10, 2) @ r10<- GFED or CCCC 3175 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3176 .if (!0) 3177 and r10, r10, #15 @ r10<- D (or stays CCCC) 3178 .endif 3179 FETCH(r1, 1) @ r1<- BBBB 3180 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3181 GET_VREG(r2, r10) @ r2<- "this" ptr 3182 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3183 cmp r2, #0 @ null "this"? 3184 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3185 beq common_errNullObject @ null "this", throw exception 3186 cmp r0, #0 @ already resolved? 3187 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3188 EXPORT_PC() @ must export for invoke 3189 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3190 b .LOP_INVOKE_SUPER_resolve @ do resolve now 3191 3192/* ------------------------------ */ 3193 .balign 64 3194.L_OP_INVOKE_DIRECT: /* 0x70 */ 3195/* File: armv5te/OP_INVOKE_DIRECT.S */ 3196 /* 3197 * Handle a direct method call. 3198 * 3199 * (We could defer the "is 'this' pointer null" test to the common 3200 * method invocation code, and use a flag to indicate that static 3201 * calls don't count. If we do this as part of copying the arguments 3202 * out we could avoiding loading the first arg twice.) 3203 * 3204 * for: invoke-direct, invoke-direct/range 3205 */ 3206 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3207 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3208 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3209 FETCH(r1, 1) @ r1<- BBBB 3210 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3211 FETCH(r10, 2) @ r10<- GFED or CCCC 3212 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3213 .if (!0) 3214 and r10, r10, #15 @ r10<- D (or stays CCCC) 3215 .endif 3216 cmp r0, #0 @ already resolved? 3217 EXPORT_PC() @ must export for invoke 3218 GET_VREG(r2, r10) @ r2<- "this" ptr 3219 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3220.LOP_INVOKE_DIRECT_finish: 3221 cmp r2, #0 @ null "this" ref? 3222 bne common_invokeMethodNoRange @ no, continue on 3223 b common_errNullObject @ yes, throw exception 3224 3225/* ------------------------------ */ 3226 .balign 64 3227.L_OP_INVOKE_STATIC: /* 0x71 */ 3228/* File: armv5te/OP_INVOKE_STATIC.S */ 3229 /* 3230 * Handle a static method call. 3231 * 3232 * for: invoke-static, invoke-static/range 3233 */ 3234 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3235 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3236 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3237 FETCH(r1, 1) @ r1<- BBBB 3238 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3239 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3240 cmp r0, #0 @ already resolved? 3241 EXPORT_PC() @ must export for invoke 3242 bne common_invokeMethodNoRange @ yes, continue on 32430: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3244 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3245 mov r2, #METHOD_STATIC @ resolver method type 3246 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3247 cmp r0, #0 @ got null? 3248 bne common_invokeMethodNoRange @ no, continue 3249 b common_exceptionThrown @ yes, handle exception 3250 3251/* ------------------------------ */ 3252 .balign 64 3253.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3254/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3255 /* 3256 * Handle an interface method call. 3257 * 3258 * for: invoke-interface, invoke-interface/range 3259 */ 3260 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3261 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3262 FETCH(r2, 2) @ r2<- FEDC or CCCC 3263 FETCH(r1, 1) @ r1<- BBBB 3264 .if (!0) 3265 and r2, r2, #15 @ r2<- C (or stays CCCC) 3266 .endif 3267 EXPORT_PC() @ must export for invoke 3268 GET_VREG(r0, r2) @ r0<- first arg ("this") 3269 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3270 cmp r0, #0 @ null obj? 3271 ldr r2, [rSELF, #offThread_method] @ r2<- method 3272 beq common_errNullObject @ yes, fail 3273 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3274 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3275 cmp r0, #0 @ failed? 3276 beq common_exceptionThrown @ yes, handle exception 3277 b common_invokeMethodNoRange @ jump to common handler 3278 3279/* ------------------------------ */ 3280 .balign 64 3281.L_OP_UNUSED_73: /* 0x73 */ 3282/* File: armv5te/OP_UNUSED_73.S */ 3283/* File: armv5te/unused.S */ 3284 bl common_abort 3285 3286 3287/* ------------------------------ */ 3288 .balign 64 3289.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3290/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3291/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3292 /* 3293 * Handle a virtual method call. 3294 * 3295 * for: invoke-virtual, invoke-virtual/range 3296 */ 3297 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3298 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3299 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3300 FETCH(r1, 1) @ r1<- BBBB 3301 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3302 FETCH(r10, 2) @ r10<- GFED or CCCC 3303 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3304 .if (!1) 3305 and r10, r10, #15 @ r10<- D (or stays CCCC) 3306 .endif 3307 cmp r0, #0 @ already resolved? 3308 EXPORT_PC() @ must export for invoke 3309 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3310 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3311 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3312 mov r2, #METHOD_VIRTUAL @ resolver method type 3313 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3314 cmp r0, #0 @ got null? 3315 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3316 b common_exceptionThrown @ yes, handle exception 3317 3318 3319/* ------------------------------ */ 3320 .balign 64 3321.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3322/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3323/* File: armv5te/OP_INVOKE_SUPER.S */ 3324 /* 3325 * Handle a "super" method call. 3326 * 3327 * for: invoke-super, invoke-super/range 3328 */ 3329 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3330 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3331 FETCH(r10, 2) @ r10<- GFED or CCCC 3332 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3333 .if (!1) 3334 and r10, r10, #15 @ r10<- D (or stays CCCC) 3335 .endif 3336 FETCH(r1, 1) @ r1<- BBBB 3337 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3338 GET_VREG(r2, r10) @ r2<- "this" ptr 3339 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3340 cmp r2, #0 @ null "this"? 3341 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3342 beq common_errNullObject @ null "this", throw exception 3343 cmp r0, #0 @ already resolved? 3344 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3345 EXPORT_PC() @ must export for invoke 3346 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3347 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3348 3349 3350/* ------------------------------ */ 3351 .balign 64 3352.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3353/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3354/* File: armv5te/OP_INVOKE_DIRECT.S */ 3355 /* 3356 * Handle a direct method call. 3357 * 3358 * (We could defer the "is 'this' pointer null" test to the common 3359 * method invocation code, and use a flag to indicate that static 3360 * calls don't count. If we do this as part of copying the arguments 3361 * out we could avoiding loading the first arg twice.) 3362 * 3363 * for: invoke-direct, invoke-direct/range 3364 */ 3365 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3366 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3367 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3368 FETCH(r1, 1) @ r1<- BBBB 3369 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3370 FETCH(r10, 2) @ r10<- GFED or CCCC 3371 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3372 .if (!1) 3373 and r10, r10, #15 @ r10<- D (or stays CCCC) 3374 .endif 3375 cmp r0, #0 @ already resolved? 3376 EXPORT_PC() @ must export for invoke 3377 GET_VREG(r2, r10) @ r2<- "this" ptr 3378 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3379.LOP_INVOKE_DIRECT_RANGE_finish: 3380 cmp r2, #0 @ null "this" ref? 3381 bne common_invokeMethodRange @ no, continue on 3382 b common_errNullObject @ yes, throw exception 3383 3384 3385/* ------------------------------ */ 3386 .balign 64 3387.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3388/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3389/* File: armv5te/OP_INVOKE_STATIC.S */ 3390 /* 3391 * Handle a static method call. 3392 * 3393 * for: invoke-static, invoke-static/range 3394 */ 3395 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3396 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3397 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3398 FETCH(r1, 1) @ r1<- BBBB 3399 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3400 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3401 cmp r0, #0 @ already resolved? 3402 EXPORT_PC() @ must export for invoke 3403 bne common_invokeMethodRange @ yes, continue on 34040: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3405 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3406 mov r2, #METHOD_STATIC @ resolver method type 3407 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3408 cmp r0, #0 @ got null? 3409 bne common_invokeMethodRange @ no, continue 3410 b common_exceptionThrown @ yes, handle exception 3411 3412 3413/* ------------------------------ */ 3414 .balign 64 3415.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3416/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3417/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3418 /* 3419 * Handle an interface method call. 3420 * 3421 * for: invoke-interface, invoke-interface/range 3422 */ 3423 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3424 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3425 FETCH(r2, 2) @ r2<- FEDC or CCCC 3426 FETCH(r1, 1) @ r1<- BBBB 3427 .if (!1) 3428 and r2, r2, #15 @ r2<- C (or stays CCCC) 3429 .endif 3430 EXPORT_PC() @ must export for invoke 3431 GET_VREG(r0, r2) @ r0<- first arg ("this") 3432 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3433 cmp r0, #0 @ null obj? 3434 ldr r2, [rSELF, #offThread_method] @ r2<- method 3435 beq common_errNullObject @ yes, fail 3436 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3437 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3438 cmp r0, #0 @ failed? 3439 beq common_exceptionThrown @ yes, handle exception 3440 b common_invokeMethodRange @ jump to common handler 3441 3442 3443/* ------------------------------ */ 3444 .balign 64 3445.L_OP_UNUSED_79: /* 0x79 */ 3446/* File: armv5te/OP_UNUSED_79.S */ 3447/* File: armv5te/unused.S */ 3448 bl common_abort 3449 3450 3451/* ------------------------------ */ 3452 .balign 64 3453.L_OP_UNUSED_7A: /* 0x7a */ 3454/* File: armv5te/OP_UNUSED_7A.S */ 3455/* File: armv5te/unused.S */ 3456 bl common_abort 3457 3458 3459/* ------------------------------ */ 3460 .balign 64 3461.L_OP_NEG_INT: /* 0x7b */ 3462/* File: armv6t2/OP_NEG_INT.S */ 3463/* File: armv6t2/unop.S */ 3464 /* 3465 * Generic 32-bit unary operation. Provide an "instr" line that 3466 * specifies an instruction that performs "result = op r0". 3467 * This could be an ARM instruction or a function call. 3468 * 3469 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3470 * int-to-byte, int-to-char, int-to-short 3471 */ 3472 /* unop vA, vB */ 3473 mov r3, rINST, lsr #12 @ r3<- B 3474 ubfx r9, rINST, #8, #4 @ r9<- A 3475 GET_VREG(r0, r3) @ r0<- vB 3476 @ optional op; may set condition codes 3477 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3478 rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3479 GET_INST_OPCODE(ip) @ extract opcode from rINST 3480 SET_VREG(r0, r9) @ vAA<- r0 3481 GOTO_OPCODE(ip) @ jump to next instruction 3482 /* 8-9 instructions */ 3483 3484 3485/* ------------------------------ */ 3486 .balign 64 3487.L_OP_NOT_INT: /* 0x7c */ 3488/* File: armv6t2/OP_NOT_INT.S */ 3489/* File: armv6t2/unop.S */ 3490 /* 3491 * Generic 32-bit unary operation. Provide an "instr" line that 3492 * specifies an instruction that performs "result = op r0". 3493 * This could be an ARM instruction or a function call. 3494 * 3495 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3496 * int-to-byte, int-to-char, int-to-short 3497 */ 3498 /* unop vA, vB */ 3499 mov r3, rINST, lsr #12 @ r3<- B 3500 ubfx r9, rINST, #8, #4 @ r9<- A 3501 GET_VREG(r0, r3) @ r0<- vB 3502 @ optional op; may set condition codes 3503 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3504 mvn r0, r0 @ r0<- op, r0-r3 changed 3505 GET_INST_OPCODE(ip) @ extract opcode from rINST 3506 SET_VREG(r0, r9) @ vAA<- r0 3507 GOTO_OPCODE(ip) @ jump to next instruction 3508 /* 8-9 instructions */ 3509 3510 3511/* ------------------------------ */ 3512 .balign 64 3513.L_OP_NEG_LONG: /* 0x7d */ 3514/* File: armv6t2/OP_NEG_LONG.S */ 3515/* File: armv6t2/unopWide.S */ 3516 /* 3517 * Generic 64-bit unary operation. Provide an "instr" line that 3518 * specifies an instruction that performs "result = op r0/r1". 3519 * This could be an ARM instruction or a function call. 3520 * 3521 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3522 */ 3523 /* unop vA, vB */ 3524 mov r3, rINST, lsr #12 @ r3<- B 3525 ubfx r9, rINST, #8, #4 @ r9<- A 3526 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3527 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3528 ldmia r3, {r0-r1} @ r0/r1<- vAA 3529 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3530 rsbs r0, r0, #0 @ optional op; may set condition codes 3531 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3532 GET_INST_OPCODE(ip) @ extract opcode from rINST 3533 stmia r9, {r0-r1} @ vAA<- r0/r1 3534 GOTO_OPCODE(ip) @ jump to next instruction 3535 /* 10-11 instructions */ 3536 3537 3538/* ------------------------------ */ 3539 .balign 64 3540.L_OP_NOT_LONG: /* 0x7e */ 3541/* File: armv6t2/OP_NOT_LONG.S */ 3542/* File: armv6t2/unopWide.S */ 3543 /* 3544 * Generic 64-bit unary operation. Provide an "instr" line that 3545 * specifies an instruction that performs "result = op r0/r1". 3546 * This could be an ARM instruction or a function call. 3547 * 3548 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3549 */ 3550 /* unop vA, vB */ 3551 mov r3, rINST, lsr #12 @ r3<- B 3552 ubfx r9, rINST, #8, #4 @ r9<- A 3553 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3554 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3555 ldmia r3, {r0-r1} @ r0/r1<- vAA 3556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3557 mvn r0, r0 @ optional op; may set condition codes 3558 mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3559 GET_INST_OPCODE(ip) @ extract opcode from rINST 3560 stmia r9, {r0-r1} @ vAA<- r0/r1 3561 GOTO_OPCODE(ip) @ jump to next instruction 3562 /* 10-11 instructions */ 3563 3564 3565/* ------------------------------ */ 3566 .balign 64 3567.L_OP_NEG_FLOAT: /* 0x7f */ 3568/* File: armv6t2/OP_NEG_FLOAT.S */ 3569/* File: armv6t2/unop.S */ 3570 /* 3571 * Generic 32-bit unary operation. Provide an "instr" line that 3572 * specifies an instruction that performs "result = op r0". 3573 * This could be an ARM instruction or a function call. 3574 * 3575 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3576 * int-to-byte, int-to-char, int-to-short 3577 */ 3578 /* unop vA, vB */ 3579 mov r3, rINST, lsr #12 @ r3<- B 3580 ubfx r9, rINST, #8, #4 @ r9<- A 3581 GET_VREG(r0, r3) @ r0<- vB 3582 @ optional op; may set condition codes 3583 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3584 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3585 GET_INST_OPCODE(ip) @ extract opcode from rINST 3586 SET_VREG(r0, r9) @ vAA<- r0 3587 GOTO_OPCODE(ip) @ jump to next instruction 3588 /* 8-9 instructions */ 3589 3590 3591/* ------------------------------ */ 3592 .balign 64 3593.L_OP_NEG_DOUBLE: /* 0x80 */ 3594/* File: armv6t2/OP_NEG_DOUBLE.S */ 3595/* File: armv6t2/unopWide.S */ 3596 /* 3597 * Generic 64-bit unary operation. Provide an "instr" line that 3598 * specifies an instruction that performs "result = op r0/r1". 3599 * This could be an ARM instruction or a function call. 3600 * 3601 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3602 */ 3603 /* unop vA, vB */ 3604 mov r3, rINST, lsr #12 @ r3<- B 3605 ubfx r9, rINST, #8, #4 @ r9<- A 3606 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3607 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3608 ldmia r3, {r0-r1} @ r0/r1<- vAA 3609 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3610 @ optional op; may set condition codes 3611 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3612 GET_INST_OPCODE(ip) @ extract opcode from rINST 3613 stmia r9, {r0-r1} @ vAA<- r0/r1 3614 GOTO_OPCODE(ip) @ jump to next instruction 3615 /* 10-11 instructions */ 3616 3617 3618/* ------------------------------ */ 3619 .balign 64 3620.L_OP_INT_TO_LONG: /* 0x81 */ 3621/* File: armv6t2/OP_INT_TO_LONG.S */ 3622/* File: armv6t2/unopWider.S */ 3623 /* 3624 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3625 * that specifies an instruction that performs "result = op r0", where 3626 * "result" is a 64-bit quantity in r0/r1. 3627 * 3628 * For: int-to-long, int-to-double, float-to-long, float-to-double 3629 */ 3630 /* unop vA, vB */ 3631 mov r3, rINST, lsr #12 @ r3<- B 3632 ubfx r9, rINST, #8, #4 @ r9<- A 3633 GET_VREG(r0, r3) @ r0<- vB 3634 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3635 @ optional op; may set condition codes 3636 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3637 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3638 GET_INST_OPCODE(ip) @ extract opcode from rINST 3639 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3640 GOTO_OPCODE(ip) @ jump to next instruction 3641 /* 9-10 instructions */ 3642 3643 3644/* ------------------------------ */ 3645 .balign 64 3646.L_OP_INT_TO_FLOAT: /* 0x82 */ 3647/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3648/* File: arm-vfp/funop.S */ 3649 /* 3650 * Generic 32-bit unary floating-point operation. Provide an "instr" 3651 * line that specifies an instruction that performs "s1 = op s0". 3652 * 3653 * for: int-to-float, float-to-int 3654 */ 3655 /* unop vA, vB */ 3656 mov r3, rINST, lsr #12 @ r3<- B 3657 mov r9, rINST, lsr #8 @ r9<- A+ 3658 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3659 flds s0, [r3] @ s0<- vB 3660 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3661 and r9, r9, #15 @ r9<- A 3662 fsitos s1, s0 @ s1<- op 3663 GET_INST_OPCODE(ip) @ extract opcode from rINST 3664 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3665 fsts s1, [r9] @ vA<- s1 3666 GOTO_OPCODE(ip) @ jump to next instruction 3667 3668 3669/* ------------------------------ */ 3670 .balign 64 3671.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3672/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3673/* File: arm-vfp/funopWider.S */ 3674 /* 3675 * Generic 32bit-to-64bit floating point unary operation. Provide an 3676 * "instr" line that specifies an instruction that performs "d0 = op s0". 3677 * 3678 * For: int-to-double, float-to-double 3679 */ 3680 /* unop vA, vB */ 3681 mov r3, rINST, lsr #12 @ r3<- B 3682 mov r9, rINST, lsr #8 @ r9<- A+ 3683 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3684 flds s0, [r3] @ s0<- vB 3685 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3686 and r9, r9, #15 @ r9<- A 3687 fsitod d0, s0 @ d0<- op 3688 GET_INST_OPCODE(ip) @ extract opcode from rINST 3689 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3690 fstd d0, [r9] @ vA<- d0 3691 GOTO_OPCODE(ip) @ jump to next instruction 3692 3693 3694/* ------------------------------ */ 3695 .balign 64 3696.L_OP_LONG_TO_INT: /* 0x84 */ 3697/* File: armv5te/OP_LONG_TO_INT.S */ 3698/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3699/* File: armv5te/OP_MOVE.S */ 3700 /* for move, move-object, long-to-int */ 3701 /* op vA, vB */ 3702 mov r1, rINST, lsr #12 @ r1<- B from 15:12 3703 mov r0, rINST, lsr #8 @ r0<- A from 11:8 3704 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3705 GET_VREG(r2, r1) @ r2<- fp[B] 3706 and r0, r0, #15 3707 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3708 SET_VREG(r2, r0) @ fp[A]<- r2 3709 GOTO_OPCODE(ip) @ execute next instruction 3710 3711 3712/* ------------------------------ */ 3713 .balign 64 3714.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3715/* File: armv6t2/OP_LONG_TO_FLOAT.S */ 3716/* File: armv6t2/unopNarrower.S */ 3717 /* 3718 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3719 * that specifies an instruction that performs "result = op r0/r1", where 3720 * "result" is a 32-bit quantity in r0. 3721 * 3722 * For: long-to-float, double-to-int, double-to-float 3723 * 3724 * (This would work for long-to-int, but that instruction is actually 3725 * an exact match for OP_MOVE.) 3726 */ 3727 /* unop vA, vB */ 3728 mov r3, rINST, lsr #12 @ r3<- B 3729 ubfx r9, rINST, #8, #4 @ r9<- A 3730 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3731 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3732 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3733 @ optional op; may set condition codes 3734 bl __aeabi_l2f @ r0<- op, r0-r3 changed 3735 GET_INST_OPCODE(ip) @ extract opcode from rINST 3736 SET_VREG(r0, r9) @ vA<- r0 3737 GOTO_OPCODE(ip) @ jump to next instruction 3738 /* 9-10 instructions */ 3739 3740 3741/* ------------------------------ */ 3742 .balign 64 3743.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3744/* File: armv6t2/OP_LONG_TO_DOUBLE.S */ 3745/* File: armv6t2/unopWide.S */ 3746 /* 3747 * Generic 64-bit unary operation. Provide an "instr" line that 3748 * specifies an instruction that performs "result = op r0/r1". 3749 * This could be an ARM instruction or a function call. 3750 * 3751 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3752 */ 3753 /* unop vA, vB */ 3754 mov r3, rINST, lsr #12 @ r3<- B 3755 ubfx r9, rINST, #8, #4 @ r9<- A 3756 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3757 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3758 ldmia r3, {r0-r1} @ r0/r1<- vAA 3759 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3760 @ optional op; may set condition codes 3761 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3762 GET_INST_OPCODE(ip) @ extract opcode from rINST 3763 stmia r9, {r0-r1} @ vAA<- r0/r1 3764 GOTO_OPCODE(ip) @ jump to next instruction 3765 /* 10-11 instructions */ 3766 3767 3768/* ------------------------------ */ 3769 .balign 64 3770.L_OP_FLOAT_TO_INT: /* 0x87 */ 3771/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3772/* File: arm-vfp/funop.S */ 3773 /* 3774 * Generic 32-bit unary floating-point operation. Provide an "instr" 3775 * line that specifies an instruction that performs "s1 = op s0". 3776 * 3777 * for: int-to-float, float-to-int 3778 */ 3779 /* unop vA, vB */ 3780 mov r3, rINST, lsr #12 @ r3<- B 3781 mov r9, rINST, lsr #8 @ r9<- A+ 3782 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3783 flds s0, [r3] @ s0<- vB 3784 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3785 and r9, r9, #15 @ r9<- A 3786 ftosizs s1, s0 @ s1<- op 3787 GET_INST_OPCODE(ip) @ extract opcode from rINST 3788 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3789 fsts s1, [r9] @ vA<- s1 3790 GOTO_OPCODE(ip) @ jump to next instruction 3791 3792 3793/* ------------------------------ */ 3794 .balign 64 3795.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3796/* File: armv6t2/OP_FLOAT_TO_LONG.S */ 3797@include "armv6t2/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3798/* File: armv6t2/unopWider.S */ 3799 /* 3800 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3801 * that specifies an instruction that performs "result = op r0", where 3802 * "result" is a 64-bit quantity in r0/r1. 3803 * 3804 * For: int-to-long, int-to-double, float-to-long, float-to-double 3805 */ 3806 /* unop vA, vB */ 3807 mov r3, rINST, lsr #12 @ r3<- B 3808 ubfx r9, rINST, #8, #4 @ r9<- A 3809 GET_VREG(r0, r3) @ r0<- vB 3810 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3811 @ optional op; may set condition codes 3812 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3813 bl f2l_doconv @ r0<- op, r0-r3 changed 3814 GET_INST_OPCODE(ip) @ extract opcode from rINST 3815 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3816 GOTO_OPCODE(ip) @ jump to next instruction 3817 /* 9-10 instructions */ 3818 3819 3820 3821/* ------------------------------ */ 3822 .balign 64 3823.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3824/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3825/* File: arm-vfp/funopWider.S */ 3826 /* 3827 * Generic 32bit-to-64bit floating point unary operation. Provide an 3828 * "instr" line that specifies an instruction that performs "d0 = op s0". 3829 * 3830 * For: int-to-double, float-to-double 3831 */ 3832 /* unop vA, vB */ 3833 mov r3, rINST, lsr #12 @ r3<- B 3834 mov r9, rINST, lsr #8 @ r9<- A+ 3835 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3836 flds s0, [r3] @ s0<- vB 3837 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3838 and r9, r9, #15 @ r9<- A 3839 fcvtds d0, s0 @ d0<- op 3840 GET_INST_OPCODE(ip) @ extract opcode from rINST 3841 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3842 fstd d0, [r9] @ vA<- d0 3843 GOTO_OPCODE(ip) @ jump to next instruction 3844 3845 3846/* ------------------------------ */ 3847 .balign 64 3848.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3849/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3850/* File: arm-vfp/funopNarrower.S */ 3851 /* 3852 * Generic 64bit-to-32bit unary floating point operation. Provide an 3853 * "instr" line that specifies an instruction that performs "s0 = op d0". 3854 * 3855 * For: double-to-int, double-to-float 3856 */ 3857 /* unop vA, vB */ 3858 mov r3, rINST, lsr #12 @ r3<- B 3859 mov r9, rINST, lsr #8 @ r9<- A+ 3860 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3861 fldd d0, [r3] @ d0<- vB 3862 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3863 and r9, r9, #15 @ r9<- A 3864 ftosizd s0, d0 @ s0<- op 3865 GET_INST_OPCODE(ip) @ extract opcode from rINST 3866 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3867 fsts s0, [r9] @ vA<- s0 3868 GOTO_OPCODE(ip) @ jump to next instruction 3869 3870 3871/* ------------------------------ */ 3872 .balign 64 3873.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3874/* File: armv6t2/OP_DOUBLE_TO_LONG.S */ 3875@include "armv6t2/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3876/* File: armv6t2/unopWide.S */ 3877 /* 3878 * Generic 64-bit unary operation. Provide an "instr" line that 3879 * specifies an instruction that performs "result = op r0/r1". 3880 * This could be an ARM instruction or a function call. 3881 * 3882 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3883 */ 3884 /* unop vA, vB */ 3885 mov r3, rINST, lsr #12 @ r3<- B 3886 ubfx r9, rINST, #8, #4 @ r9<- A 3887 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3888 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3889 ldmia r3, {r0-r1} @ r0/r1<- vAA 3890 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3891 @ optional op; may set condition codes 3892 bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3893 GET_INST_OPCODE(ip) @ extract opcode from rINST 3894 stmia r9, {r0-r1} @ vAA<- r0/r1 3895 GOTO_OPCODE(ip) @ jump to next instruction 3896 /* 10-11 instructions */ 3897 3898 3899 3900/* ------------------------------ */ 3901 .balign 64 3902.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3903/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3904/* File: arm-vfp/funopNarrower.S */ 3905 /* 3906 * Generic 64bit-to-32bit unary floating point operation. Provide an 3907 * "instr" line that specifies an instruction that performs "s0 = op d0". 3908 * 3909 * For: double-to-int, double-to-float 3910 */ 3911 /* unop vA, vB */ 3912 mov r3, rINST, lsr #12 @ r3<- B 3913 mov r9, rINST, lsr #8 @ r9<- A+ 3914 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3915 fldd d0, [r3] @ d0<- vB 3916 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3917 and r9, r9, #15 @ r9<- A 3918 fcvtsd s0, d0 @ s0<- op 3919 GET_INST_OPCODE(ip) @ extract opcode from rINST 3920 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3921 fsts s0, [r9] @ vA<- s0 3922 GOTO_OPCODE(ip) @ jump to next instruction 3923 3924 3925/* ------------------------------ */ 3926 .balign 64 3927.L_OP_INT_TO_BYTE: /* 0x8d */ 3928/* File: armv6t2/OP_INT_TO_BYTE.S */ 3929/* File: armv6t2/unop.S */ 3930 /* 3931 * Generic 32-bit unary operation. Provide an "instr" line that 3932 * specifies an instruction that performs "result = op r0". 3933 * This could be an ARM instruction or a function call. 3934 * 3935 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3936 * int-to-byte, int-to-char, int-to-short 3937 */ 3938 /* unop vA, vB */ 3939 mov r3, rINST, lsr #12 @ r3<- B 3940 ubfx r9, rINST, #8, #4 @ r9<- A 3941 GET_VREG(r0, r3) @ r0<- vB 3942 @ optional op; may set condition codes 3943 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3944 sxtb r0, r0 @ r0<- op, r0-r3 changed 3945 GET_INST_OPCODE(ip) @ extract opcode from rINST 3946 SET_VREG(r0, r9) @ vAA<- r0 3947 GOTO_OPCODE(ip) @ jump to next instruction 3948 /* 8-9 instructions */ 3949 3950 3951/* ------------------------------ */ 3952 .balign 64 3953.L_OP_INT_TO_CHAR: /* 0x8e */ 3954/* File: armv6t2/OP_INT_TO_CHAR.S */ 3955/* File: armv6t2/unop.S */ 3956 /* 3957 * Generic 32-bit unary operation. Provide an "instr" line that 3958 * specifies an instruction that performs "result = op r0". 3959 * This could be an ARM instruction or a function call. 3960 * 3961 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3962 * int-to-byte, int-to-char, int-to-short 3963 */ 3964 /* unop vA, vB */ 3965 mov r3, rINST, lsr #12 @ r3<- B 3966 ubfx r9, rINST, #8, #4 @ r9<- A 3967 GET_VREG(r0, r3) @ r0<- vB 3968 @ optional op; may set condition codes 3969 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3970 uxth r0, r0 @ r0<- op, r0-r3 changed 3971 GET_INST_OPCODE(ip) @ extract opcode from rINST 3972 SET_VREG(r0, r9) @ vAA<- r0 3973 GOTO_OPCODE(ip) @ jump to next instruction 3974 /* 8-9 instructions */ 3975 3976 3977/* ------------------------------ */ 3978 .balign 64 3979.L_OP_INT_TO_SHORT: /* 0x8f */ 3980/* File: armv6t2/OP_INT_TO_SHORT.S */ 3981/* File: armv6t2/unop.S */ 3982 /* 3983 * Generic 32-bit unary operation. Provide an "instr" line that 3984 * specifies an instruction that performs "result = op r0". 3985 * This could be an ARM instruction or a function call. 3986 * 3987 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3988 * int-to-byte, int-to-char, int-to-short 3989 */ 3990 /* unop vA, vB */ 3991 mov r3, rINST, lsr #12 @ r3<- B 3992 ubfx r9, rINST, #8, #4 @ r9<- A 3993 GET_VREG(r0, r3) @ r0<- vB 3994 @ optional op; may set condition codes 3995 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3996 sxth r0, r0 @ r0<- op, r0-r3 changed 3997 GET_INST_OPCODE(ip) @ extract opcode from rINST 3998 SET_VREG(r0, r9) @ vAA<- r0 3999 GOTO_OPCODE(ip) @ jump to next instruction 4000 /* 8-9 instructions */ 4001 4002 4003/* ------------------------------ */ 4004 .balign 64 4005.L_OP_ADD_INT: /* 0x90 */ 4006/* File: armv5te/OP_ADD_INT.S */ 4007/* File: armv5te/binop.S */ 4008 /* 4009 * Generic 32-bit binary operation. Provide an "instr" line that 4010 * specifies an instruction that performs "result = r0 op r1". 4011 * This could be an ARM instruction or a function call. (If the result 4012 * comes back in a register other than r0, you can override "result".) 4013 * 4014 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4015 * vCC (r1). Useful for integer division and modulus. Note that we 4016 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4017 * handles it correctly. 4018 * 4019 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4020 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4021 * mul-float, div-float, rem-float 4022 */ 4023 /* binop vAA, vBB, vCC */ 4024 FETCH(r0, 1) @ r0<- CCBB 4025 mov r9, rINST, lsr #8 @ r9<- AA 4026 mov r3, r0, lsr #8 @ r3<- CC 4027 and r2, r0, #255 @ r2<- BB 4028 GET_VREG(r1, r3) @ r1<- vCC 4029 GET_VREG(r0, r2) @ r0<- vBB 4030 .if 0 4031 cmp r1, #0 @ is second operand zero? 4032 beq common_errDivideByZero 4033 .endif 4034 4035 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4036 @ optional op; may set condition codes 4037 add r0, r0, r1 @ r0<- op, r0-r3 changed 4038 GET_INST_OPCODE(ip) @ extract opcode from rINST 4039 SET_VREG(r0, r9) @ vAA<- r0 4040 GOTO_OPCODE(ip) @ jump to next instruction 4041 /* 11-14 instructions */ 4042 4043 4044/* ------------------------------ */ 4045 .balign 64 4046.L_OP_SUB_INT: /* 0x91 */ 4047/* File: armv5te/OP_SUB_INT.S */ 4048/* File: armv5te/binop.S */ 4049 /* 4050 * Generic 32-bit binary operation. Provide an "instr" line that 4051 * specifies an instruction that performs "result = r0 op r1". 4052 * This could be an ARM instruction or a function call. (If the result 4053 * comes back in a register other than r0, you can override "result".) 4054 * 4055 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4056 * vCC (r1). Useful for integer division and modulus. Note that we 4057 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4058 * handles it correctly. 4059 * 4060 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4061 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4062 * mul-float, div-float, rem-float 4063 */ 4064 /* binop vAA, vBB, vCC */ 4065 FETCH(r0, 1) @ r0<- CCBB 4066 mov r9, rINST, lsr #8 @ r9<- AA 4067 mov r3, r0, lsr #8 @ r3<- CC 4068 and r2, r0, #255 @ r2<- BB 4069 GET_VREG(r1, r3) @ r1<- vCC 4070 GET_VREG(r0, r2) @ r0<- vBB 4071 .if 0 4072 cmp r1, #0 @ is second operand zero? 4073 beq common_errDivideByZero 4074 .endif 4075 4076 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4077 @ optional op; may set condition codes 4078 sub r0, r0, r1 @ r0<- op, r0-r3 changed 4079 GET_INST_OPCODE(ip) @ extract opcode from rINST 4080 SET_VREG(r0, r9) @ vAA<- r0 4081 GOTO_OPCODE(ip) @ jump to next instruction 4082 /* 11-14 instructions */ 4083 4084 4085/* ------------------------------ */ 4086 .balign 64 4087.L_OP_MUL_INT: /* 0x92 */ 4088/* File: armv5te/OP_MUL_INT.S */ 4089/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4090/* File: armv5te/binop.S */ 4091 /* 4092 * Generic 32-bit binary operation. Provide an "instr" line that 4093 * specifies an instruction that performs "result = r0 op r1". 4094 * This could be an ARM instruction or a function call. (If the result 4095 * comes back in a register other than r0, you can override "result".) 4096 * 4097 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4098 * vCC (r1). Useful for integer division and modulus. Note that we 4099 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4100 * handles it correctly. 4101 * 4102 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4103 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4104 * mul-float, div-float, rem-float 4105 */ 4106 /* binop vAA, vBB, vCC */ 4107 FETCH(r0, 1) @ r0<- CCBB 4108 mov r9, rINST, lsr #8 @ r9<- AA 4109 mov r3, r0, lsr #8 @ r3<- CC 4110 and r2, r0, #255 @ r2<- BB 4111 GET_VREG(r1, r3) @ r1<- vCC 4112 GET_VREG(r0, r2) @ r0<- vBB 4113 .if 0 4114 cmp r1, #0 @ is second operand zero? 4115 beq common_errDivideByZero 4116 .endif 4117 4118 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4119 @ optional op; may set condition codes 4120 mul r0, r1, r0 @ r0<- op, r0-r3 changed 4121 GET_INST_OPCODE(ip) @ extract opcode from rINST 4122 SET_VREG(r0, r9) @ vAA<- r0 4123 GOTO_OPCODE(ip) @ jump to next instruction 4124 /* 11-14 instructions */ 4125 4126 4127/* ------------------------------ */ 4128 .balign 64 4129.L_OP_DIV_INT: /* 0x93 */ 4130/* File: armv5te/OP_DIV_INT.S */ 4131/* File: armv5te/binop.S */ 4132 /* 4133 * Generic 32-bit binary operation. Provide an "instr" line that 4134 * specifies an instruction that performs "result = r0 op r1". 4135 * This could be an ARM instruction or a function call. (If the result 4136 * comes back in a register other than r0, you can override "result".) 4137 * 4138 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4139 * vCC (r1). Useful for integer division and modulus. Note that we 4140 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4141 * handles it correctly. 4142 * 4143 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4144 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4145 * mul-float, div-float, rem-float 4146 */ 4147 /* binop vAA, vBB, vCC */ 4148 FETCH(r0, 1) @ r0<- CCBB 4149 mov r9, rINST, lsr #8 @ r9<- AA 4150 mov r3, r0, lsr #8 @ r3<- CC 4151 and r2, r0, #255 @ r2<- BB 4152 GET_VREG(r1, r3) @ r1<- vCC 4153 GET_VREG(r0, r2) @ r0<- vBB 4154 .if 1 4155 cmp r1, #0 @ is second operand zero? 4156 beq common_errDivideByZero 4157 .endif 4158 4159 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4160 @ optional op; may set condition codes 4161 bl __aeabi_idiv @ r0<- op, r0-r3 changed 4162 GET_INST_OPCODE(ip) @ extract opcode from rINST 4163 SET_VREG(r0, r9) @ vAA<- r0 4164 GOTO_OPCODE(ip) @ jump to next instruction 4165 /* 11-14 instructions */ 4166 4167 4168/* ------------------------------ */ 4169 .balign 64 4170.L_OP_REM_INT: /* 0x94 */ 4171/* File: armv5te/OP_REM_INT.S */ 4172/* idivmod returns quotient in r0 and remainder in r1 */ 4173/* File: armv5te/binop.S */ 4174 /* 4175 * Generic 32-bit binary operation. Provide an "instr" line that 4176 * specifies an instruction that performs "result = r0 op r1". 4177 * This could be an ARM instruction or a function call. (If the result 4178 * comes back in a register other than r0, you can override "result".) 4179 * 4180 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4181 * vCC (r1). Useful for integer division and modulus. Note that we 4182 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4183 * handles it correctly. 4184 * 4185 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4186 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4187 * mul-float, div-float, rem-float 4188 */ 4189 /* binop vAA, vBB, vCC */ 4190 FETCH(r0, 1) @ r0<- CCBB 4191 mov r9, rINST, lsr #8 @ r9<- AA 4192 mov r3, r0, lsr #8 @ r3<- CC 4193 and r2, r0, #255 @ r2<- BB 4194 GET_VREG(r1, r3) @ r1<- vCC 4195 GET_VREG(r0, r2) @ r0<- vBB 4196 .if 1 4197 cmp r1, #0 @ is second operand zero? 4198 beq common_errDivideByZero 4199 .endif 4200 4201 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4202 @ optional op; may set condition codes 4203 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4204 GET_INST_OPCODE(ip) @ extract opcode from rINST 4205 SET_VREG(r1, r9) @ vAA<- r1 4206 GOTO_OPCODE(ip) @ jump to next instruction 4207 /* 11-14 instructions */ 4208 4209 4210/* ------------------------------ */ 4211 .balign 64 4212.L_OP_AND_INT: /* 0x95 */ 4213/* File: armv5te/OP_AND_INT.S */ 4214/* File: armv5te/binop.S */ 4215 /* 4216 * Generic 32-bit binary operation. Provide an "instr" line that 4217 * specifies an instruction that performs "result = r0 op r1". 4218 * This could be an ARM instruction or a function call. (If the result 4219 * comes back in a register other than r0, you can override "result".) 4220 * 4221 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4222 * vCC (r1). Useful for integer division and modulus. Note that we 4223 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4224 * handles it correctly. 4225 * 4226 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4227 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4228 * mul-float, div-float, rem-float 4229 */ 4230 /* binop vAA, vBB, vCC */ 4231 FETCH(r0, 1) @ r0<- CCBB 4232 mov r9, rINST, lsr #8 @ r9<- AA 4233 mov r3, r0, lsr #8 @ r3<- CC 4234 and r2, r0, #255 @ r2<- BB 4235 GET_VREG(r1, r3) @ r1<- vCC 4236 GET_VREG(r0, r2) @ r0<- vBB 4237 .if 0 4238 cmp r1, #0 @ is second operand zero? 4239 beq common_errDivideByZero 4240 .endif 4241 4242 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4243 @ optional op; may set condition codes 4244 and r0, r0, r1 @ r0<- op, r0-r3 changed 4245 GET_INST_OPCODE(ip) @ extract opcode from rINST 4246 SET_VREG(r0, r9) @ vAA<- r0 4247 GOTO_OPCODE(ip) @ jump to next instruction 4248 /* 11-14 instructions */ 4249 4250 4251/* ------------------------------ */ 4252 .balign 64 4253.L_OP_OR_INT: /* 0x96 */ 4254/* File: armv5te/OP_OR_INT.S */ 4255/* File: armv5te/binop.S */ 4256 /* 4257 * Generic 32-bit binary operation. Provide an "instr" line that 4258 * specifies an instruction that performs "result = r0 op r1". 4259 * This could be an ARM instruction or a function call. (If the result 4260 * comes back in a register other than r0, you can override "result".) 4261 * 4262 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4263 * vCC (r1). Useful for integer division and modulus. Note that we 4264 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4265 * handles it correctly. 4266 * 4267 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4268 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4269 * mul-float, div-float, rem-float 4270 */ 4271 /* binop vAA, vBB, vCC */ 4272 FETCH(r0, 1) @ r0<- CCBB 4273 mov r9, rINST, lsr #8 @ r9<- AA 4274 mov r3, r0, lsr #8 @ r3<- CC 4275 and r2, r0, #255 @ r2<- BB 4276 GET_VREG(r1, r3) @ r1<- vCC 4277 GET_VREG(r0, r2) @ r0<- vBB 4278 .if 0 4279 cmp r1, #0 @ is second operand zero? 4280 beq common_errDivideByZero 4281 .endif 4282 4283 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4284 @ optional op; may set condition codes 4285 orr r0, r0, r1 @ r0<- op, r0-r3 changed 4286 GET_INST_OPCODE(ip) @ extract opcode from rINST 4287 SET_VREG(r0, r9) @ vAA<- r0 4288 GOTO_OPCODE(ip) @ jump to next instruction 4289 /* 11-14 instructions */ 4290 4291 4292/* ------------------------------ */ 4293 .balign 64 4294.L_OP_XOR_INT: /* 0x97 */ 4295/* File: armv5te/OP_XOR_INT.S */ 4296/* File: armv5te/binop.S */ 4297 /* 4298 * Generic 32-bit binary operation. Provide an "instr" line that 4299 * specifies an instruction that performs "result = r0 op r1". 4300 * This could be an ARM instruction or a function call. (If the result 4301 * comes back in a register other than r0, you can override "result".) 4302 * 4303 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4304 * vCC (r1). Useful for integer division and modulus. Note that we 4305 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4306 * handles it correctly. 4307 * 4308 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4309 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4310 * mul-float, div-float, rem-float 4311 */ 4312 /* binop vAA, vBB, vCC */ 4313 FETCH(r0, 1) @ r0<- CCBB 4314 mov r9, rINST, lsr #8 @ r9<- AA 4315 mov r3, r0, lsr #8 @ r3<- CC 4316 and r2, r0, #255 @ r2<- BB 4317 GET_VREG(r1, r3) @ r1<- vCC 4318 GET_VREG(r0, r2) @ r0<- vBB 4319 .if 0 4320 cmp r1, #0 @ is second operand zero? 4321 beq common_errDivideByZero 4322 .endif 4323 4324 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4325 @ optional op; may set condition codes 4326 eor r0, r0, r1 @ r0<- op, r0-r3 changed 4327 GET_INST_OPCODE(ip) @ extract opcode from rINST 4328 SET_VREG(r0, r9) @ vAA<- r0 4329 GOTO_OPCODE(ip) @ jump to next instruction 4330 /* 11-14 instructions */ 4331 4332 4333/* ------------------------------ */ 4334 .balign 64 4335.L_OP_SHL_INT: /* 0x98 */ 4336/* File: armv5te/OP_SHL_INT.S */ 4337/* File: armv5te/binop.S */ 4338 /* 4339 * Generic 32-bit binary operation. Provide an "instr" line that 4340 * specifies an instruction that performs "result = r0 op r1". 4341 * This could be an ARM instruction or a function call. (If the result 4342 * comes back in a register other than r0, you can override "result".) 4343 * 4344 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4345 * vCC (r1). Useful for integer division and modulus. Note that we 4346 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4347 * handles it correctly. 4348 * 4349 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4350 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4351 * mul-float, div-float, rem-float 4352 */ 4353 /* binop vAA, vBB, vCC */ 4354 FETCH(r0, 1) @ r0<- CCBB 4355 mov r9, rINST, lsr #8 @ r9<- AA 4356 mov r3, r0, lsr #8 @ r3<- CC 4357 and r2, r0, #255 @ r2<- BB 4358 GET_VREG(r1, r3) @ r1<- vCC 4359 GET_VREG(r0, r2) @ r0<- vBB 4360 .if 0 4361 cmp r1, #0 @ is second operand zero? 4362 beq common_errDivideByZero 4363 .endif 4364 4365 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4366 and r1, r1, #31 @ optional op; may set condition codes 4367 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4368 GET_INST_OPCODE(ip) @ extract opcode from rINST 4369 SET_VREG(r0, r9) @ vAA<- r0 4370 GOTO_OPCODE(ip) @ jump to next instruction 4371 /* 11-14 instructions */ 4372 4373 4374/* ------------------------------ */ 4375 .balign 64 4376.L_OP_SHR_INT: /* 0x99 */ 4377/* File: armv5te/OP_SHR_INT.S */ 4378/* File: armv5te/binop.S */ 4379 /* 4380 * Generic 32-bit binary operation. Provide an "instr" line that 4381 * specifies an instruction that performs "result = r0 op r1". 4382 * This could be an ARM instruction or a function call. (If the result 4383 * comes back in a register other than r0, you can override "result".) 4384 * 4385 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4386 * vCC (r1). Useful for integer division and modulus. Note that we 4387 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4388 * handles it correctly. 4389 * 4390 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4391 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4392 * mul-float, div-float, rem-float 4393 */ 4394 /* binop vAA, vBB, vCC */ 4395 FETCH(r0, 1) @ r0<- CCBB 4396 mov r9, rINST, lsr #8 @ r9<- AA 4397 mov r3, r0, lsr #8 @ r3<- CC 4398 and r2, r0, #255 @ r2<- BB 4399 GET_VREG(r1, r3) @ r1<- vCC 4400 GET_VREG(r0, r2) @ r0<- vBB 4401 .if 0 4402 cmp r1, #0 @ is second operand zero? 4403 beq common_errDivideByZero 4404 .endif 4405 4406 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4407 and r1, r1, #31 @ optional op; may set condition codes 4408 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4409 GET_INST_OPCODE(ip) @ extract opcode from rINST 4410 SET_VREG(r0, r9) @ vAA<- r0 4411 GOTO_OPCODE(ip) @ jump to next instruction 4412 /* 11-14 instructions */ 4413 4414 4415/* ------------------------------ */ 4416 .balign 64 4417.L_OP_USHR_INT: /* 0x9a */ 4418/* File: armv5te/OP_USHR_INT.S */ 4419/* File: armv5te/binop.S */ 4420 /* 4421 * Generic 32-bit binary operation. Provide an "instr" line that 4422 * specifies an instruction that performs "result = r0 op r1". 4423 * This could be an ARM instruction or a function call. (If the result 4424 * comes back in a register other than r0, you can override "result".) 4425 * 4426 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4427 * vCC (r1). Useful for integer division and modulus. Note that we 4428 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4429 * handles it correctly. 4430 * 4431 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4432 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4433 * mul-float, div-float, rem-float 4434 */ 4435 /* binop vAA, vBB, vCC */ 4436 FETCH(r0, 1) @ r0<- CCBB 4437 mov r9, rINST, lsr #8 @ r9<- AA 4438 mov r3, r0, lsr #8 @ r3<- CC 4439 and r2, r0, #255 @ r2<- BB 4440 GET_VREG(r1, r3) @ r1<- vCC 4441 GET_VREG(r0, r2) @ r0<- vBB 4442 .if 0 4443 cmp r1, #0 @ is second operand zero? 4444 beq common_errDivideByZero 4445 .endif 4446 4447 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4448 and r1, r1, #31 @ optional op; may set condition codes 4449 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4450 GET_INST_OPCODE(ip) @ extract opcode from rINST 4451 SET_VREG(r0, r9) @ vAA<- r0 4452 GOTO_OPCODE(ip) @ jump to next instruction 4453 /* 11-14 instructions */ 4454 4455 4456/* ------------------------------ */ 4457 .balign 64 4458.L_OP_ADD_LONG: /* 0x9b */ 4459/* File: armv5te/OP_ADD_LONG.S */ 4460/* File: armv5te/binopWide.S */ 4461 /* 4462 * Generic 64-bit binary operation. Provide an "instr" line that 4463 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4464 * This could be an ARM instruction or a function call. (If the result 4465 * comes back in a register other than r0, you can override "result".) 4466 * 4467 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4468 * vCC (r1). Useful for integer division and modulus. 4469 * 4470 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4471 * xor-long, add-double, sub-double, mul-double, div-double, 4472 * rem-double 4473 * 4474 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4475 */ 4476 /* binop vAA, vBB, vCC */ 4477 FETCH(r0, 1) @ r0<- CCBB 4478 mov r9, rINST, lsr #8 @ r9<- AA 4479 and r2, r0, #255 @ r2<- BB 4480 mov r3, r0, lsr #8 @ r3<- CC 4481 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4482 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4483 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4484 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4485 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4486 .if 0 4487 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4488 beq common_errDivideByZero 4489 .endif 4490 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4491 4492 adds r0, r0, r2 @ optional op; may set condition codes 4493 adc r1, r1, r3 @ result<- op, r0-r3 changed 4494 GET_INST_OPCODE(ip) @ extract opcode from rINST 4495 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4496 GOTO_OPCODE(ip) @ jump to next instruction 4497 /* 14-17 instructions */ 4498 4499 4500/* ------------------------------ */ 4501 .balign 64 4502.L_OP_SUB_LONG: /* 0x9c */ 4503/* File: armv5te/OP_SUB_LONG.S */ 4504/* File: armv5te/binopWide.S */ 4505 /* 4506 * Generic 64-bit binary operation. Provide an "instr" line that 4507 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4508 * This could be an ARM instruction or a function call. (If the result 4509 * comes back in a register other than r0, you can override "result".) 4510 * 4511 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4512 * vCC (r1). Useful for integer division and modulus. 4513 * 4514 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4515 * xor-long, add-double, sub-double, mul-double, div-double, 4516 * rem-double 4517 * 4518 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4519 */ 4520 /* binop vAA, vBB, vCC */ 4521 FETCH(r0, 1) @ r0<- CCBB 4522 mov r9, rINST, lsr #8 @ r9<- AA 4523 and r2, r0, #255 @ r2<- BB 4524 mov r3, r0, lsr #8 @ r3<- CC 4525 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4526 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4527 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4528 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4529 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4530 .if 0 4531 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4532 beq common_errDivideByZero 4533 .endif 4534 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4535 4536 subs r0, r0, r2 @ optional op; may set condition codes 4537 sbc r1, r1, r3 @ result<- op, r0-r3 changed 4538 GET_INST_OPCODE(ip) @ extract opcode from rINST 4539 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4540 GOTO_OPCODE(ip) @ jump to next instruction 4541 /* 14-17 instructions */ 4542 4543 4544/* ------------------------------ */ 4545 .balign 64 4546.L_OP_MUL_LONG: /* 0x9d */ 4547/* File: armv5te/OP_MUL_LONG.S */ 4548 /* 4549 * Signed 64-bit integer multiply. 4550 * 4551 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4552 * WX 4553 * x YZ 4554 * -------- 4555 * ZW ZX 4556 * YW YX 4557 * 4558 * The low word of the result holds ZX, the high word holds 4559 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4560 * it doesn't fit in the low 64 bits. 4561 * 4562 * Unlike most ARM math operations, multiply instructions have 4563 * restrictions on using the same register more than once (Rd and Rm 4564 * cannot be the same). 4565 */ 4566 /* mul-long vAA, vBB, vCC */ 4567 FETCH(r0, 1) @ r0<- CCBB 4568 and r2, r0, #255 @ r2<- BB 4569 mov r3, r0, lsr #8 @ r3<- CC 4570 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4571 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4572 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4573 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4574 mul ip, r2, r1 @ ip<- ZxW 4575 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4576 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4577 mov r0, rINST, lsr #8 @ r0<- AA 4578 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4579 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4580 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4581 b .LOP_MUL_LONG_finish 4582 4583/* ------------------------------ */ 4584 .balign 64 4585.L_OP_DIV_LONG: /* 0x9e */ 4586/* File: armv5te/OP_DIV_LONG.S */ 4587/* File: armv5te/binopWide.S */ 4588 /* 4589 * Generic 64-bit binary operation. Provide an "instr" line that 4590 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4591 * This could be an ARM instruction or a function call. (If the result 4592 * comes back in a register other than r0, you can override "result".) 4593 * 4594 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4595 * vCC (r1). Useful for integer division and modulus. 4596 * 4597 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4598 * xor-long, add-double, sub-double, mul-double, div-double, 4599 * rem-double 4600 * 4601 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4602 */ 4603 /* binop vAA, vBB, vCC */ 4604 FETCH(r0, 1) @ r0<- CCBB 4605 mov r9, rINST, lsr #8 @ r9<- AA 4606 and r2, r0, #255 @ r2<- BB 4607 mov r3, r0, lsr #8 @ r3<- CC 4608 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4609 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4610 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4611 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4612 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4613 .if 1 4614 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4615 beq common_errDivideByZero 4616 .endif 4617 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4618 4619 @ optional op; may set condition codes 4620 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4621 GET_INST_OPCODE(ip) @ extract opcode from rINST 4622 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4623 GOTO_OPCODE(ip) @ jump to next instruction 4624 /* 14-17 instructions */ 4625 4626 4627/* ------------------------------ */ 4628 .balign 64 4629.L_OP_REM_LONG: /* 0x9f */ 4630/* File: armv5te/OP_REM_LONG.S */ 4631/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4632/* File: armv5te/binopWide.S */ 4633 /* 4634 * Generic 64-bit binary operation. Provide an "instr" line that 4635 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4636 * This could be an ARM instruction or a function call. (If the result 4637 * comes back in a register other than r0, you can override "result".) 4638 * 4639 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4640 * vCC (r1). Useful for integer division and modulus. 4641 * 4642 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4643 * xor-long, add-double, sub-double, mul-double, div-double, 4644 * rem-double 4645 * 4646 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4647 */ 4648 /* binop vAA, vBB, vCC */ 4649 FETCH(r0, 1) @ r0<- CCBB 4650 mov r9, rINST, lsr #8 @ r9<- AA 4651 and r2, r0, #255 @ r2<- BB 4652 mov r3, r0, lsr #8 @ r3<- CC 4653 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4654 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4655 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4656 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4657 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4658 .if 1 4659 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4660 beq common_errDivideByZero 4661 .endif 4662 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4663 4664 @ optional op; may set condition codes 4665 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4666 GET_INST_OPCODE(ip) @ extract opcode from rINST 4667 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4668 GOTO_OPCODE(ip) @ jump to next instruction 4669 /* 14-17 instructions */ 4670 4671 4672/* ------------------------------ */ 4673 .balign 64 4674.L_OP_AND_LONG: /* 0xa0 */ 4675/* File: armv5te/OP_AND_LONG.S */ 4676/* File: armv5te/binopWide.S */ 4677 /* 4678 * Generic 64-bit binary operation. Provide an "instr" line that 4679 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4680 * This could be an ARM instruction or a function call. (If the result 4681 * comes back in a register other than r0, you can override "result".) 4682 * 4683 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4684 * vCC (r1). Useful for integer division and modulus. 4685 * 4686 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4687 * xor-long, add-double, sub-double, mul-double, div-double, 4688 * rem-double 4689 * 4690 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4691 */ 4692 /* binop vAA, vBB, vCC */ 4693 FETCH(r0, 1) @ r0<- CCBB 4694 mov r9, rINST, lsr #8 @ r9<- AA 4695 and r2, r0, #255 @ r2<- BB 4696 mov r3, r0, lsr #8 @ r3<- CC 4697 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4698 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4699 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4700 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4701 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4702 .if 0 4703 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4704 beq common_errDivideByZero 4705 .endif 4706 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4707 4708 and r0, r0, r2 @ optional op; may set condition codes 4709 and r1, r1, r3 @ result<- op, r0-r3 changed 4710 GET_INST_OPCODE(ip) @ extract opcode from rINST 4711 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4712 GOTO_OPCODE(ip) @ jump to next instruction 4713 /* 14-17 instructions */ 4714 4715 4716/* ------------------------------ */ 4717 .balign 64 4718.L_OP_OR_LONG: /* 0xa1 */ 4719/* File: armv5te/OP_OR_LONG.S */ 4720/* File: armv5te/binopWide.S */ 4721 /* 4722 * Generic 64-bit binary operation. Provide an "instr" line that 4723 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4724 * This could be an ARM instruction or a function call. (If the result 4725 * comes back in a register other than r0, you can override "result".) 4726 * 4727 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4728 * vCC (r1). Useful for integer division and modulus. 4729 * 4730 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4731 * xor-long, add-double, sub-double, mul-double, div-double, 4732 * rem-double 4733 * 4734 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4735 */ 4736 /* binop vAA, vBB, vCC */ 4737 FETCH(r0, 1) @ r0<- CCBB 4738 mov r9, rINST, lsr #8 @ r9<- AA 4739 and r2, r0, #255 @ r2<- BB 4740 mov r3, r0, lsr #8 @ r3<- CC 4741 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4742 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4743 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4744 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4745 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4746 .if 0 4747 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4748 beq common_errDivideByZero 4749 .endif 4750 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4751 4752 orr r0, r0, r2 @ optional op; may set condition codes 4753 orr r1, r1, r3 @ result<- op, r0-r3 changed 4754 GET_INST_OPCODE(ip) @ extract opcode from rINST 4755 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4756 GOTO_OPCODE(ip) @ jump to next instruction 4757 /* 14-17 instructions */ 4758 4759 4760/* ------------------------------ */ 4761 .balign 64 4762.L_OP_XOR_LONG: /* 0xa2 */ 4763/* File: armv5te/OP_XOR_LONG.S */ 4764/* File: armv5te/binopWide.S */ 4765 /* 4766 * Generic 64-bit binary operation. Provide an "instr" line that 4767 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4768 * This could be an ARM instruction or a function call. (If the result 4769 * comes back in a register other than r0, you can override "result".) 4770 * 4771 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4772 * vCC (r1). Useful for integer division and modulus. 4773 * 4774 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4775 * xor-long, add-double, sub-double, mul-double, div-double, 4776 * rem-double 4777 * 4778 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4779 */ 4780 /* binop vAA, vBB, vCC */ 4781 FETCH(r0, 1) @ r0<- CCBB 4782 mov r9, rINST, lsr #8 @ r9<- AA 4783 and r2, r0, #255 @ r2<- BB 4784 mov r3, r0, lsr #8 @ r3<- CC 4785 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4786 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4787 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4788 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4789 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4790 .if 0 4791 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4792 beq common_errDivideByZero 4793 .endif 4794 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4795 4796 eor r0, r0, r2 @ optional op; may set condition codes 4797 eor r1, r1, r3 @ result<- op, r0-r3 changed 4798 GET_INST_OPCODE(ip) @ extract opcode from rINST 4799 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4800 GOTO_OPCODE(ip) @ jump to next instruction 4801 /* 14-17 instructions */ 4802 4803 4804/* ------------------------------ */ 4805 .balign 64 4806.L_OP_SHL_LONG: /* 0xa3 */ 4807/* File: armv5te/OP_SHL_LONG.S */ 4808 /* 4809 * Long integer shift. This is different from the generic 32/64-bit 4810 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4811 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4812 * 6 bits of the shift distance. 4813 */ 4814 /* shl-long vAA, vBB, vCC */ 4815 FETCH(r0, 1) @ r0<- CCBB 4816 mov r9, rINST, lsr #8 @ r9<- AA 4817 and r3, r0, #255 @ r3<- BB 4818 mov r0, r0, lsr #8 @ r0<- CC 4819 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4820 GET_VREG(r2, r0) @ r2<- vCC 4821 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4822 and r2, r2, #63 @ r2<- r2 & 0x3f 4823 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4824 4825 mov r1, r1, asl r2 @ r1<- r1 << r2 4826 rsb r3, r2, #32 @ r3<- 32 - r2 4827 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4828 subs ip, r2, #32 @ ip<- r2 - 32 4829 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4830 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4831 b .LOP_SHL_LONG_finish 4832 4833/* ------------------------------ */ 4834 .balign 64 4835.L_OP_SHR_LONG: /* 0xa4 */ 4836/* File: armv5te/OP_SHR_LONG.S */ 4837 /* 4838 * Long integer shift. This is different from the generic 32/64-bit 4839 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4840 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4841 * 6 bits of the shift distance. 4842 */ 4843 /* shr-long vAA, vBB, vCC */ 4844 FETCH(r0, 1) @ r0<- CCBB 4845 mov r9, rINST, lsr #8 @ r9<- AA 4846 and r3, r0, #255 @ r3<- BB 4847 mov r0, r0, lsr #8 @ r0<- CC 4848 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4849 GET_VREG(r2, r0) @ r2<- vCC 4850 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4851 and r2, r2, #63 @ r0<- r0 & 0x3f 4852 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4853 4854 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4855 rsb r3, r2, #32 @ r3<- 32 - r2 4856 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4857 subs ip, r2, #32 @ ip<- r2 - 32 4858 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4859 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4860 b .LOP_SHR_LONG_finish 4861 4862/* ------------------------------ */ 4863 .balign 64 4864.L_OP_USHR_LONG: /* 0xa5 */ 4865/* File: armv5te/OP_USHR_LONG.S */ 4866 /* 4867 * Long integer shift. This is different from the generic 32/64-bit 4868 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4869 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4870 * 6 bits of the shift distance. 4871 */ 4872 /* ushr-long vAA, vBB, vCC */ 4873 FETCH(r0, 1) @ r0<- CCBB 4874 mov r9, rINST, lsr #8 @ r9<- AA 4875 and r3, r0, #255 @ r3<- BB 4876 mov r0, r0, lsr #8 @ r0<- CC 4877 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4878 GET_VREG(r2, r0) @ r2<- vCC 4879 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4880 and r2, r2, #63 @ r0<- r0 & 0x3f 4881 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4882 4883 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4884 rsb r3, r2, #32 @ r3<- 32 - r2 4885 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4886 subs ip, r2, #32 @ ip<- r2 - 32 4887 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4888 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4889 b .LOP_USHR_LONG_finish 4890 4891/* ------------------------------ */ 4892 .balign 64 4893.L_OP_ADD_FLOAT: /* 0xa6 */ 4894/* File: arm-vfp/OP_ADD_FLOAT.S */ 4895/* File: arm-vfp/fbinop.S */ 4896 /* 4897 * Generic 32-bit floating-point operation. Provide an "instr" line that 4898 * specifies an instruction that performs "s2 = s0 op s1". Because we 4899 * use the "softfp" ABI, this must be an instruction, not a function call. 4900 * 4901 * For: add-float, sub-float, mul-float, div-float 4902 */ 4903 /* floatop vAA, vBB, vCC */ 4904 FETCH(r0, 1) @ r0<- CCBB 4905 mov r9, rINST, lsr #8 @ r9<- AA 4906 mov r3, r0, lsr #8 @ r3<- CC 4907 and r2, r0, #255 @ r2<- BB 4908 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4909 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4910 flds s1, [r3] @ s1<- vCC 4911 flds s0, [r2] @ s0<- vBB 4912 4913 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4914 fadds s2, s0, s1 @ s2<- op 4915 GET_INST_OPCODE(ip) @ extract opcode from rINST 4916 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4917 fsts s2, [r9] @ vAA<- s2 4918 GOTO_OPCODE(ip) @ jump to next instruction 4919 4920 4921/* ------------------------------ */ 4922 .balign 64 4923.L_OP_SUB_FLOAT: /* 0xa7 */ 4924/* File: arm-vfp/OP_SUB_FLOAT.S */ 4925/* File: arm-vfp/fbinop.S */ 4926 /* 4927 * Generic 32-bit floating-point operation. Provide an "instr" line that 4928 * specifies an instruction that performs "s2 = s0 op s1". Because we 4929 * use the "softfp" ABI, this must be an instruction, not a function call. 4930 * 4931 * For: add-float, sub-float, mul-float, div-float 4932 */ 4933 /* floatop vAA, vBB, vCC */ 4934 FETCH(r0, 1) @ r0<- CCBB 4935 mov r9, rINST, lsr #8 @ r9<- AA 4936 mov r3, r0, lsr #8 @ r3<- CC 4937 and r2, r0, #255 @ r2<- BB 4938 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4939 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4940 flds s1, [r3] @ s1<- vCC 4941 flds s0, [r2] @ s0<- vBB 4942 4943 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4944 fsubs s2, s0, s1 @ s2<- op 4945 GET_INST_OPCODE(ip) @ extract opcode from rINST 4946 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4947 fsts s2, [r9] @ vAA<- s2 4948 GOTO_OPCODE(ip) @ jump to next instruction 4949 4950 4951/* ------------------------------ */ 4952 .balign 64 4953.L_OP_MUL_FLOAT: /* 0xa8 */ 4954/* File: arm-vfp/OP_MUL_FLOAT.S */ 4955/* File: arm-vfp/fbinop.S */ 4956 /* 4957 * Generic 32-bit floating-point operation. Provide an "instr" line that 4958 * specifies an instruction that performs "s2 = s0 op s1". Because we 4959 * use the "softfp" ABI, this must be an instruction, not a function call. 4960 * 4961 * For: add-float, sub-float, mul-float, div-float 4962 */ 4963 /* floatop vAA, vBB, vCC */ 4964 FETCH(r0, 1) @ r0<- CCBB 4965 mov r9, rINST, lsr #8 @ r9<- AA 4966 mov r3, r0, lsr #8 @ r3<- CC 4967 and r2, r0, #255 @ r2<- BB 4968 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4969 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4970 flds s1, [r3] @ s1<- vCC 4971 flds s0, [r2] @ s0<- vBB 4972 4973 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4974 fmuls s2, s0, s1 @ s2<- op 4975 GET_INST_OPCODE(ip) @ extract opcode from rINST 4976 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4977 fsts s2, [r9] @ vAA<- s2 4978 GOTO_OPCODE(ip) @ jump to next instruction 4979 4980 4981/* ------------------------------ */ 4982 .balign 64 4983.L_OP_DIV_FLOAT: /* 0xa9 */ 4984/* File: arm-vfp/OP_DIV_FLOAT.S */ 4985/* File: arm-vfp/fbinop.S */ 4986 /* 4987 * Generic 32-bit floating-point operation. Provide an "instr" line that 4988 * specifies an instruction that performs "s2 = s0 op s1". Because we 4989 * use the "softfp" ABI, this must be an instruction, not a function call. 4990 * 4991 * For: add-float, sub-float, mul-float, div-float 4992 */ 4993 /* floatop vAA, vBB, vCC */ 4994 FETCH(r0, 1) @ r0<- CCBB 4995 mov r9, rINST, lsr #8 @ r9<- AA 4996 mov r3, r0, lsr #8 @ r3<- CC 4997 and r2, r0, #255 @ r2<- BB 4998 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4999 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5000 flds s1, [r3] @ s1<- vCC 5001 flds s0, [r2] @ s0<- vBB 5002 5003 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5004 fdivs s2, s0, s1 @ s2<- op 5005 GET_INST_OPCODE(ip) @ extract opcode from rINST 5006 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5007 fsts s2, [r9] @ vAA<- s2 5008 GOTO_OPCODE(ip) @ jump to next instruction 5009 5010 5011/* ------------------------------ */ 5012 .balign 64 5013.L_OP_REM_FLOAT: /* 0xaa */ 5014/* File: armv5te/OP_REM_FLOAT.S */ 5015/* EABI doesn't define a float remainder function, but libm does */ 5016/* File: armv5te/binop.S */ 5017 /* 5018 * Generic 32-bit binary operation. Provide an "instr" line that 5019 * specifies an instruction that performs "result = r0 op r1". 5020 * This could be an ARM instruction or a function call. (If the result 5021 * comes back in a register other than r0, you can override "result".) 5022 * 5023 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5024 * vCC (r1). Useful for integer division and modulus. Note that we 5025 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5026 * handles it correctly. 5027 * 5028 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5029 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5030 * mul-float, div-float, rem-float 5031 */ 5032 /* binop vAA, vBB, vCC */ 5033 FETCH(r0, 1) @ r0<- CCBB 5034 mov r9, rINST, lsr #8 @ r9<- AA 5035 mov r3, r0, lsr #8 @ r3<- CC 5036 and r2, r0, #255 @ r2<- BB 5037 GET_VREG(r1, r3) @ r1<- vCC 5038 GET_VREG(r0, r2) @ r0<- vBB 5039 .if 0 5040 cmp r1, #0 @ is second operand zero? 5041 beq common_errDivideByZero 5042 .endif 5043 5044 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5045 @ optional op; may set condition codes 5046 bl fmodf @ r0<- op, r0-r3 changed 5047 GET_INST_OPCODE(ip) @ extract opcode from rINST 5048 SET_VREG(r0, r9) @ vAA<- r0 5049 GOTO_OPCODE(ip) @ jump to next instruction 5050 /* 11-14 instructions */ 5051 5052 5053/* ------------------------------ */ 5054 .balign 64 5055.L_OP_ADD_DOUBLE: /* 0xab */ 5056/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5057/* File: arm-vfp/fbinopWide.S */ 5058 /* 5059 * Generic 64-bit double-precision floating point binary operation. 5060 * Provide an "instr" line that specifies an instruction that performs 5061 * "d2 = d0 op d1". 5062 * 5063 * for: add-double, sub-double, mul-double, div-double 5064 */ 5065 /* doubleop vAA, vBB, vCC */ 5066 FETCH(r0, 1) @ r0<- CCBB 5067 mov r9, rINST, lsr #8 @ r9<- AA 5068 mov r3, r0, lsr #8 @ r3<- CC 5069 and r2, r0, #255 @ r2<- BB 5070 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5071 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5072 fldd d1, [r3] @ d1<- vCC 5073 fldd d0, [r2] @ d0<- vBB 5074 5075 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5076 faddd d2, d0, d1 @ s2<- op 5077 GET_INST_OPCODE(ip) @ extract opcode from rINST 5078 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5079 fstd d2, [r9] @ vAA<- d2 5080 GOTO_OPCODE(ip) @ jump to next instruction 5081 5082 5083/* ------------------------------ */ 5084 .balign 64 5085.L_OP_SUB_DOUBLE: /* 0xac */ 5086/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5087/* File: arm-vfp/fbinopWide.S */ 5088 /* 5089 * Generic 64-bit double-precision floating point binary operation. 5090 * Provide an "instr" line that specifies an instruction that performs 5091 * "d2 = d0 op d1". 5092 * 5093 * for: add-double, sub-double, mul-double, div-double 5094 */ 5095 /* doubleop vAA, vBB, vCC */ 5096 FETCH(r0, 1) @ r0<- CCBB 5097 mov r9, rINST, lsr #8 @ r9<- AA 5098 mov r3, r0, lsr #8 @ r3<- CC 5099 and r2, r0, #255 @ r2<- BB 5100 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5101 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5102 fldd d1, [r3] @ d1<- vCC 5103 fldd d0, [r2] @ d0<- vBB 5104 5105 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5106 fsubd d2, d0, d1 @ s2<- op 5107 GET_INST_OPCODE(ip) @ extract opcode from rINST 5108 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5109 fstd d2, [r9] @ vAA<- d2 5110 GOTO_OPCODE(ip) @ jump to next instruction 5111 5112 5113/* ------------------------------ */ 5114 .balign 64 5115.L_OP_MUL_DOUBLE: /* 0xad */ 5116/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5117/* File: arm-vfp/fbinopWide.S */ 5118 /* 5119 * Generic 64-bit double-precision floating point binary operation. 5120 * Provide an "instr" line that specifies an instruction that performs 5121 * "d2 = d0 op d1". 5122 * 5123 * for: add-double, sub-double, mul-double, div-double 5124 */ 5125 /* doubleop vAA, vBB, vCC */ 5126 FETCH(r0, 1) @ r0<- CCBB 5127 mov r9, rINST, lsr #8 @ r9<- AA 5128 mov r3, r0, lsr #8 @ r3<- CC 5129 and r2, r0, #255 @ r2<- BB 5130 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5131 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5132 fldd d1, [r3] @ d1<- vCC 5133 fldd d0, [r2] @ d0<- vBB 5134 5135 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5136 fmuld d2, d0, d1 @ s2<- op 5137 GET_INST_OPCODE(ip) @ extract opcode from rINST 5138 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5139 fstd d2, [r9] @ vAA<- d2 5140 GOTO_OPCODE(ip) @ jump to next instruction 5141 5142 5143/* ------------------------------ */ 5144 .balign 64 5145.L_OP_DIV_DOUBLE: /* 0xae */ 5146/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5147/* File: arm-vfp/fbinopWide.S */ 5148 /* 5149 * Generic 64-bit double-precision floating point binary operation. 5150 * Provide an "instr" line that specifies an instruction that performs 5151 * "d2 = d0 op d1". 5152 * 5153 * for: add-double, sub-double, mul-double, div-double 5154 */ 5155 /* doubleop vAA, vBB, vCC */ 5156 FETCH(r0, 1) @ r0<- CCBB 5157 mov r9, rINST, lsr #8 @ r9<- AA 5158 mov r3, r0, lsr #8 @ r3<- CC 5159 and r2, r0, #255 @ r2<- BB 5160 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5161 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5162 fldd d1, [r3] @ d1<- vCC 5163 fldd d0, [r2] @ d0<- vBB 5164 5165 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5166 fdivd d2, d0, d1 @ s2<- op 5167 GET_INST_OPCODE(ip) @ extract opcode from rINST 5168 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5169 fstd d2, [r9] @ vAA<- d2 5170 GOTO_OPCODE(ip) @ jump to next instruction 5171 5172 5173/* ------------------------------ */ 5174 .balign 64 5175.L_OP_REM_DOUBLE: /* 0xaf */ 5176/* File: armv5te/OP_REM_DOUBLE.S */ 5177/* EABI doesn't define a double remainder function, but libm does */ 5178/* File: armv5te/binopWide.S */ 5179 /* 5180 * Generic 64-bit binary operation. Provide an "instr" line that 5181 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5182 * This could be an ARM instruction or a function call. (If the result 5183 * comes back in a register other than r0, you can override "result".) 5184 * 5185 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5186 * vCC (r1). Useful for integer division and modulus. 5187 * 5188 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5189 * xor-long, add-double, sub-double, mul-double, div-double, 5190 * rem-double 5191 * 5192 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5193 */ 5194 /* binop vAA, vBB, vCC */ 5195 FETCH(r0, 1) @ r0<- CCBB 5196 mov r9, rINST, lsr #8 @ r9<- AA 5197 and r2, r0, #255 @ r2<- BB 5198 mov r3, r0, lsr #8 @ r3<- CC 5199 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5200 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5201 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5202 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5203 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5204 .if 0 5205 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5206 beq common_errDivideByZero 5207 .endif 5208 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5209 5210 @ optional op; may set condition codes 5211 bl fmod @ result<- op, r0-r3 changed 5212 GET_INST_OPCODE(ip) @ extract opcode from rINST 5213 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5214 GOTO_OPCODE(ip) @ jump to next instruction 5215 /* 14-17 instructions */ 5216 5217 5218/* ------------------------------ */ 5219 .balign 64 5220.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5221/* File: armv6t2/OP_ADD_INT_2ADDR.S */ 5222/* File: armv6t2/binop2addr.S */ 5223 /* 5224 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5225 * that specifies an instruction that performs "result = r0 op r1". 5226 * This could be an ARM instruction or a function call. (If the result 5227 * comes back in a register other than r0, you can override "result".) 5228 * 5229 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5230 * vCC (r1). Useful for integer division and modulus. 5231 * 5232 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5233 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5234 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5235 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5236 */ 5237 /* binop/2addr vA, vB */ 5238 mov r3, rINST, lsr #12 @ r3<- B 5239 ubfx r9, rINST, #8, #4 @ r9<- A 5240 GET_VREG(r1, r3) @ r1<- vB 5241 GET_VREG(r0, r9) @ r0<- vA 5242 .if 0 5243 cmp r1, #0 @ is second operand zero? 5244 beq common_errDivideByZero 5245 .endif 5246 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5247 5248 @ optional op; may set condition codes 5249 add r0, r0, r1 @ r0<- op, r0-r3 changed 5250 GET_INST_OPCODE(ip) @ extract opcode from rINST 5251 SET_VREG(r0, r9) @ vAA<- r0 5252 GOTO_OPCODE(ip) @ jump to next instruction 5253 /* 10-13 instructions */ 5254 5255 5256/* ------------------------------ */ 5257 .balign 64 5258.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5259/* File: armv6t2/OP_SUB_INT_2ADDR.S */ 5260/* File: armv6t2/binop2addr.S */ 5261 /* 5262 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5263 * that specifies an instruction that performs "result = r0 op r1". 5264 * This could be an ARM instruction or a function call. (If the result 5265 * comes back in a register other than r0, you can override "result".) 5266 * 5267 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5268 * vCC (r1). Useful for integer division and modulus. 5269 * 5270 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5271 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5272 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5273 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5274 */ 5275 /* binop/2addr vA, vB */ 5276 mov r3, rINST, lsr #12 @ r3<- B 5277 ubfx r9, rINST, #8, #4 @ r9<- A 5278 GET_VREG(r1, r3) @ r1<- vB 5279 GET_VREG(r0, r9) @ r0<- vA 5280 .if 0 5281 cmp r1, #0 @ is second operand zero? 5282 beq common_errDivideByZero 5283 .endif 5284 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5285 5286 @ optional op; may set condition codes 5287 sub r0, r0, r1 @ r0<- op, r0-r3 changed 5288 GET_INST_OPCODE(ip) @ extract opcode from rINST 5289 SET_VREG(r0, r9) @ vAA<- r0 5290 GOTO_OPCODE(ip) @ jump to next instruction 5291 /* 10-13 instructions */ 5292 5293 5294/* ------------------------------ */ 5295 .balign 64 5296.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5297/* File: armv6t2/OP_MUL_INT_2ADDR.S */ 5298/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5299/* File: armv6t2/binop2addr.S */ 5300 /* 5301 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5302 * that specifies an instruction that performs "result = r0 op r1". 5303 * This could be an ARM instruction or a function call. (If the result 5304 * comes back in a register other than r0, you can override "result".) 5305 * 5306 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5307 * vCC (r1). Useful for integer division and modulus. 5308 * 5309 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5310 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5311 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5312 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5313 */ 5314 /* binop/2addr vA, vB */ 5315 mov r3, rINST, lsr #12 @ r3<- B 5316 ubfx r9, rINST, #8, #4 @ r9<- A 5317 GET_VREG(r1, r3) @ r1<- vB 5318 GET_VREG(r0, r9) @ r0<- vA 5319 .if 0 5320 cmp r1, #0 @ is second operand zero? 5321 beq common_errDivideByZero 5322 .endif 5323 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5324 5325 @ optional op; may set condition codes 5326 mul r0, r1, r0 @ r0<- op, r0-r3 changed 5327 GET_INST_OPCODE(ip) @ extract opcode from rINST 5328 SET_VREG(r0, r9) @ vAA<- r0 5329 GOTO_OPCODE(ip) @ jump to next instruction 5330 /* 10-13 instructions */ 5331 5332 5333/* ------------------------------ */ 5334 .balign 64 5335.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5336/* File: armv6t2/OP_DIV_INT_2ADDR.S */ 5337/* File: armv6t2/binop2addr.S */ 5338 /* 5339 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5340 * that specifies an instruction that performs "result = r0 op r1". 5341 * This could be an ARM instruction or a function call. (If the result 5342 * comes back in a register other than r0, you can override "result".) 5343 * 5344 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5345 * vCC (r1). Useful for integer division and modulus. 5346 * 5347 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5348 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5349 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5350 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5351 */ 5352 /* binop/2addr vA, vB */ 5353 mov r3, rINST, lsr #12 @ r3<- B 5354 ubfx r9, rINST, #8, #4 @ r9<- A 5355 GET_VREG(r1, r3) @ r1<- vB 5356 GET_VREG(r0, r9) @ r0<- vA 5357 .if 1 5358 cmp r1, #0 @ is second operand zero? 5359 beq common_errDivideByZero 5360 .endif 5361 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5362 5363 @ optional op; may set condition codes 5364 bl __aeabi_idiv @ r0<- op, r0-r3 changed 5365 GET_INST_OPCODE(ip) @ extract opcode from rINST 5366 SET_VREG(r0, r9) @ vAA<- r0 5367 GOTO_OPCODE(ip) @ jump to next instruction 5368 /* 10-13 instructions */ 5369 5370 5371/* ------------------------------ */ 5372 .balign 64 5373.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5374/* File: armv6t2/OP_REM_INT_2ADDR.S */ 5375/* idivmod returns quotient in r0 and remainder in r1 */ 5376/* File: armv6t2/binop2addr.S */ 5377 /* 5378 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5379 * that specifies an instruction that performs "result = r0 op r1". 5380 * This could be an ARM instruction or a function call. (If the result 5381 * comes back in a register other than r0, you can override "result".) 5382 * 5383 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5384 * vCC (r1). Useful for integer division and modulus. 5385 * 5386 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5387 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5388 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5389 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5390 */ 5391 /* binop/2addr vA, vB */ 5392 mov r3, rINST, lsr #12 @ r3<- B 5393 ubfx r9, rINST, #8, #4 @ r9<- A 5394 GET_VREG(r1, r3) @ r1<- vB 5395 GET_VREG(r0, r9) @ r0<- vA 5396 .if 1 5397 cmp r1, #0 @ is second operand zero? 5398 beq common_errDivideByZero 5399 .endif 5400 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5401 5402 @ optional op; may set condition codes 5403 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5404 GET_INST_OPCODE(ip) @ extract opcode from rINST 5405 SET_VREG(r1, r9) @ vAA<- r1 5406 GOTO_OPCODE(ip) @ jump to next instruction 5407 /* 10-13 instructions */ 5408 5409 5410/* ------------------------------ */ 5411 .balign 64 5412.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5413/* File: armv6t2/OP_AND_INT_2ADDR.S */ 5414/* File: armv6t2/binop2addr.S */ 5415 /* 5416 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5417 * that specifies an instruction that performs "result = r0 op r1". 5418 * This could be an ARM instruction or a function call. (If the result 5419 * comes back in a register other than r0, you can override "result".) 5420 * 5421 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5422 * vCC (r1). Useful for integer division and modulus. 5423 * 5424 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5425 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5426 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5427 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5428 */ 5429 /* binop/2addr vA, vB */ 5430 mov r3, rINST, lsr #12 @ r3<- B 5431 ubfx r9, rINST, #8, #4 @ r9<- A 5432 GET_VREG(r1, r3) @ r1<- vB 5433 GET_VREG(r0, r9) @ r0<- vA 5434 .if 0 5435 cmp r1, #0 @ is second operand zero? 5436 beq common_errDivideByZero 5437 .endif 5438 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5439 5440 @ optional op; may set condition codes 5441 and r0, r0, r1 @ r0<- op, r0-r3 changed 5442 GET_INST_OPCODE(ip) @ extract opcode from rINST 5443 SET_VREG(r0, r9) @ vAA<- r0 5444 GOTO_OPCODE(ip) @ jump to next instruction 5445 /* 10-13 instructions */ 5446 5447 5448/* ------------------------------ */ 5449 .balign 64 5450.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5451/* File: armv6t2/OP_OR_INT_2ADDR.S */ 5452/* File: armv6t2/binop2addr.S */ 5453 /* 5454 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5455 * that specifies an instruction that performs "result = r0 op r1". 5456 * This could be an ARM instruction or a function call. (If the result 5457 * comes back in a register other than r0, you can override "result".) 5458 * 5459 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5460 * vCC (r1). Useful for integer division and modulus. 5461 * 5462 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5463 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5464 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5465 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5466 */ 5467 /* binop/2addr vA, vB */ 5468 mov r3, rINST, lsr #12 @ r3<- B 5469 ubfx r9, rINST, #8, #4 @ r9<- A 5470 GET_VREG(r1, r3) @ r1<- vB 5471 GET_VREG(r0, r9) @ r0<- vA 5472 .if 0 5473 cmp r1, #0 @ is second operand zero? 5474 beq common_errDivideByZero 5475 .endif 5476 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5477 5478 @ optional op; may set condition codes 5479 orr r0, r0, r1 @ r0<- op, r0-r3 changed 5480 GET_INST_OPCODE(ip) @ extract opcode from rINST 5481 SET_VREG(r0, r9) @ vAA<- r0 5482 GOTO_OPCODE(ip) @ jump to next instruction 5483 /* 10-13 instructions */ 5484 5485 5486/* ------------------------------ */ 5487 .balign 64 5488.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5489/* File: armv6t2/OP_XOR_INT_2ADDR.S */ 5490/* File: armv6t2/binop2addr.S */ 5491 /* 5492 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5493 * that specifies an instruction that performs "result = r0 op r1". 5494 * This could be an ARM instruction or a function call. (If the result 5495 * comes back in a register other than r0, you can override "result".) 5496 * 5497 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5498 * vCC (r1). Useful for integer division and modulus. 5499 * 5500 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5501 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5502 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5503 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5504 */ 5505 /* binop/2addr vA, vB */ 5506 mov r3, rINST, lsr #12 @ r3<- B 5507 ubfx r9, rINST, #8, #4 @ r9<- A 5508 GET_VREG(r1, r3) @ r1<- vB 5509 GET_VREG(r0, r9) @ r0<- vA 5510 .if 0 5511 cmp r1, #0 @ is second operand zero? 5512 beq common_errDivideByZero 5513 .endif 5514 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5515 5516 @ optional op; may set condition codes 5517 eor r0, r0, r1 @ r0<- op, r0-r3 changed 5518 GET_INST_OPCODE(ip) @ extract opcode from rINST 5519 SET_VREG(r0, r9) @ vAA<- r0 5520 GOTO_OPCODE(ip) @ jump to next instruction 5521 /* 10-13 instructions */ 5522 5523 5524/* ------------------------------ */ 5525 .balign 64 5526.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5527/* File: armv6t2/OP_SHL_INT_2ADDR.S */ 5528/* File: armv6t2/binop2addr.S */ 5529 /* 5530 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5531 * that specifies an instruction that performs "result = r0 op r1". 5532 * This could be an ARM instruction or a function call. (If the result 5533 * comes back in a register other than r0, you can override "result".) 5534 * 5535 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5536 * vCC (r1). Useful for integer division and modulus. 5537 * 5538 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5539 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5540 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5541 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5542 */ 5543 /* binop/2addr vA, vB */ 5544 mov r3, rINST, lsr #12 @ r3<- B 5545 ubfx r9, rINST, #8, #4 @ r9<- A 5546 GET_VREG(r1, r3) @ r1<- vB 5547 GET_VREG(r0, r9) @ r0<- vA 5548 .if 0 5549 cmp r1, #0 @ is second operand zero? 5550 beq common_errDivideByZero 5551 .endif 5552 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5553 5554 and r1, r1, #31 @ optional op; may set condition codes 5555 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5556 GET_INST_OPCODE(ip) @ extract opcode from rINST 5557 SET_VREG(r0, r9) @ vAA<- r0 5558 GOTO_OPCODE(ip) @ jump to next instruction 5559 /* 10-13 instructions */ 5560 5561 5562/* ------------------------------ */ 5563 .balign 64 5564.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5565/* File: armv6t2/OP_SHR_INT_2ADDR.S */ 5566/* File: armv6t2/binop2addr.S */ 5567 /* 5568 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5569 * that specifies an instruction that performs "result = r0 op r1". 5570 * This could be an ARM instruction or a function call. (If the result 5571 * comes back in a register other than r0, you can override "result".) 5572 * 5573 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5574 * vCC (r1). Useful for integer division and modulus. 5575 * 5576 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5577 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5578 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5579 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5580 */ 5581 /* binop/2addr vA, vB */ 5582 mov r3, rINST, lsr #12 @ r3<- B 5583 ubfx r9, rINST, #8, #4 @ r9<- A 5584 GET_VREG(r1, r3) @ r1<- vB 5585 GET_VREG(r0, r9) @ r0<- vA 5586 .if 0 5587 cmp r1, #0 @ is second operand zero? 5588 beq common_errDivideByZero 5589 .endif 5590 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5591 5592 and r1, r1, #31 @ optional op; may set condition codes 5593 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5594 GET_INST_OPCODE(ip) @ extract opcode from rINST 5595 SET_VREG(r0, r9) @ vAA<- r0 5596 GOTO_OPCODE(ip) @ jump to next instruction 5597 /* 10-13 instructions */ 5598 5599 5600/* ------------------------------ */ 5601 .balign 64 5602.L_OP_USHR_INT_2ADDR: /* 0xba */ 5603/* File: armv6t2/OP_USHR_INT_2ADDR.S */ 5604/* File: armv6t2/binop2addr.S */ 5605 /* 5606 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5607 * that specifies an instruction that performs "result = r0 op r1". 5608 * This could be an ARM instruction or a function call. (If the result 5609 * comes back in a register other than r0, you can override "result".) 5610 * 5611 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5612 * vCC (r1). Useful for integer division and modulus. 5613 * 5614 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5615 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5616 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5617 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5618 */ 5619 /* binop/2addr vA, vB */ 5620 mov r3, rINST, lsr #12 @ r3<- B 5621 ubfx r9, rINST, #8, #4 @ r9<- A 5622 GET_VREG(r1, r3) @ r1<- vB 5623 GET_VREG(r0, r9) @ r0<- vA 5624 .if 0 5625 cmp r1, #0 @ is second operand zero? 5626 beq common_errDivideByZero 5627 .endif 5628 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5629 5630 and r1, r1, #31 @ optional op; may set condition codes 5631 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5632 GET_INST_OPCODE(ip) @ extract opcode from rINST 5633 SET_VREG(r0, r9) @ vAA<- r0 5634 GOTO_OPCODE(ip) @ jump to next instruction 5635 /* 10-13 instructions */ 5636 5637 5638/* ------------------------------ */ 5639 .balign 64 5640.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5641/* File: armv6t2/OP_ADD_LONG_2ADDR.S */ 5642/* File: armv6t2/binopWide2addr.S */ 5643 /* 5644 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5645 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5646 * This could be an ARM instruction or a function call. (If the result 5647 * comes back in a register other than r0, you can override "result".) 5648 * 5649 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5650 * vCC (r1). Useful for integer division and modulus. 5651 * 5652 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5653 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5654 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5655 * rem-double/2addr 5656 */ 5657 /* binop/2addr vA, vB */ 5658 mov r1, rINST, lsr #12 @ r1<- B 5659 ubfx r9, rINST, #8, #4 @ r9<- A 5660 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5661 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5662 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5663 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5664 .if 0 5665 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5666 beq common_errDivideByZero 5667 .endif 5668 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5669 5670 adds r0, r0, r2 @ optional op; may set condition codes 5671 adc r1, r1, r3 @ result<- op, r0-r3 changed 5672 GET_INST_OPCODE(ip) @ extract opcode from rINST 5673 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5674 GOTO_OPCODE(ip) @ jump to next instruction 5675 /* 12-15 instructions */ 5676 5677 5678/* ------------------------------ */ 5679 .balign 64 5680.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5681/* File: armv6t2/OP_SUB_LONG_2ADDR.S */ 5682/* File: armv6t2/binopWide2addr.S */ 5683 /* 5684 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5685 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5686 * This could be an ARM instruction or a function call. (If the result 5687 * comes back in a register other than r0, you can override "result".) 5688 * 5689 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5690 * vCC (r1). Useful for integer division and modulus. 5691 * 5692 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5693 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5694 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5695 * rem-double/2addr 5696 */ 5697 /* binop/2addr vA, vB */ 5698 mov r1, rINST, lsr #12 @ r1<- B 5699 ubfx r9, rINST, #8, #4 @ r9<- A 5700 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5701 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5702 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5703 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5704 .if 0 5705 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5706 beq common_errDivideByZero 5707 .endif 5708 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5709 5710 subs r0, r0, r2 @ optional op; may set condition codes 5711 sbc r1, r1, r3 @ result<- op, r0-r3 changed 5712 GET_INST_OPCODE(ip) @ extract opcode from rINST 5713 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5714 GOTO_OPCODE(ip) @ jump to next instruction 5715 /* 12-15 instructions */ 5716 5717 5718/* ------------------------------ */ 5719 .balign 64 5720.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5721/* File: armv6t2/OP_MUL_LONG_2ADDR.S */ 5722 /* 5723 * Signed 64-bit integer multiply, "/2addr" version. 5724 * 5725 * See OP_MUL_LONG for an explanation. 5726 * 5727 * We get a little tight on registers, so to avoid looking up &fp[A] 5728 * again we stuff it into rINST. 5729 */ 5730 /* mul-long/2addr vA, vB */ 5731 mov r1, rINST, lsr #12 @ r1<- B 5732 ubfx r9, rINST, #8, #4 @ r9<- A 5733 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5734 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5735 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5736 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5737 mul ip, r2, r1 @ ip<- ZxW 5738 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5739 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5740 mov r0, rINST @ r0<- &fp[A] (free up rINST) 5741 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5742 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5743 GET_INST_OPCODE(ip) @ extract opcode from rINST 5744 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5745 GOTO_OPCODE(ip) @ jump to next instruction 5746 5747/* ------------------------------ */ 5748 .balign 64 5749.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5750/* File: armv6t2/OP_DIV_LONG_2ADDR.S */ 5751/* File: armv6t2/binopWide2addr.S */ 5752 /* 5753 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5754 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5755 * This could be an ARM instruction or a function call. (If the result 5756 * comes back in a register other than r0, you can override "result".) 5757 * 5758 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5759 * vCC (r1). Useful for integer division and modulus. 5760 * 5761 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5762 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5763 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5764 * rem-double/2addr 5765 */ 5766 /* binop/2addr vA, vB */ 5767 mov r1, rINST, lsr #12 @ r1<- B 5768 ubfx r9, rINST, #8, #4 @ r9<- A 5769 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5770 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5771 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5772 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5773 .if 1 5774 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5775 beq common_errDivideByZero 5776 .endif 5777 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5778 5779 @ optional op; may set condition codes 5780 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5781 GET_INST_OPCODE(ip) @ extract opcode from rINST 5782 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5783 GOTO_OPCODE(ip) @ jump to next instruction 5784 /* 12-15 instructions */ 5785 5786 5787/* ------------------------------ */ 5788 .balign 64 5789.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5790/* File: armv6t2/OP_REM_LONG_2ADDR.S */ 5791/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5792/* File: armv6t2/binopWide2addr.S */ 5793 /* 5794 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5795 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5796 * This could be an ARM instruction or a function call. (If the result 5797 * comes back in a register other than r0, you can override "result".) 5798 * 5799 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5800 * vCC (r1). Useful for integer division and modulus. 5801 * 5802 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5803 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5804 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5805 * rem-double/2addr 5806 */ 5807 /* binop/2addr vA, vB */ 5808 mov r1, rINST, lsr #12 @ r1<- B 5809 ubfx r9, rINST, #8, #4 @ r9<- A 5810 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5811 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5812 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5813 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5814 .if 1 5815 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5816 beq common_errDivideByZero 5817 .endif 5818 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5819 5820 @ optional op; may set condition codes 5821 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5822 GET_INST_OPCODE(ip) @ extract opcode from rINST 5823 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5824 GOTO_OPCODE(ip) @ jump to next instruction 5825 /* 12-15 instructions */ 5826 5827 5828/* ------------------------------ */ 5829 .balign 64 5830.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5831/* File: armv6t2/OP_AND_LONG_2ADDR.S */ 5832/* File: armv6t2/binopWide2addr.S */ 5833 /* 5834 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5835 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5836 * This could be an ARM instruction or a function call. (If the result 5837 * comes back in a register other than r0, you can override "result".) 5838 * 5839 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5840 * vCC (r1). Useful for integer division and modulus. 5841 * 5842 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5843 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5844 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5845 * rem-double/2addr 5846 */ 5847 /* binop/2addr vA, vB */ 5848 mov r1, rINST, lsr #12 @ r1<- B 5849 ubfx r9, rINST, #8, #4 @ r9<- A 5850 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5851 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5852 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5853 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5854 .if 0 5855 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5856 beq common_errDivideByZero 5857 .endif 5858 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5859 5860 and r0, r0, r2 @ optional op; may set condition codes 5861 and r1, r1, r3 @ result<- op, r0-r3 changed 5862 GET_INST_OPCODE(ip) @ extract opcode from rINST 5863 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5864 GOTO_OPCODE(ip) @ jump to next instruction 5865 /* 12-15 instructions */ 5866 5867 5868/* ------------------------------ */ 5869 .balign 64 5870.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5871/* File: armv6t2/OP_OR_LONG_2ADDR.S */ 5872/* File: armv6t2/binopWide2addr.S */ 5873 /* 5874 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5875 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5876 * This could be an ARM instruction or a function call. (If the result 5877 * comes back in a register other than r0, you can override "result".) 5878 * 5879 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5880 * vCC (r1). Useful for integer division and modulus. 5881 * 5882 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5883 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5884 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5885 * rem-double/2addr 5886 */ 5887 /* binop/2addr vA, vB */ 5888 mov r1, rINST, lsr #12 @ r1<- B 5889 ubfx r9, rINST, #8, #4 @ r9<- A 5890 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5891 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5892 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5893 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5894 .if 0 5895 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5896 beq common_errDivideByZero 5897 .endif 5898 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5899 5900 orr r0, r0, r2 @ optional op; may set condition codes 5901 orr r1, r1, r3 @ result<- op, r0-r3 changed 5902 GET_INST_OPCODE(ip) @ extract opcode from rINST 5903 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5904 GOTO_OPCODE(ip) @ jump to next instruction 5905 /* 12-15 instructions */ 5906 5907 5908/* ------------------------------ */ 5909 .balign 64 5910.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5911/* File: armv6t2/OP_XOR_LONG_2ADDR.S */ 5912/* File: armv6t2/binopWide2addr.S */ 5913 /* 5914 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5915 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5916 * This could be an ARM instruction or a function call. (If the result 5917 * comes back in a register other than r0, you can override "result".) 5918 * 5919 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5920 * vCC (r1). Useful for integer division and modulus. 5921 * 5922 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5923 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5924 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5925 * rem-double/2addr 5926 */ 5927 /* binop/2addr vA, vB */ 5928 mov r1, rINST, lsr #12 @ r1<- B 5929 ubfx r9, rINST, #8, #4 @ r9<- A 5930 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5931 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5932 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5933 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5934 .if 0 5935 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5936 beq common_errDivideByZero 5937 .endif 5938 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5939 5940 eor r0, r0, r2 @ optional op; may set condition codes 5941 eor r1, r1, r3 @ result<- op, r0-r3 changed 5942 GET_INST_OPCODE(ip) @ extract opcode from rINST 5943 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5944 GOTO_OPCODE(ip) @ jump to next instruction 5945 /* 12-15 instructions */ 5946 5947 5948/* ------------------------------ */ 5949 .balign 64 5950.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 5951/* File: armv6t2/OP_SHL_LONG_2ADDR.S */ 5952 /* 5953 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5954 * 32-bit shift distance. 5955 */ 5956 /* shl-long/2addr vA, vB */ 5957 mov r3, rINST, lsr #12 @ r3<- B 5958 ubfx r9, rINST, #8, #4 @ r9<- A 5959 GET_VREG(r2, r3) @ r2<- vB 5960 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5961 and r2, r2, #63 @ r2<- r2 & 0x3f 5962 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5963 5964 mov r1, r1, asl r2 @ r1<- r1 << r2 5965 rsb r3, r2, #32 @ r3<- 32 - r2 5966 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 5967 subs ip, r2, #32 @ ip<- r2 - 32 5968 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5969 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 5970 mov r0, r0, asl r2 @ r0<- r0 << r2 5971 b .LOP_SHL_LONG_2ADDR_finish 5972 5973/* ------------------------------ */ 5974 .balign 64 5975.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 5976/* File: armv6t2/OP_SHR_LONG_2ADDR.S */ 5977 /* 5978 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5979 * 32-bit shift distance. 5980 */ 5981 /* shr-long/2addr vA, vB */ 5982 mov r3, rINST, lsr #12 @ r3<- B 5983 ubfx r9, rINST, #8, #4 @ r9<- A 5984 GET_VREG(r2, r3) @ r2<- vB 5985 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5986 and r2, r2, #63 @ r2<- r2 & 0x3f 5987 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5988 5989 mov r0, r0, lsr r2 @ r0<- r2 >> r2 5990 rsb r3, r2, #32 @ r3<- 32 - r2 5991 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 5992 subs ip, r2, #32 @ ip<- r2 - 32 5993 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5994 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 5995 mov r1, r1, asr r2 @ r1<- r1 >> r2 5996 b .LOP_SHR_LONG_2ADDR_finish 5997 5998/* ------------------------------ */ 5999 .balign 64 6000.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6001/* File: armv6t2/OP_USHR_LONG_2ADDR.S */ 6002 /* 6003 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6004 * 32-bit shift distance. 6005 */ 6006 /* ushr-long/2addr vA, vB */ 6007 mov r3, rINST, lsr #12 @ r3<- B 6008 ubfx r9, rINST, #8, #4 @ r9<- A 6009 GET_VREG(r2, r3) @ r2<- vB 6010 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6011 and r2, r2, #63 @ r2<- r2 & 0x3f 6012 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6013 6014 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6015 rsb r3, r2, #32 @ r3<- 32 - r2 6016 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6017 subs ip, r2, #32 @ ip<- r2 - 32 6018 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6019 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6020 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6021 b .LOP_USHR_LONG_2ADDR_finish 6022 6023/* ------------------------------ */ 6024 .balign 64 6025.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6026/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6027/* File: arm-vfp/fbinop2addr.S */ 6028 /* 6029 * Generic 32-bit floating point "/2addr" binary operation. Provide 6030 * an "instr" line that specifies an instruction that performs 6031 * "s2 = s0 op s1". 6032 * 6033 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6034 */ 6035 /* binop/2addr vA, vB */ 6036 mov r3, rINST, lsr #12 @ r3<- B 6037 mov r9, rINST, lsr #8 @ r9<- A+ 6038 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6039 and r9, r9, #15 @ r9<- A 6040 flds s1, [r3] @ s1<- vB 6041 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6042 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6043 flds s0, [r9] @ s0<- vA 6044 6045 fadds s2, s0, s1 @ s2<- op 6046 GET_INST_OPCODE(ip) @ extract opcode from rINST 6047 fsts s2, [r9] @ vAA<- s2 6048 GOTO_OPCODE(ip) @ jump to next instruction 6049 6050 6051/* ------------------------------ */ 6052 .balign 64 6053.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6054/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6055/* File: arm-vfp/fbinop2addr.S */ 6056 /* 6057 * Generic 32-bit floating point "/2addr" binary operation. Provide 6058 * an "instr" line that specifies an instruction that performs 6059 * "s2 = s0 op s1". 6060 * 6061 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6062 */ 6063 /* binop/2addr vA, vB */ 6064 mov r3, rINST, lsr #12 @ r3<- B 6065 mov r9, rINST, lsr #8 @ r9<- A+ 6066 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6067 and r9, r9, #15 @ r9<- A 6068 flds s1, [r3] @ s1<- vB 6069 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6070 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6071 flds s0, [r9] @ s0<- vA 6072 6073 fsubs s2, s0, s1 @ s2<- op 6074 GET_INST_OPCODE(ip) @ extract opcode from rINST 6075 fsts s2, [r9] @ vAA<- s2 6076 GOTO_OPCODE(ip) @ jump to next instruction 6077 6078 6079/* ------------------------------ */ 6080 .balign 64 6081.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6082/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6083/* File: arm-vfp/fbinop2addr.S */ 6084 /* 6085 * Generic 32-bit floating point "/2addr" binary operation. Provide 6086 * an "instr" line that specifies an instruction that performs 6087 * "s2 = s0 op s1". 6088 * 6089 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6090 */ 6091 /* binop/2addr vA, vB */ 6092 mov r3, rINST, lsr #12 @ r3<- B 6093 mov r9, rINST, lsr #8 @ r9<- A+ 6094 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6095 and r9, r9, #15 @ r9<- A 6096 flds s1, [r3] @ s1<- vB 6097 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6098 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6099 flds s0, [r9] @ s0<- vA 6100 6101 fmuls s2, s0, s1 @ s2<- op 6102 GET_INST_OPCODE(ip) @ extract opcode from rINST 6103 fsts s2, [r9] @ vAA<- s2 6104 GOTO_OPCODE(ip) @ jump to next instruction 6105 6106 6107/* ------------------------------ */ 6108 .balign 64 6109.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6110/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6111/* File: arm-vfp/fbinop2addr.S */ 6112 /* 6113 * Generic 32-bit floating point "/2addr" binary operation. Provide 6114 * an "instr" line that specifies an instruction that performs 6115 * "s2 = s0 op s1". 6116 * 6117 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6118 */ 6119 /* binop/2addr vA, vB */ 6120 mov r3, rINST, lsr #12 @ r3<- B 6121 mov r9, rINST, lsr #8 @ r9<- A+ 6122 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6123 and r9, r9, #15 @ r9<- A 6124 flds s1, [r3] @ s1<- vB 6125 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6126 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6127 flds s0, [r9] @ s0<- vA 6128 6129 fdivs s2, s0, s1 @ s2<- op 6130 GET_INST_OPCODE(ip) @ extract opcode from rINST 6131 fsts s2, [r9] @ vAA<- s2 6132 GOTO_OPCODE(ip) @ jump to next instruction 6133 6134 6135/* ------------------------------ */ 6136 .balign 64 6137.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6138/* File: armv6t2/OP_REM_FLOAT_2ADDR.S */ 6139/* EABI doesn't define a float remainder function, but libm does */ 6140/* File: armv6t2/binop2addr.S */ 6141 /* 6142 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6143 * that specifies an instruction that performs "result = r0 op r1". 6144 * This could be an ARM instruction or a function call. (If the result 6145 * comes back in a register other than r0, you can override "result".) 6146 * 6147 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6148 * vCC (r1). Useful for integer division and modulus. 6149 * 6150 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6151 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6152 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6153 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6154 */ 6155 /* binop/2addr vA, vB */ 6156 mov r3, rINST, lsr #12 @ r3<- B 6157 ubfx r9, rINST, #8, #4 @ r9<- A 6158 GET_VREG(r1, r3) @ r1<- vB 6159 GET_VREG(r0, r9) @ r0<- vA 6160 .if 0 6161 cmp r1, #0 @ is second operand zero? 6162 beq common_errDivideByZero 6163 .endif 6164 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6165 6166 @ optional op; may set condition codes 6167 bl fmodf @ r0<- op, r0-r3 changed 6168 GET_INST_OPCODE(ip) @ extract opcode from rINST 6169 SET_VREG(r0, r9) @ vAA<- r0 6170 GOTO_OPCODE(ip) @ jump to next instruction 6171 /* 10-13 instructions */ 6172 6173 6174/* ------------------------------ */ 6175 .balign 64 6176.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6177/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6178/* File: arm-vfp/fbinopWide2addr.S */ 6179 /* 6180 * Generic 64-bit floating point "/2addr" binary operation. Provide 6181 * an "instr" line that specifies an instruction that performs 6182 * "d2 = d0 op d1". 6183 * 6184 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6185 * div-double/2addr 6186 */ 6187 /* binop/2addr vA, vB */ 6188 mov r3, rINST, lsr #12 @ r3<- B 6189 mov r9, rINST, lsr #8 @ r9<- A+ 6190 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6191 and r9, r9, #15 @ r9<- A 6192 fldd d1, [r3] @ d1<- vB 6193 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6194 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6195 fldd d0, [r9] @ d0<- vA 6196 6197 faddd d2, d0, d1 @ d2<- op 6198 GET_INST_OPCODE(ip) @ extract opcode from rINST 6199 fstd d2, [r9] @ vAA<- d2 6200 GOTO_OPCODE(ip) @ jump to next instruction 6201 6202 6203/* ------------------------------ */ 6204 .balign 64 6205.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6206/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6207/* File: arm-vfp/fbinopWide2addr.S */ 6208 /* 6209 * Generic 64-bit floating point "/2addr" binary operation. Provide 6210 * an "instr" line that specifies an instruction that performs 6211 * "d2 = d0 op d1". 6212 * 6213 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6214 * div-double/2addr 6215 */ 6216 /* binop/2addr vA, vB */ 6217 mov r3, rINST, lsr #12 @ r3<- B 6218 mov r9, rINST, lsr #8 @ r9<- A+ 6219 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6220 and r9, r9, #15 @ r9<- A 6221 fldd d1, [r3] @ d1<- vB 6222 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6223 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6224 fldd d0, [r9] @ d0<- vA 6225 6226 fsubd d2, d0, d1 @ d2<- op 6227 GET_INST_OPCODE(ip) @ extract opcode from rINST 6228 fstd d2, [r9] @ vAA<- d2 6229 GOTO_OPCODE(ip) @ jump to next instruction 6230 6231 6232/* ------------------------------ */ 6233 .balign 64 6234.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6235/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6236/* File: arm-vfp/fbinopWide2addr.S */ 6237 /* 6238 * Generic 64-bit floating point "/2addr" binary operation. Provide 6239 * an "instr" line that specifies an instruction that performs 6240 * "d2 = d0 op d1". 6241 * 6242 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6243 * div-double/2addr 6244 */ 6245 /* binop/2addr vA, vB */ 6246 mov r3, rINST, lsr #12 @ r3<- B 6247 mov r9, rINST, lsr #8 @ r9<- A+ 6248 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6249 and r9, r9, #15 @ r9<- A 6250 fldd d1, [r3] @ d1<- vB 6251 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6252 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6253 fldd d0, [r9] @ d0<- vA 6254 6255 fmuld d2, d0, d1 @ d2<- op 6256 GET_INST_OPCODE(ip) @ extract opcode from rINST 6257 fstd d2, [r9] @ vAA<- d2 6258 GOTO_OPCODE(ip) @ jump to next instruction 6259 6260 6261/* ------------------------------ */ 6262 .balign 64 6263.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6264/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6265/* File: arm-vfp/fbinopWide2addr.S */ 6266 /* 6267 * Generic 64-bit floating point "/2addr" binary operation. Provide 6268 * an "instr" line that specifies an instruction that performs 6269 * "d2 = d0 op d1". 6270 * 6271 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6272 * div-double/2addr 6273 */ 6274 /* binop/2addr vA, vB */ 6275 mov r3, rINST, lsr #12 @ r3<- B 6276 mov r9, rINST, lsr #8 @ r9<- A+ 6277 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6278 and r9, r9, #15 @ r9<- A 6279 fldd d1, [r3] @ d1<- vB 6280 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6281 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6282 fldd d0, [r9] @ d0<- vA 6283 6284 fdivd d2, d0, d1 @ d2<- op 6285 GET_INST_OPCODE(ip) @ extract opcode from rINST 6286 fstd d2, [r9] @ vAA<- d2 6287 GOTO_OPCODE(ip) @ jump to next instruction 6288 6289 6290/* ------------------------------ */ 6291 .balign 64 6292.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6293/* File: armv6t2/OP_REM_DOUBLE_2ADDR.S */ 6294/* EABI doesn't define a double remainder function, but libm does */ 6295/* File: armv6t2/binopWide2addr.S */ 6296 /* 6297 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6298 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6299 * This could be an ARM instruction or a function call. (If the result 6300 * comes back in a register other than r0, you can override "result".) 6301 * 6302 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6303 * vCC (r1). Useful for integer division and modulus. 6304 * 6305 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6306 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6307 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6308 * rem-double/2addr 6309 */ 6310 /* binop/2addr vA, vB */ 6311 mov r1, rINST, lsr #12 @ r1<- B 6312 ubfx r9, rINST, #8, #4 @ r9<- A 6313 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6314 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6315 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6316 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6317 .if 0 6318 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6319 beq common_errDivideByZero 6320 .endif 6321 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6322 6323 @ optional op; may set condition codes 6324 bl fmod @ result<- op, r0-r3 changed 6325 GET_INST_OPCODE(ip) @ extract opcode from rINST 6326 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6327 GOTO_OPCODE(ip) @ jump to next instruction 6328 /* 12-15 instructions */ 6329 6330 6331/* ------------------------------ */ 6332 .balign 64 6333.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6334/* File: armv6t2/OP_ADD_INT_LIT16.S */ 6335/* File: armv6t2/binopLit16.S */ 6336 /* 6337 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6338 * that specifies an instruction that performs "result = r0 op r1". 6339 * This could be an ARM instruction or a function call. (If the result 6340 * comes back in a register other than r0, you can override "result".) 6341 * 6342 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6343 * vCC (r1). Useful for integer division and modulus. 6344 * 6345 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6346 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6347 */ 6348 /* binop/lit16 vA, vB, #+CCCC */ 6349 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6350 mov r2, rINST, lsr #12 @ r2<- B 6351 ubfx r9, rINST, #8, #4 @ r9<- A 6352 GET_VREG(r0, r2) @ r0<- vB 6353 .if 0 6354 cmp r1, #0 @ is second operand zero? 6355 beq common_errDivideByZero 6356 .endif 6357 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6358 6359 add r0, r0, r1 @ r0<- op, r0-r3 changed 6360 GET_INST_OPCODE(ip) @ extract opcode from rINST 6361 SET_VREG(r0, r9) @ vAA<- r0 6362 GOTO_OPCODE(ip) @ jump to next instruction 6363 /* 10-13 instructions */ 6364 6365 6366/* ------------------------------ */ 6367 .balign 64 6368.L_OP_RSUB_INT: /* 0xd1 */ 6369/* File: armv6t2/OP_RSUB_INT.S */ 6370/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6371/* File: armv6t2/binopLit16.S */ 6372 /* 6373 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6374 * that specifies an instruction that performs "result = r0 op r1". 6375 * This could be an ARM instruction or a function call. (If the result 6376 * comes back in a register other than r0, you can override "result".) 6377 * 6378 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6379 * vCC (r1). Useful for integer division and modulus. 6380 * 6381 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6382 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6383 */ 6384 /* binop/lit16 vA, vB, #+CCCC */ 6385 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6386 mov r2, rINST, lsr #12 @ r2<- B 6387 ubfx r9, rINST, #8, #4 @ r9<- A 6388 GET_VREG(r0, r2) @ r0<- vB 6389 .if 0 6390 cmp r1, #0 @ is second operand zero? 6391 beq common_errDivideByZero 6392 .endif 6393 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6394 6395 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6396 GET_INST_OPCODE(ip) @ extract opcode from rINST 6397 SET_VREG(r0, r9) @ vAA<- r0 6398 GOTO_OPCODE(ip) @ jump to next instruction 6399 /* 10-13 instructions */ 6400 6401 6402/* ------------------------------ */ 6403 .balign 64 6404.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6405/* File: armv6t2/OP_MUL_INT_LIT16.S */ 6406/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6407/* File: armv6t2/binopLit16.S */ 6408 /* 6409 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6410 * that specifies an instruction that performs "result = r0 op r1". 6411 * This could be an ARM instruction or a function call. (If the result 6412 * comes back in a register other than r0, you can override "result".) 6413 * 6414 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6415 * vCC (r1). Useful for integer division and modulus. 6416 * 6417 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6418 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6419 */ 6420 /* binop/lit16 vA, vB, #+CCCC */ 6421 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6422 mov r2, rINST, lsr #12 @ r2<- B 6423 ubfx r9, rINST, #8, #4 @ r9<- A 6424 GET_VREG(r0, r2) @ r0<- vB 6425 .if 0 6426 cmp r1, #0 @ is second operand zero? 6427 beq common_errDivideByZero 6428 .endif 6429 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6430 6431 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6432 GET_INST_OPCODE(ip) @ extract opcode from rINST 6433 SET_VREG(r0, r9) @ vAA<- r0 6434 GOTO_OPCODE(ip) @ jump to next instruction 6435 /* 10-13 instructions */ 6436 6437 6438/* ------------------------------ */ 6439 .balign 64 6440.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6441/* File: armv6t2/OP_DIV_INT_LIT16.S */ 6442/* File: armv6t2/binopLit16.S */ 6443 /* 6444 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6445 * that specifies an instruction that performs "result = r0 op r1". 6446 * This could be an ARM instruction or a function call. (If the result 6447 * comes back in a register other than r0, you can override "result".) 6448 * 6449 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6450 * vCC (r1). Useful for integer division and modulus. 6451 * 6452 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6453 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6454 */ 6455 /* binop/lit16 vA, vB, #+CCCC */ 6456 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6457 mov r2, rINST, lsr #12 @ r2<- B 6458 ubfx r9, rINST, #8, #4 @ r9<- A 6459 GET_VREG(r0, r2) @ r0<- vB 6460 .if 1 6461 cmp r1, #0 @ is second operand zero? 6462 beq common_errDivideByZero 6463 .endif 6464 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6465 6466 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6467 GET_INST_OPCODE(ip) @ extract opcode from rINST 6468 SET_VREG(r0, r9) @ vAA<- r0 6469 GOTO_OPCODE(ip) @ jump to next instruction 6470 /* 10-13 instructions */ 6471 6472 6473/* ------------------------------ */ 6474 .balign 64 6475.L_OP_REM_INT_LIT16: /* 0xd4 */ 6476/* File: armv6t2/OP_REM_INT_LIT16.S */ 6477/* idivmod returns quotient in r0 and remainder in r1 */ 6478/* File: armv6t2/binopLit16.S */ 6479 /* 6480 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6481 * that specifies an instruction that performs "result = r0 op r1". 6482 * This could be an ARM instruction or a function call. (If the result 6483 * comes back in a register other than r0, you can override "result".) 6484 * 6485 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6486 * vCC (r1). Useful for integer division and modulus. 6487 * 6488 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6489 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6490 */ 6491 /* binop/lit16 vA, vB, #+CCCC */ 6492 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6493 mov r2, rINST, lsr #12 @ r2<- B 6494 ubfx r9, rINST, #8, #4 @ r9<- A 6495 GET_VREG(r0, r2) @ r0<- vB 6496 .if 1 6497 cmp r1, #0 @ is second operand zero? 6498 beq common_errDivideByZero 6499 .endif 6500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6501 6502 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6503 GET_INST_OPCODE(ip) @ extract opcode from rINST 6504 SET_VREG(r1, r9) @ vAA<- r1 6505 GOTO_OPCODE(ip) @ jump to next instruction 6506 /* 10-13 instructions */ 6507 6508 6509/* ------------------------------ */ 6510 .balign 64 6511.L_OP_AND_INT_LIT16: /* 0xd5 */ 6512/* File: armv6t2/OP_AND_INT_LIT16.S */ 6513/* File: armv6t2/binopLit16.S */ 6514 /* 6515 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6516 * that specifies an instruction that performs "result = r0 op r1". 6517 * This could be an ARM instruction or a function call. (If the result 6518 * comes back in a register other than r0, you can override "result".) 6519 * 6520 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6521 * vCC (r1). Useful for integer division and modulus. 6522 * 6523 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6524 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6525 */ 6526 /* binop/lit16 vA, vB, #+CCCC */ 6527 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6528 mov r2, rINST, lsr #12 @ r2<- B 6529 ubfx r9, rINST, #8, #4 @ r9<- A 6530 GET_VREG(r0, r2) @ r0<- vB 6531 .if 0 6532 cmp r1, #0 @ is second operand zero? 6533 beq common_errDivideByZero 6534 .endif 6535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6536 6537 and r0, r0, r1 @ r0<- op, r0-r3 changed 6538 GET_INST_OPCODE(ip) @ extract opcode from rINST 6539 SET_VREG(r0, r9) @ vAA<- r0 6540 GOTO_OPCODE(ip) @ jump to next instruction 6541 /* 10-13 instructions */ 6542 6543 6544/* ------------------------------ */ 6545 .balign 64 6546.L_OP_OR_INT_LIT16: /* 0xd6 */ 6547/* File: armv6t2/OP_OR_INT_LIT16.S */ 6548/* File: armv6t2/binopLit16.S */ 6549 /* 6550 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6551 * that specifies an instruction that performs "result = r0 op r1". 6552 * This could be an ARM instruction or a function call. (If the result 6553 * comes back in a register other than r0, you can override "result".) 6554 * 6555 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6556 * vCC (r1). Useful for integer division and modulus. 6557 * 6558 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6559 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6560 */ 6561 /* binop/lit16 vA, vB, #+CCCC */ 6562 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6563 mov r2, rINST, lsr #12 @ r2<- B 6564 ubfx r9, rINST, #8, #4 @ r9<- A 6565 GET_VREG(r0, r2) @ r0<- vB 6566 .if 0 6567 cmp r1, #0 @ is second operand zero? 6568 beq common_errDivideByZero 6569 .endif 6570 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6571 6572 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6573 GET_INST_OPCODE(ip) @ extract opcode from rINST 6574 SET_VREG(r0, r9) @ vAA<- r0 6575 GOTO_OPCODE(ip) @ jump to next instruction 6576 /* 10-13 instructions */ 6577 6578 6579/* ------------------------------ */ 6580 .balign 64 6581.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6582/* File: armv6t2/OP_XOR_INT_LIT16.S */ 6583/* File: armv6t2/binopLit16.S */ 6584 /* 6585 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6586 * that specifies an instruction that performs "result = r0 op r1". 6587 * This could be an ARM instruction or a function call. (If the result 6588 * comes back in a register other than r0, you can override "result".) 6589 * 6590 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6591 * vCC (r1). Useful for integer division and modulus. 6592 * 6593 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6594 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6595 */ 6596 /* binop/lit16 vA, vB, #+CCCC */ 6597 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6598 mov r2, rINST, lsr #12 @ r2<- B 6599 ubfx r9, rINST, #8, #4 @ r9<- A 6600 GET_VREG(r0, r2) @ r0<- vB 6601 .if 0 6602 cmp r1, #0 @ is second operand zero? 6603 beq common_errDivideByZero 6604 .endif 6605 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6606 6607 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6608 GET_INST_OPCODE(ip) @ extract opcode from rINST 6609 SET_VREG(r0, r9) @ vAA<- r0 6610 GOTO_OPCODE(ip) @ jump to next instruction 6611 /* 10-13 instructions */ 6612 6613 6614/* ------------------------------ */ 6615 .balign 64 6616.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6617/* File: armv5te/OP_ADD_INT_LIT8.S */ 6618/* File: armv5te/binopLit8.S */ 6619 /* 6620 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6621 * that specifies an instruction that performs "result = r0 op r1". 6622 * This could be an ARM instruction or a function call. (If the result 6623 * comes back in a register other than r0, you can override "result".) 6624 * 6625 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6626 * vCC (r1). Useful for integer division and modulus. 6627 * 6628 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6629 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6630 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6631 */ 6632 /* binop/lit8 vAA, vBB, #+CC */ 6633 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6634 mov r9, rINST, lsr #8 @ r9<- AA 6635 and r2, r3, #255 @ r2<- BB 6636 GET_VREG(r0, r2) @ r0<- vBB 6637 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6638 .if 0 6639 @cmp r1, #0 @ is second operand zero? 6640 beq common_errDivideByZero 6641 .endif 6642 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6643 6644 @ optional op; may set condition codes 6645 add r0, r0, r1 @ r0<- op, r0-r3 changed 6646 GET_INST_OPCODE(ip) @ extract opcode from rINST 6647 SET_VREG(r0, r9) @ vAA<- r0 6648 GOTO_OPCODE(ip) @ jump to next instruction 6649 /* 10-12 instructions */ 6650 6651 6652/* ------------------------------ */ 6653 .balign 64 6654.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6655/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6656/* File: armv5te/binopLit8.S */ 6657 /* 6658 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6659 * that specifies an instruction that performs "result = r0 op r1". 6660 * This could be an ARM instruction or a function call. (If the result 6661 * comes back in a register other than r0, you can override "result".) 6662 * 6663 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6664 * vCC (r1). Useful for integer division and modulus. 6665 * 6666 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6667 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6668 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6669 */ 6670 /* binop/lit8 vAA, vBB, #+CC */ 6671 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6672 mov r9, rINST, lsr #8 @ r9<- AA 6673 and r2, r3, #255 @ r2<- BB 6674 GET_VREG(r0, r2) @ r0<- vBB 6675 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6676 .if 0 6677 @cmp r1, #0 @ is second operand zero? 6678 beq common_errDivideByZero 6679 .endif 6680 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6681 6682 @ optional op; may set condition codes 6683 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6684 GET_INST_OPCODE(ip) @ extract opcode from rINST 6685 SET_VREG(r0, r9) @ vAA<- r0 6686 GOTO_OPCODE(ip) @ jump to next instruction 6687 /* 10-12 instructions */ 6688 6689 6690/* ------------------------------ */ 6691 .balign 64 6692.L_OP_MUL_INT_LIT8: /* 0xda */ 6693/* File: armv5te/OP_MUL_INT_LIT8.S */ 6694/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6695/* File: armv5te/binopLit8.S */ 6696 /* 6697 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6698 * that specifies an instruction that performs "result = r0 op r1". 6699 * This could be an ARM instruction or a function call. (If the result 6700 * comes back in a register other than r0, you can override "result".) 6701 * 6702 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6703 * vCC (r1). Useful for integer division and modulus. 6704 * 6705 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6706 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6707 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6708 */ 6709 /* binop/lit8 vAA, vBB, #+CC */ 6710 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6711 mov r9, rINST, lsr #8 @ r9<- AA 6712 and r2, r3, #255 @ r2<- BB 6713 GET_VREG(r0, r2) @ r0<- vBB 6714 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6715 .if 0 6716 @cmp r1, #0 @ is second operand zero? 6717 beq common_errDivideByZero 6718 .endif 6719 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6720 6721 @ optional op; may set condition codes 6722 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6723 GET_INST_OPCODE(ip) @ extract opcode from rINST 6724 SET_VREG(r0, r9) @ vAA<- r0 6725 GOTO_OPCODE(ip) @ jump to next instruction 6726 /* 10-12 instructions */ 6727 6728 6729/* ------------------------------ */ 6730 .balign 64 6731.L_OP_DIV_INT_LIT8: /* 0xdb */ 6732/* File: armv5te/OP_DIV_INT_LIT8.S */ 6733/* File: armv5te/binopLit8.S */ 6734 /* 6735 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6736 * that specifies an instruction that performs "result = r0 op r1". 6737 * This could be an ARM instruction or a function call. (If the result 6738 * comes back in a register other than r0, you can override "result".) 6739 * 6740 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6741 * vCC (r1). Useful for integer division and modulus. 6742 * 6743 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6744 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6745 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6746 */ 6747 /* binop/lit8 vAA, vBB, #+CC */ 6748 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6749 mov r9, rINST, lsr #8 @ r9<- AA 6750 and r2, r3, #255 @ r2<- BB 6751 GET_VREG(r0, r2) @ r0<- vBB 6752 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6753 .if 1 6754 @cmp r1, #0 @ is second operand zero? 6755 beq common_errDivideByZero 6756 .endif 6757 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6758 6759 @ optional op; may set condition codes 6760 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6761 GET_INST_OPCODE(ip) @ extract opcode from rINST 6762 SET_VREG(r0, r9) @ vAA<- r0 6763 GOTO_OPCODE(ip) @ jump to next instruction 6764 /* 10-12 instructions */ 6765 6766 6767/* ------------------------------ */ 6768 .balign 64 6769.L_OP_REM_INT_LIT8: /* 0xdc */ 6770/* File: armv5te/OP_REM_INT_LIT8.S */ 6771/* idivmod returns quotient in r0 and remainder in r1 */ 6772/* File: armv5te/binopLit8.S */ 6773 /* 6774 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6775 * that specifies an instruction that performs "result = r0 op r1". 6776 * This could be an ARM instruction or a function call. (If the result 6777 * comes back in a register other than r0, you can override "result".) 6778 * 6779 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6780 * vCC (r1). Useful for integer division and modulus. 6781 * 6782 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6783 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6784 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6785 */ 6786 /* binop/lit8 vAA, vBB, #+CC */ 6787 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6788 mov r9, rINST, lsr #8 @ r9<- AA 6789 and r2, r3, #255 @ r2<- BB 6790 GET_VREG(r0, r2) @ r0<- vBB 6791 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6792 .if 1 6793 @cmp r1, #0 @ is second operand zero? 6794 beq common_errDivideByZero 6795 .endif 6796 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6797 6798 @ optional op; may set condition codes 6799 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6800 GET_INST_OPCODE(ip) @ extract opcode from rINST 6801 SET_VREG(r1, r9) @ vAA<- r1 6802 GOTO_OPCODE(ip) @ jump to next instruction 6803 /* 10-12 instructions */ 6804 6805 6806/* ------------------------------ */ 6807 .balign 64 6808.L_OP_AND_INT_LIT8: /* 0xdd */ 6809/* File: armv5te/OP_AND_INT_LIT8.S */ 6810/* File: armv5te/binopLit8.S */ 6811 /* 6812 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6813 * that specifies an instruction that performs "result = r0 op r1". 6814 * This could be an ARM instruction or a function call. (If the result 6815 * comes back in a register other than r0, you can override "result".) 6816 * 6817 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6818 * vCC (r1). Useful for integer division and modulus. 6819 * 6820 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6821 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6822 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6823 */ 6824 /* binop/lit8 vAA, vBB, #+CC */ 6825 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6826 mov r9, rINST, lsr #8 @ r9<- AA 6827 and r2, r3, #255 @ r2<- BB 6828 GET_VREG(r0, r2) @ r0<- vBB 6829 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6830 .if 0 6831 @cmp r1, #0 @ is second operand zero? 6832 beq common_errDivideByZero 6833 .endif 6834 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6835 6836 @ optional op; may set condition codes 6837 and r0, r0, r1 @ r0<- op, r0-r3 changed 6838 GET_INST_OPCODE(ip) @ extract opcode from rINST 6839 SET_VREG(r0, r9) @ vAA<- r0 6840 GOTO_OPCODE(ip) @ jump to next instruction 6841 /* 10-12 instructions */ 6842 6843 6844/* ------------------------------ */ 6845 .balign 64 6846.L_OP_OR_INT_LIT8: /* 0xde */ 6847/* File: armv5te/OP_OR_INT_LIT8.S */ 6848/* File: armv5te/binopLit8.S */ 6849 /* 6850 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6851 * that specifies an instruction that performs "result = r0 op r1". 6852 * This could be an ARM instruction or a function call. (If the result 6853 * comes back in a register other than r0, you can override "result".) 6854 * 6855 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6856 * vCC (r1). Useful for integer division and modulus. 6857 * 6858 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6859 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6860 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6861 */ 6862 /* binop/lit8 vAA, vBB, #+CC */ 6863 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6864 mov r9, rINST, lsr #8 @ r9<- AA 6865 and r2, r3, #255 @ r2<- BB 6866 GET_VREG(r0, r2) @ r0<- vBB 6867 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6868 .if 0 6869 @cmp r1, #0 @ is second operand zero? 6870 beq common_errDivideByZero 6871 .endif 6872 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6873 6874 @ optional op; may set condition codes 6875 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6876 GET_INST_OPCODE(ip) @ extract opcode from rINST 6877 SET_VREG(r0, r9) @ vAA<- r0 6878 GOTO_OPCODE(ip) @ jump to next instruction 6879 /* 10-12 instructions */ 6880 6881 6882/* ------------------------------ */ 6883 .balign 64 6884.L_OP_XOR_INT_LIT8: /* 0xdf */ 6885/* File: armv5te/OP_XOR_INT_LIT8.S */ 6886/* File: armv5te/binopLit8.S */ 6887 /* 6888 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6889 * that specifies an instruction that performs "result = r0 op r1". 6890 * This could be an ARM instruction or a function call. (If the result 6891 * comes back in a register other than r0, you can override "result".) 6892 * 6893 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6894 * vCC (r1). Useful for integer division and modulus. 6895 * 6896 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6897 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6898 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6899 */ 6900 /* binop/lit8 vAA, vBB, #+CC */ 6901 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6902 mov r9, rINST, lsr #8 @ r9<- AA 6903 and r2, r3, #255 @ r2<- BB 6904 GET_VREG(r0, r2) @ r0<- vBB 6905 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6906 .if 0 6907 @cmp r1, #0 @ is second operand zero? 6908 beq common_errDivideByZero 6909 .endif 6910 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6911 6912 @ optional op; may set condition codes 6913 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6914 GET_INST_OPCODE(ip) @ extract opcode from rINST 6915 SET_VREG(r0, r9) @ vAA<- r0 6916 GOTO_OPCODE(ip) @ jump to next instruction 6917 /* 10-12 instructions */ 6918 6919 6920/* ------------------------------ */ 6921 .balign 64 6922.L_OP_SHL_INT_LIT8: /* 0xe0 */ 6923/* File: armv5te/OP_SHL_INT_LIT8.S */ 6924/* File: armv5te/binopLit8.S */ 6925 /* 6926 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6927 * that specifies an instruction that performs "result = r0 op r1". 6928 * This could be an ARM instruction or a function call. (If the result 6929 * comes back in a register other than r0, you can override "result".) 6930 * 6931 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6932 * vCC (r1). Useful for integer division and modulus. 6933 * 6934 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6935 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6936 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6937 */ 6938 /* binop/lit8 vAA, vBB, #+CC */ 6939 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6940 mov r9, rINST, lsr #8 @ r9<- AA 6941 and r2, r3, #255 @ r2<- BB 6942 GET_VREG(r0, r2) @ r0<- vBB 6943 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6944 .if 0 6945 @cmp r1, #0 @ is second operand zero? 6946 beq common_errDivideByZero 6947 .endif 6948 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6949 6950 and r1, r1, #31 @ optional op; may set condition codes 6951 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 6952 GET_INST_OPCODE(ip) @ extract opcode from rINST 6953 SET_VREG(r0, r9) @ vAA<- r0 6954 GOTO_OPCODE(ip) @ jump to next instruction 6955 /* 10-12 instructions */ 6956 6957 6958/* ------------------------------ */ 6959 .balign 64 6960.L_OP_SHR_INT_LIT8: /* 0xe1 */ 6961/* File: armv5te/OP_SHR_INT_LIT8.S */ 6962/* File: armv5te/binopLit8.S */ 6963 /* 6964 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6965 * that specifies an instruction that performs "result = r0 op r1". 6966 * This could be an ARM instruction or a function call. (If the result 6967 * comes back in a register other than r0, you can override "result".) 6968 * 6969 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6970 * vCC (r1). Useful for integer division and modulus. 6971 * 6972 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6973 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6974 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6975 */ 6976 /* binop/lit8 vAA, vBB, #+CC */ 6977 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6978 mov r9, rINST, lsr #8 @ r9<- AA 6979 and r2, r3, #255 @ r2<- BB 6980 GET_VREG(r0, r2) @ r0<- vBB 6981 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6982 .if 0 6983 @cmp r1, #0 @ is second operand zero? 6984 beq common_errDivideByZero 6985 .endif 6986 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6987 6988 and r1, r1, #31 @ optional op; may set condition codes 6989 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 6990 GET_INST_OPCODE(ip) @ extract opcode from rINST 6991 SET_VREG(r0, r9) @ vAA<- r0 6992 GOTO_OPCODE(ip) @ jump to next instruction 6993 /* 10-12 instructions */ 6994 6995 6996/* ------------------------------ */ 6997 .balign 64 6998.L_OP_USHR_INT_LIT8: /* 0xe2 */ 6999/* File: armv5te/OP_USHR_INT_LIT8.S */ 7000/* File: armv5te/binopLit8.S */ 7001 /* 7002 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7003 * that specifies an instruction that performs "result = r0 op r1". 7004 * This could be an ARM instruction or a function call. (If the result 7005 * comes back in a register other than r0, you can override "result".) 7006 * 7007 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7008 * vCC (r1). Useful for integer division and modulus. 7009 * 7010 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7011 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7012 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7013 */ 7014 /* binop/lit8 vAA, vBB, #+CC */ 7015 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7016 mov r9, rINST, lsr #8 @ r9<- AA 7017 and r2, r3, #255 @ r2<- BB 7018 GET_VREG(r0, r2) @ r0<- vBB 7019 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7020 .if 0 7021 @cmp r1, #0 @ is second operand zero? 7022 beq common_errDivideByZero 7023 .endif 7024 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7025 7026 and r1, r1, #31 @ optional op; may set condition codes 7027 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7028 GET_INST_OPCODE(ip) @ extract opcode from rINST 7029 SET_VREG(r0, r9) @ vAA<- r0 7030 GOTO_OPCODE(ip) @ jump to next instruction 7031 /* 10-12 instructions */ 7032 7033 7034/* ------------------------------ */ 7035 .balign 64 7036.L_OP_IGET_VOLATILE: /* 0xe3 */ 7037/* File: armv5te/OP_IGET_VOLATILE.S */ 7038/* File: armv5te/OP_IGET.S */ 7039 /* 7040 * General 32-bit instance field get. 7041 * 7042 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7043 */ 7044 /* op vA, vB, field@CCCC */ 7045 mov r0, rINST, lsr #12 @ r0<- B 7046 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7047 FETCH(r1, 1) @ r1<- field ref CCCC 7048 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7049 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7050 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7051 cmp r0, #0 @ is resolved entry null? 7052 bne .LOP_IGET_VOLATILE_finish @ no, already resolved 70538: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7054 EXPORT_PC() @ resolve() could throw 7055 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7056 bl dvmResolveInstField @ r0<- resolved InstField ptr 7057 cmp r0, #0 7058 bne .LOP_IGET_VOLATILE_finish 7059 b common_exceptionThrown 7060 7061 7062/* ------------------------------ */ 7063 .balign 64 7064.L_OP_IPUT_VOLATILE: /* 0xe4 */ 7065/* File: armv5te/OP_IPUT_VOLATILE.S */ 7066/* File: armv5te/OP_IPUT.S */ 7067 /* 7068 * General 32-bit instance field put. 7069 * 7070 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7071 */ 7072 /* op vA, vB, field@CCCC */ 7073 mov r0, rINST, lsr #12 @ r0<- B 7074 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7075 FETCH(r1, 1) @ r1<- field ref CCCC 7076 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7077 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7078 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7079 cmp r0, #0 @ is resolved entry null? 7080 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 70818: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7082 EXPORT_PC() @ resolve() could throw 7083 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7084 bl dvmResolveInstField @ r0<- resolved InstField ptr 7085 cmp r0, #0 @ success? 7086 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7087 b common_exceptionThrown 7088 7089 7090/* ------------------------------ */ 7091 .balign 64 7092.L_OP_SGET_VOLATILE: /* 0xe5 */ 7093/* File: armv5te/OP_SGET_VOLATILE.S */ 7094/* File: armv5te/OP_SGET.S */ 7095 /* 7096 * General 32-bit SGET handler. 7097 * 7098 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7099 */ 7100 /* op vAA, field@BBBB */ 7101 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7102 FETCH(r1, 1) @ r1<- field ref BBBB 7103 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7104 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7105 cmp r0, #0 @ is resolved entry null? 7106 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7107.LOP_SGET_VOLATILE_finish: @ field ptr in r0 7108 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7109 SMP_DMB @ acquiring load 7110 mov r2, rINST, lsr #8 @ r2<- AA 7111 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7112 SET_VREG(r1, r2) @ fp[AA]<- r1 7113 GET_INST_OPCODE(ip) @ extract opcode from rINST 7114 GOTO_OPCODE(ip) @ jump to next instruction 7115 7116 7117/* ------------------------------ */ 7118 .balign 64 7119.L_OP_SPUT_VOLATILE: /* 0xe6 */ 7120/* File: armv5te/OP_SPUT_VOLATILE.S */ 7121/* File: armv5te/OP_SPUT.S */ 7122 /* 7123 * General 32-bit SPUT handler. 7124 * 7125 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7126 */ 7127 /* op vAA, field@BBBB */ 7128 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7129 FETCH(r1, 1) @ r1<- field ref BBBB 7130 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7131 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7132 cmp r0, #0 @ is resolved entry null? 7133 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7134.LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7135 mov r2, rINST, lsr #8 @ r2<- AA 7136 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7137 GET_VREG(r1, r2) @ r1<- fp[AA] 7138 GET_INST_OPCODE(ip) @ extract opcode from rINST 7139 SMP_DMB @ releasing store 7140 str r1, [r0, #offStaticField_value] @ field<- vAA 7141 GOTO_OPCODE(ip) @ jump to next instruction 7142 7143 7144/* ------------------------------ */ 7145 .balign 64 7146.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7147/* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7148/* File: armv5te/OP_IGET.S */ 7149 /* 7150 * General 32-bit instance field get. 7151 * 7152 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7153 */ 7154 /* op vA, vB, field@CCCC */ 7155 mov r0, rINST, lsr #12 @ r0<- B 7156 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7157 FETCH(r1, 1) @ r1<- field ref CCCC 7158 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7159 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7160 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7161 cmp r0, #0 @ is resolved entry null? 7162 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 71638: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7164 EXPORT_PC() @ resolve() could throw 7165 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7166 bl dvmResolveInstField @ r0<- resolved InstField ptr 7167 cmp r0, #0 7168 bne .LOP_IGET_OBJECT_VOLATILE_finish 7169 b common_exceptionThrown 7170 7171 7172/* ------------------------------ */ 7173 .balign 64 7174.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 7175/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 7176/* File: armv5te/OP_IGET_WIDE.S */ 7177 /* 7178 * Wide 32-bit instance field get. 7179 */ 7180 /* iget-wide vA, vB, field@CCCC */ 7181 mov r0, rINST, lsr #12 @ r0<- B 7182 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7183 FETCH(r1, 1) @ r1<- field ref CCCC 7184 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7185 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7186 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7187 cmp r0, #0 @ is resolved entry null? 7188 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 71898: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7190 EXPORT_PC() @ resolve() could throw 7191 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7192 bl dvmResolveInstField @ r0<- resolved InstField ptr 7193 cmp r0, #0 7194 bne .LOP_IGET_WIDE_VOLATILE_finish 7195 b common_exceptionThrown 7196 7197 7198/* ------------------------------ */ 7199 .balign 64 7200.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 7201/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 7202/* File: armv5te/OP_IPUT_WIDE.S */ 7203 /* iput-wide vA, vB, field@CCCC */ 7204 mov r0, rINST, lsr #12 @ r0<- B 7205 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7206 FETCH(r1, 1) @ r1<- field ref CCCC 7207 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7208 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7209 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7210 cmp r0, #0 @ is resolved entry null? 7211 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 72128: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7213 EXPORT_PC() @ resolve() could throw 7214 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7215 bl dvmResolveInstField @ r0<- resolved InstField ptr 7216 cmp r0, #0 @ success? 7217 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 7218 b common_exceptionThrown 7219 7220 7221/* ------------------------------ */ 7222 .balign 64 7223.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 7224/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 7225/* File: armv5te/OP_SGET_WIDE.S */ 7226 /* 7227 * 64-bit SGET handler. 7228 */ 7229 /* sget-wide vAA, field@BBBB */ 7230 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7231 FETCH(r1, 1) @ r1<- field ref BBBB 7232 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7233 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7234 cmp r0, #0 @ is resolved entry null? 7235 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 7236.LOP_SGET_WIDE_VOLATILE_finish: 7237 mov r9, rINST, lsr #8 @ r9<- AA 7238 .if 1 7239 add r0, r0, #offStaticField_value @ r0<- pointer to data 7240 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7241 .else 7242 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7243 .endif 7244 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7245 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7246 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 7247 GET_INST_OPCODE(ip) @ extract opcode from rINST 7248 GOTO_OPCODE(ip) @ jump to next instruction 7249 7250 7251/* ------------------------------ */ 7252 .balign 64 7253.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 7254/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 7255/* File: armv5te/OP_SPUT_WIDE.S */ 7256 /* 7257 * 64-bit SPUT handler. 7258 */ 7259 /* sput-wide vAA, field@BBBB */ 7260 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 7261 FETCH(r1, 1) @ r1<- field ref BBBB 7262 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 7263 mov r9, rINST, lsr #8 @ r9<- AA 7264 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 7265 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7266 cmp r2, #0 @ is resolved entry null? 7267 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7268.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 7269 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7270 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7271 GET_INST_OPCODE(r10) @ extract opcode from rINST 7272 .if 1 7273 add r2, r2, #offStaticField_value @ r2<- pointer to data 7274 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 7275 .else 7276 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7277 .endif 7278 GOTO_OPCODE(r10) @ jump to next instruction 7279 7280 7281/* ------------------------------ */ 7282 .balign 64 7283.L_OP_BREAKPOINT: /* 0xec */ 7284/* File: armv5te/OP_BREAKPOINT.S */ 7285/* File: armv5te/unused.S */ 7286 bl common_abort 7287 7288 7289/* ------------------------------ */ 7290 .balign 64 7291.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7292/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7293 /* 7294 * Handle a throw-verification-error instruction. This throws an 7295 * exception for an error discovered during verification. The 7296 * exception is indicated by AA, with some detail provided by BBBB. 7297 */ 7298 /* op AA, ref@BBBB */ 7299 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 7300 FETCH(r2, 1) @ r2<- BBBB 7301 EXPORT_PC() @ export the PC 7302 mov r1, rINST, lsr #8 @ r1<- AA 7303 bl dvmThrowVerificationError @ always throws 7304 b common_exceptionThrown @ handle exception 7305 7306/* ------------------------------ */ 7307 .balign 64 7308.L_OP_EXECUTE_INLINE: /* 0xee */ 7309/* File: armv5te/OP_EXECUTE_INLINE.S */ 7310 /* 7311 * Execute a "native inline" instruction. 7312 * 7313 * We need to call an InlineOp4Func: 7314 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7315 * 7316 * The first four args are in r0-r3, pointer to return value storage 7317 * is on the stack. The function's return value is a flag that tells 7318 * us if an exception was thrown. 7319 */ 7320 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7321 FETCH(r10, 1) @ r10<- BBBB 7322 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7323 EXPORT_PC() @ can throw 7324 sub sp, sp, #8 @ make room for arg, +64 bit align 7325 mov r0, rINST, lsr #12 @ r0<- B 7326 str r1, [sp] @ push &self->retval 7327 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7328 add sp, sp, #8 @ pop stack 7329 cmp r0, #0 @ test boolean result of inline 7330 beq common_exceptionThrown @ returned false, handle exception 7331 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7332 GET_INST_OPCODE(ip) @ extract opcode from rINST 7333 GOTO_OPCODE(ip) @ jump to next instruction 7334 7335/* ------------------------------ */ 7336 .balign 64 7337.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7338/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7339 /* 7340 * Execute a "native inline" instruction, using "/range" semantics. 7341 * Same idea as execute-inline, but we get the args differently. 7342 * 7343 * We need to call an InlineOp4Func: 7344 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7345 * 7346 * The first four args are in r0-r3, pointer to return value storage 7347 * is on the stack. The function's return value is a flag that tells 7348 * us if an exception was thrown. 7349 */ 7350 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7351 FETCH(r10, 1) @ r10<- BBBB 7352 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7353 EXPORT_PC() @ can throw 7354 sub sp, sp, #8 @ make room for arg, +64 bit align 7355 mov r0, rINST, lsr #8 @ r0<- AA 7356 str r1, [sp] @ push &self->retval 7357 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7358 add sp, sp, #8 @ pop stack 7359 cmp r0, #0 @ test boolean result of inline 7360 beq common_exceptionThrown @ returned false, handle exception 7361 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7362 GET_INST_OPCODE(ip) @ extract opcode from rINST 7363 GOTO_OPCODE(ip) @ jump to next instruction 7364 7365/* ------------------------------ */ 7366 .balign 64 7367.L_OP_INVOKE_OBJECT_INIT: /* 0xf0 */ 7368/* File: armv5te/OP_INVOKE_OBJECT_INIT.S */ 7369 /* 7370 * Invoke Object.<init> on an object. In practice we know that 7371 * Object's nullary constructor doesn't do anything, so we just 7372 * skip it (we know a debugger isn't active). 7373 */ 7374 FETCH(r0, 2) @ r0<- GFED 7375 and r1, r0, #15 @ r1<- D 7376 GET_VREG(r0, r1) @ r0<- "this" ptr 7377 cmp r0, #0 @ check for NULL 7378 beq common_errNullObject @ export PC and throw NPE 7379 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 7380 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 7381 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 7382 beq 1f @ nope, done 7383 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 73841: FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7385 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7386 GOTO_OPCODE(ip) @ execute it 7387 7388/* ------------------------------ */ 7389 .balign 64 7390.L_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 7391/* File: armv5te/OP_RETURN_VOID_BARRIER.S */ 7392 SMP_DMB_ST 7393 b common_returnFromMethod 7394 7395/* ------------------------------ */ 7396 .balign 64 7397.L_OP_IGET_QUICK: /* 0xf2 */ 7398/* File: armv6t2/OP_IGET_QUICK.S */ 7399 /* For: iget-quick, iget-object-quick */ 7400 /* op vA, vB, offset@CCCC */ 7401 mov r2, rINST, lsr #12 @ r2<- B 7402 FETCH(r1, 1) @ r1<- field byte offset 7403 GET_VREG(r3, r2) @ r3<- object we're operating on 7404 ubfx r2, rINST, #8, #4 @ r2<- A 7405 cmp r3, #0 @ check object for null 7406 beq common_errNullObject @ object was null 7407 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7408 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7409 GET_INST_OPCODE(ip) @ extract opcode from rINST 7410 SET_VREG(r0, r2) @ fp[A]<- r0 7411 GOTO_OPCODE(ip) @ jump to next instruction 7412 7413/* ------------------------------ */ 7414 .balign 64 7415.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7416/* File: armv6t2/OP_IGET_WIDE_QUICK.S */ 7417 /* iget-wide-quick vA, vB, offset@CCCC */ 7418 mov r2, rINST, lsr #12 @ r2<- B 7419 FETCH(ip, 1) @ ip<- field byte offset 7420 GET_VREG(r3, r2) @ r3<- object we're operating on 7421 ubfx r2, rINST, #8, #4 @ r2<- A 7422 cmp r3, #0 @ check object for null 7423 beq common_errNullObject @ object was null 7424 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7425 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7426 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7427 GET_INST_OPCODE(ip) @ extract opcode from rINST 7428 stmia r3, {r0-r1} @ fp[A]<- r0/r1 7429 GOTO_OPCODE(ip) @ jump to next instruction 7430 7431/* ------------------------------ */ 7432 .balign 64 7433.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7434/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7435/* File: armv5te/OP_IGET_QUICK.S */ 7436 /* For: iget-quick, iget-object-quick */ 7437 /* op vA, vB, offset@CCCC */ 7438 mov r2, rINST, lsr #12 @ r2<- B 7439 GET_VREG(r3, r2) @ r3<- object we're operating on 7440 FETCH(r1, 1) @ r1<- field byte offset 7441 cmp r3, #0 @ check object for null 7442 mov r2, rINST, lsr #8 @ r2<- A(+) 7443 beq common_errNullObject @ object was null 7444 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7445 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7446 and r2, r2, #15 7447 GET_INST_OPCODE(ip) @ extract opcode from rINST 7448 SET_VREG(r0, r2) @ fp[A]<- r0 7449 GOTO_OPCODE(ip) @ jump to next instruction 7450 7451 7452/* ------------------------------ */ 7453 .balign 64 7454.L_OP_IPUT_QUICK: /* 0xf5 */ 7455/* File: armv6t2/OP_IPUT_QUICK.S */ 7456 /* For: iput-quick, iput-object-quick */ 7457 /* op vA, vB, offset@CCCC */ 7458 mov r2, rINST, lsr #12 @ r2<- B 7459 FETCH(r1, 1) @ r1<- field byte offset 7460 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7461 ubfx r2, rINST, #8, #4 @ r2<- A 7462 cmp r3, #0 @ check object for null 7463 beq common_errNullObject @ object was null 7464 GET_VREG(r0, r2) @ r0<- fp[A] 7465 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7466 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7467 GET_INST_OPCODE(ip) @ extract opcode from rINST 7468 GOTO_OPCODE(ip) @ jump to next instruction 7469 7470/* ------------------------------ */ 7471 .balign 64 7472.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7473/* File: armv6t2/OP_IPUT_WIDE_QUICK.S */ 7474 /* iput-wide-quick vA, vB, offset@CCCC */ 7475 mov r1, rINST, lsr #12 @ r1<- B 7476 ubfx r0, rINST, #8, #4 @ r0<- A 7477 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7478 add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7479 cmp r2, #0 @ check object for null 7480 ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7481 beq common_errNullObject @ object was null 7482 FETCH(r3, 1) @ r3<- field byte offset 7483 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7484 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7485 GET_INST_OPCODE(ip) @ extract opcode from rINST 7486 GOTO_OPCODE(ip) @ jump to next instruction 7487 7488/* ------------------------------ */ 7489 .balign 64 7490.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7491/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7492 /* For: iput-object-quick */ 7493 /* op vA, vB, offset@CCCC */ 7494 mov r2, rINST, lsr #12 @ r2<- B 7495 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7496 FETCH(r1, 1) @ r1<- field byte offset 7497 cmp r3, #0 @ check object for null 7498 mov r2, rINST, lsr #8 @ r2<- A(+) 7499 beq common_errNullObject @ object was null 7500 and r2, r2, #15 7501 GET_VREG(r0, r2) @ r0<- fp[A] 7502 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 7503 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7504 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7505 cmp r0, #0 7506 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head 7507 GET_INST_OPCODE(ip) @ extract opcode from rINST 7508 GOTO_OPCODE(ip) @ jump to next instruction 7509 7510/* ------------------------------ */ 7511 .balign 64 7512.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7513/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7514 /* 7515 * Handle an optimized virtual method call. 7516 * 7517 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7518 */ 7519 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7520 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7521 FETCH(r3, 2) @ r3<- FEDC or CCCC 7522 FETCH(r1, 1) @ r1<- BBBB 7523 .if (!0) 7524 and r3, r3, #15 @ r3<- C (or stays CCCC) 7525 .endif 7526 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7527 cmp r2, #0 @ is "this" null? 7528 beq common_errNullObject @ null "this", throw exception 7529 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7530 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7531 EXPORT_PC() @ invoke must export 7532 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7533 bl common_invokeMethodNoRange @ continue on 7534 7535/* ------------------------------ */ 7536 .balign 64 7537.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7538/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7539/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7540 /* 7541 * Handle an optimized virtual method call. 7542 * 7543 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7544 */ 7545 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7546 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7547 FETCH(r3, 2) @ r3<- FEDC or CCCC 7548 FETCH(r1, 1) @ r1<- BBBB 7549 .if (!1) 7550 and r3, r3, #15 @ r3<- C (or stays CCCC) 7551 .endif 7552 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7553 cmp r2, #0 @ is "this" null? 7554 beq common_errNullObject @ null "this", throw exception 7555 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7556 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7557 EXPORT_PC() @ invoke must export 7558 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7559 bl common_invokeMethodRange @ continue on 7560 7561 7562/* ------------------------------ */ 7563 .balign 64 7564.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7565/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7566 /* 7567 * Handle an optimized "super" method call. 7568 * 7569 * for: [opt] invoke-super-quick, invoke-super-quick/range 7570 */ 7571 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7572 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7573 FETCH(r10, 2) @ r10<- GFED or CCCC 7574 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7575 .if (!0) 7576 and r10, r10, #15 @ r10<- D (or stays CCCC) 7577 .endif 7578 FETCH(r1, 1) @ r1<- BBBB 7579 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7580 EXPORT_PC() @ must export for invoke 7581 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7582 GET_VREG(r3, r10) @ r3<- "this" 7583 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7584 cmp r3, #0 @ null "this" ref? 7585 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7586 beq common_errNullObject @ "this" is null, throw exception 7587 bl common_invokeMethodNoRange @ continue on 7588 7589/* ------------------------------ */ 7590 .balign 64 7591.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7592/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7593/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7594 /* 7595 * Handle an optimized "super" method call. 7596 * 7597 * for: [opt] invoke-super-quick, invoke-super-quick/range 7598 */ 7599 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7600 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7601 FETCH(r10, 2) @ r10<- GFED or CCCC 7602 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7603 .if (!1) 7604 and r10, r10, #15 @ r10<- D (or stays CCCC) 7605 .endif 7606 FETCH(r1, 1) @ r1<- BBBB 7607 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7608 EXPORT_PC() @ must export for invoke 7609 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7610 GET_VREG(r3, r10) @ r3<- "this" 7611 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7612 cmp r3, #0 @ null "this" ref? 7613 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7614 beq common_errNullObject @ "this" is null, throw exception 7615 bl common_invokeMethodRange @ continue on 7616 7617 7618/* ------------------------------ */ 7619 .balign 64 7620.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7621/* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7622/* File: armv5te/OP_IPUT_OBJECT.S */ 7623 /* 7624 * 32-bit instance field put. 7625 * 7626 * for: iput-object, iput-object-volatile 7627 */ 7628 /* op vA, vB, field@CCCC */ 7629 mov r0, rINST, lsr #12 @ r0<- B 7630 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7631 FETCH(r1, 1) @ r1<- field ref CCCC 7632 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7633 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7634 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7635 cmp r0, #0 @ is resolved entry null? 7636 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 76378: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7638 EXPORT_PC() @ resolve() could throw 7639 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7640 bl dvmResolveInstField @ r0<- resolved InstField ptr 7641 cmp r0, #0 @ success? 7642 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 7643 b common_exceptionThrown 7644 7645 7646/* ------------------------------ */ 7647 .balign 64 7648.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 7649/* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 7650/* File: armv5te/OP_SGET.S */ 7651 /* 7652 * General 32-bit SGET handler. 7653 * 7654 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7655 */ 7656 /* op vAA, field@BBBB */ 7657 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7658 FETCH(r1, 1) @ r1<- field ref BBBB 7659 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7660 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7661 cmp r0, #0 @ is resolved entry null? 7662 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 7663.LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 7664 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7665 SMP_DMB @ acquiring load 7666 mov r2, rINST, lsr #8 @ r2<- AA 7667 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7668 SET_VREG(r1, r2) @ fp[AA]<- r1 7669 GET_INST_OPCODE(ip) @ extract opcode from rINST 7670 GOTO_OPCODE(ip) @ jump to next instruction 7671 7672 7673/* ------------------------------ */ 7674 .balign 64 7675.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 7676/* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 7677/* File: armv5te/OP_SPUT_OBJECT.S */ 7678 /* 7679 * 32-bit SPUT handler for objects 7680 * 7681 * for: sput-object, sput-object-volatile 7682 */ 7683 /* op vAA, field@BBBB */ 7684 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7685 FETCH(r1, 1) @ r1<- field ref BBBB 7686 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7687 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7688 cmp r0, #0 @ is resolved entry null? 7689 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue 7690 ldr r9, [rSELF, #offThread_method] @ r9<- current method 7691 EXPORT_PC() @ resolve() could throw, so export now 7692 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 7693 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 7694 cmp r0, #0 @ success? 7695 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish 7696 b common_exceptionThrown @ no, handle exception 7697 7698 7699 7700/* ------------------------------ */ 7701 .balign 64 7702.L_OP_DISPATCH_FF: /* 0xff */ 7703/* File: armv5te/OP_DISPATCH_FF.S */ 7704 mov ip, rINST, lsr #8 @ ip<- extended opcode 7705 add ip, ip, #256 @ add offset for extended opcodes 7706 GOTO_OPCODE(ip) @ go to proper extended handler 7707 7708 7709/* ------------------------------ */ 7710 .balign 64 7711.L_OP_CONST_CLASS_JUMBO: /* 0x100 */ 7712/* File: armv5te/OP_CONST_CLASS_JUMBO.S */ 7713 /* const-class/jumbo vBBBB, Class@AAAAAAAA */ 7714 FETCH(r0, 1) @ r0<- aaaa (lo) 7715 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex 7716 FETCH(r1, 2) @ r1<- AAAA (hi) 7717 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 7718 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7719 FETCH(r9, 3) @ r9<- BBBB 7720 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa] 7721 cmp r0, #0 @ not yet resolved? 7722 beq .LOP_CONST_CLASS_JUMBO_resolve 7723 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 7724 GET_INST_OPCODE(ip) @ extract opcode from rINST 7725 SET_VREG(r0, r9) @ vBBBB<- r0 7726 GOTO_OPCODE(ip) @ jump to next instruction 7727 7728/* ------------------------------ */ 7729 .balign 64 7730.L_OP_CHECK_CAST_JUMBO: /* 0x101 */ 7731/* File: armv5te/OP_CHECK_CAST_JUMBO.S */ 7732 /* 7733 * Check to see if a cast from one class to another is allowed. 7734 */ 7735 /* check-cast/jumbo vBBBB, class@AAAAAAAA */ 7736 FETCH(r0, 1) @ r0<- aaaa (lo) 7737 FETCH(r2, 2) @ r2<- AAAA (hi) 7738 FETCH(r3, 3) @ r3<- BBBB 7739 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa 7740 GET_VREG(r9, r3) @ r9<- object 7741 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 7742 cmp r9, #0 @ is object null? 7743 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 7744 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds 7745 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 7746 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7747 cmp r1, #0 @ have we resolved this before? 7748 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now 7749.LOP_CHECK_CAST_JUMBO_resolved: 7750 cmp r0, r1 @ same class (trivial success)? 7751 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check 7752 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up 7753 7754/* ------------------------------ */ 7755 .balign 64 7756.L_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 7757/* File: armv5te/OP_INSTANCE_OF_JUMBO.S */ 7758 /* 7759 * Check to see if an object reference is an instance of a class. 7760 * 7761 * Most common situation is a non-null object, being compared against 7762 * an already-resolved class. 7763 * 7764 * TODO: convert most of this into a common subroutine, shared with 7765 * OP_INSTANCE_OF.S. 7766 */ 7767 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7768 FETCH(r3, 4) @ r3<- vCCCC 7769 FETCH(r9, 3) @ r9<- vBBBB 7770 GET_VREG(r0, r3) @ r0<- vCCCC (object) 7771 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 7772 cmp r0, #0 @ is object null? 7773 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0 7774 FETCH(r1, 1) @ r1<- aaaa (lo) 7775 FETCH(r3, 2) @ r3<- AAAA (hi) 7776 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 7777 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa 7778 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 7779 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7780 cmp r1, #0 @ have we resolved this before? 7781 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now 7782 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue 7783 7784/* ------------------------------ */ 7785 .balign 64 7786.L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 7787/* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */ 7788 /* 7789 * Create a new instance of a class. 7790 */ 7791 /* new-instance/jumbo vBBBB, class@AAAAAAAA */ 7792 FETCH(r0, 1) @ r0<- aaaa (lo) 7793 FETCH(r1, 2) @ r1<- AAAA (hi) 7794 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7795 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7796 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7797 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7798 EXPORT_PC() @ req'd for init, resolve, alloc 7799 cmp r0, #0 @ already resolved? 7800 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now 7801.LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class 7802 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 7803 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 7804 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now 7805.LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class 7806 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 7807 bl dvmAllocObject @ r0<- new object 7808 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue 7809 7810/* ------------------------------ */ 7811 .balign 64 7812.L_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 7813/* File: armv5te/OP_NEW_ARRAY_JUMBO.S */ 7814 /* 7815 * Allocate an array of objects, specified with the array class 7816 * and a count. 7817 * 7818 * The verifier guarantees that this is an array class, so we don't 7819 * check for it here. 7820 */ 7821 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7822 FETCH(r2, 1) @ r2<- aaaa (lo) 7823 FETCH(r3, 2) @ r3<- AAAA (hi) 7824 FETCH(r0, 4) @ r0<- vCCCC 7825 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa 7826 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7827 GET_VREG(r1, r0) @ r1<- vCCCC (array length) 7828 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7829 cmp r1, #0 @ check length 7830 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 7831 bmi common_errNegativeArraySize @ negative length, bail - len in r1 7832 cmp r0, #0 @ already resolved? 7833 EXPORT_PC() @ req'd for resolve, alloc 7834 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue 7835 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now 7836 7837/* ------------------------------ */ 7838 .balign 64 7839.L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 7840/* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */ 7841 /* 7842 * Create a new array with elements filled from registers. 7843 * 7844 * TODO: convert most of this into a common subroutine, shared with 7845 * OP_FILLED_NEW_ARRAY.S. 7846 */ 7847 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */ 7848 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7849 FETCH(r0, 1) @ r0<- aaaa (lo) 7850 FETCH(r1, 2) @ r1<- AAAA (hi) 7851 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7852 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7853 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7854 EXPORT_PC() @ need for resolve and alloc 7855 cmp r0, #0 @ already resolved? 7856 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on 78578: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 7858 mov r2, #0 @ r2<- false 7859 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7860 bl dvmResolveClass @ r0<- call(clazz, ref) 7861 cmp r0, #0 @ got null? 7862 beq common_exceptionThrown @ yes, handle exception 7863 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue 7864 7865/* ------------------------------ */ 7866 .balign 64 7867.L_OP_IGET_JUMBO: /* 0x106 */ 7868/* File: armv5te/OP_IGET_JUMBO.S */ 7869 /* 7870 * Jumbo 32-bit instance field get. 7871 * 7872 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7873 * iget-char/jumbo, iget-short/jumbo 7874 */ 7875 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7876 FETCH(r1, 1) @ r1<- aaaa (lo) 7877 FETCH(r2, 2) @ r2<- AAAA (hi) 7878 FETCH(r0, 4) @ r0<- CCCC 7879 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7880 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7881 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7882 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7883 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7884 cmp r0, #0 @ is resolved entry null? 7885 bne .LOP_IGET_JUMBO_finish @ no, already resolved 78868: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7887 EXPORT_PC() @ resolve() could throw 7888 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7889 bl dvmResolveInstField @ r0<- resolved InstField ptr 7890 b .LOP_IGET_JUMBO_resolved @ resolved, continue 7891 7892/* ------------------------------ */ 7893 .balign 64 7894.L_OP_IGET_WIDE_JUMBO: /* 0x107 */ 7895/* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 7896 /* 7897 * Jumbo 64-bit instance field get. 7898 */ 7899 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 7900 FETCH(r1, 1) @ r1<- aaaa (lo) 7901 FETCH(r2, 2) @ r2<- AAAA (hi) 7902 FETCH(r0, 4) @ r0<- CCCC 7903 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7904 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7905 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7906 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7907 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7908 cmp r0, #0 @ is resolved entry null? 7909 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved 79108: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7911 EXPORT_PC() @ resolve() could throw 7912 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7913 bl dvmResolveInstField @ r0<- resolved InstField ptr 7914 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue 7915 7916/* ------------------------------ */ 7917 .balign 64 7918.L_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 7919/* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 7920/* File: armv5te/OP_IGET_JUMBO.S */ 7921 /* 7922 * Jumbo 32-bit instance field get. 7923 * 7924 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7925 * iget-char/jumbo, iget-short/jumbo 7926 */ 7927 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7928 FETCH(r1, 1) @ r1<- aaaa (lo) 7929 FETCH(r2, 2) @ r2<- AAAA (hi) 7930 FETCH(r0, 4) @ r0<- CCCC 7931 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7932 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7933 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7934 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7935 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7936 cmp r0, #0 @ is resolved entry null? 7937 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved 79388: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7939 EXPORT_PC() @ resolve() could throw 7940 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7941 bl dvmResolveInstField @ r0<- resolved InstField ptr 7942 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue 7943 7944 7945/* ------------------------------ */ 7946 .balign 64 7947.L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 7948/* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */ 7949@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" } 7950/* File: armv5te/OP_IGET_JUMBO.S */ 7951 /* 7952 * Jumbo 32-bit instance field get. 7953 * 7954 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7955 * iget-char/jumbo, iget-short/jumbo 7956 */ 7957 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7958 FETCH(r1, 1) @ r1<- aaaa (lo) 7959 FETCH(r2, 2) @ r2<- AAAA (hi) 7960 FETCH(r0, 4) @ r0<- CCCC 7961 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7962 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7963 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7964 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7965 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7966 cmp r0, #0 @ is resolved entry null? 7967 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved 79688: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7969 EXPORT_PC() @ resolve() could throw 7970 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7971 bl dvmResolveInstField @ r0<- resolved InstField ptr 7972 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue 7973 7974 7975/* ------------------------------ */ 7976 .balign 64 7977.L_OP_IGET_BYTE_JUMBO: /* 0x10a */ 7978/* File: armv5te/OP_IGET_BYTE_JUMBO.S */ 7979@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" } 7980/* File: armv5te/OP_IGET_JUMBO.S */ 7981 /* 7982 * Jumbo 32-bit instance field get. 7983 * 7984 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7985 * iget-char/jumbo, iget-short/jumbo 7986 */ 7987 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7988 FETCH(r1, 1) @ r1<- aaaa (lo) 7989 FETCH(r2, 2) @ r2<- AAAA (hi) 7990 FETCH(r0, 4) @ r0<- CCCC 7991 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7992 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7993 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7994 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7995 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7996 cmp r0, #0 @ is resolved entry null? 7997 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved 79988: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7999 EXPORT_PC() @ resolve() could throw 8000 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8001 bl dvmResolveInstField @ r0<- resolved InstField ptr 8002 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue 8003 8004 8005/* ------------------------------ */ 8006 .balign 64 8007.L_OP_IGET_CHAR_JUMBO: /* 0x10b */ 8008/* File: armv5te/OP_IGET_CHAR_JUMBO.S */ 8009@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" } 8010/* File: armv5te/OP_IGET_JUMBO.S */ 8011 /* 8012 * Jumbo 32-bit instance field get. 8013 * 8014 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8015 * iget-char/jumbo, iget-short/jumbo 8016 */ 8017 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8018 FETCH(r1, 1) @ r1<- aaaa (lo) 8019 FETCH(r2, 2) @ r2<- AAAA (hi) 8020 FETCH(r0, 4) @ r0<- CCCC 8021 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8022 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8023 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8024 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8025 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8026 cmp r0, #0 @ is resolved entry null? 8027 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved 80288: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8029 EXPORT_PC() @ resolve() could throw 8030 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8031 bl dvmResolveInstField @ r0<- resolved InstField ptr 8032 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue 8033 8034 8035/* ------------------------------ */ 8036 .balign 64 8037.L_OP_IGET_SHORT_JUMBO: /* 0x10c */ 8038/* File: armv5te/OP_IGET_SHORT_JUMBO.S */ 8039@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" } 8040/* File: armv5te/OP_IGET_JUMBO.S */ 8041 /* 8042 * Jumbo 32-bit instance field get. 8043 * 8044 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8045 * iget-char/jumbo, iget-short/jumbo 8046 */ 8047 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8048 FETCH(r1, 1) @ r1<- aaaa (lo) 8049 FETCH(r2, 2) @ r2<- AAAA (hi) 8050 FETCH(r0, 4) @ r0<- CCCC 8051 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8052 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8053 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8054 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8055 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8056 cmp r0, #0 @ is resolved entry null? 8057 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved 80588: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8059 EXPORT_PC() @ resolve() could throw 8060 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8061 bl dvmResolveInstField @ r0<- resolved InstField ptr 8062 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue 8063 8064 8065/* ------------------------------ */ 8066 .balign 64 8067.L_OP_IPUT_JUMBO: /* 0x10d */ 8068/* File: armv5te/OP_IPUT_JUMBO.S */ 8069 /* 8070 * Jumbo 32-bit instance field put. 8071 * 8072 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8073 * iput-short/jumbo 8074 */ 8075 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8076 FETCH(r1, 1) @ r1<- aaaa (lo) 8077 FETCH(r2, 2) @ r2<- AAAA (hi) 8078 FETCH(r0, 4) @ r0<- CCCC 8079 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8080 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8081 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8082 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8083 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8084 cmp r0, #0 @ is resolved entry null? 8085 bne .LOP_IPUT_JUMBO_finish @ no, already resolved 80868: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8087 EXPORT_PC() @ resolve() could throw 8088 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8089 bl dvmResolveInstField @ r0<- resolved InstField ptr 8090 b .LOP_IPUT_JUMBO_resolved @ resolved, continue 8091 8092/* ------------------------------ */ 8093 .balign 64 8094.L_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 8095/* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 8096 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8097 FETCH(r1, 1) @ r1<- aaaa (lo) 8098 FETCH(r2, 2) @ r2<- AAAA (hi) 8099 FETCH(r0, 4) @ r0<- CCCC 8100 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8101 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8102 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 8103 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 8104 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8105 cmp r0, #0 @ is resolved entry null? 8106 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved 81078: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8108 EXPORT_PC() @ resolve() could throw 8109 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8110 bl dvmResolveInstField @ r0<- resolved InstField ptr 8111 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue 8112 8113/* ------------------------------ */ 8114 .balign 64 8115.L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 8116/* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 8117 /* 8118 * Jumbo 32-bit instance field put. 8119 */ 8120 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8121 FETCH(r1, 1) @ r1<- aaaa (lo) 8122 FETCH(r2, 2) @ r2<- AAAA (hi) 8123 FETCH(r0, 4) @ r0<- CCCC 8124 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8125 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8126 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8127 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8128 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8129 cmp r0, #0 @ is resolved entry null? 8130 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved 81318: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8132 EXPORT_PC() @ resolve() could throw 8133 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8134 bl dvmResolveInstField @ r0<- resolved InstField ptr 8135 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue 8136 8137/* ------------------------------ */ 8138 .balign 64 8139.L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 8140/* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */ 8141@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" } 8142/* File: armv5te/OP_IPUT_JUMBO.S */ 8143 /* 8144 * Jumbo 32-bit instance field put. 8145 * 8146 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8147 * iput-short/jumbo 8148 */ 8149 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8150 FETCH(r1, 1) @ r1<- aaaa (lo) 8151 FETCH(r2, 2) @ r2<- AAAA (hi) 8152 FETCH(r0, 4) @ r0<- CCCC 8153 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8154 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8155 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8156 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8157 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8158 cmp r0, #0 @ is resolved entry null? 8159 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved 81608: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8161 EXPORT_PC() @ resolve() could throw 8162 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8163 bl dvmResolveInstField @ r0<- resolved InstField ptr 8164 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue 8165 8166 8167/* ------------------------------ */ 8168 .balign 64 8169.L_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 8170/* File: armv5te/OP_IPUT_BYTE_JUMBO.S */ 8171@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" } 8172/* File: armv5te/OP_IPUT_JUMBO.S */ 8173 /* 8174 * Jumbo 32-bit instance field put. 8175 * 8176 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8177 * iput-short/jumbo 8178 */ 8179 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8180 FETCH(r1, 1) @ r1<- aaaa (lo) 8181 FETCH(r2, 2) @ r2<- AAAA (hi) 8182 FETCH(r0, 4) @ r0<- CCCC 8183 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8184 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8185 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8186 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8187 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8188 cmp r0, #0 @ is resolved entry null? 8189 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved 81908: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8191 EXPORT_PC() @ resolve() could throw 8192 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8193 bl dvmResolveInstField @ r0<- resolved InstField ptr 8194 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue 8195 8196 8197/* ------------------------------ */ 8198 .balign 64 8199.L_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 8200/* File: armv5te/OP_IPUT_CHAR_JUMBO.S */ 8201@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" } 8202/* File: armv5te/OP_IPUT_JUMBO.S */ 8203 /* 8204 * Jumbo 32-bit instance field put. 8205 * 8206 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8207 * iput-short/jumbo 8208 */ 8209 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8210 FETCH(r1, 1) @ r1<- aaaa (lo) 8211 FETCH(r2, 2) @ r2<- AAAA (hi) 8212 FETCH(r0, 4) @ r0<- CCCC 8213 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8214 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8215 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8216 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8217 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8218 cmp r0, #0 @ is resolved entry null? 8219 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved 82208: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8221 EXPORT_PC() @ resolve() could throw 8222 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8223 bl dvmResolveInstField @ r0<- resolved InstField ptr 8224 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue 8225 8226 8227/* ------------------------------ */ 8228 .balign 64 8229.L_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 8230/* File: armv5te/OP_IPUT_SHORT_JUMBO.S */ 8231@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" } 8232/* File: armv5te/OP_IPUT_JUMBO.S */ 8233 /* 8234 * Jumbo 32-bit instance field put. 8235 * 8236 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8237 * iput-short/jumbo 8238 */ 8239 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8240 FETCH(r1, 1) @ r1<- aaaa (lo) 8241 FETCH(r2, 2) @ r2<- AAAA (hi) 8242 FETCH(r0, 4) @ r0<- CCCC 8243 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8244 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8245 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8246 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8247 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8248 cmp r0, #0 @ is resolved entry null? 8249 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved 82508: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8251 EXPORT_PC() @ resolve() could throw 8252 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8253 bl dvmResolveInstField @ r0<- resolved InstField ptr 8254 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue 8255 8256 8257/* ------------------------------ */ 8258 .balign 64 8259.L_OP_SGET_JUMBO: /* 0x114 */ 8260/* File: armv5te/OP_SGET_JUMBO.S */ 8261 /* 8262 * Jumbo 32-bit SGET handler. 8263 * 8264 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8265 * sget-char/jumbo, sget-short/jumbo 8266 */ 8267 /* exop vBBBB, field@AAAAAAAA */ 8268 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8269 FETCH(r0, 1) @ r0<- aaaa (lo) 8270 FETCH(r1, 2) @ r1<- AAAA (hi) 8271 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8272 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8273 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8274 cmp r0, #0 @ is resolved entry null? 8275 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve 8276.LOP_SGET_JUMBO_finish: @ field ptr in r0 8277 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8278 @ no-op @ acquiring load 8279 FETCH(r2, 3) @ r2<- BBBB 8280 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8281 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8282 GET_INST_OPCODE(ip) @ extract opcode from rINST 8283 GOTO_OPCODE(ip) @ jump to next instruction 8284 8285/* ------------------------------ */ 8286 .balign 64 8287.L_OP_SGET_WIDE_JUMBO: /* 0x115 */ 8288/* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 8289 /* 8290 * Jumbo 64-bit SGET handler. 8291 */ 8292 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 8293 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8294 FETCH(r0, 1) @ r0<- aaaa (lo) 8295 FETCH(r1, 2) @ r1<- AAAA (hi) 8296 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8297 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8298 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8299 cmp r0, #0 @ is resolved entry null? 8300 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve 8301.LOP_SGET_WIDE_JUMBO_finish: 8302 FETCH(r9, 3) @ r9<- BBBB 8303 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 8304 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8305 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8306 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 8307 GET_INST_OPCODE(ip) @ extract opcode from rINST 8308 GOTO_OPCODE(ip) @ jump to next instruction 8309 8310/* ------------------------------ */ 8311 .balign 64 8312.L_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 8313/* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 8314/* File: armv5te/OP_SGET_JUMBO.S */ 8315 /* 8316 * Jumbo 32-bit SGET handler. 8317 * 8318 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8319 * sget-char/jumbo, sget-short/jumbo 8320 */ 8321 /* exop vBBBB, field@AAAAAAAA */ 8322 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8323 FETCH(r0, 1) @ r0<- aaaa (lo) 8324 FETCH(r1, 2) @ r1<- AAAA (hi) 8325 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8326 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8327 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8328 cmp r0, #0 @ is resolved entry null? 8329 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve 8330.LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0 8331 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8332 @ no-op @ acquiring load 8333 FETCH(r2, 3) @ r2<- BBBB 8334 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8335 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8336 GET_INST_OPCODE(ip) @ extract opcode from rINST 8337 GOTO_OPCODE(ip) @ jump to next instruction 8338 8339 8340/* ------------------------------ */ 8341 .balign 64 8342.L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 8343/* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */ 8344/* File: armv5te/OP_SGET_JUMBO.S */ 8345 /* 8346 * Jumbo 32-bit SGET handler. 8347 * 8348 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8349 * sget-char/jumbo, sget-short/jumbo 8350 */ 8351 /* exop vBBBB, field@AAAAAAAA */ 8352 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8353 FETCH(r0, 1) @ r0<- aaaa (lo) 8354 FETCH(r1, 2) @ r1<- AAAA (hi) 8355 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8356 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8357 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8358 cmp r0, #0 @ is resolved entry null? 8359 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve 8360.LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0 8361 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8362 @ no-op @ acquiring load 8363 FETCH(r2, 3) @ r2<- BBBB 8364 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8365 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8366 GET_INST_OPCODE(ip) @ extract opcode from rINST 8367 GOTO_OPCODE(ip) @ jump to next instruction 8368 8369 8370/* ------------------------------ */ 8371 .balign 64 8372.L_OP_SGET_BYTE_JUMBO: /* 0x118 */ 8373/* File: armv5te/OP_SGET_BYTE_JUMBO.S */ 8374/* File: armv5te/OP_SGET_JUMBO.S */ 8375 /* 8376 * Jumbo 32-bit SGET handler. 8377 * 8378 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8379 * sget-char/jumbo, sget-short/jumbo 8380 */ 8381 /* exop vBBBB, field@AAAAAAAA */ 8382 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8383 FETCH(r0, 1) @ r0<- aaaa (lo) 8384 FETCH(r1, 2) @ r1<- AAAA (hi) 8385 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8386 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8387 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8388 cmp r0, #0 @ is resolved entry null? 8389 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve 8390.LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0 8391 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8392 @ no-op @ acquiring load 8393 FETCH(r2, 3) @ r2<- BBBB 8394 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8395 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8396 GET_INST_OPCODE(ip) @ extract opcode from rINST 8397 GOTO_OPCODE(ip) @ jump to next instruction 8398 8399 8400/* ------------------------------ */ 8401 .balign 64 8402.L_OP_SGET_CHAR_JUMBO: /* 0x119 */ 8403/* File: armv5te/OP_SGET_CHAR_JUMBO.S */ 8404/* File: armv5te/OP_SGET_JUMBO.S */ 8405 /* 8406 * Jumbo 32-bit SGET handler. 8407 * 8408 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8409 * sget-char/jumbo, sget-short/jumbo 8410 */ 8411 /* exop vBBBB, field@AAAAAAAA */ 8412 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8413 FETCH(r0, 1) @ r0<- aaaa (lo) 8414 FETCH(r1, 2) @ r1<- AAAA (hi) 8415 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8416 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8417 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8418 cmp r0, #0 @ is resolved entry null? 8419 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve 8420.LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0 8421 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8422 @ no-op @ acquiring load 8423 FETCH(r2, 3) @ r2<- BBBB 8424 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8425 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8426 GET_INST_OPCODE(ip) @ extract opcode from rINST 8427 GOTO_OPCODE(ip) @ jump to next instruction 8428 8429 8430/* ------------------------------ */ 8431 .balign 64 8432.L_OP_SGET_SHORT_JUMBO: /* 0x11a */ 8433/* File: armv5te/OP_SGET_SHORT_JUMBO.S */ 8434/* File: armv5te/OP_SGET_JUMBO.S */ 8435 /* 8436 * Jumbo 32-bit SGET handler. 8437 * 8438 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8439 * sget-char/jumbo, sget-short/jumbo 8440 */ 8441 /* exop vBBBB, field@AAAAAAAA */ 8442 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8443 FETCH(r0, 1) @ r0<- aaaa (lo) 8444 FETCH(r1, 2) @ r1<- AAAA (hi) 8445 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8446 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8447 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8448 cmp r0, #0 @ is resolved entry null? 8449 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve 8450.LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0 8451 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8452 @ no-op @ acquiring load 8453 FETCH(r2, 3) @ r2<- BBBB 8454 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8455 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8456 GET_INST_OPCODE(ip) @ extract opcode from rINST 8457 GOTO_OPCODE(ip) @ jump to next instruction 8458 8459 8460/* ------------------------------ */ 8461 .balign 64 8462.L_OP_SPUT_JUMBO: /* 0x11b */ 8463/* File: armv5te/OP_SPUT_JUMBO.S */ 8464 /* 8465 * Jumbo 32-bit SPUT handler. 8466 * 8467 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8468 * sput-short/jumbo 8469 */ 8470 /* exop vBBBB, field@AAAAAAAA */ 8471 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8472 FETCH(r0, 1) @ r0<- aaaa (lo) 8473 FETCH(r1, 2) @ r1<- AAAA (hi) 8474 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8475 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8476 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8477 cmp r0, #0 @ is resolved entry null? 8478 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve 8479.LOP_SPUT_JUMBO_finish: @ field ptr in r0 8480 FETCH(r2, 3) @ r2<- BBBB 8481 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8482 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8483 GET_INST_OPCODE(ip) @ extract opcode from rINST 8484 @ no-op @ releasing store 8485 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8486 GOTO_OPCODE(ip) @ jump to next instruction 8487 8488/* ------------------------------ */ 8489 .balign 64 8490.L_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 8491/* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 8492 /* 8493 * Jumbo 64-bit SPUT handler. 8494 */ 8495 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 8496 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 8497 FETCH(r1, 1) @ r1<- aaaa (lo) 8498 FETCH(r2, 2) @ r2<- AAAA (hi) 8499 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 8500 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8501 FETCH(r9, 3) @ r9<- BBBB 8502 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 8503 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8504 cmp r2, #0 @ is resolved entry null? 8505 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve 8506.LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9 8507 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8508 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 8509 GET_INST_OPCODE(r10) @ extract opcode from rINST 8510 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 8511 GOTO_OPCODE(r10) @ jump to next instruction 8512 8513/* ------------------------------ */ 8514 .balign 64 8515.L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 8516/* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 8517 /* 8518 * Jumbo 32-bit SPUT handler for objects 8519 */ 8520 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 8521 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8522 FETCH(r0, 1) @ r0<- aaaa (lo) 8523 FETCH(r1, 2) @ r1<- AAAA (hi) 8524 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8525 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8526 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8527 cmp r0, #0 @ is resolved entry null? 8528 bne .LOP_SPUT_OBJECT_JUMBO_finish @ no, continue 8529 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8530 EXPORT_PC() @ resolve() could throw, so export now 8531 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 8532 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8533 cmp r0, #0 @ success? 8534 bne .LOP_SPUT_OBJECT_JUMBO_finish @ yes, finish 8535 b common_exceptionThrown @ no, handle exception 8536 8537/* ------------------------------ */ 8538 .balign 64 8539.L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 8540/* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */ 8541/* File: armv5te/OP_SPUT_JUMBO.S */ 8542 /* 8543 * Jumbo 32-bit SPUT handler. 8544 * 8545 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8546 * sput-short/jumbo 8547 */ 8548 /* exop vBBBB, field@AAAAAAAA */ 8549 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8550 FETCH(r0, 1) @ r0<- aaaa (lo) 8551 FETCH(r1, 2) @ r1<- AAAA (hi) 8552 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8553 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8554 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8555 cmp r0, #0 @ is resolved entry null? 8556 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve 8557.LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0 8558 FETCH(r2, 3) @ r2<- BBBB 8559 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8560 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8561 GET_INST_OPCODE(ip) @ extract opcode from rINST 8562 @ no-op @ releasing store 8563 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8564 GOTO_OPCODE(ip) @ jump to next instruction 8565 8566 8567/* ------------------------------ */ 8568 .balign 64 8569.L_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 8570/* File: armv5te/OP_SPUT_BYTE_JUMBO.S */ 8571/* File: armv5te/OP_SPUT_JUMBO.S */ 8572 /* 8573 * Jumbo 32-bit SPUT handler. 8574 * 8575 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8576 * sput-short/jumbo 8577 */ 8578 /* exop vBBBB, field@AAAAAAAA */ 8579 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8580 FETCH(r0, 1) @ r0<- aaaa (lo) 8581 FETCH(r1, 2) @ r1<- AAAA (hi) 8582 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8583 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8584 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8585 cmp r0, #0 @ is resolved entry null? 8586 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve 8587.LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0 8588 FETCH(r2, 3) @ r2<- BBBB 8589 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8590 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8591 GET_INST_OPCODE(ip) @ extract opcode from rINST 8592 @ no-op @ releasing store 8593 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8594 GOTO_OPCODE(ip) @ jump to next instruction 8595 8596 8597/* ------------------------------ */ 8598 .balign 64 8599.L_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 8600/* File: armv5te/OP_SPUT_CHAR_JUMBO.S */ 8601/* File: armv5te/OP_SPUT_JUMBO.S */ 8602 /* 8603 * Jumbo 32-bit SPUT handler. 8604 * 8605 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8606 * sput-short/jumbo 8607 */ 8608 /* exop vBBBB, field@AAAAAAAA */ 8609 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8610 FETCH(r0, 1) @ r0<- aaaa (lo) 8611 FETCH(r1, 2) @ r1<- AAAA (hi) 8612 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8613 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8614 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8615 cmp r0, #0 @ is resolved entry null? 8616 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve 8617.LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0 8618 FETCH(r2, 3) @ r2<- BBBB 8619 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8620 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8621 GET_INST_OPCODE(ip) @ extract opcode from rINST 8622 @ no-op @ releasing store 8623 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8624 GOTO_OPCODE(ip) @ jump to next instruction 8625 8626 8627/* ------------------------------ */ 8628 .balign 64 8629.L_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 8630/* File: armv5te/OP_SPUT_SHORT_JUMBO.S */ 8631/* File: armv5te/OP_SPUT_JUMBO.S */ 8632 /* 8633 * Jumbo 32-bit SPUT handler. 8634 * 8635 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8636 * sput-short/jumbo 8637 */ 8638 /* exop vBBBB, field@AAAAAAAA */ 8639 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8640 FETCH(r0, 1) @ r0<- aaaa (lo) 8641 FETCH(r1, 2) @ r1<- AAAA (hi) 8642 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8643 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8644 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8645 cmp r0, #0 @ is resolved entry null? 8646 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve 8647.LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0 8648 FETCH(r2, 3) @ r2<- BBBB 8649 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8650 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8651 GET_INST_OPCODE(ip) @ extract opcode from rINST 8652 @ no-op @ releasing store 8653 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8654 GOTO_OPCODE(ip) @ jump to next instruction 8655 8656 8657/* ------------------------------ */ 8658 .balign 64 8659.L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 8660/* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */ 8661 /* 8662 * Handle a virtual method call. 8663 */ 8664 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8665 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8666 FETCH(r0, 1) @ r1<- aaaa (lo) 8667 FETCH(r1, 2) @ r1<- AAAA (hi) 8668 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8669 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8670 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8671 cmp r0, #0 @ already resolved? 8672 EXPORT_PC() @ must export for invoke 8673 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on 8674 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8675 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8676 mov r2, #METHOD_VIRTUAL @ resolver method type 8677 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8678 cmp r0, #0 @ got null? 8679 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue 8680 b common_exceptionThrown @ yes, handle exception 8681 8682/* ------------------------------ */ 8683 .balign 64 8684.L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 8685/* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */ 8686 /* 8687 * Handle a "super" method call. 8688 */ 8689 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8690 FETCH(r10, 4) @ r10<- CCCC 8691 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8692 FETCH(r0, 1) @ r1<- aaaa (lo) 8693 FETCH(r1, 2) @ r1<- AAAA (hi) 8694 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8695 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8696 GET_VREG(r2, r10) @ r2<- "this" ptr 8697 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8698 cmp r2, #0 @ null "this"? 8699 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8700 beq common_errNullObject @ null "this", throw exception 8701 cmp r0, #0 @ already resolved? 8702 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 8703 EXPORT_PC() @ must export for invoke 8704 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on 8705 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now 8706 8707/* ------------------------------ */ 8708 .balign 64 8709.L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 8710/* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */ 8711 /* 8712 * Handle a direct method call. 8713 * 8714 * (We could defer the "is 'this' pointer null" test to the common 8715 * method invocation code, and use a flag to indicate that static 8716 * calls don't count. If we do this as part of copying the arguments 8717 * out we could avoiding loading the first arg twice.) 8718 * 8719 */ 8720 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8721 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8722 FETCH(r0, 1) @ r1<- aaaa (lo) 8723 FETCH(r1, 2) @ r1<- AAAA (hi) 8724 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8725 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8726 FETCH(r10, 4) @ r10<- CCCC 8727 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8728 cmp r0, #0 @ already resolved? 8729 EXPORT_PC() @ must export for invoke 8730 GET_VREG(r2, r10) @ r2<- "this" ptr 8731 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now 8732.LOP_INVOKE_DIRECT_JUMBO_finish: 8733 cmp r2, #0 @ null "this" ref? 8734 bne common_invokeMethodJumbo @ no, continue on 8735 b common_errNullObject @ yes, throw exception 8736 8737/* ------------------------------ */ 8738 .balign 64 8739.L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 8740/* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */ 8741 /* 8742 * Handle a static method call. 8743 */ 8744 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8745 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8746 FETCH(r0, 1) @ r1<- aaaa (lo) 8747 FETCH(r1, 2) @ r1<- AAAA (hi) 8748 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8749 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8750 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8751 cmp r0, #0 @ already resolved? 8752 EXPORT_PC() @ must export for invoke 8753 bne common_invokeMethodJumbo @ yes, continue on 87540: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8755 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8756 mov r2, #METHOD_STATIC @ resolver method type 8757 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8758 cmp r0, #0 @ got null? 8759 bne common_invokeMethodJumbo @ no, continue 8760 b common_exceptionThrown @ yes, handle exception 8761 8762/* ------------------------------ */ 8763 .balign 64 8764.L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 8765/* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */ 8766 /* 8767 * Handle an interface method call. 8768 */ 8769 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8770 FETCH(r2, 4) @ r2<- CCCC 8771 FETCH(r0, 1) @ r0<- aaaa (lo) 8772 FETCH(r1, 2) @ r1<- AAAA (hi) 8773 EXPORT_PC() @ must export for invoke 8774 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8775 GET_VREG(r0, r2) @ r0<- first arg ("this") 8776 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 8777 cmp r0, #0 @ null obj? 8778 ldr r2, [rSELF, #offThread_method] @ r2<- method 8779 beq common_errNullObject @ yes, fail 8780 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 8781 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 8782 cmp r0, #0 @ failed? 8783 beq common_exceptionThrown @ yes, handle exception 8784 b common_invokeMethodJumbo @ jump to common handler 8785 8786/* ------------------------------ */ 8787 .balign 64 8788.L_OP_UNUSED_27FF: /* 0x127 */ 8789/* File: armv5te/OP_UNUSED_27FF.S */ 8790/* File: armv5te/unused.S */ 8791 bl common_abort 8792 8793 8794/* ------------------------------ */ 8795 .balign 64 8796.L_OP_UNUSED_28FF: /* 0x128 */ 8797/* File: armv5te/OP_UNUSED_28FF.S */ 8798/* File: armv5te/unused.S */ 8799 bl common_abort 8800 8801 8802/* ------------------------------ */ 8803 .balign 64 8804.L_OP_UNUSED_29FF: /* 0x129 */ 8805/* File: armv5te/OP_UNUSED_29FF.S */ 8806/* File: armv5te/unused.S */ 8807 bl common_abort 8808 8809 8810/* ------------------------------ */ 8811 .balign 64 8812.L_OP_UNUSED_2AFF: /* 0x12a */ 8813/* File: armv5te/OP_UNUSED_2AFF.S */ 8814/* File: armv5te/unused.S */ 8815 bl common_abort 8816 8817 8818/* ------------------------------ */ 8819 .balign 64 8820.L_OP_UNUSED_2BFF: /* 0x12b */ 8821/* File: armv5te/OP_UNUSED_2BFF.S */ 8822/* File: armv5te/unused.S */ 8823 bl common_abort 8824 8825 8826/* ------------------------------ */ 8827 .balign 64 8828.L_OP_UNUSED_2CFF: /* 0x12c */ 8829/* File: armv5te/OP_UNUSED_2CFF.S */ 8830/* File: armv5te/unused.S */ 8831 bl common_abort 8832 8833 8834/* ------------------------------ */ 8835 .balign 64 8836.L_OP_UNUSED_2DFF: /* 0x12d */ 8837/* File: armv5te/OP_UNUSED_2DFF.S */ 8838/* File: armv5te/unused.S */ 8839 bl common_abort 8840 8841 8842/* ------------------------------ */ 8843 .balign 64 8844.L_OP_UNUSED_2EFF: /* 0x12e */ 8845/* File: armv5te/OP_UNUSED_2EFF.S */ 8846/* File: armv5te/unused.S */ 8847 bl common_abort 8848 8849 8850/* ------------------------------ */ 8851 .balign 64 8852.L_OP_UNUSED_2FFF: /* 0x12f */ 8853/* File: armv5te/OP_UNUSED_2FFF.S */ 8854/* File: armv5te/unused.S */ 8855 bl common_abort 8856 8857 8858/* ------------------------------ */ 8859 .balign 64 8860.L_OP_UNUSED_30FF: /* 0x130 */ 8861/* File: armv5te/OP_UNUSED_30FF.S */ 8862/* File: armv5te/unused.S */ 8863 bl common_abort 8864 8865 8866/* ------------------------------ */ 8867 .balign 64 8868.L_OP_UNUSED_31FF: /* 0x131 */ 8869/* File: armv5te/OP_UNUSED_31FF.S */ 8870/* File: armv5te/unused.S */ 8871 bl common_abort 8872 8873 8874/* ------------------------------ */ 8875 .balign 64 8876.L_OP_UNUSED_32FF: /* 0x132 */ 8877/* File: armv5te/OP_UNUSED_32FF.S */ 8878/* File: armv5te/unused.S */ 8879 bl common_abort 8880 8881 8882/* ------------------------------ */ 8883 .balign 64 8884.L_OP_UNUSED_33FF: /* 0x133 */ 8885/* File: armv5te/OP_UNUSED_33FF.S */ 8886/* File: armv5te/unused.S */ 8887 bl common_abort 8888 8889 8890/* ------------------------------ */ 8891 .balign 64 8892.L_OP_UNUSED_34FF: /* 0x134 */ 8893/* File: armv5te/OP_UNUSED_34FF.S */ 8894/* File: armv5te/unused.S */ 8895 bl common_abort 8896 8897 8898/* ------------------------------ */ 8899 .balign 64 8900.L_OP_UNUSED_35FF: /* 0x135 */ 8901/* File: armv5te/OP_UNUSED_35FF.S */ 8902/* File: armv5te/unused.S */ 8903 bl common_abort 8904 8905 8906/* ------------------------------ */ 8907 .balign 64 8908.L_OP_UNUSED_36FF: /* 0x136 */ 8909/* File: armv5te/OP_UNUSED_36FF.S */ 8910/* File: armv5te/unused.S */ 8911 bl common_abort 8912 8913 8914/* ------------------------------ */ 8915 .balign 64 8916.L_OP_UNUSED_37FF: /* 0x137 */ 8917/* File: armv5te/OP_UNUSED_37FF.S */ 8918/* File: armv5te/unused.S */ 8919 bl common_abort 8920 8921 8922/* ------------------------------ */ 8923 .balign 64 8924.L_OP_UNUSED_38FF: /* 0x138 */ 8925/* File: armv5te/OP_UNUSED_38FF.S */ 8926/* File: armv5te/unused.S */ 8927 bl common_abort 8928 8929 8930/* ------------------------------ */ 8931 .balign 64 8932.L_OP_UNUSED_39FF: /* 0x139 */ 8933/* File: armv5te/OP_UNUSED_39FF.S */ 8934/* File: armv5te/unused.S */ 8935 bl common_abort 8936 8937 8938/* ------------------------------ */ 8939 .balign 64 8940.L_OP_UNUSED_3AFF: /* 0x13a */ 8941/* File: armv5te/OP_UNUSED_3AFF.S */ 8942/* File: armv5te/unused.S */ 8943 bl common_abort 8944 8945 8946/* ------------------------------ */ 8947 .balign 64 8948.L_OP_UNUSED_3BFF: /* 0x13b */ 8949/* File: armv5te/OP_UNUSED_3BFF.S */ 8950/* File: armv5te/unused.S */ 8951 bl common_abort 8952 8953 8954/* ------------------------------ */ 8955 .balign 64 8956.L_OP_UNUSED_3CFF: /* 0x13c */ 8957/* File: armv5te/OP_UNUSED_3CFF.S */ 8958/* File: armv5te/unused.S */ 8959 bl common_abort 8960 8961 8962/* ------------------------------ */ 8963 .balign 64 8964.L_OP_UNUSED_3DFF: /* 0x13d */ 8965/* File: armv5te/OP_UNUSED_3DFF.S */ 8966/* File: armv5te/unused.S */ 8967 bl common_abort 8968 8969 8970/* ------------------------------ */ 8971 .balign 64 8972.L_OP_UNUSED_3EFF: /* 0x13e */ 8973/* File: armv5te/OP_UNUSED_3EFF.S */ 8974/* File: armv5te/unused.S */ 8975 bl common_abort 8976 8977 8978/* ------------------------------ */ 8979 .balign 64 8980.L_OP_UNUSED_3FFF: /* 0x13f */ 8981/* File: armv5te/OP_UNUSED_3FFF.S */ 8982/* File: armv5te/unused.S */ 8983 bl common_abort 8984 8985 8986/* ------------------------------ */ 8987 .balign 64 8988.L_OP_UNUSED_40FF: /* 0x140 */ 8989/* File: armv5te/OP_UNUSED_40FF.S */ 8990/* File: armv5te/unused.S */ 8991 bl common_abort 8992 8993 8994/* ------------------------------ */ 8995 .balign 64 8996.L_OP_UNUSED_41FF: /* 0x141 */ 8997/* File: armv5te/OP_UNUSED_41FF.S */ 8998/* File: armv5te/unused.S */ 8999 bl common_abort 9000 9001 9002/* ------------------------------ */ 9003 .balign 64 9004.L_OP_UNUSED_42FF: /* 0x142 */ 9005/* File: armv5te/OP_UNUSED_42FF.S */ 9006/* File: armv5te/unused.S */ 9007 bl common_abort 9008 9009 9010/* ------------------------------ */ 9011 .balign 64 9012.L_OP_UNUSED_43FF: /* 0x143 */ 9013/* File: armv5te/OP_UNUSED_43FF.S */ 9014/* File: armv5te/unused.S */ 9015 bl common_abort 9016 9017 9018/* ------------------------------ */ 9019 .balign 64 9020.L_OP_UNUSED_44FF: /* 0x144 */ 9021/* File: armv5te/OP_UNUSED_44FF.S */ 9022/* File: armv5te/unused.S */ 9023 bl common_abort 9024 9025 9026/* ------------------------------ */ 9027 .balign 64 9028.L_OP_UNUSED_45FF: /* 0x145 */ 9029/* File: armv5te/OP_UNUSED_45FF.S */ 9030/* File: armv5te/unused.S */ 9031 bl common_abort 9032 9033 9034/* ------------------------------ */ 9035 .balign 64 9036.L_OP_UNUSED_46FF: /* 0x146 */ 9037/* File: armv5te/OP_UNUSED_46FF.S */ 9038/* File: armv5te/unused.S */ 9039 bl common_abort 9040 9041 9042/* ------------------------------ */ 9043 .balign 64 9044.L_OP_UNUSED_47FF: /* 0x147 */ 9045/* File: armv5te/OP_UNUSED_47FF.S */ 9046/* File: armv5te/unused.S */ 9047 bl common_abort 9048 9049 9050/* ------------------------------ */ 9051 .balign 64 9052.L_OP_UNUSED_48FF: /* 0x148 */ 9053/* File: armv5te/OP_UNUSED_48FF.S */ 9054/* File: armv5te/unused.S */ 9055 bl common_abort 9056 9057 9058/* ------------------------------ */ 9059 .balign 64 9060.L_OP_UNUSED_49FF: /* 0x149 */ 9061/* File: armv5te/OP_UNUSED_49FF.S */ 9062/* File: armv5te/unused.S */ 9063 bl common_abort 9064 9065 9066/* ------------------------------ */ 9067 .balign 64 9068.L_OP_UNUSED_4AFF: /* 0x14a */ 9069/* File: armv5te/OP_UNUSED_4AFF.S */ 9070/* File: armv5te/unused.S */ 9071 bl common_abort 9072 9073 9074/* ------------------------------ */ 9075 .balign 64 9076.L_OP_UNUSED_4BFF: /* 0x14b */ 9077/* File: armv5te/OP_UNUSED_4BFF.S */ 9078/* File: armv5te/unused.S */ 9079 bl common_abort 9080 9081 9082/* ------------------------------ */ 9083 .balign 64 9084.L_OP_UNUSED_4CFF: /* 0x14c */ 9085/* File: armv5te/OP_UNUSED_4CFF.S */ 9086/* File: armv5te/unused.S */ 9087 bl common_abort 9088 9089 9090/* ------------------------------ */ 9091 .balign 64 9092.L_OP_UNUSED_4DFF: /* 0x14d */ 9093/* File: armv5te/OP_UNUSED_4DFF.S */ 9094/* File: armv5te/unused.S */ 9095 bl common_abort 9096 9097 9098/* ------------------------------ */ 9099 .balign 64 9100.L_OP_UNUSED_4EFF: /* 0x14e */ 9101/* File: armv5te/OP_UNUSED_4EFF.S */ 9102/* File: armv5te/unused.S */ 9103 bl common_abort 9104 9105 9106/* ------------------------------ */ 9107 .balign 64 9108.L_OP_UNUSED_4FFF: /* 0x14f */ 9109/* File: armv5te/OP_UNUSED_4FFF.S */ 9110/* File: armv5te/unused.S */ 9111 bl common_abort 9112 9113 9114/* ------------------------------ */ 9115 .balign 64 9116.L_OP_UNUSED_50FF: /* 0x150 */ 9117/* File: armv5te/OP_UNUSED_50FF.S */ 9118/* File: armv5te/unused.S */ 9119 bl common_abort 9120 9121 9122/* ------------------------------ */ 9123 .balign 64 9124.L_OP_UNUSED_51FF: /* 0x151 */ 9125/* File: armv5te/OP_UNUSED_51FF.S */ 9126/* File: armv5te/unused.S */ 9127 bl common_abort 9128 9129 9130/* ------------------------------ */ 9131 .balign 64 9132.L_OP_UNUSED_52FF: /* 0x152 */ 9133/* File: armv5te/OP_UNUSED_52FF.S */ 9134/* File: armv5te/unused.S */ 9135 bl common_abort 9136 9137 9138/* ------------------------------ */ 9139 .balign 64 9140.L_OP_UNUSED_53FF: /* 0x153 */ 9141/* File: armv5te/OP_UNUSED_53FF.S */ 9142/* File: armv5te/unused.S */ 9143 bl common_abort 9144 9145 9146/* ------------------------------ */ 9147 .balign 64 9148.L_OP_UNUSED_54FF: /* 0x154 */ 9149/* File: armv5te/OP_UNUSED_54FF.S */ 9150/* File: armv5te/unused.S */ 9151 bl common_abort 9152 9153 9154/* ------------------------------ */ 9155 .balign 64 9156.L_OP_UNUSED_55FF: /* 0x155 */ 9157/* File: armv5te/OP_UNUSED_55FF.S */ 9158/* File: armv5te/unused.S */ 9159 bl common_abort 9160 9161 9162/* ------------------------------ */ 9163 .balign 64 9164.L_OP_UNUSED_56FF: /* 0x156 */ 9165/* File: armv5te/OP_UNUSED_56FF.S */ 9166/* File: armv5te/unused.S */ 9167 bl common_abort 9168 9169 9170/* ------------------------------ */ 9171 .balign 64 9172.L_OP_UNUSED_57FF: /* 0x157 */ 9173/* File: armv5te/OP_UNUSED_57FF.S */ 9174/* File: armv5te/unused.S */ 9175 bl common_abort 9176 9177 9178/* ------------------------------ */ 9179 .balign 64 9180.L_OP_UNUSED_58FF: /* 0x158 */ 9181/* File: armv5te/OP_UNUSED_58FF.S */ 9182/* File: armv5te/unused.S */ 9183 bl common_abort 9184 9185 9186/* ------------------------------ */ 9187 .balign 64 9188.L_OP_UNUSED_59FF: /* 0x159 */ 9189/* File: armv5te/OP_UNUSED_59FF.S */ 9190/* File: armv5te/unused.S */ 9191 bl common_abort 9192 9193 9194/* ------------------------------ */ 9195 .balign 64 9196.L_OP_UNUSED_5AFF: /* 0x15a */ 9197/* File: armv5te/OP_UNUSED_5AFF.S */ 9198/* File: armv5te/unused.S */ 9199 bl common_abort 9200 9201 9202/* ------------------------------ */ 9203 .balign 64 9204.L_OP_UNUSED_5BFF: /* 0x15b */ 9205/* File: armv5te/OP_UNUSED_5BFF.S */ 9206/* File: armv5te/unused.S */ 9207 bl common_abort 9208 9209 9210/* ------------------------------ */ 9211 .balign 64 9212.L_OP_UNUSED_5CFF: /* 0x15c */ 9213/* File: armv5te/OP_UNUSED_5CFF.S */ 9214/* File: armv5te/unused.S */ 9215 bl common_abort 9216 9217 9218/* ------------------------------ */ 9219 .balign 64 9220.L_OP_UNUSED_5DFF: /* 0x15d */ 9221/* File: armv5te/OP_UNUSED_5DFF.S */ 9222/* File: armv5te/unused.S */ 9223 bl common_abort 9224 9225 9226/* ------------------------------ */ 9227 .balign 64 9228.L_OP_UNUSED_5EFF: /* 0x15e */ 9229/* File: armv5te/OP_UNUSED_5EFF.S */ 9230/* File: armv5te/unused.S */ 9231 bl common_abort 9232 9233 9234/* ------------------------------ */ 9235 .balign 64 9236.L_OP_UNUSED_5FFF: /* 0x15f */ 9237/* File: armv5te/OP_UNUSED_5FFF.S */ 9238/* File: armv5te/unused.S */ 9239 bl common_abort 9240 9241 9242/* ------------------------------ */ 9243 .balign 64 9244.L_OP_UNUSED_60FF: /* 0x160 */ 9245/* File: armv5te/OP_UNUSED_60FF.S */ 9246/* File: armv5te/unused.S */ 9247 bl common_abort 9248 9249 9250/* ------------------------------ */ 9251 .balign 64 9252.L_OP_UNUSED_61FF: /* 0x161 */ 9253/* File: armv5te/OP_UNUSED_61FF.S */ 9254/* File: armv5te/unused.S */ 9255 bl common_abort 9256 9257 9258/* ------------------------------ */ 9259 .balign 64 9260.L_OP_UNUSED_62FF: /* 0x162 */ 9261/* File: armv5te/OP_UNUSED_62FF.S */ 9262/* File: armv5te/unused.S */ 9263 bl common_abort 9264 9265 9266/* ------------------------------ */ 9267 .balign 64 9268.L_OP_UNUSED_63FF: /* 0x163 */ 9269/* File: armv5te/OP_UNUSED_63FF.S */ 9270/* File: armv5te/unused.S */ 9271 bl common_abort 9272 9273 9274/* ------------------------------ */ 9275 .balign 64 9276.L_OP_UNUSED_64FF: /* 0x164 */ 9277/* File: armv5te/OP_UNUSED_64FF.S */ 9278/* File: armv5te/unused.S */ 9279 bl common_abort 9280 9281 9282/* ------------------------------ */ 9283 .balign 64 9284.L_OP_UNUSED_65FF: /* 0x165 */ 9285/* File: armv5te/OP_UNUSED_65FF.S */ 9286/* File: armv5te/unused.S */ 9287 bl common_abort 9288 9289 9290/* ------------------------------ */ 9291 .balign 64 9292.L_OP_UNUSED_66FF: /* 0x166 */ 9293/* File: armv5te/OP_UNUSED_66FF.S */ 9294/* File: armv5te/unused.S */ 9295 bl common_abort 9296 9297 9298/* ------------------------------ */ 9299 .balign 64 9300.L_OP_UNUSED_67FF: /* 0x167 */ 9301/* File: armv5te/OP_UNUSED_67FF.S */ 9302/* File: armv5te/unused.S */ 9303 bl common_abort 9304 9305 9306/* ------------------------------ */ 9307 .balign 64 9308.L_OP_UNUSED_68FF: /* 0x168 */ 9309/* File: armv5te/OP_UNUSED_68FF.S */ 9310/* File: armv5te/unused.S */ 9311 bl common_abort 9312 9313 9314/* ------------------------------ */ 9315 .balign 64 9316.L_OP_UNUSED_69FF: /* 0x169 */ 9317/* File: armv5te/OP_UNUSED_69FF.S */ 9318/* File: armv5te/unused.S */ 9319 bl common_abort 9320 9321 9322/* ------------------------------ */ 9323 .balign 64 9324.L_OP_UNUSED_6AFF: /* 0x16a */ 9325/* File: armv5te/OP_UNUSED_6AFF.S */ 9326/* File: armv5te/unused.S */ 9327 bl common_abort 9328 9329 9330/* ------------------------------ */ 9331 .balign 64 9332.L_OP_UNUSED_6BFF: /* 0x16b */ 9333/* File: armv5te/OP_UNUSED_6BFF.S */ 9334/* File: armv5te/unused.S */ 9335 bl common_abort 9336 9337 9338/* ------------------------------ */ 9339 .balign 64 9340.L_OP_UNUSED_6CFF: /* 0x16c */ 9341/* File: armv5te/OP_UNUSED_6CFF.S */ 9342/* File: armv5te/unused.S */ 9343 bl common_abort 9344 9345 9346/* ------------------------------ */ 9347 .balign 64 9348.L_OP_UNUSED_6DFF: /* 0x16d */ 9349/* File: armv5te/OP_UNUSED_6DFF.S */ 9350/* File: armv5te/unused.S */ 9351 bl common_abort 9352 9353 9354/* ------------------------------ */ 9355 .balign 64 9356.L_OP_UNUSED_6EFF: /* 0x16e */ 9357/* File: armv5te/OP_UNUSED_6EFF.S */ 9358/* File: armv5te/unused.S */ 9359 bl common_abort 9360 9361 9362/* ------------------------------ */ 9363 .balign 64 9364.L_OP_UNUSED_6FFF: /* 0x16f */ 9365/* File: armv5te/OP_UNUSED_6FFF.S */ 9366/* File: armv5te/unused.S */ 9367 bl common_abort 9368 9369 9370/* ------------------------------ */ 9371 .balign 64 9372.L_OP_UNUSED_70FF: /* 0x170 */ 9373/* File: armv5te/OP_UNUSED_70FF.S */ 9374/* File: armv5te/unused.S */ 9375 bl common_abort 9376 9377 9378/* ------------------------------ */ 9379 .balign 64 9380.L_OP_UNUSED_71FF: /* 0x171 */ 9381/* File: armv5te/OP_UNUSED_71FF.S */ 9382/* File: armv5te/unused.S */ 9383 bl common_abort 9384 9385 9386/* ------------------------------ */ 9387 .balign 64 9388.L_OP_UNUSED_72FF: /* 0x172 */ 9389/* File: armv5te/OP_UNUSED_72FF.S */ 9390/* File: armv5te/unused.S */ 9391 bl common_abort 9392 9393 9394/* ------------------------------ */ 9395 .balign 64 9396.L_OP_UNUSED_73FF: /* 0x173 */ 9397/* File: armv5te/OP_UNUSED_73FF.S */ 9398/* File: armv5te/unused.S */ 9399 bl common_abort 9400 9401 9402/* ------------------------------ */ 9403 .balign 64 9404.L_OP_UNUSED_74FF: /* 0x174 */ 9405/* File: armv5te/OP_UNUSED_74FF.S */ 9406/* File: armv5te/unused.S */ 9407 bl common_abort 9408 9409 9410/* ------------------------------ */ 9411 .balign 64 9412.L_OP_UNUSED_75FF: /* 0x175 */ 9413/* File: armv5te/OP_UNUSED_75FF.S */ 9414/* File: armv5te/unused.S */ 9415 bl common_abort 9416 9417 9418/* ------------------------------ */ 9419 .balign 64 9420.L_OP_UNUSED_76FF: /* 0x176 */ 9421/* File: armv5te/OP_UNUSED_76FF.S */ 9422/* File: armv5te/unused.S */ 9423 bl common_abort 9424 9425 9426/* ------------------------------ */ 9427 .balign 64 9428.L_OP_UNUSED_77FF: /* 0x177 */ 9429/* File: armv5te/OP_UNUSED_77FF.S */ 9430/* File: armv5te/unused.S */ 9431 bl common_abort 9432 9433 9434/* ------------------------------ */ 9435 .balign 64 9436.L_OP_UNUSED_78FF: /* 0x178 */ 9437/* File: armv5te/OP_UNUSED_78FF.S */ 9438/* File: armv5te/unused.S */ 9439 bl common_abort 9440 9441 9442/* ------------------------------ */ 9443 .balign 64 9444.L_OP_UNUSED_79FF: /* 0x179 */ 9445/* File: armv5te/OP_UNUSED_79FF.S */ 9446/* File: armv5te/unused.S */ 9447 bl common_abort 9448 9449 9450/* ------------------------------ */ 9451 .balign 64 9452.L_OP_UNUSED_7AFF: /* 0x17a */ 9453/* File: armv5te/OP_UNUSED_7AFF.S */ 9454/* File: armv5te/unused.S */ 9455 bl common_abort 9456 9457 9458/* ------------------------------ */ 9459 .balign 64 9460.L_OP_UNUSED_7BFF: /* 0x17b */ 9461/* File: armv5te/OP_UNUSED_7BFF.S */ 9462/* File: armv5te/unused.S */ 9463 bl common_abort 9464 9465 9466/* ------------------------------ */ 9467 .balign 64 9468.L_OP_UNUSED_7CFF: /* 0x17c */ 9469/* File: armv5te/OP_UNUSED_7CFF.S */ 9470/* File: armv5te/unused.S */ 9471 bl common_abort 9472 9473 9474/* ------------------------------ */ 9475 .balign 64 9476.L_OP_UNUSED_7DFF: /* 0x17d */ 9477/* File: armv5te/OP_UNUSED_7DFF.S */ 9478/* File: armv5te/unused.S */ 9479 bl common_abort 9480 9481 9482/* ------------------------------ */ 9483 .balign 64 9484.L_OP_UNUSED_7EFF: /* 0x17e */ 9485/* File: armv5te/OP_UNUSED_7EFF.S */ 9486/* File: armv5te/unused.S */ 9487 bl common_abort 9488 9489 9490/* ------------------------------ */ 9491 .balign 64 9492.L_OP_UNUSED_7FFF: /* 0x17f */ 9493/* File: armv5te/OP_UNUSED_7FFF.S */ 9494/* File: armv5te/unused.S */ 9495 bl common_abort 9496 9497 9498/* ------------------------------ */ 9499 .balign 64 9500.L_OP_UNUSED_80FF: /* 0x180 */ 9501/* File: armv5te/OP_UNUSED_80FF.S */ 9502/* File: armv5te/unused.S */ 9503 bl common_abort 9504 9505 9506/* ------------------------------ */ 9507 .balign 64 9508.L_OP_UNUSED_81FF: /* 0x181 */ 9509/* File: armv5te/OP_UNUSED_81FF.S */ 9510/* File: armv5te/unused.S */ 9511 bl common_abort 9512 9513 9514/* ------------------------------ */ 9515 .balign 64 9516.L_OP_UNUSED_82FF: /* 0x182 */ 9517/* File: armv5te/OP_UNUSED_82FF.S */ 9518/* File: armv5te/unused.S */ 9519 bl common_abort 9520 9521 9522/* ------------------------------ */ 9523 .balign 64 9524.L_OP_UNUSED_83FF: /* 0x183 */ 9525/* File: armv5te/OP_UNUSED_83FF.S */ 9526/* File: armv5te/unused.S */ 9527 bl common_abort 9528 9529 9530/* ------------------------------ */ 9531 .balign 64 9532.L_OP_UNUSED_84FF: /* 0x184 */ 9533/* File: armv5te/OP_UNUSED_84FF.S */ 9534/* File: armv5te/unused.S */ 9535 bl common_abort 9536 9537 9538/* ------------------------------ */ 9539 .balign 64 9540.L_OP_UNUSED_85FF: /* 0x185 */ 9541/* File: armv5te/OP_UNUSED_85FF.S */ 9542/* File: armv5te/unused.S */ 9543 bl common_abort 9544 9545 9546/* ------------------------------ */ 9547 .balign 64 9548.L_OP_UNUSED_86FF: /* 0x186 */ 9549/* File: armv5te/OP_UNUSED_86FF.S */ 9550/* File: armv5te/unused.S */ 9551 bl common_abort 9552 9553 9554/* ------------------------------ */ 9555 .balign 64 9556.L_OP_UNUSED_87FF: /* 0x187 */ 9557/* File: armv5te/OP_UNUSED_87FF.S */ 9558/* File: armv5te/unused.S */ 9559 bl common_abort 9560 9561 9562/* ------------------------------ */ 9563 .balign 64 9564.L_OP_UNUSED_88FF: /* 0x188 */ 9565/* File: armv5te/OP_UNUSED_88FF.S */ 9566/* File: armv5te/unused.S */ 9567 bl common_abort 9568 9569 9570/* ------------------------------ */ 9571 .balign 64 9572.L_OP_UNUSED_89FF: /* 0x189 */ 9573/* File: armv5te/OP_UNUSED_89FF.S */ 9574/* File: armv5te/unused.S */ 9575 bl common_abort 9576 9577 9578/* ------------------------------ */ 9579 .balign 64 9580.L_OP_UNUSED_8AFF: /* 0x18a */ 9581/* File: armv5te/OP_UNUSED_8AFF.S */ 9582/* File: armv5te/unused.S */ 9583 bl common_abort 9584 9585 9586/* ------------------------------ */ 9587 .balign 64 9588.L_OP_UNUSED_8BFF: /* 0x18b */ 9589/* File: armv5te/OP_UNUSED_8BFF.S */ 9590/* File: armv5te/unused.S */ 9591 bl common_abort 9592 9593 9594/* ------------------------------ */ 9595 .balign 64 9596.L_OP_UNUSED_8CFF: /* 0x18c */ 9597/* File: armv5te/OP_UNUSED_8CFF.S */ 9598/* File: armv5te/unused.S */ 9599 bl common_abort 9600 9601 9602/* ------------------------------ */ 9603 .balign 64 9604.L_OP_UNUSED_8DFF: /* 0x18d */ 9605/* File: armv5te/OP_UNUSED_8DFF.S */ 9606/* File: armv5te/unused.S */ 9607 bl common_abort 9608 9609 9610/* ------------------------------ */ 9611 .balign 64 9612.L_OP_UNUSED_8EFF: /* 0x18e */ 9613/* File: armv5te/OP_UNUSED_8EFF.S */ 9614/* File: armv5te/unused.S */ 9615 bl common_abort 9616 9617 9618/* ------------------------------ */ 9619 .balign 64 9620.L_OP_UNUSED_8FFF: /* 0x18f */ 9621/* File: armv5te/OP_UNUSED_8FFF.S */ 9622/* File: armv5te/unused.S */ 9623 bl common_abort 9624 9625 9626/* ------------------------------ */ 9627 .balign 64 9628.L_OP_UNUSED_90FF: /* 0x190 */ 9629/* File: armv5te/OP_UNUSED_90FF.S */ 9630/* File: armv5te/unused.S */ 9631 bl common_abort 9632 9633 9634/* ------------------------------ */ 9635 .balign 64 9636.L_OP_UNUSED_91FF: /* 0x191 */ 9637/* File: armv5te/OP_UNUSED_91FF.S */ 9638/* File: armv5te/unused.S */ 9639 bl common_abort 9640 9641 9642/* ------------------------------ */ 9643 .balign 64 9644.L_OP_UNUSED_92FF: /* 0x192 */ 9645/* File: armv5te/OP_UNUSED_92FF.S */ 9646/* File: armv5te/unused.S */ 9647 bl common_abort 9648 9649 9650/* ------------------------------ */ 9651 .balign 64 9652.L_OP_UNUSED_93FF: /* 0x193 */ 9653/* File: armv5te/OP_UNUSED_93FF.S */ 9654/* File: armv5te/unused.S */ 9655 bl common_abort 9656 9657 9658/* ------------------------------ */ 9659 .balign 64 9660.L_OP_UNUSED_94FF: /* 0x194 */ 9661/* File: armv5te/OP_UNUSED_94FF.S */ 9662/* File: armv5te/unused.S */ 9663 bl common_abort 9664 9665 9666/* ------------------------------ */ 9667 .balign 64 9668.L_OP_UNUSED_95FF: /* 0x195 */ 9669/* File: armv5te/OP_UNUSED_95FF.S */ 9670/* File: armv5te/unused.S */ 9671 bl common_abort 9672 9673 9674/* ------------------------------ */ 9675 .balign 64 9676.L_OP_UNUSED_96FF: /* 0x196 */ 9677/* File: armv5te/OP_UNUSED_96FF.S */ 9678/* File: armv5te/unused.S */ 9679 bl common_abort 9680 9681 9682/* ------------------------------ */ 9683 .balign 64 9684.L_OP_UNUSED_97FF: /* 0x197 */ 9685/* File: armv5te/OP_UNUSED_97FF.S */ 9686/* File: armv5te/unused.S */ 9687 bl common_abort 9688 9689 9690/* ------------------------------ */ 9691 .balign 64 9692.L_OP_UNUSED_98FF: /* 0x198 */ 9693/* File: armv5te/OP_UNUSED_98FF.S */ 9694/* File: armv5te/unused.S */ 9695 bl common_abort 9696 9697 9698/* ------------------------------ */ 9699 .balign 64 9700.L_OP_UNUSED_99FF: /* 0x199 */ 9701/* File: armv5te/OP_UNUSED_99FF.S */ 9702/* File: armv5te/unused.S */ 9703 bl common_abort 9704 9705 9706/* ------------------------------ */ 9707 .balign 64 9708.L_OP_UNUSED_9AFF: /* 0x19a */ 9709/* File: armv5te/OP_UNUSED_9AFF.S */ 9710/* File: armv5te/unused.S */ 9711 bl common_abort 9712 9713 9714/* ------------------------------ */ 9715 .balign 64 9716.L_OP_UNUSED_9BFF: /* 0x19b */ 9717/* File: armv5te/OP_UNUSED_9BFF.S */ 9718/* File: armv5te/unused.S */ 9719 bl common_abort 9720 9721 9722/* ------------------------------ */ 9723 .balign 64 9724.L_OP_UNUSED_9CFF: /* 0x19c */ 9725/* File: armv5te/OP_UNUSED_9CFF.S */ 9726/* File: armv5te/unused.S */ 9727 bl common_abort 9728 9729 9730/* ------------------------------ */ 9731 .balign 64 9732.L_OP_UNUSED_9DFF: /* 0x19d */ 9733/* File: armv5te/OP_UNUSED_9DFF.S */ 9734/* File: armv5te/unused.S */ 9735 bl common_abort 9736 9737 9738/* ------------------------------ */ 9739 .balign 64 9740.L_OP_UNUSED_9EFF: /* 0x19e */ 9741/* File: armv5te/OP_UNUSED_9EFF.S */ 9742/* File: armv5te/unused.S */ 9743 bl common_abort 9744 9745 9746/* ------------------------------ */ 9747 .balign 64 9748.L_OP_UNUSED_9FFF: /* 0x19f */ 9749/* File: armv5te/OP_UNUSED_9FFF.S */ 9750/* File: armv5te/unused.S */ 9751 bl common_abort 9752 9753 9754/* ------------------------------ */ 9755 .balign 64 9756.L_OP_UNUSED_A0FF: /* 0x1a0 */ 9757/* File: armv5te/OP_UNUSED_A0FF.S */ 9758/* File: armv5te/unused.S */ 9759 bl common_abort 9760 9761 9762/* ------------------------------ */ 9763 .balign 64 9764.L_OP_UNUSED_A1FF: /* 0x1a1 */ 9765/* File: armv5te/OP_UNUSED_A1FF.S */ 9766/* File: armv5te/unused.S */ 9767 bl common_abort 9768 9769 9770/* ------------------------------ */ 9771 .balign 64 9772.L_OP_UNUSED_A2FF: /* 0x1a2 */ 9773/* File: armv5te/OP_UNUSED_A2FF.S */ 9774/* File: armv5te/unused.S */ 9775 bl common_abort 9776 9777 9778/* ------------------------------ */ 9779 .balign 64 9780.L_OP_UNUSED_A3FF: /* 0x1a3 */ 9781/* File: armv5te/OP_UNUSED_A3FF.S */ 9782/* File: armv5te/unused.S */ 9783 bl common_abort 9784 9785 9786/* ------------------------------ */ 9787 .balign 64 9788.L_OP_UNUSED_A4FF: /* 0x1a4 */ 9789/* File: armv5te/OP_UNUSED_A4FF.S */ 9790/* File: armv5te/unused.S */ 9791 bl common_abort 9792 9793 9794/* ------------------------------ */ 9795 .balign 64 9796.L_OP_UNUSED_A5FF: /* 0x1a5 */ 9797/* File: armv5te/OP_UNUSED_A5FF.S */ 9798/* File: armv5te/unused.S */ 9799 bl common_abort 9800 9801 9802/* ------------------------------ */ 9803 .balign 64 9804.L_OP_UNUSED_A6FF: /* 0x1a6 */ 9805/* File: armv5te/OP_UNUSED_A6FF.S */ 9806/* File: armv5te/unused.S */ 9807 bl common_abort 9808 9809 9810/* ------------------------------ */ 9811 .balign 64 9812.L_OP_UNUSED_A7FF: /* 0x1a7 */ 9813/* File: armv5te/OP_UNUSED_A7FF.S */ 9814/* File: armv5te/unused.S */ 9815 bl common_abort 9816 9817 9818/* ------------------------------ */ 9819 .balign 64 9820.L_OP_UNUSED_A8FF: /* 0x1a8 */ 9821/* File: armv5te/OP_UNUSED_A8FF.S */ 9822/* File: armv5te/unused.S */ 9823 bl common_abort 9824 9825 9826/* ------------------------------ */ 9827 .balign 64 9828.L_OP_UNUSED_A9FF: /* 0x1a9 */ 9829/* File: armv5te/OP_UNUSED_A9FF.S */ 9830/* File: armv5te/unused.S */ 9831 bl common_abort 9832 9833 9834/* ------------------------------ */ 9835 .balign 64 9836.L_OP_UNUSED_AAFF: /* 0x1aa */ 9837/* File: armv5te/OP_UNUSED_AAFF.S */ 9838/* File: armv5te/unused.S */ 9839 bl common_abort 9840 9841 9842/* ------------------------------ */ 9843 .balign 64 9844.L_OP_UNUSED_ABFF: /* 0x1ab */ 9845/* File: armv5te/OP_UNUSED_ABFF.S */ 9846/* File: armv5te/unused.S */ 9847 bl common_abort 9848 9849 9850/* ------------------------------ */ 9851 .balign 64 9852.L_OP_UNUSED_ACFF: /* 0x1ac */ 9853/* File: armv5te/OP_UNUSED_ACFF.S */ 9854/* File: armv5te/unused.S */ 9855 bl common_abort 9856 9857 9858/* ------------------------------ */ 9859 .balign 64 9860.L_OP_UNUSED_ADFF: /* 0x1ad */ 9861/* File: armv5te/OP_UNUSED_ADFF.S */ 9862/* File: armv5te/unused.S */ 9863 bl common_abort 9864 9865 9866/* ------------------------------ */ 9867 .balign 64 9868.L_OP_UNUSED_AEFF: /* 0x1ae */ 9869/* File: armv5te/OP_UNUSED_AEFF.S */ 9870/* File: armv5te/unused.S */ 9871 bl common_abort 9872 9873 9874/* ------------------------------ */ 9875 .balign 64 9876.L_OP_UNUSED_AFFF: /* 0x1af */ 9877/* File: armv5te/OP_UNUSED_AFFF.S */ 9878/* File: armv5te/unused.S */ 9879 bl common_abort 9880 9881 9882/* ------------------------------ */ 9883 .balign 64 9884.L_OP_UNUSED_B0FF: /* 0x1b0 */ 9885/* File: armv5te/OP_UNUSED_B0FF.S */ 9886/* File: armv5te/unused.S */ 9887 bl common_abort 9888 9889 9890/* ------------------------------ */ 9891 .balign 64 9892.L_OP_UNUSED_B1FF: /* 0x1b1 */ 9893/* File: armv5te/OP_UNUSED_B1FF.S */ 9894/* File: armv5te/unused.S */ 9895 bl common_abort 9896 9897 9898/* ------------------------------ */ 9899 .balign 64 9900.L_OP_UNUSED_B2FF: /* 0x1b2 */ 9901/* File: armv5te/OP_UNUSED_B2FF.S */ 9902/* File: armv5te/unused.S */ 9903 bl common_abort 9904 9905 9906/* ------------------------------ */ 9907 .balign 64 9908.L_OP_UNUSED_B3FF: /* 0x1b3 */ 9909/* File: armv5te/OP_UNUSED_B3FF.S */ 9910/* File: armv5te/unused.S */ 9911 bl common_abort 9912 9913 9914/* ------------------------------ */ 9915 .balign 64 9916.L_OP_UNUSED_B4FF: /* 0x1b4 */ 9917/* File: armv5te/OP_UNUSED_B4FF.S */ 9918/* File: armv5te/unused.S */ 9919 bl common_abort 9920 9921 9922/* ------------------------------ */ 9923 .balign 64 9924.L_OP_UNUSED_B5FF: /* 0x1b5 */ 9925/* File: armv5te/OP_UNUSED_B5FF.S */ 9926/* File: armv5te/unused.S */ 9927 bl common_abort 9928 9929 9930/* ------------------------------ */ 9931 .balign 64 9932.L_OP_UNUSED_B6FF: /* 0x1b6 */ 9933/* File: armv5te/OP_UNUSED_B6FF.S */ 9934/* File: armv5te/unused.S */ 9935 bl common_abort 9936 9937 9938/* ------------------------------ */ 9939 .balign 64 9940.L_OP_UNUSED_B7FF: /* 0x1b7 */ 9941/* File: armv5te/OP_UNUSED_B7FF.S */ 9942/* File: armv5te/unused.S */ 9943 bl common_abort 9944 9945 9946/* ------------------------------ */ 9947 .balign 64 9948.L_OP_UNUSED_B8FF: /* 0x1b8 */ 9949/* File: armv5te/OP_UNUSED_B8FF.S */ 9950/* File: armv5te/unused.S */ 9951 bl common_abort 9952 9953 9954/* ------------------------------ */ 9955 .balign 64 9956.L_OP_UNUSED_B9FF: /* 0x1b9 */ 9957/* File: armv5te/OP_UNUSED_B9FF.S */ 9958/* File: armv5te/unused.S */ 9959 bl common_abort 9960 9961 9962/* ------------------------------ */ 9963 .balign 64 9964.L_OP_UNUSED_BAFF: /* 0x1ba */ 9965/* File: armv5te/OP_UNUSED_BAFF.S */ 9966/* File: armv5te/unused.S */ 9967 bl common_abort 9968 9969 9970/* ------------------------------ */ 9971 .balign 64 9972.L_OP_UNUSED_BBFF: /* 0x1bb */ 9973/* File: armv5te/OP_UNUSED_BBFF.S */ 9974/* File: armv5te/unused.S */ 9975 bl common_abort 9976 9977 9978/* ------------------------------ */ 9979 .balign 64 9980.L_OP_UNUSED_BCFF: /* 0x1bc */ 9981/* File: armv5te/OP_UNUSED_BCFF.S */ 9982/* File: armv5te/unused.S */ 9983 bl common_abort 9984 9985 9986/* ------------------------------ */ 9987 .balign 64 9988.L_OP_UNUSED_BDFF: /* 0x1bd */ 9989/* File: armv5te/OP_UNUSED_BDFF.S */ 9990/* File: armv5te/unused.S */ 9991 bl common_abort 9992 9993 9994/* ------------------------------ */ 9995 .balign 64 9996.L_OP_UNUSED_BEFF: /* 0x1be */ 9997/* File: armv5te/OP_UNUSED_BEFF.S */ 9998/* File: armv5te/unused.S */ 9999 bl common_abort 10000 10001 10002/* ------------------------------ */ 10003 .balign 64 10004.L_OP_UNUSED_BFFF: /* 0x1bf */ 10005/* File: armv5te/OP_UNUSED_BFFF.S */ 10006/* File: armv5te/unused.S */ 10007 bl common_abort 10008 10009 10010/* ------------------------------ */ 10011 .balign 64 10012.L_OP_UNUSED_C0FF: /* 0x1c0 */ 10013/* File: armv5te/OP_UNUSED_C0FF.S */ 10014/* File: armv5te/unused.S */ 10015 bl common_abort 10016 10017 10018/* ------------------------------ */ 10019 .balign 64 10020.L_OP_UNUSED_C1FF: /* 0x1c1 */ 10021/* File: armv5te/OP_UNUSED_C1FF.S */ 10022/* File: armv5te/unused.S */ 10023 bl common_abort 10024 10025 10026/* ------------------------------ */ 10027 .balign 64 10028.L_OP_UNUSED_C2FF: /* 0x1c2 */ 10029/* File: armv5te/OP_UNUSED_C2FF.S */ 10030/* File: armv5te/unused.S */ 10031 bl common_abort 10032 10033 10034/* ------------------------------ */ 10035 .balign 64 10036.L_OP_UNUSED_C3FF: /* 0x1c3 */ 10037/* File: armv5te/OP_UNUSED_C3FF.S */ 10038/* File: armv5te/unused.S */ 10039 bl common_abort 10040 10041 10042/* ------------------------------ */ 10043 .balign 64 10044.L_OP_UNUSED_C4FF: /* 0x1c4 */ 10045/* File: armv5te/OP_UNUSED_C4FF.S */ 10046/* File: armv5te/unused.S */ 10047 bl common_abort 10048 10049 10050/* ------------------------------ */ 10051 .balign 64 10052.L_OP_UNUSED_C5FF: /* 0x1c5 */ 10053/* File: armv5te/OP_UNUSED_C5FF.S */ 10054/* File: armv5te/unused.S */ 10055 bl common_abort 10056 10057 10058/* ------------------------------ */ 10059 .balign 64 10060.L_OP_UNUSED_C6FF: /* 0x1c6 */ 10061/* File: armv5te/OP_UNUSED_C6FF.S */ 10062/* File: armv5te/unused.S */ 10063 bl common_abort 10064 10065 10066/* ------------------------------ */ 10067 .balign 64 10068.L_OP_UNUSED_C7FF: /* 0x1c7 */ 10069/* File: armv5te/OP_UNUSED_C7FF.S */ 10070/* File: armv5te/unused.S */ 10071 bl common_abort 10072 10073 10074/* ------------------------------ */ 10075 .balign 64 10076.L_OP_UNUSED_C8FF: /* 0x1c8 */ 10077/* File: armv5te/OP_UNUSED_C8FF.S */ 10078/* File: armv5te/unused.S */ 10079 bl common_abort 10080 10081 10082/* ------------------------------ */ 10083 .balign 64 10084.L_OP_UNUSED_C9FF: /* 0x1c9 */ 10085/* File: armv5te/OP_UNUSED_C9FF.S */ 10086/* File: armv5te/unused.S */ 10087 bl common_abort 10088 10089 10090/* ------------------------------ */ 10091 .balign 64 10092.L_OP_UNUSED_CAFF: /* 0x1ca */ 10093/* File: armv5te/OP_UNUSED_CAFF.S */ 10094/* File: armv5te/unused.S */ 10095 bl common_abort 10096 10097 10098/* ------------------------------ */ 10099 .balign 64 10100.L_OP_UNUSED_CBFF: /* 0x1cb */ 10101/* File: armv5te/OP_UNUSED_CBFF.S */ 10102/* File: armv5te/unused.S */ 10103 bl common_abort 10104 10105 10106/* ------------------------------ */ 10107 .balign 64 10108.L_OP_UNUSED_CCFF: /* 0x1cc */ 10109/* File: armv5te/OP_UNUSED_CCFF.S */ 10110/* File: armv5te/unused.S */ 10111 bl common_abort 10112 10113 10114/* ------------------------------ */ 10115 .balign 64 10116.L_OP_UNUSED_CDFF: /* 0x1cd */ 10117/* File: armv5te/OP_UNUSED_CDFF.S */ 10118/* File: armv5te/unused.S */ 10119 bl common_abort 10120 10121 10122/* ------------------------------ */ 10123 .balign 64 10124.L_OP_UNUSED_CEFF: /* 0x1ce */ 10125/* File: armv5te/OP_UNUSED_CEFF.S */ 10126/* File: armv5te/unused.S */ 10127 bl common_abort 10128 10129 10130/* ------------------------------ */ 10131 .balign 64 10132.L_OP_UNUSED_CFFF: /* 0x1cf */ 10133/* File: armv5te/OP_UNUSED_CFFF.S */ 10134/* File: armv5te/unused.S */ 10135 bl common_abort 10136 10137 10138/* ------------------------------ */ 10139 .balign 64 10140.L_OP_UNUSED_D0FF: /* 0x1d0 */ 10141/* File: armv5te/OP_UNUSED_D0FF.S */ 10142/* File: armv5te/unused.S */ 10143 bl common_abort 10144 10145 10146/* ------------------------------ */ 10147 .balign 64 10148.L_OP_UNUSED_D1FF: /* 0x1d1 */ 10149/* File: armv5te/OP_UNUSED_D1FF.S */ 10150/* File: armv5te/unused.S */ 10151 bl common_abort 10152 10153 10154/* ------------------------------ */ 10155 .balign 64 10156.L_OP_UNUSED_D2FF: /* 0x1d2 */ 10157/* File: armv5te/OP_UNUSED_D2FF.S */ 10158/* File: armv5te/unused.S */ 10159 bl common_abort 10160 10161 10162/* ------------------------------ */ 10163 .balign 64 10164.L_OP_UNUSED_D3FF: /* 0x1d3 */ 10165/* File: armv5te/OP_UNUSED_D3FF.S */ 10166/* File: armv5te/unused.S */ 10167 bl common_abort 10168 10169 10170/* ------------------------------ */ 10171 .balign 64 10172.L_OP_UNUSED_D4FF: /* 0x1d4 */ 10173/* File: armv5te/OP_UNUSED_D4FF.S */ 10174/* File: armv5te/unused.S */ 10175 bl common_abort 10176 10177 10178/* ------------------------------ */ 10179 .balign 64 10180.L_OP_UNUSED_D5FF: /* 0x1d5 */ 10181/* File: armv5te/OP_UNUSED_D5FF.S */ 10182/* File: armv5te/unused.S */ 10183 bl common_abort 10184 10185 10186/* ------------------------------ */ 10187 .balign 64 10188.L_OP_UNUSED_D6FF: /* 0x1d6 */ 10189/* File: armv5te/OP_UNUSED_D6FF.S */ 10190/* File: armv5te/unused.S */ 10191 bl common_abort 10192 10193 10194/* ------------------------------ */ 10195 .balign 64 10196.L_OP_UNUSED_D7FF: /* 0x1d7 */ 10197/* File: armv5te/OP_UNUSED_D7FF.S */ 10198/* File: armv5te/unused.S */ 10199 bl common_abort 10200 10201 10202/* ------------------------------ */ 10203 .balign 64 10204.L_OP_UNUSED_D8FF: /* 0x1d8 */ 10205/* File: armv5te/OP_UNUSED_D8FF.S */ 10206/* File: armv5te/unused.S */ 10207 bl common_abort 10208 10209 10210/* ------------------------------ */ 10211 .balign 64 10212.L_OP_UNUSED_D9FF: /* 0x1d9 */ 10213/* File: armv5te/OP_UNUSED_D9FF.S */ 10214/* File: armv5te/unused.S */ 10215 bl common_abort 10216 10217 10218/* ------------------------------ */ 10219 .balign 64 10220.L_OP_UNUSED_DAFF: /* 0x1da */ 10221/* File: armv5te/OP_UNUSED_DAFF.S */ 10222/* File: armv5te/unused.S */ 10223 bl common_abort 10224 10225 10226/* ------------------------------ */ 10227 .balign 64 10228.L_OP_UNUSED_DBFF: /* 0x1db */ 10229/* File: armv5te/OP_UNUSED_DBFF.S */ 10230/* File: armv5te/unused.S */ 10231 bl common_abort 10232 10233 10234/* ------------------------------ */ 10235 .balign 64 10236.L_OP_UNUSED_DCFF: /* 0x1dc */ 10237/* File: armv5te/OP_UNUSED_DCFF.S */ 10238/* File: armv5te/unused.S */ 10239 bl common_abort 10240 10241 10242/* ------------------------------ */ 10243 .balign 64 10244.L_OP_UNUSED_DDFF: /* 0x1dd */ 10245/* File: armv5te/OP_UNUSED_DDFF.S */ 10246/* File: armv5te/unused.S */ 10247 bl common_abort 10248 10249 10250/* ------------------------------ */ 10251 .balign 64 10252.L_OP_UNUSED_DEFF: /* 0x1de */ 10253/* File: armv5te/OP_UNUSED_DEFF.S */ 10254/* File: armv5te/unused.S */ 10255 bl common_abort 10256 10257 10258/* ------------------------------ */ 10259 .balign 64 10260.L_OP_UNUSED_DFFF: /* 0x1df */ 10261/* File: armv5te/OP_UNUSED_DFFF.S */ 10262/* File: armv5te/unused.S */ 10263 bl common_abort 10264 10265 10266/* ------------------------------ */ 10267 .balign 64 10268.L_OP_UNUSED_E0FF: /* 0x1e0 */ 10269/* File: armv5te/OP_UNUSED_E0FF.S */ 10270/* File: armv5te/unused.S */ 10271 bl common_abort 10272 10273 10274/* ------------------------------ */ 10275 .balign 64 10276.L_OP_UNUSED_E1FF: /* 0x1e1 */ 10277/* File: armv5te/OP_UNUSED_E1FF.S */ 10278/* File: armv5te/unused.S */ 10279 bl common_abort 10280 10281 10282/* ------------------------------ */ 10283 .balign 64 10284.L_OP_UNUSED_E2FF: /* 0x1e2 */ 10285/* File: armv5te/OP_UNUSED_E2FF.S */ 10286/* File: armv5te/unused.S */ 10287 bl common_abort 10288 10289 10290/* ------------------------------ */ 10291 .balign 64 10292.L_OP_UNUSED_E3FF: /* 0x1e3 */ 10293/* File: armv5te/OP_UNUSED_E3FF.S */ 10294/* File: armv5te/unused.S */ 10295 bl common_abort 10296 10297 10298/* ------------------------------ */ 10299 .balign 64 10300.L_OP_UNUSED_E4FF: /* 0x1e4 */ 10301/* File: armv5te/OP_UNUSED_E4FF.S */ 10302/* File: armv5te/unused.S */ 10303 bl common_abort 10304 10305 10306/* ------------------------------ */ 10307 .balign 64 10308.L_OP_UNUSED_E5FF: /* 0x1e5 */ 10309/* File: armv5te/OP_UNUSED_E5FF.S */ 10310/* File: armv5te/unused.S */ 10311 bl common_abort 10312 10313 10314/* ------------------------------ */ 10315 .balign 64 10316.L_OP_UNUSED_E6FF: /* 0x1e6 */ 10317/* File: armv5te/OP_UNUSED_E6FF.S */ 10318/* File: armv5te/unused.S */ 10319 bl common_abort 10320 10321 10322/* ------------------------------ */ 10323 .balign 64 10324.L_OP_UNUSED_E7FF: /* 0x1e7 */ 10325/* File: armv5te/OP_UNUSED_E7FF.S */ 10326/* File: armv5te/unused.S */ 10327 bl common_abort 10328 10329 10330/* ------------------------------ */ 10331 .balign 64 10332.L_OP_UNUSED_E8FF: /* 0x1e8 */ 10333/* File: armv5te/OP_UNUSED_E8FF.S */ 10334/* File: armv5te/unused.S */ 10335 bl common_abort 10336 10337 10338/* ------------------------------ */ 10339 .balign 64 10340.L_OP_UNUSED_E9FF: /* 0x1e9 */ 10341/* File: armv5te/OP_UNUSED_E9FF.S */ 10342/* File: armv5te/unused.S */ 10343 bl common_abort 10344 10345 10346/* ------------------------------ */ 10347 .balign 64 10348.L_OP_UNUSED_EAFF: /* 0x1ea */ 10349/* File: armv5te/OP_UNUSED_EAFF.S */ 10350/* File: armv5te/unused.S */ 10351 bl common_abort 10352 10353 10354/* ------------------------------ */ 10355 .balign 64 10356.L_OP_UNUSED_EBFF: /* 0x1eb */ 10357/* File: armv5te/OP_UNUSED_EBFF.S */ 10358/* File: armv5te/unused.S */ 10359 bl common_abort 10360 10361 10362/* ------------------------------ */ 10363 .balign 64 10364.L_OP_UNUSED_ECFF: /* 0x1ec */ 10365/* File: armv5te/OP_UNUSED_ECFF.S */ 10366/* File: armv5te/unused.S */ 10367 bl common_abort 10368 10369 10370/* ------------------------------ */ 10371 .balign 64 10372.L_OP_UNUSED_EDFF: /* 0x1ed */ 10373/* File: armv5te/OP_UNUSED_EDFF.S */ 10374/* File: armv5te/unused.S */ 10375 bl common_abort 10376 10377 10378/* ------------------------------ */ 10379 .balign 64 10380.L_OP_UNUSED_EEFF: /* 0x1ee */ 10381/* File: armv5te/OP_UNUSED_EEFF.S */ 10382/* File: armv5te/unused.S */ 10383 bl common_abort 10384 10385 10386/* ------------------------------ */ 10387 .balign 64 10388.L_OP_UNUSED_EFFF: /* 0x1ef */ 10389/* File: armv5te/OP_UNUSED_EFFF.S */ 10390/* File: armv5te/unused.S */ 10391 bl common_abort 10392 10393 10394/* ------------------------------ */ 10395 .balign 64 10396.L_OP_UNUSED_F0FF: /* 0x1f0 */ 10397/* File: armv5te/OP_UNUSED_F0FF.S */ 10398/* File: armv5te/unused.S */ 10399 bl common_abort 10400 10401 10402/* ------------------------------ */ 10403 .balign 64 10404.L_OP_UNUSED_F1FF: /* 0x1f1 */ 10405/* File: armv5te/OP_UNUSED_F1FF.S */ 10406/* File: armv5te/unused.S */ 10407 bl common_abort 10408 10409 10410/* ------------------------------ */ 10411 .balign 64 10412.L_OP_UNUSED_F2FF: /* 0x1f2 */ 10413/* File: armv5te/OP_UNUSED_F2FF.S */ 10414/* File: armv5te/unused.S */ 10415 bl common_abort 10416 10417 10418/* ------------------------------ */ 10419 .balign 64 10420.L_OP_UNUSED_F3FF: /* 0x1f3 */ 10421/* File: armv5te/OP_UNUSED_F3FF.S */ 10422/* File: armv5te/unused.S */ 10423 bl common_abort 10424 10425 10426/* ------------------------------ */ 10427 .balign 64 10428.L_OP_UNUSED_F4FF: /* 0x1f4 */ 10429/* File: armv5te/OP_UNUSED_F4FF.S */ 10430/* File: armv5te/unused.S */ 10431 bl common_abort 10432 10433 10434/* ------------------------------ */ 10435 .balign 64 10436.L_OP_UNUSED_F5FF: /* 0x1f5 */ 10437/* File: armv5te/OP_UNUSED_F5FF.S */ 10438/* File: armv5te/unused.S */ 10439 bl common_abort 10440 10441 10442/* ------------------------------ */ 10443 .balign 64 10444.L_OP_UNUSED_F6FF: /* 0x1f6 */ 10445/* File: armv5te/OP_UNUSED_F6FF.S */ 10446/* File: armv5te/unused.S */ 10447 bl common_abort 10448 10449 10450/* ------------------------------ */ 10451 .balign 64 10452.L_OP_UNUSED_F7FF: /* 0x1f7 */ 10453/* File: armv5te/OP_UNUSED_F7FF.S */ 10454/* File: armv5te/unused.S */ 10455 bl common_abort 10456 10457 10458/* ------------------------------ */ 10459 .balign 64 10460.L_OP_UNUSED_F8FF: /* 0x1f8 */ 10461/* File: armv5te/OP_UNUSED_F8FF.S */ 10462/* File: armv5te/unused.S */ 10463 bl common_abort 10464 10465 10466/* ------------------------------ */ 10467 .balign 64 10468.L_OP_UNUSED_F9FF: /* 0x1f9 */ 10469/* File: armv5te/OP_UNUSED_F9FF.S */ 10470/* File: armv5te/unused.S */ 10471 bl common_abort 10472 10473 10474/* ------------------------------ */ 10475 .balign 64 10476.L_OP_UNUSED_FAFF: /* 0x1fa */ 10477/* File: armv5te/OP_UNUSED_FAFF.S */ 10478/* File: armv5te/unused.S */ 10479 bl common_abort 10480 10481 10482/* ------------------------------ */ 10483 .balign 64 10484.L_OP_UNUSED_FBFF: /* 0x1fb */ 10485/* File: armv5te/OP_UNUSED_FBFF.S */ 10486/* File: armv5te/unused.S */ 10487 bl common_abort 10488 10489 10490/* ------------------------------ */ 10491 .balign 64 10492.L_OP_UNUSED_FCFF: /* 0x1fc */ 10493/* File: armv5te/OP_UNUSED_FCFF.S */ 10494/* File: armv5te/unused.S */ 10495 bl common_abort 10496 10497 10498/* ------------------------------ */ 10499 .balign 64 10500.L_OP_UNUSED_FDFF: /* 0x1fd */ 10501/* File: armv5te/OP_UNUSED_FDFF.S */ 10502/* File: armv5te/unused.S */ 10503 bl common_abort 10504 10505 10506/* ------------------------------ */ 10507 .balign 64 10508.L_OP_UNUSED_FEFF: /* 0x1fe */ 10509/* File: armv5te/OP_UNUSED_FEFF.S */ 10510/* File: armv5te/unused.S */ 10511 bl common_abort 10512 10513 10514/* ------------------------------ */ 10515 .balign 64 10516.L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 10517/* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */ 10518 /* 10519 * Handle a jumbo throw-verification-error instruction. This throws an 10520 * exception for an error discovered during verification. The 10521 * exception is indicated by BBBB, with some detail provided by AAAAAAAA. 10522 */ 10523 /* exop BBBB, Class@AAAAAAAA */ 10524 FETCH(r1, 1) @ r1<- aaaa (lo) 10525 FETCH(r2, 2) @ r2<- AAAA (hi) 10526 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10527 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa 10528 EXPORT_PC() @ export the PC 10529 FETCH(r1, 3) @ r1<- BBBB 10530 bl dvmThrowVerificationError @ always throws 10531 b common_exceptionThrown @ handle exception 10532 10533 .balign 64 10534 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 10535 .global dvmAsmInstructionEnd 10536dvmAsmInstructionEnd: 10537 10538/* 10539 * =========================================================================== 10540 * Sister implementations 10541 * =========================================================================== 10542 */ 10543 .global dvmAsmSisterStart 10544 .type dvmAsmSisterStart, %function 10545 .text 10546 .balign 4 10547dvmAsmSisterStart: 10548 10549/* continuation for OP_CONST_STRING */ 10550 10551 /* 10552 * Continuation if the String has not yet been resolved. 10553 * r1: BBBB (String ref) 10554 * r9: target register 10555 */ 10556.LOP_CONST_STRING_resolve: 10557 EXPORT_PC() 10558 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10559 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10560 bl dvmResolveString @ r0<- String reference 10561 cmp r0, #0 @ failed? 10562 beq common_exceptionThrown @ yup, handle the exception 10563 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10564 GET_INST_OPCODE(ip) @ extract opcode from rINST 10565 SET_VREG(r0, r9) @ vAA<- r0 10566 GOTO_OPCODE(ip) @ jump to next instruction 10567 10568/* continuation for OP_CONST_STRING_JUMBO */ 10569 10570 /* 10571 * Continuation if the String has not yet been resolved. 10572 * r1: BBBBBBBB (String ref) 10573 * r9: target register 10574 */ 10575.LOP_CONST_STRING_JUMBO_resolve: 10576 EXPORT_PC() 10577 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10578 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10579 bl dvmResolveString @ r0<- String reference 10580 cmp r0, #0 @ failed? 10581 beq common_exceptionThrown @ yup, handle the exception 10582 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10583 GET_INST_OPCODE(ip) @ extract opcode from rINST 10584 SET_VREG(r0, r9) @ vAA<- r0 10585 GOTO_OPCODE(ip) @ jump to next instruction 10586 10587/* continuation for OP_CONST_CLASS */ 10588 10589 /* 10590 * Continuation if the Class has not yet been resolved. 10591 * r1: BBBB (Class ref) 10592 * r9: target register 10593 */ 10594.LOP_CONST_CLASS_resolve: 10595 EXPORT_PC() 10596 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10597 mov r2, #1 @ r2<- true 10598 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10599 bl dvmResolveClass @ r0<- Class reference 10600 cmp r0, #0 @ failed? 10601 beq common_exceptionThrown @ yup, handle the exception 10602 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10603 GET_INST_OPCODE(ip) @ extract opcode from rINST 10604 SET_VREG(r0, r9) @ vAA<- r0 10605 GOTO_OPCODE(ip) @ jump to next instruction 10606 10607/* continuation for OP_CHECK_CAST */ 10608 10609 /* 10610 * Trivial test failed, need to perform full check. This is common. 10611 * r0 holds obj->clazz 10612 * r1 holds desired class resolved from BBBB 10613 * r9 holds object 10614 */ 10615.LOP_CHECK_CAST_fullcheck: 10616 mov r10, r1 @ avoid ClassObject getting clobbered 10617 bl dvmInstanceofNonTrivial @ r0<- boolean result 10618 cmp r0, #0 @ failed? 10619 bne .LOP_CHECK_CAST_okay @ no, success 10620 10621 @ A cast has failed. We need to throw a ClassCastException. 10622 EXPORT_PC() @ about to throw 10623 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 10624 mov r1, r10 @ r1<- desired class 10625 bl dvmThrowClassCastException 10626 b common_exceptionThrown 10627 10628 /* 10629 * Resolution required. This is the least-likely path. 10630 * 10631 * r2 holds BBBB 10632 * r9 holds object 10633 */ 10634.LOP_CHECK_CAST_resolve: 10635 EXPORT_PC() @ resolve() could throw 10636 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10637 mov r1, r2 @ r1<- BBBB 10638 mov r2, #0 @ r2<- false 10639 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10640 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10641 cmp r0, #0 @ got null? 10642 beq common_exceptionThrown @ yes, handle exception 10643 mov r1, r0 @ r1<- class resolved from BBB 10644 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 10645 b .LOP_CHECK_CAST_resolved @ pick up where we left off 10646 10647/* continuation for OP_INSTANCE_OF */ 10648 10649 /* 10650 * Trivial test failed, need to perform full check. This is common. 10651 * r0 holds obj->clazz 10652 * r1 holds class resolved from BBBB 10653 * r9 holds A 10654 */ 10655.LOP_INSTANCE_OF_fullcheck: 10656 bl dvmInstanceofNonTrivial @ r0<- boolean result 10657 @ fall through to OP_INSTANCE_OF_store 10658 10659 /* 10660 * r0 holds boolean result 10661 * r9 holds A 10662 */ 10663.LOP_INSTANCE_OF_store: 10664 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10665 SET_VREG(r0, r9) @ vA<- r0 10666 GET_INST_OPCODE(ip) @ extract opcode from rINST 10667 GOTO_OPCODE(ip) @ jump to next instruction 10668 10669 /* 10670 * Trivial test succeeded, save and bail. 10671 * r9 holds A 10672 */ 10673.LOP_INSTANCE_OF_trivial: 10674 mov r0, #1 @ indicate success 10675 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 10676 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10677 SET_VREG(r0, r9) @ vA<- r0 10678 GET_INST_OPCODE(ip) @ extract opcode from rINST 10679 GOTO_OPCODE(ip) @ jump to next instruction 10680 10681 /* 10682 * Resolution required. This is the least-likely path. 10683 * 10684 * r3 holds BBBB 10685 * r9 holds A 10686 */ 10687.LOP_INSTANCE_OF_resolve: 10688 EXPORT_PC() @ resolve() could throw 10689 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10690 mov r1, r3 @ r1<- BBBB 10691 mov r2, #1 @ r2<- true 10692 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10693 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10694 cmp r0, #0 @ got null? 10695 beq common_exceptionThrown @ yes, handle exception 10696 mov r1, r0 @ r1<- class resolved from BBB 10697 mov r3, rINST, lsr #12 @ r3<- B 10698 GET_VREG(r0, r3) @ r0<- vB (object) 10699 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 10700 b .LOP_INSTANCE_OF_resolved @ pick up where we left off 10701 10702/* continuation for OP_NEW_INSTANCE */ 10703 10704 .balign 32 @ minimize cache lines 10705.LOP_NEW_INSTANCE_finish: @ r0=new object 10706 mov r3, rINST, lsr #8 @ r3<- AA 10707 cmp r0, #0 @ failed? 10708 beq common_exceptionThrown @ yes, handle the exception 10709 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10710 GET_INST_OPCODE(ip) @ extract opcode from rINST 10711 SET_VREG(r0, r3) @ vAA<- r0 10712 GOTO_OPCODE(ip) @ jump to next instruction 10713 10714 /* 10715 * Class initialization required. 10716 * 10717 * r0 holds class object 10718 */ 10719.LOP_NEW_INSTANCE_needinit: 10720 mov r9, r0 @ save r0 10721 bl dvmInitClass @ initialize class 10722 cmp r0, #0 @ check boolean result 10723 mov r0, r9 @ restore r0 10724 bne .LOP_NEW_INSTANCE_initialized @ success, continue 10725 b common_exceptionThrown @ failed, deal with init exception 10726 10727 /* 10728 * Resolution required. This is the least-likely path. 10729 * 10730 * r1 holds BBBB 10731 */ 10732.LOP_NEW_INSTANCE_resolve: 10733 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10734 mov r2, #0 @ r2<- false 10735 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10736 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10737 cmp r0, #0 @ got null? 10738 bne .LOP_NEW_INSTANCE_resolved @ no, continue 10739 b common_exceptionThrown @ yes, handle exception 10740 10741/* continuation for OP_NEW_ARRAY */ 10742 10743 10744 /* 10745 * Resolve class. (This is an uncommon case.) 10746 * 10747 * r1 holds array length 10748 * r2 holds class ref CCCC 10749 */ 10750.LOP_NEW_ARRAY_resolve: 10751 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10752 mov r9, r1 @ r9<- length (save) 10753 mov r1, r2 @ r1<- CCCC 10754 mov r2, #0 @ r2<- false 10755 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10756 bl dvmResolveClass @ r0<- call(clazz, ref) 10757 cmp r0, #0 @ got null? 10758 mov r1, r9 @ r1<- length (restore) 10759 beq common_exceptionThrown @ yes, handle exception 10760 @ fall through to OP_NEW_ARRAY_finish 10761 10762 /* 10763 * Finish allocation. 10764 * 10765 * r0 holds class 10766 * r1 holds array length 10767 */ 10768.LOP_NEW_ARRAY_finish: 10769 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 10770 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 10771 cmp r0, #0 @ failed? 10772 mov r2, rINST, lsr #8 @ r2<- A+ 10773 beq common_exceptionThrown @ yes, handle the exception 10774 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10775 and r2, r2, #15 @ r2<- A 10776 GET_INST_OPCODE(ip) @ extract opcode from rINST 10777 SET_VREG(r0, r2) @ vA<- r0 10778 GOTO_OPCODE(ip) @ jump to next instruction 10779 10780/* continuation for OP_FILLED_NEW_ARRAY */ 10781 10782 /* 10783 * On entry: 10784 * r0 holds array class 10785 * r10 holds AA or BA 10786 */ 10787.LOP_FILLED_NEW_ARRAY_continue: 10788 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 10789 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 10790 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 10791 .if 0 10792 mov r1, r10 @ r1<- AA (length) 10793 .else 10794 mov r1, r10, lsr #4 @ r1<- B (length) 10795 .endif 10796 cmp rINST, #'I' @ array of ints? 10797 cmpne rINST, #'L' @ array of objects? 10798 cmpne rINST, #'[' @ array of arrays? 10799 mov r9, r1 @ save length in r9 10800 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 10801 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 10802 cmp r0, #0 @ null return? 10803 beq common_exceptionThrown @ alloc failed, handle exception 10804 10805 FETCH(r1, 2) @ r1<- FEDC or CCCC 10806 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 10807 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 10808 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 10809 subs r9, r9, #1 @ length--, check for neg 10810 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 10811 bmi 2f @ was zero, bail 10812 10813 @ copy values from registers into the array 10814 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 10815 .if 0 10816 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 108171: ldr r3, [r2], #4 @ r3<- *r2++ 10818 subs r9, r9, #1 @ count-- 10819 str r3, [r0], #4 @ *contents++ = vX 10820 bpl 1b 10821 @ continue at 2 10822 .else 10823 cmp r9, #4 @ length was initially 5? 10824 and r2, r10, #15 @ r2<- A 10825 bne 1f @ <= 4 args, branch 10826 GET_VREG(r3, r2) @ r3<- vA 10827 sub r9, r9, #1 @ count-- 10828 str r3, [r0, #16] @ contents[4] = vA 108291: and r2, r1, #15 @ r2<- F/E/D/C 10830 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 10831 mov r1, r1, lsr #4 @ r1<- next reg in low 4 10832 subs r9, r9, #1 @ count-- 10833 str r3, [r0], #4 @ *contents++ = vX 10834 bpl 1b 10835 @ continue at 2 10836 .endif 10837 108382: 10839 ldr r0, [rSELF, #offThread_retval] @ r0<- object 10840 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 10841 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 10842 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 10843 cmp r1, #'I' @ Is int array? 10844 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 10845 GOTO_OPCODE(ip) @ execute it 10846 10847 /* 10848 * Throw an exception indicating that we have not implemented this 10849 * mode of filled-new-array. 10850 */ 10851.LOP_FILLED_NEW_ARRAY_notimpl: 10852 ldr r0, .L_strFilledNewArrayNotImpl 10853 bl dvmThrowInternalError 10854 b common_exceptionThrown 10855 10856 .if (!0) @ define in one or the other, not both 10857.L_strFilledNewArrayNotImpl: 10858 .word .LstrFilledNewArrayNotImpl 10859 .endif 10860 10861/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 10862 10863 /* 10864 * On entry: 10865 * r0 holds array class 10866 * r10 holds AA or BA 10867 */ 10868.LOP_FILLED_NEW_ARRAY_RANGE_continue: 10869 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 10870 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 10871 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 10872 .if 1 10873 mov r1, r10 @ r1<- AA (length) 10874 .else 10875 mov r1, r10, lsr #4 @ r1<- B (length) 10876 .endif 10877 cmp rINST, #'I' @ array of ints? 10878 cmpne rINST, #'L' @ array of objects? 10879 cmpne rINST, #'[' @ array of arrays? 10880 mov r9, r1 @ save length in r9 10881 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 10882 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 10883 cmp r0, #0 @ null return? 10884 beq common_exceptionThrown @ alloc failed, handle exception 10885 10886 FETCH(r1, 2) @ r1<- FEDC or CCCC 10887 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 10888 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 10889 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 10890 subs r9, r9, #1 @ length--, check for neg 10891 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 10892 bmi 2f @ was zero, bail 10893 10894 @ copy values from registers into the array 10895 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 10896 .if 1 10897 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 108981: ldr r3, [r2], #4 @ r3<- *r2++ 10899 subs r9, r9, #1 @ count-- 10900 str r3, [r0], #4 @ *contents++ = vX 10901 bpl 1b 10902 @ continue at 2 10903 .else 10904 cmp r9, #4 @ length was initially 5? 10905 and r2, r10, #15 @ r2<- A 10906 bne 1f @ <= 4 args, branch 10907 GET_VREG(r3, r2) @ r3<- vA 10908 sub r9, r9, #1 @ count-- 10909 str r3, [r0, #16] @ contents[4] = vA 109101: and r2, r1, #15 @ r2<- F/E/D/C 10911 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 10912 mov r1, r1, lsr #4 @ r1<- next reg in low 4 10913 subs r9, r9, #1 @ count-- 10914 str r3, [r0], #4 @ *contents++ = vX 10915 bpl 1b 10916 @ continue at 2 10917 .endif 10918 109192: 10920 ldr r0, [rSELF, #offThread_retval] @ r0<- object 10921 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 10922 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 10923 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 10924 cmp r1, #'I' @ Is int array? 10925 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 10926 GOTO_OPCODE(ip) @ execute it 10927 10928 /* 10929 * Throw an exception indicating that we have not implemented this 10930 * mode of filled-new-array. 10931 */ 10932.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 10933 ldr r0, .L_strFilledNewArrayNotImpl 10934 bl dvmThrowInternalError 10935 b common_exceptionThrown 10936 10937 .if (!1) @ define in one or the other, not both 10938.L_strFilledNewArrayNotImpl: 10939 .word .LstrFilledNewArrayNotImpl 10940 .endif 10941 10942/* continuation for OP_CMPL_FLOAT */ 10943.LOP_CMPL_FLOAT_finish: 10944 SET_VREG(r0, r9) @ vAA<- r0 10945 GOTO_OPCODE(ip) @ jump to next instruction 10946 10947/* continuation for OP_CMPG_FLOAT */ 10948.LOP_CMPG_FLOAT_finish: 10949 SET_VREG(r0, r9) @ vAA<- r0 10950 GOTO_OPCODE(ip) @ jump to next instruction 10951 10952/* continuation for OP_CMPL_DOUBLE */ 10953.LOP_CMPL_DOUBLE_finish: 10954 SET_VREG(r0, r9) @ vAA<- r0 10955 GOTO_OPCODE(ip) @ jump to next instruction 10956 10957/* continuation for OP_CMPG_DOUBLE */ 10958.LOP_CMPG_DOUBLE_finish: 10959 SET_VREG(r0, r9) @ vAA<- r0 10960 GOTO_OPCODE(ip) @ jump to next instruction 10961 10962/* continuation for OP_CMP_LONG */ 10963 10964.LOP_CMP_LONG_less: 10965 mvn r1, #0 @ r1<- -1 10966 @ Want to cond code the next mov so we can avoid branch, but don't see it; 10967 @ instead, we just replicate the tail end. 10968 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10969 SET_VREG(r1, r9) @ vAA<- r1 10970 GET_INST_OPCODE(ip) @ extract opcode from rINST 10971 GOTO_OPCODE(ip) @ jump to next instruction 10972 10973.LOP_CMP_LONG_greater: 10974 mov r1, #1 @ r1<- 1 10975 @ fall through to _finish 10976 10977.LOP_CMP_LONG_finish: 10978 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10979 SET_VREG(r1, r9) @ vAA<- r1 10980 GET_INST_OPCODE(ip) @ extract opcode from rINST 10981 GOTO_OPCODE(ip) @ jump to next instruction 10982 10983/* continuation for OP_AGET_WIDE */ 10984 10985.LOP_AGET_WIDE_finish: 10986 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10987 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 10988 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 10989 GET_INST_OPCODE(ip) @ extract opcode from rINST 10990 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 10991 GOTO_OPCODE(ip) @ jump to next instruction 10992 10993/* continuation for OP_APUT_WIDE */ 10994 10995.LOP_APUT_WIDE_finish: 10996 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10997 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 10998 GET_INST_OPCODE(ip) @ extract opcode from rINST 10999 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11000 GOTO_OPCODE(ip) @ jump to next instruction 11001 11002/* continuation for OP_APUT_OBJECT */ 11003 /* 11004 * On entry: 11005 * rINST = vBB (arrayObj) 11006 * r9 = vAA (obj) 11007 * r10 = offset into array (vBB + vCC * width) 11008 */ 11009.LOP_APUT_OBJECT_finish: 11010 cmp r9, #0 @ storing null reference? 11011 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 11012 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 11013 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz 11014 bl dvmCanPutArrayElement @ test object type vs. array type 11015 cmp r0, #0 @ okay? 11016 beq .LOP_APUT_OBJECT_throw @ no 11017 mov r1, rINST @ r1<- arrayObj 11018 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11019 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base 11020 add r10, #offArrayObject_contents @ r0<- pointer to slot 11021 GET_INST_OPCODE(ip) @ extract opcode from rINST 11022 str r9, [r10] @ vBB[vCC]<- vAA 11023 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head 11024 GOTO_OPCODE(ip) @ jump to next instruction 11025.LOP_APUT_OBJECT_skip_check: 11026 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11027 GET_INST_OPCODE(ip) @ extract opcode from rINST 11028 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 11029 GOTO_OPCODE(ip) @ jump to next instruction 11030.LOP_APUT_OBJECT_throw: 11031 @ The types don't match. We need to throw an ArrayStoreException. 11032 ldr r0, [r9, #offObject_clazz] 11033 ldr r1, [rINST, #offObject_clazz] 11034 EXPORT_PC() 11035 bl dvmThrowArrayStoreException 11036 b common_exceptionThrown 11037 11038/* continuation for OP_IGET */ 11039 11040 /* 11041 * Currently: 11042 * r0 holds resolved field 11043 * r9 holds object 11044 */ 11045.LOP_IGET_finish: 11046 @bl common_squeak0 11047 cmp r9, #0 @ check object for null 11048 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11049 beq common_errNullObject @ object was null 11050 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11051 ubfx r2, rINST, #8, #4 @ r2<- A 11052 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11053 GET_INST_OPCODE(ip) @ extract opcode from rINST 11054 SET_VREG(r0, r2) @ fp[A]<- r0 11055 GOTO_OPCODE(ip) @ jump to next instruction 11056 11057/* continuation for OP_IGET_WIDE */ 11058 11059 /* 11060 * Currently: 11061 * r0 holds resolved field 11062 * r9 holds object 11063 */ 11064.LOP_IGET_WIDE_finish: 11065 cmp r9, #0 @ check object for null 11066 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11067 beq common_errNullObject @ object was null 11068 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11069 ubfx r2, rINST, #8, #4 @ r2<- A 11070 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11071 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11072 GET_INST_OPCODE(ip) @ extract opcode from rINST 11073 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11074 GOTO_OPCODE(ip) @ jump to next instruction 11075 11076/* continuation for OP_IGET_OBJECT */ 11077 11078 /* 11079 * Currently: 11080 * r0 holds resolved field 11081 * r9 holds object 11082 */ 11083.LOP_IGET_OBJECT_finish: 11084 @bl common_squeak0 11085 cmp r9, #0 @ check object for null 11086 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11087 beq common_errNullObject @ object was null 11088 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11089 @ no-op @ acquiring load 11090 mov r2, rINST, lsr #8 @ r2<- A+ 11091 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11092 and r2, r2, #15 @ r2<- A 11093 GET_INST_OPCODE(ip) @ extract opcode from rINST 11094 SET_VREG(r0, r2) @ fp[A]<- r0 11095 GOTO_OPCODE(ip) @ jump to next instruction 11096 11097/* continuation for OP_IGET_BOOLEAN */ 11098 11099 /* 11100 * Currently: 11101 * r0 holds resolved field 11102 * r9 holds object 11103 */ 11104.LOP_IGET_BOOLEAN_finish: 11105 @bl common_squeak1 11106 cmp r9, #0 @ check object for null 11107 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11108 beq common_errNullObject @ object was null 11109 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11110 @ no-op @ acquiring load 11111 mov r2, rINST, lsr #8 @ r2<- A+ 11112 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11113 and r2, r2, #15 @ r2<- A 11114 GET_INST_OPCODE(ip) @ extract opcode from rINST 11115 SET_VREG(r0, r2) @ fp[A]<- r0 11116 GOTO_OPCODE(ip) @ jump to next instruction 11117 11118/* continuation for OP_IGET_BYTE */ 11119 11120 /* 11121 * Currently: 11122 * r0 holds resolved field 11123 * r9 holds object 11124 */ 11125.LOP_IGET_BYTE_finish: 11126 @bl common_squeak2 11127 cmp r9, #0 @ check object for null 11128 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11129 beq common_errNullObject @ object was null 11130 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11131 @ no-op @ acquiring load 11132 mov r2, rINST, lsr #8 @ r2<- A+ 11133 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11134 and r2, r2, #15 @ r2<- A 11135 GET_INST_OPCODE(ip) @ extract opcode from rINST 11136 SET_VREG(r0, r2) @ fp[A]<- r0 11137 GOTO_OPCODE(ip) @ jump to next instruction 11138 11139/* continuation for OP_IGET_CHAR */ 11140 11141 /* 11142 * Currently: 11143 * r0 holds resolved field 11144 * r9 holds object 11145 */ 11146.LOP_IGET_CHAR_finish: 11147 @bl common_squeak3 11148 cmp r9, #0 @ check object for null 11149 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11150 beq common_errNullObject @ object was null 11151 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11152 @ no-op @ acquiring load 11153 mov r2, rINST, lsr #8 @ r2<- A+ 11154 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11155 and r2, r2, #15 @ r2<- A 11156 GET_INST_OPCODE(ip) @ extract opcode from rINST 11157 SET_VREG(r0, r2) @ fp[A]<- r0 11158 GOTO_OPCODE(ip) @ jump to next instruction 11159 11160/* continuation for OP_IGET_SHORT */ 11161 11162 /* 11163 * Currently: 11164 * r0 holds resolved field 11165 * r9 holds object 11166 */ 11167.LOP_IGET_SHORT_finish: 11168 @bl common_squeak4 11169 cmp r9, #0 @ check object for null 11170 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11171 beq common_errNullObject @ object was null 11172 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11173 @ no-op @ acquiring load 11174 mov r2, rINST, lsr #8 @ r2<- A+ 11175 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11176 and r2, r2, #15 @ r2<- A 11177 GET_INST_OPCODE(ip) @ extract opcode from rINST 11178 SET_VREG(r0, r2) @ fp[A]<- r0 11179 GOTO_OPCODE(ip) @ jump to next instruction 11180 11181/* continuation for OP_IPUT */ 11182 11183 /* 11184 * Currently: 11185 * r0 holds resolved field 11186 * r9 holds object 11187 */ 11188.LOP_IPUT_finish: 11189 @bl common_squeak0 11190 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11191 ubfx r1, rINST, #8, #4 @ r1<- A 11192 cmp r9, #0 @ check object for null 11193 GET_VREG(r0, r1) @ r0<- fp[A] 11194 beq common_errNullObject @ object was null 11195 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11196 GET_INST_OPCODE(ip) @ extract opcode from rINST 11197 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11198 GOTO_OPCODE(ip) @ jump to next instruction 11199 11200/* continuation for OP_IPUT_WIDE */ 11201 11202 /* 11203 * Currently: 11204 * r0 holds resolved field 11205 * r9 holds object 11206 */ 11207.LOP_IPUT_WIDE_finish: 11208 ubfx r2, rINST, #8, #4 @ r2<- A 11209 cmp r9, #0 @ check object for null 11210 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11211 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 11212 beq common_errNullObject @ object was null 11213 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11214 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 11215 GET_INST_OPCODE(ip) @ extract opcode from rINST 11216 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0 11217 GOTO_OPCODE(ip) @ jump to next instruction 11218 11219/* continuation for OP_IPUT_OBJECT */ 11220 11221 /* 11222 * Currently: 11223 * r0 holds resolved field 11224 * r9 holds object 11225 */ 11226.LOP_IPUT_OBJECT_finish: 11227 @bl common_squeak0 11228 mov r1, rINST, lsr #8 @ r1<- A+ 11229 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11230 and r1, r1, #15 @ r1<- A 11231 cmp r9, #0 @ check object for null 11232 GET_VREG(r0, r1) @ r0<- fp[A] 11233 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11234 beq common_errNullObject @ object was null 11235 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11236 GET_INST_OPCODE(ip) @ extract opcode from rINST 11237 @ no-op @ releasing store 11238 str r0, [r9, r3] @ obj.field (32 bits)<- r0 11239 cmp r0, #0 @ stored a null reference? 11240 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 11241 GOTO_OPCODE(ip) @ jump to next instruction 11242 11243/* continuation for OP_IPUT_BOOLEAN */ 11244 11245 /* 11246 * Currently: 11247 * r0 holds resolved field 11248 * r9 holds object 11249 */ 11250.LOP_IPUT_BOOLEAN_finish: 11251 @bl common_squeak1 11252 mov r1, rINST, lsr #8 @ r1<- A+ 11253 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11254 and r1, r1, #15 @ r1<- A 11255 cmp r9, #0 @ check object for null 11256 GET_VREG(r0, r1) @ r0<- fp[A] 11257 beq common_errNullObject @ object was null 11258 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11259 GET_INST_OPCODE(ip) @ extract opcode from rINST 11260 @ no-op @ releasing store 11261 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11262 GOTO_OPCODE(ip) @ jump to next instruction 11263 11264/* continuation for OP_IPUT_BYTE */ 11265 11266 /* 11267 * Currently: 11268 * r0 holds resolved field 11269 * r9 holds object 11270 */ 11271.LOP_IPUT_BYTE_finish: 11272 @bl common_squeak2 11273 mov r1, rINST, lsr #8 @ r1<- A+ 11274 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11275 and r1, r1, #15 @ r1<- A 11276 cmp r9, #0 @ check object for null 11277 GET_VREG(r0, r1) @ r0<- fp[A] 11278 beq common_errNullObject @ object was null 11279 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11280 GET_INST_OPCODE(ip) @ extract opcode from rINST 11281 @ no-op @ releasing store 11282 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11283 GOTO_OPCODE(ip) @ jump to next instruction 11284 11285/* continuation for OP_IPUT_CHAR */ 11286 11287 /* 11288 * Currently: 11289 * r0 holds resolved field 11290 * r9 holds object 11291 */ 11292.LOP_IPUT_CHAR_finish: 11293 @bl common_squeak3 11294 mov r1, rINST, lsr #8 @ r1<- A+ 11295 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11296 and r1, r1, #15 @ r1<- A 11297 cmp r9, #0 @ check object for null 11298 GET_VREG(r0, r1) @ r0<- fp[A] 11299 beq common_errNullObject @ object was null 11300 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11301 GET_INST_OPCODE(ip) @ extract opcode from rINST 11302 @ no-op @ releasing store 11303 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11304 GOTO_OPCODE(ip) @ jump to next instruction 11305 11306/* continuation for OP_IPUT_SHORT */ 11307 11308 /* 11309 * Currently: 11310 * r0 holds resolved field 11311 * r9 holds object 11312 */ 11313.LOP_IPUT_SHORT_finish: 11314 @bl common_squeak4 11315 mov r1, rINST, lsr #8 @ r1<- A+ 11316 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11317 and r1, r1, #15 @ r1<- A 11318 cmp r9, #0 @ check object for null 11319 GET_VREG(r0, r1) @ r0<- fp[A] 11320 beq common_errNullObject @ object was null 11321 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11322 GET_INST_OPCODE(ip) @ extract opcode from rINST 11323 @ no-op @ releasing store 11324 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11325 GOTO_OPCODE(ip) @ jump to next instruction 11326 11327/* continuation for OP_SGET */ 11328 11329 /* 11330 * Continuation if the field has not yet been resolved. 11331 * r1: BBBB field ref 11332 */ 11333.LOP_SGET_resolve: 11334 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11335 EXPORT_PC() @ resolve() could throw, so export now 11336 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11337 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11338 cmp r0, #0 @ success? 11339 bne .LOP_SGET_finish @ yes, finish 11340 b common_exceptionThrown @ no, handle exception 11341 11342/* continuation for OP_SGET_WIDE */ 11343 11344 /* 11345 * Continuation if the field has not yet been resolved. 11346 * r1: BBBB field ref 11347 * 11348 * Returns StaticField pointer in r0. 11349 */ 11350.LOP_SGET_WIDE_resolve: 11351 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11352 EXPORT_PC() @ resolve() could throw, so export now 11353 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11354 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11355 cmp r0, #0 @ success? 11356 bne .LOP_SGET_WIDE_finish @ yes, finish 11357 b common_exceptionThrown @ no, handle exception 11358 11359/* continuation for OP_SGET_OBJECT */ 11360 11361 /* 11362 * Continuation if the field has not yet been resolved. 11363 * r1: BBBB field ref 11364 */ 11365.LOP_SGET_OBJECT_resolve: 11366 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11367 EXPORT_PC() @ resolve() could throw, so export now 11368 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11369 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11370 cmp r0, #0 @ success? 11371 bne .LOP_SGET_OBJECT_finish @ yes, finish 11372 b common_exceptionThrown @ no, handle exception 11373 11374/* continuation for OP_SGET_BOOLEAN */ 11375 11376 /* 11377 * Continuation if the field has not yet been resolved. 11378 * r1: BBBB field ref 11379 */ 11380.LOP_SGET_BOOLEAN_resolve: 11381 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11382 EXPORT_PC() @ resolve() could throw, so export now 11383 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11384 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11385 cmp r0, #0 @ success? 11386 bne .LOP_SGET_BOOLEAN_finish @ yes, finish 11387 b common_exceptionThrown @ no, handle exception 11388 11389/* continuation for OP_SGET_BYTE */ 11390 11391 /* 11392 * Continuation if the field has not yet been resolved. 11393 * r1: BBBB field ref 11394 */ 11395.LOP_SGET_BYTE_resolve: 11396 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11397 EXPORT_PC() @ resolve() could throw, so export now 11398 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11399 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11400 cmp r0, #0 @ success? 11401 bne .LOP_SGET_BYTE_finish @ yes, finish 11402 b common_exceptionThrown @ no, handle exception 11403 11404/* continuation for OP_SGET_CHAR */ 11405 11406 /* 11407 * Continuation if the field has not yet been resolved. 11408 * r1: BBBB field ref 11409 */ 11410.LOP_SGET_CHAR_resolve: 11411 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11412 EXPORT_PC() @ resolve() could throw, so export now 11413 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11414 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11415 cmp r0, #0 @ success? 11416 bne .LOP_SGET_CHAR_finish @ yes, finish 11417 b common_exceptionThrown @ no, handle exception 11418 11419/* continuation for OP_SGET_SHORT */ 11420 11421 /* 11422 * Continuation if the field has not yet been resolved. 11423 * r1: BBBB field ref 11424 */ 11425.LOP_SGET_SHORT_resolve: 11426 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11427 EXPORT_PC() @ resolve() could throw, so export now 11428 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11429 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11430 cmp r0, #0 @ success? 11431 bne .LOP_SGET_SHORT_finish @ yes, finish 11432 b common_exceptionThrown @ no, handle exception 11433 11434/* continuation for OP_SPUT */ 11435 11436 /* 11437 * Continuation if the field has not yet been resolved. 11438 * r1: BBBB field ref 11439 */ 11440.LOP_SPUT_resolve: 11441 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11442 EXPORT_PC() @ resolve() could throw, so export now 11443 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11444 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11445 cmp r0, #0 @ success? 11446 bne .LOP_SPUT_finish @ yes, finish 11447 b common_exceptionThrown @ no, handle exception 11448 11449/* continuation for OP_SPUT_WIDE */ 11450 11451 /* 11452 * Continuation if the field has not yet been resolved. 11453 * r1: BBBB field ref 11454 * r9: &fp[AA] 11455 * 11456 * Returns StaticField pointer in r2. 11457 */ 11458.LOP_SPUT_WIDE_resolve: 11459 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11460 EXPORT_PC() @ resolve() could throw, so export now 11461 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11462 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11463 cmp r0, #0 @ success? 11464 mov r2, r0 @ copy to r2 11465 bne .LOP_SPUT_WIDE_finish @ yes, finish 11466 b common_exceptionThrown @ no, handle exception 11467 11468/* continuation for OP_SPUT_OBJECT */ 11469.LOP_SPUT_OBJECT_finish: @ field ptr in r0 11470 mov r2, rINST, lsr #8 @ r2<- AA 11471 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11472 GET_VREG(r1, r2) @ r1<- fp[AA] 11473 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11474 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 11475 GET_INST_OPCODE(ip) @ extract opcode from rINST 11476 @ no-op @ releasing store 11477 str r1, [r0, #offStaticField_value] @ field<- vAA 11478 cmp r1, #0 @ stored a null object? 11479 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 11480 GOTO_OPCODE(ip) @ jump to next instruction 11481 11482/* continuation for OP_SPUT_BOOLEAN */ 11483 11484 /* 11485 * Continuation if the field has not yet been resolved. 11486 * r1: BBBB field ref 11487 */ 11488.LOP_SPUT_BOOLEAN_resolve: 11489 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11490 EXPORT_PC() @ resolve() could throw, so export now 11491 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11492 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11493 cmp r0, #0 @ success? 11494 bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 11495 b common_exceptionThrown @ no, handle exception 11496 11497/* continuation for OP_SPUT_BYTE */ 11498 11499 /* 11500 * Continuation if the field has not yet been resolved. 11501 * r1: BBBB field ref 11502 */ 11503.LOP_SPUT_BYTE_resolve: 11504 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11505 EXPORT_PC() @ resolve() could throw, so export now 11506 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11507 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11508 cmp r0, #0 @ success? 11509 bne .LOP_SPUT_BYTE_finish @ yes, finish 11510 b common_exceptionThrown @ no, handle exception 11511 11512/* continuation for OP_SPUT_CHAR */ 11513 11514 /* 11515 * Continuation if the field has not yet been resolved. 11516 * r1: BBBB field ref 11517 */ 11518.LOP_SPUT_CHAR_resolve: 11519 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11520 EXPORT_PC() @ resolve() could throw, so export now 11521 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11522 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11523 cmp r0, #0 @ success? 11524 bne .LOP_SPUT_CHAR_finish @ yes, finish 11525 b common_exceptionThrown @ no, handle exception 11526 11527/* continuation for OP_SPUT_SHORT */ 11528 11529 /* 11530 * Continuation if the field has not yet been resolved. 11531 * r1: BBBB field ref 11532 */ 11533.LOP_SPUT_SHORT_resolve: 11534 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11535 EXPORT_PC() @ resolve() could throw, so export now 11536 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11537 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11538 cmp r0, #0 @ success? 11539 bne .LOP_SPUT_SHORT_finish @ yes, finish 11540 b common_exceptionThrown @ no, handle exception 11541 11542/* continuation for OP_INVOKE_VIRTUAL */ 11543 11544 /* 11545 * At this point: 11546 * r0 = resolved base method 11547 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11548 */ 11549.LOP_INVOKE_VIRTUAL_continue: 11550 GET_VREG(r1, r10) @ r1<- "this" ptr 11551 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11552 cmp r1, #0 @ is "this" null? 11553 beq common_errNullObject @ null "this", throw exception 11554 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11555 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11556 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11557 bl common_invokeMethodNoRange @ continue on 11558 11559/* continuation for OP_INVOKE_SUPER */ 11560 11561 /* 11562 * At this point: 11563 * r0 = resolved base method 11564 * r9 = method->clazz 11565 */ 11566.LOP_INVOKE_SUPER_continue: 11567 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11568 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11569 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11570 EXPORT_PC() @ must export for invoke 11571 cmp r2, r3 @ compare (methodIndex, vtableCount) 11572 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 11573 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11574 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11575 bl common_invokeMethodNoRange @ continue on 11576 11577.LOP_INVOKE_SUPER_resolve: 11578 mov r0, r9 @ r0<- method->clazz 11579 mov r2, #METHOD_VIRTUAL @ resolver method type 11580 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11581 cmp r0, #0 @ got null? 11582 bne .LOP_INVOKE_SUPER_continue @ no, continue 11583 b common_exceptionThrown @ yes, handle exception 11584 11585 /* 11586 * Throw a NoSuchMethodError with the method name as the message. 11587 * r0 = resolved base method 11588 */ 11589.LOP_INVOKE_SUPER_nsm: 11590 ldr r1, [r0, #offMethod_name] @ r1<- method name 11591 b common_errNoSuchMethod 11592 11593/* continuation for OP_INVOKE_DIRECT */ 11594 11595 /* 11596 * On entry: 11597 * r1 = reference (BBBB or CCCC) 11598 * r10 = "this" register 11599 */ 11600.LOP_INVOKE_DIRECT_resolve: 11601 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11602 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11603 mov r2, #METHOD_DIRECT @ resolver method type 11604 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11605 cmp r0, #0 @ got null? 11606 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 11607 bne .LOP_INVOKE_DIRECT_finish @ no, continue 11608 b common_exceptionThrown @ yes, handle exception 11609 11610/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 11611 11612 /* 11613 * At this point: 11614 * r0 = resolved base method 11615 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 11616 */ 11617.LOP_INVOKE_VIRTUAL_RANGE_continue: 11618 GET_VREG(r1, r10) @ r1<- "this" ptr 11619 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11620 cmp r1, #0 @ is "this" null? 11621 beq common_errNullObject @ null "this", throw exception 11622 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 11623 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 11624 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 11625 bl common_invokeMethodRange @ continue on 11626 11627/* continuation for OP_INVOKE_SUPER_RANGE */ 11628 11629 /* 11630 * At this point: 11631 * r0 = resolved base method 11632 * r9 = method->clazz 11633 */ 11634.LOP_INVOKE_SUPER_RANGE_continue: 11635 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 11636 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 11637 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 11638 EXPORT_PC() @ must export for invoke 11639 cmp r2, r3 @ compare (methodIndex, vtableCount) 11640 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 11641 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 11642 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 11643 bl common_invokeMethodRange @ continue on 11644 11645.LOP_INVOKE_SUPER_RANGE_resolve: 11646 mov r0, r9 @ r0<- method->clazz 11647 mov r2, #METHOD_VIRTUAL @ resolver method type 11648 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11649 cmp r0, #0 @ got null? 11650 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 11651 b common_exceptionThrown @ yes, handle exception 11652 11653 /* 11654 * Throw a NoSuchMethodError with the method name as the message. 11655 * r0 = resolved base method 11656 */ 11657.LOP_INVOKE_SUPER_RANGE_nsm: 11658 ldr r1, [r0, #offMethod_name] @ r1<- method name 11659 b common_errNoSuchMethod 11660 11661/* continuation for OP_INVOKE_DIRECT_RANGE */ 11662 11663 /* 11664 * On entry: 11665 * r1 = reference (BBBB or CCCC) 11666 * r10 = "this" register 11667 */ 11668.LOP_INVOKE_DIRECT_RANGE_resolve: 11669 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11670 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11671 mov r2, #METHOD_DIRECT @ resolver method type 11672 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 11673 cmp r0, #0 @ got null? 11674 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 11675 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 11676 b common_exceptionThrown @ yes, handle exception 11677 11678/* continuation for OP_FLOAT_TO_LONG */ 11679/* 11680 * Convert the float in r0 to a long in r0/r1. 11681 * 11682 * We have to clip values to long min/max per the specification. The 11683 * expected common case is a "reasonable" value that converts directly 11684 * to modest integer. The EABI convert function isn't doing this for us. 11685 */ 11686f2l_doconv: 11687 stmfd sp!, {r4, lr} 11688 mov r1, #0x5f000000 @ (float)maxlong 11689 mov r4, r0 11690 bl __aeabi_fcmpge @ is arg >= maxlong? 11691 cmp r0, #0 @ nonzero == yes 11692 mvnne r0, #0 @ return maxlong (7fffffff) 11693 mvnne r1, #0x80000000 11694 ldmnefd sp!, {r4, pc} 11695 11696 mov r0, r4 @ recover arg 11697 mov r1, #0xdf000000 @ (float)minlong 11698 bl __aeabi_fcmple @ is arg <= minlong? 11699 cmp r0, #0 @ nonzero == yes 11700 movne r0, #0 @ return minlong (80000000) 11701 movne r1, #0x80000000 11702 ldmnefd sp!, {r4, pc} 11703 11704 mov r0, r4 @ recover arg 11705 mov r1, r4 11706 bl __aeabi_fcmpeq @ is arg == self? 11707 cmp r0, #0 @ zero == no 11708 moveq r1, #0 @ return zero for NaN 11709 ldmeqfd sp!, {r4, pc} 11710 11711 mov r0, r4 @ recover arg 11712 bl __aeabi_f2lz @ convert float to long 11713 ldmfd sp!, {r4, pc} 11714 11715/* continuation for OP_DOUBLE_TO_LONG */ 11716/* 11717 * Convert the double in r0/r1 to a long in r0/r1. 11718 * 11719 * We have to clip values to long min/max per the specification. The 11720 * expected common case is a "reasonable" value that converts directly 11721 * to modest integer. The EABI convert function isn't doing this for us. 11722 */ 11723d2l_doconv: 11724 stmfd sp!, {r4, r5, lr} @ save regs 11725 mov r3, #0x43000000 @ maxlong, as a double (high word) 11726 add r3, #0x00e00000 @ 0x43e00000 11727 mov r2, #0 @ maxlong, as a double (low word) 11728 sub sp, sp, #4 @ align for EABI 11729 mov r4, r0 @ save a copy of r0 11730 mov r5, r1 @ and r1 11731 bl __aeabi_dcmpge @ is arg >= maxlong? 11732 cmp r0, #0 @ nonzero == yes 11733 mvnne r0, #0 @ return maxlong (7fffffffffffffff) 11734 mvnne r1, #0x80000000 11735 bne 1f 11736 11737 mov r0, r4 @ recover arg 11738 mov r1, r5 11739 mov r3, #0xc3000000 @ minlong, as a double (high word) 11740 add r3, #0x00e00000 @ 0xc3e00000 11741 mov r2, #0 @ minlong, as a double (low word) 11742 bl __aeabi_dcmple @ is arg <= minlong? 11743 cmp r0, #0 @ nonzero == yes 11744 movne r0, #0 @ return minlong (8000000000000000) 11745 movne r1, #0x80000000 11746 bne 1f 11747 11748 mov r0, r4 @ recover arg 11749 mov r1, r5 11750 mov r2, r4 @ compare against self 11751 mov r3, r5 11752 bl __aeabi_dcmpeq @ is arg == self? 11753 cmp r0, #0 @ zero == no 11754 moveq r1, #0 @ return zero for NaN 11755 beq 1f 11756 11757 mov r0, r4 @ recover arg 11758 mov r1, r5 11759 bl __aeabi_d2lz @ convert double to long 11760 117611: 11762 add sp, sp, #4 11763 ldmfd sp!, {r4, r5, pc} 11764 11765/* continuation for OP_MUL_LONG */ 11766 11767.LOP_MUL_LONG_finish: 11768 GET_INST_OPCODE(ip) @ extract opcode from rINST 11769 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 11770 GOTO_OPCODE(ip) @ jump to next instruction 11771 11772/* continuation for OP_SHL_LONG */ 11773 11774.LOP_SHL_LONG_finish: 11775 mov r0, r0, asl r2 @ r0<- r0 << r2 11776 GET_INST_OPCODE(ip) @ extract opcode from rINST 11777 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11778 GOTO_OPCODE(ip) @ jump to next instruction 11779 11780/* continuation for OP_SHR_LONG */ 11781 11782.LOP_SHR_LONG_finish: 11783 mov r1, r1, asr r2 @ r1<- r1 >> r2 11784 GET_INST_OPCODE(ip) @ extract opcode from rINST 11785 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11786 GOTO_OPCODE(ip) @ jump to next instruction 11787 11788/* continuation for OP_USHR_LONG */ 11789 11790.LOP_USHR_LONG_finish: 11791 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 11792 GET_INST_OPCODE(ip) @ extract opcode from rINST 11793 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11794 GOTO_OPCODE(ip) @ jump to next instruction 11795 11796/* continuation for OP_SHL_LONG_2ADDR */ 11797 11798.LOP_SHL_LONG_2ADDR_finish: 11799 GET_INST_OPCODE(ip) @ extract opcode from rINST 11800 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11801 GOTO_OPCODE(ip) @ jump to next instruction 11802 11803/* continuation for OP_SHR_LONG_2ADDR */ 11804 11805.LOP_SHR_LONG_2ADDR_finish: 11806 GET_INST_OPCODE(ip) @ extract opcode from rINST 11807 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11808 GOTO_OPCODE(ip) @ jump to next instruction 11809 11810/* continuation for OP_USHR_LONG_2ADDR */ 11811 11812.LOP_USHR_LONG_2ADDR_finish: 11813 GET_INST_OPCODE(ip) @ extract opcode from rINST 11814 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 11815 GOTO_OPCODE(ip) @ jump to next instruction 11816 11817/* continuation for OP_IGET_VOLATILE */ 11818 11819 /* 11820 * Currently: 11821 * r0 holds resolved field 11822 * r9 holds object 11823 */ 11824.LOP_IGET_VOLATILE_finish: 11825 @bl common_squeak0 11826 cmp r9, #0 @ check object for null 11827 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11828 beq common_errNullObject @ object was null 11829 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11830 SMP_DMB @ acquiring load 11831 mov r2, rINST, lsr #8 @ r2<- A+ 11832 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11833 and r2, r2, #15 @ r2<- A 11834 GET_INST_OPCODE(ip) @ extract opcode from rINST 11835 SET_VREG(r0, r2) @ fp[A]<- r0 11836 GOTO_OPCODE(ip) @ jump to next instruction 11837 11838/* continuation for OP_IPUT_VOLATILE */ 11839 11840 /* 11841 * Currently: 11842 * r0 holds resolved field 11843 * r9 holds object 11844 */ 11845.LOP_IPUT_VOLATILE_finish: 11846 @bl common_squeak0 11847 mov r1, rINST, lsr #8 @ r1<- A+ 11848 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11849 and r1, r1, #15 @ r1<- A 11850 cmp r9, #0 @ check object for null 11851 GET_VREG(r0, r1) @ r0<- fp[A] 11852 beq common_errNullObject @ object was null 11853 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11854 GET_INST_OPCODE(ip) @ extract opcode from rINST 11855 SMP_DMB @ releasing store 11856 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11857 GOTO_OPCODE(ip) @ jump to next instruction 11858 11859/* continuation for OP_SGET_VOLATILE */ 11860 11861 /* 11862 * Continuation if the field has not yet been resolved. 11863 * r1: BBBB field ref 11864 */ 11865.LOP_SGET_VOLATILE_resolve: 11866 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11867 EXPORT_PC() @ resolve() could throw, so export now 11868 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11869 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11870 cmp r0, #0 @ success? 11871 bne .LOP_SGET_VOLATILE_finish @ yes, finish 11872 b common_exceptionThrown @ no, handle exception 11873 11874/* continuation for OP_SPUT_VOLATILE */ 11875 11876 /* 11877 * Continuation if the field has not yet been resolved. 11878 * r1: BBBB field ref 11879 */ 11880.LOP_SPUT_VOLATILE_resolve: 11881 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11882 EXPORT_PC() @ resolve() could throw, so export now 11883 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11884 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11885 cmp r0, #0 @ success? 11886 bne .LOP_SPUT_VOLATILE_finish @ yes, finish 11887 b common_exceptionThrown @ no, handle exception 11888 11889/* continuation for OP_IGET_OBJECT_VOLATILE */ 11890 11891 /* 11892 * Currently: 11893 * r0 holds resolved field 11894 * r9 holds object 11895 */ 11896.LOP_IGET_OBJECT_VOLATILE_finish: 11897 @bl common_squeak0 11898 cmp r9, #0 @ check object for null 11899 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11900 beq common_errNullObject @ object was null 11901 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11902 SMP_DMB @ acquiring load 11903 mov r2, rINST, lsr #8 @ r2<- A+ 11904 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11905 and r2, r2, #15 @ r2<- A 11906 GET_INST_OPCODE(ip) @ extract opcode from rINST 11907 SET_VREG(r0, r2) @ fp[A]<- r0 11908 GOTO_OPCODE(ip) @ jump to next instruction 11909 11910/* continuation for OP_IGET_WIDE_VOLATILE */ 11911 11912 /* 11913 * Currently: 11914 * r0 holds resolved field 11915 * r9 holds object 11916 */ 11917.LOP_IGET_WIDE_VOLATILE_finish: 11918 cmp r9, #0 @ check object for null 11919 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11920 beq common_errNullObject @ object was null 11921 .if 1 11922 add r0, r9, r3 @ r0<- address of field 11923 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 11924 .else 11925 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11926 .endif 11927 mov r2, rINST, lsr #8 @ r2<- A+ 11928 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11929 and r2, r2, #15 @ r2<- A 11930 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11931 GET_INST_OPCODE(ip) @ extract opcode from rINST 11932 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11933 GOTO_OPCODE(ip) @ jump to next instruction 11934 11935/* continuation for OP_IPUT_WIDE_VOLATILE */ 11936 11937 /* 11938 * Currently: 11939 * r0 holds resolved field 11940 * r9 holds object 11941 */ 11942.LOP_IPUT_WIDE_VOLATILE_finish: 11943 mov r2, rINST, lsr #8 @ r2<- A+ 11944 cmp r9, #0 @ check object for null 11945 and r2, r2, #15 @ r2<- A 11946 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11947 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 11948 beq common_errNullObject @ object was null 11949 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11950 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 11951 GET_INST_OPCODE(r10) @ extract opcode from rINST 11952 .if 1 11953 add r2, r9, r3 @ r2<- target address 11954 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 11955 .else 11956 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 11957 .endif 11958 GOTO_OPCODE(r10) @ jump to next instruction 11959 11960/* continuation for OP_SGET_WIDE_VOLATILE */ 11961 11962 /* 11963 * Continuation if the field has not yet been resolved. 11964 * r1: BBBB field ref 11965 * 11966 * Returns StaticField pointer in r0. 11967 */ 11968.LOP_SGET_WIDE_VOLATILE_resolve: 11969 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11970 EXPORT_PC() @ resolve() could throw, so export now 11971 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11972 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11973 cmp r0, #0 @ success? 11974 bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 11975 b common_exceptionThrown @ no, handle exception 11976 11977/* continuation for OP_SPUT_WIDE_VOLATILE */ 11978 11979 /* 11980 * Continuation if the field has not yet been resolved. 11981 * r1: BBBB field ref 11982 * r9: &fp[AA] 11983 * 11984 * Returns StaticField pointer in r2. 11985 */ 11986.LOP_SPUT_WIDE_VOLATILE_resolve: 11987 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11988 EXPORT_PC() @ resolve() could throw, so export now 11989 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11990 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11991 cmp r0, #0 @ success? 11992 mov r2, r0 @ copy to r2 11993 bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 11994 b common_exceptionThrown @ no, handle exception 11995 11996/* continuation for OP_EXECUTE_INLINE */ 11997 11998 /* 11999 * Extract args, call function. 12000 * r0 = #of args (0-4) 12001 * r10 = call index 12002 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12003 * 12004 * Other ideas: 12005 * - Use a jump table from the main piece to jump directly into the 12006 * AND/LDR pairs. Costs a data load, saves a branch. 12007 * - Have five separate pieces that do the loading, so we can work the 12008 * interleave a little better. Increases code size. 12009 */ 12010.LOP_EXECUTE_INLINE_continue: 12011 rsb r0, r0, #4 @ r0<- 4-r0 12012 FETCH(r9, 2) @ r9<- FEDC 12013 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12014 bl common_abort @ (skipped due to ARM prefetch) 120154: and ip, r9, #0xf000 @ isolate F 12016 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 120173: and ip, r9, #0x0f00 @ isolate E 12018 ldr r2, [rFP, ip, lsr #6] @ r2<- vE 120192: and ip, r9, #0x00f0 @ isolate D 12020 ldr r1, [rFP, ip, lsr #2] @ r1<- vD 120211: and ip, r9, #0x000f @ isolate C 12022 ldr r0, [rFP, ip, lsl #2] @ r0<- vC 120230: 12024 ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 12025 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12026 @ (not reached) 12027 12028.LOP_EXECUTE_INLINE_table: 12029 .word gDvmInlineOpsTable 12030 12031/* continuation for OP_EXECUTE_INLINE_RANGE */ 12032 12033 /* 12034 * Extract args, call function. 12035 * r0 = #of args (0-4) 12036 * r10 = call index 12037 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12038 */ 12039.LOP_EXECUTE_INLINE_RANGE_continue: 12040 rsb r0, r0, #4 @ r0<- 4-r0 12041 FETCH(r9, 2) @ r9<- CCCC 12042 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12043 bl common_abort @ (skipped due to ARM prefetch) 120444: add ip, r9, #3 @ base+3 12045 GET_VREG(r3, ip) @ r3<- vBase[3] 120463: add ip, r9, #2 @ base+2 12047 GET_VREG(r2, ip) @ r2<- vBase[2] 120482: add ip, r9, #1 @ base+1 12049 GET_VREG(r1, ip) @ r1<- vBase[1] 120501: add ip, r9, #0 @ (nop) 12051 GET_VREG(r0, ip) @ r0<- vBase[0] 120520: 12053 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 12054 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12055 @ (not reached) 12056 12057.LOP_EXECUTE_INLINE_RANGE_table: 12058 .word gDvmInlineOpsTable 12059 12060/* continuation for OP_IPUT_OBJECT_VOLATILE */ 12061 12062 /* 12063 * Currently: 12064 * r0 holds resolved field 12065 * r9 holds object 12066 */ 12067.LOP_IPUT_OBJECT_VOLATILE_finish: 12068 @bl common_squeak0 12069 mov r1, rINST, lsr #8 @ r1<- A+ 12070 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12071 and r1, r1, #15 @ r1<- A 12072 cmp r9, #0 @ check object for null 12073 GET_VREG(r0, r1) @ r0<- fp[A] 12074 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12075 beq common_errNullObject @ object was null 12076 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12077 GET_INST_OPCODE(ip) @ extract opcode from rINST 12078 SMP_DMB @ releasing store 12079 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12080 cmp r0, #0 @ stored a null reference? 12081 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12082 GOTO_OPCODE(ip) @ jump to next instruction 12083 12084/* continuation for OP_SGET_OBJECT_VOLATILE */ 12085 12086 /* 12087 * Continuation if the field has not yet been resolved. 12088 * r1: BBBB field ref 12089 */ 12090.LOP_SGET_OBJECT_VOLATILE_resolve: 12091 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12092 EXPORT_PC() @ resolve() could throw, so export now 12093 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12094 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12095 cmp r0, #0 @ success? 12096 bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish 12097 b common_exceptionThrown @ no, handle exception 12098 12099/* continuation for OP_SPUT_OBJECT_VOLATILE */ 12100.LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 12101 mov r2, rINST, lsr #8 @ r2<- AA 12102 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12103 GET_VREG(r1, r2) @ r1<- fp[AA] 12104 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12105 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 12106 GET_INST_OPCODE(ip) @ extract opcode from rINST 12107 SMP_DMB @ releasing store 12108 str r1, [r0, #offStaticField_value] @ field<- vAA 12109 cmp r1, #0 @ stored a null object? 12110 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12111 GOTO_OPCODE(ip) @ jump to next instruction 12112 12113/* continuation for OP_CONST_CLASS_JUMBO */ 12114 12115 /* 12116 * Continuation if the Class has not yet been resolved. 12117 * r1: AAAAAAAA (Class ref) 12118 * r9: target register 12119 */ 12120.LOP_CONST_CLASS_JUMBO_resolve: 12121 EXPORT_PC() 12122 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12123 mov r2, #1 @ r2<- true 12124 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12125 bl dvmResolveClass @ r0<- Class reference 12126 cmp r0, #0 @ failed? 12127 beq common_exceptionThrown @ yup, handle the exception 12128 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12129 GET_INST_OPCODE(ip) @ extract opcode from rINST 12130 SET_VREG(r0, r9) @ vBBBB<- r0 12131 GOTO_OPCODE(ip) @ jump to next instruction 12132 12133/* continuation for OP_CHECK_CAST_JUMBO */ 12134 12135 /* 12136 * Trivial test failed, need to perform full check. This is common. 12137 * r0 holds obj->clazz 12138 * r1 holds desired class resolved from AAAAAAAA 12139 * r9 holds object 12140 */ 12141.LOP_CHECK_CAST_JUMBO_fullcheck: 12142 mov r10, r1 @ avoid ClassObject getting clobbered 12143 bl dvmInstanceofNonTrivial @ r0<- boolean result 12144 cmp r0, #0 @ failed? 12145 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success 12146 12147 @ A cast has failed. We need to throw a ClassCastException. 12148 EXPORT_PC() @ about to throw 12149 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 12150 mov r1, r10 @ r1<- desired class 12151 bl dvmThrowClassCastException 12152 b common_exceptionThrown 12153 12154 /* 12155 * Advance PC and get the next opcode. 12156 */ 12157.LOP_CHECK_CAST_JUMBO_okay: 12158 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12159 GET_INST_OPCODE(ip) @ extract opcode from rINST 12160 GOTO_OPCODE(ip) @ jump to next instruction 12161 12162 /* 12163 * Resolution required. This is the least-likely path. 12164 * 12165 * r2 holds AAAAAAAA 12166 * r9 holds object 12167 */ 12168.LOP_CHECK_CAST_JUMBO_resolve: 12169 EXPORT_PC() @ resolve() could throw 12170 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12171 mov r1, r2 @ r1<- AAAAAAAA 12172 mov r2, #0 @ r2<- false 12173 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12174 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12175 cmp r0, #0 @ got null? 12176 beq common_exceptionThrown @ yes, handle exception 12177 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12178 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 12179 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off 12180 12181/* continuation for OP_INSTANCE_OF_JUMBO */ 12182 12183 /* 12184 * Class resolved, determine type of check necessary. This is common. 12185 * r0 holds obj->clazz 12186 * r1 holds class resolved from AAAAAAAA 12187 * r9 holds BBBB 12188 */ 12189.LOP_INSTANCE_OF_JUMBO_resolved: 12190 cmp r0, r1 @ same class (trivial success)? 12191 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish 12192 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck 12193 12194 /* 12195 * Trivial test failed, need to perform full check. This is common. 12196 * r0 holds obj->clazz 12197 * r1 holds class resolved from AAAAAAAA 12198 * r9 holds BBBB 12199 */ 12200.LOP_INSTANCE_OF_JUMBO_fullcheck: 12201 bl dvmInstanceofNonTrivial @ r0<- boolean result 12202 @ fall through to OP_INSTANCE_OF_JUMBO_store 12203 12204 /* 12205 * r0 holds boolean result 12206 * r9 holds BBBB 12207 */ 12208.LOP_INSTANCE_OF_JUMBO_store: 12209 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12210 SET_VREG(r0, r9) @ vBBBB<- r0 12211 GET_INST_OPCODE(ip) @ extract opcode from rINST 12212 GOTO_OPCODE(ip) @ jump to next instruction 12213 12214 /* 12215 * Trivial test succeeded, save and bail. 12216 * r9 holds BBBB 12217 */ 12218.LOP_INSTANCE_OF_JUMBO_trivial: 12219 mov r0, #1 @ indicate success 12220 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper 12221 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12222 SET_VREG(r0, r9) @ vBBBB<- r0 12223 GET_INST_OPCODE(ip) @ extract opcode from rINST 12224 GOTO_OPCODE(ip) @ jump to next instruction 12225 12226 /* 12227 * Resolution required. This is the least-likely path. 12228 * 12229 * r3 holds AAAAAAAA 12230 * r9 holds BBBB 12231 */ 12232 12233.LOP_INSTANCE_OF_JUMBO_resolve: 12234 EXPORT_PC() @ resolve() could throw 12235 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12236 mov r1, r3 @ r1<- AAAAAAAA 12237 mov r2, #1 @ r2<- true 12238 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12239 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12240 cmp r0, #0 @ got null? 12241 beq common_exceptionThrown @ yes, handle exception 12242 FETCH(r3, 4) @ r3<- vCCCC 12243 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12244 GET_VREG(r0, r3) @ r0<- vCCCC (object) 12245 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 12246 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off 12247 12248/* continuation for OP_NEW_INSTANCE_JUMBO */ 12249 12250 .balign 32 @ minimize cache lines 12251.LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object 12252 FETCH(r3, 3) @ r3<- BBBB 12253 cmp r0, #0 @ failed? 12254 beq common_exceptionThrown @ yes, handle the exception 12255 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12256 GET_INST_OPCODE(ip) @ extract opcode from rINST 12257 SET_VREG(r0, r3) @ vBBBB<- r0 12258 GOTO_OPCODE(ip) @ jump to next instruction 12259 12260 /* 12261 * Class initialization required. 12262 * 12263 * r0 holds class object 12264 */ 12265.LOP_NEW_INSTANCE_JUMBO_needinit: 12266 mov r9, r0 @ save r0 12267 bl dvmInitClass @ initialize class 12268 cmp r0, #0 @ check boolean result 12269 mov r0, r9 @ restore r0 12270 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue 12271 b common_exceptionThrown @ failed, deal with init exception 12272 12273 /* 12274 * Resolution required. This is the least-likely path. 12275 * 12276 * r1 holds AAAAAAAA 12277 */ 12278.LOP_NEW_INSTANCE_JUMBO_resolve: 12279 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12280 mov r2, #0 @ r2<- false 12281 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12282 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12283 cmp r0, #0 @ got null? 12284 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue 12285 b common_exceptionThrown @ yes, handle exception 12286 12287/* continuation for OP_NEW_ARRAY_JUMBO */ 12288 12289 12290 /* 12291 * Resolve class. (This is an uncommon case.) 12292 * 12293 * r1 holds array length 12294 * r2 holds class ref AAAAAAAA 12295 */ 12296.LOP_NEW_ARRAY_JUMBO_resolve: 12297 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12298 mov r9, r1 @ r9<- length (save) 12299 mov r1, r2 @ r1<- AAAAAAAA 12300 mov r2, #0 @ r2<- false 12301 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12302 bl dvmResolveClass @ r0<- call(clazz, ref) 12303 cmp r0, #0 @ got null? 12304 mov r1, r9 @ r1<- length (restore) 12305 beq common_exceptionThrown @ yes, handle exception 12306 @ fall through to OP_NEW_ARRAY_JUMBO_finish 12307 12308 /* 12309 * Finish allocation. 12310 * 12311 * r0 holds class 12312 * r1 holds array length 12313 */ 12314.LOP_NEW_ARRAY_JUMBO_finish: 12315 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 12316 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 12317 cmp r0, #0 @ failed? 12318 FETCH(r2, 3) @ r2<- vBBBB 12319 beq common_exceptionThrown @ yes, handle the exception 12320 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12321 GET_INST_OPCODE(ip) @ extract opcode from rINST 12322 SET_VREG(r0, r2) @ vBBBB<- r0 12323 GOTO_OPCODE(ip) @ jump to next instruction 12324 12325/* continuation for OP_FILLED_NEW_ARRAY_JUMBO */ 12326 12327 /* 12328 * On entry: 12329 * r0 holds array class 12330 */ 12331.LOP_FILLED_NEW_ARRAY_JUMBO_continue: 12332 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 12333 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 12334 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 12335 FETCH(r1, 3) @ r1<- BBBB (length) 12336 cmp rINST, #'I' @ array of ints? 12337 cmpne rINST, #'L' @ array of objects? 12338 cmpne rINST, #'[' @ array of arrays? 12339 mov r9, r1 @ save length in r9 12340 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet 12341 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 12342 cmp r0, #0 @ null return? 12343 beq common_exceptionThrown @ alloc failed, handle exception 12344 12345 FETCH(r1, 4) @ r1<- CCCC 12346 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 12347 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 12348 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 12349 subs r9, r9, #1 @ length--, check for neg 12350 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST 12351 bmi 2f @ was zero, bail 12352 12353 @ copy values from registers into the array 12354 @ r0=array, r1=CCCC, r9=BBBB (length) 12355 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 123561: ldr r3, [r2], #4 @ r3<- *r2++ 12357 subs r9, r9, #1 @ count-- 12358 str r3, [r0], #4 @ *contents++ = vX 12359 bpl 1b 12360 123612: ldr r0, [rSELF, #offThread_retval] @ r0<- object 12362 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 12363 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12364 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 12365 cmp r1, #'I' @ Is int array? 12366 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 12367 GOTO_OPCODE(ip) @ execute it 12368 12369 /* 12370 * Throw an exception indicating that we have not implemented this 12371 * mode of filled-new-array. 12372 */ 12373.LOP_FILLED_NEW_ARRAY_JUMBO_notimpl: 12374 ldr r0, .L_strFilledNewArrayNotImpl 12375 bl dvmThrowInternalError 12376 b common_exceptionThrown 12377 12378/* continuation for OP_IGET_JUMBO */ 12379 12380 /* 12381 * Currently: 12382 * r0 holds resolved field 12383 * r9 holds object 12384 */ 12385.LOP_IGET_JUMBO_resolved: 12386 cmp r0, #0 @ resolution unsuccessful? 12387 beq common_exceptionThrown @ yes, throw exception 12388 @ fall through to OP_IGET_JUMBO_finish 12389 12390 /* 12391 * Currently: 12392 * r0 holds resolved field 12393 * r9 holds object 12394 */ 12395.LOP_IGET_JUMBO_finish: 12396 @bl common_squeak0 12397 cmp r9, #0 @ check object for null 12398 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12399 beq common_errNullObject @ object was null 12400 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12401 @ no-op @ acquiring load 12402 FETCH(r2, 3) @ r2<- BBBB 12403 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12404 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12405 GET_INST_OPCODE(ip) @ extract opcode from rINST 12406 GOTO_OPCODE(ip) @ jump to next instruction 12407 12408/* continuation for OP_IGET_WIDE_JUMBO */ 12409 12410 /* 12411 * Currently: 12412 * r0 holds resolved field 12413 * r9 holds object 12414 */ 12415.LOP_IGET_WIDE_JUMBO_resolved: 12416 cmp r0, #0 @ resolution unsuccessful? 12417 beq common_exceptionThrown @ yes, throw exception 12418 @ fall through to OP_IGET_WIDE_JUMBO_finish 12419 12420 /* 12421 * Currently: 12422 * r0 holds resolved field 12423 * r9 holds object 12424 */ 12425.LOP_IGET_WIDE_JUMBO_finish: 12426 cmp r9, #0 @ check object for null 12427 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12428 beq common_errNullObject @ object was null 12429 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12430 FETCH(r2, 3) @ r2<- BBBB 12431 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12432 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12433 GET_INST_OPCODE(ip) @ extract opcode from rINST 12434 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 12435 GOTO_OPCODE(ip) @ jump to next instruction 12436 12437/* continuation for OP_IGET_OBJECT_JUMBO */ 12438 12439 /* 12440 * Currently: 12441 * r0 holds resolved field 12442 * r9 holds object 12443 */ 12444.LOP_IGET_OBJECT_JUMBO_resolved: 12445 cmp r0, #0 @ resolution unsuccessful? 12446 beq common_exceptionThrown @ yes, throw exception 12447 @ fall through to OP_IGET_OBJECT_JUMBO_finish 12448 12449 /* 12450 * Currently: 12451 * r0 holds resolved field 12452 * r9 holds object 12453 */ 12454.LOP_IGET_OBJECT_JUMBO_finish: 12455 @bl common_squeak0 12456 cmp r9, #0 @ check object for null 12457 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12458 beq common_errNullObject @ object was null 12459 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12460 @ no-op @ acquiring load 12461 FETCH(r2, 3) @ r2<- BBBB 12462 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12463 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12464 GET_INST_OPCODE(ip) @ extract opcode from rINST 12465 GOTO_OPCODE(ip) @ jump to next instruction 12466 12467/* continuation for OP_IGET_BOOLEAN_JUMBO */ 12468 12469 /* 12470 * Currently: 12471 * r0 holds resolved field 12472 * r9 holds object 12473 */ 12474.LOP_IGET_BOOLEAN_JUMBO_resolved: 12475 cmp r0, #0 @ resolution unsuccessful? 12476 beq common_exceptionThrown @ yes, throw exception 12477 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish 12478 12479 /* 12480 * Currently: 12481 * r0 holds resolved field 12482 * r9 holds object 12483 */ 12484.LOP_IGET_BOOLEAN_JUMBO_finish: 12485 @bl common_squeak1 12486 cmp r9, #0 @ check object for null 12487 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12488 beq common_errNullObject @ object was null 12489 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12490 @ no-op @ acquiring load 12491 FETCH(r2, 3) @ r2<- BBBB 12492 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12493 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12494 GET_INST_OPCODE(ip) @ extract opcode from rINST 12495 GOTO_OPCODE(ip) @ jump to next instruction 12496 12497/* continuation for OP_IGET_BYTE_JUMBO */ 12498 12499 /* 12500 * Currently: 12501 * r0 holds resolved field 12502 * r9 holds object 12503 */ 12504.LOP_IGET_BYTE_JUMBO_resolved: 12505 cmp r0, #0 @ resolution unsuccessful? 12506 beq common_exceptionThrown @ yes, throw exception 12507 @ fall through to OP_IGET_BYTE_JUMBO_finish 12508 12509 /* 12510 * Currently: 12511 * r0 holds resolved field 12512 * r9 holds object 12513 */ 12514.LOP_IGET_BYTE_JUMBO_finish: 12515 @bl common_squeak2 12516 cmp r9, #0 @ check object for null 12517 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12518 beq common_errNullObject @ object was null 12519 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12520 @ no-op @ acquiring load 12521 FETCH(r2, 3) @ r2<- BBBB 12522 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12523 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12524 GET_INST_OPCODE(ip) @ extract opcode from rINST 12525 GOTO_OPCODE(ip) @ jump to next instruction 12526 12527/* continuation for OP_IGET_CHAR_JUMBO */ 12528 12529 /* 12530 * Currently: 12531 * r0 holds resolved field 12532 * r9 holds object 12533 */ 12534.LOP_IGET_CHAR_JUMBO_resolved: 12535 cmp r0, #0 @ resolution unsuccessful? 12536 beq common_exceptionThrown @ yes, throw exception 12537 @ fall through to OP_IGET_CHAR_JUMBO_finish 12538 12539 /* 12540 * Currently: 12541 * r0 holds resolved field 12542 * r9 holds object 12543 */ 12544.LOP_IGET_CHAR_JUMBO_finish: 12545 @bl common_squeak3 12546 cmp r9, #0 @ check object for null 12547 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12548 beq common_errNullObject @ object was null 12549 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12550 @ no-op @ acquiring load 12551 FETCH(r2, 3) @ r2<- BBBB 12552 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12553 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12554 GET_INST_OPCODE(ip) @ extract opcode from rINST 12555 GOTO_OPCODE(ip) @ jump to next instruction 12556 12557/* continuation for OP_IGET_SHORT_JUMBO */ 12558 12559 /* 12560 * Currently: 12561 * r0 holds resolved field 12562 * r9 holds object 12563 */ 12564.LOP_IGET_SHORT_JUMBO_resolved: 12565 cmp r0, #0 @ resolution unsuccessful? 12566 beq common_exceptionThrown @ yes, throw exception 12567 @ fall through to OP_IGET_SHORT_JUMBO_finish 12568 12569 /* 12570 * Currently: 12571 * r0 holds resolved field 12572 * r9 holds object 12573 */ 12574.LOP_IGET_SHORT_JUMBO_finish: 12575 @bl common_squeak4 12576 cmp r9, #0 @ check object for null 12577 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12578 beq common_errNullObject @ object was null 12579 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12580 @ no-op @ acquiring load 12581 FETCH(r2, 3) @ r2<- BBBB 12582 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12583 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12584 GET_INST_OPCODE(ip) @ extract opcode from rINST 12585 GOTO_OPCODE(ip) @ jump to next instruction 12586 12587/* continuation for OP_IPUT_JUMBO */ 12588 12589 /* 12590 * Currently: 12591 * r0 holds resolved field 12592 * r9 holds object 12593 */ 12594.LOP_IPUT_JUMBO_resolved: 12595 cmp r0, #0 @ resolution unsuccessful? 12596 beq common_exceptionThrown @ yes, throw exception 12597 @ fall through to OP_IPUT_JUMBO_finish 12598 12599 /* 12600 * Currently: 12601 * r0 holds resolved field 12602 * r9 holds object 12603 */ 12604.LOP_IPUT_JUMBO_finish: 12605 @bl common_squeak0 12606 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12607 FETCH(r1, 3) @ r1<- BBBB 12608 cmp r9, #0 @ check object for null 12609 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12610 beq common_errNullObject @ object was null 12611 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12612 GET_INST_OPCODE(ip) @ extract opcode from rINST 12613 @ no-op @ releasing store 12614 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12615 GOTO_OPCODE(ip) @ jump to next instruction 12616 12617/* continuation for OP_IPUT_WIDE_JUMBO */ 12618 12619 /* 12620 * Currently: 12621 * r0 holds resolved field 12622 * r9 holds object 12623 */ 12624.LOP_IPUT_WIDE_JUMBO_resolved: 12625 cmp r0, #0 @ resolution unsuccessful? 12626 beq common_exceptionThrown @ yes, throw exception 12627 @ fall through to OP_IPUT_WIDE_JUMBO_finish 12628 12629 /* 12630 * Currently: 12631 * r0 holds resolved field 12632 * r9 holds object 12633 */ 12634.LOP_IPUT_WIDE_JUMBO_finish: 12635 cmp r9, #0 @ check object for null 12636 FETCH(r2, 3) @ r1<- BBBB 12637 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12638 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12639 beq common_errNullObject @ object was null 12640 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12641 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 12642 GET_INST_OPCODE(r10) @ extract opcode from rINST 12643 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12644 GOTO_OPCODE(r10) @ jump to next instruction 12645 12646/* continuation for OP_IPUT_OBJECT_JUMBO */ 12647 12648 /* 12649 * Currently: 12650 * r0 holds resolved field 12651 * r9 holds object 12652 */ 12653.LOP_IPUT_OBJECT_JUMBO_resolved: 12654 cmp r0, #0 @ resolution unsuccessful? 12655 beq common_exceptionThrown @ yes, throw exception 12656 @ fall through to OP_IPUT_OBJECT_JUMBO_finish 12657 12658 /* 12659 * Currently: 12660 * r0 holds resolved field 12661 * r9 holds object 12662 */ 12663.LOP_IPUT_OBJECT_JUMBO_finish: 12664 @bl common_squeak0 12665 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12666 FETCH(r1, 3) @ r1<- BBBB 12667 cmp r9, #0 @ check object for null 12668 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12669 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12670 beq common_errNullObject @ object was null 12671 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12672 GET_INST_OPCODE(ip) @ extract opcode from rINST 12673 @ no-op @ releasing store 12674 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12675 cmp r0, #0 @ stored a null reference? 12676 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12677 GOTO_OPCODE(ip) @ jump to next instruction 12678 12679/* continuation for OP_IPUT_BOOLEAN_JUMBO */ 12680 12681 /* 12682 * Currently: 12683 * r0 holds resolved field 12684 * r9 holds object 12685 */ 12686.LOP_IPUT_BOOLEAN_JUMBO_resolved: 12687 cmp r0, #0 @ resolution unsuccessful? 12688 beq common_exceptionThrown @ yes, throw exception 12689 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish 12690 12691 /* 12692 * Currently: 12693 * r0 holds resolved field 12694 * r9 holds object 12695 */ 12696.LOP_IPUT_BOOLEAN_JUMBO_finish: 12697 @bl common_squeak1 12698 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12699 FETCH(r1, 3) @ r1<- BBBB 12700 cmp r9, #0 @ check object for null 12701 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12702 beq common_errNullObject @ object was null 12703 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12704 GET_INST_OPCODE(ip) @ extract opcode from rINST 12705 @ no-op @ releasing store 12706 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12707 GOTO_OPCODE(ip) @ jump to next instruction 12708 12709/* continuation for OP_IPUT_BYTE_JUMBO */ 12710 12711 /* 12712 * Currently: 12713 * r0 holds resolved field 12714 * r9 holds object 12715 */ 12716.LOP_IPUT_BYTE_JUMBO_resolved: 12717 cmp r0, #0 @ resolution unsuccessful? 12718 beq common_exceptionThrown @ yes, throw exception 12719 @ fall through to OP_IPUT_BYTE_JUMBO_finish 12720 12721 /* 12722 * Currently: 12723 * r0 holds resolved field 12724 * r9 holds object 12725 */ 12726.LOP_IPUT_BYTE_JUMBO_finish: 12727 @bl common_squeak2 12728 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12729 FETCH(r1, 3) @ r1<- BBBB 12730 cmp r9, #0 @ check object for null 12731 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12732 beq common_errNullObject @ object was null 12733 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12734 GET_INST_OPCODE(ip) @ extract opcode from rINST 12735 @ no-op @ releasing store 12736 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12737 GOTO_OPCODE(ip) @ jump to next instruction 12738 12739/* continuation for OP_IPUT_CHAR_JUMBO */ 12740 12741 /* 12742 * Currently: 12743 * r0 holds resolved field 12744 * r9 holds object 12745 */ 12746.LOP_IPUT_CHAR_JUMBO_resolved: 12747 cmp r0, #0 @ resolution unsuccessful? 12748 beq common_exceptionThrown @ yes, throw exception 12749 @ fall through to OP_IPUT_CHAR_JUMBO_finish 12750 12751 /* 12752 * Currently: 12753 * r0 holds resolved field 12754 * r9 holds object 12755 */ 12756.LOP_IPUT_CHAR_JUMBO_finish: 12757 @bl common_squeak3 12758 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12759 FETCH(r1, 3) @ r1<- BBBB 12760 cmp r9, #0 @ check object for null 12761 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12762 beq common_errNullObject @ object was null 12763 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12764 GET_INST_OPCODE(ip) @ extract opcode from rINST 12765 @ no-op @ releasing store 12766 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12767 GOTO_OPCODE(ip) @ jump to next instruction 12768 12769/* continuation for OP_IPUT_SHORT_JUMBO */ 12770 12771 /* 12772 * Currently: 12773 * r0 holds resolved field 12774 * r9 holds object 12775 */ 12776.LOP_IPUT_SHORT_JUMBO_resolved: 12777 cmp r0, #0 @ resolution unsuccessful? 12778 beq common_exceptionThrown @ yes, throw exception 12779 @ fall through to OP_IPUT_SHORT_JUMBO_finish 12780 12781 /* 12782 * Currently: 12783 * r0 holds resolved field 12784 * r9 holds object 12785 */ 12786.LOP_IPUT_SHORT_JUMBO_finish: 12787 @bl common_squeak4 12788 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12789 FETCH(r1, 3) @ r1<- BBBB 12790 cmp r9, #0 @ check object for null 12791 GET_VREG(r0, r1) @ r0<- fp[BBBB] 12792 beq common_errNullObject @ object was null 12793 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12794 GET_INST_OPCODE(ip) @ extract opcode from rINST 12795 @ no-op @ releasing store 12796 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12797 GOTO_OPCODE(ip) @ jump to next instruction 12798 12799/* continuation for OP_SGET_JUMBO */ 12800 12801 /* 12802 * Continuation if the field has not yet been resolved. 12803 * r1: AAAAAAAA field ref 12804 */ 12805.LOP_SGET_JUMBO_resolve: 12806 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12807 EXPORT_PC() @ resolve() could throw, so export now 12808 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12809 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12810 cmp r0, #0 @ success? 12811 bne .LOP_SGET_JUMBO_finish @ yes, finish 12812 b common_exceptionThrown @ no, handle exception 12813 12814/* continuation for OP_SGET_WIDE_JUMBO */ 12815 12816 /* 12817 * Continuation if the field has not yet been resolved. 12818 * r1: BBBB field ref 12819 * 12820 * Returns StaticField pointer in r0. 12821 */ 12822.LOP_SGET_WIDE_JUMBO_resolve: 12823 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12824 EXPORT_PC() @ resolve() could throw, so export now 12825 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12826 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12827 cmp r0, #0 @ success? 12828 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish 12829 b common_exceptionThrown @ no, handle exception 12830 12831/* continuation for OP_SGET_OBJECT_JUMBO */ 12832 12833 /* 12834 * Continuation if the field has not yet been resolved. 12835 * r1: AAAAAAAA field ref 12836 */ 12837.LOP_SGET_OBJECT_JUMBO_resolve: 12838 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12839 EXPORT_PC() @ resolve() could throw, so export now 12840 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12841 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12842 cmp r0, #0 @ success? 12843 bne .LOP_SGET_OBJECT_JUMBO_finish @ yes, finish 12844 b common_exceptionThrown @ no, handle exception 12845 12846/* continuation for OP_SGET_BOOLEAN_JUMBO */ 12847 12848 /* 12849 * Continuation if the field has not yet been resolved. 12850 * r1: AAAAAAAA field ref 12851 */ 12852.LOP_SGET_BOOLEAN_JUMBO_resolve: 12853 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12854 EXPORT_PC() @ resolve() could throw, so export now 12855 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12856 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12857 cmp r0, #0 @ success? 12858 bne .LOP_SGET_BOOLEAN_JUMBO_finish @ yes, finish 12859 b common_exceptionThrown @ no, handle exception 12860 12861/* continuation for OP_SGET_BYTE_JUMBO */ 12862 12863 /* 12864 * Continuation if the field has not yet been resolved. 12865 * r1: AAAAAAAA field ref 12866 */ 12867.LOP_SGET_BYTE_JUMBO_resolve: 12868 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12869 EXPORT_PC() @ resolve() could throw, so export now 12870 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12871 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12872 cmp r0, #0 @ success? 12873 bne .LOP_SGET_BYTE_JUMBO_finish @ yes, finish 12874 b common_exceptionThrown @ no, handle exception 12875 12876/* continuation for OP_SGET_CHAR_JUMBO */ 12877 12878 /* 12879 * Continuation if the field has not yet been resolved. 12880 * r1: AAAAAAAA field ref 12881 */ 12882.LOP_SGET_CHAR_JUMBO_resolve: 12883 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12884 EXPORT_PC() @ resolve() could throw, so export now 12885 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12886 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12887 cmp r0, #0 @ success? 12888 bne .LOP_SGET_CHAR_JUMBO_finish @ yes, finish 12889 b common_exceptionThrown @ no, handle exception 12890 12891/* continuation for OP_SGET_SHORT_JUMBO */ 12892 12893 /* 12894 * Continuation if the field has not yet been resolved. 12895 * r1: AAAAAAAA field ref 12896 */ 12897.LOP_SGET_SHORT_JUMBO_resolve: 12898 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12899 EXPORT_PC() @ resolve() could throw, so export now 12900 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12901 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12902 cmp r0, #0 @ success? 12903 bne .LOP_SGET_SHORT_JUMBO_finish @ yes, finish 12904 b common_exceptionThrown @ no, handle exception 12905 12906/* continuation for OP_SPUT_JUMBO */ 12907 12908 /* 12909 * Continuation if the field has not yet been resolved. 12910 * r1: AAAAAAAA field ref 12911 */ 12912.LOP_SPUT_JUMBO_resolve: 12913 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12914 EXPORT_PC() @ resolve() could throw, so export now 12915 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12916 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12917 cmp r0, #0 @ success? 12918 bne .LOP_SPUT_JUMBO_finish @ yes, finish 12919 b common_exceptionThrown @ no, handle exception 12920 12921/* continuation for OP_SPUT_WIDE_JUMBO */ 12922 12923 /* 12924 * Continuation if the field has not yet been resolved. 12925 * r1: BBBB field ref 12926 * r9: &fp[AA] 12927 * 12928 * Returns StaticField pointer in r2. 12929 */ 12930.LOP_SPUT_WIDE_JUMBO_resolve: 12931 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12932 EXPORT_PC() @ resolve() could throw, so export now 12933 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12934 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12935 cmp r0, #0 @ success? 12936 mov r2, r0 @ copy to r2 12937 bne .LOP_SPUT_WIDE_JUMBO_finish @ yes, finish 12938 b common_exceptionThrown @ no, handle exception 12939 12940/* continuation for OP_SPUT_OBJECT_JUMBO */ 12941 12942.LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0 12943 FETCH(r2, 3) @ r2<- BBBB 12944 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12945 GET_VREG(r1, r2) @ r1<- fp[BBBB] 12946 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12947 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 12948 GET_INST_OPCODE(ip) @ extract opcode from rINST 12949 @ no-op @ releasing store 12950 str r1, [r0, #offStaticField_value] @ field<- vBBBB 12951 cmp r1, #0 @ stored a null object? 12952 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12953 GOTO_OPCODE(ip) @ jump to next instruction 12954 12955/* continuation for OP_SPUT_BOOLEAN_JUMBO */ 12956 12957 /* 12958 * Continuation if the field has not yet been resolved. 12959 * r1: AAAAAAAA field ref 12960 */ 12961.LOP_SPUT_BOOLEAN_JUMBO_resolve: 12962 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12963 EXPORT_PC() @ resolve() could throw, so export now 12964 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12965 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12966 cmp r0, #0 @ success? 12967 bne .LOP_SPUT_BOOLEAN_JUMBO_finish @ yes, finish 12968 b common_exceptionThrown @ no, handle exception 12969 12970/* continuation for OP_SPUT_BYTE_JUMBO */ 12971 12972 /* 12973 * Continuation if the field has not yet been resolved. 12974 * r1: AAAAAAAA field ref 12975 */ 12976.LOP_SPUT_BYTE_JUMBO_resolve: 12977 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12978 EXPORT_PC() @ resolve() could throw, so export now 12979 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12980 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12981 cmp r0, #0 @ success? 12982 bne .LOP_SPUT_BYTE_JUMBO_finish @ yes, finish 12983 b common_exceptionThrown @ no, handle exception 12984 12985/* continuation for OP_SPUT_CHAR_JUMBO */ 12986 12987 /* 12988 * Continuation if the field has not yet been resolved. 12989 * r1: AAAAAAAA field ref 12990 */ 12991.LOP_SPUT_CHAR_JUMBO_resolve: 12992 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12993 EXPORT_PC() @ resolve() could throw, so export now 12994 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12995 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12996 cmp r0, #0 @ success? 12997 bne .LOP_SPUT_CHAR_JUMBO_finish @ yes, finish 12998 b common_exceptionThrown @ no, handle exception 12999 13000/* continuation for OP_SPUT_SHORT_JUMBO */ 13001 13002 /* 13003 * Continuation if the field has not yet been resolved. 13004 * r1: AAAAAAAA field ref 13005 */ 13006.LOP_SPUT_SHORT_JUMBO_resolve: 13007 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13008 EXPORT_PC() @ resolve() could throw, so export now 13009 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13010 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13011 cmp r0, #0 @ success? 13012 bne .LOP_SPUT_SHORT_JUMBO_finish @ yes, finish 13013 b common_exceptionThrown @ no, handle exception 13014 13015/* continuation for OP_INVOKE_VIRTUAL_JUMBO */ 13016 13017 /* 13018 * At this point: 13019 * r0 = resolved base method 13020 */ 13021.LOP_INVOKE_VIRTUAL_JUMBO_continue: 13022 FETCH(r10, 4) @ r10<- CCCC 13023 GET_VREG(r1, r10) @ r1<- "this" ptr 13024 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13025 cmp r1, #0 @ is "this" null? 13026 beq common_errNullObject @ null "this", throw exception 13027 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 13028 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 13029 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 13030 bl common_invokeMethodJumbo @ continue on 13031 13032/* continuation for OP_INVOKE_SUPER_JUMBO */ 13033 13034 /* 13035 * At this point: 13036 * r0 = resolved base method 13037 * r9 = method->clazz 13038 */ 13039.LOP_INVOKE_SUPER_JUMBO_continue: 13040 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 13041 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13042 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 13043 EXPORT_PC() @ must export for invoke 13044 cmp r2, r3 @ compare (methodIndex, vtableCount) 13045 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass 13046 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 13047 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 13048 bl common_invokeMethodJumbo @ continue on 13049 13050.LOP_INVOKE_SUPER_JUMBO_resolve: 13051 mov r0, r9 @ r0<- method->clazz 13052 mov r2, #METHOD_VIRTUAL @ resolver method type 13053 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13054 cmp r0, #0 @ got null? 13055 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue 13056 b common_exceptionThrown @ yes, handle exception 13057 13058 /* 13059 * Throw a NoSuchMethodError with the method name as the message. 13060 * r0 = resolved base method 13061 */ 13062.LOP_INVOKE_SUPER_JUMBO_nsm: 13063 ldr r1, [r0, #offMethod_name] @ r1<- method name 13064 b common_errNoSuchMethod 13065 13066/* continuation for OP_INVOKE_DIRECT_JUMBO */ 13067 13068 /* 13069 * On entry: 13070 * r1 = reference (CCCC) 13071 * r10 = "this" register 13072 */ 13073.LOP_INVOKE_DIRECT_JUMBO_resolve: 13074 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 13075 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 13076 mov r2, #METHOD_DIRECT @ resolver method type 13077 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13078 cmp r0, #0 @ got null? 13079 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 13080 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue 13081 b common_exceptionThrown @ yes, handle exception 13082 13083 .size dvmAsmSisterStart, .-dvmAsmSisterStart 13084 .global dvmAsmSisterEnd 13085dvmAsmSisterEnd: 13086 13087 13088 .global dvmAsmAltInstructionStart 13089 .type dvmAsmAltInstructionStart, %function 13090dvmAsmAltInstructionStart: 13091 .text 13092 13093/* ------------------------------ */ 13094 .balign 64 13095.L_ALT_OP_NOP: /* 0x00 */ 13096/* File: armv5te/alt_stub.S */ 13097/* 13098 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13099 * any interesting requests and then jump to the real instruction 13100 * handler. Note that the call to dvmCheckInst is done as a tail call. 13101 */ 13102 adrl lr, dvmAsmInstructionStart + (0 * 64) 13103 mov r0, rPC @ arg0 13104 mov r1, rSELF @ arg1 13105 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13106 13107/* ------------------------------ */ 13108 .balign 64 13109.L_ALT_OP_MOVE: /* 0x01 */ 13110/* File: armv5te/alt_stub.S */ 13111/* 13112 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13113 * any interesting requests and then jump to the real instruction 13114 * handler. Note that the call to dvmCheckInst is done as a tail call. 13115 */ 13116 adrl lr, dvmAsmInstructionStart + (1 * 64) 13117 mov r0, rPC @ arg0 13118 mov r1, rSELF @ arg1 13119 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13120 13121/* ------------------------------ */ 13122 .balign 64 13123.L_ALT_OP_MOVE_FROM16: /* 0x02 */ 13124/* File: armv5te/alt_stub.S */ 13125/* 13126 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13127 * any interesting requests and then jump to the real instruction 13128 * handler. Note that the call to dvmCheckInst is done as a tail call. 13129 */ 13130 adrl lr, dvmAsmInstructionStart + (2 * 64) 13131 mov r0, rPC @ arg0 13132 mov r1, rSELF @ arg1 13133 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13134 13135/* ------------------------------ */ 13136 .balign 64 13137.L_ALT_OP_MOVE_16: /* 0x03 */ 13138/* File: armv5te/alt_stub.S */ 13139/* 13140 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13141 * any interesting requests and then jump to the real instruction 13142 * handler. Note that the call to dvmCheckInst is done as a tail call. 13143 */ 13144 adrl lr, dvmAsmInstructionStart + (3 * 64) 13145 mov r0, rPC @ arg0 13146 mov r1, rSELF @ arg1 13147 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13148 13149/* ------------------------------ */ 13150 .balign 64 13151.L_ALT_OP_MOVE_WIDE: /* 0x04 */ 13152/* File: armv5te/alt_stub.S */ 13153/* 13154 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13155 * any interesting requests and then jump to the real instruction 13156 * handler. Note that the call to dvmCheckInst is done as a tail call. 13157 */ 13158 adrl lr, dvmAsmInstructionStart + (4 * 64) 13159 mov r0, rPC @ arg0 13160 mov r1, rSELF @ arg1 13161 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13162 13163/* ------------------------------ */ 13164 .balign 64 13165.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */ 13166/* File: armv5te/alt_stub.S */ 13167/* 13168 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13169 * any interesting requests and then jump to the real instruction 13170 * handler. Note that the call to dvmCheckInst is done as a tail call. 13171 */ 13172 adrl lr, dvmAsmInstructionStart + (5 * 64) 13173 mov r0, rPC @ arg0 13174 mov r1, rSELF @ arg1 13175 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13176 13177/* ------------------------------ */ 13178 .balign 64 13179.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */ 13180/* File: armv5te/alt_stub.S */ 13181/* 13182 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13183 * any interesting requests and then jump to the real instruction 13184 * handler. Note that the call to dvmCheckInst is done as a tail call. 13185 */ 13186 adrl lr, dvmAsmInstructionStart + (6 * 64) 13187 mov r0, rPC @ arg0 13188 mov r1, rSELF @ arg1 13189 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13190 13191/* ------------------------------ */ 13192 .balign 64 13193.L_ALT_OP_MOVE_OBJECT: /* 0x07 */ 13194/* File: armv5te/alt_stub.S */ 13195/* 13196 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13197 * any interesting requests and then jump to the real instruction 13198 * handler. Note that the call to dvmCheckInst is done as a tail call. 13199 */ 13200 adrl lr, dvmAsmInstructionStart + (7 * 64) 13201 mov r0, rPC @ arg0 13202 mov r1, rSELF @ arg1 13203 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13204 13205/* ------------------------------ */ 13206 .balign 64 13207.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 13208/* File: armv5te/alt_stub.S */ 13209/* 13210 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13211 * any interesting requests and then jump to the real instruction 13212 * handler. Note that the call to dvmCheckInst is done as a tail call. 13213 */ 13214 adrl lr, dvmAsmInstructionStart + (8 * 64) 13215 mov r0, rPC @ arg0 13216 mov r1, rSELF @ arg1 13217 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13218 13219/* ------------------------------ */ 13220 .balign 64 13221.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */ 13222/* File: armv5te/alt_stub.S */ 13223/* 13224 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13225 * any interesting requests and then jump to the real instruction 13226 * handler. Note that the call to dvmCheckInst is done as a tail call. 13227 */ 13228 adrl lr, dvmAsmInstructionStart + (9 * 64) 13229 mov r0, rPC @ arg0 13230 mov r1, rSELF @ arg1 13231 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13232 13233/* ------------------------------ */ 13234 .balign 64 13235.L_ALT_OP_MOVE_RESULT: /* 0x0a */ 13236/* File: armv5te/alt_stub.S */ 13237/* 13238 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13239 * any interesting requests and then jump to the real instruction 13240 * handler. Note that the call to dvmCheckInst is done as a tail call. 13241 */ 13242 adrl lr, dvmAsmInstructionStart + (10 * 64) 13243 mov r0, rPC @ arg0 13244 mov r1, rSELF @ arg1 13245 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13246 13247/* ------------------------------ */ 13248 .balign 64 13249.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */ 13250/* File: armv5te/alt_stub.S */ 13251/* 13252 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13253 * any interesting requests and then jump to the real instruction 13254 * handler. Note that the call to dvmCheckInst is done as a tail call. 13255 */ 13256 adrl lr, dvmAsmInstructionStart + (11 * 64) 13257 mov r0, rPC @ arg0 13258 mov r1, rSELF @ arg1 13259 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13260 13261/* ------------------------------ */ 13262 .balign 64 13263.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 13264/* File: armv5te/alt_stub.S */ 13265/* 13266 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13267 * any interesting requests and then jump to the real instruction 13268 * handler. Note that the call to dvmCheckInst is done as a tail call. 13269 */ 13270 adrl lr, dvmAsmInstructionStart + (12 * 64) 13271 mov r0, rPC @ arg0 13272 mov r1, rSELF @ arg1 13273 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13274 13275/* ------------------------------ */ 13276 .balign 64 13277.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */ 13278/* File: armv5te/alt_stub.S */ 13279/* 13280 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13281 * any interesting requests and then jump to the real instruction 13282 * handler. Note that the call to dvmCheckInst is done as a tail call. 13283 */ 13284 adrl lr, dvmAsmInstructionStart + (13 * 64) 13285 mov r0, rPC @ arg0 13286 mov r1, rSELF @ arg1 13287 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13288 13289/* ------------------------------ */ 13290 .balign 64 13291.L_ALT_OP_RETURN_VOID: /* 0x0e */ 13292/* File: armv5te/alt_stub.S */ 13293/* 13294 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13295 * any interesting requests and then jump to the real instruction 13296 * handler. Note that the call to dvmCheckInst is done as a tail call. 13297 */ 13298 adrl lr, dvmAsmInstructionStart + (14 * 64) 13299 mov r0, rPC @ arg0 13300 mov r1, rSELF @ arg1 13301 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13302 13303/* ------------------------------ */ 13304 .balign 64 13305.L_ALT_OP_RETURN: /* 0x0f */ 13306/* File: armv5te/alt_stub.S */ 13307/* 13308 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13309 * any interesting requests and then jump to the real instruction 13310 * handler. Note that the call to dvmCheckInst is done as a tail call. 13311 */ 13312 adrl lr, dvmAsmInstructionStart + (15 * 64) 13313 mov r0, rPC @ arg0 13314 mov r1, rSELF @ arg1 13315 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13316 13317/* ------------------------------ */ 13318 .balign 64 13319.L_ALT_OP_RETURN_WIDE: /* 0x10 */ 13320/* File: armv5te/alt_stub.S */ 13321/* 13322 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13323 * any interesting requests and then jump to the real instruction 13324 * handler. Note that the call to dvmCheckInst is done as a tail call. 13325 */ 13326 adrl lr, dvmAsmInstructionStart + (16 * 64) 13327 mov r0, rPC @ arg0 13328 mov r1, rSELF @ arg1 13329 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13330 13331/* ------------------------------ */ 13332 .balign 64 13333.L_ALT_OP_RETURN_OBJECT: /* 0x11 */ 13334/* File: armv5te/alt_stub.S */ 13335/* 13336 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13337 * any interesting requests and then jump to the real instruction 13338 * handler. Note that the call to dvmCheckInst is done as a tail call. 13339 */ 13340 adrl lr, dvmAsmInstructionStart + (17 * 64) 13341 mov r0, rPC @ arg0 13342 mov r1, rSELF @ arg1 13343 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13344 13345/* ------------------------------ */ 13346 .balign 64 13347.L_ALT_OP_CONST_4: /* 0x12 */ 13348/* File: armv5te/alt_stub.S */ 13349/* 13350 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13351 * any interesting requests and then jump to the real instruction 13352 * handler. Note that the call to dvmCheckInst is done as a tail call. 13353 */ 13354 adrl lr, dvmAsmInstructionStart + (18 * 64) 13355 mov r0, rPC @ arg0 13356 mov r1, rSELF @ arg1 13357 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13358 13359/* ------------------------------ */ 13360 .balign 64 13361.L_ALT_OP_CONST_16: /* 0x13 */ 13362/* File: armv5te/alt_stub.S */ 13363/* 13364 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13365 * any interesting requests and then jump to the real instruction 13366 * handler. Note that the call to dvmCheckInst is done as a tail call. 13367 */ 13368 adrl lr, dvmAsmInstructionStart + (19 * 64) 13369 mov r0, rPC @ arg0 13370 mov r1, rSELF @ arg1 13371 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13372 13373/* ------------------------------ */ 13374 .balign 64 13375.L_ALT_OP_CONST: /* 0x14 */ 13376/* File: armv5te/alt_stub.S */ 13377/* 13378 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13379 * any interesting requests and then jump to the real instruction 13380 * handler. Note that the call to dvmCheckInst is done as a tail call. 13381 */ 13382 adrl lr, dvmAsmInstructionStart + (20 * 64) 13383 mov r0, rPC @ arg0 13384 mov r1, rSELF @ arg1 13385 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13386 13387/* ------------------------------ */ 13388 .balign 64 13389.L_ALT_OP_CONST_HIGH16: /* 0x15 */ 13390/* File: armv5te/alt_stub.S */ 13391/* 13392 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13393 * any interesting requests and then jump to the real instruction 13394 * handler. Note that the call to dvmCheckInst is done as a tail call. 13395 */ 13396 adrl lr, dvmAsmInstructionStart + (21 * 64) 13397 mov r0, rPC @ arg0 13398 mov r1, rSELF @ arg1 13399 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13400 13401/* ------------------------------ */ 13402 .balign 64 13403.L_ALT_OP_CONST_WIDE_16: /* 0x16 */ 13404/* File: armv5te/alt_stub.S */ 13405/* 13406 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13407 * any interesting requests and then jump to the real instruction 13408 * handler. Note that the call to dvmCheckInst is done as a tail call. 13409 */ 13410 adrl lr, dvmAsmInstructionStart + (22 * 64) 13411 mov r0, rPC @ arg0 13412 mov r1, rSELF @ arg1 13413 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13414 13415/* ------------------------------ */ 13416 .balign 64 13417.L_ALT_OP_CONST_WIDE_32: /* 0x17 */ 13418/* File: armv5te/alt_stub.S */ 13419/* 13420 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13421 * any interesting requests and then jump to the real instruction 13422 * handler. Note that the call to dvmCheckInst is done as a tail call. 13423 */ 13424 adrl lr, dvmAsmInstructionStart + (23 * 64) 13425 mov r0, rPC @ arg0 13426 mov r1, rSELF @ arg1 13427 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13428 13429/* ------------------------------ */ 13430 .balign 64 13431.L_ALT_OP_CONST_WIDE: /* 0x18 */ 13432/* File: armv5te/alt_stub.S */ 13433/* 13434 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13435 * any interesting requests and then jump to the real instruction 13436 * handler. Note that the call to dvmCheckInst is done as a tail call. 13437 */ 13438 adrl lr, dvmAsmInstructionStart + (24 * 64) 13439 mov r0, rPC @ arg0 13440 mov r1, rSELF @ arg1 13441 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13442 13443/* ------------------------------ */ 13444 .balign 64 13445.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */ 13446/* File: armv5te/alt_stub.S */ 13447/* 13448 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13449 * any interesting requests and then jump to the real instruction 13450 * handler. Note that the call to dvmCheckInst is done as a tail call. 13451 */ 13452 adrl lr, dvmAsmInstructionStart + (25 * 64) 13453 mov r0, rPC @ arg0 13454 mov r1, rSELF @ arg1 13455 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13456 13457/* ------------------------------ */ 13458 .balign 64 13459.L_ALT_OP_CONST_STRING: /* 0x1a */ 13460/* File: armv5te/alt_stub.S */ 13461/* 13462 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13463 * any interesting requests and then jump to the real instruction 13464 * handler. Note that the call to dvmCheckInst is done as a tail call. 13465 */ 13466 adrl lr, dvmAsmInstructionStart + (26 * 64) 13467 mov r0, rPC @ arg0 13468 mov r1, rSELF @ arg1 13469 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13470 13471/* ------------------------------ */ 13472 .balign 64 13473.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */ 13474/* File: armv5te/alt_stub.S */ 13475/* 13476 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13477 * any interesting requests and then jump to the real instruction 13478 * handler. Note that the call to dvmCheckInst is done as a tail call. 13479 */ 13480 adrl lr, dvmAsmInstructionStart + (27 * 64) 13481 mov r0, rPC @ arg0 13482 mov r1, rSELF @ arg1 13483 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13484 13485/* ------------------------------ */ 13486 .balign 64 13487.L_ALT_OP_CONST_CLASS: /* 0x1c */ 13488/* File: armv5te/alt_stub.S */ 13489/* 13490 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13491 * any interesting requests and then jump to the real instruction 13492 * handler. Note that the call to dvmCheckInst is done as a tail call. 13493 */ 13494 adrl lr, dvmAsmInstructionStart + (28 * 64) 13495 mov r0, rPC @ arg0 13496 mov r1, rSELF @ arg1 13497 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13498 13499/* ------------------------------ */ 13500 .balign 64 13501.L_ALT_OP_MONITOR_ENTER: /* 0x1d */ 13502/* File: armv5te/alt_stub.S */ 13503/* 13504 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13505 * any interesting requests and then jump to the real instruction 13506 * handler. Note that the call to dvmCheckInst is done as a tail call. 13507 */ 13508 adrl lr, dvmAsmInstructionStart + (29 * 64) 13509 mov r0, rPC @ arg0 13510 mov r1, rSELF @ arg1 13511 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13512 13513/* ------------------------------ */ 13514 .balign 64 13515.L_ALT_OP_MONITOR_EXIT: /* 0x1e */ 13516/* File: armv5te/alt_stub.S */ 13517/* 13518 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13519 * any interesting requests and then jump to the real instruction 13520 * handler. Note that the call to dvmCheckInst is done as a tail call. 13521 */ 13522 adrl lr, dvmAsmInstructionStart + (30 * 64) 13523 mov r0, rPC @ arg0 13524 mov r1, rSELF @ arg1 13525 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13526 13527/* ------------------------------ */ 13528 .balign 64 13529.L_ALT_OP_CHECK_CAST: /* 0x1f */ 13530/* File: armv5te/alt_stub.S */ 13531/* 13532 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13533 * any interesting requests and then jump to the real instruction 13534 * handler. Note that the call to dvmCheckInst is done as a tail call. 13535 */ 13536 adrl lr, dvmAsmInstructionStart + (31 * 64) 13537 mov r0, rPC @ arg0 13538 mov r1, rSELF @ arg1 13539 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13540 13541/* ------------------------------ */ 13542 .balign 64 13543.L_ALT_OP_INSTANCE_OF: /* 0x20 */ 13544/* File: armv5te/alt_stub.S */ 13545/* 13546 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13547 * any interesting requests and then jump to the real instruction 13548 * handler. Note that the call to dvmCheckInst is done as a tail call. 13549 */ 13550 adrl lr, dvmAsmInstructionStart + (32 * 64) 13551 mov r0, rPC @ arg0 13552 mov r1, rSELF @ arg1 13553 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13554 13555/* ------------------------------ */ 13556 .balign 64 13557.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */ 13558/* File: armv5te/alt_stub.S */ 13559/* 13560 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13561 * any interesting requests and then jump to the real instruction 13562 * handler. Note that the call to dvmCheckInst is done as a tail call. 13563 */ 13564 adrl lr, dvmAsmInstructionStart + (33 * 64) 13565 mov r0, rPC @ arg0 13566 mov r1, rSELF @ arg1 13567 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13568 13569/* ------------------------------ */ 13570 .balign 64 13571.L_ALT_OP_NEW_INSTANCE: /* 0x22 */ 13572/* File: armv5te/alt_stub.S */ 13573/* 13574 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13575 * any interesting requests and then jump to the real instruction 13576 * handler. Note that the call to dvmCheckInst is done as a tail call. 13577 */ 13578 adrl lr, dvmAsmInstructionStart + (34 * 64) 13579 mov r0, rPC @ arg0 13580 mov r1, rSELF @ arg1 13581 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13582 13583/* ------------------------------ */ 13584 .balign 64 13585.L_ALT_OP_NEW_ARRAY: /* 0x23 */ 13586/* File: armv5te/alt_stub.S */ 13587/* 13588 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13589 * any interesting requests and then jump to the real instruction 13590 * handler. Note that the call to dvmCheckInst is done as a tail call. 13591 */ 13592 adrl lr, dvmAsmInstructionStart + (35 * 64) 13593 mov r0, rPC @ arg0 13594 mov r1, rSELF @ arg1 13595 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13596 13597/* ------------------------------ */ 13598 .balign 64 13599.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */ 13600/* File: armv5te/alt_stub.S */ 13601/* 13602 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13603 * any interesting requests and then jump to the real instruction 13604 * handler. Note that the call to dvmCheckInst is done as a tail call. 13605 */ 13606 adrl lr, dvmAsmInstructionStart + (36 * 64) 13607 mov r0, rPC @ arg0 13608 mov r1, rSELF @ arg1 13609 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13610 13611/* ------------------------------ */ 13612 .balign 64 13613.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 13614/* File: armv5te/alt_stub.S */ 13615/* 13616 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13617 * any interesting requests and then jump to the real instruction 13618 * handler. Note that the call to dvmCheckInst is done as a tail call. 13619 */ 13620 adrl lr, dvmAsmInstructionStart + (37 * 64) 13621 mov r0, rPC @ arg0 13622 mov r1, rSELF @ arg1 13623 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13624 13625/* ------------------------------ */ 13626 .balign 64 13627.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */ 13628/* File: armv5te/alt_stub.S */ 13629/* 13630 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13631 * any interesting requests and then jump to the real instruction 13632 * handler. Note that the call to dvmCheckInst is done as a tail call. 13633 */ 13634 adrl lr, dvmAsmInstructionStart + (38 * 64) 13635 mov r0, rPC @ arg0 13636 mov r1, rSELF @ arg1 13637 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13638 13639/* ------------------------------ */ 13640 .balign 64 13641.L_ALT_OP_THROW: /* 0x27 */ 13642/* File: armv5te/alt_stub.S */ 13643/* 13644 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13645 * any interesting requests and then jump to the real instruction 13646 * handler. Note that the call to dvmCheckInst is done as a tail call. 13647 */ 13648 adrl lr, dvmAsmInstructionStart + (39 * 64) 13649 mov r0, rPC @ arg0 13650 mov r1, rSELF @ arg1 13651 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13652 13653/* ------------------------------ */ 13654 .balign 64 13655.L_ALT_OP_GOTO: /* 0x28 */ 13656/* File: armv5te/alt_stub.S */ 13657/* 13658 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13659 * any interesting requests and then jump to the real instruction 13660 * handler. Note that the call to dvmCheckInst is done as a tail call. 13661 */ 13662 adrl lr, dvmAsmInstructionStart + (40 * 64) 13663 mov r0, rPC @ arg0 13664 mov r1, rSELF @ arg1 13665 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13666 13667/* ------------------------------ */ 13668 .balign 64 13669.L_ALT_OP_GOTO_16: /* 0x29 */ 13670/* File: armv5te/alt_stub.S */ 13671/* 13672 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13673 * any interesting requests and then jump to the real instruction 13674 * handler. Note that the call to dvmCheckInst is done as a tail call. 13675 */ 13676 adrl lr, dvmAsmInstructionStart + (41 * 64) 13677 mov r0, rPC @ arg0 13678 mov r1, rSELF @ arg1 13679 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13680 13681/* ------------------------------ */ 13682 .balign 64 13683.L_ALT_OP_GOTO_32: /* 0x2a */ 13684/* File: armv5te/alt_stub.S */ 13685/* 13686 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13687 * any interesting requests and then jump to the real instruction 13688 * handler. Note that the call to dvmCheckInst is done as a tail call. 13689 */ 13690 adrl lr, dvmAsmInstructionStart + (42 * 64) 13691 mov r0, rPC @ arg0 13692 mov r1, rSELF @ arg1 13693 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13694 13695/* ------------------------------ */ 13696 .balign 64 13697.L_ALT_OP_PACKED_SWITCH: /* 0x2b */ 13698/* File: armv5te/alt_stub.S */ 13699/* 13700 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13701 * any interesting requests and then jump to the real instruction 13702 * handler. Note that the call to dvmCheckInst is done as a tail call. 13703 */ 13704 adrl lr, dvmAsmInstructionStart + (43 * 64) 13705 mov r0, rPC @ arg0 13706 mov r1, rSELF @ arg1 13707 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13708 13709/* ------------------------------ */ 13710 .balign 64 13711.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */ 13712/* File: armv5te/alt_stub.S */ 13713/* 13714 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13715 * any interesting requests and then jump to the real instruction 13716 * handler. Note that the call to dvmCheckInst is done as a tail call. 13717 */ 13718 adrl lr, dvmAsmInstructionStart + (44 * 64) 13719 mov r0, rPC @ arg0 13720 mov r1, rSELF @ arg1 13721 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13722 13723/* ------------------------------ */ 13724 .balign 64 13725.L_ALT_OP_CMPL_FLOAT: /* 0x2d */ 13726/* File: armv5te/alt_stub.S */ 13727/* 13728 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13729 * any interesting requests and then jump to the real instruction 13730 * handler. Note that the call to dvmCheckInst is done as a tail call. 13731 */ 13732 adrl lr, dvmAsmInstructionStart + (45 * 64) 13733 mov r0, rPC @ arg0 13734 mov r1, rSELF @ arg1 13735 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13736 13737/* ------------------------------ */ 13738 .balign 64 13739.L_ALT_OP_CMPG_FLOAT: /* 0x2e */ 13740/* File: armv5te/alt_stub.S */ 13741/* 13742 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13743 * any interesting requests and then jump to the real instruction 13744 * handler. Note that the call to dvmCheckInst is done as a tail call. 13745 */ 13746 adrl lr, dvmAsmInstructionStart + (46 * 64) 13747 mov r0, rPC @ arg0 13748 mov r1, rSELF @ arg1 13749 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13750 13751/* ------------------------------ */ 13752 .balign 64 13753.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */ 13754/* File: armv5te/alt_stub.S */ 13755/* 13756 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13757 * any interesting requests and then jump to the real instruction 13758 * handler. Note that the call to dvmCheckInst is done as a tail call. 13759 */ 13760 adrl lr, dvmAsmInstructionStart + (47 * 64) 13761 mov r0, rPC @ arg0 13762 mov r1, rSELF @ arg1 13763 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13764 13765/* ------------------------------ */ 13766 .balign 64 13767.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */ 13768/* File: armv5te/alt_stub.S */ 13769/* 13770 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13771 * any interesting requests and then jump to the real instruction 13772 * handler. Note that the call to dvmCheckInst is done as a tail call. 13773 */ 13774 adrl lr, dvmAsmInstructionStart + (48 * 64) 13775 mov r0, rPC @ arg0 13776 mov r1, rSELF @ arg1 13777 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13778 13779/* ------------------------------ */ 13780 .balign 64 13781.L_ALT_OP_CMP_LONG: /* 0x31 */ 13782/* File: armv5te/alt_stub.S */ 13783/* 13784 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13785 * any interesting requests and then jump to the real instruction 13786 * handler. Note that the call to dvmCheckInst is done as a tail call. 13787 */ 13788 adrl lr, dvmAsmInstructionStart + (49 * 64) 13789 mov r0, rPC @ arg0 13790 mov r1, rSELF @ arg1 13791 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13792 13793/* ------------------------------ */ 13794 .balign 64 13795.L_ALT_OP_IF_EQ: /* 0x32 */ 13796/* File: armv5te/alt_stub.S */ 13797/* 13798 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13799 * any interesting requests and then jump to the real instruction 13800 * handler. Note that the call to dvmCheckInst is done as a tail call. 13801 */ 13802 adrl lr, dvmAsmInstructionStart + (50 * 64) 13803 mov r0, rPC @ arg0 13804 mov r1, rSELF @ arg1 13805 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13806 13807/* ------------------------------ */ 13808 .balign 64 13809.L_ALT_OP_IF_NE: /* 0x33 */ 13810/* File: armv5te/alt_stub.S */ 13811/* 13812 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13813 * any interesting requests and then jump to the real instruction 13814 * handler. Note that the call to dvmCheckInst is done as a tail call. 13815 */ 13816 adrl lr, dvmAsmInstructionStart + (51 * 64) 13817 mov r0, rPC @ arg0 13818 mov r1, rSELF @ arg1 13819 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13820 13821/* ------------------------------ */ 13822 .balign 64 13823.L_ALT_OP_IF_LT: /* 0x34 */ 13824/* File: armv5te/alt_stub.S */ 13825/* 13826 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13827 * any interesting requests and then jump to the real instruction 13828 * handler. Note that the call to dvmCheckInst is done as a tail call. 13829 */ 13830 adrl lr, dvmAsmInstructionStart + (52 * 64) 13831 mov r0, rPC @ arg0 13832 mov r1, rSELF @ arg1 13833 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13834 13835/* ------------------------------ */ 13836 .balign 64 13837.L_ALT_OP_IF_GE: /* 0x35 */ 13838/* File: armv5te/alt_stub.S */ 13839/* 13840 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13841 * any interesting requests and then jump to the real instruction 13842 * handler. Note that the call to dvmCheckInst is done as a tail call. 13843 */ 13844 adrl lr, dvmAsmInstructionStart + (53 * 64) 13845 mov r0, rPC @ arg0 13846 mov r1, rSELF @ arg1 13847 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13848 13849/* ------------------------------ */ 13850 .balign 64 13851.L_ALT_OP_IF_GT: /* 0x36 */ 13852/* File: armv5te/alt_stub.S */ 13853/* 13854 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13855 * any interesting requests and then jump to the real instruction 13856 * handler. Note that the call to dvmCheckInst is done as a tail call. 13857 */ 13858 adrl lr, dvmAsmInstructionStart + (54 * 64) 13859 mov r0, rPC @ arg0 13860 mov r1, rSELF @ arg1 13861 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13862 13863/* ------------------------------ */ 13864 .balign 64 13865.L_ALT_OP_IF_LE: /* 0x37 */ 13866/* File: armv5te/alt_stub.S */ 13867/* 13868 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13869 * any interesting requests and then jump to the real instruction 13870 * handler. Note that the call to dvmCheckInst is done as a tail call. 13871 */ 13872 adrl lr, dvmAsmInstructionStart + (55 * 64) 13873 mov r0, rPC @ arg0 13874 mov r1, rSELF @ arg1 13875 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13876 13877/* ------------------------------ */ 13878 .balign 64 13879.L_ALT_OP_IF_EQZ: /* 0x38 */ 13880/* File: armv5te/alt_stub.S */ 13881/* 13882 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13883 * any interesting requests and then jump to the real instruction 13884 * handler. Note that the call to dvmCheckInst is done as a tail call. 13885 */ 13886 adrl lr, dvmAsmInstructionStart + (56 * 64) 13887 mov r0, rPC @ arg0 13888 mov r1, rSELF @ arg1 13889 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13890 13891/* ------------------------------ */ 13892 .balign 64 13893.L_ALT_OP_IF_NEZ: /* 0x39 */ 13894/* File: armv5te/alt_stub.S */ 13895/* 13896 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13897 * any interesting requests and then jump to the real instruction 13898 * handler. Note that the call to dvmCheckInst is done as a tail call. 13899 */ 13900 adrl lr, dvmAsmInstructionStart + (57 * 64) 13901 mov r0, rPC @ arg0 13902 mov r1, rSELF @ arg1 13903 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13904 13905/* ------------------------------ */ 13906 .balign 64 13907.L_ALT_OP_IF_LTZ: /* 0x3a */ 13908/* File: armv5te/alt_stub.S */ 13909/* 13910 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13911 * any interesting requests and then jump to the real instruction 13912 * handler. Note that the call to dvmCheckInst is done as a tail call. 13913 */ 13914 adrl lr, dvmAsmInstructionStart + (58 * 64) 13915 mov r0, rPC @ arg0 13916 mov r1, rSELF @ arg1 13917 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13918 13919/* ------------------------------ */ 13920 .balign 64 13921.L_ALT_OP_IF_GEZ: /* 0x3b */ 13922/* File: armv5te/alt_stub.S */ 13923/* 13924 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13925 * any interesting requests and then jump to the real instruction 13926 * handler. Note that the call to dvmCheckInst is done as a tail call. 13927 */ 13928 adrl lr, dvmAsmInstructionStart + (59 * 64) 13929 mov r0, rPC @ arg0 13930 mov r1, rSELF @ arg1 13931 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13932 13933/* ------------------------------ */ 13934 .balign 64 13935.L_ALT_OP_IF_GTZ: /* 0x3c */ 13936/* File: armv5te/alt_stub.S */ 13937/* 13938 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13939 * any interesting requests and then jump to the real instruction 13940 * handler. Note that the call to dvmCheckInst is done as a tail call. 13941 */ 13942 adrl lr, dvmAsmInstructionStart + (60 * 64) 13943 mov r0, rPC @ arg0 13944 mov r1, rSELF @ arg1 13945 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13946 13947/* ------------------------------ */ 13948 .balign 64 13949.L_ALT_OP_IF_LEZ: /* 0x3d */ 13950/* File: armv5te/alt_stub.S */ 13951/* 13952 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13953 * any interesting requests and then jump to the real instruction 13954 * handler. Note that the call to dvmCheckInst is done as a tail call. 13955 */ 13956 adrl lr, dvmAsmInstructionStart + (61 * 64) 13957 mov r0, rPC @ arg0 13958 mov r1, rSELF @ arg1 13959 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13960 13961/* ------------------------------ */ 13962 .balign 64 13963.L_ALT_OP_UNUSED_3E: /* 0x3e */ 13964/* File: armv5te/alt_stub.S */ 13965/* 13966 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13967 * any interesting requests and then jump to the real instruction 13968 * handler. Note that the call to dvmCheckInst is done as a tail call. 13969 */ 13970 adrl lr, dvmAsmInstructionStart + (62 * 64) 13971 mov r0, rPC @ arg0 13972 mov r1, rSELF @ arg1 13973 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13974 13975/* ------------------------------ */ 13976 .balign 64 13977.L_ALT_OP_UNUSED_3F: /* 0x3f */ 13978/* File: armv5te/alt_stub.S */ 13979/* 13980 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13981 * any interesting requests and then jump to the real instruction 13982 * handler. Note that the call to dvmCheckInst is done as a tail call. 13983 */ 13984 adrl lr, dvmAsmInstructionStart + (63 * 64) 13985 mov r0, rPC @ arg0 13986 mov r1, rSELF @ arg1 13987 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13988 13989/* ------------------------------ */ 13990 .balign 64 13991.L_ALT_OP_UNUSED_40: /* 0x40 */ 13992/* File: armv5te/alt_stub.S */ 13993/* 13994 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13995 * any interesting requests and then jump to the real instruction 13996 * handler. Note that the call to dvmCheckInst is done as a tail call. 13997 */ 13998 adrl lr, dvmAsmInstructionStart + (64 * 64) 13999 mov r0, rPC @ arg0 14000 mov r1, rSELF @ arg1 14001 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14002 14003/* ------------------------------ */ 14004 .balign 64 14005.L_ALT_OP_UNUSED_41: /* 0x41 */ 14006/* File: armv5te/alt_stub.S */ 14007/* 14008 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14009 * any interesting requests and then jump to the real instruction 14010 * handler. Note that the call to dvmCheckInst is done as a tail call. 14011 */ 14012 adrl lr, dvmAsmInstructionStart + (65 * 64) 14013 mov r0, rPC @ arg0 14014 mov r1, rSELF @ arg1 14015 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14016 14017/* ------------------------------ */ 14018 .balign 64 14019.L_ALT_OP_UNUSED_42: /* 0x42 */ 14020/* File: armv5te/alt_stub.S */ 14021/* 14022 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14023 * any interesting requests and then jump to the real instruction 14024 * handler. Note that the call to dvmCheckInst is done as a tail call. 14025 */ 14026 adrl lr, dvmAsmInstructionStart + (66 * 64) 14027 mov r0, rPC @ arg0 14028 mov r1, rSELF @ arg1 14029 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14030 14031/* ------------------------------ */ 14032 .balign 64 14033.L_ALT_OP_UNUSED_43: /* 0x43 */ 14034/* File: armv5te/alt_stub.S */ 14035/* 14036 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14037 * any interesting requests and then jump to the real instruction 14038 * handler. Note that the call to dvmCheckInst is done as a tail call. 14039 */ 14040 adrl lr, dvmAsmInstructionStart + (67 * 64) 14041 mov r0, rPC @ arg0 14042 mov r1, rSELF @ arg1 14043 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14044 14045/* ------------------------------ */ 14046 .balign 64 14047.L_ALT_OP_AGET: /* 0x44 */ 14048/* File: armv5te/alt_stub.S */ 14049/* 14050 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14051 * any interesting requests and then jump to the real instruction 14052 * handler. Note that the call to dvmCheckInst is done as a tail call. 14053 */ 14054 adrl lr, dvmAsmInstructionStart + (68 * 64) 14055 mov r0, rPC @ arg0 14056 mov r1, rSELF @ arg1 14057 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14058 14059/* ------------------------------ */ 14060 .balign 64 14061.L_ALT_OP_AGET_WIDE: /* 0x45 */ 14062/* File: armv5te/alt_stub.S */ 14063/* 14064 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14065 * any interesting requests and then jump to the real instruction 14066 * handler. Note that the call to dvmCheckInst is done as a tail call. 14067 */ 14068 adrl lr, dvmAsmInstructionStart + (69 * 64) 14069 mov r0, rPC @ arg0 14070 mov r1, rSELF @ arg1 14071 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14072 14073/* ------------------------------ */ 14074 .balign 64 14075.L_ALT_OP_AGET_OBJECT: /* 0x46 */ 14076/* File: armv5te/alt_stub.S */ 14077/* 14078 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14079 * any interesting requests and then jump to the real instruction 14080 * handler. Note that the call to dvmCheckInst is done as a tail call. 14081 */ 14082 adrl lr, dvmAsmInstructionStart + (70 * 64) 14083 mov r0, rPC @ arg0 14084 mov r1, rSELF @ arg1 14085 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14086 14087/* ------------------------------ */ 14088 .balign 64 14089.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */ 14090/* File: armv5te/alt_stub.S */ 14091/* 14092 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14093 * any interesting requests and then jump to the real instruction 14094 * handler. Note that the call to dvmCheckInst is done as a tail call. 14095 */ 14096 adrl lr, dvmAsmInstructionStart + (71 * 64) 14097 mov r0, rPC @ arg0 14098 mov r1, rSELF @ arg1 14099 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14100 14101/* ------------------------------ */ 14102 .balign 64 14103.L_ALT_OP_AGET_BYTE: /* 0x48 */ 14104/* File: armv5te/alt_stub.S */ 14105/* 14106 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14107 * any interesting requests and then jump to the real instruction 14108 * handler. Note that the call to dvmCheckInst is done as a tail call. 14109 */ 14110 adrl lr, dvmAsmInstructionStart + (72 * 64) 14111 mov r0, rPC @ arg0 14112 mov r1, rSELF @ arg1 14113 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14114 14115/* ------------------------------ */ 14116 .balign 64 14117.L_ALT_OP_AGET_CHAR: /* 0x49 */ 14118/* File: armv5te/alt_stub.S */ 14119/* 14120 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14121 * any interesting requests and then jump to the real instruction 14122 * handler. Note that the call to dvmCheckInst is done as a tail call. 14123 */ 14124 adrl lr, dvmAsmInstructionStart + (73 * 64) 14125 mov r0, rPC @ arg0 14126 mov r1, rSELF @ arg1 14127 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14128 14129/* ------------------------------ */ 14130 .balign 64 14131.L_ALT_OP_AGET_SHORT: /* 0x4a */ 14132/* File: armv5te/alt_stub.S */ 14133/* 14134 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14135 * any interesting requests and then jump to the real instruction 14136 * handler. Note that the call to dvmCheckInst is done as a tail call. 14137 */ 14138 adrl lr, dvmAsmInstructionStart + (74 * 64) 14139 mov r0, rPC @ arg0 14140 mov r1, rSELF @ arg1 14141 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14142 14143/* ------------------------------ */ 14144 .balign 64 14145.L_ALT_OP_APUT: /* 0x4b */ 14146/* File: armv5te/alt_stub.S */ 14147/* 14148 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14149 * any interesting requests and then jump to the real instruction 14150 * handler. Note that the call to dvmCheckInst is done as a tail call. 14151 */ 14152 adrl lr, dvmAsmInstructionStart + (75 * 64) 14153 mov r0, rPC @ arg0 14154 mov r1, rSELF @ arg1 14155 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14156 14157/* ------------------------------ */ 14158 .balign 64 14159.L_ALT_OP_APUT_WIDE: /* 0x4c */ 14160/* File: armv5te/alt_stub.S */ 14161/* 14162 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14163 * any interesting requests and then jump to the real instruction 14164 * handler. Note that the call to dvmCheckInst is done as a tail call. 14165 */ 14166 adrl lr, dvmAsmInstructionStart + (76 * 64) 14167 mov r0, rPC @ arg0 14168 mov r1, rSELF @ arg1 14169 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14170 14171/* ------------------------------ */ 14172 .balign 64 14173.L_ALT_OP_APUT_OBJECT: /* 0x4d */ 14174/* File: armv5te/alt_stub.S */ 14175/* 14176 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14177 * any interesting requests and then jump to the real instruction 14178 * handler. Note that the call to dvmCheckInst is done as a tail call. 14179 */ 14180 adrl lr, dvmAsmInstructionStart + (77 * 64) 14181 mov r0, rPC @ arg0 14182 mov r1, rSELF @ arg1 14183 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14184 14185/* ------------------------------ */ 14186 .balign 64 14187.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */ 14188/* File: armv5te/alt_stub.S */ 14189/* 14190 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14191 * any interesting requests and then jump to the real instruction 14192 * handler. Note that the call to dvmCheckInst is done as a tail call. 14193 */ 14194 adrl lr, dvmAsmInstructionStart + (78 * 64) 14195 mov r0, rPC @ arg0 14196 mov r1, rSELF @ arg1 14197 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14198 14199/* ------------------------------ */ 14200 .balign 64 14201.L_ALT_OP_APUT_BYTE: /* 0x4f */ 14202/* File: armv5te/alt_stub.S */ 14203/* 14204 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14205 * any interesting requests and then jump to the real instruction 14206 * handler. Note that the call to dvmCheckInst is done as a tail call. 14207 */ 14208 adrl lr, dvmAsmInstructionStart + (79 * 64) 14209 mov r0, rPC @ arg0 14210 mov r1, rSELF @ arg1 14211 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14212 14213/* ------------------------------ */ 14214 .balign 64 14215.L_ALT_OP_APUT_CHAR: /* 0x50 */ 14216/* File: armv5te/alt_stub.S */ 14217/* 14218 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14219 * any interesting requests and then jump to the real instruction 14220 * handler. Note that the call to dvmCheckInst is done as a tail call. 14221 */ 14222 adrl lr, dvmAsmInstructionStart + (80 * 64) 14223 mov r0, rPC @ arg0 14224 mov r1, rSELF @ arg1 14225 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14226 14227/* ------------------------------ */ 14228 .balign 64 14229.L_ALT_OP_APUT_SHORT: /* 0x51 */ 14230/* File: armv5te/alt_stub.S */ 14231/* 14232 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14233 * any interesting requests and then jump to the real instruction 14234 * handler. Note that the call to dvmCheckInst is done as a tail call. 14235 */ 14236 adrl lr, dvmAsmInstructionStart + (81 * 64) 14237 mov r0, rPC @ arg0 14238 mov r1, rSELF @ arg1 14239 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14240 14241/* ------------------------------ */ 14242 .balign 64 14243.L_ALT_OP_IGET: /* 0x52 */ 14244/* File: armv5te/alt_stub.S */ 14245/* 14246 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14247 * any interesting requests and then jump to the real instruction 14248 * handler. Note that the call to dvmCheckInst is done as a tail call. 14249 */ 14250 adrl lr, dvmAsmInstructionStart + (82 * 64) 14251 mov r0, rPC @ arg0 14252 mov r1, rSELF @ arg1 14253 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14254 14255/* ------------------------------ */ 14256 .balign 64 14257.L_ALT_OP_IGET_WIDE: /* 0x53 */ 14258/* File: armv5te/alt_stub.S */ 14259/* 14260 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14261 * any interesting requests and then jump to the real instruction 14262 * handler. Note that the call to dvmCheckInst is done as a tail call. 14263 */ 14264 adrl lr, dvmAsmInstructionStart + (83 * 64) 14265 mov r0, rPC @ arg0 14266 mov r1, rSELF @ arg1 14267 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14268 14269/* ------------------------------ */ 14270 .balign 64 14271.L_ALT_OP_IGET_OBJECT: /* 0x54 */ 14272/* File: armv5te/alt_stub.S */ 14273/* 14274 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14275 * any interesting requests and then jump to the real instruction 14276 * handler. Note that the call to dvmCheckInst is done as a tail call. 14277 */ 14278 adrl lr, dvmAsmInstructionStart + (84 * 64) 14279 mov r0, rPC @ arg0 14280 mov r1, rSELF @ arg1 14281 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14282 14283/* ------------------------------ */ 14284 .balign 64 14285.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */ 14286/* File: armv5te/alt_stub.S */ 14287/* 14288 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14289 * any interesting requests and then jump to the real instruction 14290 * handler. Note that the call to dvmCheckInst is done as a tail call. 14291 */ 14292 adrl lr, dvmAsmInstructionStart + (85 * 64) 14293 mov r0, rPC @ arg0 14294 mov r1, rSELF @ arg1 14295 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14296 14297/* ------------------------------ */ 14298 .balign 64 14299.L_ALT_OP_IGET_BYTE: /* 0x56 */ 14300/* File: armv5te/alt_stub.S */ 14301/* 14302 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14303 * any interesting requests and then jump to the real instruction 14304 * handler. Note that the call to dvmCheckInst is done as a tail call. 14305 */ 14306 adrl lr, dvmAsmInstructionStart + (86 * 64) 14307 mov r0, rPC @ arg0 14308 mov r1, rSELF @ arg1 14309 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14310 14311/* ------------------------------ */ 14312 .balign 64 14313.L_ALT_OP_IGET_CHAR: /* 0x57 */ 14314/* File: armv5te/alt_stub.S */ 14315/* 14316 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14317 * any interesting requests and then jump to the real instruction 14318 * handler. Note that the call to dvmCheckInst is done as a tail call. 14319 */ 14320 adrl lr, dvmAsmInstructionStart + (87 * 64) 14321 mov r0, rPC @ arg0 14322 mov r1, rSELF @ arg1 14323 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14324 14325/* ------------------------------ */ 14326 .balign 64 14327.L_ALT_OP_IGET_SHORT: /* 0x58 */ 14328/* File: armv5te/alt_stub.S */ 14329/* 14330 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14331 * any interesting requests and then jump to the real instruction 14332 * handler. Note that the call to dvmCheckInst is done as a tail call. 14333 */ 14334 adrl lr, dvmAsmInstructionStart + (88 * 64) 14335 mov r0, rPC @ arg0 14336 mov r1, rSELF @ arg1 14337 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14338 14339/* ------------------------------ */ 14340 .balign 64 14341.L_ALT_OP_IPUT: /* 0x59 */ 14342/* File: armv5te/alt_stub.S */ 14343/* 14344 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14345 * any interesting requests and then jump to the real instruction 14346 * handler. Note that the call to dvmCheckInst is done as a tail call. 14347 */ 14348 adrl lr, dvmAsmInstructionStart + (89 * 64) 14349 mov r0, rPC @ arg0 14350 mov r1, rSELF @ arg1 14351 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14352 14353/* ------------------------------ */ 14354 .balign 64 14355.L_ALT_OP_IPUT_WIDE: /* 0x5a */ 14356/* File: armv5te/alt_stub.S */ 14357/* 14358 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14359 * any interesting requests and then jump to the real instruction 14360 * handler. Note that the call to dvmCheckInst is done as a tail call. 14361 */ 14362 adrl lr, dvmAsmInstructionStart + (90 * 64) 14363 mov r0, rPC @ arg0 14364 mov r1, rSELF @ arg1 14365 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14366 14367/* ------------------------------ */ 14368 .balign 64 14369.L_ALT_OP_IPUT_OBJECT: /* 0x5b */ 14370/* File: armv5te/alt_stub.S */ 14371/* 14372 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14373 * any interesting requests and then jump to the real instruction 14374 * handler. Note that the call to dvmCheckInst is done as a tail call. 14375 */ 14376 adrl lr, dvmAsmInstructionStart + (91 * 64) 14377 mov r0, rPC @ arg0 14378 mov r1, rSELF @ arg1 14379 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14380 14381/* ------------------------------ */ 14382 .balign 64 14383.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */ 14384/* File: armv5te/alt_stub.S */ 14385/* 14386 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14387 * any interesting requests and then jump to the real instruction 14388 * handler. Note that the call to dvmCheckInst is done as a tail call. 14389 */ 14390 adrl lr, dvmAsmInstructionStart + (92 * 64) 14391 mov r0, rPC @ arg0 14392 mov r1, rSELF @ arg1 14393 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14394 14395/* ------------------------------ */ 14396 .balign 64 14397.L_ALT_OP_IPUT_BYTE: /* 0x5d */ 14398/* File: armv5te/alt_stub.S */ 14399/* 14400 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14401 * any interesting requests and then jump to the real instruction 14402 * handler. Note that the call to dvmCheckInst is done as a tail call. 14403 */ 14404 adrl lr, dvmAsmInstructionStart + (93 * 64) 14405 mov r0, rPC @ arg0 14406 mov r1, rSELF @ arg1 14407 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14408 14409/* ------------------------------ */ 14410 .balign 64 14411.L_ALT_OP_IPUT_CHAR: /* 0x5e */ 14412/* File: armv5te/alt_stub.S */ 14413/* 14414 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14415 * any interesting requests and then jump to the real instruction 14416 * handler. Note that the call to dvmCheckInst is done as a tail call. 14417 */ 14418 adrl lr, dvmAsmInstructionStart + (94 * 64) 14419 mov r0, rPC @ arg0 14420 mov r1, rSELF @ arg1 14421 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14422 14423/* ------------------------------ */ 14424 .balign 64 14425.L_ALT_OP_IPUT_SHORT: /* 0x5f */ 14426/* File: armv5te/alt_stub.S */ 14427/* 14428 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14429 * any interesting requests and then jump to the real instruction 14430 * handler. Note that the call to dvmCheckInst is done as a tail call. 14431 */ 14432 adrl lr, dvmAsmInstructionStart + (95 * 64) 14433 mov r0, rPC @ arg0 14434 mov r1, rSELF @ arg1 14435 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14436 14437/* ------------------------------ */ 14438 .balign 64 14439.L_ALT_OP_SGET: /* 0x60 */ 14440/* File: armv5te/alt_stub.S */ 14441/* 14442 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14443 * any interesting requests and then jump to the real instruction 14444 * handler. Note that the call to dvmCheckInst is done as a tail call. 14445 */ 14446 adrl lr, dvmAsmInstructionStart + (96 * 64) 14447 mov r0, rPC @ arg0 14448 mov r1, rSELF @ arg1 14449 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14450 14451/* ------------------------------ */ 14452 .balign 64 14453.L_ALT_OP_SGET_WIDE: /* 0x61 */ 14454/* File: armv5te/alt_stub.S */ 14455/* 14456 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14457 * any interesting requests and then jump to the real instruction 14458 * handler. Note that the call to dvmCheckInst is done as a tail call. 14459 */ 14460 adrl lr, dvmAsmInstructionStart + (97 * 64) 14461 mov r0, rPC @ arg0 14462 mov r1, rSELF @ arg1 14463 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14464 14465/* ------------------------------ */ 14466 .balign 64 14467.L_ALT_OP_SGET_OBJECT: /* 0x62 */ 14468/* File: armv5te/alt_stub.S */ 14469/* 14470 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14471 * any interesting requests and then jump to the real instruction 14472 * handler. Note that the call to dvmCheckInst is done as a tail call. 14473 */ 14474 adrl lr, dvmAsmInstructionStart + (98 * 64) 14475 mov r0, rPC @ arg0 14476 mov r1, rSELF @ arg1 14477 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14478 14479/* ------------------------------ */ 14480 .balign 64 14481.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */ 14482/* File: armv5te/alt_stub.S */ 14483/* 14484 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14485 * any interesting requests and then jump to the real instruction 14486 * handler. Note that the call to dvmCheckInst is done as a tail call. 14487 */ 14488 adrl lr, dvmAsmInstructionStart + (99 * 64) 14489 mov r0, rPC @ arg0 14490 mov r1, rSELF @ arg1 14491 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14492 14493/* ------------------------------ */ 14494 .balign 64 14495.L_ALT_OP_SGET_BYTE: /* 0x64 */ 14496/* File: armv5te/alt_stub.S */ 14497/* 14498 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14499 * any interesting requests and then jump to the real instruction 14500 * handler. Note that the call to dvmCheckInst is done as a tail call. 14501 */ 14502 adrl lr, dvmAsmInstructionStart + (100 * 64) 14503 mov r0, rPC @ arg0 14504 mov r1, rSELF @ arg1 14505 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14506 14507/* ------------------------------ */ 14508 .balign 64 14509.L_ALT_OP_SGET_CHAR: /* 0x65 */ 14510/* File: armv5te/alt_stub.S */ 14511/* 14512 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14513 * any interesting requests and then jump to the real instruction 14514 * handler. Note that the call to dvmCheckInst is done as a tail call. 14515 */ 14516 adrl lr, dvmAsmInstructionStart + (101 * 64) 14517 mov r0, rPC @ arg0 14518 mov r1, rSELF @ arg1 14519 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14520 14521/* ------------------------------ */ 14522 .balign 64 14523.L_ALT_OP_SGET_SHORT: /* 0x66 */ 14524/* File: armv5te/alt_stub.S */ 14525/* 14526 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14527 * any interesting requests and then jump to the real instruction 14528 * handler. Note that the call to dvmCheckInst is done as a tail call. 14529 */ 14530 adrl lr, dvmAsmInstructionStart + (102 * 64) 14531 mov r0, rPC @ arg0 14532 mov r1, rSELF @ arg1 14533 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14534 14535/* ------------------------------ */ 14536 .balign 64 14537.L_ALT_OP_SPUT: /* 0x67 */ 14538/* File: armv5te/alt_stub.S */ 14539/* 14540 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14541 * any interesting requests and then jump to the real instruction 14542 * handler. Note that the call to dvmCheckInst is done as a tail call. 14543 */ 14544 adrl lr, dvmAsmInstructionStart + (103 * 64) 14545 mov r0, rPC @ arg0 14546 mov r1, rSELF @ arg1 14547 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14548 14549/* ------------------------------ */ 14550 .balign 64 14551.L_ALT_OP_SPUT_WIDE: /* 0x68 */ 14552/* File: armv5te/alt_stub.S */ 14553/* 14554 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14555 * any interesting requests and then jump to the real instruction 14556 * handler. Note that the call to dvmCheckInst is done as a tail call. 14557 */ 14558 adrl lr, dvmAsmInstructionStart + (104 * 64) 14559 mov r0, rPC @ arg0 14560 mov r1, rSELF @ arg1 14561 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14562 14563/* ------------------------------ */ 14564 .balign 64 14565.L_ALT_OP_SPUT_OBJECT: /* 0x69 */ 14566/* File: armv5te/alt_stub.S */ 14567/* 14568 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14569 * any interesting requests and then jump to the real instruction 14570 * handler. Note that the call to dvmCheckInst is done as a tail call. 14571 */ 14572 adrl lr, dvmAsmInstructionStart + (105 * 64) 14573 mov r0, rPC @ arg0 14574 mov r1, rSELF @ arg1 14575 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14576 14577/* ------------------------------ */ 14578 .balign 64 14579.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */ 14580/* File: armv5te/alt_stub.S */ 14581/* 14582 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14583 * any interesting requests and then jump to the real instruction 14584 * handler. Note that the call to dvmCheckInst is done as a tail call. 14585 */ 14586 adrl lr, dvmAsmInstructionStart + (106 * 64) 14587 mov r0, rPC @ arg0 14588 mov r1, rSELF @ arg1 14589 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14590 14591/* ------------------------------ */ 14592 .balign 64 14593.L_ALT_OP_SPUT_BYTE: /* 0x6b */ 14594/* File: armv5te/alt_stub.S */ 14595/* 14596 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14597 * any interesting requests and then jump to the real instruction 14598 * handler. Note that the call to dvmCheckInst is done as a tail call. 14599 */ 14600 adrl lr, dvmAsmInstructionStart + (107 * 64) 14601 mov r0, rPC @ arg0 14602 mov r1, rSELF @ arg1 14603 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14604 14605/* ------------------------------ */ 14606 .balign 64 14607.L_ALT_OP_SPUT_CHAR: /* 0x6c */ 14608/* File: armv5te/alt_stub.S */ 14609/* 14610 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14611 * any interesting requests and then jump to the real instruction 14612 * handler. Note that the call to dvmCheckInst is done as a tail call. 14613 */ 14614 adrl lr, dvmAsmInstructionStart + (108 * 64) 14615 mov r0, rPC @ arg0 14616 mov r1, rSELF @ arg1 14617 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14618 14619/* ------------------------------ */ 14620 .balign 64 14621.L_ALT_OP_SPUT_SHORT: /* 0x6d */ 14622/* File: armv5te/alt_stub.S */ 14623/* 14624 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14625 * any interesting requests and then jump to the real instruction 14626 * handler. Note that the call to dvmCheckInst is done as a tail call. 14627 */ 14628 adrl lr, dvmAsmInstructionStart + (109 * 64) 14629 mov r0, rPC @ arg0 14630 mov r1, rSELF @ arg1 14631 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14632 14633/* ------------------------------ */ 14634 .balign 64 14635.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */ 14636/* File: armv5te/alt_stub.S */ 14637/* 14638 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14639 * any interesting requests and then jump to the real instruction 14640 * handler. Note that the call to dvmCheckInst is done as a tail call. 14641 */ 14642 adrl lr, dvmAsmInstructionStart + (110 * 64) 14643 mov r0, rPC @ arg0 14644 mov r1, rSELF @ arg1 14645 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14646 14647/* ------------------------------ */ 14648 .balign 64 14649.L_ALT_OP_INVOKE_SUPER: /* 0x6f */ 14650/* File: armv5te/alt_stub.S */ 14651/* 14652 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14653 * any interesting requests and then jump to the real instruction 14654 * handler. Note that the call to dvmCheckInst is done as a tail call. 14655 */ 14656 adrl lr, dvmAsmInstructionStart + (111 * 64) 14657 mov r0, rPC @ arg0 14658 mov r1, rSELF @ arg1 14659 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14660 14661/* ------------------------------ */ 14662 .balign 64 14663.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */ 14664/* File: armv5te/alt_stub.S */ 14665/* 14666 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14667 * any interesting requests and then jump to the real instruction 14668 * handler. Note that the call to dvmCheckInst is done as a tail call. 14669 */ 14670 adrl lr, dvmAsmInstructionStart + (112 * 64) 14671 mov r0, rPC @ arg0 14672 mov r1, rSELF @ arg1 14673 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14674 14675/* ------------------------------ */ 14676 .balign 64 14677.L_ALT_OP_INVOKE_STATIC: /* 0x71 */ 14678/* File: armv5te/alt_stub.S */ 14679/* 14680 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14681 * any interesting requests and then jump to the real instruction 14682 * handler. Note that the call to dvmCheckInst is done as a tail call. 14683 */ 14684 adrl lr, dvmAsmInstructionStart + (113 * 64) 14685 mov r0, rPC @ arg0 14686 mov r1, rSELF @ arg1 14687 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14688 14689/* ------------------------------ */ 14690 .balign 64 14691.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */ 14692/* File: armv5te/alt_stub.S */ 14693/* 14694 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14695 * any interesting requests and then jump to the real instruction 14696 * handler. Note that the call to dvmCheckInst is done as a tail call. 14697 */ 14698 adrl lr, dvmAsmInstructionStart + (114 * 64) 14699 mov r0, rPC @ arg0 14700 mov r1, rSELF @ arg1 14701 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14702 14703/* ------------------------------ */ 14704 .balign 64 14705.L_ALT_OP_UNUSED_73: /* 0x73 */ 14706/* File: armv5te/alt_stub.S */ 14707/* 14708 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14709 * any interesting requests and then jump to the real instruction 14710 * handler. Note that the call to dvmCheckInst is done as a tail call. 14711 */ 14712 adrl lr, dvmAsmInstructionStart + (115 * 64) 14713 mov r0, rPC @ arg0 14714 mov r1, rSELF @ arg1 14715 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14716 14717/* ------------------------------ */ 14718 .balign 64 14719.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 14720/* File: armv5te/alt_stub.S */ 14721/* 14722 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14723 * any interesting requests and then jump to the real instruction 14724 * handler. Note that the call to dvmCheckInst is done as a tail call. 14725 */ 14726 adrl lr, dvmAsmInstructionStart + (116 * 64) 14727 mov r0, rPC @ arg0 14728 mov r1, rSELF @ arg1 14729 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14730 14731/* ------------------------------ */ 14732 .balign 64 14733.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 14734/* File: armv5te/alt_stub.S */ 14735/* 14736 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14737 * any interesting requests and then jump to the real instruction 14738 * handler. Note that the call to dvmCheckInst is done as a tail call. 14739 */ 14740 adrl lr, dvmAsmInstructionStart + (117 * 64) 14741 mov r0, rPC @ arg0 14742 mov r1, rSELF @ arg1 14743 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14744 14745/* ------------------------------ */ 14746 .balign 64 14747.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 14748/* File: armv5te/alt_stub.S */ 14749/* 14750 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14751 * any interesting requests and then jump to the real instruction 14752 * handler. Note that the call to dvmCheckInst is done as a tail call. 14753 */ 14754 adrl lr, dvmAsmInstructionStart + (118 * 64) 14755 mov r0, rPC @ arg0 14756 mov r1, rSELF @ arg1 14757 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14758 14759/* ------------------------------ */ 14760 .balign 64 14761.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 14762/* File: armv5te/alt_stub.S */ 14763/* 14764 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14765 * any interesting requests and then jump to the real instruction 14766 * handler. Note that the call to dvmCheckInst is done as a tail call. 14767 */ 14768 adrl lr, dvmAsmInstructionStart + (119 * 64) 14769 mov r0, rPC @ arg0 14770 mov r1, rSELF @ arg1 14771 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14772 14773/* ------------------------------ */ 14774 .balign 64 14775.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 14776/* File: armv5te/alt_stub.S */ 14777/* 14778 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14779 * any interesting requests and then jump to the real instruction 14780 * handler. Note that the call to dvmCheckInst is done as a tail call. 14781 */ 14782 adrl lr, dvmAsmInstructionStart + (120 * 64) 14783 mov r0, rPC @ arg0 14784 mov r1, rSELF @ arg1 14785 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14786 14787/* ------------------------------ */ 14788 .balign 64 14789.L_ALT_OP_UNUSED_79: /* 0x79 */ 14790/* File: armv5te/alt_stub.S */ 14791/* 14792 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14793 * any interesting requests and then jump to the real instruction 14794 * handler. Note that the call to dvmCheckInst is done as a tail call. 14795 */ 14796 adrl lr, dvmAsmInstructionStart + (121 * 64) 14797 mov r0, rPC @ arg0 14798 mov r1, rSELF @ arg1 14799 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14800 14801/* ------------------------------ */ 14802 .balign 64 14803.L_ALT_OP_UNUSED_7A: /* 0x7a */ 14804/* File: armv5te/alt_stub.S */ 14805/* 14806 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14807 * any interesting requests and then jump to the real instruction 14808 * handler. Note that the call to dvmCheckInst is done as a tail call. 14809 */ 14810 adrl lr, dvmAsmInstructionStart + (122 * 64) 14811 mov r0, rPC @ arg0 14812 mov r1, rSELF @ arg1 14813 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14814 14815/* ------------------------------ */ 14816 .balign 64 14817.L_ALT_OP_NEG_INT: /* 0x7b */ 14818/* File: armv5te/alt_stub.S */ 14819/* 14820 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14821 * any interesting requests and then jump to the real instruction 14822 * handler. Note that the call to dvmCheckInst is done as a tail call. 14823 */ 14824 adrl lr, dvmAsmInstructionStart + (123 * 64) 14825 mov r0, rPC @ arg0 14826 mov r1, rSELF @ arg1 14827 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14828 14829/* ------------------------------ */ 14830 .balign 64 14831.L_ALT_OP_NOT_INT: /* 0x7c */ 14832/* File: armv5te/alt_stub.S */ 14833/* 14834 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14835 * any interesting requests and then jump to the real instruction 14836 * handler. Note that the call to dvmCheckInst is done as a tail call. 14837 */ 14838 adrl lr, dvmAsmInstructionStart + (124 * 64) 14839 mov r0, rPC @ arg0 14840 mov r1, rSELF @ arg1 14841 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14842 14843/* ------------------------------ */ 14844 .balign 64 14845.L_ALT_OP_NEG_LONG: /* 0x7d */ 14846/* File: armv5te/alt_stub.S */ 14847/* 14848 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14849 * any interesting requests and then jump to the real instruction 14850 * handler. Note that the call to dvmCheckInst is done as a tail call. 14851 */ 14852 adrl lr, dvmAsmInstructionStart + (125 * 64) 14853 mov r0, rPC @ arg0 14854 mov r1, rSELF @ arg1 14855 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14856 14857/* ------------------------------ */ 14858 .balign 64 14859.L_ALT_OP_NOT_LONG: /* 0x7e */ 14860/* File: armv5te/alt_stub.S */ 14861/* 14862 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14863 * any interesting requests and then jump to the real instruction 14864 * handler. Note that the call to dvmCheckInst is done as a tail call. 14865 */ 14866 adrl lr, dvmAsmInstructionStart + (126 * 64) 14867 mov r0, rPC @ arg0 14868 mov r1, rSELF @ arg1 14869 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14870 14871/* ------------------------------ */ 14872 .balign 64 14873.L_ALT_OP_NEG_FLOAT: /* 0x7f */ 14874/* File: armv5te/alt_stub.S */ 14875/* 14876 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14877 * any interesting requests and then jump to the real instruction 14878 * handler. Note that the call to dvmCheckInst is done as a tail call. 14879 */ 14880 adrl lr, dvmAsmInstructionStart + (127 * 64) 14881 mov r0, rPC @ arg0 14882 mov r1, rSELF @ arg1 14883 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14884 14885/* ------------------------------ */ 14886 .balign 64 14887.L_ALT_OP_NEG_DOUBLE: /* 0x80 */ 14888/* File: armv5te/alt_stub.S */ 14889/* 14890 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14891 * any interesting requests and then jump to the real instruction 14892 * handler. Note that the call to dvmCheckInst is done as a tail call. 14893 */ 14894 adrl lr, dvmAsmInstructionStart + (128 * 64) 14895 mov r0, rPC @ arg0 14896 mov r1, rSELF @ arg1 14897 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14898 14899/* ------------------------------ */ 14900 .balign 64 14901.L_ALT_OP_INT_TO_LONG: /* 0x81 */ 14902/* File: armv5te/alt_stub.S */ 14903/* 14904 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14905 * any interesting requests and then jump to the real instruction 14906 * handler. Note that the call to dvmCheckInst is done as a tail call. 14907 */ 14908 adrl lr, dvmAsmInstructionStart + (129 * 64) 14909 mov r0, rPC @ arg0 14910 mov r1, rSELF @ arg1 14911 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14912 14913/* ------------------------------ */ 14914 .balign 64 14915.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */ 14916/* File: armv5te/alt_stub.S */ 14917/* 14918 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14919 * any interesting requests and then jump to the real instruction 14920 * handler. Note that the call to dvmCheckInst is done as a tail call. 14921 */ 14922 adrl lr, dvmAsmInstructionStart + (130 * 64) 14923 mov r0, rPC @ arg0 14924 mov r1, rSELF @ arg1 14925 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14926 14927/* ------------------------------ */ 14928 .balign 64 14929.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */ 14930/* File: armv5te/alt_stub.S */ 14931/* 14932 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14933 * any interesting requests and then jump to the real instruction 14934 * handler. Note that the call to dvmCheckInst is done as a tail call. 14935 */ 14936 adrl lr, dvmAsmInstructionStart + (131 * 64) 14937 mov r0, rPC @ arg0 14938 mov r1, rSELF @ arg1 14939 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14940 14941/* ------------------------------ */ 14942 .balign 64 14943.L_ALT_OP_LONG_TO_INT: /* 0x84 */ 14944/* File: armv5te/alt_stub.S */ 14945/* 14946 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14947 * any interesting requests and then jump to the real instruction 14948 * handler. Note that the call to dvmCheckInst is done as a tail call. 14949 */ 14950 adrl lr, dvmAsmInstructionStart + (132 * 64) 14951 mov r0, rPC @ arg0 14952 mov r1, rSELF @ arg1 14953 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14954 14955/* ------------------------------ */ 14956 .balign 64 14957.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */ 14958/* File: armv5te/alt_stub.S */ 14959/* 14960 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14961 * any interesting requests and then jump to the real instruction 14962 * handler. Note that the call to dvmCheckInst is done as a tail call. 14963 */ 14964 adrl lr, dvmAsmInstructionStart + (133 * 64) 14965 mov r0, rPC @ arg0 14966 mov r1, rSELF @ arg1 14967 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14968 14969/* ------------------------------ */ 14970 .balign 64 14971.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */ 14972/* File: armv5te/alt_stub.S */ 14973/* 14974 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14975 * any interesting requests and then jump to the real instruction 14976 * handler. Note that the call to dvmCheckInst is done as a tail call. 14977 */ 14978 adrl lr, dvmAsmInstructionStart + (134 * 64) 14979 mov r0, rPC @ arg0 14980 mov r1, rSELF @ arg1 14981 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14982 14983/* ------------------------------ */ 14984 .balign 64 14985.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */ 14986/* File: armv5te/alt_stub.S */ 14987/* 14988 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14989 * any interesting requests and then jump to the real instruction 14990 * handler. Note that the call to dvmCheckInst is done as a tail call. 14991 */ 14992 adrl lr, dvmAsmInstructionStart + (135 * 64) 14993 mov r0, rPC @ arg0 14994 mov r1, rSELF @ arg1 14995 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14996 14997/* ------------------------------ */ 14998 .balign 64 14999.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */ 15000/* File: armv5te/alt_stub.S */ 15001/* 15002 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15003 * any interesting requests and then jump to the real instruction 15004 * handler. Note that the call to dvmCheckInst is done as a tail call. 15005 */ 15006 adrl lr, dvmAsmInstructionStart + (136 * 64) 15007 mov r0, rPC @ arg0 15008 mov r1, rSELF @ arg1 15009 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15010 15011/* ------------------------------ */ 15012 .balign 64 15013.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 15014/* File: armv5te/alt_stub.S */ 15015/* 15016 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15017 * any interesting requests and then jump to the real instruction 15018 * handler. Note that the call to dvmCheckInst is done as a tail call. 15019 */ 15020 adrl lr, dvmAsmInstructionStart + (137 * 64) 15021 mov r0, rPC @ arg0 15022 mov r1, rSELF @ arg1 15023 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15024 15025/* ------------------------------ */ 15026 .balign 64 15027.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */ 15028/* File: armv5te/alt_stub.S */ 15029/* 15030 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15031 * any interesting requests and then jump to the real instruction 15032 * handler. Note that the call to dvmCheckInst is done as a tail call. 15033 */ 15034 adrl lr, dvmAsmInstructionStart + (138 * 64) 15035 mov r0, rPC @ arg0 15036 mov r1, rSELF @ arg1 15037 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15038 15039/* ------------------------------ */ 15040 .balign 64 15041.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */ 15042/* File: armv5te/alt_stub.S */ 15043/* 15044 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15045 * any interesting requests and then jump to the real instruction 15046 * handler. Note that the call to dvmCheckInst is done as a tail call. 15047 */ 15048 adrl lr, dvmAsmInstructionStart + (139 * 64) 15049 mov r0, rPC @ arg0 15050 mov r1, rSELF @ arg1 15051 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15052 15053/* ------------------------------ */ 15054 .balign 64 15055.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 15056/* File: armv5te/alt_stub.S */ 15057/* 15058 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15059 * any interesting requests and then jump to the real instruction 15060 * handler. Note that the call to dvmCheckInst is done as a tail call. 15061 */ 15062 adrl lr, dvmAsmInstructionStart + (140 * 64) 15063 mov r0, rPC @ arg0 15064 mov r1, rSELF @ arg1 15065 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15066 15067/* ------------------------------ */ 15068 .balign 64 15069.L_ALT_OP_INT_TO_BYTE: /* 0x8d */ 15070/* File: armv5te/alt_stub.S */ 15071/* 15072 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15073 * any interesting requests and then jump to the real instruction 15074 * handler. Note that the call to dvmCheckInst is done as a tail call. 15075 */ 15076 adrl lr, dvmAsmInstructionStart + (141 * 64) 15077 mov r0, rPC @ arg0 15078 mov r1, rSELF @ arg1 15079 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15080 15081/* ------------------------------ */ 15082 .balign 64 15083.L_ALT_OP_INT_TO_CHAR: /* 0x8e */ 15084/* File: armv5te/alt_stub.S */ 15085/* 15086 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15087 * any interesting requests and then jump to the real instruction 15088 * handler. Note that the call to dvmCheckInst is done as a tail call. 15089 */ 15090 adrl lr, dvmAsmInstructionStart + (142 * 64) 15091 mov r0, rPC @ arg0 15092 mov r1, rSELF @ arg1 15093 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15094 15095/* ------------------------------ */ 15096 .balign 64 15097.L_ALT_OP_INT_TO_SHORT: /* 0x8f */ 15098/* File: armv5te/alt_stub.S */ 15099/* 15100 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15101 * any interesting requests and then jump to the real instruction 15102 * handler. Note that the call to dvmCheckInst is done as a tail call. 15103 */ 15104 adrl lr, dvmAsmInstructionStart + (143 * 64) 15105 mov r0, rPC @ arg0 15106 mov r1, rSELF @ arg1 15107 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15108 15109/* ------------------------------ */ 15110 .balign 64 15111.L_ALT_OP_ADD_INT: /* 0x90 */ 15112/* File: armv5te/alt_stub.S */ 15113/* 15114 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15115 * any interesting requests and then jump to the real instruction 15116 * handler. Note that the call to dvmCheckInst is done as a tail call. 15117 */ 15118 adrl lr, dvmAsmInstructionStart + (144 * 64) 15119 mov r0, rPC @ arg0 15120 mov r1, rSELF @ arg1 15121 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15122 15123/* ------------------------------ */ 15124 .balign 64 15125.L_ALT_OP_SUB_INT: /* 0x91 */ 15126/* File: armv5te/alt_stub.S */ 15127/* 15128 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15129 * any interesting requests and then jump to the real instruction 15130 * handler. Note that the call to dvmCheckInst is done as a tail call. 15131 */ 15132 adrl lr, dvmAsmInstructionStart + (145 * 64) 15133 mov r0, rPC @ arg0 15134 mov r1, rSELF @ arg1 15135 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15136 15137/* ------------------------------ */ 15138 .balign 64 15139.L_ALT_OP_MUL_INT: /* 0x92 */ 15140/* File: armv5te/alt_stub.S */ 15141/* 15142 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15143 * any interesting requests and then jump to the real instruction 15144 * handler. Note that the call to dvmCheckInst is done as a tail call. 15145 */ 15146 adrl lr, dvmAsmInstructionStart + (146 * 64) 15147 mov r0, rPC @ arg0 15148 mov r1, rSELF @ arg1 15149 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15150 15151/* ------------------------------ */ 15152 .balign 64 15153.L_ALT_OP_DIV_INT: /* 0x93 */ 15154/* File: armv5te/alt_stub.S */ 15155/* 15156 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15157 * any interesting requests and then jump to the real instruction 15158 * handler. Note that the call to dvmCheckInst is done as a tail call. 15159 */ 15160 adrl lr, dvmAsmInstructionStart + (147 * 64) 15161 mov r0, rPC @ arg0 15162 mov r1, rSELF @ arg1 15163 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15164 15165/* ------------------------------ */ 15166 .balign 64 15167.L_ALT_OP_REM_INT: /* 0x94 */ 15168/* File: armv5te/alt_stub.S */ 15169/* 15170 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15171 * any interesting requests and then jump to the real instruction 15172 * handler. Note that the call to dvmCheckInst is done as a tail call. 15173 */ 15174 adrl lr, dvmAsmInstructionStart + (148 * 64) 15175 mov r0, rPC @ arg0 15176 mov r1, rSELF @ arg1 15177 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15178 15179/* ------------------------------ */ 15180 .balign 64 15181.L_ALT_OP_AND_INT: /* 0x95 */ 15182/* File: armv5te/alt_stub.S */ 15183/* 15184 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15185 * any interesting requests and then jump to the real instruction 15186 * handler. Note that the call to dvmCheckInst is done as a tail call. 15187 */ 15188 adrl lr, dvmAsmInstructionStart + (149 * 64) 15189 mov r0, rPC @ arg0 15190 mov r1, rSELF @ arg1 15191 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15192 15193/* ------------------------------ */ 15194 .balign 64 15195.L_ALT_OP_OR_INT: /* 0x96 */ 15196/* File: armv5te/alt_stub.S */ 15197/* 15198 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15199 * any interesting requests and then jump to the real instruction 15200 * handler. Note that the call to dvmCheckInst is done as a tail call. 15201 */ 15202 adrl lr, dvmAsmInstructionStart + (150 * 64) 15203 mov r0, rPC @ arg0 15204 mov r1, rSELF @ arg1 15205 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15206 15207/* ------------------------------ */ 15208 .balign 64 15209.L_ALT_OP_XOR_INT: /* 0x97 */ 15210/* File: armv5te/alt_stub.S */ 15211/* 15212 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15213 * any interesting requests and then jump to the real instruction 15214 * handler. Note that the call to dvmCheckInst is done as a tail call. 15215 */ 15216 adrl lr, dvmAsmInstructionStart + (151 * 64) 15217 mov r0, rPC @ arg0 15218 mov r1, rSELF @ arg1 15219 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15220 15221/* ------------------------------ */ 15222 .balign 64 15223.L_ALT_OP_SHL_INT: /* 0x98 */ 15224/* File: armv5te/alt_stub.S */ 15225/* 15226 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15227 * any interesting requests and then jump to the real instruction 15228 * handler. Note that the call to dvmCheckInst is done as a tail call. 15229 */ 15230 adrl lr, dvmAsmInstructionStart + (152 * 64) 15231 mov r0, rPC @ arg0 15232 mov r1, rSELF @ arg1 15233 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15234 15235/* ------------------------------ */ 15236 .balign 64 15237.L_ALT_OP_SHR_INT: /* 0x99 */ 15238/* File: armv5te/alt_stub.S */ 15239/* 15240 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15241 * any interesting requests and then jump to the real instruction 15242 * handler. Note that the call to dvmCheckInst is done as a tail call. 15243 */ 15244 adrl lr, dvmAsmInstructionStart + (153 * 64) 15245 mov r0, rPC @ arg0 15246 mov r1, rSELF @ arg1 15247 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15248 15249/* ------------------------------ */ 15250 .balign 64 15251.L_ALT_OP_USHR_INT: /* 0x9a */ 15252/* File: armv5te/alt_stub.S */ 15253/* 15254 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15255 * any interesting requests and then jump to the real instruction 15256 * handler. Note that the call to dvmCheckInst is done as a tail call. 15257 */ 15258 adrl lr, dvmAsmInstructionStart + (154 * 64) 15259 mov r0, rPC @ arg0 15260 mov r1, rSELF @ arg1 15261 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15262 15263/* ------------------------------ */ 15264 .balign 64 15265.L_ALT_OP_ADD_LONG: /* 0x9b */ 15266/* File: armv5te/alt_stub.S */ 15267/* 15268 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15269 * any interesting requests and then jump to the real instruction 15270 * handler. Note that the call to dvmCheckInst is done as a tail call. 15271 */ 15272 adrl lr, dvmAsmInstructionStart + (155 * 64) 15273 mov r0, rPC @ arg0 15274 mov r1, rSELF @ arg1 15275 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15276 15277/* ------------------------------ */ 15278 .balign 64 15279.L_ALT_OP_SUB_LONG: /* 0x9c */ 15280/* File: armv5te/alt_stub.S */ 15281/* 15282 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15283 * any interesting requests and then jump to the real instruction 15284 * handler. Note that the call to dvmCheckInst is done as a tail call. 15285 */ 15286 adrl lr, dvmAsmInstructionStart + (156 * 64) 15287 mov r0, rPC @ arg0 15288 mov r1, rSELF @ arg1 15289 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15290 15291/* ------------------------------ */ 15292 .balign 64 15293.L_ALT_OP_MUL_LONG: /* 0x9d */ 15294/* File: armv5te/alt_stub.S */ 15295/* 15296 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15297 * any interesting requests and then jump to the real instruction 15298 * handler. Note that the call to dvmCheckInst is done as a tail call. 15299 */ 15300 adrl lr, dvmAsmInstructionStart + (157 * 64) 15301 mov r0, rPC @ arg0 15302 mov r1, rSELF @ arg1 15303 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15304 15305/* ------------------------------ */ 15306 .balign 64 15307.L_ALT_OP_DIV_LONG: /* 0x9e */ 15308/* File: armv5te/alt_stub.S */ 15309/* 15310 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15311 * any interesting requests and then jump to the real instruction 15312 * handler. Note that the call to dvmCheckInst is done as a tail call. 15313 */ 15314 adrl lr, dvmAsmInstructionStart + (158 * 64) 15315 mov r0, rPC @ arg0 15316 mov r1, rSELF @ arg1 15317 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15318 15319/* ------------------------------ */ 15320 .balign 64 15321.L_ALT_OP_REM_LONG: /* 0x9f */ 15322/* File: armv5te/alt_stub.S */ 15323/* 15324 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15325 * any interesting requests and then jump to the real instruction 15326 * handler. Note that the call to dvmCheckInst is done as a tail call. 15327 */ 15328 adrl lr, dvmAsmInstructionStart + (159 * 64) 15329 mov r0, rPC @ arg0 15330 mov r1, rSELF @ arg1 15331 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15332 15333/* ------------------------------ */ 15334 .balign 64 15335.L_ALT_OP_AND_LONG: /* 0xa0 */ 15336/* File: armv5te/alt_stub.S */ 15337/* 15338 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15339 * any interesting requests and then jump to the real instruction 15340 * handler. Note that the call to dvmCheckInst is done as a tail call. 15341 */ 15342 adrl lr, dvmAsmInstructionStart + (160 * 64) 15343 mov r0, rPC @ arg0 15344 mov r1, rSELF @ arg1 15345 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15346 15347/* ------------------------------ */ 15348 .balign 64 15349.L_ALT_OP_OR_LONG: /* 0xa1 */ 15350/* File: armv5te/alt_stub.S */ 15351/* 15352 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15353 * any interesting requests and then jump to the real instruction 15354 * handler. Note that the call to dvmCheckInst is done as a tail call. 15355 */ 15356 adrl lr, dvmAsmInstructionStart + (161 * 64) 15357 mov r0, rPC @ arg0 15358 mov r1, rSELF @ arg1 15359 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15360 15361/* ------------------------------ */ 15362 .balign 64 15363.L_ALT_OP_XOR_LONG: /* 0xa2 */ 15364/* File: armv5te/alt_stub.S */ 15365/* 15366 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15367 * any interesting requests and then jump to the real instruction 15368 * handler. Note that the call to dvmCheckInst is done as a tail call. 15369 */ 15370 adrl lr, dvmAsmInstructionStart + (162 * 64) 15371 mov r0, rPC @ arg0 15372 mov r1, rSELF @ arg1 15373 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15374 15375/* ------------------------------ */ 15376 .balign 64 15377.L_ALT_OP_SHL_LONG: /* 0xa3 */ 15378/* File: armv5te/alt_stub.S */ 15379/* 15380 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15381 * any interesting requests and then jump to the real instruction 15382 * handler. Note that the call to dvmCheckInst is done as a tail call. 15383 */ 15384 adrl lr, dvmAsmInstructionStart + (163 * 64) 15385 mov r0, rPC @ arg0 15386 mov r1, rSELF @ arg1 15387 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15388 15389/* ------------------------------ */ 15390 .balign 64 15391.L_ALT_OP_SHR_LONG: /* 0xa4 */ 15392/* File: armv5te/alt_stub.S */ 15393/* 15394 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15395 * any interesting requests and then jump to the real instruction 15396 * handler. Note that the call to dvmCheckInst is done as a tail call. 15397 */ 15398 adrl lr, dvmAsmInstructionStart + (164 * 64) 15399 mov r0, rPC @ arg0 15400 mov r1, rSELF @ arg1 15401 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15402 15403/* ------------------------------ */ 15404 .balign 64 15405.L_ALT_OP_USHR_LONG: /* 0xa5 */ 15406/* File: armv5te/alt_stub.S */ 15407/* 15408 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15409 * any interesting requests and then jump to the real instruction 15410 * handler. Note that the call to dvmCheckInst is done as a tail call. 15411 */ 15412 adrl lr, dvmAsmInstructionStart + (165 * 64) 15413 mov r0, rPC @ arg0 15414 mov r1, rSELF @ arg1 15415 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15416 15417/* ------------------------------ */ 15418 .balign 64 15419.L_ALT_OP_ADD_FLOAT: /* 0xa6 */ 15420/* File: armv5te/alt_stub.S */ 15421/* 15422 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15423 * any interesting requests and then jump to the real instruction 15424 * handler. Note that the call to dvmCheckInst is done as a tail call. 15425 */ 15426 adrl lr, dvmAsmInstructionStart + (166 * 64) 15427 mov r0, rPC @ arg0 15428 mov r1, rSELF @ arg1 15429 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15430 15431/* ------------------------------ */ 15432 .balign 64 15433.L_ALT_OP_SUB_FLOAT: /* 0xa7 */ 15434/* File: armv5te/alt_stub.S */ 15435/* 15436 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15437 * any interesting requests and then jump to the real instruction 15438 * handler. Note that the call to dvmCheckInst is done as a tail call. 15439 */ 15440 adrl lr, dvmAsmInstructionStart + (167 * 64) 15441 mov r0, rPC @ arg0 15442 mov r1, rSELF @ arg1 15443 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15444 15445/* ------------------------------ */ 15446 .balign 64 15447.L_ALT_OP_MUL_FLOAT: /* 0xa8 */ 15448/* File: armv5te/alt_stub.S */ 15449/* 15450 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15451 * any interesting requests and then jump to the real instruction 15452 * handler. Note that the call to dvmCheckInst is done as a tail call. 15453 */ 15454 adrl lr, dvmAsmInstructionStart + (168 * 64) 15455 mov r0, rPC @ arg0 15456 mov r1, rSELF @ arg1 15457 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15458 15459/* ------------------------------ */ 15460 .balign 64 15461.L_ALT_OP_DIV_FLOAT: /* 0xa9 */ 15462/* File: armv5te/alt_stub.S */ 15463/* 15464 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15465 * any interesting requests and then jump to the real instruction 15466 * handler. Note that the call to dvmCheckInst is done as a tail call. 15467 */ 15468 adrl lr, dvmAsmInstructionStart + (169 * 64) 15469 mov r0, rPC @ arg0 15470 mov r1, rSELF @ arg1 15471 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15472 15473/* ------------------------------ */ 15474 .balign 64 15475.L_ALT_OP_REM_FLOAT: /* 0xaa */ 15476/* File: armv5te/alt_stub.S */ 15477/* 15478 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15479 * any interesting requests and then jump to the real instruction 15480 * handler. Note that the call to dvmCheckInst is done as a tail call. 15481 */ 15482 adrl lr, dvmAsmInstructionStart + (170 * 64) 15483 mov r0, rPC @ arg0 15484 mov r1, rSELF @ arg1 15485 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15486 15487/* ------------------------------ */ 15488 .balign 64 15489.L_ALT_OP_ADD_DOUBLE: /* 0xab */ 15490/* File: armv5te/alt_stub.S */ 15491/* 15492 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15493 * any interesting requests and then jump to the real instruction 15494 * handler. Note that the call to dvmCheckInst is done as a tail call. 15495 */ 15496 adrl lr, dvmAsmInstructionStart + (171 * 64) 15497 mov r0, rPC @ arg0 15498 mov r1, rSELF @ arg1 15499 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15500 15501/* ------------------------------ */ 15502 .balign 64 15503.L_ALT_OP_SUB_DOUBLE: /* 0xac */ 15504/* File: armv5te/alt_stub.S */ 15505/* 15506 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15507 * any interesting requests and then jump to the real instruction 15508 * handler. Note that the call to dvmCheckInst is done as a tail call. 15509 */ 15510 adrl lr, dvmAsmInstructionStart + (172 * 64) 15511 mov r0, rPC @ arg0 15512 mov r1, rSELF @ arg1 15513 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15514 15515/* ------------------------------ */ 15516 .balign 64 15517.L_ALT_OP_MUL_DOUBLE: /* 0xad */ 15518/* File: armv5te/alt_stub.S */ 15519/* 15520 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15521 * any interesting requests and then jump to the real instruction 15522 * handler. Note that the call to dvmCheckInst is done as a tail call. 15523 */ 15524 adrl lr, dvmAsmInstructionStart + (173 * 64) 15525 mov r0, rPC @ arg0 15526 mov r1, rSELF @ arg1 15527 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15528 15529/* ------------------------------ */ 15530 .balign 64 15531.L_ALT_OP_DIV_DOUBLE: /* 0xae */ 15532/* File: armv5te/alt_stub.S */ 15533/* 15534 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15535 * any interesting requests and then jump to the real instruction 15536 * handler. Note that the call to dvmCheckInst is done as a tail call. 15537 */ 15538 adrl lr, dvmAsmInstructionStart + (174 * 64) 15539 mov r0, rPC @ arg0 15540 mov r1, rSELF @ arg1 15541 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15542 15543/* ------------------------------ */ 15544 .balign 64 15545.L_ALT_OP_REM_DOUBLE: /* 0xaf */ 15546/* File: armv5te/alt_stub.S */ 15547/* 15548 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15549 * any interesting requests and then jump to the real instruction 15550 * handler. Note that the call to dvmCheckInst is done as a tail call. 15551 */ 15552 adrl lr, dvmAsmInstructionStart + (175 * 64) 15553 mov r0, rPC @ arg0 15554 mov r1, rSELF @ arg1 15555 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15556 15557/* ------------------------------ */ 15558 .balign 64 15559.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */ 15560/* File: armv5te/alt_stub.S */ 15561/* 15562 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15563 * any interesting requests and then jump to the real instruction 15564 * handler. Note that the call to dvmCheckInst is done as a tail call. 15565 */ 15566 adrl lr, dvmAsmInstructionStart + (176 * 64) 15567 mov r0, rPC @ arg0 15568 mov r1, rSELF @ arg1 15569 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15570 15571/* ------------------------------ */ 15572 .balign 64 15573.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */ 15574/* File: armv5te/alt_stub.S */ 15575/* 15576 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15577 * any interesting requests and then jump to the real instruction 15578 * handler. Note that the call to dvmCheckInst is done as a tail call. 15579 */ 15580 adrl lr, dvmAsmInstructionStart + (177 * 64) 15581 mov r0, rPC @ arg0 15582 mov r1, rSELF @ arg1 15583 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15584 15585/* ------------------------------ */ 15586 .balign 64 15587.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */ 15588/* File: armv5te/alt_stub.S */ 15589/* 15590 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15591 * any interesting requests and then jump to the real instruction 15592 * handler. Note that the call to dvmCheckInst is done as a tail call. 15593 */ 15594 adrl lr, dvmAsmInstructionStart + (178 * 64) 15595 mov r0, rPC @ arg0 15596 mov r1, rSELF @ arg1 15597 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15598 15599/* ------------------------------ */ 15600 .balign 64 15601.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */ 15602/* File: armv5te/alt_stub.S */ 15603/* 15604 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15605 * any interesting requests and then jump to the real instruction 15606 * handler. Note that the call to dvmCheckInst is done as a tail call. 15607 */ 15608 adrl lr, dvmAsmInstructionStart + (179 * 64) 15609 mov r0, rPC @ arg0 15610 mov r1, rSELF @ arg1 15611 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15612 15613/* ------------------------------ */ 15614 .balign 64 15615.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */ 15616/* File: armv5te/alt_stub.S */ 15617/* 15618 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15619 * any interesting requests and then jump to the real instruction 15620 * handler. Note that the call to dvmCheckInst is done as a tail call. 15621 */ 15622 adrl lr, dvmAsmInstructionStart + (180 * 64) 15623 mov r0, rPC @ arg0 15624 mov r1, rSELF @ arg1 15625 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15626 15627/* ------------------------------ */ 15628 .balign 64 15629.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */ 15630/* File: armv5te/alt_stub.S */ 15631/* 15632 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15633 * any interesting requests and then jump to the real instruction 15634 * handler. Note that the call to dvmCheckInst is done as a tail call. 15635 */ 15636 adrl lr, dvmAsmInstructionStart + (181 * 64) 15637 mov r0, rPC @ arg0 15638 mov r1, rSELF @ arg1 15639 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15640 15641/* ------------------------------ */ 15642 .balign 64 15643.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */ 15644/* File: armv5te/alt_stub.S */ 15645/* 15646 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15647 * any interesting requests and then jump to the real instruction 15648 * handler. Note that the call to dvmCheckInst is done as a tail call. 15649 */ 15650 adrl lr, dvmAsmInstructionStart + (182 * 64) 15651 mov r0, rPC @ arg0 15652 mov r1, rSELF @ arg1 15653 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15654 15655/* ------------------------------ */ 15656 .balign 64 15657.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */ 15658/* File: armv5te/alt_stub.S */ 15659/* 15660 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15661 * any interesting requests and then jump to the real instruction 15662 * handler. Note that the call to dvmCheckInst is done as a tail call. 15663 */ 15664 adrl lr, dvmAsmInstructionStart + (183 * 64) 15665 mov r0, rPC @ arg0 15666 mov r1, rSELF @ arg1 15667 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15668 15669/* ------------------------------ */ 15670 .balign 64 15671.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */ 15672/* File: armv5te/alt_stub.S */ 15673/* 15674 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15675 * any interesting requests and then jump to the real instruction 15676 * handler. Note that the call to dvmCheckInst is done as a tail call. 15677 */ 15678 adrl lr, dvmAsmInstructionStart + (184 * 64) 15679 mov r0, rPC @ arg0 15680 mov r1, rSELF @ arg1 15681 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15682 15683/* ------------------------------ */ 15684 .balign 64 15685.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */ 15686/* File: armv5te/alt_stub.S */ 15687/* 15688 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15689 * any interesting requests and then jump to the real instruction 15690 * handler. Note that the call to dvmCheckInst is done as a tail call. 15691 */ 15692 adrl lr, dvmAsmInstructionStart + (185 * 64) 15693 mov r0, rPC @ arg0 15694 mov r1, rSELF @ arg1 15695 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15696 15697/* ------------------------------ */ 15698 .balign 64 15699.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */ 15700/* File: armv5te/alt_stub.S */ 15701/* 15702 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15703 * any interesting requests and then jump to the real instruction 15704 * handler. Note that the call to dvmCheckInst is done as a tail call. 15705 */ 15706 adrl lr, dvmAsmInstructionStart + (186 * 64) 15707 mov r0, rPC @ arg0 15708 mov r1, rSELF @ arg1 15709 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15710 15711/* ------------------------------ */ 15712 .balign 64 15713.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */ 15714/* File: armv5te/alt_stub.S */ 15715/* 15716 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15717 * any interesting requests and then jump to the real instruction 15718 * handler. Note that the call to dvmCheckInst is done as a tail call. 15719 */ 15720 adrl lr, dvmAsmInstructionStart + (187 * 64) 15721 mov r0, rPC @ arg0 15722 mov r1, rSELF @ arg1 15723 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15724 15725/* ------------------------------ */ 15726 .balign 64 15727.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */ 15728/* File: armv5te/alt_stub.S */ 15729/* 15730 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15731 * any interesting requests and then jump to the real instruction 15732 * handler. Note that the call to dvmCheckInst is done as a tail call. 15733 */ 15734 adrl lr, dvmAsmInstructionStart + (188 * 64) 15735 mov r0, rPC @ arg0 15736 mov r1, rSELF @ arg1 15737 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15738 15739/* ------------------------------ */ 15740 .balign 64 15741.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */ 15742/* File: armv5te/alt_stub.S */ 15743/* 15744 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15745 * any interesting requests and then jump to the real instruction 15746 * handler. Note that the call to dvmCheckInst is done as a tail call. 15747 */ 15748 adrl lr, dvmAsmInstructionStart + (189 * 64) 15749 mov r0, rPC @ arg0 15750 mov r1, rSELF @ arg1 15751 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15752 15753/* ------------------------------ */ 15754 .balign 64 15755.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */ 15756/* File: armv5te/alt_stub.S */ 15757/* 15758 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15759 * any interesting requests and then jump to the real instruction 15760 * handler. Note that the call to dvmCheckInst is done as a tail call. 15761 */ 15762 adrl lr, dvmAsmInstructionStart + (190 * 64) 15763 mov r0, rPC @ arg0 15764 mov r1, rSELF @ arg1 15765 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15766 15767/* ------------------------------ */ 15768 .balign 64 15769.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */ 15770/* File: armv5te/alt_stub.S */ 15771/* 15772 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15773 * any interesting requests and then jump to the real instruction 15774 * handler. Note that the call to dvmCheckInst is done as a tail call. 15775 */ 15776 adrl lr, dvmAsmInstructionStart + (191 * 64) 15777 mov r0, rPC @ arg0 15778 mov r1, rSELF @ arg1 15779 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15780 15781/* ------------------------------ */ 15782 .balign 64 15783.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */ 15784/* File: armv5te/alt_stub.S */ 15785/* 15786 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15787 * any interesting requests and then jump to the real instruction 15788 * handler. Note that the call to dvmCheckInst is done as a tail call. 15789 */ 15790 adrl lr, dvmAsmInstructionStart + (192 * 64) 15791 mov r0, rPC @ arg0 15792 mov r1, rSELF @ arg1 15793 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15794 15795/* ------------------------------ */ 15796 .balign 64 15797.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */ 15798/* File: armv5te/alt_stub.S */ 15799/* 15800 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15801 * any interesting requests and then jump to the real instruction 15802 * handler. Note that the call to dvmCheckInst is done as a tail call. 15803 */ 15804 adrl lr, dvmAsmInstructionStart + (193 * 64) 15805 mov r0, rPC @ arg0 15806 mov r1, rSELF @ arg1 15807 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15808 15809/* ------------------------------ */ 15810 .balign 64 15811.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */ 15812/* File: armv5te/alt_stub.S */ 15813/* 15814 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15815 * any interesting requests and then jump to the real instruction 15816 * handler. Note that the call to dvmCheckInst is done as a tail call. 15817 */ 15818 adrl lr, dvmAsmInstructionStart + (194 * 64) 15819 mov r0, rPC @ arg0 15820 mov r1, rSELF @ arg1 15821 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15822 15823/* ------------------------------ */ 15824 .balign 64 15825.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */ 15826/* File: armv5te/alt_stub.S */ 15827/* 15828 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15829 * any interesting requests and then jump to the real instruction 15830 * handler. Note that the call to dvmCheckInst is done as a tail call. 15831 */ 15832 adrl lr, dvmAsmInstructionStart + (195 * 64) 15833 mov r0, rPC @ arg0 15834 mov r1, rSELF @ arg1 15835 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15836 15837/* ------------------------------ */ 15838 .balign 64 15839.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */ 15840/* File: armv5te/alt_stub.S */ 15841/* 15842 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15843 * any interesting requests and then jump to the real instruction 15844 * handler. Note that the call to dvmCheckInst is done as a tail call. 15845 */ 15846 adrl lr, dvmAsmInstructionStart + (196 * 64) 15847 mov r0, rPC @ arg0 15848 mov r1, rSELF @ arg1 15849 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15850 15851/* ------------------------------ */ 15852 .balign 64 15853.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */ 15854/* File: armv5te/alt_stub.S */ 15855/* 15856 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15857 * any interesting requests and then jump to the real instruction 15858 * handler. Note that the call to dvmCheckInst is done as a tail call. 15859 */ 15860 adrl lr, dvmAsmInstructionStart + (197 * 64) 15861 mov r0, rPC @ arg0 15862 mov r1, rSELF @ arg1 15863 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15864 15865/* ------------------------------ */ 15866 .balign 64 15867.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 15868/* File: armv5te/alt_stub.S */ 15869/* 15870 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15871 * any interesting requests and then jump to the real instruction 15872 * handler. Note that the call to dvmCheckInst is done as a tail call. 15873 */ 15874 adrl lr, dvmAsmInstructionStart + (198 * 64) 15875 mov r0, rPC @ arg0 15876 mov r1, rSELF @ arg1 15877 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15878 15879/* ------------------------------ */ 15880 .balign 64 15881.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 15882/* File: armv5te/alt_stub.S */ 15883/* 15884 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15885 * any interesting requests and then jump to the real instruction 15886 * handler. Note that the call to dvmCheckInst is done as a tail call. 15887 */ 15888 adrl lr, dvmAsmInstructionStart + (199 * 64) 15889 mov r0, rPC @ arg0 15890 mov r1, rSELF @ arg1 15891 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15892 15893/* ------------------------------ */ 15894 .balign 64 15895.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 15896/* File: armv5te/alt_stub.S */ 15897/* 15898 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15899 * any interesting requests and then jump to the real instruction 15900 * handler. Note that the call to dvmCheckInst is done as a tail call. 15901 */ 15902 adrl lr, dvmAsmInstructionStart + (200 * 64) 15903 mov r0, rPC @ arg0 15904 mov r1, rSELF @ arg1 15905 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15906 15907/* ------------------------------ */ 15908 .balign 64 15909.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 15910/* File: armv5te/alt_stub.S */ 15911/* 15912 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15913 * any interesting requests and then jump to the real instruction 15914 * handler. Note that the call to dvmCheckInst is done as a tail call. 15915 */ 15916 adrl lr, dvmAsmInstructionStart + (201 * 64) 15917 mov r0, rPC @ arg0 15918 mov r1, rSELF @ arg1 15919 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15920 15921/* ------------------------------ */ 15922 .balign 64 15923.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */ 15924/* File: armv5te/alt_stub.S */ 15925/* 15926 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15927 * any interesting requests and then jump to the real instruction 15928 * handler. Note that the call to dvmCheckInst is done as a tail call. 15929 */ 15930 adrl lr, dvmAsmInstructionStart + (202 * 64) 15931 mov r0, rPC @ arg0 15932 mov r1, rSELF @ arg1 15933 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15934 15935/* ------------------------------ */ 15936 .balign 64 15937.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 15938/* File: armv5te/alt_stub.S */ 15939/* 15940 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15941 * any interesting requests and then jump to the real instruction 15942 * handler. Note that the call to dvmCheckInst is done as a tail call. 15943 */ 15944 adrl lr, dvmAsmInstructionStart + (203 * 64) 15945 mov r0, rPC @ arg0 15946 mov r1, rSELF @ arg1 15947 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15948 15949/* ------------------------------ */ 15950 .balign 64 15951.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 15952/* File: armv5te/alt_stub.S */ 15953/* 15954 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15955 * any interesting requests and then jump to the real instruction 15956 * handler. Note that the call to dvmCheckInst is done as a tail call. 15957 */ 15958 adrl lr, dvmAsmInstructionStart + (204 * 64) 15959 mov r0, rPC @ arg0 15960 mov r1, rSELF @ arg1 15961 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15962 15963/* ------------------------------ */ 15964 .balign 64 15965.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 15966/* File: armv5te/alt_stub.S */ 15967/* 15968 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15969 * any interesting requests and then jump to the real instruction 15970 * handler. Note that the call to dvmCheckInst is done as a tail call. 15971 */ 15972 adrl lr, dvmAsmInstructionStart + (205 * 64) 15973 mov r0, rPC @ arg0 15974 mov r1, rSELF @ arg1 15975 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15976 15977/* ------------------------------ */ 15978 .balign 64 15979.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 15980/* File: armv5te/alt_stub.S */ 15981/* 15982 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15983 * any interesting requests and then jump to the real instruction 15984 * handler. Note that the call to dvmCheckInst is done as a tail call. 15985 */ 15986 adrl lr, dvmAsmInstructionStart + (206 * 64) 15987 mov r0, rPC @ arg0 15988 mov r1, rSELF @ arg1 15989 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15990 15991/* ------------------------------ */ 15992 .balign 64 15993.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 15994/* File: armv5te/alt_stub.S */ 15995/* 15996 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15997 * any interesting requests and then jump to the real instruction 15998 * handler. Note that the call to dvmCheckInst is done as a tail call. 15999 */ 16000 adrl lr, dvmAsmInstructionStart + (207 * 64) 16001 mov r0, rPC @ arg0 16002 mov r1, rSELF @ arg1 16003 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16004 16005/* ------------------------------ */ 16006 .balign 64 16007.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */ 16008/* File: armv5te/alt_stub.S */ 16009/* 16010 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16011 * any interesting requests and then jump to the real instruction 16012 * handler. Note that the call to dvmCheckInst is done as a tail call. 16013 */ 16014 adrl lr, dvmAsmInstructionStart + (208 * 64) 16015 mov r0, rPC @ arg0 16016 mov r1, rSELF @ arg1 16017 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16018 16019/* ------------------------------ */ 16020 .balign 64 16021.L_ALT_OP_RSUB_INT: /* 0xd1 */ 16022/* File: armv5te/alt_stub.S */ 16023/* 16024 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16025 * any interesting requests and then jump to the real instruction 16026 * handler. Note that the call to dvmCheckInst is done as a tail call. 16027 */ 16028 adrl lr, dvmAsmInstructionStart + (209 * 64) 16029 mov r0, rPC @ arg0 16030 mov r1, rSELF @ arg1 16031 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16032 16033/* ------------------------------ */ 16034 .balign 64 16035.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */ 16036/* File: armv5te/alt_stub.S */ 16037/* 16038 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16039 * any interesting requests and then jump to the real instruction 16040 * handler. Note that the call to dvmCheckInst is done as a tail call. 16041 */ 16042 adrl lr, dvmAsmInstructionStart + (210 * 64) 16043 mov r0, rPC @ arg0 16044 mov r1, rSELF @ arg1 16045 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16046 16047/* ------------------------------ */ 16048 .balign 64 16049.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */ 16050/* File: armv5te/alt_stub.S */ 16051/* 16052 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16053 * any interesting requests and then jump to the real instruction 16054 * handler. Note that the call to dvmCheckInst is done as a tail call. 16055 */ 16056 adrl lr, dvmAsmInstructionStart + (211 * 64) 16057 mov r0, rPC @ arg0 16058 mov r1, rSELF @ arg1 16059 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16060 16061/* ------------------------------ */ 16062 .balign 64 16063.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */ 16064/* File: armv5te/alt_stub.S */ 16065/* 16066 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16067 * any interesting requests and then jump to the real instruction 16068 * handler. Note that the call to dvmCheckInst is done as a tail call. 16069 */ 16070 adrl lr, dvmAsmInstructionStart + (212 * 64) 16071 mov r0, rPC @ arg0 16072 mov r1, rSELF @ arg1 16073 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16074 16075/* ------------------------------ */ 16076 .balign 64 16077.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */ 16078/* File: armv5te/alt_stub.S */ 16079/* 16080 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16081 * any interesting requests and then jump to the real instruction 16082 * handler. Note that the call to dvmCheckInst is done as a tail call. 16083 */ 16084 adrl lr, dvmAsmInstructionStart + (213 * 64) 16085 mov r0, rPC @ arg0 16086 mov r1, rSELF @ arg1 16087 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16088 16089/* ------------------------------ */ 16090 .balign 64 16091.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */ 16092/* File: armv5te/alt_stub.S */ 16093/* 16094 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16095 * any interesting requests and then jump to the real instruction 16096 * handler. Note that the call to dvmCheckInst is done as a tail call. 16097 */ 16098 adrl lr, dvmAsmInstructionStart + (214 * 64) 16099 mov r0, rPC @ arg0 16100 mov r1, rSELF @ arg1 16101 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16102 16103/* ------------------------------ */ 16104 .balign 64 16105.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */ 16106/* File: armv5te/alt_stub.S */ 16107/* 16108 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16109 * any interesting requests and then jump to the real instruction 16110 * handler. Note that the call to dvmCheckInst is done as a tail call. 16111 */ 16112 adrl lr, dvmAsmInstructionStart + (215 * 64) 16113 mov r0, rPC @ arg0 16114 mov r1, rSELF @ arg1 16115 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16116 16117/* ------------------------------ */ 16118 .balign 64 16119.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */ 16120/* File: armv5te/alt_stub.S */ 16121/* 16122 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16123 * any interesting requests and then jump to the real instruction 16124 * handler. Note that the call to dvmCheckInst is done as a tail call. 16125 */ 16126 adrl lr, dvmAsmInstructionStart + (216 * 64) 16127 mov r0, rPC @ arg0 16128 mov r1, rSELF @ arg1 16129 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16130 16131/* ------------------------------ */ 16132 .balign 64 16133.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */ 16134/* File: armv5te/alt_stub.S */ 16135/* 16136 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16137 * any interesting requests and then jump to the real instruction 16138 * handler. Note that the call to dvmCheckInst is done as a tail call. 16139 */ 16140 adrl lr, dvmAsmInstructionStart + (217 * 64) 16141 mov r0, rPC @ arg0 16142 mov r1, rSELF @ arg1 16143 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16144 16145/* ------------------------------ */ 16146 .balign 64 16147.L_ALT_OP_MUL_INT_LIT8: /* 0xda */ 16148/* File: armv5te/alt_stub.S */ 16149/* 16150 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16151 * any interesting requests and then jump to the real instruction 16152 * handler. Note that the call to dvmCheckInst is done as a tail call. 16153 */ 16154 adrl lr, dvmAsmInstructionStart + (218 * 64) 16155 mov r0, rPC @ arg0 16156 mov r1, rSELF @ arg1 16157 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16158 16159/* ------------------------------ */ 16160 .balign 64 16161.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */ 16162/* File: armv5te/alt_stub.S */ 16163/* 16164 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16165 * any interesting requests and then jump to the real instruction 16166 * handler. Note that the call to dvmCheckInst is done as a tail call. 16167 */ 16168 adrl lr, dvmAsmInstructionStart + (219 * 64) 16169 mov r0, rPC @ arg0 16170 mov r1, rSELF @ arg1 16171 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16172 16173/* ------------------------------ */ 16174 .balign 64 16175.L_ALT_OP_REM_INT_LIT8: /* 0xdc */ 16176/* File: armv5te/alt_stub.S */ 16177/* 16178 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16179 * any interesting requests and then jump to the real instruction 16180 * handler. Note that the call to dvmCheckInst is done as a tail call. 16181 */ 16182 adrl lr, dvmAsmInstructionStart + (220 * 64) 16183 mov r0, rPC @ arg0 16184 mov r1, rSELF @ arg1 16185 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16186 16187/* ------------------------------ */ 16188 .balign 64 16189.L_ALT_OP_AND_INT_LIT8: /* 0xdd */ 16190/* File: armv5te/alt_stub.S */ 16191/* 16192 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16193 * any interesting requests and then jump to the real instruction 16194 * handler. Note that the call to dvmCheckInst is done as a tail call. 16195 */ 16196 adrl lr, dvmAsmInstructionStart + (221 * 64) 16197 mov r0, rPC @ arg0 16198 mov r1, rSELF @ arg1 16199 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16200 16201/* ------------------------------ */ 16202 .balign 64 16203.L_ALT_OP_OR_INT_LIT8: /* 0xde */ 16204/* File: armv5te/alt_stub.S */ 16205/* 16206 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16207 * any interesting requests and then jump to the real instruction 16208 * handler. Note that the call to dvmCheckInst is done as a tail call. 16209 */ 16210 adrl lr, dvmAsmInstructionStart + (222 * 64) 16211 mov r0, rPC @ arg0 16212 mov r1, rSELF @ arg1 16213 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16214 16215/* ------------------------------ */ 16216 .balign 64 16217.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */ 16218/* File: armv5te/alt_stub.S */ 16219/* 16220 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16221 * any interesting requests and then jump to the real instruction 16222 * handler. Note that the call to dvmCheckInst is done as a tail call. 16223 */ 16224 adrl lr, dvmAsmInstructionStart + (223 * 64) 16225 mov r0, rPC @ arg0 16226 mov r1, rSELF @ arg1 16227 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16228 16229/* ------------------------------ */ 16230 .balign 64 16231.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */ 16232/* File: armv5te/alt_stub.S */ 16233/* 16234 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16235 * any interesting requests and then jump to the real instruction 16236 * handler. Note that the call to dvmCheckInst is done as a tail call. 16237 */ 16238 adrl lr, dvmAsmInstructionStart + (224 * 64) 16239 mov r0, rPC @ arg0 16240 mov r1, rSELF @ arg1 16241 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16242 16243/* ------------------------------ */ 16244 .balign 64 16245.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */ 16246/* File: armv5te/alt_stub.S */ 16247/* 16248 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16249 * any interesting requests and then jump to the real instruction 16250 * handler. Note that the call to dvmCheckInst is done as a tail call. 16251 */ 16252 adrl lr, dvmAsmInstructionStart + (225 * 64) 16253 mov r0, rPC @ arg0 16254 mov r1, rSELF @ arg1 16255 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16256 16257/* ------------------------------ */ 16258 .balign 64 16259.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */ 16260/* File: armv5te/alt_stub.S */ 16261/* 16262 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16263 * any interesting requests and then jump to the real instruction 16264 * handler. Note that the call to dvmCheckInst is done as a tail call. 16265 */ 16266 adrl lr, dvmAsmInstructionStart + (226 * 64) 16267 mov r0, rPC @ arg0 16268 mov r1, rSELF @ arg1 16269 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16270 16271/* ------------------------------ */ 16272 .balign 64 16273.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */ 16274/* File: armv5te/alt_stub.S */ 16275/* 16276 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16277 * any interesting requests and then jump to the real instruction 16278 * handler. Note that the call to dvmCheckInst is done as a tail call. 16279 */ 16280 adrl lr, dvmAsmInstructionStart + (227 * 64) 16281 mov r0, rPC @ arg0 16282 mov r1, rSELF @ arg1 16283 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16284 16285/* ------------------------------ */ 16286 .balign 64 16287.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */ 16288/* File: armv5te/alt_stub.S */ 16289/* 16290 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16291 * any interesting requests and then jump to the real instruction 16292 * handler. Note that the call to dvmCheckInst is done as a tail call. 16293 */ 16294 adrl lr, dvmAsmInstructionStart + (228 * 64) 16295 mov r0, rPC @ arg0 16296 mov r1, rSELF @ arg1 16297 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16298 16299/* ------------------------------ */ 16300 .balign 64 16301.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */ 16302/* File: armv5te/alt_stub.S */ 16303/* 16304 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16305 * any interesting requests and then jump to the real instruction 16306 * handler. Note that the call to dvmCheckInst is done as a tail call. 16307 */ 16308 adrl lr, dvmAsmInstructionStart + (229 * 64) 16309 mov r0, rPC @ arg0 16310 mov r1, rSELF @ arg1 16311 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16312 16313/* ------------------------------ */ 16314 .balign 64 16315.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */ 16316/* File: armv5te/alt_stub.S */ 16317/* 16318 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16319 * any interesting requests and then jump to the real instruction 16320 * handler. Note that the call to dvmCheckInst is done as a tail call. 16321 */ 16322 adrl lr, dvmAsmInstructionStart + (230 * 64) 16323 mov r0, rPC @ arg0 16324 mov r1, rSELF @ arg1 16325 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16326 16327/* ------------------------------ */ 16328 .balign 64 16329.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 16330/* File: armv5te/alt_stub.S */ 16331/* 16332 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16333 * any interesting requests and then jump to the real instruction 16334 * handler. Note that the call to dvmCheckInst is done as a tail call. 16335 */ 16336 adrl lr, dvmAsmInstructionStart + (231 * 64) 16337 mov r0, rPC @ arg0 16338 mov r1, rSELF @ arg1 16339 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16340 16341/* ------------------------------ */ 16342 .balign 64 16343.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 16344/* File: armv5te/alt_stub.S */ 16345/* 16346 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16347 * any interesting requests and then jump to the real instruction 16348 * handler. Note that the call to dvmCheckInst is done as a tail call. 16349 */ 16350 adrl lr, dvmAsmInstructionStart + (232 * 64) 16351 mov r0, rPC @ arg0 16352 mov r1, rSELF @ arg1 16353 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16354 16355/* ------------------------------ */ 16356 .balign 64 16357.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 16358/* File: armv5te/alt_stub.S */ 16359/* 16360 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16361 * any interesting requests and then jump to the real instruction 16362 * handler. Note that the call to dvmCheckInst is done as a tail call. 16363 */ 16364 adrl lr, dvmAsmInstructionStart + (233 * 64) 16365 mov r0, rPC @ arg0 16366 mov r1, rSELF @ arg1 16367 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16368 16369/* ------------------------------ */ 16370 .balign 64 16371.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */ 16372/* File: armv5te/alt_stub.S */ 16373/* 16374 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16375 * any interesting requests and then jump to the real instruction 16376 * handler. Note that the call to dvmCheckInst is done as a tail call. 16377 */ 16378 adrl lr, dvmAsmInstructionStart + (234 * 64) 16379 mov r0, rPC @ arg0 16380 mov r1, rSELF @ arg1 16381 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16382 16383/* ------------------------------ */ 16384 .balign 64 16385.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 16386/* File: armv5te/alt_stub.S */ 16387/* 16388 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16389 * any interesting requests and then jump to the real instruction 16390 * handler. Note that the call to dvmCheckInst is done as a tail call. 16391 */ 16392 adrl lr, dvmAsmInstructionStart + (235 * 64) 16393 mov r0, rPC @ arg0 16394 mov r1, rSELF @ arg1 16395 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16396 16397/* ------------------------------ */ 16398 .balign 64 16399.L_ALT_OP_BREAKPOINT: /* 0xec */ 16400/* File: armv5te/alt_stub.S */ 16401/* 16402 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16403 * any interesting requests and then jump to the real instruction 16404 * handler. Note that the call to dvmCheckInst is done as a tail call. 16405 */ 16406 adrl lr, dvmAsmInstructionStart + (236 * 64) 16407 mov r0, rPC @ arg0 16408 mov r1, rSELF @ arg1 16409 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16410 16411/* ------------------------------ */ 16412 .balign 64 16413.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 16414/* File: armv5te/alt_stub.S */ 16415/* 16416 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16417 * any interesting requests and then jump to the real instruction 16418 * handler. Note that the call to dvmCheckInst is done as a tail call. 16419 */ 16420 adrl lr, dvmAsmInstructionStart + (237 * 64) 16421 mov r0, rPC @ arg0 16422 mov r1, rSELF @ arg1 16423 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16424 16425/* ------------------------------ */ 16426 .balign 64 16427.L_ALT_OP_EXECUTE_INLINE: /* 0xee */ 16428/* File: armv5te/alt_stub.S */ 16429/* 16430 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16431 * any interesting requests and then jump to the real instruction 16432 * handler. Note that the call to dvmCheckInst is done as a tail call. 16433 */ 16434 adrl lr, dvmAsmInstructionStart + (238 * 64) 16435 mov r0, rPC @ arg0 16436 mov r1, rSELF @ arg1 16437 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16438 16439/* ------------------------------ */ 16440 .balign 64 16441.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 16442/* File: armv5te/alt_stub.S */ 16443/* 16444 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16445 * any interesting requests and then jump to the real instruction 16446 * handler. Note that the call to dvmCheckInst is done as a tail call. 16447 */ 16448 adrl lr, dvmAsmInstructionStart + (239 * 64) 16449 mov r0, rPC @ arg0 16450 mov r1, rSELF @ arg1 16451 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16452 16453/* ------------------------------ */ 16454 .balign 64 16455.L_ALT_OP_INVOKE_OBJECT_INIT: /* 0xf0 */ 16456/* File: armv5te/alt_stub.S */ 16457/* 16458 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16459 * any interesting requests and then jump to the real instruction 16460 * handler. Note that the call to dvmCheckInst is done as a tail call. 16461 */ 16462 adrl lr, dvmAsmInstructionStart + (240 * 64) 16463 mov r0, rPC @ arg0 16464 mov r1, rSELF @ arg1 16465 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16466 16467/* ------------------------------ */ 16468 .balign 64 16469.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 16470/* File: armv5te/alt_stub.S */ 16471/* 16472 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16473 * any interesting requests and then jump to the real instruction 16474 * handler. Note that the call to dvmCheckInst is done as a tail call. 16475 */ 16476 adrl lr, dvmAsmInstructionStart + (241 * 64) 16477 mov r0, rPC @ arg0 16478 mov r1, rSELF @ arg1 16479 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16480 16481/* ------------------------------ */ 16482 .balign 64 16483.L_ALT_OP_IGET_QUICK: /* 0xf2 */ 16484/* File: armv5te/alt_stub.S */ 16485/* 16486 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16487 * any interesting requests and then jump to the real instruction 16488 * handler. Note that the call to dvmCheckInst is done as a tail call. 16489 */ 16490 adrl lr, dvmAsmInstructionStart + (242 * 64) 16491 mov r0, rPC @ arg0 16492 mov r1, rSELF @ arg1 16493 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16494 16495/* ------------------------------ */ 16496 .balign 64 16497.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */ 16498/* File: armv5te/alt_stub.S */ 16499/* 16500 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16501 * any interesting requests and then jump to the real instruction 16502 * handler. Note that the call to dvmCheckInst is done as a tail call. 16503 */ 16504 adrl lr, dvmAsmInstructionStart + (243 * 64) 16505 mov r0, rPC @ arg0 16506 mov r1, rSELF @ arg1 16507 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16508 16509/* ------------------------------ */ 16510 .balign 64 16511.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 16512/* File: armv5te/alt_stub.S */ 16513/* 16514 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16515 * any interesting requests and then jump to the real instruction 16516 * handler. Note that the call to dvmCheckInst is done as a tail call. 16517 */ 16518 adrl lr, dvmAsmInstructionStart + (244 * 64) 16519 mov r0, rPC @ arg0 16520 mov r1, rSELF @ arg1 16521 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16522 16523/* ------------------------------ */ 16524 .balign 64 16525.L_ALT_OP_IPUT_QUICK: /* 0xf5 */ 16526/* File: armv5te/alt_stub.S */ 16527/* 16528 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16529 * any interesting requests and then jump to the real instruction 16530 * handler. Note that the call to dvmCheckInst is done as a tail call. 16531 */ 16532 adrl lr, dvmAsmInstructionStart + (245 * 64) 16533 mov r0, rPC @ arg0 16534 mov r1, rSELF @ arg1 16535 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16536 16537/* ------------------------------ */ 16538 .balign 64 16539.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 16540/* File: armv5te/alt_stub.S */ 16541/* 16542 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16543 * any interesting requests and then jump to the real instruction 16544 * handler. Note that the call to dvmCheckInst is done as a tail call. 16545 */ 16546 adrl lr, dvmAsmInstructionStart + (246 * 64) 16547 mov r0, rPC @ arg0 16548 mov r1, rSELF @ arg1 16549 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16550 16551/* ------------------------------ */ 16552 .balign 64 16553.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 16554/* File: armv5te/alt_stub.S */ 16555/* 16556 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16557 * any interesting requests and then jump to the real instruction 16558 * handler. Note that the call to dvmCheckInst is done as a tail call. 16559 */ 16560 adrl lr, dvmAsmInstructionStart + (247 * 64) 16561 mov r0, rPC @ arg0 16562 mov r1, rSELF @ arg1 16563 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16564 16565/* ------------------------------ */ 16566 .balign 64 16567.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 16568/* File: armv5te/alt_stub.S */ 16569/* 16570 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16571 * any interesting requests and then jump to the real instruction 16572 * handler. Note that the call to dvmCheckInst is done as a tail call. 16573 */ 16574 adrl lr, dvmAsmInstructionStart + (248 * 64) 16575 mov r0, rPC @ arg0 16576 mov r1, rSELF @ arg1 16577 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16578 16579/* ------------------------------ */ 16580 .balign 64 16581.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 16582/* File: armv5te/alt_stub.S */ 16583/* 16584 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16585 * any interesting requests and then jump to the real instruction 16586 * handler. Note that the call to dvmCheckInst is done as a tail call. 16587 */ 16588 adrl lr, dvmAsmInstructionStart + (249 * 64) 16589 mov r0, rPC @ arg0 16590 mov r1, rSELF @ arg1 16591 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16592 16593/* ------------------------------ */ 16594 .balign 64 16595.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 16596/* File: armv5te/alt_stub.S */ 16597/* 16598 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16599 * any interesting requests and then jump to the real instruction 16600 * handler. Note that the call to dvmCheckInst is done as a tail call. 16601 */ 16602 adrl lr, dvmAsmInstructionStart + (250 * 64) 16603 mov r0, rPC @ arg0 16604 mov r1, rSELF @ arg1 16605 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16606 16607/* ------------------------------ */ 16608 .balign 64 16609.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 16610/* File: armv5te/alt_stub.S */ 16611/* 16612 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16613 * any interesting requests and then jump to the real instruction 16614 * handler. Note that the call to dvmCheckInst is done as a tail call. 16615 */ 16616 adrl lr, dvmAsmInstructionStart + (251 * 64) 16617 mov r0, rPC @ arg0 16618 mov r1, rSELF @ arg1 16619 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16620 16621/* ------------------------------ */ 16622 .balign 64 16623.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 16624/* File: armv5te/alt_stub.S */ 16625/* 16626 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16627 * any interesting requests and then jump to the real instruction 16628 * handler. Note that the call to dvmCheckInst is done as a tail call. 16629 */ 16630 adrl lr, dvmAsmInstructionStart + (252 * 64) 16631 mov r0, rPC @ arg0 16632 mov r1, rSELF @ arg1 16633 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16634 16635/* ------------------------------ */ 16636 .balign 64 16637.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 16638/* File: armv5te/alt_stub.S */ 16639/* 16640 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16641 * any interesting requests and then jump to the real instruction 16642 * handler. Note that the call to dvmCheckInst is done as a tail call. 16643 */ 16644 adrl lr, dvmAsmInstructionStart + (253 * 64) 16645 mov r0, rPC @ arg0 16646 mov r1, rSELF @ arg1 16647 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16648 16649/* ------------------------------ */ 16650 .balign 64 16651.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 16652/* File: armv5te/alt_stub.S */ 16653/* 16654 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16655 * any interesting requests and then jump to the real instruction 16656 * handler. Note that the call to dvmCheckInst is done as a tail call. 16657 */ 16658 adrl lr, dvmAsmInstructionStart + (254 * 64) 16659 mov r0, rPC @ arg0 16660 mov r1, rSELF @ arg1 16661 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16662 16663/* ------------------------------ */ 16664 .balign 64 16665.L_ALT_OP_DISPATCH_FF: /* 0xff */ 16666/* File: armv5te/alt_stub.S */ 16667/* 16668 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16669 * any interesting requests and then jump to the real instruction 16670 * handler. Note that the call to dvmCheckInst is done as a tail call. 16671 */ 16672 adrl lr, dvmAsmInstructionStart + (255 * 64) 16673 mov r0, rPC @ arg0 16674 mov r1, rSELF @ arg1 16675 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16676 16677/* ------------------------------ */ 16678 .balign 64 16679.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */ 16680/* File: armv5te/alt_stub.S */ 16681/* 16682 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16683 * any interesting requests and then jump to the real instruction 16684 * handler. Note that the call to dvmCheckInst is done as a tail call. 16685 */ 16686 adrl lr, dvmAsmInstructionStart + (256 * 64) 16687 mov r0, rPC @ arg0 16688 mov r1, rSELF @ arg1 16689 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16690 16691/* ------------------------------ */ 16692 .balign 64 16693.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */ 16694/* File: armv5te/alt_stub.S */ 16695/* 16696 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16697 * any interesting requests and then jump to the real instruction 16698 * handler. Note that the call to dvmCheckInst is done as a tail call. 16699 */ 16700 adrl lr, dvmAsmInstructionStart + (257 * 64) 16701 mov r0, rPC @ arg0 16702 mov r1, rSELF @ arg1 16703 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16704 16705/* ------------------------------ */ 16706 .balign 64 16707.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 16708/* File: armv5te/alt_stub.S */ 16709/* 16710 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16711 * any interesting requests and then jump to the real instruction 16712 * handler. Note that the call to dvmCheckInst is done as a tail call. 16713 */ 16714 adrl lr, dvmAsmInstructionStart + (258 * 64) 16715 mov r0, rPC @ arg0 16716 mov r1, rSELF @ arg1 16717 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16718 16719/* ------------------------------ */ 16720 .balign 64 16721.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 16722/* File: armv5te/alt_stub.S */ 16723/* 16724 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16725 * any interesting requests and then jump to the real instruction 16726 * handler. Note that the call to dvmCheckInst is done as a tail call. 16727 */ 16728 adrl lr, dvmAsmInstructionStart + (259 * 64) 16729 mov r0, rPC @ arg0 16730 mov r1, rSELF @ arg1 16731 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16732 16733/* ------------------------------ */ 16734 .balign 64 16735.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 16736/* File: armv5te/alt_stub.S */ 16737/* 16738 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16739 * any interesting requests and then jump to the real instruction 16740 * handler. Note that the call to dvmCheckInst is done as a tail call. 16741 */ 16742 adrl lr, dvmAsmInstructionStart + (260 * 64) 16743 mov r0, rPC @ arg0 16744 mov r1, rSELF @ arg1 16745 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16746 16747/* ------------------------------ */ 16748 .balign 64 16749.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 16750/* File: armv5te/alt_stub.S */ 16751/* 16752 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16753 * any interesting requests and then jump to the real instruction 16754 * handler. Note that the call to dvmCheckInst is done as a tail call. 16755 */ 16756 adrl lr, dvmAsmInstructionStart + (261 * 64) 16757 mov r0, rPC @ arg0 16758 mov r1, rSELF @ arg1 16759 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16760 16761/* ------------------------------ */ 16762 .balign 64 16763.L_ALT_OP_IGET_JUMBO: /* 0x106 */ 16764/* File: armv5te/alt_stub.S */ 16765/* 16766 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16767 * any interesting requests and then jump to the real instruction 16768 * handler. Note that the call to dvmCheckInst is done as a tail call. 16769 */ 16770 adrl lr, dvmAsmInstructionStart + (262 * 64) 16771 mov r0, rPC @ arg0 16772 mov r1, rSELF @ arg1 16773 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16774 16775/* ------------------------------ */ 16776 .balign 64 16777.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */ 16778/* File: armv5te/alt_stub.S */ 16779/* 16780 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16781 * any interesting requests and then jump to the real instruction 16782 * handler. Note that the call to dvmCheckInst is done as a tail call. 16783 */ 16784 adrl lr, dvmAsmInstructionStart + (263 * 64) 16785 mov r0, rPC @ arg0 16786 mov r1, rSELF @ arg1 16787 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16788 16789/* ------------------------------ */ 16790 .balign 64 16791.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 16792/* File: armv5te/alt_stub.S */ 16793/* 16794 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16795 * any interesting requests and then jump to the real instruction 16796 * handler. Note that the call to dvmCheckInst is done as a tail call. 16797 */ 16798 adrl lr, dvmAsmInstructionStart + (264 * 64) 16799 mov r0, rPC @ arg0 16800 mov r1, rSELF @ arg1 16801 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16802 16803/* ------------------------------ */ 16804 .balign 64 16805.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 16806/* File: armv5te/alt_stub.S */ 16807/* 16808 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16809 * any interesting requests and then jump to the real instruction 16810 * handler. Note that the call to dvmCheckInst is done as a tail call. 16811 */ 16812 adrl lr, dvmAsmInstructionStart + (265 * 64) 16813 mov r0, rPC @ arg0 16814 mov r1, rSELF @ arg1 16815 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16816 16817/* ------------------------------ */ 16818 .balign 64 16819.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */ 16820/* File: armv5te/alt_stub.S */ 16821/* 16822 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16823 * any interesting requests and then jump to the real instruction 16824 * handler. Note that the call to dvmCheckInst is done as a tail call. 16825 */ 16826 adrl lr, dvmAsmInstructionStart + (266 * 64) 16827 mov r0, rPC @ arg0 16828 mov r1, rSELF @ arg1 16829 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16830 16831/* ------------------------------ */ 16832 .balign 64 16833.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */ 16834/* File: armv5te/alt_stub.S */ 16835/* 16836 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16837 * any interesting requests and then jump to the real instruction 16838 * handler. Note that the call to dvmCheckInst is done as a tail call. 16839 */ 16840 adrl lr, dvmAsmInstructionStart + (267 * 64) 16841 mov r0, rPC @ arg0 16842 mov r1, rSELF @ arg1 16843 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16844 16845/* ------------------------------ */ 16846 .balign 64 16847.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */ 16848/* File: armv5te/alt_stub.S */ 16849/* 16850 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16851 * any interesting requests and then jump to the real instruction 16852 * handler. Note that the call to dvmCheckInst is done as a tail call. 16853 */ 16854 adrl lr, dvmAsmInstructionStart + (268 * 64) 16855 mov r0, rPC @ arg0 16856 mov r1, rSELF @ arg1 16857 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16858 16859/* ------------------------------ */ 16860 .balign 64 16861.L_ALT_OP_IPUT_JUMBO: /* 0x10d */ 16862/* File: armv5te/alt_stub.S */ 16863/* 16864 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16865 * any interesting requests and then jump to the real instruction 16866 * handler. Note that the call to dvmCheckInst is done as a tail call. 16867 */ 16868 adrl lr, dvmAsmInstructionStart + (269 * 64) 16869 mov r0, rPC @ arg0 16870 mov r1, rSELF @ arg1 16871 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16872 16873/* ------------------------------ */ 16874 .balign 64 16875.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 16876/* File: armv5te/alt_stub.S */ 16877/* 16878 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16879 * any interesting requests and then jump to the real instruction 16880 * handler. Note that the call to dvmCheckInst is done as a tail call. 16881 */ 16882 adrl lr, dvmAsmInstructionStart + (270 * 64) 16883 mov r0, rPC @ arg0 16884 mov r1, rSELF @ arg1 16885 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16886 16887/* ------------------------------ */ 16888 .balign 64 16889.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 16890/* File: armv5te/alt_stub.S */ 16891/* 16892 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16893 * any interesting requests and then jump to the real instruction 16894 * handler. Note that the call to dvmCheckInst is done as a tail call. 16895 */ 16896 adrl lr, dvmAsmInstructionStart + (271 * 64) 16897 mov r0, rPC @ arg0 16898 mov r1, rSELF @ arg1 16899 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16900 16901/* ------------------------------ */ 16902 .balign 64 16903.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 16904/* File: armv5te/alt_stub.S */ 16905/* 16906 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16907 * any interesting requests and then jump to the real instruction 16908 * handler. Note that the call to dvmCheckInst is done as a tail call. 16909 */ 16910 adrl lr, dvmAsmInstructionStart + (272 * 64) 16911 mov r0, rPC @ arg0 16912 mov r1, rSELF @ arg1 16913 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16914 16915/* ------------------------------ */ 16916 .balign 64 16917.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 16918/* File: armv5te/alt_stub.S */ 16919/* 16920 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16921 * any interesting requests and then jump to the real instruction 16922 * handler. Note that the call to dvmCheckInst is done as a tail call. 16923 */ 16924 adrl lr, dvmAsmInstructionStart + (273 * 64) 16925 mov r0, rPC @ arg0 16926 mov r1, rSELF @ arg1 16927 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16928 16929/* ------------------------------ */ 16930 .balign 64 16931.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 16932/* File: armv5te/alt_stub.S */ 16933/* 16934 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16935 * any interesting requests and then jump to the real instruction 16936 * handler. Note that the call to dvmCheckInst is done as a tail call. 16937 */ 16938 adrl lr, dvmAsmInstructionStart + (274 * 64) 16939 mov r0, rPC @ arg0 16940 mov r1, rSELF @ arg1 16941 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16942 16943/* ------------------------------ */ 16944 .balign 64 16945.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 16946/* File: armv5te/alt_stub.S */ 16947/* 16948 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16949 * any interesting requests and then jump to the real instruction 16950 * handler. Note that the call to dvmCheckInst is done as a tail call. 16951 */ 16952 adrl lr, dvmAsmInstructionStart + (275 * 64) 16953 mov r0, rPC @ arg0 16954 mov r1, rSELF @ arg1 16955 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16956 16957/* ------------------------------ */ 16958 .balign 64 16959.L_ALT_OP_SGET_JUMBO: /* 0x114 */ 16960/* File: armv5te/alt_stub.S */ 16961/* 16962 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16963 * any interesting requests and then jump to the real instruction 16964 * handler. Note that the call to dvmCheckInst is done as a tail call. 16965 */ 16966 adrl lr, dvmAsmInstructionStart + (276 * 64) 16967 mov r0, rPC @ arg0 16968 mov r1, rSELF @ arg1 16969 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16970 16971/* ------------------------------ */ 16972 .balign 64 16973.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */ 16974/* File: armv5te/alt_stub.S */ 16975/* 16976 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16977 * any interesting requests and then jump to the real instruction 16978 * handler. Note that the call to dvmCheckInst is done as a tail call. 16979 */ 16980 adrl lr, dvmAsmInstructionStart + (277 * 64) 16981 mov r0, rPC @ arg0 16982 mov r1, rSELF @ arg1 16983 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16984 16985/* ------------------------------ */ 16986 .balign 64 16987.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 16988/* File: armv5te/alt_stub.S */ 16989/* 16990 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16991 * any interesting requests and then jump to the real instruction 16992 * handler. Note that the call to dvmCheckInst is done as a tail call. 16993 */ 16994 adrl lr, dvmAsmInstructionStart + (278 * 64) 16995 mov r0, rPC @ arg0 16996 mov r1, rSELF @ arg1 16997 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16998 16999/* ------------------------------ */ 17000 .balign 64 17001.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 17002/* File: armv5te/alt_stub.S */ 17003/* 17004 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17005 * any interesting requests and then jump to the real instruction 17006 * handler. Note that the call to dvmCheckInst is done as a tail call. 17007 */ 17008 adrl lr, dvmAsmInstructionStart + (279 * 64) 17009 mov r0, rPC @ arg0 17010 mov r1, rSELF @ arg1 17011 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17012 17013/* ------------------------------ */ 17014 .balign 64 17015.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */ 17016/* File: armv5te/alt_stub.S */ 17017/* 17018 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17019 * any interesting requests and then jump to the real instruction 17020 * handler. Note that the call to dvmCheckInst is done as a tail call. 17021 */ 17022 adrl lr, dvmAsmInstructionStart + (280 * 64) 17023 mov r0, rPC @ arg0 17024 mov r1, rSELF @ arg1 17025 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17026 17027/* ------------------------------ */ 17028 .balign 64 17029.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */ 17030/* File: armv5te/alt_stub.S */ 17031/* 17032 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17033 * any interesting requests and then jump to the real instruction 17034 * handler. Note that the call to dvmCheckInst is done as a tail call. 17035 */ 17036 adrl lr, dvmAsmInstructionStart + (281 * 64) 17037 mov r0, rPC @ arg0 17038 mov r1, rSELF @ arg1 17039 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17040 17041/* ------------------------------ */ 17042 .balign 64 17043.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */ 17044/* File: armv5te/alt_stub.S */ 17045/* 17046 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17047 * any interesting requests and then jump to the real instruction 17048 * handler. Note that the call to dvmCheckInst is done as a tail call. 17049 */ 17050 adrl lr, dvmAsmInstructionStart + (282 * 64) 17051 mov r0, rPC @ arg0 17052 mov r1, rSELF @ arg1 17053 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17054 17055/* ------------------------------ */ 17056 .balign 64 17057.L_ALT_OP_SPUT_JUMBO: /* 0x11b */ 17058/* File: armv5te/alt_stub.S */ 17059/* 17060 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17061 * any interesting requests and then jump to the real instruction 17062 * handler. Note that the call to dvmCheckInst is done as a tail call. 17063 */ 17064 adrl lr, dvmAsmInstructionStart + (283 * 64) 17065 mov r0, rPC @ arg0 17066 mov r1, rSELF @ arg1 17067 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17068 17069/* ------------------------------ */ 17070 .balign 64 17071.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 17072/* File: armv5te/alt_stub.S */ 17073/* 17074 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17075 * any interesting requests and then jump to the real instruction 17076 * handler. Note that the call to dvmCheckInst is done as a tail call. 17077 */ 17078 adrl lr, dvmAsmInstructionStart + (284 * 64) 17079 mov r0, rPC @ arg0 17080 mov r1, rSELF @ arg1 17081 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17082 17083/* ------------------------------ */ 17084 .balign 64 17085.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 17086/* File: armv5te/alt_stub.S */ 17087/* 17088 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17089 * any interesting requests and then jump to the real instruction 17090 * handler. Note that the call to dvmCheckInst is done as a tail call. 17091 */ 17092 adrl lr, dvmAsmInstructionStart + (285 * 64) 17093 mov r0, rPC @ arg0 17094 mov r1, rSELF @ arg1 17095 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17096 17097/* ------------------------------ */ 17098 .balign 64 17099.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 17100/* File: armv5te/alt_stub.S */ 17101/* 17102 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17103 * any interesting requests and then jump to the real instruction 17104 * handler. Note that the call to dvmCheckInst is done as a tail call. 17105 */ 17106 adrl lr, dvmAsmInstructionStart + (286 * 64) 17107 mov r0, rPC @ arg0 17108 mov r1, rSELF @ arg1 17109 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17110 17111/* ------------------------------ */ 17112 .balign 64 17113.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 17114/* File: armv5te/alt_stub.S */ 17115/* 17116 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17117 * any interesting requests and then jump to the real instruction 17118 * handler. Note that the call to dvmCheckInst is done as a tail call. 17119 */ 17120 adrl lr, dvmAsmInstructionStart + (287 * 64) 17121 mov r0, rPC @ arg0 17122 mov r1, rSELF @ arg1 17123 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17124 17125/* ------------------------------ */ 17126 .balign 64 17127.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 17128/* File: armv5te/alt_stub.S */ 17129/* 17130 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17131 * any interesting requests and then jump to the real instruction 17132 * handler. Note that the call to dvmCheckInst is done as a tail call. 17133 */ 17134 adrl lr, dvmAsmInstructionStart + (288 * 64) 17135 mov r0, rPC @ arg0 17136 mov r1, rSELF @ arg1 17137 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17138 17139/* ------------------------------ */ 17140 .balign 64 17141.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 17142/* File: armv5te/alt_stub.S */ 17143/* 17144 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17145 * any interesting requests and then jump to the real instruction 17146 * handler. Note that the call to dvmCheckInst is done as a tail call. 17147 */ 17148 adrl lr, dvmAsmInstructionStart + (289 * 64) 17149 mov r0, rPC @ arg0 17150 mov r1, rSELF @ arg1 17151 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17152 17153/* ------------------------------ */ 17154 .balign 64 17155.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 17156/* File: armv5te/alt_stub.S */ 17157/* 17158 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17159 * any interesting requests and then jump to the real instruction 17160 * handler. Note that the call to dvmCheckInst is done as a tail call. 17161 */ 17162 adrl lr, dvmAsmInstructionStart + (290 * 64) 17163 mov r0, rPC @ arg0 17164 mov r1, rSELF @ arg1 17165 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17166 17167/* ------------------------------ */ 17168 .balign 64 17169.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 17170/* File: armv5te/alt_stub.S */ 17171/* 17172 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17173 * any interesting requests and then jump to the real instruction 17174 * handler. Note that the call to dvmCheckInst is done as a tail call. 17175 */ 17176 adrl lr, dvmAsmInstructionStart + (291 * 64) 17177 mov r0, rPC @ arg0 17178 mov r1, rSELF @ arg1 17179 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17180 17181/* ------------------------------ */ 17182 .balign 64 17183.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 17184/* File: armv5te/alt_stub.S */ 17185/* 17186 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17187 * any interesting requests and then jump to the real instruction 17188 * handler. Note that the call to dvmCheckInst is done as a tail call. 17189 */ 17190 adrl lr, dvmAsmInstructionStart + (292 * 64) 17191 mov r0, rPC @ arg0 17192 mov r1, rSELF @ arg1 17193 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17194 17195/* ------------------------------ */ 17196 .balign 64 17197.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 17198/* File: armv5te/alt_stub.S */ 17199/* 17200 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17201 * any interesting requests and then jump to the real instruction 17202 * handler. Note that the call to dvmCheckInst is done as a tail call. 17203 */ 17204 adrl lr, dvmAsmInstructionStart + (293 * 64) 17205 mov r0, rPC @ arg0 17206 mov r1, rSELF @ arg1 17207 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17208 17209/* ------------------------------ */ 17210 .balign 64 17211.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 17212/* File: armv5te/alt_stub.S */ 17213/* 17214 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17215 * any interesting requests and then jump to the real instruction 17216 * handler. Note that the call to dvmCheckInst is done as a tail call. 17217 */ 17218 adrl lr, dvmAsmInstructionStart + (294 * 64) 17219 mov r0, rPC @ arg0 17220 mov r1, rSELF @ arg1 17221 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17222 17223/* ------------------------------ */ 17224 .balign 64 17225.L_ALT_OP_UNUSED_27FF: /* 0x127 */ 17226/* File: armv5te/alt_stub.S */ 17227/* 17228 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17229 * any interesting requests and then jump to the real instruction 17230 * handler. Note that the call to dvmCheckInst is done as a tail call. 17231 */ 17232 adrl lr, dvmAsmInstructionStart + (295 * 64) 17233 mov r0, rPC @ arg0 17234 mov r1, rSELF @ arg1 17235 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17236 17237/* ------------------------------ */ 17238 .balign 64 17239.L_ALT_OP_UNUSED_28FF: /* 0x128 */ 17240/* File: armv5te/alt_stub.S */ 17241/* 17242 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17243 * any interesting requests and then jump to the real instruction 17244 * handler. Note that the call to dvmCheckInst is done as a tail call. 17245 */ 17246 adrl lr, dvmAsmInstructionStart + (296 * 64) 17247 mov r0, rPC @ arg0 17248 mov r1, rSELF @ arg1 17249 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17250 17251/* ------------------------------ */ 17252 .balign 64 17253.L_ALT_OP_UNUSED_29FF: /* 0x129 */ 17254/* File: armv5te/alt_stub.S */ 17255/* 17256 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17257 * any interesting requests and then jump to the real instruction 17258 * handler. Note that the call to dvmCheckInst is done as a tail call. 17259 */ 17260 adrl lr, dvmAsmInstructionStart + (297 * 64) 17261 mov r0, rPC @ arg0 17262 mov r1, rSELF @ arg1 17263 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17264 17265/* ------------------------------ */ 17266 .balign 64 17267.L_ALT_OP_UNUSED_2AFF: /* 0x12a */ 17268/* File: armv5te/alt_stub.S */ 17269/* 17270 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17271 * any interesting requests and then jump to the real instruction 17272 * handler. Note that the call to dvmCheckInst is done as a tail call. 17273 */ 17274 adrl lr, dvmAsmInstructionStart + (298 * 64) 17275 mov r0, rPC @ arg0 17276 mov r1, rSELF @ arg1 17277 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17278 17279/* ------------------------------ */ 17280 .balign 64 17281.L_ALT_OP_UNUSED_2BFF: /* 0x12b */ 17282/* File: armv5te/alt_stub.S */ 17283/* 17284 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17285 * any interesting requests and then jump to the real instruction 17286 * handler. Note that the call to dvmCheckInst is done as a tail call. 17287 */ 17288 adrl lr, dvmAsmInstructionStart + (299 * 64) 17289 mov r0, rPC @ arg0 17290 mov r1, rSELF @ arg1 17291 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17292 17293/* ------------------------------ */ 17294 .balign 64 17295.L_ALT_OP_UNUSED_2CFF: /* 0x12c */ 17296/* File: armv5te/alt_stub.S */ 17297/* 17298 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17299 * any interesting requests and then jump to the real instruction 17300 * handler. Note that the call to dvmCheckInst is done as a tail call. 17301 */ 17302 adrl lr, dvmAsmInstructionStart + (300 * 64) 17303 mov r0, rPC @ arg0 17304 mov r1, rSELF @ arg1 17305 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17306 17307/* ------------------------------ */ 17308 .balign 64 17309.L_ALT_OP_UNUSED_2DFF: /* 0x12d */ 17310/* File: armv5te/alt_stub.S */ 17311/* 17312 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17313 * any interesting requests and then jump to the real instruction 17314 * handler. Note that the call to dvmCheckInst is done as a tail call. 17315 */ 17316 adrl lr, dvmAsmInstructionStart + (301 * 64) 17317 mov r0, rPC @ arg0 17318 mov r1, rSELF @ arg1 17319 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17320 17321/* ------------------------------ */ 17322 .balign 64 17323.L_ALT_OP_UNUSED_2EFF: /* 0x12e */ 17324/* File: armv5te/alt_stub.S */ 17325/* 17326 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17327 * any interesting requests and then jump to the real instruction 17328 * handler. Note that the call to dvmCheckInst is done as a tail call. 17329 */ 17330 adrl lr, dvmAsmInstructionStart + (302 * 64) 17331 mov r0, rPC @ arg0 17332 mov r1, rSELF @ arg1 17333 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17334 17335/* ------------------------------ */ 17336 .balign 64 17337.L_ALT_OP_UNUSED_2FFF: /* 0x12f */ 17338/* File: armv5te/alt_stub.S */ 17339/* 17340 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17341 * any interesting requests and then jump to the real instruction 17342 * handler. Note that the call to dvmCheckInst is done as a tail call. 17343 */ 17344 adrl lr, dvmAsmInstructionStart + (303 * 64) 17345 mov r0, rPC @ arg0 17346 mov r1, rSELF @ arg1 17347 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17348 17349/* ------------------------------ */ 17350 .balign 64 17351.L_ALT_OP_UNUSED_30FF: /* 0x130 */ 17352/* File: armv5te/alt_stub.S */ 17353/* 17354 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17355 * any interesting requests and then jump to the real instruction 17356 * handler. Note that the call to dvmCheckInst is done as a tail call. 17357 */ 17358 adrl lr, dvmAsmInstructionStart + (304 * 64) 17359 mov r0, rPC @ arg0 17360 mov r1, rSELF @ arg1 17361 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17362 17363/* ------------------------------ */ 17364 .balign 64 17365.L_ALT_OP_UNUSED_31FF: /* 0x131 */ 17366/* File: armv5te/alt_stub.S */ 17367/* 17368 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17369 * any interesting requests and then jump to the real instruction 17370 * handler. Note that the call to dvmCheckInst is done as a tail call. 17371 */ 17372 adrl lr, dvmAsmInstructionStart + (305 * 64) 17373 mov r0, rPC @ arg0 17374 mov r1, rSELF @ arg1 17375 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17376 17377/* ------------------------------ */ 17378 .balign 64 17379.L_ALT_OP_UNUSED_32FF: /* 0x132 */ 17380/* File: armv5te/alt_stub.S */ 17381/* 17382 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17383 * any interesting requests and then jump to the real instruction 17384 * handler. Note that the call to dvmCheckInst is done as a tail call. 17385 */ 17386 adrl lr, dvmAsmInstructionStart + (306 * 64) 17387 mov r0, rPC @ arg0 17388 mov r1, rSELF @ arg1 17389 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17390 17391/* ------------------------------ */ 17392 .balign 64 17393.L_ALT_OP_UNUSED_33FF: /* 0x133 */ 17394/* File: armv5te/alt_stub.S */ 17395/* 17396 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17397 * any interesting requests and then jump to the real instruction 17398 * handler. Note that the call to dvmCheckInst is done as a tail call. 17399 */ 17400 adrl lr, dvmAsmInstructionStart + (307 * 64) 17401 mov r0, rPC @ arg0 17402 mov r1, rSELF @ arg1 17403 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17404 17405/* ------------------------------ */ 17406 .balign 64 17407.L_ALT_OP_UNUSED_34FF: /* 0x134 */ 17408/* File: armv5te/alt_stub.S */ 17409/* 17410 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17411 * any interesting requests and then jump to the real instruction 17412 * handler. Note that the call to dvmCheckInst is done as a tail call. 17413 */ 17414 adrl lr, dvmAsmInstructionStart + (308 * 64) 17415 mov r0, rPC @ arg0 17416 mov r1, rSELF @ arg1 17417 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17418 17419/* ------------------------------ */ 17420 .balign 64 17421.L_ALT_OP_UNUSED_35FF: /* 0x135 */ 17422/* File: armv5te/alt_stub.S */ 17423/* 17424 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17425 * any interesting requests and then jump to the real instruction 17426 * handler. Note that the call to dvmCheckInst is done as a tail call. 17427 */ 17428 adrl lr, dvmAsmInstructionStart + (309 * 64) 17429 mov r0, rPC @ arg0 17430 mov r1, rSELF @ arg1 17431 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17432 17433/* ------------------------------ */ 17434 .balign 64 17435.L_ALT_OP_UNUSED_36FF: /* 0x136 */ 17436/* File: armv5te/alt_stub.S */ 17437/* 17438 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17439 * any interesting requests and then jump to the real instruction 17440 * handler. Note that the call to dvmCheckInst is done as a tail call. 17441 */ 17442 adrl lr, dvmAsmInstructionStart + (310 * 64) 17443 mov r0, rPC @ arg0 17444 mov r1, rSELF @ arg1 17445 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17446 17447/* ------------------------------ */ 17448 .balign 64 17449.L_ALT_OP_UNUSED_37FF: /* 0x137 */ 17450/* File: armv5te/alt_stub.S */ 17451/* 17452 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17453 * any interesting requests and then jump to the real instruction 17454 * handler. Note that the call to dvmCheckInst is done as a tail call. 17455 */ 17456 adrl lr, dvmAsmInstructionStart + (311 * 64) 17457 mov r0, rPC @ arg0 17458 mov r1, rSELF @ arg1 17459 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17460 17461/* ------------------------------ */ 17462 .balign 64 17463.L_ALT_OP_UNUSED_38FF: /* 0x138 */ 17464/* File: armv5te/alt_stub.S */ 17465/* 17466 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17467 * any interesting requests and then jump to the real instruction 17468 * handler. Note that the call to dvmCheckInst is done as a tail call. 17469 */ 17470 adrl lr, dvmAsmInstructionStart + (312 * 64) 17471 mov r0, rPC @ arg0 17472 mov r1, rSELF @ arg1 17473 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17474 17475/* ------------------------------ */ 17476 .balign 64 17477.L_ALT_OP_UNUSED_39FF: /* 0x139 */ 17478/* File: armv5te/alt_stub.S */ 17479/* 17480 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17481 * any interesting requests and then jump to the real instruction 17482 * handler. Note that the call to dvmCheckInst is done as a tail call. 17483 */ 17484 adrl lr, dvmAsmInstructionStart + (313 * 64) 17485 mov r0, rPC @ arg0 17486 mov r1, rSELF @ arg1 17487 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17488 17489/* ------------------------------ */ 17490 .balign 64 17491.L_ALT_OP_UNUSED_3AFF: /* 0x13a */ 17492/* File: armv5te/alt_stub.S */ 17493/* 17494 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17495 * any interesting requests and then jump to the real instruction 17496 * handler. Note that the call to dvmCheckInst is done as a tail call. 17497 */ 17498 adrl lr, dvmAsmInstructionStart + (314 * 64) 17499 mov r0, rPC @ arg0 17500 mov r1, rSELF @ arg1 17501 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17502 17503/* ------------------------------ */ 17504 .balign 64 17505.L_ALT_OP_UNUSED_3BFF: /* 0x13b */ 17506/* File: armv5te/alt_stub.S */ 17507/* 17508 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17509 * any interesting requests and then jump to the real instruction 17510 * handler. Note that the call to dvmCheckInst is done as a tail call. 17511 */ 17512 adrl lr, dvmAsmInstructionStart + (315 * 64) 17513 mov r0, rPC @ arg0 17514 mov r1, rSELF @ arg1 17515 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17516 17517/* ------------------------------ */ 17518 .balign 64 17519.L_ALT_OP_UNUSED_3CFF: /* 0x13c */ 17520/* File: armv5te/alt_stub.S */ 17521/* 17522 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17523 * any interesting requests and then jump to the real instruction 17524 * handler. Note that the call to dvmCheckInst is done as a tail call. 17525 */ 17526 adrl lr, dvmAsmInstructionStart + (316 * 64) 17527 mov r0, rPC @ arg0 17528 mov r1, rSELF @ arg1 17529 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17530 17531/* ------------------------------ */ 17532 .balign 64 17533.L_ALT_OP_UNUSED_3DFF: /* 0x13d */ 17534/* File: armv5te/alt_stub.S */ 17535/* 17536 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17537 * any interesting requests and then jump to the real instruction 17538 * handler. Note that the call to dvmCheckInst is done as a tail call. 17539 */ 17540 adrl lr, dvmAsmInstructionStart + (317 * 64) 17541 mov r0, rPC @ arg0 17542 mov r1, rSELF @ arg1 17543 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17544 17545/* ------------------------------ */ 17546 .balign 64 17547.L_ALT_OP_UNUSED_3EFF: /* 0x13e */ 17548/* File: armv5te/alt_stub.S */ 17549/* 17550 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17551 * any interesting requests and then jump to the real instruction 17552 * handler. Note that the call to dvmCheckInst is done as a tail call. 17553 */ 17554 adrl lr, dvmAsmInstructionStart + (318 * 64) 17555 mov r0, rPC @ arg0 17556 mov r1, rSELF @ arg1 17557 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17558 17559/* ------------------------------ */ 17560 .balign 64 17561.L_ALT_OP_UNUSED_3FFF: /* 0x13f */ 17562/* File: armv5te/alt_stub.S */ 17563/* 17564 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17565 * any interesting requests and then jump to the real instruction 17566 * handler. Note that the call to dvmCheckInst is done as a tail call. 17567 */ 17568 adrl lr, dvmAsmInstructionStart + (319 * 64) 17569 mov r0, rPC @ arg0 17570 mov r1, rSELF @ arg1 17571 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17572 17573/* ------------------------------ */ 17574 .balign 64 17575.L_ALT_OP_UNUSED_40FF: /* 0x140 */ 17576/* File: armv5te/alt_stub.S */ 17577/* 17578 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17579 * any interesting requests and then jump to the real instruction 17580 * handler. Note that the call to dvmCheckInst is done as a tail call. 17581 */ 17582 adrl lr, dvmAsmInstructionStart + (320 * 64) 17583 mov r0, rPC @ arg0 17584 mov r1, rSELF @ arg1 17585 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17586 17587/* ------------------------------ */ 17588 .balign 64 17589.L_ALT_OP_UNUSED_41FF: /* 0x141 */ 17590/* File: armv5te/alt_stub.S */ 17591/* 17592 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17593 * any interesting requests and then jump to the real instruction 17594 * handler. Note that the call to dvmCheckInst is done as a tail call. 17595 */ 17596 adrl lr, dvmAsmInstructionStart + (321 * 64) 17597 mov r0, rPC @ arg0 17598 mov r1, rSELF @ arg1 17599 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17600 17601/* ------------------------------ */ 17602 .balign 64 17603.L_ALT_OP_UNUSED_42FF: /* 0x142 */ 17604/* File: armv5te/alt_stub.S */ 17605/* 17606 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17607 * any interesting requests and then jump to the real instruction 17608 * handler. Note that the call to dvmCheckInst is done as a tail call. 17609 */ 17610 adrl lr, dvmAsmInstructionStart + (322 * 64) 17611 mov r0, rPC @ arg0 17612 mov r1, rSELF @ arg1 17613 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17614 17615/* ------------------------------ */ 17616 .balign 64 17617.L_ALT_OP_UNUSED_43FF: /* 0x143 */ 17618/* File: armv5te/alt_stub.S */ 17619/* 17620 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17621 * any interesting requests and then jump to the real instruction 17622 * handler. Note that the call to dvmCheckInst is done as a tail call. 17623 */ 17624 adrl lr, dvmAsmInstructionStart + (323 * 64) 17625 mov r0, rPC @ arg0 17626 mov r1, rSELF @ arg1 17627 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17628 17629/* ------------------------------ */ 17630 .balign 64 17631.L_ALT_OP_UNUSED_44FF: /* 0x144 */ 17632/* File: armv5te/alt_stub.S */ 17633/* 17634 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17635 * any interesting requests and then jump to the real instruction 17636 * handler. Note that the call to dvmCheckInst is done as a tail call. 17637 */ 17638 adrl lr, dvmAsmInstructionStart + (324 * 64) 17639 mov r0, rPC @ arg0 17640 mov r1, rSELF @ arg1 17641 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17642 17643/* ------------------------------ */ 17644 .balign 64 17645.L_ALT_OP_UNUSED_45FF: /* 0x145 */ 17646/* File: armv5te/alt_stub.S */ 17647/* 17648 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17649 * any interesting requests and then jump to the real instruction 17650 * handler. Note that the call to dvmCheckInst is done as a tail call. 17651 */ 17652 adrl lr, dvmAsmInstructionStart + (325 * 64) 17653 mov r0, rPC @ arg0 17654 mov r1, rSELF @ arg1 17655 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17656 17657/* ------------------------------ */ 17658 .balign 64 17659.L_ALT_OP_UNUSED_46FF: /* 0x146 */ 17660/* File: armv5te/alt_stub.S */ 17661/* 17662 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17663 * any interesting requests and then jump to the real instruction 17664 * handler. Note that the call to dvmCheckInst is done as a tail call. 17665 */ 17666 adrl lr, dvmAsmInstructionStart + (326 * 64) 17667 mov r0, rPC @ arg0 17668 mov r1, rSELF @ arg1 17669 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17670 17671/* ------------------------------ */ 17672 .balign 64 17673.L_ALT_OP_UNUSED_47FF: /* 0x147 */ 17674/* File: armv5te/alt_stub.S */ 17675/* 17676 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17677 * any interesting requests and then jump to the real instruction 17678 * handler. Note that the call to dvmCheckInst is done as a tail call. 17679 */ 17680 adrl lr, dvmAsmInstructionStart + (327 * 64) 17681 mov r0, rPC @ arg0 17682 mov r1, rSELF @ arg1 17683 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17684 17685/* ------------------------------ */ 17686 .balign 64 17687.L_ALT_OP_UNUSED_48FF: /* 0x148 */ 17688/* File: armv5te/alt_stub.S */ 17689/* 17690 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17691 * any interesting requests and then jump to the real instruction 17692 * handler. Note that the call to dvmCheckInst is done as a tail call. 17693 */ 17694 adrl lr, dvmAsmInstructionStart + (328 * 64) 17695 mov r0, rPC @ arg0 17696 mov r1, rSELF @ arg1 17697 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17698 17699/* ------------------------------ */ 17700 .balign 64 17701.L_ALT_OP_UNUSED_49FF: /* 0x149 */ 17702/* File: armv5te/alt_stub.S */ 17703/* 17704 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17705 * any interesting requests and then jump to the real instruction 17706 * handler. Note that the call to dvmCheckInst is done as a tail call. 17707 */ 17708 adrl lr, dvmAsmInstructionStart + (329 * 64) 17709 mov r0, rPC @ arg0 17710 mov r1, rSELF @ arg1 17711 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17712 17713/* ------------------------------ */ 17714 .balign 64 17715.L_ALT_OP_UNUSED_4AFF: /* 0x14a */ 17716/* File: armv5te/alt_stub.S */ 17717/* 17718 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17719 * any interesting requests and then jump to the real instruction 17720 * handler. Note that the call to dvmCheckInst is done as a tail call. 17721 */ 17722 adrl lr, dvmAsmInstructionStart + (330 * 64) 17723 mov r0, rPC @ arg0 17724 mov r1, rSELF @ arg1 17725 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17726 17727/* ------------------------------ */ 17728 .balign 64 17729.L_ALT_OP_UNUSED_4BFF: /* 0x14b */ 17730/* File: armv5te/alt_stub.S */ 17731/* 17732 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17733 * any interesting requests and then jump to the real instruction 17734 * handler. Note that the call to dvmCheckInst is done as a tail call. 17735 */ 17736 adrl lr, dvmAsmInstructionStart + (331 * 64) 17737 mov r0, rPC @ arg0 17738 mov r1, rSELF @ arg1 17739 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17740 17741/* ------------------------------ */ 17742 .balign 64 17743.L_ALT_OP_UNUSED_4CFF: /* 0x14c */ 17744/* File: armv5te/alt_stub.S */ 17745/* 17746 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17747 * any interesting requests and then jump to the real instruction 17748 * handler. Note that the call to dvmCheckInst is done as a tail call. 17749 */ 17750 adrl lr, dvmAsmInstructionStart + (332 * 64) 17751 mov r0, rPC @ arg0 17752 mov r1, rSELF @ arg1 17753 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17754 17755/* ------------------------------ */ 17756 .balign 64 17757.L_ALT_OP_UNUSED_4DFF: /* 0x14d */ 17758/* File: armv5te/alt_stub.S */ 17759/* 17760 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17761 * any interesting requests and then jump to the real instruction 17762 * handler. Note that the call to dvmCheckInst is done as a tail call. 17763 */ 17764 adrl lr, dvmAsmInstructionStart + (333 * 64) 17765 mov r0, rPC @ arg0 17766 mov r1, rSELF @ arg1 17767 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17768 17769/* ------------------------------ */ 17770 .balign 64 17771.L_ALT_OP_UNUSED_4EFF: /* 0x14e */ 17772/* File: armv5te/alt_stub.S */ 17773/* 17774 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17775 * any interesting requests and then jump to the real instruction 17776 * handler. Note that the call to dvmCheckInst is done as a tail call. 17777 */ 17778 adrl lr, dvmAsmInstructionStart + (334 * 64) 17779 mov r0, rPC @ arg0 17780 mov r1, rSELF @ arg1 17781 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17782 17783/* ------------------------------ */ 17784 .balign 64 17785.L_ALT_OP_UNUSED_4FFF: /* 0x14f */ 17786/* File: armv5te/alt_stub.S */ 17787/* 17788 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17789 * any interesting requests and then jump to the real instruction 17790 * handler. Note that the call to dvmCheckInst is done as a tail call. 17791 */ 17792 adrl lr, dvmAsmInstructionStart + (335 * 64) 17793 mov r0, rPC @ arg0 17794 mov r1, rSELF @ arg1 17795 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17796 17797/* ------------------------------ */ 17798 .balign 64 17799.L_ALT_OP_UNUSED_50FF: /* 0x150 */ 17800/* File: armv5te/alt_stub.S */ 17801/* 17802 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17803 * any interesting requests and then jump to the real instruction 17804 * handler. Note that the call to dvmCheckInst is done as a tail call. 17805 */ 17806 adrl lr, dvmAsmInstructionStart + (336 * 64) 17807 mov r0, rPC @ arg0 17808 mov r1, rSELF @ arg1 17809 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17810 17811/* ------------------------------ */ 17812 .balign 64 17813.L_ALT_OP_UNUSED_51FF: /* 0x151 */ 17814/* File: armv5te/alt_stub.S */ 17815/* 17816 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17817 * any interesting requests and then jump to the real instruction 17818 * handler. Note that the call to dvmCheckInst is done as a tail call. 17819 */ 17820 adrl lr, dvmAsmInstructionStart + (337 * 64) 17821 mov r0, rPC @ arg0 17822 mov r1, rSELF @ arg1 17823 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17824 17825/* ------------------------------ */ 17826 .balign 64 17827.L_ALT_OP_UNUSED_52FF: /* 0x152 */ 17828/* File: armv5te/alt_stub.S */ 17829/* 17830 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17831 * any interesting requests and then jump to the real instruction 17832 * handler. Note that the call to dvmCheckInst is done as a tail call. 17833 */ 17834 adrl lr, dvmAsmInstructionStart + (338 * 64) 17835 mov r0, rPC @ arg0 17836 mov r1, rSELF @ arg1 17837 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17838 17839/* ------------------------------ */ 17840 .balign 64 17841.L_ALT_OP_UNUSED_53FF: /* 0x153 */ 17842/* File: armv5te/alt_stub.S */ 17843/* 17844 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17845 * any interesting requests and then jump to the real instruction 17846 * handler. Note that the call to dvmCheckInst is done as a tail call. 17847 */ 17848 adrl lr, dvmAsmInstructionStart + (339 * 64) 17849 mov r0, rPC @ arg0 17850 mov r1, rSELF @ arg1 17851 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17852 17853/* ------------------------------ */ 17854 .balign 64 17855.L_ALT_OP_UNUSED_54FF: /* 0x154 */ 17856/* File: armv5te/alt_stub.S */ 17857/* 17858 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17859 * any interesting requests and then jump to the real instruction 17860 * handler. Note that the call to dvmCheckInst is done as a tail call. 17861 */ 17862 adrl lr, dvmAsmInstructionStart + (340 * 64) 17863 mov r0, rPC @ arg0 17864 mov r1, rSELF @ arg1 17865 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17866 17867/* ------------------------------ */ 17868 .balign 64 17869.L_ALT_OP_UNUSED_55FF: /* 0x155 */ 17870/* File: armv5te/alt_stub.S */ 17871/* 17872 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17873 * any interesting requests and then jump to the real instruction 17874 * handler. Note that the call to dvmCheckInst is done as a tail call. 17875 */ 17876 adrl lr, dvmAsmInstructionStart + (341 * 64) 17877 mov r0, rPC @ arg0 17878 mov r1, rSELF @ arg1 17879 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17880 17881/* ------------------------------ */ 17882 .balign 64 17883.L_ALT_OP_UNUSED_56FF: /* 0x156 */ 17884/* File: armv5te/alt_stub.S */ 17885/* 17886 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17887 * any interesting requests and then jump to the real instruction 17888 * handler. Note that the call to dvmCheckInst is done as a tail call. 17889 */ 17890 adrl lr, dvmAsmInstructionStart + (342 * 64) 17891 mov r0, rPC @ arg0 17892 mov r1, rSELF @ arg1 17893 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17894 17895/* ------------------------------ */ 17896 .balign 64 17897.L_ALT_OP_UNUSED_57FF: /* 0x157 */ 17898/* File: armv5te/alt_stub.S */ 17899/* 17900 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17901 * any interesting requests and then jump to the real instruction 17902 * handler. Note that the call to dvmCheckInst is done as a tail call. 17903 */ 17904 adrl lr, dvmAsmInstructionStart + (343 * 64) 17905 mov r0, rPC @ arg0 17906 mov r1, rSELF @ arg1 17907 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17908 17909/* ------------------------------ */ 17910 .balign 64 17911.L_ALT_OP_UNUSED_58FF: /* 0x158 */ 17912/* File: armv5te/alt_stub.S */ 17913/* 17914 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17915 * any interesting requests and then jump to the real instruction 17916 * handler. Note that the call to dvmCheckInst is done as a tail call. 17917 */ 17918 adrl lr, dvmAsmInstructionStart + (344 * 64) 17919 mov r0, rPC @ arg0 17920 mov r1, rSELF @ arg1 17921 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17922 17923/* ------------------------------ */ 17924 .balign 64 17925.L_ALT_OP_UNUSED_59FF: /* 0x159 */ 17926/* File: armv5te/alt_stub.S */ 17927/* 17928 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17929 * any interesting requests and then jump to the real instruction 17930 * handler. Note that the call to dvmCheckInst is done as a tail call. 17931 */ 17932 adrl lr, dvmAsmInstructionStart + (345 * 64) 17933 mov r0, rPC @ arg0 17934 mov r1, rSELF @ arg1 17935 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17936 17937/* ------------------------------ */ 17938 .balign 64 17939.L_ALT_OP_UNUSED_5AFF: /* 0x15a */ 17940/* File: armv5te/alt_stub.S */ 17941/* 17942 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17943 * any interesting requests and then jump to the real instruction 17944 * handler. Note that the call to dvmCheckInst is done as a tail call. 17945 */ 17946 adrl lr, dvmAsmInstructionStart + (346 * 64) 17947 mov r0, rPC @ arg0 17948 mov r1, rSELF @ arg1 17949 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17950 17951/* ------------------------------ */ 17952 .balign 64 17953.L_ALT_OP_UNUSED_5BFF: /* 0x15b */ 17954/* File: armv5te/alt_stub.S */ 17955/* 17956 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17957 * any interesting requests and then jump to the real instruction 17958 * handler. Note that the call to dvmCheckInst is done as a tail call. 17959 */ 17960 adrl lr, dvmAsmInstructionStart + (347 * 64) 17961 mov r0, rPC @ arg0 17962 mov r1, rSELF @ arg1 17963 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17964 17965/* ------------------------------ */ 17966 .balign 64 17967.L_ALT_OP_UNUSED_5CFF: /* 0x15c */ 17968/* File: armv5te/alt_stub.S */ 17969/* 17970 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17971 * any interesting requests and then jump to the real instruction 17972 * handler. Note that the call to dvmCheckInst is done as a tail call. 17973 */ 17974 adrl lr, dvmAsmInstructionStart + (348 * 64) 17975 mov r0, rPC @ arg0 17976 mov r1, rSELF @ arg1 17977 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17978 17979/* ------------------------------ */ 17980 .balign 64 17981.L_ALT_OP_UNUSED_5DFF: /* 0x15d */ 17982/* File: armv5te/alt_stub.S */ 17983/* 17984 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17985 * any interesting requests and then jump to the real instruction 17986 * handler. Note that the call to dvmCheckInst is done as a tail call. 17987 */ 17988 adrl lr, dvmAsmInstructionStart + (349 * 64) 17989 mov r0, rPC @ arg0 17990 mov r1, rSELF @ arg1 17991 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17992 17993/* ------------------------------ */ 17994 .balign 64 17995.L_ALT_OP_UNUSED_5EFF: /* 0x15e */ 17996/* File: armv5te/alt_stub.S */ 17997/* 17998 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17999 * any interesting requests and then jump to the real instruction 18000 * handler. Note that the call to dvmCheckInst is done as a tail call. 18001 */ 18002 adrl lr, dvmAsmInstructionStart + (350 * 64) 18003 mov r0, rPC @ arg0 18004 mov r1, rSELF @ arg1 18005 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18006 18007/* ------------------------------ */ 18008 .balign 64 18009.L_ALT_OP_UNUSED_5FFF: /* 0x15f */ 18010/* File: armv5te/alt_stub.S */ 18011/* 18012 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18013 * any interesting requests and then jump to the real instruction 18014 * handler. Note that the call to dvmCheckInst is done as a tail call. 18015 */ 18016 adrl lr, dvmAsmInstructionStart + (351 * 64) 18017 mov r0, rPC @ arg0 18018 mov r1, rSELF @ arg1 18019 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18020 18021/* ------------------------------ */ 18022 .balign 64 18023.L_ALT_OP_UNUSED_60FF: /* 0x160 */ 18024/* File: armv5te/alt_stub.S */ 18025/* 18026 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18027 * any interesting requests and then jump to the real instruction 18028 * handler. Note that the call to dvmCheckInst is done as a tail call. 18029 */ 18030 adrl lr, dvmAsmInstructionStart + (352 * 64) 18031 mov r0, rPC @ arg0 18032 mov r1, rSELF @ arg1 18033 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18034 18035/* ------------------------------ */ 18036 .balign 64 18037.L_ALT_OP_UNUSED_61FF: /* 0x161 */ 18038/* File: armv5te/alt_stub.S */ 18039/* 18040 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18041 * any interesting requests and then jump to the real instruction 18042 * handler. Note that the call to dvmCheckInst is done as a tail call. 18043 */ 18044 adrl lr, dvmAsmInstructionStart + (353 * 64) 18045 mov r0, rPC @ arg0 18046 mov r1, rSELF @ arg1 18047 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18048 18049/* ------------------------------ */ 18050 .balign 64 18051.L_ALT_OP_UNUSED_62FF: /* 0x162 */ 18052/* File: armv5te/alt_stub.S */ 18053/* 18054 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18055 * any interesting requests and then jump to the real instruction 18056 * handler. Note that the call to dvmCheckInst is done as a tail call. 18057 */ 18058 adrl lr, dvmAsmInstructionStart + (354 * 64) 18059 mov r0, rPC @ arg0 18060 mov r1, rSELF @ arg1 18061 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18062 18063/* ------------------------------ */ 18064 .balign 64 18065.L_ALT_OP_UNUSED_63FF: /* 0x163 */ 18066/* File: armv5te/alt_stub.S */ 18067/* 18068 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18069 * any interesting requests and then jump to the real instruction 18070 * handler. Note that the call to dvmCheckInst is done as a tail call. 18071 */ 18072 adrl lr, dvmAsmInstructionStart + (355 * 64) 18073 mov r0, rPC @ arg0 18074 mov r1, rSELF @ arg1 18075 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18076 18077/* ------------------------------ */ 18078 .balign 64 18079.L_ALT_OP_UNUSED_64FF: /* 0x164 */ 18080/* File: armv5te/alt_stub.S */ 18081/* 18082 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18083 * any interesting requests and then jump to the real instruction 18084 * handler. Note that the call to dvmCheckInst is done as a tail call. 18085 */ 18086 adrl lr, dvmAsmInstructionStart + (356 * 64) 18087 mov r0, rPC @ arg0 18088 mov r1, rSELF @ arg1 18089 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18090 18091/* ------------------------------ */ 18092 .balign 64 18093.L_ALT_OP_UNUSED_65FF: /* 0x165 */ 18094/* File: armv5te/alt_stub.S */ 18095/* 18096 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18097 * any interesting requests and then jump to the real instruction 18098 * handler. Note that the call to dvmCheckInst is done as a tail call. 18099 */ 18100 adrl lr, dvmAsmInstructionStart + (357 * 64) 18101 mov r0, rPC @ arg0 18102 mov r1, rSELF @ arg1 18103 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18104 18105/* ------------------------------ */ 18106 .balign 64 18107.L_ALT_OP_UNUSED_66FF: /* 0x166 */ 18108/* File: armv5te/alt_stub.S */ 18109/* 18110 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18111 * any interesting requests and then jump to the real instruction 18112 * handler. Note that the call to dvmCheckInst is done as a tail call. 18113 */ 18114 adrl lr, dvmAsmInstructionStart + (358 * 64) 18115 mov r0, rPC @ arg0 18116 mov r1, rSELF @ arg1 18117 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18118 18119/* ------------------------------ */ 18120 .balign 64 18121.L_ALT_OP_UNUSED_67FF: /* 0x167 */ 18122/* File: armv5te/alt_stub.S */ 18123/* 18124 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18125 * any interesting requests and then jump to the real instruction 18126 * handler. Note that the call to dvmCheckInst is done as a tail call. 18127 */ 18128 adrl lr, dvmAsmInstructionStart + (359 * 64) 18129 mov r0, rPC @ arg0 18130 mov r1, rSELF @ arg1 18131 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18132 18133/* ------------------------------ */ 18134 .balign 64 18135.L_ALT_OP_UNUSED_68FF: /* 0x168 */ 18136/* File: armv5te/alt_stub.S */ 18137/* 18138 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18139 * any interesting requests and then jump to the real instruction 18140 * handler. Note that the call to dvmCheckInst is done as a tail call. 18141 */ 18142 adrl lr, dvmAsmInstructionStart + (360 * 64) 18143 mov r0, rPC @ arg0 18144 mov r1, rSELF @ arg1 18145 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18146 18147/* ------------------------------ */ 18148 .balign 64 18149.L_ALT_OP_UNUSED_69FF: /* 0x169 */ 18150/* File: armv5te/alt_stub.S */ 18151/* 18152 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18153 * any interesting requests and then jump to the real instruction 18154 * handler. Note that the call to dvmCheckInst is done as a tail call. 18155 */ 18156 adrl lr, dvmAsmInstructionStart + (361 * 64) 18157 mov r0, rPC @ arg0 18158 mov r1, rSELF @ arg1 18159 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18160 18161/* ------------------------------ */ 18162 .balign 64 18163.L_ALT_OP_UNUSED_6AFF: /* 0x16a */ 18164/* File: armv5te/alt_stub.S */ 18165/* 18166 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18167 * any interesting requests and then jump to the real instruction 18168 * handler. Note that the call to dvmCheckInst is done as a tail call. 18169 */ 18170 adrl lr, dvmAsmInstructionStart + (362 * 64) 18171 mov r0, rPC @ arg0 18172 mov r1, rSELF @ arg1 18173 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18174 18175/* ------------------------------ */ 18176 .balign 64 18177.L_ALT_OP_UNUSED_6BFF: /* 0x16b */ 18178/* File: armv5te/alt_stub.S */ 18179/* 18180 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18181 * any interesting requests and then jump to the real instruction 18182 * handler. Note that the call to dvmCheckInst is done as a tail call. 18183 */ 18184 adrl lr, dvmAsmInstructionStart + (363 * 64) 18185 mov r0, rPC @ arg0 18186 mov r1, rSELF @ arg1 18187 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18188 18189/* ------------------------------ */ 18190 .balign 64 18191.L_ALT_OP_UNUSED_6CFF: /* 0x16c */ 18192/* File: armv5te/alt_stub.S */ 18193/* 18194 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18195 * any interesting requests and then jump to the real instruction 18196 * handler. Note that the call to dvmCheckInst is done as a tail call. 18197 */ 18198 adrl lr, dvmAsmInstructionStart + (364 * 64) 18199 mov r0, rPC @ arg0 18200 mov r1, rSELF @ arg1 18201 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18202 18203/* ------------------------------ */ 18204 .balign 64 18205.L_ALT_OP_UNUSED_6DFF: /* 0x16d */ 18206/* File: armv5te/alt_stub.S */ 18207/* 18208 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18209 * any interesting requests and then jump to the real instruction 18210 * handler. Note that the call to dvmCheckInst is done as a tail call. 18211 */ 18212 adrl lr, dvmAsmInstructionStart + (365 * 64) 18213 mov r0, rPC @ arg0 18214 mov r1, rSELF @ arg1 18215 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18216 18217/* ------------------------------ */ 18218 .balign 64 18219.L_ALT_OP_UNUSED_6EFF: /* 0x16e */ 18220/* File: armv5te/alt_stub.S */ 18221/* 18222 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18223 * any interesting requests and then jump to the real instruction 18224 * handler. Note that the call to dvmCheckInst is done as a tail call. 18225 */ 18226 adrl lr, dvmAsmInstructionStart + (366 * 64) 18227 mov r0, rPC @ arg0 18228 mov r1, rSELF @ arg1 18229 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18230 18231/* ------------------------------ */ 18232 .balign 64 18233.L_ALT_OP_UNUSED_6FFF: /* 0x16f */ 18234/* File: armv5te/alt_stub.S */ 18235/* 18236 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18237 * any interesting requests and then jump to the real instruction 18238 * handler. Note that the call to dvmCheckInst is done as a tail call. 18239 */ 18240 adrl lr, dvmAsmInstructionStart + (367 * 64) 18241 mov r0, rPC @ arg0 18242 mov r1, rSELF @ arg1 18243 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18244 18245/* ------------------------------ */ 18246 .balign 64 18247.L_ALT_OP_UNUSED_70FF: /* 0x170 */ 18248/* File: armv5te/alt_stub.S */ 18249/* 18250 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18251 * any interesting requests and then jump to the real instruction 18252 * handler. Note that the call to dvmCheckInst is done as a tail call. 18253 */ 18254 adrl lr, dvmAsmInstructionStart + (368 * 64) 18255 mov r0, rPC @ arg0 18256 mov r1, rSELF @ arg1 18257 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18258 18259/* ------------------------------ */ 18260 .balign 64 18261.L_ALT_OP_UNUSED_71FF: /* 0x171 */ 18262/* File: armv5te/alt_stub.S */ 18263/* 18264 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18265 * any interesting requests and then jump to the real instruction 18266 * handler. Note that the call to dvmCheckInst is done as a tail call. 18267 */ 18268 adrl lr, dvmAsmInstructionStart + (369 * 64) 18269 mov r0, rPC @ arg0 18270 mov r1, rSELF @ arg1 18271 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18272 18273/* ------------------------------ */ 18274 .balign 64 18275.L_ALT_OP_UNUSED_72FF: /* 0x172 */ 18276/* File: armv5te/alt_stub.S */ 18277/* 18278 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18279 * any interesting requests and then jump to the real instruction 18280 * handler. Note that the call to dvmCheckInst is done as a tail call. 18281 */ 18282 adrl lr, dvmAsmInstructionStart + (370 * 64) 18283 mov r0, rPC @ arg0 18284 mov r1, rSELF @ arg1 18285 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18286 18287/* ------------------------------ */ 18288 .balign 64 18289.L_ALT_OP_UNUSED_73FF: /* 0x173 */ 18290/* File: armv5te/alt_stub.S */ 18291/* 18292 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18293 * any interesting requests and then jump to the real instruction 18294 * handler. Note that the call to dvmCheckInst is done as a tail call. 18295 */ 18296 adrl lr, dvmAsmInstructionStart + (371 * 64) 18297 mov r0, rPC @ arg0 18298 mov r1, rSELF @ arg1 18299 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18300 18301/* ------------------------------ */ 18302 .balign 64 18303.L_ALT_OP_UNUSED_74FF: /* 0x174 */ 18304/* File: armv5te/alt_stub.S */ 18305/* 18306 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18307 * any interesting requests and then jump to the real instruction 18308 * handler. Note that the call to dvmCheckInst is done as a tail call. 18309 */ 18310 adrl lr, dvmAsmInstructionStart + (372 * 64) 18311 mov r0, rPC @ arg0 18312 mov r1, rSELF @ arg1 18313 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18314 18315/* ------------------------------ */ 18316 .balign 64 18317.L_ALT_OP_UNUSED_75FF: /* 0x175 */ 18318/* File: armv5te/alt_stub.S */ 18319/* 18320 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18321 * any interesting requests and then jump to the real instruction 18322 * handler. Note that the call to dvmCheckInst is done as a tail call. 18323 */ 18324 adrl lr, dvmAsmInstructionStart + (373 * 64) 18325 mov r0, rPC @ arg0 18326 mov r1, rSELF @ arg1 18327 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18328 18329/* ------------------------------ */ 18330 .balign 64 18331.L_ALT_OP_UNUSED_76FF: /* 0x176 */ 18332/* File: armv5te/alt_stub.S */ 18333/* 18334 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18335 * any interesting requests and then jump to the real instruction 18336 * handler. Note that the call to dvmCheckInst is done as a tail call. 18337 */ 18338 adrl lr, dvmAsmInstructionStart + (374 * 64) 18339 mov r0, rPC @ arg0 18340 mov r1, rSELF @ arg1 18341 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18342 18343/* ------------------------------ */ 18344 .balign 64 18345.L_ALT_OP_UNUSED_77FF: /* 0x177 */ 18346/* File: armv5te/alt_stub.S */ 18347/* 18348 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18349 * any interesting requests and then jump to the real instruction 18350 * handler. Note that the call to dvmCheckInst is done as a tail call. 18351 */ 18352 adrl lr, dvmAsmInstructionStart + (375 * 64) 18353 mov r0, rPC @ arg0 18354 mov r1, rSELF @ arg1 18355 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18356 18357/* ------------------------------ */ 18358 .balign 64 18359.L_ALT_OP_UNUSED_78FF: /* 0x178 */ 18360/* File: armv5te/alt_stub.S */ 18361/* 18362 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18363 * any interesting requests and then jump to the real instruction 18364 * handler. Note that the call to dvmCheckInst is done as a tail call. 18365 */ 18366 adrl lr, dvmAsmInstructionStart + (376 * 64) 18367 mov r0, rPC @ arg0 18368 mov r1, rSELF @ arg1 18369 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18370 18371/* ------------------------------ */ 18372 .balign 64 18373.L_ALT_OP_UNUSED_79FF: /* 0x179 */ 18374/* File: armv5te/alt_stub.S */ 18375/* 18376 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18377 * any interesting requests and then jump to the real instruction 18378 * handler. Note that the call to dvmCheckInst is done as a tail call. 18379 */ 18380 adrl lr, dvmAsmInstructionStart + (377 * 64) 18381 mov r0, rPC @ arg0 18382 mov r1, rSELF @ arg1 18383 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18384 18385/* ------------------------------ */ 18386 .balign 64 18387.L_ALT_OP_UNUSED_7AFF: /* 0x17a */ 18388/* File: armv5te/alt_stub.S */ 18389/* 18390 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18391 * any interesting requests and then jump to the real instruction 18392 * handler. Note that the call to dvmCheckInst is done as a tail call. 18393 */ 18394 adrl lr, dvmAsmInstructionStart + (378 * 64) 18395 mov r0, rPC @ arg0 18396 mov r1, rSELF @ arg1 18397 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18398 18399/* ------------------------------ */ 18400 .balign 64 18401.L_ALT_OP_UNUSED_7BFF: /* 0x17b */ 18402/* File: armv5te/alt_stub.S */ 18403/* 18404 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18405 * any interesting requests and then jump to the real instruction 18406 * handler. Note that the call to dvmCheckInst is done as a tail call. 18407 */ 18408 adrl lr, dvmAsmInstructionStart + (379 * 64) 18409 mov r0, rPC @ arg0 18410 mov r1, rSELF @ arg1 18411 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18412 18413/* ------------------------------ */ 18414 .balign 64 18415.L_ALT_OP_UNUSED_7CFF: /* 0x17c */ 18416/* File: armv5te/alt_stub.S */ 18417/* 18418 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18419 * any interesting requests and then jump to the real instruction 18420 * handler. Note that the call to dvmCheckInst is done as a tail call. 18421 */ 18422 adrl lr, dvmAsmInstructionStart + (380 * 64) 18423 mov r0, rPC @ arg0 18424 mov r1, rSELF @ arg1 18425 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18426 18427/* ------------------------------ */ 18428 .balign 64 18429.L_ALT_OP_UNUSED_7DFF: /* 0x17d */ 18430/* File: armv5te/alt_stub.S */ 18431/* 18432 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18433 * any interesting requests and then jump to the real instruction 18434 * handler. Note that the call to dvmCheckInst is done as a tail call. 18435 */ 18436 adrl lr, dvmAsmInstructionStart + (381 * 64) 18437 mov r0, rPC @ arg0 18438 mov r1, rSELF @ arg1 18439 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18440 18441/* ------------------------------ */ 18442 .balign 64 18443.L_ALT_OP_UNUSED_7EFF: /* 0x17e */ 18444/* File: armv5te/alt_stub.S */ 18445/* 18446 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18447 * any interesting requests and then jump to the real instruction 18448 * handler. Note that the call to dvmCheckInst is done as a tail call. 18449 */ 18450 adrl lr, dvmAsmInstructionStart + (382 * 64) 18451 mov r0, rPC @ arg0 18452 mov r1, rSELF @ arg1 18453 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18454 18455/* ------------------------------ */ 18456 .balign 64 18457.L_ALT_OP_UNUSED_7FFF: /* 0x17f */ 18458/* File: armv5te/alt_stub.S */ 18459/* 18460 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18461 * any interesting requests and then jump to the real instruction 18462 * handler. Note that the call to dvmCheckInst is done as a tail call. 18463 */ 18464 adrl lr, dvmAsmInstructionStart + (383 * 64) 18465 mov r0, rPC @ arg0 18466 mov r1, rSELF @ arg1 18467 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18468 18469/* ------------------------------ */ 18470 .balign 64 18471.L_ALT_OP_UNUSED_80FF: /* 0x180 */ 18472/* File: armv5te/alt_stub.S */ 18473/* 18474 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18475 * any interesting requests and then jump to the real instruction 18476 * handler. Note that the call to dvmCheckInst is done as a tail call. 18477 */ 18478 adrl lr, dvmAsmInstructionStart + (384 * 64) 18479 mov r0, rPC @ arg0 18480 mov r1, rSELF @ arg1 18481 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18482 18483/* ------------------------------ */ 18484 .balign 64 18485.L_ALT_OP_UNUSED_81FF: /* 0x181 */ 18486/* File: armv5te/alt_stub.S */ 18487/* 18488 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18489 * any interesting requests and then jump to the real instruction 18490 * handler. Note that the call to dvmCheckInst is done as a tail call. 18491 */ 18492 adrl lr, dvmAsmInstructionStart + (385 * 64) 18493 mov r0, rPC @ arg0 18494 mov r1, rSELF @ arg1 18495 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18496 18497/* ------------------------------ */ 18498 .balign 64 18499.L_ALT_OP_UNUSED_82FF: /* 0x182 */ 18500/* File: armv5te/alt_stub.S */ 18501/* 18502 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18503 * any interesting requests and then jump to the real instruction 18504 * handler. Note that the call to dvmCheckInst is done as a tail call. 18505 */ 18506 adrl lr, dvmAsmInstructionStart + (386 * 64) 18507 mov r0, rPC @ arg0 18508 mov r1, rSELF @ arg1 18509 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18510 18511/* ------------------------------ */ 18512 .balign 64 18513.L_ALT_OP_UNUSED_83FF: /* 0x183 */ 18514/* File: armv5te/alt_stub.S */ 18515/* 18516 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18517 * any interesting requests and then jump to the real instruction 18518 * handler. Note that the call to dvmCheckInst is done as a tail call. 18519 */ 18520 adrl lr, dvmAsmInstructionStart + (387 * 64) 18521 mov r0, rPC @ arg0 18522 mov r1, rSELF @ arg1 18523 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18524 18525/* ------------------------------ */ 18526 .balign 64 18527.L_ALT_OP_UNUSED_84FF: /* 0x184 */ 18528/* File: armv5te/alt_stub.S */ 18529/* 18530 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18531 * any interesting requests and then jump to the real instruction 18532 * handler. Note that the call to dvmCheckInst is done as a tail call. 18533 */ 18534 adrl lr, dvmAsmInstructionStart + (388 * 64) 18535 mov r0, rPC @ arg0 18536 mov r1, rSELF @ arg1 18537 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18538 18539/* ------------------------------ */ 18540 .balign 64 18541.L_ALT_OP_UNUSED_85FF: /* 0x185 */ 18542/* File: armv5te/alt_stub.S */ 18543/* 18544 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18545 * any interesting requests and then jump to the real instruction 18546 * handler. Note that the call to dvmCheckInst is done as a tail call. 18547 */ 18548 adrl lr, dvmAsmInstructionStart + (389 * 64) 18549 mov r0, rPC @ arg0 18550 mov r1, rSELF @ arg1 18551 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18552 18553/* ------------------------------ */ 18554 .balign 64 18555.L_ALT_OP_UNUSED_86FF: /* 0x186 */ 18556/* File: armv5te/alt_stub.S */ 18557/* 18558 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18559 * any interesting requests and then jump to the real instruction 18560 * handler. Note that the call to dvmCheckInst is done as a tail call. 18561 */ 18562 adrl lr, dvmAsmInstructionStart + (390 * 64) 18563 mov r0, rPC @ arg0 18564 mov r1, rSELF @ arg1 18565 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18566 18567/* ------------------------------ */ 18568 .balign 64 18569.L_ALT_OP_UNUSED_87FF: /* 0x187 */ 18570/* File: armv5te/alt_stub.S */ 18571/* 18572 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18573 * any interesting requests and then jump to the real instruction 18574 * handler. Note that the call to dvmCheckInst is done as a tail call. 18575 */ 18576 adrl lr, dvmAsmInstructionStart + (391 * 64) 18577 mov r0, rPC @ arg0 18578 mov r1, rSELF @ arg1 18579 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18580 18581/* ------------------------------ */ 18582 .balign 64 18583.L_ALT_OP_UNUSED_88FF: /* 0x188 */ 18584/* File: armv5te/alt_stub.S */ 18585/* 18586 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18587 * any interesting requests and then jump to the real instruction 18588 * handler. Note that the call to dvmCheckInst is done as a tail call. 18589 */ 18590 adrl lr, dvmAsmInstructionStart + (392 * 64) 18591 mov r0, rPC @ arg0 18592 mov r1, rSELF @ arg1 18593 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18594 18595/* ------------------------------ */ 18596 .balign 64 18597.L_ALT_OP_UNUSED_89FF: /* 0x189 */ 18598/* File: armv5te/alt_stub.S */ 18599/* 18600 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18601 * any interesting requests and then jump to the real instruction 18602 * handler. Note that the call to dvmCheckInst is done as a tail call. 18603 */ 18604 adrl lr, dvmAsmInstructionStart + (393 * 64) 18605 mov r0, rPC @ arg0 18606 mov r1, rSELF @ arg1 18607 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18608 18609/* ------------------------------ */ 18610 .balign 64 18611.L_ALT_OP_UNUSED_8AFF: /* 0x18a */ 18612/* File: armv5te/alt_stub.S */ 18613/* 18614 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18615 * any interesting requests and then jump to the real instruction 18616 * handler. Note that the call to dvmCheckInst is done as a tail call. 18617 */ 18618 adrl lr, dvmAsmInstructionStart + (394 * 64) 18619 mov r0, rPC @ arg0 18620 mov r1, rSELF @ arg1 18621 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18622 18623/* ------------------------------ */ 18624 .balign 64 18625.L_ALT_OP_UNUSED_8BFF: /* 0x18b */ 18626/* File: armv5te/alt_stub.S */ 18627/* 18628 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18629 * any interesting requests and then jump to the real instruction 18630 * handler. Note that the call to dvmCheckInst is done as a tail call. 18631 */ 18632 adrl lr, dvmAsmInstructionStart + (395 * 64) 18633 mov r0, rPC @ arg0 18634 mov r1, rSELF @ arg1 18635 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18636 18637/* ------------------------------ */ 18638 .balign 64 18639.L_ALT_OP_UNUSED_8CFF: /* 0x18c */ 18640/* File: armv5te/alt_stub.S */ 18641/* 18642 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18643 * any interesting requests and then jump to the real instruction 18644 * handler. Note that the call to dvmCheckInst is done as a tail call. 18645 */ 18646 adrl lr, dvmAsmInstructionStart + (396 * 64) 18647 mov r0, rPC @ arg0 18648 mov r1, rSELF @ arg1 18649 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18650 18651/* ------------------------------ */ 18652 .balign 64 18653.L_ALT_OP_UNUSED_8DFF: /* 0x18d */ 18654/* File: armv5te/alt_stub.S */ 18655/* 18656 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18657 * any interesting requests and then jump to the real instruction 18658 * handler. Note that the call to dvmCheckInst is done as a tail call. 18659 */ 18660 adrl lr, dvmAsmInstructionStart + (397 * 64) 18661 mov r0, rPC @ arg0 18662 mov r1, rSELF @ arg1 18663 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18664 18665/* ------------------------------ */ 18666 .balign 64 18667.L_ALT_OP_UNUSED_8EFF: /* 0x18e */ 18668/* File: armv5te/alt_stub.S */ 18669/* 18670 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18671 * any interesting requests and then jump to the real instruction 18672 * handler. Note that the call to dvmCheckInst is done as a tail call. 18673 */ 18674 adrl lr, dvmAsmInstructionStart + (398 * 64) 18675 mov r0, rPC @ arg0 18676 mov r1, rSELF @ arg1 18677 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18678 18679/* ------------------------------ */ 18680 .balign 64 18681.L_ALT_OP_UNUSED_8FFF: /* 0x18f */ 18682/* File: armv5te/alt_stub.S */ 18683/* 18684 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18685 * any interesting requests and then jump to the real instruction 18686 * handler. Note that the call to dvmCheckInst is done as a tail call. 18687 */ 18688 adrl lr, dvmAsmInstructionStart + (399 * 64) 18689 mov r0, rPC @ arg0 18690 mov r1, rSELF @ arg1 18691 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18692 18693/* ------------------------------ */ 18694 .balign 64 18695.L_ALT_OP_UNUSED_90FF: /* 0x190 */ 18696/* File: armv5te/alt_stub.S */ 18697/* 18698 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18699 * any interesting requests and then jump to the real instruction 18700 * handler. Note that the call to dvmCheckInst is done as a tail call. 18701 */ 18702 adrl lr, dvmAsmInstructionStart + (400 * 64) 18703 mov r0, rPC @ arg0 18704 mov r1, rSELF @ arg1 18705 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18706 18707/* ------------------------------ */ 18708 .balign 64 18709.L_ALT_OP_UNUSED_91FF: /* 0x191 */ 18710/* File: armv5te/alt_stub.S */ 18711/* 18712 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18713 * any interesting requests and then jump to the real instruction 18714 * handler. Note that the call to dvmCheckInst is done as a tail call. 18715 */ 18716 adrl lr, dvmAsmInstructionStart + (401 * 64) 18717 mov r0, rPC @ arg0 18718 mov r1, rSELF @ arg1 18719 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18720 18721/* ------------------------------ */ 18722 .balign 64 18723.L_ALT_OP_UNUSED_92FF: /* 0x192 */ 18724/* File: armv5te/alt_stub.S */ 18725/* 18726 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18727 * any interesting requests and then jump to the real instruction 18728 * handler. Note that the call to dvmCheckInst is done as a tail call. 18729 */ 18730 adrl lr, dvmAsmInstructionStart + (402 * 64) 18731 mov r0, rPC @ arg0 18732 mov r1, rSELF @ arg1 18733 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18734 18735/* ------------------------------ */ 18736 .balign 64 18737.L_ALT_OP_UNUSED_93FF: /* 0x193 */ 18738/* File: armv5te/alt_stub.S */ 18739/* 18740 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18741 * any interesting requests and then jump to the real instruction 18742 * handler. Note that the call to dvmCheckInst is done as a tail call. 18743 */ 18744 adrl lr, dvmAsmInstructionStart + (403 * 64) 18745 mov r0, rPC @ arg0 18746 mov r1, rSELF @ arg1 18747 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18748 18749/* ------------------------------ */ 18750 .balign 64 18751.L_ALT_OP_UNUSED_94FF: /* 0x194 */ 18752/* File: armv5te/alt_stub.S */ 18753/* 18754 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18755 * any interesting requests and then jump to the real instruction 18756 * handler. Note that the call to dvmCheckInst is done as a tail call. 18757 */ 18758 adrl lr, dvmAsmInstructionStart + (404 * 64) 18759 mov r0, rPC @ arg0 18760 mov r1, rSELF @ arg1 18761 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18762 18763/* ------------------------------ */ 18764 .balign 64 18765.L_ALT_OP_UNUSED_95FF: /* 0x195 */ 18766/* File: armv5te/alt_stub.S */ 18767/* 18768 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18769 * any interesting requests and then jump to the real instruction 18770 * handler. Note that the call to dvmCheckInst is done as a tail call. 18771 */ 18772 adrl lr, dvmAsmInstructionStart + (405 * 64) 18773 mov r0, rPC @ arg0 18774 mov r1, rSELF @ arg1 18775 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18776 18777/* ------------------------------ */ 18778 .balign 64 18779.L_ALT_OP_UNUSED_96FF: /* 0x196 */ 18780/* File: armv5te/alt_stub.S */ 18781/* 18782 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18783 * any interesting requests and then jump to the real instruction 18784 * handler. Note that the call to dvmCheckInst is done as a tail call. 18785 */ 18786 adrl lr, dvmAsmInstructionStart + (406 * 64) 18787 mov r0, rPC @ arg0 18788 mov r1, rSELF @ arg1 18789 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18790 18791/* ------------------------------ */ 18792 .balign 64 18793.L_ALT_OP_UNUSED_97FF: /* 0x197 */ 18794/* File: armv5te/alt_stub.S */ 18795/* 18796 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18797 * any interesting requests and then jump to the real instruction 18798 * handler. Note that the call to dvmCheckInst is done as a tail call. 18799 */ 18800 adrl lr, dvmAsmInstructionStart + (407 * 64) 18801 mov r0, rPC @ arg0 18802 mov r1, rSELF @ arg1 18803 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18804 18805/* ------------------------------ */ 18806 .balign 64 18807.L_ALT_OP_UNUSED_98FF: /* 0x198 */ 18808/* File: armv5te/alt_stub.S */ 18809/* 18810 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18811 * any interesting requests and then jump to the real instruction 18812 * handler. Note that the call to dvmCheckInst is done as a tail call. 18813 */ 18814 adrl lr, dvmAsmInstructionStart + (408 * 64) 18815 mov r0, rPC @ arg0 18816 mov r1, rSELF @ arg1 18817 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18818 18819/* ------------------------------ */ 18820 .balign 64 18821.L_ALT_OP_UNUSED_99FF: /* 0x199 */ 18822/* File: armv5te/alt_stub.S */ 18823/* 18824 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18825 * any interesting requests and then jump to the real instruction 18826 * handler. Note that the call to dvmCheckInst is done as a tail call. 18827 */ 18828 adrl lr, dvmAsmInstructionStart + (409 * 64) 18829 mov r0, rPC @ arg0 18830 mov r1, rSELF @ arg1 18831 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18832 18833/* ------------------------------ */ 18834 .balign 64 18835.L_ALT_OP_UNUSED_9AFF: /* 0x19a */ 18836/* File: armv5te/alt_stub.S */ 18837/* 18838 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18839 * any interesting requests and then jump to the real instruction 18840 * handler. Note that the call to dvmCheckInst is done as a tail call. 18841 */ 18842 adrl lr, dvmAsmInstructionStart + (410 * 64) 18843 mov r0, rPC @ arg0 18844 mov r1, rSELF @ arg1 18845 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18846 18847/* ------------------------------ */ 18848 .balign 64 18849.L_ALT_OP_UNUSED_9BFF: /* 0x19b */ 18850/* File: armv5te/alt_stub.S */ 18851/* 18852 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18853 * any interesting requests and then jump to the real instruction 18854 * handler. Note that the call to dvmCheckInst is done as a tail call. 18855 */ 18856 adrl lr, dvmAsmInstructionStart + (411 * 64) 18857 mov r0, rPC @ arg0 18858 mov r1, rSELF @ arg1 18859 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18860 18861/* ------------------------------ */ 18862 .balign 64 18863.L_ALT_OP_UNUSED_9CFF: /* 0x19c */ 18864/* File: armv5te/alt_stub.S */ 18865/* 18866 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18867 * any interesting requests and then jump to the real instruction 18868 * handler. Note that the call to dvmCheckInst is done as a tail call. 18869 */ 18870 adrl lr, dvmAsmInstructionStart + (412 * 64) 18871 mov r0, rPC @ arg0 18872 mov r1, rSELF @ arg1 18873 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18874 18875/* ------------------------------ */ 18876 .balign 64 18877.L_ALT_OP_UNUSED_9DFF: /* 0x19d */ 18878/* File: armv5te/alt_stub.S */ 18879/* 18880 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18881 * any interesting requests and then jump to the real instruction 18882 * handler. Note that the call to dvmCheckInst is done as a tail call. 18883 */ 18884 adrl lr, dvmAsmInstructionStart + (413 * 64) 18885 mov r0, rPC @ arg0 18886 mov r1, rSELF @ arg1 18887 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18888 18889/* ------------------------------ */ 18890 .balign 64 18891.L_ALT_OP_UNUSED_9EFF: /* 0x19e */ 18892/* File: armv5te/alt_stub.S */ 18893/* 18894 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18895 * any interesting requests and then jump to the real instruction 18896 * handler. Note that the call to dvmCheckInst is done as a tail call. 18897 */ 18898 adrl lr, dvmAsmInstructionStart + (414 * 64) 18899 mov r0, rPC @ arg0 18900 mov r1, rSELF @ arg1 18901 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18902 18903/* ------------------------------ */ 18904 .balign 64 18905.L_ALT_OP_UNUSED_9FFF: /* 0x19f */ 18906/* File: armv5te/alt_stub.S */ 18907/* 18908 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18909 * any interesting requests and then jump to the real instruction 18910 * handler. Note that the call to dvmCheckInst is done as a tail call. 18911 */ 18912 adrl lr, dvmAsmInstructionStart + (415 * 64) 18913 mov r0, rPC @ arg0 18914 mov r1, rSELF @ arg1 18915 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18916 18917/* ------------------------------ */ 18918 .balign 64 18919.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */ 18920/* File: armv5te/alt_stub.S */ 18921/* 18922 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18923 * any interesting requests and then jump to the real instruction 18924 * handler. Note that the call to dvmCheckInst is done as a tail call. 18925 */ 18926 adrl lr, dvmAsmInstructionStart + (416 * 64) 18927 mov r0, rPC @ arg0 18928 mov r1, rSELF @ arg1 18929 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18930 18931/* ------------------------------ */ 18932 .balign 64 18933.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */ 18934/* File: armv5te/alt_stub.S */ 18935/* 18936 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18937 * any interesting requests and then jump to the real instruction 18938 * handler. Note that the call to dvmCheckInst is done as a tail call. 18939 */ 18940 adrl lr, dvmAsmInstructionStart + (417 * 64) 18941 mov r0, rPC @ arg0 18942 mov r1, rSELF @ arg1 18943 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18944 18945/* ------------------------------ */ 18946 .balign 64 18947.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */ 18948/* File: armv5te/alt_stub.S */ 18949/* 18950 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18951 * any interesting requests and then jump to the real instruction 18952 * handler. Note that the call to dvmCheckInst is done as a tail call. 18953 */ 18954 adrl lr, dvmAsmInstructionStart + (418 * 64) 18955 mov r0, rPC @ arg0 18956 mov r1, rSELF @ arg1 18957 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18958 18959/* ------------------------------ */ 18960 .balign 64 18961.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */ 18962/* File: armv5te/alt_stub.S */ 18963/* 18964 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18965 * any interesting requests and then jump to the real instruction 18966 * handler. Note that the call to dvmCheckInst is done as a tail call. 18967 */ 18968 adrl lr, dvmAsmInstructionStart + (419 * 64) 18969 mov r0, rPC @ arg0 18970 mov r1, rSELF @ arg1 18971 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18972 18973/* ------------------------------ */ 18974 .balign 64 18975.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */ 18976/* File: armv5te/alt_stub.S */ 18977/* 18978 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18979 * any interesting requests and then jump to the real instruction 18980 * handler. Note that the call to dvmCheckInst is done as a tail call. 18981 */ 18982 adrl lr, dvmAsmInstructionStart + (420 * 64) 18983 mov r0, rPC @ arg0 18984 mov r1, rSELF @ arg1 18985 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18986 18987/* ------------------------------ */ 18988 .balign 64 18989.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */ 18990/* File: armv5te/alt_stub.S */ 18991/* 18992 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18993 * any interesting requests and then jump to the real instruction 18994 * handler. Note that the call to dvmCheckInst is done as a tail call. 18995 */ 18996 adrl lr, dvmAsmInstructionStart + (421 * 64) 18997 mov r0, rPC @ arg0 18998 mov r1, rSELF @ arg1 18999 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19000 19001/* ------------------------------ */ 19002 .balign 64 19003.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */ 19004/* File: armv5te/alt_stub.S */ 19005/* 19006 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19007 * any interesting requests and then jump to the real instruction 19008 * handler. Note that the call to dvmCheckInst is done as a tail call. 19009 */ 19010 adrl lr, dvmAsmInstructionStart + (422 * 64) 19011 mov r0, rPC @ arg0 19012 mov r1, rSELF @ arg1 19013 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19014 19015/* ------------------------------ */ 19016 .balign 64 19017.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */ 19018/* File: armv5te/alt_stub.S */ 19019/* 19020 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19021 * any interesting requests and then jump to the real instruction 19022 * handler. Note that the call to dvmCheckInst is done as a tail call. 19023 */ 19024 adrl lr, dvmAsmInstructionStart + (423 * 64) 19025 mov r0, rPC @ arg0 19026 mov r1, rSELF @ arg1 19027 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19028 19029/* ------------------------------ */ 19030 .balign 64 19031.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */ 19032/* File: armv5te/alt_stub.S */ 19033/* 19034 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19035 * any interesting requests and then jump to the real instruction 19036 * handler. Note that the call to dvmCheckInst is done as a tail call. 19037 */ 19038 adrl lr, dvmAsmInstructionStart + (424 * 64) 19039 mov r0, rPC @ arg0 19040 mov r1, rSELF @ arg1 19041 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19042 19043/* ------------------------------ */ 19044 .balign 64 19045.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */ 19046/* File: armv5te/alt_stub.S */ 19047/* 19048 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19049 * any interesting requests and then jump to the real instruction 19050 * handler. Note that the call to dvmCheckInst is done as a tail call. 19051 */ 19052 adrl lr, dvmAsmInstructionStart + (425 * 64) 19053 mov r0, rPC @ arg0 19054 mov r1, rSELF @ arg1 19055 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19056 19057/* ------------------------------ */ 19058 .balign 64 19059.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */ 19060/* File: armv5te/alt_stub.S */ 19061/* 19062 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19063 * any interesting requests and then jump to the real instruction 19064 * handler. Note that the call to dvmCheckInst is done as a tail call. 19065 */ 19066 adrl lr, dvmAsmInstructionStart + (426 * 64) 19067 mov r0, rPC @ arg0 19068 mov r1, rSELF @ arg1 19069 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19070 19071/* ------------------------------ */ 19072 .balign 64 19073.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */ 19074/* File: armv5te/alt_stub.S */ 19075/* 19076 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19077 * any interesting requests and then jump to the real instruction 19078 * handler. Note that the call to dvmCheckInst is done as a tail call. 19079 */ 19080 adrl lr, dvmAsmInstructionStart + (427 * 64) 19081 mov r0, rPC @ arg0 19082 mov r1, rSELF @ arg1 19083 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19084 19085/* ------------------------------ */ 19086 .balign 64 19087.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */ 19088/* File: armv5te/alt_stub.S */ 19089/* 19090 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19091 * any interesting requests and then jump to the real instruction 19092 * handler. Note that the call to dvmCheckInst is done as a tail call. 19093 */ 19094 adrl lr, dvmAsmInstructionStart + (428 * 64) 19095 mov r0, rPC @ arg0 19096 mov r1, rSELF @ arg1 19097 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19098 19099/* ------------------------------ */ 19100 .balign 64 19101.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */ 19102/* File: armv5te/alt_stub.S */ 19103/* 19104 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19105 * any interesting requests and then jump to the real instruction 19106 * handler. Note that the call to dvmCheckInst is done as a tail call. 19107 */ 19108 adrl lr, dvmAsmInstructionStart + (429 * 64) 19109 mov r0, rPC @ arg0 19110 mov r1, rSELF @ arg1 19111 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19112 19113/* ------------------------------ */ 19114 .balign 64 19115.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */ 19116/* File: armv5te/alt_stub.S */ 19117/* 19118 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19119 * any interesting requests and then jump to the real instruction 19120 * handler. Note that the call to dvmCheckInst is done as a tail call. 19121 */ 19122 adrl lr, dvmAsmInstructionStart + (430 * 64) 19123 mov r0, rPC @ arg0 19124 mov r1, rSELF @ arg1 19125 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19126 19127/* ------------------------------ */ 19128 .balign 64 19129.L_ALT_OP_UNUSED_AFFF: /* 0x1af */ 19130/* File: armv5te/alt_stub.S */ 19131/* 19132 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19133 * any interesting requests and then jump to the real instruction 19134 * handler. Note that the call to dvmCheckInst is done as a tail call. 19135 */ 19136 adrl lr, dvmAsmInstructionStart + (431 * 64) 19137 mov r0, rPC @ arg0 19138 mov r1, rSELF @ arg1 19139 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19140 19141/* ------------------------------ */ 19142 .balign 64 19143.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */ 19144/* File: armv5te/alt_stub.S */ 19145/* 19146 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19147 * any interesting requests and then jump to the real instruction 19148 * handler. Note that the call to dvmCheckInst is done as a tail call. 19149 */ 19150 adrl lr, dvmAsmInstructionStart + (432 * 64) 19151 mov r0, rPC @ arg0 19152 mov r1, rSELF @ arg1 19153 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19154 19155/* ------------------------------ */ 19156 .balign 64 19157.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */ 19158/* File: armv5te/alt_stub.S */ 19159/* 19160 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19161 * any interesting requests and then jump to the real instruction 19162 * handler. Note that the call to dvmCheckInst is done as a tail call. 19163 */ 19164 adrl lr, dvmAsmInstructionStart + (433 * 64) 19165 mov r0, rPC @ arg0 19166 mov r1, rSELF @ arg1 19167 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19168 19169/* ------------------------------ */ 19170 .balign 64 19171.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */ 19172/* File: armv5te/alt_stub.S */ 19173/* 19174 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19175 * any interesting requests and then jump to the real instruction 19176 * handler. Note that the call to dvmCheckInst is done as a tail call. 19177 */ 19178 adrl lr, dvmAsmInstructionStart + (434 * 64) 19179 mov r0, rPC @ arg0 19180 mov r1, rSELF @ arg1 19181 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19182 19183/* ------------------------------ */ 19184 .balign 64 19185.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */ 19186/* File: armv5te/alt_stub.S */ 19187/* 19188 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19189 * any interesting requests and then jump to the real instruction 19190 * handler. Note that the call to dvmCheckInst is done as a tail call. 19191 */ 19192 adrl lr, dvmAsmInstructionStart + (435 * 64) 19193 mov r0, rPC @ arg0 19194 mov r1, rSELF @ arg1 19195 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19196 19197/* ------------------------------ */ 19198 .balign 64 19199.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */ 19200/* File: armv5te/alt_stub.S */ 19201/* 19202 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19203 * any interesting requests and then jump to the real instruction 19204 * handler. Note that the call to dvmCheckInst is done as a tail call. 19205 */ 19206 adrl lr, dvmAsmInstructionStart + (436 * 64) 19207 mov r0, rPC @ arg0 19208 mov r1, rSELF @ arg1 19209 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19210 19211/* ------------------------------ */ 19212 .balign 64 19213.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */ 19214/* File: armv5te/alt_stub.S */ 19215/* 19216 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19217 * any interesting requests and then jump to the real instruction 19218 * handler. Note that the call to dvmCheckInst is done as a tail call. 19219 */ 19220 adrl lr, dvmAsmInstructionStart + (437 * 64) 19221 mov r0, rPC @ arg0 19222 mov r1, rSELF @ arg1 19223 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19224 19225/* ------------------------------ */ 19226 .balign 64 19227.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */ 19228/* File: armv5te/alt_stub.S */ 19229/* 19230 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19231 * any interesting requests and then jump to the real instruction 19232 * handler. Note that the call to dvmCheckInst is done as a tail call. 19233 */ 19234 adrl lr, dvmAsmInstructionStart + (438 * 64) 19235 mov r0, rPC @ arg0 19236 mov r1, rSELF @ arg1 19237 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19238 19239/* ------------------------------ */ 19240 .balign 64 19241.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */ 19242/* File: armv5te/alt_stub.S */ 19243/* 19244 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19245 * any interesting requests and then jump to the real instruction 19246 * handler. Note that the call to dvmCheckInst is done as a tail call. 19247 */ 19248 adrl lr, dvmAsmInstructionStart + (439 * 64) 19249 mov r0, rPC @ arg0 19250 mov r1, rSELF @ arg1 19251 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19252 19253/* ------------------------------ */ 19254 .balign 64 19255.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */ 19256/* File: armv5te/alt_stub.S */ 19257/* 19258 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19259 * any interesting requests and then jump to the real instruction 19260 * handler. Note that the call to dvmCheckInst is done as a tail call. 19261 */ 19262 adrl lr, dvmAsmInstructionStart + (440 * 64) 19263 mov r0, rPC @ arg0 19264 mov r1, rSELF @ arg1 19265 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19266 19267/* ------------------------------ */ 19268 .balign 64 19269.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */ 19270/* File: armv5te/alt_stub.S */ 19271/* 19272 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19273 * any interesting requests and then jump to the real instruction 19274 * handler. Note that the call to dvmCheckInst is done as a tail call. 19275 */ 19276 adrl lr, dvmAsmInstructionStart + (441 * 64) 19277 mov r0, rPC @ arg0 19278 mov r1, rSELF @ arg1 19279 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19280 19281/* ------------------------------ */ 19282 .balign 64 19283.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */ 19284/* File: armv5te/alt_stub.S */ 19285/* 19286 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19287 * any interesting requests and then jump to the real instruction 19288 * handler. Note that the call to dvmCheckInst is done as a tail call. 19289 */ 19290 adrl lr, dvmAsmInstructionStart + (442 * 64) 19291 mov r0, rPC @ arg0 19292 mov r1, rSELF @ arg1 19293 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19294 19295/* ------------------------------ */ 19296 .balign 64 19297.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */ 19298/* File: armv5te/alt_stub.S */ 19299/* 19300 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19301 * any interesting requests and then jump to the real instruction 19302 * handler. Note that the call to dvmCheckInst is done as a tail call. 19303 */ 19304 adrl lr, dvmAsmInstructionStart + (443 * 64) 19305 mov r0, rPC @ arg0 19306 mov r1, rSELF @ arg1 19307 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19308 19309/* ------------------------------ */ 19310 .balign 64 19311.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */ 19312/* File: armv5te/alt_stub.S */ 19313/* 19314 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19315 * any interesting requests and then jump to the real instruction 19316 * handler. Note that the call to dvmCheckInst is done as a tail call. 19317 */ 19318 adrl lr, dvmAsmInstructionStart + (444 * 64) 19319 mov r0, rPC @ arg0 19320 mov r1, rSELF @ arg1 19321 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19322 19323/* ------------------------------ */ 19324 .balign 64 19325.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */ 19326/* File: armv5te/alt_stub.S */ 19327/* 19328 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19329 * any interesting requests and then jump to the real instruction 19330 * handler. Note that the call to dvmCheckInst is done as a tail call. 19331 */ 19332 adrl lr, dvmAsmInstructionStart + (445 * 64) 19333 mov r0, rPC @ arg0 19334 mov r1, rSELF @ arg1 19335 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19336 19337/* ------------------------------ */ 19338 .balign 64 19339.L_ALT_OP_UNUSED_BEFF: /* 0x1be */ 19340/* File: armv5te/alt_stub.S */ 19341/* 19342 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19343 * any interesting requests and then jump to the real instruction 19344 * handler. Note that the call to dvmCheckInst is done as a tail call. 19345 */ 19346 adrl lr, dvmAsmInstructionStart + (446 * 64) 19347 mov r0, rPC @ arg0 19348 mov r1, rSELF @ arg1 19349 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19350 19351/* ------------------------------ */ 19352 .balign 64 19353.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */ 19354/* File: armv5te/alt_stub.S */ 19355/* 19356 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19357 * any interesting requests and then jump to the real instruction 19358 * handler. Note that the call to dvmCheckInst is done as a tail call. 19359 */ 19360 adrl lr, dvmAsmInstructionStart + (447 * 64) 19361 mov r0, rPC @ arg0 19362 mov r1, rSELF @ arg1 19363 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19364 19365/* ------------------------------ */ 19366 .balign 64 19367.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */ 19368/* File: armv5te/alt_stub.S */ 19369/* 19370 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19371 * any interesting requests and then jump to the real instruction 19372 * handler. Note that the call to dvmCheckInst is done as a tail call. 19373 */ 19374 adrl lr, dvmAsmInstructionStart + (448 * 64) 19375 mov r0, rPC @ arg0 19376 mov r1, rSELF @ arg1 19377 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19378 19379/* ------------------------------ */ 19380 .balign 64 19381.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */ 19382/* File: armv5te/alt_stub.S */ 19383/* 19384 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19385 * any interesting requests and then jump to the real instruction 19386 * handler. Note that the call to dvmCheckInst is done as a tail call. 19387 */ 19388 adrl lr, dvmAsmInstructionStart + (449 * 64) 19389 mov r0, rPC @ arg0 19390 mov r1, rSELF @ arg1 19391 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19392 19393/* ------------------------------ */ 19394 .balign 64 19395.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */ 19396/* File: armv5te/alt_stub.S */ 19397/* 19398 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19399 * any interesting requests and then jump to the real instruction 19400 * handler. Note that the call to dvmCheckInst is done as a tail call. 19401 */ 19402 adrl lr, dvmAsmInstructionStart + (450 * 64) 19403 mov r0, rPC @ arg0 19404 mov r1, rSELF @ arg1 19405 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19406 19407/* ------------------------------ */ 19408 .balign 64 19409.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */ 19410/* File: armv5te/alt_stub.S */ 19411/* 19412 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19413 * any interesting requests and then jump to the real instruction 19414 * handler. Note that the call to dvmCheckInst is done as a tail call. 19415 */ 19416 adrl lr, dvmAsmInstructionStart + (451 * 64) 19417 mov r0, rPC @ arg0 19418 mov r1, rSELF @ arg1 19419 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19420 19421/* ------------------------------ */ 19422 .balign 64 19423.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */ 19424/* File: armv5te/alt_stub.S */ 19425/* 19426 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19427 * any interesting requests and then jump to the real instruction 19428 * handler. Note that the call to dvmCheckInst is done as a tail call. 19429 */ 19430 adrl lr, dvmAsmInstructionStart + (452 * 64) 19431 mov r0, rPC @ arg0 19432 mov r1, rSELF @ arg1 19433 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19434 19435/* ------------------------------ */ 19436 .balign 64 19437.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */ 19438/* File: armv5te/alt_stub.S */ 19439/* 19440 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19441 * any interesting requests and then jump to the real instruction 19442 * handler. Note that the call to dvmCheckInst is done as a tail call. 19443 */ 19444 adrl lr, dvmAsmInstructionStart + (453 * 64) 19445 mov r0, rPC @ arg0 19446 mov r1, rSELF @ arg1 19447 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19448 19449/* ------------------------------ */ 19450 .balign 64 19451.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */ 19452/* File: armv5te/alt_stub.S */ 19453/* 19454 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19455 * any interesting requests and then jump to the real instruction 19456 * handler. Note that the call to dvmCheckInst is done as a tail call. 19457 */ 19458 adrl lr, dvmAsmInstructionStart + (454 * 64) 19459 mov r0, rPC @ arg0 19460 mov r1, rSELF @ arg1 19461 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19462 19463/* ------------------------------ */ 19464 .balign 64 19465.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */ 19466/* File: armv5te/alt_stub.S */ 19467/* 19468 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19469 * any interesting requests and then jump to the real instruction 19470 * handler. Note that the call to dvmCheckInst is done as a tail call. 19471 */ 19472 adrl lr, dvmAsmInstructionStart + (455 * 64) 19473 mov r0, rPC @ arg0 19474 mov r1, rSELF @ arg1 19475 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19476 19477/* ------------------------------ */ 19478 .balign 64 19479.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */ 19480/* File: armv5te/alt_stub.S */ 19481/* 19482 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19483 * any interesting requests and then jump to the real instruction 19484 * handler. Note that the call to dvmCheckInst is done as a tail call. 19485 */ 19486 adrl lr, dvmAsmInstructionStart + (456 * 64) 19487 mov r0, rPC @ arg0 19488 mov r1, rSELF @ arg1 19489 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19490 19491/* ------------------------------ */ 19492 .balign 64 19493.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */ 19494/* File: armv5te/alt_stub.S */ 19495/* 19496 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19497 * any interesting requests and then jump to the real instruction 19498 * handler. Note that the call to dvmCheckInst is done as a tail call. 19499 */ 19500 adrl lr, dvmAsmInstructionStart + (457 * 64) 19501 mov r0, rPC @ arg0 19502 mov r1, rSELF @ arg1 19503 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19504 19505/* ------------------------------ */ 19506 .balign 64 19507.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */ 19508/* File: armv5te/alt_stub.S */ 19509/* 19510 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19511 * any interesting requests and then jump to the real instruction 19512 * handler. Note that the call to dvmCheckInst is done as a tail call. 19513 */ 19514 adrl lr, dvmAsmInstructionStart + (458 * 64) 19515 mov r0, rPC @ arg0 19516 mov r1, rSELF @ arg1 19517 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19518 19519/* ------------------------------ */ 19520 .balign 64 19521.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */ 19522/* File: armv5te/alt_stub.S */ 19523/* 19524 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19525 * any interesting requests and then jump to the real instruction 19526 * handler. Note that the call to dvmCheckInst is done as a tail call. 19527 */ 19528 adrl lr, dvmAsmInstructionStart + (459 * 64) 19529 mov r0, rPC @ arg0 19530 mov r1, rSELF @ arg1 19531 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19532 19533/* ------------------------------ */ 19534 .balign 64 19535.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */ 19536/* File: armv5te/alt_stub.S */ 19537/* 19538 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19539 * any interesting requests and then jump to the real instruction 19540 * handler. Note that the call to dvmCheckInst is done as a tail call. 19541 */ 19542 adrl lr, dvmAsmInstructionStart + (460 * 64) 19543 mov r0, rPC @ arg0 19544 mov r1, rSELF @ arg1 19545 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19546 19547/* ------------------------------ */ 19548 .balign 64 19549.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */ 19550/* File: armv5te/alt_stub.S */ 19551/* 19552 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19553 * any interesting requests and then jump to the real instruction 19554 * handler. Note that the call to dvmCheckInst is done as a tail call. 19555 */ 19556 adrl lr, dvmAsmInstructionStart + (461 * 64) 19557 mov r0, rPC @ arg0 19558 mov r1, rSELF @ arg1 19559 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19560 19561/* ------------------------------ */ 19562 .balign 64 19563.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */ 19564/* File: armv5te/alt_stub.S */ 19565/* 19566 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19567 * any interesting requests and then jump to the real instruction 19568 * handler. Note that the call to dvmCheckInst is done as a tail call. 19569 */ 19570 adrl lr, dvmAsmInstructionStart + (462 * 64) 19571 mov r0, rPC @ arg0 19572 mov r1, rSELF @ arg1 19573 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19574 19575/* ------------------------------ */ 19576 .balign 64 19577.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */ 19578/* File: armv5te/alt_stub.S */ 19579/* 19580 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19581 * any interesting requests and then jump to the real instruction 19582 * handler. Note that the call to dvmCheckInst is done as a tail call. 19583 */ 19584 adrl lr, dvmAsmInstructionStart + (463 * 64) 19585 mov r0, rPC @ arg0 19586 mov r1, rSELF @ arg1 19587 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19588 19589/* ------------------------------ */ 19590 .balign 64 19591.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */ 19592/* File: armv5te/alt_stub.S */ 19593/* 19594 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19595 * any interesting requests and then jump to the real instruction 19596 * handler. Note that the call to dvmCheckInst is done as a tail call. 19597 */ 19598 adrl lr, dvmAsmInstructionStart + (464 * 64) 19599 mov r0, rPC @ arg0 19600 mov r1, rSELF @ arg1 19601 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19602 19603/* ------------------------------ */ 19604 .balign 64 19605.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */ 19606/* File: armv5te/alt_stub.S */ 19607/* 19608 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19609 * any interesting requests and then jump to the real instruction 19610 * handler. Note that the call to dvmCheckInst is done as a tail call. 19611 */ 19612 adrl lr, dvmAsmInstructionStart + (465 * 64) 19613 mov r0, rPC @ arg0 19614 mov r1, rSELF @ arg1 19615 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19616 19617/* ------------------------------ */ 19618 .balign 64 19619.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */ 19620/* File: armv5te/alt_stub.S */ 19621/* 19622 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19623 * any interesting requests and then jump to the real instruction 19624 * handler. Note that the call to dvmCheckInst is done as a tail call. 19625 */ 19626 adrl lr, dvmAsmInstructionStart + (466 * 64) 19627 mov r0, rPC @ arg0 19628 mov r1, rSELF @ arg1 19629 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19630 19631/* ------------------------------ */ 19632 .balign 64 19633.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */ 19634/* File: armv5te/alt_stub.S */ 19635/* 19636 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19637 * any interesting requests and then jump to the real instruction 19638 * handler. Note that the call to dvmCheckInst is done as a tail call. 19639 */ 19640 adrl lr, dvmAsmInstructionStart + (467 * 64) 19641 mov r0, rPC @ arg0 19642 mov r1, rSELF @ arg1 19643 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19644 19645/* ------------------------------ */ 19646 .balign 64 19647.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */ 19648/* File: armv5te/alt_stub.S */ 19649/* 19650 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19651 * any interesting requests and then jump to the real instruction 19652 * handler. Note that the call to dvmCheckInst is done as a tail call. 19653 */ 19654 adrl lr, dvmAsmInstructionStart + (468 * 64) 19655 mov r0, rPC @ arg0 19656 mov r1, rSELF @ arg1 19657 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19658 19659/* ------------------------------ */ 19660 .balign 64 19661.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */ 19662/* File: armv5te/alt_stub.S */ 19663/* 19664 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19665 * any interesting requests and then jump to the real instruction 19666 * handler. Note that the call to dvmCheckInst is done as a tail call. 19667 */ 19668 adrl lr, dvmAsmInstructionStart + (469 * 64) 19669 mov r0, rPC @ arg0 19670 mov r1, rSELF @ arg1 19671 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19672 19673/* ------------------------------ */ 19674 .balign 64 19675.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */ 19676/* File: armv5te/alt_stub.S */ 19677/* 19678 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19679 * any interesting requests and then jump to the real instruction 19680 * handler. Note that the call to dvmCheckInst is done as a tail call. 19681 */ 19682 adrl lr, dvmAsmInstructionStart + (470 * 64) 19683 mov r0, rPC @ arg0 19684 mov r1, rSELF @ arg1 19685 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19686 19687/* ------------------------------ */ 19688 .balign 64 19689.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */ 19690/* File: armv5te/alt_stub.S */ 19691/* 19692 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19693 * any interesting requests and then jump to the real instruction 19694 * handler. Note that the call to dvmCheckInst is done as a tail call. 19695 */ 19696 adrl lr, dvmAsmInstructionStart + (471 * 64) 19697 mov r0, rPC @ arg0 19698 mov r1, rSELF @ arg1 19699 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19700 19701/* ------------------------------ */ 19702 .balign 64 19703.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */ 19704/* File: armv5te/alt_stub.S */ 19705/* 19706 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19707 * any interesting requests and then jump to the real instruction 19708 * handler. Note that the call to dvmCheckInst is done as a tail call. 19709 */ 19710 adrl lr, dvmAsmInstructionStart + (472 * 64) 19711 mov r0, rPC @ arg0 19712 mov r1, rSELF @ arg1 19713 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19714 19715/* ------------------------------ */ 19716 .balign 64 19717.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */ 19718/* File: armv5te/alt_stub.S */ 19719/* 19720 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19721 * any interesting requests and then jump to the real instruction 19722 * handler. Note that the call to dvmCheckInst is done as a tail call. 19723 */ 19724 adrl lr, dvmAsmInstructionStart + (473 * 64) 19725 mov r0, rPC @ arg0 19726 mov r1, rSELF @ arg1 19727 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19728 19729/* ------------------------------ */ 19730 .balign 64 19731.L_ALT_OP_UNUSED_DAFF: /* 0x1da */ 19732/* File: armv5te/alt_stub.S */ 19733/* 19734 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19735 * any interesting requests and then jump to the real instruction 19736 * handler. Note that the call to dvmCheckInst is done as a tail call. 19737 */ 19738 adrl lr, dvmAsmInstructionStart + (474 * 64) 19739 mov r0, rPC @ arg0 19740 mov r1, rSELF @ arg1 19741 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19742 19743/* ------------------------------ */ 19744 .balign 64 19745.L_ALT_OP_UNUSED_DBFF: /* 0x1db */ 19746/* File: armv5te/alt_stub.S */ 19747/* 19748 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19749 * any interesting requests and then jump to the real instruction 19750 * handler. Note that the call to dvmCheckInst is done as a tail call. 19751 */ 19752 adrl lr, dvmAsmInstructionStart + (475 * 64) 19753 mov r0, rPC @ arg0 19754 mov r1, rSELF @ arg1 19755 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19756 19757/* ------------------------------ */ 19758 .balign 64 19759.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */ 19760/* File: armv5te/alt_stub.S */ 19761/* 19762 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19763 * any interesting requests and then jump to the real instruction 19764 * handler. Note that the call to dvmCheckInst is done as a tail call. 19765 */ 19766 adrl lr, dvmAsmInstructionStart + (476 * 64) 19767 mov r0, rPC @ arg0 19768 mov r1, rSELF @ arg1 19769 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19770 19771/* ------------------------------ */ 19772 .balign 64 19773.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */ 19774/* File: armv5te/alt_stub.S */ 19775/* 19776 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19777 * any interesting requests and then jump to the real instruction 19778 * handler. Note that the call to dvmCheckInst is done as a tail call. 19779 */ 19780 adrl lr, dvmAsmInstructionStart + (477 * 64) 19781 mov r0, rPC @ arg0 19782 mov r1, rSELF @ arg1 19783 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19784 19785/* ------------------------------ */ 19786 .balign 64 19787.L_ALT_OP_UNUSED_DEFF: /* 0x1de */ 19788/* File: armv5te/alt_stub.S */ 19789/* 19790 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19791 * any interesting requests and then jump to the real instruction 19792 * handler. Note that the call to dvmCheckInst is done as a tail call. 19793 */ 19794 adrl lr, dvmAsmInstructionStart + (478 * 64) 19795 mov r0, rPC @ arg0 19796 mov r1, rSELF @ arg1 19797 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19798 19799/* ------------------------------ */ 19800 .balign 64 19801.L_ALT_OP_UNUSED_DFFF: /* 0x1df */ 19802/* File: armv5te/alt_stub.S */ 19803/* 19804 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19805 * any interesting requests and then jump to the real instruction 19806 * handler. Note that the call to dvmCheckInst is done as a tail call. 19807 */ 19808 adrl lr, dvmAsmInstructionStart + (479 * 64) 19809 mov r0, rPC @ arg0 19810 mov r1, rSELF @ arg1 19811 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19812 19813/* ------------------------------ */ 19814 .balign 64 19815.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */ 19816/* File: armv5te/alt_stub.S */ 19817/* 19818 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19819 * any interesting requests and then jump to the real instruction 19820 * handler. Note that the call to dvmCheckInst is done as a tail call. 19821 */ 19822 adrl lr, dvmAsmInstructionStart + (480 * 64) 19823 mov r0, rPC @ arg0 19824 mov r1, rSELF @ arg1 19825 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19826 19827/* ------------------------------ */ 19828 .balign 64 19829.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */ 19830/* File: armv5te/alt_stub.S */ 19831/* 19832 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19833 * any interesting requests and then jump to the real instruction 19834 * handler. Note that the call to dvmCheckInst is done as a tail call. 19835 */ 19836 adrl lr, dvmAsmInstructionStart + (481 * 64) 19837 mov r0, rPC @ arg0 19838 mov r1, rSELF @ arg1 19839 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19840 19841/* ------------------------------ */ 19842 .balign 64 19843.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */ 19844/* File: armv5te/alt_stub.S */ 19845/* 19846 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19847 * any interesting requests and then jump to the real instruction 19848 * handler. Note that the call to dvmCheckInst is done as a tail call. 19849 */ 19850 adrl lr, dvmAsmInstructionStart + (482 * 64) 19851 mov r0, rPC @ arg0 19852 mov r1, rSELF @ arg1 19853 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19854 19855/* ------------------------------ */ 19856 .balign 64 19857.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */ 19858/* File: armv5te/alt_stub.S */ 19859/* 19860 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19861 * any interesting requests and then jump to the real instruction 19862 * handler. Note that the call to dvmCheckInst is done as a tail call. 19863 */ 19864 adrl lr, dvmAsmInstructionStart + (483 * 64) 19865 mov r0, rPC @ arg0 19866 mov r1, rSELF @ arg1 19867 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19868 19869/* ------------------------------ */ 19870 .balign 64 19871.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */ 19872/* File: armv5te/alt_stub.S */ 19873/* 19874 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19875 * any interesting requests and then jump to the real instruction 19876 * handler. Note that the call to dvmCheckInst is done as a tail call. 19877 */ 19878 adrl lr, dvmAsmInstructionStart + (484 * 64) 19879 mov r0, rPC @ arg0 19880 mov r1, rSELF @ arg1 19881 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19882 19883/* ------------------------------ */ 19884 .balign 64 19885.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */ 19886/* File: armv5te/alt_stub.S */ 19887/* 19888 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19889 * any interesting requests and then jump to the real instruction 19890 * handler. Note that the call to dvmCheckInst is done as a tail call. 19891 */ 19892 adrl lr, dvmAsmInstructionStart + (485 * 64) 19893 mov r0, rPC @ arg0 19894 mov r1, rSELF @ arg1 19895 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19896 19897/* ------------------------------ */ 19898 .balign 64 19899.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */ 19900/* File: armv5te/alt_stub.S */ 19901/* 19902 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19903 * any interesting requests and then jump to the real instruction 19904 * handler. Note that the call to dvmCheckInst is done as a tail call. 19905 */ 19906 adrl lr, dvmAsmInstructionStart + (486 * 64) 19907 mov r0, rPC @ arg0 19908 mov r1, rSELF @ arg1 19909 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19910 19911/* ------------------------------ */ 19912 .balign 64 19913.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */ 19914/* File: armv5te/alt_stub.S */ 19915/* 19916 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19917 * any interesting requests and then jump to the real instruction 19918 * handler. Note that the call to dvmCheckInst is done as a tail call. 19919 */ 19920 adrl lr, dvmAsmInstructionStart + (487 * 64) 19921 mov r0, rPC @ arg0 19922 mov r1, rSELF @ arg1 19923 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19924 19925/* ------------------------------ */ 19926 .balign 64 19927.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */ 19928/* File: armv5te/alt_stub.S */ 19929/* 19930 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19931 * any interesting requests and then jump to the real instruction 19932 * handler. Note that the call to dvmCheckInst is done as a tail call. 19933 */ 19934 adrl lr, dvmAsmInstructionStart + (488 * 64) 19935 mov r0, rPC @ arg0 19936 mov r1, rSELF @ arg1 19937 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19938 19939/* ------------------------------ */ 19940 .balign 64 19941.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */ 19942/* File: armv5te/alt_stub.S */ 19943/* 19944 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19945 * any interesting requests and then jump to the real instruction 19946 * handler. Note that the call to dvmCheckInst is done as a tail call. 19947 */ 19948 adrl lr, dvmAsmInstructionStart + (489 * 64) 19949 mov r0, rPC @ arg0 19950 mov r1, rSELF @ arg1 19951 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19952 19953/* ------------------------------ */ 19954 .balign 64 19955.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */ 19956/* File: armv5te/alt_stub.S */ 19957/* 19958 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19959 * any interesting requests and then jump to the real instruction 19960 * handler. Note that the call to dvmCheckInst is done as a tail call. 19961 */ 19962 adrl lr, dvmAsmInstructionStart + (490 * 64) 19963 mov r0, rPC @ arg0 19964 mov r1, rSELF @ arg1 19965 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19966 19967/* ------------------------------ */ 19968 .balign 64 19969.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */ 19970/* File: armv5te/alt_stub.S */ 19971/* 19972 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19973 * any interesting requests and then jump to the real instruction 19974 * handler. Note that the call to dvmCheckInst is done as a tail call. 19975 */ 19976 adrl lr, dvmAsmInstructionStart + (491 * 64) 19977 mov r0, rPC @ arg0 19978 mov r1, rSELF @ arg1 19979 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19980 19981/* ------------------------------ */ 19982 .balign 64 19983.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */ 19984/* File: armv5te/alt_stub.S */ 19985/* 19986 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19987 * any interesting requests and then jump to the real instruction 19988 * handler. Note that the call to dvmCheckInst is done as a tail call. 19989 */ 19990 adrl lr, dvmAsmInstructionStart + (492 * 64) 19991 mov r0, rPC @ arg0 19992 mov r1, rSELF @ arg1 19993 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19994 19995/* ------------------------------ */ 19996 .balign 64 19997.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */ 19998/* File: armv5te/alt_stub.S */ 19999/* 20000 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20001 * any interesting requests and then jump to the real instruction 20002 * handler. Note that the call to dvmCheckInst is done as a tail call. 20003 */ 20004 adrl lr, dvmAsmInstructionStart + (493 * 64) 20005 mov r0, rPC @ arg0 20006 mov r1, rSELF @ arg1 20007 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20008 20009/* ------------------------------ */ 20010 .balign 64 20011.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */ 20012/* File: armv5te/alt_stub.S */ 20013/* 20014 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20015 * any interesting requests and then jump to the real instruction 20016 * handler. Note that the call to dvmCheckInst is done as a tail call. 20017 */ 20018 adrl lr, dvmAsmInstructionStart + (494 * 64) 20019 mov r0, rPC @ arg0 20020 mov r1, rSELF @ arg1 20021 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20022 20023/* ------------------------------ */ 20024 .balign 64 20025.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */ 20026/* File: armv5te/alt_stub.S */ 20027/* 20028 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20029 * any interesting requests and then jump to the real instruction 20030 * handler. Note that the call to dvmCheckInst is done as a tail call. 20031 */ 20032 adrl lr, dvmAsmInstructionStart + (495 * 64) 20033 mov r0, rPC @ arg0 20034 mov r1, rSELF @ arg1 20035 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20036 20037/* ------------------------------ */ 20038 .balign 64 20039.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */ 20040/* File: armv5te/alt_stub.S */ 20041/* 20042 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20043 * any interesting requests and then jump to the real instruction 20044 * handler. Note that the call to dvmCheckInst is done as a tail call. 20045 */ 20046 adrl lr, dvmAsmInstructionStart + (496 * 64) 20047 mov r0, rPC @ arg0 20048 mov r1, rSELF @ arg1 20049 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20050 20051/* ------------------------------ */ 20052 .balign 64 20053.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */ 20054/* File: armv5te/alt_stub.S */ 20055/* 20056 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20057 * any interesting requests and then jump to the real instruction 20058 * handler. Note that the call to dvmCheckInst is done as a tail call. 20059 */ 20060 adrl lr, dvmAsmInstructionStart + (497 * 64) 20061 mov r0, rPC @ arg0 20062 mov r1, rSELF @ arg1 20063 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20064 20065/* ------------------------------ */ 20066 .balign 64 20067.L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */ 20068/* File: armv5te/alt_stub.S */ 20069/* 20070 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20071 * any interesting requests and then jump to the real instruction 20072 * handler. Note that the call to dvmCheckInst is done as a tail call. 20073 */ 20074 adrl lr, dvmAsmInstructionStart + (498 * 64) 20075 mov r0, rPC @ arg0 20076 mov r1, rSELF @ arg1 20077 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20078 20079/* ------------------------------ */ 20080 .balign 64 20081.L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */ 20082/* File: armv5te/alt_stub.S */ 20083/* 20084 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20085 * any interesting requests and then jump to the real instruction 20086 * handler. Note that the call to dvmCheckInst is done as a tail call. 20087 */ 20088 adrl lr, dvmAsmInstructionStart + (499 * 64) 20089 mov r0, rPC @ arg0 20090 mov r1, rSELF @ arg1 20091 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20092 20093/* ------------------------------ */ 20094 .balign 64 20095.L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */ 20096/* File: armv5te/alt_stub.S */ 20097/* 20098 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20099 * any interesting requests and then jump to the real instruction 20100 * handler. Note that the call to dvmCheckInst is done as a tail call. 20101 */ 20102 adrl lr, dvmAsmInstructionStart + (500 * 64) 20103 mov r0, rPC @ arg0 20104 mov r1, rSELF @ arg1 20105 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20106 20107/* ------------------------------ */ 20108 .balign 64 20109.L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */ 20110/* File: armv5te/alt_stub.S */ 20111/* 20112 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20113 * any interesting requests and then jump to the real instruction 20114 * handler. Note that the call to dvmCheckInst is done as a tail call. 20115 */ 20116 adrl lr, dvmAsmInstructionStart + (501 * 64) 20117 mov r0, rPC @ arg0 20118 mov r1, rSELF @ arg1 20119 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20120 20121/* ------------------------------ */ 20122 .balign 64 20123.L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */ 20124/* File: armv5te/alt_stub.S */ 20125/* 20126 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20127 * any interesting requests and then jump to the real instruction 20128 * handler. Note that the call to dvmCheckInst is done as a tail call. 20129 */ 20130 adrl lr, dvmAsmInstructionStart + (502 * 64) 20131 mov r0, rPC @ arg0 20132 mov r1, rSELF @ arg1 20133 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20134 20135/* ------------------------------ */ 20136 .balign 64 20137.L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */ 20138/* File: armv5te/alt_stub.S */ 20139/* 20140 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20141 * any interesting requests and then jump to the real instruction 20142 * handler. Note that the call to dvmCheckInst is done as a tail call. 20143 */ 20144 adrl lr, dvmAsmInstructionStart + (503 * 64) 20145 mov r0, rPC @ arg0 20146 mov r1, rSELF @ arg1 20147 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20148 20149/* ------------------------------ */ 20150 .balign 64 20151.L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */ 20152/* File: armv5te/alt_stub.S */ 20153/* 20154 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20155 * any interesting requests and then jump to the real instruction 20156 * handler. Note that the call to dvmCheckInst is done as a tail call. 20157 */ 20158 adrl lr, dvmAsmInstructionStart + (504 * 64) 20159 mov r0, rPC @ arg0 20160 mov r1, rSELF @ arg1 20161 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20162 20163/* ------------------------------ */ 20164 .balign 64 20165.L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */ 20166/* File: armv5te/alt_stub.S */ 20167/* 20168 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20169 * any interesting requests and then jump to the real instruction 20170 * handler. Note that the call to dvmCheckInst is done as a tail call. 20171 */ 20172 adrl lr, dvmAsmInstructionStart + (505 * 64) 20173 mov r0, rPC @ arg0 20174 mov r1, rSELF @ arg1 20175 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20176 20177/* ------------------------------ */ 20178 .balign 64 20179.L_ALT_OP_UNUSED_FAFF: /* 0x1fa */ 20180/* File: armv5te/alt_stub.S */ 20181/* 20182 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20183 * any interesting requests and then jump to the real instruction 20184 * handler. Note that the call to dvmCheckInst is done as a tail call. 20185 */ 20186 adrl lr, dvmAsmInstructionStart + (506 * 64) 20187 mov r0, rPC @ arg0 20188 mov r1, rSELF @ arg1 20189 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20190 20191/* ------------------------------ */ 20192 .balign 64 20193.L_ALT_OP_UNUSED_FBFF: /* 0x1fb */ 20194/* File: armv5te/alt_stub.S */ 20195/* 20196 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20197 * any interesting requests and then jump to the real instruction 20198 * handler. Note that the call to dvmCheckInst is done as a tail call. 20199 */ 20200 adrl lr, dvmAsmInstructionStart + (507 * 64) 20201 mov r0, rPC @ arg0 20202 mov r1, rSELF @ arg1 20203 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20204 20205/* ------------------------------ */ 20206 .balign 64 20207.L_ALT_OP_UNUSED_FCFF: /* 0x1fc */ 20208/* File: armv5te/alt_stub.S */ 20209/* 20210 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20211 * any interesting requests and then jump to the real instruction 20212 * handler. Note that the call to dvmCheckInst is done as a tail call. 20213 */ 20214 adrl lr, dvmAsmInstructionStart + (508 * 64) 20215 mov r0, rPC @ arg0 20216 mov r1, rSELF @ arg1 20217 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20218 20219/* ------------------------------ */ 20220 .balign 64 20221.L_ALT_OP_UNUSED_FDFF: /* 0x1fd */ 20222/* File: armv5te/alt_stub.S */ 20223/* 20224 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20225 * any interesting requests and then jump to the real instruction 20226 * handler. Note that the call to dvmCheckInst is done as a tail call. 20227 */ 20228 adrl lr, dvmAsmInstructionStart + (509 * 64) 20229 mov r0, rPC @ arg0 20230 mov r1, rSELF @ arg1 20231 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20232 20233/* ------------------------------ */ 20234 .balign 64 20235.L_ALT_OP_UNUSED_FEFF: /* 0x1fe */ 20236/* File: armv5te/alt_stub.S */ 20237/* 20238 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20239 * any interesting requests and then jump to the real instruction 20240 * handler. Note that the call to dvmCheckInst is done as a tail call. 20241 */ 20242 adrl lr, dvmAsmInstructionStart + (510 * 64) 20243 mov r0, rPC @ arg0 20244 mov r1, rSELF @ arg1 20245 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20246 20247/* ------------------------------ */ 20248 .balign 64 20249.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 20250/* File: armv5te/alt_stub.S */ 20251/* 20252 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20253 * any interesting requests and then jump to the real instruction 20254 * handler. Note that the call to dvmCheckInst is done as a tail call. 20255 */ 20256 adrl lr, dvmAsmInstructionStart + (511 * 64) 20257 mov r0, rPC @ arg0 20258 mov r1, rSELF @ arg1 20259 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20260 20261 .balign 64 20262 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart 20263 .global dvmAsmAltInstructionEnd 20264dvmAsmAltInstructionEnd: 20265/* File: armv5te/footer.S */ 20266 20267/* 20268 * =========================================================================== 20269 * Common subroutines and data 20270 * =========================================================================== 20271 */ 20272 20273 20274 20275 .text 20276 .align 2 20277 20278#if defined(WITH_JIT) 20279#if defined(WITH_SELF_VERIFICATION) 20280 .global dvmJitToInterpPunt 20281dvmJitToInterpPunt: 20282 mov r2,#kSVSPunt @ r2<- interpreter entry point 20283 mov r3, #0 20284 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20285 b jitSVShadowRunEnd @ doesn't return 20286 20287 .global dvmJitToInterpSingleStep 20288dvmJitToInterpSingleStep: 20289 str lr,[rSELF,#offThread_jitResumeNPC] 20290 str r1,[rSELF,#offThread_jitResumeDPC] 20291 mov r2,#kSVSSingleStep @ r2<- interpreter entry point 20292 b jitSVShadowRunEnd @ doesn't return 20293 20294 .global dvmJitToInterpNoChainNoProfile 20295dvmJitToInterpNoChainNoProfile: 20296 mov r0,rPC @ pass our target PC 20297 mov r2,#kSVSNoProfile @ r2<- interpreter entry point 20298 mov r3, #0 @ 0 means !inJitCodeCache 20299 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 20300 b jitSVShadowRunEnd @ doesn't return 20301 20302 .global dvmJitToInterpTraceSelectNoChain 20303dvmJitToInterpTraceSelectNoChain: 20304 mov r0,rPC @ pass our target PC 20305 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20306 mov r3, #0 @ 0 means !inJitCodeCache 20307 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20308 b jitSVShadowRunEnd @ doesn't return 20309 20310 .global dvmJitToInterpTraceSelect 20311dvmJitToInterpTraceSelect: 20312 ldr r0,[lr, #-1] @ pass our target PC 20313 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20314 mov r3, #0 @ 0 means !inJitCodeCache 20315 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20316 b jitSVShadowRunEnd @ doesn't return 20317 20318 .global dvmJitToInterpBackwardBranch 20319dvmJitToInterpBackwardBranch: 20320 ldr r0,[lr, #-1] @ pass our target PC 20321 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 20322 mov r3, #0 @ 0 means !inJitCodeCache 20323 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20324 b jitSVShadowRunEnd @ doesn't return 20325 20326 .global dvmJitToInterpNormal 20327dvmJitToInterpNormal: 20328 ldr r0,[lr, #-1] @ pass our target PC 20329 mov r2,#kSVSNormal @ r2<- interpreter entry point 20330 mov r3, #0 @ 0 means !inJitCodeCache 20331 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20332 b jitSVShadowRunEnd @ doesn't return 20333 20334 .global dvmJitToInterpNoChain 20335dvmJitToInterpNoChain: 20336 mov r0,rPC @ pass our target PC 20337 mov r2,#kSVSNoChain @ r2<- interpreter entry point 20338 mov r3, #0 @ 0 means !inJitCodeCache 20339 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20340 b jitSVShadowRunEnd @ doesn't return 20341#else 20342/* 20343 * Return from the translation cache to the interpreter when the compiler is 20344 * having issues translating/executing a Dalvik instruction. We have to skip 20345 * the code cache lookup otherwise it is possible to indefinitely bouce 20346 * between the interpreter and the code cache if the instruction that fails 20347 * to be compiled happens to be at a trace start. 20348 */ 20349 .global dvmJitToInterpPunt 20350dvmJitToInterpPunt: 20351 mov rPC, r0 20352#if defined(WITH_JIT_TUNING) 20353 mov r0,lr 20354 bl dvmBumpPunt; 20355#endif 20356 EXPORT_PC() 20357 mov r0, #0 20358 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20359 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20360 FETCH_INST() 20361 GET_INST_OPCODE(ip) 20362 GOTO_OPCODE(ip) 20363 20364/* 20365 * Return to the interpreter to handle a single instruction. 20366 * On entry: 20367 * r0 <= PC 20368 * r1 <= PC of resume instruction 20369 * lr <= resume point in translation 20370 */ 20371 .global dvmJitToInterpSingleStep 20372dvmJitToInterpSingleStep: 20373 str lr,[rSELF,#offThread_jitResumeNPC] 20374 str r1,[rSELF,#offThread_jitResumeDPC] 20375 mov r1,#kInterpEntryInstr 20376 @ enum is 4 byte in aapcs-EABI 20377 str r1, [rSELF, #offThread_entryPoint] 20378 mov rPC,r0 20379 EXPORT_PC() 20380 20381 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20382 mov r2,#kJitSingleStep @ Ask for single step and then revert 20383 str r2,[rSELF,#offThread_jitState] 20384 mov r1,#1 @ set changeInterp to bail to debug interp 20385 b common_gotoBail 20386 20387/* 20388 * Return from the translation cache and immediately request 20389 * a translation for the exit target. Commonly used for callees. 20390 */ 20391 .global dvmJitToInterpTraceSelectNoChain 20392dvmJitToInterpTraceSelectNoChain: 20393#if defined(WITH_JIT_TUNING) 20394 bl dvmBumpNoChain 20395#endif 20396 mov r0,rPC 20397 bl dvmJitGetTraceAddr @ Is there a translation? 20398 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20399 mov r1, rPC @ arg1 of translation may need this 20400 mov lr, #0 @ in case target is HANDLER_INTERPRET 20401 cmp r0,#0 @ !0 means translation exists 20402 bxne r0 @ continue native execution if so 20403 b 2f @ branch over to use the interpreter 20404 20405/* 20406 * Return from the translation cache and immediately request 20407 * a translation for the exit target. Commonly used following 20408 * invokes. 20409 */ 20410 .global dvmJitToInterpTraceSelect 20411dvmJitToInterpTraceSelect: 20412 ldr rPC,[lr, #-1] @ get our target PC 20413 add rINST,lr,#-5 @ save start of chain branch 20414 add rINST, #-4 @ .. which is 9 bytes back 20415 mov r0,rPC 20416 bl dvmJitGetTraceAddr @ Is there a translation? 20417 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20418 cmp r0,#0 20419 beq 2f 20420 mov r1,rINST 20421 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 20422 mov r1, rPC @ arg1 of translation may need this 20423 mov lr, #0 @ in case target is HANDLER_INTERPRET 20424 cmp r0,#0 @ successful chain? 20425 bxne r0 @ continue native execution 20426 b toInterpreter @ didn't chain - resume with interpreter 20427 20428/* No translation, so request one if profiling isn't disabled*/ 204292: 20430 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20431 GET_JIT_PROF_TABLE(r0) 20432 FETCH_INST() 20433 cmp r0, #0 20434 movne r2,#kJitTSelectRequestHot @ ask for trace selection 20435 bne common_selectTrace 20436 GET_INST_OPCODE(ip) 20437 GOTO_OPCODE(ip) 20438 20439/* 20440 * Return from the translation cache to the interpreter. 20441 * The return was done with a BLX from thumb mode, and 20442 * the following 32-bit word contains the target rPC value. 20443 * Note that lr (r14) will have its low-order bit set to denote 20444 * its thumb-mode origin. 20445 * 20446 * We'll need to stash our lr origin away, recover the new 20447 * target and then check to see if there is a translation available 20448 * for our new target. If so, we do a translation chain and 20449 * go back to native execution. Otherwise, it's back to the 20450 * interpreter (after treating this entry as a potential 20451 * trace start). 20452 */ 20453 .global dvmJitToInterpNormal 20454dvmJitToInterpNormal: 20455 ldr rPC,[lr, #-1] @ get our target PC 20456 add rINST,lr,#-5 @ save start of chain branch 20457 add rINST,#-4 @ .. which is 9 bytes back 20458#if defined(WITH_JIT_TUNING) 20459 bl dvmBumpNormal 20460#endif 20461 mov r0,rPC 20462 bl dvmJitGetTraceAddr @ Is there a translation? 20463 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20464 cmp r0,#0 20465 beq toInterpreter @ go if not, otherwise do chain 20466 mov r1,rINST 20467 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 20468 mov r1, rPC @ arg1 of translation may need this 20469 mov lr, #0 @ in case target is HANDLER_INTERPRET 20470 cmp r0,#0 @ successful chain? 20471 bxne r0 @ continue native execution 20472 b toInterpreter @ didn't chain - resume with interpreter 20473 20474/* 20475 * Return from the translation cache to the interpreter to do method invocation. 20476 * Check if translation exists for the callee, but don't chain to it. 20477 */ 20478 .global dvmJitToInterpNoChainNoProfile 20479dvmJitToInterpNoChainNoProfile: 20480#if defined(WITH_JIT_TUNING) 20481 bl dvmBumpNoChain 20482#endif 20483 mov r0,rPC 20484 bl dvmJitGetTraceAddr @ Is there a translation? 20485 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20486 mov r1, rPC @ arg1 of translation may need this 20487 mov lr, #0 @ in case target is HANDLER_INTERPRET 20488 cmp r0,#0 20489 bxne r0 @ continue native execution if so 20490 EXPORT_PC() 20491 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20492 FETCH_INST() 20493 GET_INST_OPCODE(ip) @ extract opcode from rINST 20494 GOTO_OPCODE(ip) @ jump to next instruction 20495 20496/* 20497 * Return from the translation cache to the interpreter to do method invocation. 20498 * Check if translation exists for the callee, but don't chain to it. 20499 */ 20500 .global dvmJitToInterpNoChain 20501dvmJitToInterpNoChain: 20502#if defined(WITH_JIT_TUNING) 20503 bl dvmBumpNoChain 20504#endif 20505 mov r0,rPC 20506 bl dvmJitGetTraceAddr @ Is there a translation? 20507 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20508 mov r1, rPC @ arg1 of translation may need this 20509 mov lr, #0 @ in case target is HANDLER_INTERPRET 20510 cmp r0,#0 20511 bxne r0 @ continue native execution if so 20512#endif 20513 20514/* 20515 * No translation, restore interpreter regs and start interpreting. 20516 * rSELF & rFP were preserved in the translated code, and rPC has 20517 * already been restored by the time we get here. We'll need to set 20518 * up rIBASE & rINST, and load the address of the JitTable into r0. 20519 */ 20520toInterpreter: 20521 EXPORT_PC() 20522 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20523 FETCH_INST() 20524 GET_JIT_PROF_TABLE(r0) 20525 @ NOTE: intended fallthrough 20526 20527/* 20528 * Common code to update potential trace start counter, and initiate 20529 * a trace-build if appropriate. On entry, rPC should point to the 20530 * next instruction to execute, and rINST should be already loaded with 20531 * the next opcode word, and r0 holds a pointer to the jit profile 20532 * table (pJitProfTable). 20533 */ 20534common_testUpdateProfile: 20535 cmp r0,#0 20536 GET_INST_OPCODE(ip) 20537 GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 20538 20539common_updateProfile: 20540 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 20541 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 20542 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 20543 GET_INST_OPCODE(ip) 20544 subs r1,r1,#1 @ decrement counter 20545 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 20546 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 20547 20548/* 20549 * Here, we switch to the debug interpreter to request 20550 * trace selection. First, though, check to see if there 20551 * is already a native translation in place (and, if so, 20552 * jump to it now). 20553 */ 20554 20555 GET_JIT_THRESHOLD(r1) 20556 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 20557 EXPORT_PC() 20558 mov r0,rPC 20559 bl dvmJitGetTraceAddr @ r0<- dvmJitGetTraceAddr(rPC) 20560 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20561 mov r1, rPC @ arg1 of translation may need this 20562 mov lr, #0 @ in case target is HANDLER_INTERPRET 20563 cmp r0,#0 20564#if !defined(WITH_SELF_VERIFICATION) 20565 bxne r0 @ jump to the translation 20566 mov r2,#kJitTSelectRequest @ ask for trace selection 20567 @ fall-through to common_selectTrace 20568#else 20569 moveq r2,#kJitTSelectRequest @ ask for trace selection 20570 beq common_selectTrace 20571 /* 20572 * At this point, we have a target translation. However, if 20573 * that translation is actually the interpret-only pseudo-translation 20574 * we want to treat it the same as no translation. 20575 */ 20576 mov r10, r0 @ save target 20577 bl dvmCompilerGetInterpretTemplate 20578 cmp r0, r10 @ special case? 20579 bne jitSVShadowRunStart @ set up self verification shadow space 20580 @ Need to clear the inJitCodeCache flag 20581 mov r3, #0 @ 0 means not in the JIT code cache 20582 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 20583 GET_INST_OPCODE(ip) 20584 GOTO_OPCODE(ip) 20585 /* no return */ 20586#endif 20587 20588/* 20589 * On entry: 20590 * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 20591 */ 20592common_selectTrace: 20593 20594 str r2,[rSELF,#offThread_jitState] 20595 mov r2,#kInterpEntryInstr @ normal entry reason 20596 str r2,[rSELF,#offThread_entryPoint] 20597 mov r1,#1 @ set changeInterp 20598 b common_gotoBail 20599 20600#if defined(WITH_SELF_VERIFICATION) 20601/* 20602 * Save PC and registers to shadow memory for self verification mode 20603 * before jumping to native translation. 20604 * On entry: 20605 * rPC, rFP, rSELF: the values that they should contain 20606 * r10: the address of the target translation. 20607 */ 20608jitSVShadowRunStart: 20609 mov r0,rPC @ r0<- program counter 20610 mov r1,rFP @ r1<- frame pointer 20611 mov r2,rSELF @ r2<- self (Thread) pointer 20612 mov r3,r10 @ r3<- target translation 20613 bl dvmSelfVerificationSaveState @ save registers to shadow space 20614 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 20615 bx r10 @ jump to the translation 20616 20617/* 20618 * Restore PC, registers, and interpreter state to original values 20619 * before jumping back to the interpreter. 20620 */ 20621jitSVShadowRunEnd: 20622 mov r1,rFP @ pass ending fp 20623 mov r3,rSELF @ pass self ptr for convenience 20624 bl dvmSelfVerificationRestoreState @ restore pc and fp values 20625 ldr rPC,[rSELF,#offThread_pc] @ restore PC 20626 ldr rFP,[rSELF,#offThread_fp] @ restore FP 20627 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 20628 cmp r1,#0 @ check for punt condition 20629 beq 1f 20630 mov r2,#kJitSelfVerification @ ask for self verification 20631 str r2,[rSELF,#offThread_jitState] 20632 mov r2,#kInterpEntryInstr @ normal entry reason 20633 str r2,[rSELF,#offThread_entryPoint] 20634 mov r1,#1 @ set changeInterp 20635 b common_gotoBail 20636 206371: @ exit to interpreter without check 20638 EXPORT_PC() 20639 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20640 FETCH_INST() 20641 GET_INST_OPCODE(ip) 20642 GOTO_OPCODE(ip) 20643#endif 20644 20645#endif 20646 20647/* 20648 * Common code when a backward branch is taken. 20649 * 20650 * TODO: we could avoid a branch by just setting r0 and falling through 20651 * into the common_periodicChecks code, and having a test on r0 at the 20652 * end determine if we should return to the caller or update & branch to 20653 * the next instr. 20654 * 20655 * On entry: 20656 * r9 is PC adjustment *in bytes* 20657 */ 20658common_backwardBranch: 20659 mov r0, #kInterpEntryInstr 20660 bl common_periodicChecks 20661#if defined(WITH_JIT) 20662 GET_JIT_PROF_TABLE(r0) 20663 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 20664 cmp r0,#0 20665 bne common_updateProfile 20666 GET_INST_OPCODE(ip) 20667 GOTO_OPCODE(ip) 20668#else 20669 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 20670 GET_INST_OPCODE(ip) @ extract opcode from rINST 20671 GOTO_OPCODE(ip) @ jump to next instruction 20672#endif 20673 20674 20675/* 20676 * Need to see if the thread needs to be suspended or debugger/profiler 20677 * activity has begun. If so, we suspend the thread or side-exit to 20678 * the debug interpreter as appropriate. 20679 * 20680 * The common case is no activity on any of these, so we want to figure 20681 * that out quickly. If something is up, we can then sort out what. 20682 * 20683 * We want to be fast if the VM was built without debugger or profiler 20684 * support, but we also need to recognize that the system is usually 20685 * shipped with both of these enabled. 20686 * 20687 * TODO: reduce this so we're just checking a single location. 20688 * 20689 * On entry: 20690 * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling) 20691 * r9 is trampoline PC adjustment *in bytes* 20692 */ 20693common_periodicChecks: 20694/* TUNING - make this a direct load when interpBreak moved to Thread */ 20695 ldr r1, [rSELF, #offThread_pInterpBreak] @ r3<- &interpBreak 20696 /* speculatively thread-specific suspend count */ 20697 ldr ip, [rSELF, #offThread_suspendCount] 20698 ldr r1, [r1] @ r1<- interpBreak 20699 cmp r1, #0 @ anything unusual? 20700 bxeq lr @ return if not 20701 /* 20702 * One or more interesting events have happened. Figure out what. 20703 * 20704 * r0 still holds the reentry type. 20705 */ 20706 cmp ip, #0 @ want suspend? 20707 beq 3f @ no, must be something else 20708 20709 stmfd sp!, {r0, lr} @ preserve r0 and lr 20710#if defined(WITH_JIT) 20711 /* 20712 * Refresh the Jit's cached copy of profile table pointer. This pointer 20713 * doubles as the Jit's on/off switch. 20714 */ 20715 ldr r3, [rSELF, #offThread_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 20716 mov r0, rSELF @ r0<- self 20717 ldr r3, [r3] @ r3 <- pJitProfTable 20718 EXPORT_PC() @ need for precise GC 20719 str r3, [rSELF, #offThread_pJitProfTable] @ refresh Jit's on/off switch 20720#else 20721 mov r0, rSELF @ r0<- self 20722 EXPORT_PC() @ need for precise GC 20723#endif 20724 bl dvmCheckSuspendPending @ do full check, suspend if necessary 20725 ldmfd sp!, {r0, lr} @ restore r0 and lr 20726 20727 /* 20728 * Reload the interpBreak flags - they may have changed while we 20729 * were suspended. 20730 */ 20731/* TUNING - direct load when InterpBreak moved to Thread */ 20732 ldr r1, [rSELF, #offThread_pInterpBreak] @ r1<- &interpBreak 20733 ldr r1, [r1] @ r1<- interpBreak 207343: 20735 /* 20736 * TODO: this code is too fragile. Need a general mechanism 20737 * to identify what actions to take by submode. Some profiling modes 20738 * (instruction count) need to single-step, while method tracing 20739 * may not. Debugging with breakpoints can run unfettered, but 20740 * source-level single-stepping requires Dalvik singlestepping. 20741 * GC may require a one-shot action and then full-speed resumption. 20742 */ 20743 ands r1, #(kSubModeDebuggerActive | kSubModeEmulatorTrace | kSubModeInstCounting) 20744 bxeq lr @ nothing to do, return 20745 20746 @ debugger/profiler enabled, bail out; self->entryPoint was set above 20747 str r0, [rSELF, #offThread_entryPoint] @ store r0, need for debug/prof 20748 add rPC, rPC, r9 @ update rPC 20749 mov r1, #1 @ "want switch" = true 20750 b common_gotoBail @ side exit 20751 20752 20753/* 20754 * The equivalent of "goto bail", this calls through the "bail handler". 20755 * 20756 * State registers will be saved to the "thread" area before bailing. 20757 * 20758 * On entry: 20759 * r1 is "bool changeInterp", indicating if we want to switch to the 20760 * other interpreter or just bail all the way out 20761 */ 20762common_gotoBail: 20763 SAVE_PC_FP_TO_SELF() @ export state to "thread" 20764 mov r0, rSELF @ r0<- self ptr 20765 b dvmMterpStdBail @ call(self, changeInterp) 20766 20767 @add r1, r1, #1 @ using (boolean+1) 20768 @add r0, rSELF, #offThread_jmpBuf @ r0<- &self->jmpBuf 20769 @bl _longjmp @ does not return 20770 @bl common_abort 20771 20772 20773/* 20774 * Common code for jumbo method invocation. 20775 * NOTE: this adjusts rPC to account for the difference in instruction width. 20776 * As a result, the savedPc in the stack frame will not be wholly accurate. So 20777 * long as that is only used for source file line number calculations, we're 20778 * okay. 20779 * 20780 * On entry: 20781 * r0 is "Method* methodToCall", the method we're trying to call 20782 */ 20783common_invokeMethodJumbo: 20784.LinvokeNewJumbo: 20785 @ prepare to copy args to "outs" area of current frame 20786 add rPC, rPC, #4 @ adjust pc to make return consistent 20787 FETCH(r2, 1) @ r2<- BBBB (arg count) 20788 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 20789 cmp r2, #0 @ no args? 20790 beq .LinvokeArgsDone @ if no args, skip the rest 20791 FETCH(r1, 2) @ r1<- CCCC 20792 b .LinvokeRangeArgs @ handle args like invoke range 20793 20794/* 20795 * Common code for method invocation with range. 20796 * 20797 * On entry: 20798 * r0 is "Method* methodToCall", the method we're trying to call 20799 */ 20800common_invokeMethodRange: 20801.LinvokeNewRange: 20802 @ prepare to copy args to "outs" area of current frame 20803 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 20804 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 20805 beq .LinvokeArgsDone @ if no args, skip the rest 20806 FETCH(r1, 2) @ r1<- CCCC 20807 20808.LinvokeRangeArgs: 20809 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 20810 @ (very few methods have > 10 args; could unroll for common cases) 20811 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 20812 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 208131: ldr r1, [r3], #4 @ val = *fp++ 20814 subs r2, r2, #1 @ count-- 20815 str r1, [r10], #4 @ *outs++ = val 20816 bne 1b @ ...while count != 0 20817 b .LinvokeArgsDone 20818 20819/* 20820 * Common code for method invocation without range. 20821 * 20822 * On entry: 20823 * r0 is "Method* methodToCall", the method we're trying to call 20824 */ 20825common_invokeMethodNoRange: 20826.LinvokeNewNoRange: 20827 @ prepare to copy args to "outs" area of current frame 20828 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 20829 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 20830 FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 20831 beq .LinvokeArgsDone 20832 20833 @ r0=methodToCall, r1=GFED, r2=count, r10=outs 20834.LinvokeNonRange: 20835 rsb r2, r2, #5 @ r2<- 5-r2 20836 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 20837 bl common_abort @ (skipped due to ARM prefetch) 208385: and ip, rINST, #0x0f00 @ isolate A 20839 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 20840 mov r0, r0 @ nop 20841 str r2, [r10, #-4]! @ *--outs = vA 208424: and ip, r1, #0xf000 @ isolate G 20843 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 20844 mov r0, r0 @ nop 20845 str r2, [r10, #-4]! @ *--outs = vG 208463: and ip, r1, #0x0f00 @ isolate F 20847 ldr r2, [rFP, ip, lsr #6] @ r2<- vF 20848 mov r0, r0 @ nop 20849 str r2, [r10, #-4]! @ *--outs = vF 208502: and ip, r1, #0x00f0 @ isolate E 20851 ldr r2, [rFP, ip, lsr #2] @ r2<- vE 20852 mov r0, r0 @ nop 20853 str r2, [r10, #-4]! @ *--outs = vE 208541: and ip, r1, #0x000f @ isolate D 20855 ldr r2, [rFP, ip, lsl #2] @ r2<- vD 20856 mov r0, r0 @ nop 20857 str r2, [r10, #-4]! @ *--outs = vD 208580: @ fall through to .LinvokeArgsDone 20859 20860.LinvokeArgsDone: @ r0=methodToCall 20861 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 20862 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 20863 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 20864 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 20865 @ find space for the new stack frame, check for overflow 20866 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 20867 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 20868 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 20869@ bl common_dumpRegs 20870 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd 20871 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 20872 cmp r3, r9 @ bottom < interpStackEnd? 20873 ldr lr, [rSELF, #offThread_pInterpBreak] 20874 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 20875 blo .LstackOverflow @ yes, this frame will overflow stack 20876 20877 @ set up newSaveArea 20878 ldr lr, [lr] @ lr<- active submodes 20879#ifdef EASY_GDB 20880 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 20881 str ip, [r10, #offStackSaveArea_prevSave] 20882#endif 20883 str rFP, [r10, #offStackSaveArea_prevFrame] 20884 str rPC, [r10, #offStackSaveArea_savedPc] 20885#if defined(WITH_JIT) 20886 mov r9, #0 20887 str r9, [r10, #offStackSaveArea_returnAddr] 20888#endif 20889 ands lr, #kSubModeMethodTrace @ method tracing? 20890 beq 1f @ skip if not 20891 stmfd sp!, {r0-r3} @ preserve r0-r3 20892 mov r1, r6 20893 @ r0=methodToCall, r1=rSELF 20894 bl dvmFastMethodTraceEnter 20895 ldmfd sp!, {r0-r3} @ restore r0-r3 208961: 20897 str r0, [r10, #offStackSaveArea_method] 20898 tst r3, #ACC_NATIVE 20899 bne .LinvokeNative 20900 20901 /* 20902 stmfd sp!, {r0-r3} 20903 bl common_printNewline 20904 mov r0, rFP 20905 mov r1, #0 20906 bl dvmDumpFp 20907 ldmfd sp!, {r0-r3} 20908 stmfd sp!, {r0-r3} 20909 mov r0, r1 20910 mov r1, r10 20911 bl dvmDumpFp 20912 bl common_printNewline 20913 ldmfd sp!, {r0-r3} 20914 */ 20915 20916 ldrh r9, [r2] @ r9 <- load INST from new PC 20917 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 20918 mov rPC, r2 @ publish new rPC 20919 20920 @ Update state values for the new method 20921 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST 20922 str r0, [rSELF, #offThread_method] @ self->method = methodToCall 20923 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ... 20924#if defined(WITH_JIT) 20925 GET_JIT_PROF_TABLE(r0) 20926 mov rFP, r1 @ fp = newFp 20927 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 20928 mov rINST, r9 @ publish new rINST 20929 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 20930 cmp r0,#0 20931 bne common_updateProfile 20932 GOTO_OPCODE(ip) @ jump to next instruction 20933#else 20934 mov rFP, r1 @ fp = newFp 20935 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 20936 mov rINST, r9 @ publish new rINST 20937 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 20938 GOTO_OPCODE(ip) @ jump to next instruction 20939#endif 20940 20941.LinvokeNative: 20942 @ Prep for the native call 20943 @ r0=methodToCall, r1=newFp, r10=newSaveArea 20944 ldr lr, [rSELF, #offThread_pInterpBreak] 20945 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->... 20946 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 20947 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 20948 ldr lr, [lr] @ lr<- active submodes 20949 20950 mov r2, r0 @ r2<- methodToCall 20951 mov r0, r1 @ r0<- newFp (points to args) 20952 add r1, rSELF, #offThread_retval @ r1<- &retval 20953 mov r3, rSELF @ arg3<- self 20954 20955#ifdef ASSIST_DEBUGGER 20956 /* insert fake function header to help gdb find the stack frame */ 20957 b .Lskip 20958 .type dalvik_mterp, %function 20959dalvik_mterp: 20960 .fnstart 20961 MTERP_ENTRY1 20962 MTERP_ENTRY2 20963.Lskip: 20964#endif 20965 20966 ands lr, #kSubModeMethodTrace @ method tracing? 20967 beq 110f @ hop if not 20968 @ r2=JNIMethod, r6=rSELF 20969 stmfd sp!, {r2,r6} 20970 20971 mov lr, pc @ set return addr 20972 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 20973 20974 @ r0=JNIMethod, r1=rSELF 20975 ldmfd sp!, {r0-r1} 20976 bl dvmFastNativeMethodTraceExit 20977 b 220f 20978110: 20979 mov lr, pc @ set return addr 20980 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 20981220: 20982#if defined(WITH_JIT) 20983 ldr r3, [rSELF, #offThread_ppJitProfTable] @ Refresh Jit's on/off status 20984#endif 20985 20986 @ native return; r10=newSaveArea 20987 @ equivalent to dvmPopJniLocals 20988 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 20989 ldr r1, [rSELF, #offThread_exception] @ check for exception 20990#if defined(WITH_JIT) 20991 ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 20992#endif 20993 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 20994 cmp r1, #0 @ null? 20995 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top 20996#if defined(WITH_JIT) 20997 str r3, [rSELF, #offThread_pJitProfTable] @ refresh cached on/off switch 20998#endif 20999 bne common_exceptionThrown @ no, handle exception 21000 21001 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 21002 GET_INST_OPCODE(ip) @ extract opcode from rINST 21003 GOTO_OPCODE(ip) @ jump to next instruction 21004 21005.LstackOverflow: @ r0=methodToCall 21006 mov r1, r0 @ r1<- methodToCall 21007 mov r0, rSELF @ r0<- self 21008 bl dvmHandleStackOverflow 21009 b common_exceptionThrown 21010#ifdef ASSIST_DEBUGGER 21011 .fnend 21012 .size dalvik_mterp, .-dalvik_mterp 21013#endif 21014 21015 21016 /* 21017 * Common code for method invocation, calling through "glue code". 21018 * 21019 * TODO: now that we have range and non-range invoke handlers, this 21020 * needs to be split into two. Maybe just create entry points 21021 * that set r9 and jump here? 21022 * 21023 * On entry: 21024 * r0 is "Method* methodToCall", the method we're trying to call 21025 * r9 is "bool methodCallRange", indicating if this is a /range variant 21026 */ 21027 .if 0 21028.LinvokeOld: 21029 sub sp, sp, #8 @ space for args + pad 21030 FETCH(ip, 2) @ ip<- FEDC or CCCC 21031 mov r2, r0 @ A2<- methodToCall 21032 mov r0, rSELF @ A0<- self 21033 SAVE_PC_FP_TO_SELF() @ export state to "self" 21034 mov r1, r9 @ A1<- methodCallRange 21035 mov r3, rINST, lsr #8 @ A3<- AA 21036 str ip, [sp, #0] @ A4<- ip 21037 bl dvmMterp_invokeMethod @ call the C invokeMethod 21038 add sp, sp, #8 @ remove arg area 21039 b common_resumeAfterGlueCall @ continue to next instruction 21040 .endif 21041 21042 21043 21044/* 21045 * Common code for handling a return instruction. 21046 * 21047 * This does not return. 21048 */ 21049common_returnFromMethod: 21050.LreturnNew: 21051 mov r0, #kInterpEntryReturn 21052 mov r9, #0 21053 bl common_periodicChecks 21054 21055 ldr lr, [rSELF, #offThread_pInterpBreak] 21056 SAVEAREA_FROM_FP(r0, rFP) 21057 ldr lr, [lr] @ lr<- active submodes 21058 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 21059 ands lr, #kSubModeMethodTrace @ method tracing? 21060 beq 333f 21061 stmfd sp!, {r0-r3} @ preserve r0-r3 21062 mov r0, r6 21063 @ r0=rSELF 21064 bl dvmFastJavaMethodTraceExit 21065 ldmfd sp!, {r0-r3} @ restore r0-r3 21066333: 21067 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 21068 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 21069 @ r2<- method we're returning to 21070 cmp r2, #0 @ is this a break frame? 21071#if defined(WORKAROUND_CORTEX_A9_745320) 21072 /* Don't use conditional loads if the HW defect exists */ 21073 beq 101f 21074 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21075101: 21076#else 21077 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21078#endif 21079 mov r1, #0 @ "want switch" = false 21080 beq common_gotoBail @ break frame, bail out completely 21081 21082 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 21083 str r2, [rSELF, #offThread_method]@ self->method = newSave->method 21084 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 21085 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21086#if defined(WITH_JIT) 21087 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 21088 mov rPC, r9 @ publish new rPC 21089 str r1, [rSELF, #offThread_methodClassDex] 21090 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land 21091 cmp r10, #0 @ caller is compiled code 21092 blxne r10 21093 GET_INST_OPCODE(ip) @ extract opcode from rINST 21094 GOTO_OPCODE(ip) @ jump to next instruction 21095#else 21096 GET_INST_OPCODE(ip) @ extract opcode from rINST 21097 mov rPC, r9 @ publish new rPC 21098 str r1, [rSELF, #offThread_methodClassDex] 21099 GOTO_OPCODE(ip) @ jump to next instruction 21100#endif 21101 21102 /* 21103 * Return handling, calls through "glue code". 21104 */ 21105 .if 0 21106.LreturnOld: 21107 SAVE_PC_FP_TO_SELF() @ export state 21108 mov r0, rSELF @ arg to function 21109 bl dvmMterp_returnFromMethod 21110 b common_resumeAfterGlueCall 21111 .endif 21112 21113 21114/* 21115 * Somebody has thrown an exception. Handle it. 21116 * 21117 * If the exception processing code returns to us (instead of falling 21118 * out of the interpreter), continue with whatever the next instruction 21119 * now happens to be. 21120 * 21121 * This does not return. 21122 */ 21123 .global dvmMterpCommonExceptionThrown 21124dvmMterpCommonExceptionThrown: 21125common_exceptionThrown: 21126.LexceptionNew: 21127 mov r0, #kInterpEntryThrow 21128 mov r9, #0 21129 bl common_periodicChecks 21130 21131 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception 21132 mov r1, rSELF @ r1<- self 21133 mov r0, r9 @ r0<- exception 21134 bl dvmAddTrackedAlloc @ don't let the exception be GCed 21135 mov r3, #0 @ r3<- NULL 21136 str r3, [rSELF, #offThread_exception] @ self->exception = NULL 21137 21138 /* set up args and a local for "&fp" */ 21139 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 21140 str rFP, [sp, #-4]! @ *--sp = fp 21141 mov ip, sp @ ip<- &fp 21142 mov r3, #0 @ r3<- false 21143 str ip, [sp, #-4]! @ *--sp = &fp 21144 ldr r1, [rSELF, #offThread_method] @ r1<- self->method 21145 mov r0, rSELF @ r0<- self 21146 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 21147 mov r2, r9 @ r2<- exception 21148 sub r1, rPC, r1 @ r1<- pc - method->insns 21149 mov r1, r1, asr #1 @ r1<- offset in code units 21150 21151 /* call, r0 gets catchRelPc (a code-unit offset) */ 21152 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 21153 21154 /* fix earlier stack overflow if necessary; may trash rFP */ 21155 ldrb r1, [rSELF, #offThread_stackOverflowed] 21156 cmp r1, #0 @ did we overflow earlier? 21157 beq 1f @ no, skip ahead 21158 mov rFP, r0 @ save relPc result in rFP 21159 mov r0, rSELF @ r0<- self 21160 mov r1, r9 @ r1<- exception 21161 bl dvmCleanupStackOverflow @ call(self) 21162 mov r0, rFP @ restore result 211631: 21164 21165 /* update frame pointer and check result from dvmFindCatchBlock */ 21166 ldr rFP, [sp, #4] @ retrieve the updated rFP 21167 cmp r0, #0 @ is catchRelPc < 0? 21168 add sp, sp, #8 @ restore stack 21169 bmi .LnotCaughtLocally 21170 21171 /* adjust locals to match self->curFrame and updated PC */ 21172 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 21173 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 21174 str r1, [rSELF, #offThread_method] @ self->method = new method 21175 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 21176 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 21177 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 21178 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 21179 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth... 21180 21181 /* release the tracked alloc on the exception */ 21182 mov r0, r9 @ r0<- exception 21183 mov r1, rSELF @ r1<- self 21184 bl dvmReleaseTrackedAlloc @ release the exception 21185 21186 /* restore the exception if the handler wants it */ 21187 FETCH_INST() @ load rINST from rPC 21188 GET_INST_OPCODE(ip) @ extract opcode from rINST 21189 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 21190 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception 21191 GOTO_OPCODE(ip) @ jump to next instruction 21192 21193.LnotCaughtLocally: @ r9=exception 21194 /* fix stack overflow if necessary */ 21195 ldrb r1, [rSELF, #offThread_stackOverflowed] 21196 cmp r1, #0 @ did we overflow earlier? 21197 movne r0, rSELF @ if yes: r0<- self 21198 movne r1, r9 @ if yes: r1<- exception 21199 blne dvmCleanupStackOverflow @ if yes: call(self) 21200 21201 @ may want to show "not caught locally" debug messages here 21202#if DVM_SHOW_EXCEPTION >= 2 21203 /* call __android_log_print(prio, tag, format, ...) */ 21204 /* "Exception %s from %s:%d not caught locally" */ 21205 @ dvmLineNumFromPC(method, pc - method->insns) 21206 ldr r0, [rSELF, #offThread_method] 21207 ldr r1, [r0, #offMethod_insns] 21208 sub r1, rPC, r1 21209 asr r1, r1, #1 21210 bl dvmLineNumFromPC 21211 str r0, [sp, #-4]! 21212 @ dvmGetMethodSourceFile(method) 21213 ldr r0, [rSELF, #offThread_method] 21214 bl dvmGetMethodSourceFile 21215 str r0, [sp, #-4]! 21216 @ exception->clazz->descriptor 21217 ldr r3, [r9, #offObject_clazz] 21218 ldr r3, [r3, #offClassObject_descriptor] 21219 @ 21220 ldr r2, strExceptionNotCaughtLocally 21221 ldr r1, strLogTag 21222 mov r0, #3 @ LOG_DEBUG 21223 bl __android_log_print 21224#endif 21225 str r9, [rSELF, #offThread_exception] @ restore exception 21226 mov r0, r9 @ r0<- exception 21227 mov r1, rSELF @ r1<- self 21228 bl dvmReleaseTrackedAlloc @ release the exception 21229 mov r1, #0 @ "want switch" = false 21230 b common_gotoBail @ bail out 21231 21232 21233 /* 21234 * Exception handling, calls through "glue code". 21235 */ 21236 .if 0 21237.LexceptionOld: 21238 SAVE_PC_FP_TO_SELF() @ export state 21239 mov r0, rSELF @ arg to function 21240 bl dvmMterp_exceptionThrown 21241 b common_resumeAfterGlueCall 21242 .endif 21243 21244 21245/* 21246 * After returning from a "glued" function, pull out the updated 21247 * values and start executing at the next instruction. 21248 */ 21249common_resumeAfterGlueCall: 21250 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread 21251 FETCH_INST() @ load rINST from rPC 21252 GET_INST_OPCODE(ip) @ extract opcode from rINST 21253 GOTO_OPCODE(ip) @ jump to next instruction 21254 21255/* 21256 * Invalid array index. Note that our calling convention is strange; we use r1 21257 * and r3 because those just happen to be the registers all our callers are 21258 * using. We shuffle them here before calling the C function. 21259 * r1: index 21260 * r3: size 21261 */ 21262common_errArrayIndex: 21263 EXPORT_PC() 21264 mov r0, r1 21265 mov r1, r3 21266 bl dvmThrowArrayIndexOutOfBoundsException 21267 b common_exceptionThrown 21268 21269/* 21270 * Integer divide or mod by zero. 21271 */ 21272common_errDivideByZero: 21273 EXPORT_PC() 21274 ldr r0, strDivideByZero 21275 bl dvmThrowArithmeticException 21276 b common_exceptionThrown 21277 21278/* 21279 * Attempt to allocate an array with a negative size. 21280 * On entry: length in r1 21281 */ 21282common_errNegativeArraySize: 21283 EXPORT_PC() 21284 mov r0, r1 @ arg0 <- len 21285 bl dvmThrowNegativeArraySizeException @ (len) 21286 b common_exceptionThrown 21287 21288/* 21289 * Invocation of a non-existent method. 21290 * On entry: method name in r1 21291 */ 21292common_errNoSuchMethod: 21293 EXPORT_PC() 21294 mov r0, r1 21295 bl dvmThrowNoSuchMethodError 21296 b common_exceptionThrown 21297 21298/* 21299 * We encountered a null object when we weren't expecting one. We 21300 * export the PC, throw a NullPointerException, and goto the exception 21301 * processing code. 21302 */ 21303common_errNullObject: 21304 EXPORT_PC() 21305 mov r0, #0 21306 bl dvmThrowNullPointerException 21307 b common_exceptionThrown 21308 21309/* 21310 * For debugging, cause an immediate fault. The source address will 21311 * be in lr (use a bl instruction to jump here). 21312 */ 21313common_abort: 21314 ldr pc, .LdeadFood 21315.LdeadFood: 21316 .word 0xdeadf00d 21317 21318/* 21319 * Spit out a "we were here", preserving all registers. (The attempt 21320 * to save ip won't work, but we need to save an even number of 21321 * registers for EABI 64-bit stack alignment.) 21322 */ 21323 .macro SQUEAK num 21324common_squeak\num: 21325 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21326 ldr r0, strSqueak 21327 mov r1, #\num 21328 bl printf 21329 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21330 bx lr 21331 .endm 21332 21333 SQUEAK 0 21334 SQUEAK 1 21335 SQUEAK 2 21336 SQUEAK 3 21337 SQUEAK 4 21338 SQUEAK 5 21339 21340/* 21341 * Spit out the number in r0, preserving registers. 21342 */ 21343common_printNum: 21344 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21345 mov r1, r0 21346 ldr r0, strSqueak 21347 bl printf 21348 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21349 bx lr 21350 21351/* 21352 * Print a newline, preserving registers. 21353 */ 21354common_printNewline: 21355 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21356 ldr r0, strNewline 21357 bl printf 21358 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21359 bx lr 21360 21361 /* 21362 * Print the 32-bit quantity in r0 as a hex value, preserving registers. 21363 */ 21364common_printHex: 21365 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21366 mov r1, r0 21367 ldr r0, strPrintHex 21368 bl printf 21369 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21370 bx lr 21371 21372/* 21373 * Print the 64-bit quantity in r0-r1, preserving registers. 21374 */ 21375common_printLong: 21376 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21377 mov r3, r1 21378 mov r2, r0 21379 ldr r0, strPrintLong 21380 bl printf 21381 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21382 bx lr 21383 21384/* 21385 * Print full method info. Pass the Method* in r0. Preserves regs. 21386 */ 21387common_printMethod: 21388 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21389 bl dvmMterpPrintMethod 21390 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21391 bx lr 21392 21393/* 21394 * Call a C helper function that dumps regs and possibly some 21395 * additional info. Requires the C function to be compiled in. 21396 */ 21397 .if 0 21398common_dumpRegs: 21399 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21400 bl dvmMterpDumpArmRegs 21401 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21402 bx lr 21403 .endif 21404 21405#if 0 21406/* 21407 * Experiment on VFP mode. 21408 * 21409 * uint32_t setFPSCR(uint32_t val, uint32_t mask) 21410 * 21411 * Updates the bits specified by "mask", setting them to the values in "val". 21412 */ 21413setFPSCR: 21414 and r0, r0, r1 @ make sure no stray bits are set 21415 fmrx r2, fpscr @ get VFP reg 21416 mvn r1, r1 @ bit-invert mask 21417 and r2, r2, r1 @ clear masked bits 21418 orr r2, r2, r0 @ set specified bits 21419 fmxr fpscr, r2 @ set VFP reg 21420 mov r0, r2 @ return new value 21421 bx lr 21422 21423 .align 2 21424 .global dvmConfigureFP 21425 .type dvmConfigureFP, %function 21426dvmConfigureFP: 21427 stmfd sp!, {ip, lr} 21428 /* 0x03000000 sets DN/FZ */ 21429 /* 0x00009f00 clears the six exception enable flags */ 21430 bl common_squeak0 21431 mov r0, #0x03000000 @ r0<- 0x03000000 21432 add r1, r0, #0x9f00 @ r1<- 0x03009f00 21433 bl setFPSCR 21434 ldmfd sp!, {ip, pc} 21435#endif 21436 21437 21438/* 21439 * String references, must be close to the code that uses them. 21440 */ 21441 .align 2 21442strDivideByZero: 21443 .word .LstrDivideByZero 21444strLogTag: 21445 .word .LstrLogTag 21446strExceptionNotCaughtLocally: 21447 .word .LstrExceptionNotCaughtLocally 21448 21449strNewline: 21450 .word .LstrNewline 21451strSqueak: 21452 .word .LstrSqueak 21453strPrintHex: 21454 .word .LstrPrintHex 21455strPrintLong: 21456 .word .LstrPrintLong 21457 21458/* 21459 * Zero-terminated ASCII string data. 21460 * 21461 * On ARM we have two choices: do like gcc does, and LDR from a .word 21462 * with the address, or use an ADR pseudo-op to get the address 21463 * directly. ADR saves 4 bytes and an indirection, but it's using a 21464 * PC-relative addressing mode and hence has a limited range, which 21465 * makes it not work well with mergeable string sections. 21466 */ 21467 .section .rodata.str1.4,"aMS",%progbits,1 21468 21469.LstrBadEntryPoint: 21470 .asciz "Bad entry point %d\n" 21471.LstrFilledNewArrayNotImpl: 21472 .asciz "filled-new-array only implemented for objects and 'int'" 21473.LstrDivideByZero: 21474 .asciz "divide by zero" 21475.LstrLogTag: 21476 .asciz "mterp" 21477.LstrExceptionNotCaughtLocally: 21478 .asciz "Exception %s from %s:%d not caught locally\n" 21479 21480.LstrNewline: 21481 .asciz "\n" 21482.LstrSqueak: 21483 .asciz "<%d>" 21484.LstrPrintHex: 21485 .asciz "<0x%x>" 21486.LstrPrintLong: 21487 .asciz "<%lld>" 21488 21489