1633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 2633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Carsten Langgaard, carstenl@mips.com 3633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 4633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 5633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * This program is free software; you can distribute it and/or modify it 6633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * under the terms of the GNU General Public License (Version 2) as 7633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * published by the Free Software Foundation. 8633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 9633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * This program is distributed in the hope it will be useful, but WITHOUT 10633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * for more details. 13633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 14633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * You should have received a copy of the GNU General Public License along 15633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * with this program; if not, write to the Free Software Foundation, Inc., 16633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 18633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Defines of the MIPS boards specific address-MAP, registers, etc. 19633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 20633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef __ASM_MIPS_BOARDS_GENERIC_H 21633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define __ASM_MIPS_BOARDS_GENERIC_H 22633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 23633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <asm/addrspace.h> 24633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <asm/byteorder.h> 25633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <asm/mips-boards/bonito64.h> 26633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 27633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 28633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Display register base. 29633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 30633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ASCII_DISPLAY_WORD_BASE 0x1f000410 31633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ASCII_DISPLAY_POS_BASE 0x1f000418 32633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 33633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 34633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 35633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Yamon Prom print address. 36633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 37633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define YAMON_PROM_PRINT_ADDR 0x1fc00504 38633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 39633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 40633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 41633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Reset register. 42633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 43633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SOFTRES_REG 0x1f000500 44633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GORESET 0x42 45633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 46633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 47633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Revision register. 48633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 49633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_REG 0x1fc00010 50633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_QED_RM5261 0 51633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_LV 1 52633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_BONITO64 2 53633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_20K 3 54633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_FPGA 4 55633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_MSC 5 56633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_EMUL 6 57633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_FPGA2 7 58633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_FPGAR2 8 59633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_FPGA3 9 60633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_24K 10 61633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_FPGA4 11 62633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_FPGA5 12 63633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 64633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/**** Artificial corid defines ****/ 65633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 66633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * CoreEMUL with Bonito System Controller is treated like a Core20K 67633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC 68633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 69633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_EMUL_BON -1 70633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 71633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 72633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) 73633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 74633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern int mips_revision_corid; 75633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 76633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCON_OTHER 0 77633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCON_SOCITSC 1 78633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCON_SOCITSCP 2 79633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 80633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ 81633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCON_UNKNOWN -1 82633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCON_GT64120 -2 83633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCON_BONITO -3 84633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCON_BRTL -4 85633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCON_SOCIT -5 86633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCON_ROCIT -6 87633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 88633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) 89633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 90633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern int mips_revision_sconid; 91633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 92633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void mips_reboot_setup(void); 93633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 94633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_PCI 95633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void mips_pcibios_init(void); 96633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else 97633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define mips_pcibios_init() do { } while (0) 98633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 99633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 100633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_KGDB 101633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void kgdb_config(void); 102633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 103633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 104633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 105