MachineInstr.h revision 5080f4d9919d39b367891dc51e739c571a66036c
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "llvm/CodeGen/MachineOperand.h" 20 21namespace llvm { 22 23class TargetInstrDesc; 24 25template <typename T> struct ilist_traits; 26template <typename T> struct ilist; 27 28//===----------------------------------------------------------------------===// 29/// MachineInstr - Representation of each machine instruction. 30/// 31class MachineInstr { 32 const TargetInstrDesc *TID; // Instruction descriptor. 33 unsigned short NumImplicitOps; // Number of implicit operands (which 34 // are determined at construction time). 35 36 std::vector<MachineOperand> Operands; // the operands 37 MachineInstr *Prev, *Next; // Links for MBB's intrusive list. 38 MachineBasicBlock *Parent; // Pointer to the owning basic block. 39 40 // OperandComplete - Return true if it's illegal to add a new operand 41 bool OperandsComplete() const; 42 43 MachineInstr(const MachineInstr&); 44 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 45 46 // Intrusive list support 47 friend struct ilist_traits<MachineInstr>; 48 friend struct ilist_traits<MachineBasicBlock>; 49 void setParent(MachineBasicBlock *P) { Parent = P; } 50public: 51 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with 52 /// TID NULL and no operands. 53 MachineInstr(); 54 55 /// MachineInstr ctor - This constructor create a MachineInstr and add the 56 /// implicit operands. It reserves space for number of operands specified by 57 /// TargetInstrDesc. 58 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false); 59 60 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 61 /// the MachineInstr is created and added to the end of the specified basic 62 /// block. 63 /// 64 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID); 65 66 ~MachineInstr(); 67 68 const MachineBasicBlock* getParent() const { return Parent; } 69 MachineBasicBlock* getParent() { return Parent; } 70 71 /// getDesc - Returns the target instruction descriptor of this 72 /// MachineInstr. 73 const TargetInstrDesc &getDesc() const { return *TID; } 74 75 /// getOpcode - Returns the opcode of this MachineInstr. 76 /// 77 int getOpcode() const; 78 79 /// Access to explicit operands of the instruction. 80 /// 81 unsigned getNumOperands() const { return Operands.size(); } 82 83 const MachineOperand& getOperand(unsigned i) const { 84 assert(i < getNumOperands() && "getOperand() out of range!"); 85 return Operands[i]; 86 } 87 MachineOperand& getOperand(unsigned i) { 88 assert(i < getNumOperands() && "getOperand() out of range!"); 89 return Operands[i]; 90 } 91 92 /// getNumExplicitOperands - Returns the number of non-implicit operands. 93 /// 94 unsigned getNumExplicitOperands() const; 95 96 /// isIdenticalTo - Return true if this instruction is identical to (same 97 /// opcode and same operands as) the specified instruction. 98 bool isIdenticalTo(const MachineInstr *Other) const { 99 if (Other->getOpcode() != getOpcode() || 100 Other->getNumOperands() != getNumOperands()) 101 return false; 102 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 103 if (!getOperand(i).isIdenticalTo(Other->getOperand(i))) 104 return false; 105 return true; 106 } 107 108 /// clone - Create a copy of 'this' instruction that is identical in 109 /// all ways except the the instruction has no parent, prev, or next. 110 MachineInstr* clone() const { return new MachineInstr(*this); } 111 112 /// removeFromParent - This method unlinks 'this' from the containing basic 113 /// block, and returns it, but does not delete it. 114 MachineInstr *removeFromParent(); 115 116 /// eraseFromParent - This method unlinks 'this' from the containing basic 117 /// block and deletes it. 118 void eraseFromParent() { 119 delete removeFromParent(); 120 } 121 122 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of 123 /// the specific register or -1 if it is not found. It further tightening 124 /// the search criteria to a use that kills the register if isKill is true. 125 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false) const; 126 127 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of 128 /// the specific register or NULL if it is not found. 129 MachineOperand *findRegisterDefOperand(unsigned Reg); 130 131 /// findFirstPredOperandIdx() - Find the index of the first operand in the 132 /// operand list that is used to represent the predicate. It returns -1 if 133 /// none is found. 134 int findFirstPredOperandIdx() const; 135 136 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due 137 /// to two addr elimination. 138 bool isRegReDefinedByTwoAddr(unsigned Reg) const; 139 140 /// copyKillDeadInfo - Copies kill / dead operand properties from MI. 141 /// 142 void copyKillDeadInfo(const MachineInstr *MI); 143 144 /// copyPredicates - Copies predicate operand(s) from MI. 145 void copyPredicates(const MachineInstr *MI); 146 147 // 148 // Debugging support 149 // 150 void print(std::ostream *OS, const TargetMachine *TM) const { 151 if (OS) print(*OS, TM); 152 } 153 void print(std::ostream &OS, const TargetMachine *TM = 0) const; 154 void print(std::ostream *OS) const { if (OS) print(*OS); } 155 void dump() const; 156 157 //===--------------------------------------------------------------------===// 158 // Accessors used to build up machine instructions. 159 160 /// addOperand - Add the specified operand to the instruction. If it is an 161 /// implicit operand, it is added to the end of the operand list. If it is 162 /// an explicit operand it is added at the end of the explicit operand list 163 /// (before the first implicit operand). 164 void addOperand(const MachineOperand &Op); 165 166 /// setDesc - Replace the instruction descriptor (thus opcode) of 167 /// the current instruction with a new one. 168 /// 169 void setDesc(const TargetInstrDesc &tid) { TID = &tid; } 170 171 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 172 /// fewer operand than it started with. 173 /// 174 void RemoveOperand(unsigned i); 175 176private: 177 /// getRegInfo - If this instruction is embedded into a MachineFunction, 178 /// return the MachineRegisterInfo object for the current function, otherwise 179 /// return null. 180 MachineRegisterInfo *getRegInfo(); 181 182 /// addImplicitDefUseOperands - Add all implicit def and use operands to 183 /// this instruction. 184 void addImplicitDefUseOperands(); 185 186 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 187 /// this instruction from their respective use lists. This requires that the 188 /// operands already be on their use lists. 189 void RemoveRegOperandsFromUseLists(); 190 191 /// AddRegOperandsToUseLists - Add all of the register operands in 192 /// this instruction from their respective use lists. This requires that the 193 /// operands not be on their use lists yet. 194 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo); 195}; 196 197//===----------------------------------------------------------------------===// 198// Debugging Support 199 200inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) { 201 MI.print(OS); 202 return OS; 203} 204 205} // End llvm namespace 206 207#endif 208