1//===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines interfaces to access the target independent code generation 11// passes provided by the LLVM backend. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_PASSES_H 16#define LLVM_CODEGEN_PASSES_H 17 18#include "llvm/Pass.h" 19#include "llvm/Target/TargetMachine.h" 20#include <string> 21 22namespace llvm { 23 24 class FunctionPass; 25 class MachineFunctionPass; 26 class PassInfo; 27 class PassManagerBase; 28 class TargetLoweringBase; 29 class TargetLowering; 30 class TargetRegisterClass; 31 class raw_ostream; 32} 33 34namespace llvm { 35 36class PassConfigImpl; 37 38/// Target-Independent Code Generator Pass Configuration Options. 39/// 40/// This is an ImmutablePass solely for the purpose of exposing CodeGen options 41/// to the internals of other CodeGen passes. 42class TargetPassConfig : public ImmutablePass { 43public: 44 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they 45 /// are unregistered pass IDs. They are only useful for use with 46 /// TargetPassConfig APIs to identify multiple occurrences of the same pass. 47 /// 48 49 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early 50 /// during codegen, on SSA form. 51 static char EarlyTailDuplicateID; 52 53 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine 54 /// optimization after regalloc. 55 static char PostRAMachineLICMID; 56 57private: 58 PassManagerBase *PM; 59 AnalysisID StartAfter; 60 AnalysisID StopAfter; 61 bool Started; 62 bool Stopped; 63 64protected: 65 TargetMachine *TM; 66 PassConfigImpl *Impl; // Internal data structures 67 bool Initialized; // Flagged after all passes are configured. 68 69 // Target Pass Options 70 // Targets provide a default setting, user flags override. 71 // 72 bool DisableVerify; 73 74 /// Default setting for -enable-tail-merge on this target. 75 bool EnableTailMerge; 76 77public: 78 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm); 79 // Dummy constructor. 80 TargetPassConfig(); 81 82 virtual ~TargetPassConfig(); 83 84 static char ID; 85 86 /// Get the right type of TargetMachine for this target. 87 template<typename TMC> TMC &getTM() const { 88 return *static_cast<TMC*>(TM); 89 } 90 91 const TargetLowering *getTargetLowering() const { 92 return TM->getTargetLowering(); 93 } 94 95 // 96 void setInitialized() { Initialized = true; } 97 98 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } 99 100 /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow 101 /// running only a portion of the normal code-gen pass sequence. If the 102 /// Start pass ID is zero, then compilation will begin at the normal point; 103 /// otherwise, clear the Started flag to indicate that passes should not be 104 /// added until the starting pass is seen. If the Stop pass ID is zero, 105 /// then compilation will continue to the end. 106 void setStartStopPasses(AnalysisID Start, AnalysisID Stop) { 107 StartAfter = Start; 108 StopAfter = Stop; 109 Started = (StartAfter == 0); 110 } 111 112 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } 113 114 bool getEnableTailMerge() const { return EnableTailMerge; } 115 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } 116 117 /// Allow the target to override a specific pass without overriding the pass 118 /// pipeline. When passes are added to the standard pipeline at the 119 /// point where StandardID is expected, add TargetID in its place. 120 void substitutePass(AnalysisID StandardID, AnalysisID TargetID); 121 122 /// Insert InsertedPassID pass after TargetPassID pass. 123 void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID); 124 125 /// Allow the target to enable a specific standard pass by default. 126 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); } 127 128 /// Allow the target to disable a specific standard pass by default. 129 void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); } 130 131 /// Return the pass substituted for StandardID by the target. 132 /// If no substitution exists, return StandardID. 133 AnalysisID getPassSubstitution(AnalysisID StandardID) const; 134 135 /// Return true if the optimized regalloc pipeline is enabled. 136 bool getOptimizeRegAlloc() const; 137 138 /// Add common target configurable passes that perform LLVM IR to IR 139 /// transforms following machine independent optimization. 140 virtual void addIRPasses(); 141 142 /// Add passes to lower exception handling for the code generator. 143 void addPassesToHandleExceptions(); 144 145 /// Add pass to prepare the LLVM IR for code generation. This should be done 146 /// before exception handling preparation passes. 147 virtual void addCodeGenPrepare(); 148 149 /// Add common passes that perform LLVM IR to IR transforms in preparation for 150 /// instruction selection. 151 virtual void addISelPrepare(); 152 153 /// addInstSelector - This method should install an instruction selector pass, 154 /// which converts from LLVM code to machine instructions. 155 virtual bool addInstSelector() { 156 return true; 157 } 158 159 /// Add the complete, standard set of LLVM CodeGen passes. 160 /// Fully developed targets will not generally override this. 161 virtual void addMachinePasses(); 162 163protected: 164 // Helper to verify the analysis is really immutable. 165 void setOpt(bool &Opt, bool Val); 166 167 /// Methods with trivial inline returns are convenient points in the common 168 /// codegen pass pipeline where targets may insert passes. Methods with 169 /// out-of-line standard implementations are major CodeGen stages called by 170 /// addMachinePasses. Some targets may override major stages when inserting 171 /// passes is insufficient, but maintaining overriden stages is more work. 172 /// 173 174 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 175 /// passes (which are run just before instruction selector). 176 virtual bool addPreISel() { 177 return true; 178 } 179 180 /// addMachineSSAOptimization - Add standard passes that optimize machine 181 /// instructions in SSA form. 182 virtual void addMachineSSAOptimization(); 183 184 /// Add passes that optimize instruction level parallelism for out-of-order 185 /// targets. These passes are run while the machine code is still in SSA 186 /// form, so they can use MachineTraceMetrics to control their heuristics. 187 /// 188 /// All passes added here should preserve the MachineDominatorTree, 189 /// MachineLoopInfo, and MachineTraceMetrics analyses. 190 virtual bool addILPOpts() { 191 return false; 192 } 193 194 /// addPreRegAlloc - This method may be implemented by targets that want to 195 /// run passes immediately before register allocation. This should return 196 /// true if -print-machineinstrs should print after these passes. 197 virtual bool addPreRegAlloc() { 198 return false; 199 } 200 201 /// createTargetRegisterAllocator - Create the register allocator pass for 202 /// this target at the current optimization level. 203 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); 204 205 /// addFastRegAlloc - Add the minimum set of target-independent passes that 206 /// are required for fast register allocation. 207 virtual void addFastRegAlloc(FunctionPass *RegAllocPass); 208 209 /// addOptimizedRegAlloc - Add passes related to register allocation. 210 /// LLVMTargetMachine provides standard regalloc passes for most targets. 211 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); 212 213 /// addPreRewrite - Add passes to the optimized register allocation pipeline 214 /// after register allocation is complete, but before virtual registers are 215 /// rewritten to physical registers. 216 /// 217 /// These passes must preserve VirtRegMap and LiveIntervals, and when running 218 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. 219 /// When these passes run, VirtRegMap contains legal physreg assignments for 220 /// all virtual registers. 221 virtual bool addPreRewrite() { 222 return false; 223 } 224 225 /// addFinalizeRegAlloc - This method may be implemented by targets that want 226 /// to run passes within the regalloc pipeline, immediately after the register 227 /// allocation pass itself. These passes run as soon as virtual regisiters 228 /// have been rewritten to physical registers but before and other postRA 229 /// optimization happens. Targets that have marked instructions for bundling 230 /// must have finalized those bundles by the time these passes have run, 231 /// because subsequent passes are not guaranteed to be bundle-aware. 232 virtual bool addFinalizeRegAlloc() { 233 return false; 234 } 235 236 /// addPostRegAlloc - This method may be implemented by targets that want to 237 /// run passes after register allocation pass pipeline but before 238 /// prolog-epilog insertion. This should return true if -print-machineinstrs 239 /// should print after these passes. 240 virtual bool addPostRegAlloc() { 241 return false; 242 } 243 244 /// Add passes that optimize machine instructions after register allocation. 245 virtual void addMachineLateOptimization(); 246 247 /// addPreSched2 - This method may be implemented by targets that want to 248 /// run passes after prolog-epilog insertion and before the second instruction 249 /// scheduling pass. This should return true if -print-machineinstrs should 250 /// print after these passes. 251 virtual bool addPreSched2() { 252 return false; 253 } 254 255 /// addGCPasses - Add late codegen passes that analyze code for garbage 256 /// collection. This should return true if GC info should be printed after 257 /// these passes. 258 virtual bool addGCPasses(); 259 260 /// Add standard basic block placement passes. 261 virtual void addBlockPlacement(); 262 263 /// addPreEmitPass - This pass may be implemented by targets that want to run 264 /// passes immediately before machine code is emitted. This should return 265 /// true if -print-machineinstrs should print out the code after the passes. 266 virtual bool addPreEmitPass() { 267 return false; 268 } 269 270 /// Utilities for targets to add passes to the pass manager. 271 /// 272 273 /// Add a CodeGen pass at this point in the pipeline after checking overrides. 274 /// Return the pass that was added, or zero if no pass was added. 275 AnalysisID addPass(AnalysisID PassID); 276 277 /// Add a pass to the PassManager if that pass is supposed to be run, as 278 /// determined by the StartAfter and StopAfter options. 279 void addPass(Pass *P); 280 281 /// addMachinePasses helper to create the target-selected or overriden 282 /// regalloc pass. 283 FunctionPass *createRegAllocPass(bool Optimized); 284 285 /// printAndVerify - Add a pass to dump then verify the machine function, if 286 /// those steps are enabled. 287 /// 288 void printAndVerify(const char *Banner); 289}; 290} // namespace llvm 291 292/// List of target independent CodeGen pass IDs. 293namespace llvm { 294 /// \brief Create a basic TargetTransformInfo analysis pass. 295 /// 296 /// This pass implements the target transform info analysis using the target 297 /// independent information available to the LLVM code generator. 298 ImmutablePass * 299 createBasicTargetTransformInfoPass(const TargetLoweringBase *TLI); 300 301 /// createUnreachableBlockEliminationPass - The LLVM code generator does not 302 /// work well with unreachable basic blocks (what live ranges make sense for a 303 /// block that cannot be reached?). As such, a code generator should either 304 /// not instruction select unreachable blocks, or run this pass as its 305 /// last LLVM modifying pass to clean up blocks that are not reachable from 306 /// the entry block. 307 FunctionPass *createUnreachableBlockEliminationPass(); 308 309 /// MachineFunctionPrinter pass - This pass prints out the machine function to 310 /// the given stream as a debugging tool. 311 MachineFunctionPass * 312 createMachineFunctionPrinterPass(raw_ostream &OS, 313 const std::string &Banner =""); 314 315 /// MachineLoopInfo - This pass is a loop analysis pass. 316 extern char &MachineLoopInfoID; 317 318 /// MachineDominators - This pass is a machine dominators analysis pass. 319 extern char &MachineDominatorsID; 320 321 /// EdgeBundles analysis - Bundle machine CFG edges. 322 extern char &EdgeBundlesID; 323 324 /// LiveVariables pass - This pass computes the set of blocks in which each 325 /// variable is life and sets machine operand kill flags. 326 extern char &LiveVariablesID; 327 328 /// PHIElimination - This pass eliminates machine instruction PHI nodes 329 /// by inserting copy instructions. This destroys SSA information, but is the 330 /// desired input for some register allocators. This pass is "required" by 331 /// these register allocator like this: AU.addRequiredID(PHIEliminationID); 332 extern char &PHIEliminationID; 333 334 /// StrongPHIElimination - This pass eliminates machine instruction PHI 335 /// nodes by inserting copy instructions. This destroys SSA information, but 336 /// is the desired input for some register allocators. This pass is 337 /// "required" by these register allocator like this: 338 /// AU.addRequiredID(PHIEliminationID); 339 /// This pass is still in development 340 extern char &StrongPHIEliminationID; 341 342 /// LiveIntervals - This analysis keeps track of the live ranges of virtual 343 /// and physical registers. 344 extern char &LiveIntervalsID; 345 346 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. 347 extern char &LiveStacksID; 348 349 /// TwoAddressInstruction - This pass reduces two-address instructions to 350 /// use two operands. This destroys SSA information but it is desired by 351 /// register allocators. 352 extern char &TwoAddressInstructionPassID; 353 354 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. 355 extern char &ProcessImplicitDefsID; 356 357 /// RegisterCoalescer - This pass merges live ranges to eliminate copies. 358 extern char &RegisterCoalescerID; 359 360 /// MachineScheduler - This pass schedules machine instructions. 361 extern char &MachineSchedulerID; 362 363 /// SpillPlacement analysis. Suggest optimal placement of spill code between 364 /// basic blocks. 365 extern char &SpillPlacementID; 366 367 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as 368 /// assigned in VirtRegMap. 369 extern char &VirtRegRewriterID; 370 371 /// UnreachableMachineBlockElimination - This pass removes unreachable 372 /// machine basic blocks. 373 extern char &UnreachableMachineBlockElimID; 374 375 /// DeadMachineInstructionElim - This pass removes dead machine instructions. 376 extern char &DeadMachineInstructionElimID; 377 378 /// FastRegisterAllocation Pass - This pass register allocates as fast as 379 /// possible. It is best suited for debug code where live ranges are short. 380 /// 381 FunctionPass *createFastRegisterAllocator(); 382 383 /// BasicRegisterAllocation Pass - This pass implements a degenerate global 384 /// register allocator using the basic regalloc framework. 385 /// 386 FunctionPass *createBasicRegisterAllocator(); 387 388 /// Greedy register allocation pass - This pass implements a global register 389 /// allocator for optimized builds. 390 /// 391 FunctionPass *createGreedyRegisterAllocator(); 392 393 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean 394 /// Quadratic Prograaming (PBQP) based register allocator. 395 /// 396 FunctionPass *createDefaultPBQPRegisterAllocator(); 397 398 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, 399 /// and eliminates abstract frame references. 400 extern char &PrologEpilogCodeInserterID; 401 402 /// ExpandPostRAPseudos - This pass expands pseudo instructions after 403 /// register allocation. 404 extern char &ExpandPostRAPseudosID; 405 406 /// createPostRAScheduler - This pass performs post register allocation 407 /// scheduling. 408 extern char &PostRASchedulerID; 409 410 /// BranchFolding - This pass performs machine code CFG based 411 /// optimizations to delete branches to branches, eliminate branches to 412 /// successor blocks (creating fall throughs), and eliminating branches over 413 /// branches. 414 extern char &BranchFolderPassID; 415 416 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. 417 extern char &MachineFunctionPrinterPassID; 418 419 /// TailDuplicate - Duplicate blocks with unconditional branches 420 /// into tails of their predecessors. 421 extern char &TailDuplicateID; 422 423 /// MachineTraceMetrics - This pass computes critical path and CPU resource 424 /// usage in an ensemble of traces. 425 extern char &MachineTraceMetricsID; 426 427 /// EarlyIfConverter - This pass performs if-conversion on SSA form by 428 /// inserting cmov instructions. 429 extern char &EarlyIfConverterID; 430 431 /// StackSlotColoring - This pass performs stack coloring and merging. 432 /// It merges disjoint allocas to reduce the stack size. 433 extern char &StackColoringID; 434 435 /// IfConverter - This pass performs machine code if conversion. 436 extern char &IfConverterID; 437 438 /// MachineBlockPlacement - This pass places basic blocks based on branch 439 /// probabilities. 440 extern char &MachineBlockPlacementID; 441 442 /// MachineBlockPlacementStats - This pass collects statistics about the 443 /// basic block placement using branch probabilities and block frequency 444 /// information. 445 extern char &MachineBlockPlacementStatsID; 446 447 /// Code Placement - This pass optimize code placement and aligns loop 448 /// headers to target specific alignment boundary. 449 extern char &CodePlacementOptID; 450 451 /// GCLowering Pass - Performs target-independent LLVM IR transformations for 452 /// highly portable strategies. 453 /// 454 FunctionPass *createGCLoweringPass(); 455 456 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points 457 /// in machine code. Must be added very late during code generation, just 458 /// prior to output, and importantly after all CFG transformations (such as 459 /// branch folding). 460 extern char &GCMachineCodeAnalysisID; 461 462 /// Creates a pass to print GC metadata. 463 /// 464 FunctionPass *createGCInfoPrinter(raw_ostream &OS); 465 466 /// MachineCSE - This pass performs global CSE on machine instructions. 467 extern char &MachineCSEID; 468 469 /// MachineLICM - This pass performs LICM on machine instructions. 470 extern char &MachineLICMID; 471 472 /// MachineSinking - This pass performs sinking on machine instructions. 473 extern char &MachineSinkingID; 474 475 /// MachineCopyPropagation - This pass performs copy propagation on 476 /// machine instructions. 477 extern char &MachineCopyPropagationID; 478 479 /// PeepholeOptimizer - This pass performs peephole optimizations - 480 /// like extension and comparison eliminations. 481 extern char &PeepholeOptimizerID; 482 483 /// OptimizePHIs - This pass optimizes machine instruction PHIs 484 /// to take advantage of opportunities created during DAG legalization. 485 extern char &OptimizePHIsID; 486 487 /// StackSlotColoring - This pass performs stack slot coloring. 488 extern char &StackSlotColoringID; 489 490 /// createStackProtectorPass - This pass adds stack protectors to functions. 491 /// 492 FunctionPass *createStackProtectorPass(const TargetLoweringBase *tli); 493 494 /// createMachineVerifierPass - This pass verifies cenerated machine code 495 /// instructions for correctness. 496 /// 497 FunctionPass *createMachineVerifierPass(const char *Banner = 0); 498 499 /// createDwarfEHPass - This pass mulches exception handling code into a form 500 /// adapted to code generation. Required if using dwarf exception handling. 501 FunctionPass *createDwarfEHPass(const TargetMachine *tm); 502 503 /// createSjLjEHPreparePass - This pass adapts exception handling code to use 504 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. 505 /// 506 FunctionPass *createSjLjEHPreparePass(const TargetLoweringBase *tli); 507 508 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack 509 /// slots relative to one another and allocates base registers to access them 510 /// when it is estimated by the target to be out of range of normal frame 511 /// pointer or stack pointer index addressing. 512 extern char &LocalStackSlotAllocationID; 513 514 /// ExpandISelPseudos - This pass expands pseudo-instructions. 515 extern char &ExpandISelPseudosID; 516 517 /// createExecutionDependencyFixPass - This pass fixes execution time 518 /// problems with dependent instructions, such as switching execution 519 /// domains to match. 520 /// 521 /// The pass will examine instructions using and defining registers in RC. 522 /// 523 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); 524 525 /// UnpackMachineBundles - This pass unpack machine instruction bundles. 526 extern char &UnpackMachineBundlesID; 527 528 /// FinalizeMachineBundles - This pass finalize machine instruction 529 /// bundles (created earlier, e.g. during pre-RA scheduling). 530 extern char &FinalizeMachineBundlesID; 531 532} // End llvm namespace 533 534#endif 535