LLVMTargetMachine.cpp revision 262a96edb436543227b9b5e49f95a082e1c73b5f
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LLVMTargetMachine class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetMachine.h" 15#include "llvm/PassManager.h" 16#include "llvm/Pass.h" 17#include "llvm/Assembly/PrintModulePass.h" 18#include "llvm/CodeGen/AsmPrinter.h" 19#include "llvm/CodeGen/Passes.h" 20#include "llvm/CodeGen/GCStrategy.h" 21#include "llvm/CodeGen/MachineFunctionAnalysis.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/MC/MCAsmInfo.h" 24#include "llvm/Target/TargetRegistry.h" 25#include "llvm/Transforms/Scalar.h" 26#include "llvm/Support/CommandLine.h" 27#include "llvm/Support/Debug.h" 28#include "llvm/Support/FormattedStream.h" 29using namespace llvm; 30 31namespace llvm { 32 bool EnableFastISel; 33} 34 35static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden, 36 cl::desc("Disable Post Regalloc")); 37static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, 38 cl::desc("Disable branch folding")); 39static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, 40 cl::desc("Disable tail duplication")); 41static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden, 42 cl::desc("Disable code placement")); 43static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, 44 cl::desc("Disable Stack Slot Coloring")); 45static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, 46 cl::desc("Disable Machine LICM")); 47static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, 48 cl::desc("Disable Machine Sinking")); 49static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, 50 cl::desc("Disable Loop Strength Reduction Pass")); 51static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, 52 cl::desc("Disable Codegen Prepare")); 53static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, 54 cl::desc("Print LLVM IR produced by the loop-reduce pass")); 55static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, 56 cl::desc("Print LLVM IR input to isel pass")); 57static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden, 58 cl::desc("Dump emitter generated instructions as assembly")); 59static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, 60 cl::desc("Dump garbage collector data")); 61static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden, 62 cl::desc("Verify generated machine code"), 63 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL)); 64 65 66// Enable or disable FastISel. Both options are needed, because 67// FastISel is enabled by default with -fast, and we wish to be 68// able to enable or disable fast-isel independently from -O0. 69static cl::opt<cl::boolOrDefault> 70EnableFastISelOption("fast-isel", cl::Hidden, 71 cl::desc("Enable the \"fast\" instruction selector")); 72 73// Enable or disable an experimental optimization to split GEPs 74// and run a special GVN pass which does not examine loads, in 75// an effort to factor out redundancy implicit in complex GEPs. 76static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden, 77 cl::desc("Split GEPs and run no-load GVN")); 78 79static cl::opt<bool> PreAllocTailDup("pre-regalloc-taildup", cl::Hidden, 80 cl::desc("Pre-register allocation tail duplication")); 81 82LLVMTargetMachine::LLVMTargetMachine(const Target &T, 83 const std::string &TargetTriple) 84 : TargetMachine(T) { 85 AsmInfo = T.createAsmInfo(TargetTriple); 86} 87 88// Set the default code model for the JIT for a generic target. 89// FIXME: Is small right here? or .is64Bit() ? Large : Small? 90void 91LLVMTargetMachine::setCodeModelForJIT() { 92 setCodeModel(CodeModel::Small); 93} 94 95// Set the default code model for static compilation for a generic target. 96void 97LLVMTargetMachine::setCodeModelForStatic() { 98 setCodeModel(CodeModel::Small); 99} 100 101FileModel::Model 102LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, 103 formatted_raw_ostream &Out, 104 CodeGenFileType FileType, 105 CodeGenOpt::Level OptLevel) { 106 // Add common CodeGen passes. 107 if (addCommonCodeGenPasses(PM, OptLevel)) 108 return FileModel::Error; 109 110 switch (FileType) { 111 default: 112 break; 113 case TargetMachine::AssemblyFile: 114 if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out)) 115 return FileModel::Error; 116 return FileModel::AsmFile; 117 case TargetMachine::ObjectFile: 118 if (getMachOWriterInfo()) 119 return FileModel::MachOFile; 120 else if (getELFWriterInfo()) 121 return FileModel::ElfFile; 122 } 123 124 return FileModel::Error; 125} 126 127bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, 128 CodeGenOpt::Level OptLevel, 129 bool Verbose, 130 formatted_raw_ostream &Out) { 131 FunctionPass *Printer = 132 getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose); 133 if (!Printer) 134 return true; 135 136 PM.add(Printer); 137 return false; 138} 139 140/// addPassesToEmitFileFinish - If the passes to emit the specified file had to 141/// be split up (e.g., to add an object writer pass), this method can be used to 142/// finish up adding passes to emit the file, if necessary. 143bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, 144 MachineCodeEmitter *MCE, 145 CodeGenOpt::Level OptLevel) { 146 // Make sure the code model is set. 147 setCodeModelForStatic(); 148 149 if (MCE) 150 addSimpleCodeEmitter(PM, OptLevel, *MCE); 151 if (PrintEmittedAsm) 152 addAssemblyEmitter(PM, OptLevel, true, ferrs()); 153 154 PM.add(createGCInfoDeleter()); 155 156 return false; // success! 157} 158 159/// addPassesToEmitFileFinish - If the passes to emit the specified file had to 160/// be split up (e.g., to add an object writer pass), this method can be used to 161/// finish up adding passes to emit the file, if necessary. 162bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, 163 JITCodeEmitter *JCE, 164 CodeGenOpt::Level OptLevel) { 165 // Make sure the code model is set. 166 setCodeModelForJIT(); 167 168 if (JCE) 169 addSimpleCodeEmitter(PM, OptLevel, *JCE); 170 if (PrintEmittedAsm) 171 addAssemblyEmitter(PM, OptLevel, true, ferrs()); 172 173 PM.add(createGCInfoDeleter()); 174 175 return false; // success! 176} 177 178/// addPassesToEmitFileFinish - If the passes to emit the specified file had to 179/// be split up (e.g., to add an object writer pass), this method can be used to 180/// finish up adding passes to emit the file, if necessary. 181bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, 182 ObjectCodeEmitter *OCE, 183 CodeGenOpt::Level OptLevel) { 184 // Make sure the code model is set. 185 setCodeModelForStatic(); 186 187 if (OCE) 188 addSimpleCodeEmitter(PM, OptLevel, *OCE); 189 if (PrintEmittedAsm) 190 addAssemblyEmitter(PM, OptLevel, true, ferrs()); 191 192 PM.add(createGCInfoDeleter()); 193 194 return false; // success! 195} 196 197/// addPassesToEmitMachineCode - Add passes to the specified pass manager to 198/// get machine code emitted. This uses a MachineCodeEmitter object to handle 199/// actually outputting the machine code and resolving things like the address 200/// of functions. This method should returns true if machine code emission is 201/// not supported. 202/// 203bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, 204 MachineCodeEmitter &MCE, 205 CodeGenOpt::Level OptLevel) { 206 // Make sure the code model is set. 207 setCodeModelForJIT(); 208 209 // Add common CodeGen passes. 210 if (addCommonCodeGenPasses(PM, OptLevel)) 211 return true; 212 213 addCodeEmitter(PM, OptLevel, MCE); 214 if (PrintEmittedAsm) 215 addAssemblyEmitter(PM, OptLevel, true, ferrs()); 216 217 PM.add(createGCInfoDeleter()); 218 219 return false; // success! 220} 221 222/// addPassesToEmitMachineCode - Add passes to the specified pass manager to 223/// get machine code emitted. This uses a MachineCodeEmitter object to handle 224/// actually outputting the machine code and resolving things like the address 225/// of functions. This method should returns true if machine code emission is 226/// not supported. 227/// 228bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, 229 JITCodeEmitter &JCE, 230 CodeGenOpt::Level OptLevel) { 231 // Make sure the code model is set. 232 setCodeModelForJIT(); 233 234 // Add common CodeGen passes. 235 if (addCommonCodeGenPasses(PM, OptLevel)) 236 return true; 237 238 addCodeEmitter(PM, OptLevel, JCE); 239 if (PrintEmittedAsm) 240 addAssemblyEmitter(PM, OptLevel, true, ferrs()); 241 242 PM.add(createGCInfoDeleter()); 243 244 return false; // success! 245} 246 247static void printAndVerify(PassManagerBase &PM, 248 const char *Banner, 249 bool allowDoubleDefs = false) { 250 if (PrintMachineCode) 251 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner)); 252 253 if (VerifyMachineCode) 254 PM.add(createMachineVerifierPass(allowDoubleDefs)); 255} 256 257/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both 258/// emitting to assembly files or machine code output. 259/// 260bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, 261 CodeGenOpt::Level OptLevel) { 262 // Standard LLVM-Level Passes. 263 264 // Optionally, tun split-GEPs and no-load GVN. 265 if (EnableSplitGEPGVN) { 266 PM.add(createGEPSplitterPass()); 267 PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true)); 268 } 269 270 // Run loop strength reduction before anything else. 271 if (OptLevel != CodeGenOpt::None && !DisableLSR) { 272 PM.add(createLoopStrengthReducePass(getTargetLowering())); 273 if (PrintLSR) 274 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs())); 275 } 276 277 // Turn exception handling constructs into something the code generators can 278 // handle. 279 switch (getMCAsmInfo()->getExceptionHandlingType()) 280 { 281 case ExceptionHandling::SjLj: 282 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 283 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None)); 284 PM.add(createSjLjEHPass(getTargetLowering())); 285 break; 286 case ExceptionHandling::Dwarf: 287 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None)); 288 break; 289 case ExceptionHandling::None: 290 PM.add(createLowerInvokePass(getTargetLowering())); 291 break; 292 } 293 294 PM.add(createGCLoweringPass()); 295 296 // Make sure that no unreachable blocks are instruction selected. 297 PM.add(createUnreachableBlockEliminationPass()); 298 299 if (OptLevel != CodeGenOpt::None && !DisableCGP) 300 PM.add(createCodeGenPreparePass(getTargetLowering())); 301 302 PM.add(createStackProtectorPass(getTargetLowering())); 303 304 if (PrintISelInput) 305 PM.add(createPrintFunctionPass("\n\n" 306 "*** Final LLVM Code input to ISel ***\n", 307 &dbgs())); 308 309 // Standard Lower-Level Passes. 310 311 // Set up a MachineFunction for the rest of CodeGen to work on. 312 PM.add(new MachineFunctionAnalysis(*this, OptLevel)); 313 314 // Enable FastISel with -fast, but allow that to be overridden. 315 if (EnableFastISelOption == cl::BOU_TRUE || 316 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE)) 317 EnableFastISel = true; 318 319 // Ask the target for an isel. 320 if (addInstSelector(PM, OptLevel)) 321 return true; 322 323 // Print the instruction selected machine code... 324 printAndVerify(PM, "After Instruction Selection", 325 /* allowDoubleDefs= */ true); 326 327 if (OptLevel != CodeGenOpt::None) { 328 if (!DisableMachineLICM) 329 PM.add(createMachineLICMPass()); 330 if (!DisableMachineSink) 331 PM.add(createMachineSinkingPass()); 332 printAndVerify(PM, "After MachineLICM and MachineSinking", 333 /* allowDoubleDefs= */ true); 334 } 335 336 // Pre-ra tail duplication. 337 if (OptLevel != CodeGenOpt::None && 338 !DisableTailDuplicate && PreAllocTailDup) { 339 PM.add(createTailDuplicatePass(true)); 340 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate", 341 /* allowDoubleDefs= */ true); 342 } 343 344 // Run pre-ra passes. 345 if (addPreRegAlloc(PM, OptLevel)) 346 printAndVerify(PM, "After PreRegAlloc passes", 347 /* allowDoubleDefs= */ true); 348 349 // Perform register allocation. 350 PM.add(createRegisterAllocator()); 351 printAndVerify(PM, "After Register Allocation"); 352 353 // Perform stack slot coloring. 354 if (OptLevel != CodeGenOpt::None && !DisableSSC) { 355 // FIXME: Re-enable coloring with register when it's capable of adding 356 // kill markers. 357 PM.add(createStackSlotColoringPass(false)); 358 printAndVerify(PM, "After StackSlotColoring"); 359 } 360 361 // Run post-ra passes. 362 if (addPostRegAlloc(PM, OptLevel)) 363 printAndVerify(PM, "After PostRegAlloc passes"); 364 365 PM.add(createLowerSubregsPass()); 366 printAndVerify(PM, "After LowerSubregs"); 367 368 // Insert prolog/epilog code. Eliminate abstract frame index references... 369 PM.add(createPrologEpilogCodeInserter()); 370 printAndVerify(PM, "After PrologEpilogCodeInserter"); 371 372 // Run pre-sched2 passes. 373 if (addPreSched2(PM, OptLevel)) 374 printAndVerify(PM, "After PreSched2 passes"); 375 376 // Second pass scheduler. 377 if (OptLevel != CodeGenOpt::None && !DisablePostRA) { 378 PM.add(createPostRAScheduler(OptLevel)); 379 printAndVerify(PM, "After PostRAScheduler"); 380 } 381 382 // Branch folding must be run after regalloc and prolog/epilog insertion. 383 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) { 384 PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); 385 printAndVerify(PM, "After BranchFolding"); 386 } 387 388 // Tail duplication. 389 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) { 390 PM.add(createTailDuplicatePass(false)); 391 printAndVerify(PM, "After TailDuplicate"); 392 } 393 394 PM.add(createGCMachineCodeAnalysisPass()); 395 396 if (PrintGCInfo) 397 PM.add(createGCInfoPrinter(dbgs())); 398 399 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) { 400 PM.add(createCodePlacementOptPass()); 401 printAndVerify(PM, "After CodePlacementOpt"); 402 } 403 404 if (addPreEmitPass(PM, OptLevel)) 405 printAndVerify(PM, "After PreEmit passes"); 406 407 return false; 408} 409