LLVMTargetMachine.cpp revision 572645cf84060c0fc25cb91d38cb9079918b3a88
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LLVMTargetMachine class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetMachine.h" 15#include "llvm/PassManager.h" 16#include "llvm/Pass.h" 17#include "llvm/Analysis/Verifier.h" 18#include "llvm/Assembly/PrintModulePass.h" 19#include "llvm/CodeGen/AsmPrinter.h" 20#include "llvm/CodeGen/Passes.h" 21#include "llvm/CodeGen/GCStrategy.h" 22#include "llvm/CodeGen/MachineFunctionAnalysis.h" 23#include "llvm/Target/TargetOptions.h" 24#include "llvm/MC/MCAsmInfo.h" 25#include "llvm/MC/MCContext.h" 26#include "llvm/MC/MCStreamer.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetRegistry.h" 29#include "llvm/Transforms/Scalar.h" 30#include "llvm/ADT/OwningPtr.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/FormattedStream.h" 34using namespace llvm; 35 36namespace llvm { 37 bool EnableFastISel; 38} 39 40static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden, 41 cl::desc("Disable Post Regalloc")); 42static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, 43 cl::desc("Disable branch folding")); 44static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, 45 cl::desc("Disable tail duplication")); 46static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden, 47 cl::desc("Disable pre-register allocation tail duplication")); 48static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden, 49 cl::desc("Disable code placement")); 50static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, 51 cl::desc("Disable Stack Slot Coloring")); 52static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, 53 cl::desc("Disable Machine LICM")); 54static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, 55 cl::desc("Disable Machine Sinking")); 56static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, 57 cl::desc("Disable Loop Strength Reduction Pass")); 58static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, 59 cl::desc("Disable Codegen Prepare")); 60static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, 61 cl::desc("Print LLVM IR produced by the loop-reduce pass")); 62static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, 63 cl::desc("Print LLVM IR input to isel pass")); 64static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, 65 cl::desc("Dump garbage collector data")); 66static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden, 67 cl::desc("Verify generated machine code"), 68 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL)); 69 70static cl::opt<cl::boolOrDefault> 71AsmVerbose("asm-verbose", cl::desc("Add comments to directives."), 72 cl::init(cl::BOU_UNSET)); 73 74static bool getVerboseAsm() { 75 switch (AsmVerbose) { 76 default: 77 case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault(); 78 case cl::BOU_TRUE: return true; 79 case cl::BOU_FALSE: return false; 80 } 81} 82 83// Enable or disable FastISel. Both options are needed, because 84// FastISel is enabled by default with -fast, and we wish to be 85// able to enable or disable fast-isel independently from -O0. 86static cl::opt<cl::boolOrDefault> 87EnableFastISelOption("fast-isel", cl::Hidden, 88 cl::desc("Enable the \"fast\" instruction selector")); 89 90// Enable or disable an experimental optimization to split GEPs 91// and run a special GVN pass which does not examine loads, in 92// an effort to factor out redundancy implicit in complex GEPs. 93static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden, 94 cl::desc("Split GEPs and run no-load GVN")); 95 96LLVMTargetMachine::LLVMTargetMachine(const Target &T, 97 const std::string &TargetTriple) 98 : TargetMachine(T) { 99 AsmInfo = T.createAsmInfo(TargetTriple); 100} 101 102// Set the default code model for the JIT for a generic target. 103// FIXME: Is small right here? or .is64Bit() ? Large : Small? 104void 105LLVMTargetMachine::setCodeModelForJIT() { 106 setCodeModel(CodeModel::Small); 107} 108 109// Set the default code model for static compilation for a generic target. 110void 111LLVMTargetMachine::setCodeModelForStatic() { 112 setCodeModel(CodeModel::Small); 113} 114 115bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, 116 formatted_raw_ostream &Out, 117 CodeGenFileType FileType, 118 CodeGenOpt::Level OptLevel) { 119 // Add common CodeGen passes. 120 if (addCommonCodeGenPasses(PM, OptLevel)) 121 return true; 122 123 OwningPtr<MCContext> Context(new MCContext()); 124 OwningPtr<MCStreamer> AsmStreamer; 125 126 formatted_raw_ostream *LegacyOutput; 127 switch (FileType) { 128 default: return true; 129 case CGFT_AssemblyFile: { 130 const MCAsmInfo &MAI = *getMCAsmInfo(); 131 MCInstPrinter *InstPrinter = 132 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, Out); 133 AsmStreamer.reset(createAsmStreamer(*Context, Out, MAI, 134 getTargetData()->isLittleEndian(), 135 getVerboseAsm(), InstPrinter, 136 /*codeemitter*/0)); 137 // Set the AsmPrinter's "O" to the output file. 138 LegacyOutput = &Out; 139 break; 140 } 141 case CGFT_ObjectFile: { 142 // Create the code emitter for the target if it exists. If not, .o file 143 // emission fails. 144 MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this); 145 if (MCE == 0) 146 return true; 147 148 AsmStreamer.reset(createMachOStreamer(*Context, Out, MCE)); 149 150 // Any output to the asmprinter's "O" stream is bad and needs to be fixed, 151 // force it to come out stderr. 152 // FIXME: this is horrible and leaks, eventually remove the raw_ostream from 153 // asmprinter. 154 LegacyOutput = new formatted_raw_ostream(errs()); 155 break; 156 } 157 case CGFT_Null: 158 // The Null output is intended for use for performance analysis and testing, 159 // not real users. 160 AsmStreamer.reset(createNullStreamer(*Context)); 161 // Any output to the asmprinter's "O" stream is bad and needs to be fixed, 162 // force it to come out stderr. 163 // FIXME: this is horrible and leaks, eventually remove the raw_ostream from 164 // asmprinter. 165 LegacyOutput = new formatted_raw_ostream(errs()); 166 break; 167 } 168 169 // Create the AsmPrinter, which takes ownership of Context and AsmStreamer 170 // if successful. 171 FunctionPass *Printer = 172 getTarget().createAsmPrinter(*LegacyOutput, *this, *Context, *AsmStreamer, 173 getMCAsmInfo()); 174 if (Printer == 0) 175 return true; 176 177 // If successful, createAsmPrinter took ownership of AsmStreamer and Context. 178 Context.take(); AsmStreamer.take(); 179 180 PM.add(Printer); 181 182 // Make sure the code model is set. 183 setCodeModelForStatic(); 184 PM.add(createGCInfoDeleter()); 185 return false; 186} 187 188/// addPassesToEmitMachineCode - Add passes to the specified pass manager to 189/// get machine code emitted. This uses a JITCodeEmitter object to handle 190/// actually outputting the machine code and resolving things like the address 191/// of functions. This method should returns true if machine code emission is 192/// not supported. 193/// 194bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, 195 JITCodeEmitter &JCE, 196 CodeGenOpt::Level OptLevel) { 197 // Make sure the code model is set. 198 setCodeModelForJIT(); 199 200 // Add common CodeGen passes. 201 if (addCommonCodeGenPasses(PM, OptLevel)) 202 return true; 203 204 addCodeEmitter(PM, OptLevel, JCE); 205 PM.add(createGCInfoDeleter()); 206 207 return false; // success! 208} 209 210static void printAndVerify(PassManagerBase &PM, 211 const char *Banner, 212 bool allowDoubleDefs = false) { 213 if (PrintMachineCode) 214 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner)); 215 216 if (VerifyMachineCode) 217 PM.add(createMachineVerifierPass(allowDoubleDefs)); 218} 219 220/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both 221/// emitting to assembly files or machine code output. 222/// 223bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, 224 CodeGenOpt::Level OptLevel) { 225 // Standard LLVM-Level Passes. 226 227 // Optionally, tun split-GEPs and no-load GVN. 228 if (EnableSplitGEPGVN) { 229 PM.add(createGEPSplitterPass()); 230 PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true)); 231 } 232 233 // Run loop strength reduction before anything else. 234 if (OptLevel != CodeGenOpt::None && !DisableLSR) { 235 PM.add(createLoopStrengthReducePass(getTargetLowering())); 236 if (PrintLSR) 237 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs())); 238#ifndef NDEBUG 239 PM.add(createVerifierPass()); 240#endif 241 } 242 243 // Turn exception handling constructs into something the code generators can 244 // handle. 245 switch (getMCAsmInfo()->getExceptionHandlingType()) 246 { 247 case ExceptionHandling::SjLj: 248 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 249 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, 250 // catch info can get misplaced when a selector ends up more than one block 251 // removed from the parent invoke(s). This could happen when a landing 252 // pad is shared by multiple invokes and is also a target of a normal 253 // edge from elsewhere. 254 PM.add(createSjLjEHPass(getTargetLowering())); 255 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None)); 256 break; 257 case ExceptionHandling::Dwarf: 258 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None)); 259 break; 260 case ExceptionHandling::None: 261 PM.add(createLowerInvokePass(getTargetLowering())); 262 break; 263 } 264 265 PM.add(createGCLoweringPass()); 266 267 // Make sure that no unreachable blocks are instruction selected. 268 PM.add(createUnreachableBlockEliminationPass()); 269 270 if (OptLevel != CodeGenOpt::None && !DisableCGP) 271 PM.add(createCodeGenPreparePass(getTargetLowering())); 272 273 PM.add(createStackProtectorPass(getTargetLowering())); 274 275 if (PrintISelInput) 276 PM.add(createPrintFunctionPass("\n\n" 277 "*** Final LLVM Code input to ISel ***\n", 278 &dbgs())); 279 280 // Standard Lower-Level Passes. 281 282 // Set up a MachineFunction for the rest of CodeGen to work on. 283 PM.add(new MachineFunctionAnalysis(*this, OptLevel)); 284 285 // Enable FastISel with -fast, but allow that to be overridden. 286 if (EnableFastISelOption == cl::BOU_TRUE || 287 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE)) 288 EnableFastISel = true; 289 290 // Ask the target for an isel. 291 if (addInstSelector(PM, OptLevel)) 292 return true; 293 294 // Print the instruction selected machine code... 295 printAndVerify(PM, "After Instruction Selection", 296 /* allowDoubleDefs= */ true); 297 298 299 // Delete dead machine instructions regardless of optimization level. 300 PM.add(createDeadMachineInstructionElimPass()); 301 printAndVerify(PM, "After codegen DCE pass", 302 /* allowDoubleDefs= */ true); 303 304 if (OptLevel != CodeGenOpt::None) { 305 PM.add(createOptimizeExtsPass()); 306 PM.add(createOptimizePHIsPass()); 307 if (!DisableMachineLICM) 308 PM.add(createMachineLICMPass()); 309 if (!DisableMachineSink) 310 PM.add(createMachineSinkingPass()); 311 printAndVerify(PM, "After MachineLICM and MachineSinking", 312 /* allowDoubleDefs= */ true); 313 } 314 315 // Pre-ra tail duplication. 316 if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) { 317 PM.add(createTailDuplicatePass(true)); 318 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate", 319 /* allowDoubleDefs= */ true); 320 } 321 322 // Run pre-ra passes. 323 if (addPreRegAlloc(PM, OptLevel)) 324 printAndVerify(PM, "After PreRegAlloc passes", 325 /* allowDoubleDefs= */ true); 326 327 // Perform register allocation. 328 PM.add(createRegisterAllocator()); 329 printAndVerify(PM, "After Register Allocation"); 330 331 // Perform stack slot coloring. 332 if (OptLevel != CodeGenOpt::None && !DisableSSC) { 333 // FIXME: Re-enable coloring with register when it's capable of adding 334 // kill markers. 335 PM.add(createStackSlotColoringPass(false)); 336 printAndVerify(PM, "After StackSlotColoring"); 337 } 338 339 // Run post-ra passes. 340 if (addPostRegAlloc(PM, OptLevel)) 341 printAndVerify(PM, "After PostRegAlloc passes"); 342 343 PM.add(createLowerSubregsPass()); 344 printAndVerify(PM, "After LowerSubregs"); 345 346 // Insert prolog/epilog code. Eliminate abstract frame index references... 347 PM.add(createPrologEpilogCodeInserter()); 348 printAndVerify(PM, "After PrologEpilogCodeInserter"); 349 350 // Run pre-sched2 passes. 351 if (addPreSched2(PM, OptLevel)) 352 printAndVerify(PM, "After PreSched2 passes"); 353 354 // Second pass scheduler. 355 if (OptLevel != CodeGenOpt::None && !DisablePostRA) { 356 PM.add(createPostRAScheduler(OptLevel)); 357 printAndVerify(PM, "After PostRAScheduler"); 358 } 359 360 // Branch folding must be run after regalloc and prolog/epilog insertion. 361 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) { 362 PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); 363 printAndVerify(PM, "After BranchFolding"); 364 } 365 366 // Tail duplication. 367 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) { 368 PM.add(createTailDuplicatePass(false)); 369 printAndVerify(PM, "After TailDuplicate"); 370 } 371 372 PM.add(createGCMachineCodeAnalysisPass()); 373 374 if (PrintGCInfo) 375 PM.add(createGCInfoPrinter(dbgs())); 376 377 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) { 378 PM.add(createCodePlacementOptPass()); 379 printAndVerify(PM, "After CodePlacementOpt"); 380 } 381 382 if (addPreEmitPass(PM, OptLevel)) 383 printAndVerify(PM, "After PreEmit passes"); 384 385 return false; 386} 387