LLVMTargetMachine.cpp revision f73ff3aaf64627fb71753032904ee3ab2a7add28 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/Analysis/LoopPass.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/Collector.h"
21#include "llvm/Target/TargetOptions.h"
22#include "llvm/Target/TargetAsmInfo.h"
23#include "llvm/Transforms/Scalar.h"
24#include "llvm/Support/CommandLine.h"
25using namespace llvm;
26
27static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
28    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
29static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
30    cl::desc("Print LLVM IR input to isel pass"));
31static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
32    cl::desc("Dump emitter generated instructions as assembly"));
33static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
34    cl::desc("Dump garbage collector data"));
35
36// Hidden options to help debugging
37static cl::opt<bool>
38EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
39              cl::desc("Perform sinking on machine code"));
40static cl::opt<bool>
41AlignLoops("align-loops", cl::init(true), cl::Hidden,
42           cl::desc("Align loop headers"));
43static cl::opt<bool>
44PerformLICM("machine-licm",
45            cl::init(false), cl::Hidden,
46            cl::desc("Perform loop-invariant code motion on machine code"));
47
48// When this works it will be on by default.
49static cl::opt<bool>
50DisablePostRAScheduler("disable-post-RA-scheduler",
51                       cl::desc("Disable scheduling after register allocation"),
52                       cl::init(true));
53
54FileModel::Model
55LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
56                                       std::ostream &Out,
57                                       CodeGenFileType FileType,
58                                       bool Fast) {
59  // Standard LLVM-Level Passes.
60
61  // Run loop strength reduction before anything else.
62  if (!Fast) {
63    PM.add(createLoopStrengthReducePass(getTargetLowering()));
64    if (PrintLSR)
65      PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
66  }
67
68  PM.add(createGCLoweringPass());
69
70  if (!getTargetAsmInfo()->doesSupportExceptionHandling())
71    PM.add(createLowerInvokePass(getTargetLowering()));
72
73  // Make sure that no unreachable blocks are instruction selected.
74  PM.add(createUnreachableBlockEliminationPass());
75
76  if (!Fast)
77    PM.add(createCodeGenPreparePass(getTargetLowering()));
78
79  if (PrintISelInput)
80    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
81                                 &cerr));
82
83  // Ask the target for an isel.
84  if (addInstSelector(PM, Fast))
85    return FileModel::Error;
86
87  // Print the instruction selected machine code...
88  if (PrintMachineCode)
89    PM.add(createMachineFunctionPrinterPass(cerr));
90
91  if (PerformLICM)
92    PM.add(createMachineLICMPass());
93
94  if (EnableSinking)
95    PM.add(createMachineSinkingPass());
96
97  // Run pre-ra passes.
98  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
99    PM.add(createMachineFunctionPrinterPass(cerr));
100
101  // Perform register allocation to convert to a concrete x86 representation
102  PM.add(createRegisterAllocator());
103
104  if (PrintMachineCode)
105    PM.add(createMachineFunctionPrinterPass(cerr));
106
107  PM.add(createLowerSubregsPass());
108
109  if (PrintMachineCode)  // Print the subreg lowered code
110    PM.add(createMachineFunctionPrinterPass(cerr));
111
112  // Run post-ra passes.
113  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
114    PM.add(createMachineFunctionPrinterPass(cerr));
115
116  // Insert prolog/epilog code.  Eliminate abstract frame index references...
117  PM.add(createPrologEpilogCodeInserter());
118
119  // Second pass scheduler.
120  if (!Fast && !DisablePostRAScheduler)
121    PM.add(createPostRAScheduler());
122
123  // Branch folding must be run after regalloc and prolog/epilog insertion.
124  if (!Fast)
125    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
126
127  PM.add(createGCMachineCodeAnalysisPass());
128  if (PrintMachineCode)
129    PM.add(createMachineFunctionPrinterPass(cerr));
130
131  if (PrintGCInfo)
132    PM.add(createCollectorMetadataPrinter(*cerr));
133
134  // Fold redundant debug labels.
135  PM.add(createDebugLabelFoldingPass());
136
137  if (PrintMachineCode)  // Print the register-allocated code
138    PM.add(createMachineFunctionPrinterPass(cerr));
139
140  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
141    PM.add(createMachineFunctionPrinterPass(cerr));
142
143  if (AlignLoops && !Fast && !OptimizeForSize)
144    PM.add(createLoopAlignerPass());
145
146  switch (FileType) {
147  default:
148    break;
149  case TargetMachine::AssemblyFile:
150    if (addAssemblyEmitter(PM, Fast, Out))
151      return FileModel::Error;
152    return FileModel::AsmFile;
153  case TargetMachine::ObjectFile:
154    if (getMachOWriterInfo())
155      return FileModel::MachOFile;
156    else if (getELFWriterInfo())
157      return FileModel::ElfFile;
158  }
159
160  return FileModel::Error;
161}
162
163/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
164/// be split up (e.g., to add an object writer pass), this method can be used to
165/// finish up adding passes to emit the file, if necessary.
166bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
167                                                  MachineCodeEmitter *MCE,
168                                                  bool Fast) {
169  if (MCE)
170    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
171
172  PM.add(createCollectorMetadataDeleter());
173
174  // Delete machine code for this function
175  PM.add(createMachineCodeDeleter());
176
177  return false; // success!
178}
179
180/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
181/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
182/// actually outputting the machine code and resolving things like the address
183/// of functions.  This method should returns true if machine code emission is
184/// not supported.
185///
186bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
187                                                   MachineCodeEmitter &MCE,
188                                                   bool Fast) {
189  // Standard LLVM-Level Passes.
190
191  // Run loop strength reduction before anything else.
192  if (!Fast) {
193    PM.add(createLoopStrengthReducePass(getTargetLowering()));
194    if (PrintLSR)
195      PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
196  }
197
198  PM.add(createGCLoweringPass());
199
200  if (!getTargetAsmInfo()->doesSupportExceptionHandling())
201    PM.add(createLowerInvokePass(getTargetLowering()));
202
203  // Make sure that no unreachable blocks are instruction selected.
204  PM.add(createUnreachableBlockEliminationPass());
205
206  if (!Fast)
207    PM.add(createCodeGenPreparePass(getTargetLowering()));
208
209  if (PrintISelInput)
210    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
211                                 &cerr));
212
213  // Ask the target for an isel.
214  if (addInstSelector(PM, Fast))
215    return true;
216
217  // Print the instruction selected machine code...
218  if (PrintMachineCode)
219    PM.add(createMachineFunctionPrinterPass(cerr));
220
221  if (PerformLICM)
222    PM.add(createMachineLICMPass());
223
224  if (EnableSinking)
225    PM.add(createMachineSinkingPass());
226
227  // Run pre-ra passes.
228  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
229    PM.add(createMachineFunctionPrinterPass(cerr));
230
231  // Perform register allocation to convert to a concrete x86 representation
232  PM.add(createRegisterAllocator());
233
234  if (PrintMachineCode)
235    PM.add(createMachineFunctionPrinterPass(cerr));
236
237  PM.add(createLowerSubregsPass());
238
239  if (PrintMachineCode)  // Print the subreg lowered code
240    PM.add(createMachineFunctionPrinterPass(cerr));
241
242  // Run post-ra passes.
243  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
244    PM.add(createMachineFunctionPrinterPass(cerr));
245
246  // Insert prolog/epilog code.  Eliminate abstract frame index references...
247  PM.add(createPrologEpilogCodeInserter());
248
249  if (PrintMachineCode)  // Print the register-allocated code
250    PM.add(createMachineFunctionPrinterPass(cerr));
251
252  // Second pass scheduler.
253  if (!Fast)
254    PM.add(createPostRAScheduler());
255
256  // Branch folding must be run after regalloc and prolog/epilog insertion.
257  if (!Fast)
258    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
259
260  PM.add(createGCMachineCodeAnalysisPass());
261  if (PrintMachineCode)
262    PM.add(createMachineFunctionPrinterPass(cerr));
263
264  if (PrintGCInfo)
265    PM.add(createCollectorMetadataPrinter(*cerr));
266
267  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
268    PM.add(createMachineFunctionPrinterPass(cerr));
269
270  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
271
272  PM.add(createCollectorMetadataDeleter());
273
274  // Delete machine code for this function
275  PM.add(createMachineCodeDeleter());
276
277  return false; // success!
278}
279