LiveVariables.cpp revision 7a3abdc63c0cc4e5d5411c3add0e909c6ac49e79
1//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveVariable analysis pass. For each machine 11// instruction in the function, this pass calculates the set of registers that 12// are immediately dead after the instruction (i.e., the instruction calculates 13// the value, but it is never used) and the set of registers that are used by 14// the instruction, but are never used after the instruction (i.e., they are 15// killed). 16// 17// This class computes live variables using are sparse implementation based on 18// the machine code SSA form. This class computes live variable information for 19// each virtual and _register allocatable_ physical register in a function. It 20// uses the dominance properties of SSA form to efficiently compute live 21// variables for virtual registers, and assumes that physical registers are only 22// live within a single basic block (allowing it to do a single local analysis 23// to resolve physical register lifetimes in each basic block). If a physical 24// register is not register allocatable, it is not tracked. This is useful for 25// things like the stack pointer and condition codes. 26// 27//===----------------------------------------------------------------------===// 28 29#include "llvm/CodeGen/LiveVariables.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/Target/MRegisterInfo.h" 32#include "llvm/Target/TargetInstrInfo.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/ADT/DepthFirstIterator.h" 35#include "llvm/ADT/STLExtras.h" 36#include "llvm/Config/alloca.h" 37#include <algorithm> 38#include <iostream> 39using namespace llvm; 40 41static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis"); 42 43void LiveVariables::VarInfo::dump() const { 44 std::cerr << "Register Defined by: "; 45 if (DefInst) 46 std::cerr << *DefInst; 47 else 48 std::cerr << "<null>\n"; 49 std::cerr << " Alive in blocks: "; 50 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i) 51 if (AliveBlocks[i]) std::cerr << i << ", "; 52 std::cerr << "\n Killed by:"; 53 if (Kills.empty()) 54 std::cerr << " No instructions.\n"; 55 else { 56 for (unsigned i = 0, e = Kills.size(); i != e; ++i) 57 std::cerr << "\n #" << i << ": " << *Kills[i]; 58 std::cerr << "\n"; 59 } 60} 61 62LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { 63 assert(MRegisterInfo::isVirtualRegister(RegIdx) && 64 "getVarInfo: not a virtual register!"); 65 RegIdx -= MRegisterInfo::FirstVirtualRegister; 66 if (RegIdx >= VirtRegInfo.size()) { 67 if (RegIdx >= 2*VirtRegInfo.size()) 68 VirtRegInfo.resize(RegIdx*2); 69 else 70 VirtRegInfo.resize(2*VirtRegInfo.size()); 71 } 72 return VirtRegInfo[RegIdx]; 73} 74 75bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const { 76 std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I = 77 RegistersKilled.find(MI); 78 if (I == RegistersKilled.end()) return false; 79 80 // Do a binary search, as these lists can grow pretty big, particularly for 81 // call instructions on targets with lots of call-clobbered registers. 82 return std::binary_search(I->second.begin(), I->second.end(), Reg); 83} 84 85bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const { 86 std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I = 87 RegistersDead.find(MI); 88 if (I == RegistersDead.end()) return false; 89 90 // Do a binary search, as these lists can grow pretty big, particularly for 91 // call instructions on targets with lots of call-clobbered registers. 92 return std::binary_search(I->second.begin(), I->second.end(), Reg); 93} 94 95 96void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, 97 MachineBasicBlock *MBB) { 98 unsigned BBNum = MBB->getNumber(); 99 100 // Check to see if this basic block is one of the killing blocks. If so, 101 // remove it... 102 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 103 if (VRInfo.Kills[i]->getParent() == MBB) { 104 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry 105 break; 106 } 107 108 if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion 109 110 if (VRInfo.AliveBlocks.size() <= BBNum) 111 VRInfo.AliveBlocks.resize(BBNum+1); // Make space... 112 113 if (VRInfo.AliveBlocks[BBNum]) 114 return; // We already know the block is live 115 116 // Mark the variable known alive in this bb 117 VRInfo.AliveBlocks[BBNum] = true; 118 119 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), 120 E = MBB->pred_end(); PI != E; ++PI) 121 MarkVirtRegAliveInBlock(VRInfo, *PI); 122} 123 124void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, 125 MachineInstr *MI) { 126 assert(VRInfo.DefInst && "Register use before def!"); 127 128 // Check to see if this basic block is already a kill block... 129 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { 130 // Yes, this register is killed in this basic block already. Increase the 131 // live range by updating the kill instruction. 132 VRInfo.Kills.back() = MI; 133 return; 134 } 135 136#ifndef NDEBUG 137 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 138 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!"); 139#endif 140 141 assert(MBB != VRInfo.DefInst->getParent() && 142 "Should have kill for defblock!"); 143 144 // Add a new kill entry for this basic block. 145 VRInfo.Kills.push_back(MI); 146 147 // Update all dominating blocks to mark them known live. 148 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), 149 E = MBB->pred_end(); PI != E; ++PI) 150 MarkVirtRegAliveInBlock(VRInfo, *PI); 151} 152 153void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { 154 PhysRegInfo[Reg] = MI; 155 PhysRegUsed[Reg] = true; 156 157 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); 158 unsigned Alias = *AliasSet; ++AliasSet) { 159 PhysRegInfo[Alias] = MI; 160 PhysRegUsed[Alias] = true; 161 } 162} 163 164void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { 165 // Does this kill a previous version of this register? 166 if (MachineInstr *LastUse = PhysRegInfo[Reg]) { 167 if (PhysRegUsed[Reg]) 168 RegistersKilled[LastUse].push_back(Reg); 169 else 170 RegistersDead[LastUse].push_back(Reg); 171 } 172 PhysRegInfo[Reg] = MI; 173 PhysRegUsed[Reg] = false; 174 175 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); 176 unsigned Alias = *AliasSet; ++AliasSet) { 177 if (MachineInstr *LastUse = PhysRegInfo[Alias]) { 178 if (PhysRegUsed[Alias]) 179 RegistersKilled[LastUse].push_back(Alias); 180 else 181 RegistersDead[LastUse].push_back(Alias); 182 } 183 PhysRegInfo[Alias] = MI; 184 PhysRegUsed[Alias] = false; 185 } 186} 187 188bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { 189 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 190 RegInfo = MF.getTarget().getRegisterInfo(); 191 assert(RegInfo && "Target doesn't have register information?"); 192 193 AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF); 194 195 // PhysRegInfo - Keep track of which instruction was the last use of a 196 // physical register. This is a purely local property, because all physical 197 // register references as presumed dead across basic blocks. 198 // 199 PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) * 200 RegInfo->getNumRegs()); 201 PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs()); 202 std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0); 203 204 /// Get some space for a respectable number of registers... 205 VirtRegInfo.resize(64); 206 207 // Mark live-in registers as live-in. 208 for (MachineFunction::livein_iterator I = MF.livein_begin(), 209 E = MF.livein_end(); I != E; ++I) { 210 assert(MRegisterInfo::isPhysicalRegister(I->first) && 211 "Cannot have a live-in virtual register!"); 212 HandlePhysRegDef(I->first, 0); 213 } 214 215 // Calculate live variable information in depth first order on the CFG of the 216 // function. This guarantees that we will see the definition of a virtual 217 // register before its uses due to dominance properties of SSA (except for PHI 218 // nodes, which are treated as a special case). 219 // 220 MachineBasicBlock *Entry = MF.begin(); 221 std::set<MachineBasicBlock*> Visited; 222 for (df_ext_iterator<MachineBasicBlock*> DFI = df_ext_begin(Entry, Visited), 223 E = df_ext_end(Entry, Visited); DFI != E; ++DFI) { 224 MachineBasicBlock *MBB = *DFI; 225 unsigned BBNum = MBB->getNumber(); 226 227 // Loop over all of the instructions, processing them. 228 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 229 I != E; ++I) { 230 MachineInstr *MI = I; 231 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode()); 232 233 // Process all of the operands of the instruction... 234 unsigned NumOperandsToProcess = MI->getNumOperands(); 235 236 // Unless it is a PHI node. In this case, ONLY process the DEF, not any 237 // of the uses. They will be handled in other basic blocks. 238 if (MI->getOpcode() == TargetInstrInfo::PHI) 239 NumOperandsToProcess = 1; 240 241 // Loop over implicit uses, using them. 242 if (MID.ImplicitUses) { 243 for (const unsigned *ImplicitUses = MID.ImplicitUses; 244 *ImplicitUses; ++ImplicitUses) 245 HandlePhysRegUse(*ImplicitUses, MI); 246 } 247 248 // Process all explicit uses... 249 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 250 MachineOperand &MO = MI->getOperand(i); 251 if (MO.isUse() && MO.isRegister() && MO.getReg()) { 252 if (MRegisterInfo::isVirtualRegister(MO.getReg())){ 253 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI); 254 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 255 AllocatablePhysicalRegisters[MO.getReg()]) { 256 HandlePhysRegUse(MO.getReg(), MI); 257 } 258 } 259 } 260 261 // Loop over implicit defs, defining them. 262 if (MID.ImplicitDefs) { 263 for (const unsigned *ImplicitDefs = MID.ImplicitDefs; 264 *ImplicitDefs; ++ImplicitDefs) 265 HandlePhysRegDef(*ImplicitDefs, MI); 266 } 267 268 // Process all explicit defs... 269 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 270 MachineOperand &MO = MI->getOperand(i); 271 if (MO.isDef() && MO.isRegister() && MO.getReg()) { 272 if (MRegisterInfo::isVirtualRegister(MO.getReg())) { 273 VarInfo &VRInfo = getVarInfo(MO.getReg()); 274 275 assert(VRInfo.DefInst == 0 && "Variable multiply defined!"); 276 VRInfo.DefInst = MI; 277 // Defaults to dead 278 VRInfo.Kills.push_back(MI); 279 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 280 AllocatablePhysicalRegisters[MO.getReg()]) { 281 HandlePhysRegDef(MO.getReg(), MI); 282 } 283 } 284 } 285 } 286 287 // Handle any virtual assignments from PHI nodes which might be at the 288 // bottom of this basic block. We check all of our successor blocks to see 289 // if they have PHI nodes, and if so, we simulate an assignment at the end 290 // of the current block. 291 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 292 E = MBB->succ_end(); SI != E; ++SI) { 293 MachineBasicBlock *Succ = *SI; 294 295 // PHI nodes are guaranteed to be at the top of the block... 296 for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end(); 297 MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) { 298 for (unsigned i = 1; ; i += 2) { 299 assert(MI->getNumOperands() > i+1 && 300 "Didn't find an entry for our predecessor??"); 301 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) { 302 MachineOperand &MO = MI->getOperand(i); 303 VarInfo &VRInfo = getVarInfo(MO.getReg()); 304 assert(VRInfo.DefInst && "Register use before def (or no def)!"); 305 306 // Only mark it alive only in the block we are representing. 307 MarkVirtRegAliveInBlock(VRInfo, MBB); 308 break; // Found the PHI entry for this block. 309 } 310 } 311 } 312 } 313 314 // Finally, if the last block in the function is a return, make sure to mark 315 // it as using all of the live-out values in the function. 316 if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) { 317 MachineInstr *Ret = &MBB->back(); 318 for (MachineFunction::liveout_iterator I = MF.liveout_begin(), 319 E = MF.liveout_end(); I != E; ++I) { 320 assert(MRegisterInfo::isPhysicalRegister(*I) && 321 "Cannot have a live-in virtual register!"); 322 HandlePhysRegUse(*I, Ret); 323 } 324 } 325 326 // Loop over PhysRegInfo, killing any registers that are available at the 327 // end of the basic block. This also resets the PhysRegInfo map. 328 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) 329 if (PhysRegInfo[i]) 330 HandlePhysRegDef(i, 0); 331 } 332 333 // Convert the information we have gathered into VirtRegInfo and transform it 334 // into a form usable by RegistersKilled. 335 // 336 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i) 337 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) { 338 if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst) 339 RegistersDead[VirtRegInfo[i].Kills[j]].push_back( 340 i + MRegisterInfo::FirstVirtualRegister); 341 342 else 343 RegistersKilled[VirtRegInfo[i].Kills[j]].push_back( 344 i + MRegisterInfo::FirstVirtualRegister); 345 } 346 347 // Walk through the RegistersKilled/Dead sets, and sort the registers killed 348 // or dead. This allows us to use efficient binary search for membership 349 // testing. 350 for (std::map<MachineInstr*, std::vector<unsigned> >::iterator 351 I = RegistersKilled.begin(), E = RegistersKilled.end(); I != E; ++I) 352 std::sort(I->second.begin(), I->second.end()); 353 for (std::map<MachineInstr*, std::vector<unsigned> >::iterator 354 I = RegistersDead.begin(), E = RegistersDead.end(); I != E; ++I) 355 std::sort(I->second.begin(), I->second.end()); 356 357 // Check to make sure there are no unreachable blocks in the MC CFG for the 358 // function. If so, it is due to a bug in the instruction selector or some 359 // other part of the code generator if this happens. 360#ifndef NDEBUG 361 for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i) 362 assert(Visited.count(&*i) != 0 && "unreachable basic block found"); 363#endif 364 365 return false; 366} 367 368/// instructionChanged - When the address of an instruction changes, this 369/// method should be called so that live variables can update its internal 370/// data structures. This removes the records for OldMI, transfering them to 371/// the records for NewMI. 372void LiveVariables::instructionChanged(MachineInstr *OldMI, 373 MachineInstr *NewMI) { 374 // If the instruction defines any virtual registers, update the VarInfo for 375 // the instruction. 376 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { 377 MachineOperand &MO = OldMI->getOperand(i); 378 if (MO.isRegister() && MO.getReg() && 379 MRegisterInfo::isVirtualRegister(MO.getReg())) { 380 unsigned Reg = MO.getReg(); 381 VarInfo &VI = getVarInfo(Reg); 382 if (MO.isDef()) { 383 // Update the defining instruction. 384 if (VI.DefInst == OldMI) 385 VI.DefInst = NewMI; 386 } 387 if (MO.isUse()) { 388 // If this is a kill of the value, update the VI kills list. 389 if (VI.removeKill(OldMI)) 390 VI.Kills.push_back(NewMI); // Yes, there was a kill of it 391 } 392 } 393 } 394 395 // Move the killed information over... 396 killed_iterator I, E; 397 tie(I, E) = killed_range(OldMI); 398 if (I != E) { 399 std::vector<unsigned> &V = RegistersKilled[NewMI]; 400 bool WasEmpty = V.empty(); 401 V.insert(V.end(), I, E); 402 if (!WasEmpty) 403 std::sort(V.begin(), V.end()); // Keep the reg list sorted. 404 RegistersKilled.erase(OldMI); 405 } 406 407 // Move the dead information over... 408 tie(I, E) = dead_range(OldMI); 409 if (I != E) { 410 std::vector<unsigned> &V = RegistersDead[NewMI]; 411 bool WasEmpty = V.empty(); 412 V.insert(V.end(), I, E); 413 if (!WasEmpty) 414 std::sort(V.begin(), V.end()); // Keep the reg list sorted. 415 RegistersDead.erase(OldMI); 416 } 417} 418 419/// removeVirtualRegistersKilled - Remove all killed info for the specified 420/// instruction. 421void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) { 422 std::map<MachineInstr*, std::vector<unsigned> >::iterator I = 423 RegistersKilled.find(MI); 424 if (I == RegistersKilled.end()) return; 425 426 std::vector<unsigned> &Regs = I->second; 427 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 428 if (MRegisterInfo::isVirtualRegister(Regs[i])) { 429 bool removed = getVarInfo(Regs[i]).removeKill(MI); 430 assert(removed && "kill not in register's VarInfo?"); 431 } 432 } 433 RegistersKilled.erase(I); 434} 435 436/// removeVirtualRegistersDead - Remove all of the dead registers for the 437/// specified instruction from the live variable information. 438void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) { 439 std::map<MachineInstr*, std::vector<unsigned> >::iterator I = 440 RegistersDead.find(MI); 441 if (I == RegistersDead.end()) return; 442 443 std::vector<unsigned> &Regs = I->second; 444 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 445 if (MRegisterInfo::isVirtualRegister(Regs[i])) { 446 bool removed = getVarInfo(Regs[i]).removeKill(MI); 447 assert(removed && "kill not in register's VarInfo?"); 448 } 449 } 450 RegistersDead.erase(I); 451} 452 453 454