LiveVariables.cpp revision a018540807775703d630e9c92f9d8013d545599e
1//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveVariable analysis pass. For each machine 11// instruction in the function, this pass calculates the set of registers that 12// are immediately dead after the instruction (i.e., the instruction calculates 13// the value, but it is never used) and the set of registers that are used by 14// the instruction, but are never used after the instruction (i.e., they are 15// killed). 16// 17// This class computes live variables using are sparse implementation based on 18// the machine code SSA form. This class computes live variable information for 19// each virtual and _register allocatable_ physical register in a function. It 20// uses the dominance properties of SSA form to efficiently compute live 21// variables for virtual registers, and assumes that physical registers are only 22// live within a single basic block (allowing it to do a single local analysis 23// to resolve physical register lifetimes in each basic block). If a physical 24// register is not register allocatable, it is not tracked. This is useful for 25// things like the stack pointer and condition codes. 26// 27//===----------------------------------------------------------------------===// 28 29#include "llvm/CodeGen/LiveVariables.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/Target/MRegisterInfo.h" 32#include "llvm/Target/TargetInstrInfo.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/ADT/DepthFirstIterator.h" 35#include "llvm/ADT/SmallPtrSet.h" 36#include "llvm/ADT/STLExtras.h" 37#include "llvm/Config/alloca.h" 38#include <algorithm> 39using namespace llvm; 40 41char LiveVariables::ID = 0; 42static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis"); 43 44void LiveVariables::VarInfo::dump() const { 45 cerr << "Register Defined by: "; 46 if (DefInst) 47 cerr << *DefInst; 48 else 49 cerr << "<null>\n"; 50 cerr << " Alive in blocks: "; 51 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i) 52 if (AliveBlocks[i]) cerr << i << ", "; 53 cerr << " Used in blocks: "; 54 for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i) 55 if (UsedBlocks[i]) cerr << i << ", "; 56 cerr << "\n Killed by:"; 57 if (Kills.empty()) 58 cerr << " No instructions.\n"; 59 else { 60 for (unsigned i = 0, e = Kills.size(); i != e; ++i) 61 cerr << "\n #" << i << ": " << *Kills[i]; 62 cerr << "\n"; 63 } 64} 65 66LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { 67 assert(MRegisterInfo::isVirtualRegister(RegIdx) && 68 "getVarInfo: not a virtual register!"); 69 RegIdx -= MRegisterInfo::FirstVirtualRegister; 70 if (RegIdx >= VirtRegInfo.size()) { 71 if (RegIdx >= 2*VirtRegInfo.size()) 72 VirtRegInfo.resize(RegIdx*2); 73 else 74 VirtRegInfo.resize(2*VirtRegInfo.size()); 75 } 76 VarInfo &VI = VirtRegInfo[RegIdx]; 77 VI.AliveBlocks.resize(MF->getNumBlockIDs()); 78 VI.UsedBlocks.resize(MF->getNumBlockIDs()); 79 return VI; 80} 81 82bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const { 83 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 84 MachineOperand &MO = MI->getOperand(i); 85 if (MO.isRegister() && MO.isKill()) { 86 if ((MO.getReg() == Reg) || 87 (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 88 MRegisterInfo::isPhysicalRegister(Reg) && 89 RegInfo->isSubRegister(MO.getReg(), Reg))) 90 return true; 91 } 92 } 93 return false; 94} 95 96bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const { 97 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 98 MachineOperand &MO = MI->getOperand(i); 99 if (MO.isRegister() && MO.isDead()) { 100 if ((MO.getReg() == Reg) || 101 (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 102 MRegisterInfo::isPhysicalRegister(Reg) && 103 RegInfo->isSubRegister(MO.getReg(), Reg))) 104 return true; 105 } 106 } 107 return false; 108} 109 110bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const { 111 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 112 MachineOperand &MO = MI->getOperand(i); 113 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) 114 return true; 115 } 116 return false; 117} 118 119void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, 120 MachineBasicBlock *MBB, 121 std::vector<MachineBasicBlock*> &WorkList) { 122 unsigned BBNum = MBB->getNumber(); 123 124 // Check to see if this basic block is one of the killing blocks. If so, 125 // remove it... 126 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 127 if (VRInfo.Kills[i]->getParent() == MBB) { 128 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry 129 break; 130 } 131 132 if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion 133 134 if (VRInfo.AliveBlocks[BBNum]) 135 return; // We already know the block is live 136 137 // Mark the variable known alive in this bb 138 VRInfo.AliveBlocks[BBNum] = true; 139 140 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(), 141 E = MBB->pred_rend(); PI != E; ++PI) 142 WorkList.push_back(*PI); 143} 144 145void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, 146 MachineBasicBlock *MBB) { 147 std::vector<MachineBasicBlock*> WorkList; 148 MarkVirtRegAliveInBlock(VRInfo, MBB, WorkList); 149 while (!WorkList.empty()) { 150 MachineBasicBlock *Pred = WorkList.back(); 151 WorkList.pop_back(); 152 MarkVirtRegAliveInBlock(VRInfo, Pred, WorkList); 153 } 154} 155 156 157void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, 158 MachineInstr *MI) { 159 assert(VRInfo.DefInst && "Register use before def!"); 160 161 unsigned BBNum = MBB->getNumber(); 162 163 VRInfo.UsedBlocks[BBNum] = true; 164 VRInfo.NumUses++; 165 166 // Check to see if this basic block is already a kill block... 167 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { 168 // Yes, this register is killed in this basic block already. Increase the 169 // live range by updating the kill instruction. 170 VRInfo.Kills.back() = MI; 171 return; 172 } 173 174#ifndef NDEBUG 175 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 176 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!"); 177#endif 178 179 assert(MBB != VRInfo.DefInst->getParent() && 180 "Should have kill for defblock!"); 181 182 // Add a new kill entry for this basic block. 183 // If this virtual register is already marked as alive in this basic block, 184 // that means it is alive in at least one of the successor block, it's not 185 // a kill. 186 if (!VRInfo.AliveBlocks[BBNum]) 187 VRInfo.Kills.push_back(MI); 188 189 // Update all dominating blocks to mark them known live. 190 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), 191 E = MBB->pred_end(); PI != E; ++PI) 192 MarkVirtRegAliveInBlock(VRInfo, *PI); 193} 194 195bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI, 196 bool AddIfNotFound) { 197 bool Found = false; 198 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 199 MachineOperand &MO = MI->getOperand(i); 200 if (MO.isRegister() && MO.isUse()) { 201 unsigned Reg = MO.getReg(); 202 if (!Reg) 203 continue; 204 if (Reg == IncomingReg) { 205 MO.setIsKill(); 206 Found = true; 207 break; 208 } else if (MRegisterInfo::isPhysicalRegister(Reg) && 209 MRegisterInfo::isPhysicalRegister(IncomingReg) && 210 RegInfo->isSuperRegister(IncomingReg, Reg) && 211 MO.isKill()) 212 // A super-register kill already exists. 213 Found = true; 214 } 215 } 216 217 // If not found, this means an alias of one of the operand is killed. Add a 218 // new implicit operand if required. 219 if (!Found && AddIfNotFound) { 220 MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); 221 return true; 222 } 223 return Found; 224} 225 226bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI, 227 bool AddIfNotFound) { 228 bool Found = false; 229 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 230 MachineOperand &MO = MI->getOperand(i); 231 if (MO.isRegister() && MO.isDef()) { 232 unsigned Reg = MO.getReg(); 233 if (!Reg) 234 continue; 235 if (Reg == IncomingReg) { 236 MO.setIsDead(); 237 Found = true; 238 break; 239 } else if (MRegisterInfo::isPhysicalRegister(Reg) && 240 MRegisterInfo::isPhysicalRegister(IncomingReg) && 241 RegInfo->isSuperRegister(IncomingReg, Reg) && 242 MO.isDead()) 243 // There exists a super-register that's marked dead. 244 return true; 245 } 246 } 247 248 // If not found, this means an alias of one of the operand is dead. Add a 249 // new implicit operand. 250 if (!Found && AddIfNotFound) { 251 MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/, 252 true/*IsDead*/); 253 return true; 254 } 255 return Found; 256} 257 258void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { 259 // Turn previous partial def's into read/mod/write. 260 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) { 261 MachineInstr *Def = PhysRegPartDef[Reg][i]; 262 // First one is just a def. This means the use is reading some undef bits. 263 if (i != 0) 264 Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); 265 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/); 266 } 267 PhysRegPartDef[Reg].clear(); 268 269 // There was an earlier def of a super-register. Add implicit def to that MI. 270 // A: EAX = ... 271 // B: = AX 272 // Add implicit def to A. 273 if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] && 274 !PhysRegUsed[Reg]) { 275 MachineInstr *Def = PhysRegInfo[Reg]; 276 if (!Def->findRegisterDefOperand(Reg)) 277 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/); 278 } 279 280 // There is a now a proper use, forget about the last partial use. 281 PhysRegPartUse[Reg] = NULL; 282 PhysRegInfo[Reg] = MI; 283 PhysRegUsed[Reg] = true; 284 285 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 286 unsigned SubReg = *SubRegs; ++SubRegs) { 287 PhysRegInfo[SubReg] = MI; 288 PhysRegUsed[SubReg] = true; 289 } 290 291 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); 292 unsigned SuperReg = *SuperRegs; ++SuperRegs) { 293 // Remember the partial use of this superreg if it was previously defined. 294 bool HasPrevDef = PhysRegInfo[SuperReg] != NULL; 295 if (!HasPrevDef) { 296 for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg); 297 unsigned SSReg = *SSRegs; ++SSRegs) { 298 if (PhysRegInfo[SSReg] != NULL) { 299 HasPrevDef = true; 300 break; 301 } 302 } 303 } 304 if (HasPrevDef) { 305 PhysRegInfo[SuperReg] = MI; 306 PhysRegPartUse[SuperReg] = MI; 307 } 308 } 309} 310 311bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI, 312 SmallSet<unsigned, 4> &SubKills) { 313 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); 314 unsigned SubReg = *SubRegs; ++SubRegs) { 315 MachineInstr *LastRef = PhysRegInfo[SubReg]; 316 if (LastRef != RefMI || 317 !HandlePhysRegKill(SubReg, RefMI, SubKills)) 318 SubKills.insert(SubReg); 319 } 320 321 if (*RegInfo->getImmediateSubRegisters(Reg) == 0) { 322 // No sub-registers, just check if reg is killed by RefMI. 323 if (PhysRegInfo[Reg] == RefMI) 324 return true; 325 } else if (SubKills.empty()) 326 // None of the sub-registers are killed elsewhere... 327 return true; 328 return false; 329} 330 331void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI, 332 SmallSet<unsigned, 4> &SubKills) { 333 if (SubKills.count(Reg) == 0) 334 addRegisterKilled(Reg, MI, true); 335 else { 336 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); 337 unsigned SubReg = *SubRegs; ++SubRegs) 338 addRegisterKills(SubReg, MI, SubKills); 339 } 340} 341 342bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) { 343 SmallSet<unsigned, 4> SubKills; 344 if (HandlePhysRegKill(Reg, RefMI, SubKills)) { 345 addRegisterKilled(Reg, RefMI, true); 346 return true; 347 } else { 348 // Some sub-registers are killed by another MI. 349 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); 350 unsigned SubReg = *SubRegs; ++SubRegs) 351 addRegisterKills(SubReg, RefMI, SubKills); 352 return false; 353 } 354} 355 356void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { 357 // Does this kill a previous version of this register? 358 if (MachineInstr *LastRef = PhysRegInfo[Reg]) { 359 if (PhysRegUsed[Reg]) { 360 if (!HandlePhysRegKill(Reg, LastRef)) { 361 if (PhysRegPartUse[Reg]) 362 addRegisterKilled(Reg, PhysRegPartUse[Reg], true); 363 } 364 } else if (PhysRegPartUse[Reg]) 365 // Add implicit use / kill to last partial use. 366 addRegisterKilled(Reg, PhysRegPartUse[Reg], true); 367 else if (LastRef != MI) 368 // Defined, but not used. However, watch out for cases where a super-reg 369 // is also defined on the same MI. 370 addRegisterDead(Reg, LastRef); 371 } 372 373 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 374 unsigned SubReg = *SubRegs; ++SubRegs) { 375 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) { 376 if (PhysRegUsed[SubReg]) { 377 if (!HandlePhysRegKill(SubReg, LastRef)) { 378 if (PhysRegPartUse[SubReg]) 379 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true); 380 } 381 } else if (PhysRegPartUse[SubReg]) 382 // Add implicit use / kill to last use of a sub-register. 383 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true); 384 else if (LastRef != MI) 385 // This must be a def of the subreg on the same MI. 386 addRegisterDead(SubReg, LastRef); 387 } 388 } 389 390 if (MI) { 391 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); 392 unsigned SuperReg = *SuperRegs; ++SuperRegs) { 393 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) { 394 // The larger register is previously defined. Now a smaller part is 395 // being re-defined. Treat it as read/mod/write. 396 // EAX = 397 // AX = EAX<imp-use,kill>, EAX<imp-def> 398 MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); 399 MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/); 400 PhysRegInfo[SuperReg] = MI; 401 PhysRegUsed[SuperReg] = false; 402 PhysRegPartUse[SuperReg] = NULL; 403 } else { 404 // Remember this partial def. 405 PhysRegPartDef[SuperReg].push_back(MI); 406 } 407 } 408 409 PhysRegInfo[Reg] = MI; 410 PhysRegUsed[Reg] = false; 411 PhysRegPartDef[Reg].clear(); 412 PhysRegPartUse[Reg] = NULL; 413 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 414 unsigned SubReg = *SubRegs; ++SubRegs) { 415 PhysRegInfo[SubReg] = MI; 416 PhysRegUsed[SubReg] = false; 417 PhysRegPartDef[SubReg].clear(); 418 PhysRegPartUse[SubReg] = NULL; 419 } 420 } 421} 422 423bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { 424 MF = &mf; 425 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 426 RegInfo = MF->getTarget().getRegisterInfo(); 427 assert(RegInfo && "Target doesn't have register information?"); 428 429 ReservedRegisters = RegInfo->getReservedRegs(mf); 430 431 unsigned NumRegs = RegInfo->getNumRegs(); 432 PhysRegInfo = new MachineInstr*[NumRegs]; 433 PhysRegUsed = new bool[NumRegs]; 434 PhysRegPartUse = new MachineInstr*[NumRegs]; 435 PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs]; 436 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()]; 437 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0); 438 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false); 439 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0); 440 441 /// Get some space for a respectable number of registers... 442 VirtRegInfo.resize(64); 443 444 analyzePHINodes(mf); 445 446 // Calculate live variable information in depth first order on the CFG of the 447 // function. This guarantees that we will see the definition of a virtual 448 // register before its uses due to dominance properties of SSA (except for PHI 449 // nodes, which are treated as a special case). 450 // 451 MachineBasicBlock *Entry = MF->begin(); 452 SmallPtrSet<MachineBasicBlock*,16> Visited; 453 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> > 454 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); 455 DFI != E; ++DFI) { 456 MachineBasicBlock *MBB = *DFI; 457 458 // Mark live-in registers as live-in. 459 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(), 460 EE = MBB->livein_end(); II != EE; ++II) { 461 assert(MRegisterInfo::isPhysicalRegister(*II) && 462 "Cannot have a live-in virtual register!"); 463 HandlePhysRegDef(*II, 0); 464 } 465 466 // Loop over all of the instructions, processing them. 467 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 468 I != E; ++I) { 469 MachineInstr *MI = I; 470 471 // Process all of the operands of the instruction... 472 unsigned NumOperandsToProcess = MI->getNumOperands(); 473 474 // Unless it is a PHI node. In this case, ONLY process the DEF, not any 475 // of the uses. They will be handled in other basic blocks. 476 if (MI->getOpcode() == TargetInstrInfo::PHI) 477 NumOperandsToProcess = 1; 478 479 // Process all uses... 480 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 481 MachineOperand &MO = MI->getOperand(i); 482 if (MO.isRegister() && MO.isUse() && MO.getReg()) { 483 if (MRegisterInfo::isVirtualRegister(MO.getReg())){ 484 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI); 485 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 486 !ReservedRegisters[MO.getReg()]) { 487 HandlePhysRegUse(MO.getReg(), MI); 488 } 489 } 490 } 491 492 // Process all defs... 493 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 494 MachineOperand &MO = MI->getOperand(i); 495 if (MO.isRegister() && MO.isDef() && MO.getReg()) { 496 if (MRegisterInfo::isVirtualRegister(MO.getReg())) { 497 VarInfo &VRInfo = getVarInfo(MO.getReg()); 498 499 assert(VRInfo.DefInst == 0 && "Variable multiply defined!"); 500 VRInfo.DefInst = MI; 501 // Defaults to dead 502 VRInfo.Kills.push_back(MI); 503 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 504 !ReservedRegisters[MO.getReg()]) { 505 HandlePhysRegDef(MO.getReg(), MI); 506 } 507 } 508 } 509 } 510 511 // Handle any virtual assignments from PHI nodes which might be at the 512 // bottom of this basic block. We check all of our successor blocks to see 513 // if they have PHI nodes, and if so, we simulate an assignment at the end 514 // of the current block. 515 if (!PHIVarInfo[MBB->getNumber()].empty()) { 516 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()]; 517 518 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(), 519 E = VarInfoVec.end(); I != E; ++I) { 520 VarInfo& VRInfo = getVarInfo(*I); 521 assert(VRInfo.DefInst && "Register use before def (or no def)!"); 522 523 // Only mark it alive only in the block we are representing. 524 MarkVirtRegAliveInBlock(VRInfo, MBB); 525 } 526 } 527 528 // Finally, if the last instruction in the block is a return, make sure to mark 529 // it as using all of the live-out values in the function. 530 if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) { 531 MachineInstr *Ret = &MBB->back(); 532 for (MachineFunction::liveout_iterator I = MF->liveout_begin(), 533 E = MF->liveout_end(); I != E; ++I) { 534 assert(MRegisterInfo::isPhysicalRegister(*I) && 535 "Cannot have a live-in virtual register!"); 536 HandlePhysRegUse(*I, Ret); 537 // Add live-out registers as implicit uses. 538 if (Ret->findRegisterUseOperandIdx(*I) == -1) 539 Ret->addRegOperand(*I, false, true); 540 } 541 } 542 543 // Loop over PhysRegInfo, killing any registers that are available at the 544 // end of the basic block. This also resets the PhysRegInfo map. 545 for (unsigned i = 0; i != NumRegs; ++i) 546 if (PhysRegInfo[i]) 547 HandlePhysRegDef(i, 0); 548 549 // Clear some states between BB's. These are purely local information. 550 for (unsigned i = 0; i != NumRegs; ++i) 551 PhysRegPartDef[i].clear(); 552 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0); 553 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false); 554 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0); 555 } 556 557 // Convert and transfer the dead / killed information we have gathered into 558 // VirtRegInfo onto MI's. 559 // 560 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) 561 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) { 562 if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst) 563 addRegisterDead(i + MRegisterInfo::FirstVirtualRegister, 564 VirtRegInfo[i].Kills[j]); 565 else 566 addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister, 567 VirtRegInfo[i].Kills[j]); 568 } 569 570 // Check to make sure there are no unreachable blocks in the MC CFG for the 571 // function. If so, it is due to a bug in the instruction selector or some 572 // other part of the code generator if this happens. 573#ifndef NDEBUG 574 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i) 575 assert(Visited.count(&*i) != 0 && "unreachable basic block found"); 576#endif 577 578 delete[] PhysRegInfo; 579 delete[] PhysRegUsed; 580 delete[] PhysRegPartUse; 581 delete[] PhysRegPartDef; 582 delete[] PHIVarInfo; 583 584 return false; 585} 586 587/// instructionChanged - When the address of an instruction changes, this 588/// method should be called so that live variables can update its internal 589/// data structures. This removes the records for OldMI, transfering them to 590/// the records for NewMI. 591void LiveVariables::instructionChanged(MachineInstr *OldMI, 592 MachineInstr *NewMI) { 593 // If the instruction defines any virtual registers, update the VarInfo, 594 // kill and dead information for the instruction. 595 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { 596 MachineOperand &MO = OldMI->getOperand(i); 597 if (MO.isRegister() && MO.getReg() && 598 MRegisterInfo::isVirtualRegister(MO.getReg())) { 599 unsigned Reg = MO.getReg(); 600 VarInfo &VI = getVarInfo(Reg); 601 if (MO.isDef()) { 602 if (MO.isDead()) { 603 MO.unsetIsDead(); 604 addVirtualRegisterDead(Reg, NewMI); 605 } 606 // Update the defining instruction. 607 if (VI.DefInst == OldMI) 608 VI.DefInst = NewMI; 609 } 610 if (MO.isKill()) { 611 MO.unsetIsKill(); 612 addVirtualRegisterKilled(Reg, NewMI); 613 } 614 // If this is a kill of the value, update the VI kills list. 615 if (VI.removeKill(OldMI)) 616 VI.Kills.push_back(NewMI); // Yes, there was a kill of it 617 } 618 } 619} 620 621/// removeVirtualRegistersKilled - Remove all killed info for the specified 622/// instruction. 623void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) { 624 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 625 MachineOperand &MO = MI->getOperand(i); 626 if (MO.isRegister() && MO.isKill()) { 627 MO.unsetIsKill(); 628 unsigned Reg = MO.getReg(); 629 if (MRegisterInfo::isVirtualRegister(Reg)) { 630 bool removed = getVarInfo(Reg).removeKill(MI); 631 assert(removed && "kill not in register's VarInfo?"); 632 } 633 } 634 } 635} 636 637/// removeVirtualRegistersDead - Remove all of the dead registers for the 638/// specified instruction from the live variable information. 639void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) { 640 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 641 MachineOperand &MO = MI->getOperand(i); 642 if (MO.isRegister() && MO.isDead()) { 643 MO.unsetIsDead(); 644 unsigned Reg = MO.getReg(); 645 if (MRegisterInfo::isVirtualRegister(Reg)) { 646 bool removed = getVarInfo(Reg).removeKill(MI); 647 assert(removed && "kill not in register's VarInfo?"); 648 } 649 } 650 } 651} 652 653/// analyzePHINodes - Gather information about the PHI nodes in here. In 654/// particular, we want to map the variable information of a virtual 655/// register which is used in a PHI node. We map that to the BB the vreg is 656/// coming from. 657/// 658void LiveVariables::analyzePHINodes(const MachineFunction& Fn) { 659 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end(); 660 I != E; ++I) 661 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 662 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) 663 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 664 PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()]. 665 push_back(BBI->getOperand(i).getReg()); 666} 667