MachineLICM.cpp revision 237dee125997dcaf16e391878465162cc680c0fa
1//===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass performs loop invariant code motion on machine instructions. We 11// attempt to remove as much code from the body of a loop as possible. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "machine-licm" 16#include "llvm/CodeGen/Passes.h" 17#include "llvm/CodeGen/MachineDominators.h" 18#include "llvm/CodeGen/MachineLoopInfo.h" 19#include "llvm/CodeGen/MachineRegisterInfo.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/Target/TargetInstrInfo.h" 22#include "llvm/Target/TargetMachine.h" 23#include "llvm/ADT/SmallVector.h" 24#include "llvm/ADT/Statistic.h" 25#include "llvm/Support/CommandLine.h" 26#include "llvm/Support/Compiler.h" 27#include "llvm/Support/Debug.h" 28 29using namespace llvm; 30 31STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops"); 32 33namespace { 34 class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass { 35 const TargetMachine *TM; 36 const TargetInstrInfo *TII; 37 38 // Various analyses that we use... 39 MachineLoopInfo *LI; // Current MachineLoopInfo 40 MachineDominatorTree *DT; // Machine dominator tree for the cur loop 41 MachineRegisterInfo *RegInfo; // Machine register information 42 43 // State that is updated as we process loops 44 bool Changed; // True if a loop is changed. 45 MachineLoop *CurLoop; // The current loop we are working on. 46 public: 47 static char ID; // Pass identification, replacement for typeid 48 MachineLICM() : MachineFunctionPass(&ID) {} 49 50 virtual bool runOnMachineFunction(MachineFunction &MF); 51 52 const char *getPassName() const { return "Machine Instruction LICM"; } 53 54 // FIXME: Loop preheaders? 55 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 56 AU.setPreservesCFG(); 57 AU.addRequired<MachineLoopInfo>(); 58 AU.addRequired<MachineDominatorTree>(); 59 AU.addPreserved<MachineLoopInfo>(); 60 AU.addPreserved<MachineDominatorTree>(); 61 MachineFunctionPass::getAnalysisUsage(AU); 62 } 63 private: 64 /// VisitAllLoops - Visit all of the loops in depth first order and try to 65 /// hoist invariant instructions from them. 66 /// 67 void VisitAllLoops(MachineLoop *L) { 68 const std::vector<MachineLoop*> &SubLoops = L->getSubLoops(); 69 70 for (MachineLoop::iterator 71 I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I) { 72 MachineLoop *ML = *I; 73 74 // Traverse the body of the loop in depth first order on the dominator 75 // tree so that we are guaranteed to see definitions before we see uses. 76 VisitAllLoops(ML); 77 HoistRegion(DT->getNode(ML->getHeader())); 78 } 79 80 HoistRegion(DT->getNode(L->getHeader())); 81 } 82 83 /// IsInSubLoop - A little predicate that returns true if the specified 84 /// basic block is in a subloop of the current one, not the current one 85 /// itself. 86 /// 87 bool IsInSubLoop(MachineBasicBlock *BB) { 88 assert(CurLoop->contains(BB) && "Only valid if BB is IN the loop"); 89 return LI->getLoopFor(BB) != CurLoop; 90 } 91 92 /// IsLoopInvariantInst - Returns true if the instruction is loop 93 /// invariant. I.e., all virtual register operands are defined outside of 94 /// the loop, physical registers aren't accessed (explicitly or implicitly), 95 /// and the instruction is hoistable. 96 /// 97 bool IsLoopInvariantInst(MachineInstr &I); 98 99 /// FindPredecessors - Get all of the predecessors of the loop that are not 100 /// back-edges. 101 /// 102 void FindPredecessors(std::vector<MachineBasicBlock*> &Preds) { 103 const MachineBasicBlock *Header = CurLoop->getHeader(); 104 105 for (MachineBasicBlock::const_pred_iterator 106 I = Header->pred_begin(), E = Header->pred_end(); I != E; ++I) 107 if (!CurLoop->contains(*I)) 108 Preds.push_back(*I); 109 } 110 111 /// MoveInstToEndOfBlock - Moves the machine instruction to the bottom of 112 /// the predecessor basic block (but before the terminator instructions). 113 /// 114 void MoveInstToEndOfBlock(MachineBasicBlock *ToMBB, 115 MachineBasicBlock *FromMBB, 116 MachineInstr *MI); 117 118 /// HoistRegion - Walk the specified region of the CFG (defined by all 119 /// blocks dominated by the specified block, and that are in the current 120 /// loop) in depth first order w.r.t the DominatorTree. This allows us to 121 /// visit definitions before uses, allowing us to hoist a loop body in one 122 /// pass without iteration. 123 /// 124 void HoistRegion(MachineDomTreeNode *N); 125 126 /// Hoist - When an instruction is found to only use loop invariant operands 127 /// that is safe to hoist, this instruction is called to do the dirty work. 128 /// 129 void Hoist(MachineInstr &MI); 130 }; 131} // end anonymous namespace 132 133char MachineLICM::ID = 0; 134static RegisterPass<MachineLICM> 135X("machinelicm", "Machine Loop Invariant Code Motion"); 136 137FunctionPass *llvm::createMachineLICMPass() { return new MachineLICM(); } 138 139/// Hoist expressions out of the specified loop. Note, alias info for inner loop 140/// is not preserved so it is not a good idea to run LICM multiple times on one 141/// loop. 142/// 143bool MachineLICM::runOnMachineFunction(MachineFunction &MF) { 144 DOUT << "******** Machine LICM ********\n"; 145 146 Changed = false; 147 TM = &MF.getTarget(); 148 TII = TM->getInstrInfo(); 149 RegInfo = &MF.getRegInfo(); 150 151 // Get our Loop information... 152 LI = &getAnalysis<MachineLoopInfo>(); 153 DT = &getAnalysis<MachineDominatorTree>(); 154 155 for (MachineLoopInfo::iterator 156 I = LI->begin(), E = LI->end(); I != E; ++I) { 157 CurLoop = *I; 158 159 // Visit all of the instructions of the loop. We want to visit the subloops 160 // first, though, so that we can hoist their invariants first into their 161 // containing loop before we process that loop. 162 VisitAllLoops(CurLoop); 163 } 164 165 return Changed; 166} 167 168/// HoistRegion - Walk the specified region of the CFG (defined by all blocks 169/// dominated by the specified block, and that are in the current loop) in depth 170/// first order w.r.t the DominatorTree. This allows us to visit definitions 171/// before uses, allowing us to hoist a loop body in one pass without iteration. 172/// 173void MachineLICM::HoistRegion(MachineDomTreeNode *N) { 174 assert(N != 0 && "Null dominator tree node?"); 175 MachineBasicBlock *BB = N->getBlock(); 176 177 // If this subregion is not in the top level loop at all, exit. 178 if (!CurLoop->contains(BB)) return; 179 180 // Only need to process the contents of this block if it is not part of a 181 // subloop (which would already have been processed). 182 if (!IsInSubLoop(BB)) 183 for (MachineBasicBlock::iterator 184 I = BB->begin(), E = BB->end(); I != E; ) { 185 MachineInstr &MI = *I++; 186 187 // Try hoisting the instruction out of the loop. We can only do this if 188 // all of the operands of the instruction are loop invariant and if it is 189 // safe to hoist the instruction. 190 Hoist(MI); 191 } 192 193 const std::vector<MachineDomTreeNode*> &Children = N->getChildren(); 194 195 for (unsigned I = 0, E = Children.size(); I != E; ++I) 196 HoistRegion(Children[I]); 197} 198 199/// IsLoopInvariantInst - Returns true if the instruction is loop 200/// invariant. I.e., all virtual register operands are defined outside of the 201/// loop, physical registers aren't accessed explicitly, and there are no side 202/// effects that aren't captured by the operands or other flags. 203/// 204bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) { 205 const TargetInstrDesc &TID = I.getDesc(); 206 207 // Ignore stuff that we obviously can't hoist. 208 if (TID.mayStore() || TID.isCall() || TID.isTerminator() || 209 TID.hasUnmodeledSideEffects()) 210 return false; 211 212 if (TID.mayLoad()) { 213 // Okay, this instruction does a load. As a refinement, we allow the target 214 // to decide whether the loaded value is actually a constant. If so, we can 215 // actually use it as a load. 216 if (!TII->isInvariantLoad(&I)) 217 // FIXME: we should be able to sink loads with no other side effects if 218 // there is nothing that can change memory from here until the end of 219 // block. This is a trivial form of alias analysis. 220 return false; 221 } 222 223 DEBUG({ 224 DOUT << "--- Checking if we can hoist " << I; 225 if (I.getDesc().getImplicitUses()) { 226 DOUT << " * Instruction has implicit uses:\n"; 227 228 const TargetRegisterInfo *TRI = TM->getRegisterInfo(); 229 for (const unsigned *ImpUses = I.getDesc().getImplicitUses(); 230 *ImpUses; ++ImpUses) 231 DOUT << " -> " << TRI->getName(*ImpUses) << "\n"; 232 } 233 234 if (I.getDesc().getImplicitDefs()) { 235 DOUT << " * Instruction has implicit defines:\n"; 236 237 const TargetRegisterInfo *TRI = TM->getRegisterInfo(); 238 for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs(); 239 *ImpDefs; ++ImpDefs) 240 DOUT << " -> " << TRI->getName(*ImpDefs) << "\n"; 241 } 242 }); 243 244 if (I.getDesc().getImplicitDefs() || I.getDesc().getImplicitUses()) { 245 DOUT << "Cannot hoist with implicit defines or uses\n"; 246 return false; 247 } 248 249 // The instruction is loop invariant if all of its operands are. 250 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 251 const MachineOperand &MO = I.getOperand(i); 252 253 if (!MO.isReg()) 254 continue; 255 256 if (MO.isDef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 257 // Don't hoist an instruction that defines a physical register. 258 return false; 259 260 if (!MO.isUse()) 261 continue; 262 263 unsigned Reg = MO.getReg(); 264 if (Reg == 0) continue; 265 266 // Don't hoist instructions that access physical registers. 267 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 268 return false; 269 270 assert(RegInfo->getVRegDef(Reg) && 271 "Machine instr not mapped for this vreg?!"); 272 273 // If the loop contains the definition of an operand, then the instruction 274 // isn't loop invariant. 275 if (CurLoop->contains(RegInfo->getVRegDef(Reg)->getParent())) 276 return false; 277 } 278 279 // If we got this far, the instruction is loop invariant! 280 return true; 281} 282 283/// MoveInstToEndOfBlock - Moves the machine instruction to the bottom of the 284/// predecessor basic block (but before the terminator instructions). 285/// 286void MachineLICM::MoveInstToEndOfBlock(MachineBasicBlock *ToMBB, 287 MachineBasicBlock *FromMBB, 288 MachineInstr *MI) { 289 DEBUG({ 290 DOUT << "Hoisting " << *MI; 291 if (ToMBB->getBasicBlock()) 292 DOUT << " to MachineBasicBlock " 293 << ToMBB->getBasicBlock()->getName(); 294 if (FromMBB->getBasicBlock()) 295 DOUT << " from MachineBasicBlock " 296 << FromMBB->getBasicBlock()->getName(); 297 DOUT << "\n"; 298 }); 299 300 MachineBasicBlock::iterator WhereIter = ToMBB->getFirstTerminator(); 301 MachineBasicBlock::iterator To, From = FromMBB->begin(); 302 303 while (&*From != MI) 304 ++From; 305 306 assert(From != FromMBB->end() && "Didn't find instr in BB!"); 307 308 To = From; 309 ToMBB->splice(WhereIter, FromMBB, From, ++To); 310 ++NumHoisted; 311} 312 313/// Hoist - When an instruction is found to use only loop invariant operands 314/// that are safe to hoist, this instruction is called to do the dirty work. 315/// 316void MachineLICM::Hoist(MachineInstr &MI) { 317 if (!IsLoopInvariantInst(MI)) return; 318 319 std::vector<MachineBasicBlock*> Preds; 320 321 // Non-back-edge predecessors. 322 FindPredecessors(Preds); 323 324 // Either we don't have any predecessors(?!) or we have more than one, which 325 // is forbidden. 326 if (Preds.empty() || Preds.size() != 1) return; 327 328 // Check that the predecessor is qualified to take the hoisted instruction. 329 // I.e., there is only one edge from the predecessor, and it's to the loop 330 // header. 331 MachineBasicBlock *MBB = Preds.front(); 332 333 // FIXME: We are assuming at first that the basic block coming into this loop 334 // has only one successor. This isn't the case in general because we haven't 335 // broken critical edges or added preheaders. 336 if (MBB->succ_size() != 1) return; 337 assert(*MBB->succ_begin() == CurLoop->getHeader() && 338 "The predecessor doesn't feed directly into the loop header!"); 339 340 // Now move the instructions to the predecessor. 341 MoveInstToEndOfBlock(MBB, MI.getParent(), &MI); 342 Changed = true; 343} 344