162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 15f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 1698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman#include "llvm/Target/TargetInstrInfo.h" 176d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen#include "llvm/Target/TargetMachine.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund OlesenMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 21aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen : TRI(&TRI), IsSSA(true), TracksLiveness(true) { 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 2390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints.reserve(256); 244b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen UsedRegUnits.resize(TRI.getNumRegUnits()); 25d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen UsedPhysRegMask.resize(TRI.getNumRegs()); 26d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen 2762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 3733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 3833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 3933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 40e8a3cc68782cc5d43d7b8e24c4afa94448905349Jakob Stoklund Olesen assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 4133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 4233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 4333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 44bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesenconst TargetRegisterClass * 45bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund OlesenMachineRegisterInfo::constrainRegClass(unsigned Reg, 4691fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen const TargetRegisterClass *RC, 4791fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen unsigned MinNumRegs) { 48bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 49bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen if (OldRC == RC) 50bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return RC; 51e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 5291fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 5391fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen return NewRC; 5491fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (NewRC->getNumRegs() < MinNumRegs) 55bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return 0; 5691fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen setRegClass(Reg, NewRC); 57bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return NewRC; 58bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen} 59bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 606d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesenbool 616d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund OlesenMachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 626d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetInstrInfo *TII = TM.getInstrInfo(); 636d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 646d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 656d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 666d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Stop early if there is no room to grow. 676d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (NewRC == OldRC) 686d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 696d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 706d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Accumulate constraints from all uses. 716d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 726d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen ++I) { 736d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *OpRC = 74dee83c90bb7bda57f6d0db2d8f9138f411ecdbbcJakob Stoklund Olesen I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 750488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen if (unsigned SubIdx = I.getOperand().getSubReg()) { 760488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen if (OpRC) 770488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); 780488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen else 790488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); 800488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen } else if (OpRC) 81e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen NewRC = TRI->getCommonSubClass(NewRC, OpRC); 826d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 836d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 846d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen } 856d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen setRegClass(Reg, NewRC); 866d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return true; 876d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen} 886d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 892e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 902e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 912e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 922e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 932e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 942e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 95f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen assert(RegClass->isAllocatable() && 96f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen "Virtual register RegClass must be allocatable."); 97994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen 98994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen // New virtual register number. 99994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 100994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo.grow(Reg); 101994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo[Reg].first = RegClass; 102994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen RegAllocHints.grow(Reg); 103994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen return Reg; 1042e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 1052e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 10619273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 10719273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trickvoid MachineRegisterInfo::clearVirtRegs() { 10819273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#ifndef NDEBUG 10919273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 11019273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 11119273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick "Vreg use list non-empty still?"); 11219273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#endif 11319273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick VRegInfo.clear(); 11419273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick} 11519273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick 116ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen/// Add MO to the linked list of operands for its register. 117ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesenvoid MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 118ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen assert(!MO->isOnRegUseList() && "Already on list"); 119c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 120c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *const Head = HeadRef; 121c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 122c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Head points to the first list element. 123c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Next is NULL on the last list element. 124c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Prev pointers are circular, so Head->Prev == Last. 125c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 126c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Head is NULL for an empty list. 127c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (!Head) { 128c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Prev = MO; 129c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = 0; 130c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = MO; 131c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen return; 132c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } 133c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 134c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 135c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert MO between Last and Head in the circular Prev chain. 136c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Last = Head->Contents.Reg.Prev; 137c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(Last && "Inconsistent use list"); 138c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 139c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Head->Contents.Reg.Prev = MO; 140c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Prev = Last; 141c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 142c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Def operands always precede uses. This allows def_iterator to stop early. 143c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert def operands at the front, and use operands at the back. 144c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (MO->isDef()) { 145c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert def at the front. 146c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = Head; 147c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = MO; 148c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } else { 149c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert use at the end. 150c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = 0; 151c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Last->Contents.Reg.Next = MO; 15281a6995243380668e6f991fa4e11dd0a6e37e030Jakob Stoklund Olesen } 153ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen} 154ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 155ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen/// Remove MO from its use-def list. 156ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesenvoid MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 157ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen assert(MO->isOnRegUseList() && "Operand not on use list"); 158c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 159c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *const Head = HeadRef; 160c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(Head && "List already empty"); 161ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 162ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen // Unlink this from the doubly linked list of operands. 163c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Next = MO->Contents.Reg.Next; 164c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Prev = MO->Contents.Reg.Prev; 165c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 166c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Prev links are circular, next link is NULL instead of looping back to Head. 167c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (MO == Head) 168c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = Next; 169c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen else 170c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Prev->Contents.Reg.Next = Next; 171c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 172c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen (Next ? Next : Head)->Contents.Reg.Prev = Prev; 173c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 174ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen MO->Contents.Reg.Prev = 0; 175ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen MO->Contents.Reg.Next = 0; 176ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen} 177ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 178bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// Move NumOps operands from Src to Dst, updating use-def lists as needed. 179bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// 180bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// The Dst range is assumed to be uninitialized memory. (Or it may contain 181bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// operands that won't be destroyed, which is OK because the MO destructor is 182bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// trivial anyway). 183bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// 184bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// The Src and Dst ranges may overlap. 185bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesenvoid MachineRegisterInfo::moveOperands(MachineOperand *Dst, 186bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Src, 187bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen unsigned NumOps) { 188bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Src != Dst && NumOps && "Noop moveOperands"); 189bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 190bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Copy backwards if Dst is within the Src range. 191bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen int Stride = 1; 192bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Dst >= Src && Dst < Src + NumOps) { 193bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Stride = -1; 194bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Dst += NumOps - 1; 195bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Src += NumOps - 1; 196bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } 197bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 198bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Copy one operand at a time. 199bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen do { 200bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen new (Dst) MachineOperand(*Src); 201bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 202bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Dst takes Src's place in the use-def chain. 203bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Src->isReg()) { 204bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); 205bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Prev = Src->Contents.Reg.Prev; 206bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Next = Src->Contents.Reg.Next; 207bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Head && "List empty, but operand is chained"); 208bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Prev && "Operand was not on use-def list"); 209bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 210bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Prev links are circular, next link is NULL instead of looping back to 211bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Head. 212bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Src == Head) 213bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Head = Dst; 214bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen else 215bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Prev->Contents.Reg.Next = Dst; 216bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 217bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Update Prev pointer. This also works when Src was pointing to itself 218bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // in a 1-element list. In that case Head == Dst. 219bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen (Next ? Next : Head)->Contents.Reg.Prev = Dst; 220bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } 221bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 222bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Dst += Stride; 223bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Src += Stride; 224bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } while (--NumOps); 225bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen} 226bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 227e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 228e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 229e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 230e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 231e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 232e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 233e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 234e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 235e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &O = I.getOperand(); 236e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 237e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 238e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 239e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 240e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 241a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 242a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 243a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 244a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 245a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 2462bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman // Since we are in SSA form, we can use the first definition. 2471e8db1a4faac5c9fdd486a6ddcdec1909f12e789Benjamin Kramer def_iterator I = def_begin(Reg); 2485f917cd3fada4507c0f4b718dd6af24b5e7086f1Manman Ren assert((I.atEnd() || llvm::next(I) == def_end()) && 2495f917cd3fada4507c0f4b718dd6af24b5e7086f1Manman Ren "getVRegDef assumes a single definition or no definition"); 2501e8db1a4faac5c9fdd486a6ddcdec1909f12e789Benjamin Kramer return !I.atEnd() ? &*I : 0; 251a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 2521eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 25354d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// getUniqueVRegDef - Return the unique machine instr that defines the 25454d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// specified virtual register or null if none is found. If there are 25554d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// multiple definitions or no definition, return null. 25654d69668b22b8c37aa6e45f14445f3988cc430d4Manman RenMachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 25754d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren if (def_empty(Reg)) return 0; 25854d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren def_iterator I = def_begin(Reg); 25954d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren if (llvm::next(I) != def_end()) 26054d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren return 0; 26154d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren return &*I; 26254d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren} 26354d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren 2641423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 2651423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_nodbg_iterator UI = use_nodbg_begin(RegNo); 2661423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_nodbg_end()) 2671423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 2681423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_nodbg_end(); 2691423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 2701eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 27149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clearKillFlags - Iterate over all the uses of the given register and 27249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clear the kill flag from the MachineOperand. This function is used by 27349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// optimization passes which extend register lifetimes and need only 27449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// preserve conservative kill flag information. 27549b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohmanvoid MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 27649b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 27749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman UI.getOperand().setIsKill(false); 27849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman} 27949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 28013e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 28113e73f483ef2ba630962dad3125393292533b756Dan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 28213e73f483ef2ba630962dad3125393292533b756Dan Gohman if (I->first == Reg || I->second == Reg) 28313e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 28413e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 28513e73f483ef2ba630962dad3125393292533b756Dan Gohman} 28613e73f483ef2ba630962dad3125393292533b756Dan Gohman 2872ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 2882ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// corresponding live-in physical register. 2892ad0fcf794924f618a7240741cc14a39be99d0f2Evan Chengunsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 2902ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2912ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng if (I->second == VReg) 2922ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return I->first; 2932ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return 0; 2942ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng} 2952ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 2963946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// getLiveInVirtReg - If PReg is a live-in physical register, return the 2973946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// corresponding live-in physical register. 2983946043a80a043b3cf43b34bf068feaadc46485bEvan Chengunsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 2993946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 3003946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng if (I->first == PReg) 3013946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return I->second; 3023946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return 0; 3033946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng} 3043946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 30598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 30698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// into the given entry block. 30798708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanvoid 30898708260f55cab997a5db77e930a2bd35f4172aaDan GohmanMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 30998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 31098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 311701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng // Emit the copies into the top of the block. 312fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 313fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (LiveIns[i].second) { 314fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (use_empty(LiveIns[i].second)) { 315fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // The livein has no uses. Drop it. 316fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // 317fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // It would be preferable to have isel avoid creating live-in 318fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // records for unused arguments in the first place, but it's 319fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // complicated by the debug info code for arguments. 320fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman LiveIns.erase(LiveIns.begin() + i); 321fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman --i; --e; 322fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 323fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Emit a copy. 32468e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 3251e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen TII.get(TargetOpcode::COPY), LiveIns[i].second) 3261e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen .addReg(LiveIns[i].first); 327fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman 328fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 329fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 330fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } 331fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 332fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 333fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 334701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng } 33598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 33698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 3371eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 3381eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 3391eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 3401eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng I.getOperand().getParent()->dump(); 3411eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 3421eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 343d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 344d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesenvoid MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 345d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen ReservedRegs = TRI->getReservedRegs(MF); 346e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen assert(ReservedRegs.size() == TRI->getNumRegs() && 347e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen "Invalid ReservedRegs vector from target"); 348d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen} 349c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 350c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesenbool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 351c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen const MachineFunction &MF) const { 352c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 353c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 354e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen // Check if any overlapping register is modified, or allocatable so it may be 355e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen // used later. 356396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) 357e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen if (!def_empty(*AI) || isAllocatable(*AI)) 358c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return false; 359c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return true; 360c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen} 361