MachineRegisterInfo.cpp revision 0f9c658558f70ba0017575019adbbd0b0b6b13e5
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implementation of the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineRegisterInfo.h" 15#include "llvm/CodeGen/MachineInstrBuilder.h" 16#include "llvm/Target/TargetInstrInfo.h" 17#include "llvm/Support/CommandLine.h" 18using namespace llvm; 19 20MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { 21 VRegInfo.reserve(256); 22 RegAllocHints.reserve(256); 23 RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1. 24 UsedPhysRegs.resize(TRI.getNumRegs()); 25 26 // Create the physreg use/def lists. 27 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 28 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 29} 30 31MachineRegisterInfo::~MachineRegisterInfo() { 32#ifndef NDEBUG 33 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) 34 assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); 35 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 36 assert(!PhysRegUseDefLists[i] && 37 "PhysRegUseDefLists has entries after all instructions are deleted"); 38#endif 39 delete [] PhysRegUseDefLists; 40} 41 42/// setRegClass - Set the register class of the specified virtual register. 43/// 44void 45MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 46 unsigned VR = Reg; 47 Reg -= TargetRegisterInfo::FirstVirtualRegister; 48 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 49 const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 50 VRegInfo[Reg].first = RC; 51 52 // Remove from old register class's vregs list. This may be slow but 53 // fortunately this operation is rarely needed. 54 std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 55 std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR); 56 VRegs.erase(I); 57 58 // Add to new register class's vregs list. 59 RegClass2VRegMap[RC->getID()].push_back(VR); 60} 61 62/// createVirtualRegister - Create and return a new virtual register in the 63/// function with the specified register class. 64/// 65unsigned 66MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 67 assert(RegClass && "Cannot create register without RegClass!"); 68 // Add a reg, but keep track of whether the vector reallocated or not. 69 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 70 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 71 RegAllocHints.push_back(std::make_pair(0, 0)); 72 73 if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1))) 74 // The vector reallocated, handle this now. 75 HandleVRegListReallocation(); 76 unsigned VR = getLastVirtReg(); 77 RegClass2VRegMap[RegClass->getID()].push_back(VR); 78 return VR; 79} 80 81/// HandleVRegListReallocation - We just added a virtual register to the 82/// VRegInfo info list and it reallocated. Update the use/def lists info 83/// pointers. 84void MachineRegisterInfo::HandleVRegListReallocation() { 85 // The back pointers for the vreg lists point into the previous vector. 86 // Update them to point to their correct slots. 87 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) { 88 MachineOperand *List = VRegInfo[i].second; 89 if (!List) continue; 90 // Update the back-pointer to be accurate once more. 91 List->Contents.Reg.Prev = &VRegInfo[i].second; 92 } 93} 94 95/// replaceRegWith - Replace all instances of FromReg with ToReg in the 96/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 97/// except that it also changes any definitions of the register as well. 98void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 99 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 100 101 // TODO: This could be more efficient by bulk changing the operands. 102 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 103 MachineOperand &O = I.getOperand(); 104 ++I; 105 O.setReg(ToReg); 106 } 107} 108 109 110/// getVRegDef - Return the machine instr that defines the specified virtual 111/// register or null if none is found. This assumes that the code is in SSA 112/// form, so there should only be one definition. 113MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 114 assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && 115 "Invalid vreg!"); 116 // Since we are in SSA form, we can use the first definition. 117 if (!def_empty(Reg)) 118 return &*def_begin(Reg); 119 return 0; 120} 121 122bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 123 use_iterator UI = use_begin(RegNo); 124 if (UI == use_end()) 125 return false; 126 return ++UI == use_end(); 127} 128 129bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 130 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 131 if (UI == use_nodbg_end()) 132 return false; 133 return ++UI == use_nodbg_end(); 134} 135 136/// clearKillFlags - Iterate over all the uses of the given register and 137/// clear the kill flag from the MachineOperand. This function is used by 138/// optimization passes which extend register lifetimes and need only 139/// preserve conservative kill flag information. 140void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 141 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 142 UI.getOperand().setIsKill(false); 143} 144 145bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 146 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 147 if (I->first == Reg || I->second == Reg) 148 return true; 149 return false; 150} 151 152bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 153 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 154 if (*I == Reg) 155 return true; 156 return false; 157} 158 159/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 160/// corresponding live-in physical register. 161unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 162 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 163 if (I->second == VReg) 164 return I->first; 165 return 0; 166} 167 168/// getLiveInVirtReg - If PReg is a live-in physical register, return the 169/// corresponding live-in physical register. 170unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 171 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 172 if (I->first == PReg) 173 return I->second; 174 return 0; 175} 176 177/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 178/// into the given entry block. 179void 180MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 181 const TargetRegisterInfo &TRI, 182 const TargetInstrInfo &TII) { 183 // Emit the copies into the top of the block. 184 for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 185 E = livein_end(); LI != E; ++LI) 186 if (LI->second) { 187 const TargetRegisterClass *RC = getRegClass(LI->second); 188 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 189 LI->second, LI->first, RC, RC, 190 DebugLoc()); 191 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 192 (void) Emitted; 193 } 194 195 // Add function live-ins to entry block live-in set. 196 for (MachineRegisterInfo::livein_iterator I = livein_begin(), 197 E = livein_end(); I != E; ++I) 198 EntryMBB->addLiveIn(I->first); 199} 200 201void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) { 202 for (int i = UsedPhysRegs.find_first(); i >= 0; 203 i = UsedPhysRegs.find_next(i)) 204 for (const unsigned *SS = TRI.getSubRegisters(i); 205 unsigned SubReg = *SS; ++SS) 206 if (SubReg > unsigned(i)) 207 UsedPhysRegs.set(SubReg); 208} 209 210#ifndef NDEBUG 211void MachineRegisterInfo::dumpUses(unsigned Reg) const { 212 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 213 I.getOperand().getParent()->dump(); 214} 215#endif 216