MachineRegisterInfo.cpp revision 269120cd9b45b24665433ea28eb7d092c138ca76
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implementation of the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineRegisterInfo.h" 15#include "llvm/CodeGen/MachineInstrBuilder.h" 16#include "llvm/Target/TargetInstrInfo.h" 17#include "llvm/Target/TargetMachine.h" 18using namespace llvm; 19 20MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) { 22 VRegInfo.reserve(256); 23 RegAllocHints.reserve(256); 24 UsedPhysRegs.resize(TRI.getNumRegs()); 25 UsedPhysRegMask.resize(TRI.getNumRegs()); 26 27 // Create the physreg use/def lists. 28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 30} 31 32MachineRegisterInfo::~MachineRegisterInfo() { 33#ifndef NDEBUG 34 clearVirtRegs(); 35 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 36 assert(!PhysRegUseDefLists[i] && 37 "PhysRegUseDefLists has entries after all instructions are deleted"); 38#endif 39 delete [] PhysRegUseDefLists; 40} 41 42/// setRegClass - Set the register class of the specified virtual register. 43/// 44void 45MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 46 VRegInfo[Reg].first = RC; 47} 48 49const TargetRegisterClass * 50MachineRegisterInfo::constrainRegClass(unsigned Reg, 51 const TargetRegisterClass *RC, 52 unsigned MinNumRegs) { 53 const TargetRegisterClass *OldRC = getRegClass(Reg); 54 if (OldRC == RC) 55 return RC; 56 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 57 if (!NewRC || NewRC == OldRC) 58 return NewRC; 59 if (NewRC->getNumRegs() < MinNumRegs) 60 return 0; 61 setRegClass(Reg, NewRC); 62 return NewRC; 63} 64 65bool 66MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 67 const TargetInstrInfo *TII = TM.getInstrInfo(); 68 const TargetRegisterClass *OldRC = getRegClass(Reg); 69 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 70 71 // Stop early if there is no room to grow. 72 if (NewRC == OldRC) 73 return false; 74 75 // Accumulate constraints from all uses. 76 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 77 ++I) { 78 const TargetRegisterClass *OpRC = 79 I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 80 if (unsigned SubIdx = I.getOperand().getSubReg()) { 81 if (OpRC) 82 NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); 83 else 84 NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); 85 } else if (OpRC) 86 NewRC = TRI->getCommonSubClass(NewRC, OpRC); 87 if (!NewRC || NewRC == OldRC) 88 return false; 89 } 90 setRegClass(Reg, NewRC); 91 return true; 92} 93 94/// createVirtualRegister - Create and return a new virtual register in the 95/// function with the specified register class. 96/// 97unsigned 98MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 99 assert(RegClass && "Cannot create register without RegClass!"); 100 assert(RegClass->isAllocatable() && 101 "Virtual register RegClass must be allocatable."); 102 103 // New virtual register number. 104 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 105 106 // Add a reg, but keep track of whether the vector reallocated or not. 107 const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0); 108 void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg]; 109 VRegInfo.grow(Reg); 110 VRegInfo[Reg].first = RegClass; 111 RegAllocHints.grow(Reg); 112 113 if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) 114 // The vector reallocated, handle this now. 115 HandleVRegListReallocation(); 116 return Reg; 117} 118 119/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 120void MachineRegisterInfo::clearVirtRegs() { 121#ifndef NDEBUG 122 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 123 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 124 "Vreg use list non-empty still?"); 125#endif 126 VRegInfo.clear(); 127} 128 129/// HandleVRegListReallocation - We just added a virtual register to the 130/// VRegInfo info list and it reallocated. Update the use/def lists info 131/// pointers. 132void MachineRegisterInfo::HandleVRegListReallocation() { 133 // The back pointers for the vreg lists point into the previous vector. 134 // Update them to point to their correct slots. 135 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 136 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 137 MachineOperand *List = VRegInfo[Reg].second; 138 if (!List) continue; 139 // Update the back-pointer to be accurate once more. 140 List->Contents.Reg.Prev = &VRegInfo[Reg].second; 141 } 142} 143 144/// replaceRegWith - Replace all instances of FromReg with ToReg in the 145/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 146/// except that it also changes any definitions of the register as well. 147void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 148 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 149 150 // TODO: This could be more efficient by bulk changing the operands. 151 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 152 MachineOperand &O = I.getOperand(); 153 ++I; 154 O.setReg(ToReg); 155 } 156} 157 158 159/// getVRegDef - Return the machine instr that defines the specified virtual 160/// register or null if none is found. This assumes that the code is in SSA 161/// form, so there should only be one definition. 162MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 163 // Since we are in SSA form, we can use the first definition. 164 def_iterator I = def_begin(Reg); 165 assert((I.atEnd() || llvm::next(I) == def_end()) && 166 "getVRegDef assumes a single definition or no definition"); 167 return !I.atEnd() ? &*I : 0; 168} 169 170/// getUniqueVRegDef - Return the unique machine instr that defines the 171/// specified virtual register or null if none is found. If there are 172/// multiple definitions or no definition, return null. 173MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 174 if (def_empty(Reg)) return 0; 175 def_iterator I = def_begin(Reg); 176 if (llvm::next(I) != def_end()) 177 return 0; 178 return &*I; 179} 180 181bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 182 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 183 if (UI == use_nodbg_end()) 184 return false; 185 return ++UI == use_nodbg_end(); 186} 187 188/// clearKillFlags - Iterate over all the uses of the given register and 189/// clear the kill flag from the MachineOperand. This function is used by 190/// optimization passes which extend register lifetimes and need only 191/// preserve conservative kill flag information. 192void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 193 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 194 UI.getOperand().setIsKill(false); 195} 196 197bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 198 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 199 if (I->first == Reg || I->second == Reg) 200 return true; 201 return false; 202} 203 204bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 205 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 206 if (*I == Reg) 207 return true; 208 return false; 209} 210 211/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 212/// corresponding live-in physical register. 213unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 214 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 215 if (I->second == VReg) 216 return I->first; 217 return 0; 218} 219 220/// getLiveInVirtReg - If PReg is a live-in physical register, return the 221/// corresponding live-in physical register. 222unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 223 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 224 if (I->first == PReg) 225 return I->second; 226 return 0; 227} 228 229/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 230/// into the given entry block. 231void 232MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 233 const TargetRegisterInfo &TRI, 234 const TargetInstrInfo &TII) { 235 // Emit the copies into the top of the block. 236 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 237 if (LiveIns[i].second) { 238 if (use_empty(LiveIns[i].second)) { 239 // The livein has no uses. Drop it. 240 // 241 // It would be preferable to have isel avoid creating live-in 242 // records for unused arguments in the first place, but it's 243 // complicated by the debug info code for arguments. 244 LiveIns.erase(LiveIns.begin() + i); 245 --i; --e; 246 } else { 247 // Emit a copy. 248 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 249 TII.get(TargetOpcode::COPY), LiveIns[i].second) 250 .addReg(LiveIns[i].first); 251 252 // Add the register to the entry block live-in set. 253 EntryMBB->addLiveIn(LiveIns[i].first); 254 } 255 } else { 256 // Add the register to the entry block live-in set. 257 EntryMBB->addLiveIn(LiveIns[i].first); 258 } 259} 260 261#ifndef NDEBUG 262void MachineRegisterInfo::dumpUses(unsigned Reg) const { 263 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 264 I.getOperand().getParent()->dump(); 265} 266#endif 267 268void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 269 ReservedRegs = TRI->getReservedRegs(MF); 270} 271 272bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 273 const MachineFunction &MF) const { 274 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 275 276 // Check if any overlapping register is modified. 277 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) 278 if (!def_empty(*AI)) 279 return false; 280 281 // Check if any overlapping register is allocatable so it may be used later. 282 if (AllocatableRegs.empty()) 283 AllocatableRegs = TRI->getAllocatableSet(MF); 284 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) 285 if (AllocatableRegs.test(*AI)) 286 return false; 287 return true; 288} 289