MachineRegisterInfo.cpp revision 82b07dc4995d48065bd95affff4d8513a5cad4f2
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implementation of the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineRegisterInfo.h" 15#include "llvm/CodeGen/MachineInstrBuilder.h" 16#include "llvm/Target/TargetInstrInfo.h" 17#include "llvm/Support/CommandLine.h" 18using namespace llvm; 19 20MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { 21 VRegInfo.reserve(256); 22 RegAllocHints.reserve(256); 23 RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1. 24 UsedPhysRegs.resize(TRI.getNumRegs()); 25 26 // Create the physreg use/def lists. 27 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 28 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 29} 30 31MachineRegisterInfo::~MachineRegisterInfo() { 32#ifndef NDEBUG 33 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) 34 assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); 35 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 36 assert(!PhysRegUseDefLists[i] && 37 "PhysRegUseDefLists has entries after all instructions are deleted"); 38#endif 39 delete [] PhysRegUseDefLists; 40} 41 42/// setRegClass - Set the register class of the specified virtual register. 43/// 44void 45MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 46 unsigned VR = Reg; 47 Reg -= TargetRegisterInfo::FirstVirtualRegister; 48 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 49 const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 50 VRegInfo[Reg].first = RC; 51 52 // Remove from old register class's vregs list. This may be slow but 53 // fortunately this operation is rarely needed. 54 std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 55 std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR); 56 VRegs.erase(I); 57 58 // Add to new register class's vregs list. 59 RegClass2VRegMap[RC->getID()].push_back(VR); 60} 61 62/// createVirtualRegister - Create and return a new virtual register in the 63/// function with the specified register class. 64/// 65unsigned 66MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 67 assert(RegClass && "Cannot create register without RegClass!"); 68 // Add a reg, but keep track of whether the vector reallocated or not. 69 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 70 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 71 RegAllocHints.push_back(std::make_pair(0, 0)); 72 73 if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1))) 74 // The vector reallocated, handle this now. 75 HandleVRegListReallocation(); 76 unsigned VR = getLastVirtReg(); 77 RegClass2VRegMap[RegClass->getID()].push_back(VR); 78 return VR; 79} 80 81/// HandleVRegListReallocation - We just added a virtual register to the 82/// VRegInfo info list and it reallocated. Update the use/def lists info 83/// pointers. 84void MachineRegisterInfo::HandleVRegListReallocation() { 85 // The back pointers for the vreg lists point into the previous vector. 86 // Update them to point to their correct slots. 87 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) { 88 MachineOperand *List = VRegInfo[i].second; 89 if (!List) continue; 90 // Update the back-pointer to be accurate once more. 91 List->Contents.Reg.Prev = &VRegInfo[i].second; 92 } 93} 94 95/// replaceRegWith - Replace all instances of FromReg with ToReg in the 96/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 97/// except that it also changes any definitions of the register as well. 98void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 99 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 100 101 // TODO: This could be more efficient by bulk changing the operands. 102 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 103 MachineOperand &O = I.getOperand(); 104 ++I; 105 O.setReg(ToReg); 106 } 107} 108 109 110/// getVRegDef - Return the machine instr that defines the specified virtual 111/// register or null if none is found. This assumes that the code is in SSA 112/// form, so there should only be one definition. 113MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 114 assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && 115 "Invalid vreg!"); 116 // Since we are in SSA form, we can use the first definition. 117 if (!def_empty(Reg)) 118 return &*def_begin(Reg); 119 return 0; 120} 121 122bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 123 use_iterator UI = use_begin(RegNo); 124 if (UI == use_end()) 125 return false; 126 return ++UI == use_end(); 127} 128 129bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 130 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 131 if (UI == use_nodbg_end()) 132 return false; 133 return ++UI == use_nodbg_end(); 134} 135 136bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 137 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 138 if (I->first == Reg || I->second == Reg) 139 return true; 140 return false; 141} 142 143bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 144 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 145 if (*I == Reg) 146 return true; 147 return false; 148} 149 150/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 151/// corresponding live-in physical register. 152unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 153 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 154 if (I->second == VReg) 155 return I->first; 156 return 0; 157} 158 159static cl::opt<bool> 160SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 161 cl::desc("Schedule copies of livein registers"), 162 cl::init(false)); 163 164/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 165/// physical register has only a single copy use, then coalesced the copy 166/// if possible. 167static void EmitLiveInCopy(MachineBasicBlock *MBB, 168 MachineBasicBlock::iterator &InsertPos, 169 unsigned VirtReg, unsigned PhysReg, 170 const TargetRegisterClass *RC, 171 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 172 const MachineRegisterInfo &MRI, 173 const TargetRegisterInfo &TRI, 174 const TargetInstrInfo &TII) { 175 unsigned NumUses = 0; 176 MachineInstr *UseMI = NULL; 177 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 178 UE = MRI.use_end(); UI != UE; ++UI) { 179 UseMI = &*UI; 180 if (++NumUses > 1) 181 break; 182 } 183 184 // If the number of uses is not one, or the use is not a move instruction, 185 // don't coalesce. Also, only coalesce away a virtual register to virtual 186 // register copy. 187 bool Coalesced = false; 188 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 189 if (NumUses == 1 && 190 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 191 TargetRegisterInfo::isVirtualRegister(DstReg)) { 192 VirtReg = DstReg; 193 Coalesced = true; 194 } 195 196 // Now find an ideal location to insert the copy. 197 MachineBasicBlock::iterator Pos = InsertPos; 198 while (Pos != MBB->begin()) { 199 MachineInstr *PrevMI = prior(Pos); 200 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 201 // copyRegToReg might emit multiple instructions to do a copy. 202 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 203 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 204 // This is what the BB looks like right now: 205 // r1024 = mov r0 206 // ... 207 // r1 = mov r1024 208 // 209 // We want to insert "r1025 = mov r1". Inserting this copy below the 210 // move to r1024 makes it impossible for that move to be coalesced. 211 // 212 // r1025 = mov r1 213 // r1024 = mov r0 214 // ... 215 // r1 = mov 1024 216 // r2 = mov 1025 217 break; // Woot! Found a good location. 218 --Pos; 219 } 220 221 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC, 222 DebugLoc()); 223 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 224 (void) Emitted; 225 226 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 227 if (Coalesced) { 228 if (&*InsertPos == UseMI) ++InsertPos; 229 MBB->erase(UseMI); 230 } 231} 232 233/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 234/// into the given entry block. 235void 236MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 237 const TargetRegisterInfo &TRI, 238 const TargetInstrInfo &TII) { 239 if (SchedLiveInCopies) { 240 // Emit the copies at a heuristically-determined location in the block. 241 DenseMap<MachineInstr*, unsigned> CopyRegMap; 242 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 243 for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 244 E = livein_end(); LI != E; ++LI) 245 if (LI->second) { 246 const TargetRegisterClass *RC = getRegClass(LI->second); 247 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 248 RC, CopyRegMap, *this, TRI, TII); 249 } 250 } else { 251 // Emit the copies into the top of the block. 252 for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 253 E = livein_end(); LI != E; ++LI) 254 if (LI->second) { 255 const TargetRegisterClass *RC = getRegClass(LI->second); 256 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 257 LI->second, LI->first, RC, RC, 258 DebugLoc()); 259 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 260 (void) Emitted; 261 } 262 } 263 264 // Add function live-ins to entry block live-in set. 265 for (MachineRegisterInfo::livein_iterator I = livein_begin(), 266 E = livein_end(); I != E; ++I) 267 EntryMBB->addLiveIn(I->first); 268} 269 270void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) { 271 for (int i = UsedPhysRegs.find_first(); i >= 0; 272 i = UsedPhysRegs.find_next(i)) 273 for (const unsigned *SS = TRI.getSubRegisters(i); 274 unsigned SubReg = *SS; ++SS) 275 if (SubReg > i) 276 UsedPhysRegs.set(SubReg); 277} 278 279#ifndef NDEBUG 280void MachineRegisterInfo::dumpUses(unsigned Reg) const { 281 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 282 I.getOperand().getParent()->dump(); 283} 284#endif 285