RegAllocGreedy.cpp revision 39b5abf507b43da6b92f68b86406e0015ead18e9
1//===-- RegAllocGreedy.cpp - greedy register allocator --------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the RAGreedy function pass for register allocation in 11// optimized builds. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "regalloc" 16#include "AllocationOrder.h" 17#include "InterferenceCache.h" 18#include "LiveDebugVariables.h" 19#include "LiveRangeEdit.h" 20#include "RegAllocBase.h" 21#include "Spiller.h" 22#include "SpillPlacement.h" 23#include "SplitKit.h" 24#include "VirtRegMap.h" 25#include "RegisterCoalescer.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Analysis/AliasAnalysis.h" 28#include "llvm/Function.h" 29#include "llvm/PassAnalysisSupport.h" 30#include "llvm/CodeGen/CalcSpillWeights.h" 31#include "llvm/CodeGen/EdgeBundles.h" 32#include "llvm/CodeGen/LiveIntervalAnalysis.h" 33#include "llvm/CodeGen/LiveStackAnalysis.h" 34#include "llvm/CodeGen/MachineDominators.h" 35#include "llvm/CodeGen/MachineFunctionPass.h" 36#include "llvm/CodeGen/MachineLoopInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/Passes.h" 39#include "llvm/CodeGen/RegAllocRegistry.h" 40#include "llvm/Target/TargetOptions.h" 41#include "llvm/Support/Debug.h" 42#include "llvm/Support/ErrorHandling.h" 43#include "llvm/Support/raw_ostream.h" 44#include "llvm/Support/Timer.h" 45 46#include <queue> 47 48using namespace llvm; 49 50STATISTIC(NumGlobalSplits, "Number of split global live ranges"); 51STATISTIC(NumLocalSplits, "Number of split local live ranges"); 52STATISTIC(NumEvicted, "Number of interferences evicted"); 53 54static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", 55 createGreedyRegisterAllocator); 56 57namespace { 58class RAGreedy : public MachineFunctionPass, 59 public RegAllocBase, 60 private LiveRangeEdit::Delegate { 61 62 // context 63 MachineFunction *MF; 64 65 // analyses 66 SlotIndexes *Indexes; 67 LiveStacks *LS; 68 MachineDominatorTree *DomTree; 69 MachineLoopInfo *Loops; 70 EdgeBundles *Bundles; 71 SpillPlacement *SpillPlacer; 72 LiveDebugVariables *DebugVars; 73 74 // state 75 std::auto_ptr<Spiller> SpillerInstance; 76 std::priority_queue<std::pair<unsigned, unsigned> > Queue; 77 unsigned NextCascade; 78 79 // Live ranges pass through a number of stages as we try to allocate them. 80 // Some of the stages may also create new live ranges: 81 // 82 // - Region splitting. 83 // - Per-block splitting. 84 // - Local splitting. 85 // - Spilling. 86 // 87 // Ranges produced by one of the stages skip the previous stages when they are 88 // dequeued. This improves performance because we can skip interference checks 89 // that are unlikely to give any results. It also guarantees that the live 90 // range splitting algorithm terminates, something that is otherwise hard to 91 // ensure. 92 enum LiveRangeStage { 93 RS_New, ///< Never seen before. 94 RS_First, ///< First time in the queue. 95 RS_Second, ///< Second time in the queue. 96 RS_Global, ///< Produced by global splitting. 97 RS_Local, ///< Produced by local splitting. 98 RS_Spill ///< Produced by spilling. 99 }; 100 101 static const char *const StageName[]; 102 103 // RegInfo - Keep additional information about each live range. 104 struct RegInfo { 105 LiveRangeStage Stage; 106 107 // Cascade - Eviction loop prevention. See canEvictInterference(). 108 unsigned Cascade; 109 110 RegInfo() : Stage(RS_New), Cascade(0) {} 111 }; 112 113 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo; 114 115 LiveRangeStage getStage(const LiveInterval &VirtReg) const { 116 return ExtraRegInfo[VirtReg.reg].Stage; 117 } 118 119 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { 120 ExtraRegInfo.resize(MRI->getNumVirtRegs()); 121 ExtraRegInfo[VirtReg.reg].Stage = Stage; 122 } 123 124 template<typename Iterator> 125 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) { 126 ExtraRegInfo.resize(MRI->getNumVirtRegs()); 127 for (;Begin != End; ++Begin) { 128 unsigned Reg = (*Begin)->reg; 129 if (ExtraRegInfo[Reg].Stage == RS_New) 130 ExtraRegInfo[Reg].Stage = NewStage; 131 } 132 } 133 134 /// Cost of evicting interference. 135 struct EvictionCost { 136 unsigned BrokenHints; ///< Total number of broken hints. 137 float MaxWeight; ///< Maximum spill weight evicted. 138 139 EvictionCost(unsigned B = 0) : BrokenHints(B), MaxWeight(0) {} 140 141 bool operator<(const EvictionCost &O) const { 142 if (BrokenHints != O.BrokenHints) 143 return BrokenHints < O.BrokenHints; 144 return MaxWeight < O.MaxWeight; 145 } 146 }; 147 148 // splitting state. 149 std::auto_ptr<SplitAnalysis> SA; 150 std::auto_ptr<SplitEditor> SE; 151 152 /// Cached per-block interference maps 153 InterferenceCache IntfCache; 154 155 /// All basic blocks where the current register has uses. 156 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints; 157 158 /// Global live range splitting candidate info. 159 struct GlobalSplitCandidate { 160 unsigned PhysReg; 161 InterferenceCache::Cursor Intf; 162 BitVector LiveBundles; 163 SmallVector<unsigned, 8> ActiveBlocks; 164 165 void reset(InterferenceCache &Cache, unsigned Reg) { 166 PhysReg = Reg; 167 Intf.setPhysReg(Cache, Reg); 168 LiveBundles.clear(); 169 ActiveBlocks.clear(); 170 } 171 }; 172 173 /// Candidate info for for each PhysReg in AllocationOrder. 174 /// This vector never shrinks, but grows to the size of the largest register 175 /// class. 176 SmallVector<GlobalSplitCandidate, 32> GlobalCand; 177 178public: 179 RAGreedy(); 180 181 /// Return the pass name. 182 virtual const char* getPassName() const { 183 return "Greedy Register Allocator"; 184 } 185 186 /// RAGreedy analysis usage. 187 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 188 virtual void releaseMemory(); 189 virtual Spiller &spiller() { return *SpillerInstance; } 190 virtual void enqueue(LiveInterval *LI); 191 virtual LiveInterval *dequeue(); 192 virtual unsigned selectOrSplit(LiveInterval&, 193 SmallVectorImpl<LiveInterval*>&); 194 195 /// Perform register allocation. 196 virtual bool runOnMachineFunction(MachineFunction &mf); 197 198 static char ID; 199 200private: 201 void LRE_WillEraseInstruction(MachineInstr*); 202 bool LRE_CanEraseVirtReg(unsigned); 203 void LRE_WillShrinkVirtReg(unsigned); 204 void LRE_DidCloneVirtReg(unsigned, unsigned); 205 206 float calcSpillCost(); 207 bool addSplitConstraints(InterferenceCache::Cursor, float&); 208 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>); 209 void growRegion(GlobalSplitCandidate &Cand); 210 float calcGlobalSplitCost(GlobalSplitCandidate&); 211 void splitAroundRegion(LiveInterval&, GlobalSplitCandidate&, 212 SmallVectorImpl<LiveInterval*>&); 213 void calcGapWeights(unsigned, SmallVectorImpl<float>&); 214 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool); 215 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&); 216 void evictInterference(LiveInterval&, unsigned, 217 SmallVectorImpl<LiveInterval*>&); 218 219 unsigned tryAssign(LiveInterval&, AllocationOrder&, 220 SmallVectorImpl<LiveInterval*>&); 221 unsigned tryEvict(LiveInterval&, AllocationOrder&, 222 SmallVectorImpl<LiveInterval*>&, unsigned = ~0u); 223 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&, 224 SmallVectorImpl<LiveInterval*>&); 225 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&, 226 SmallVectorImpl<LiveInterval*>&); 227 unsigned trySplit(LiveInterval&, AllocationOrder&, 228 SmallVectorImpl<LiveInterval*>&); 229}; 230} // end anonymous namespace 231 232char RAGreedy::ID = 0; 233 234#ifndef NDEBUG 235const char *const RAGreedy::StageName[] = { 236 "RS_New", 237 "RS_First", 238 "RS_Second", 239 "RS_Global", 240 "RS_Local", 241 "RS_Spill" 242}; 243#endif 244 245// Hysteresis to use when comparing floats. 246// This helps stabilize decisions based on float comparisons. 247const float Hysteresis = 0.98f; 248 249 250FunctionPass* llvm::createGreedyRegisterAllocator() { 251 return new RAGreedy(); 252} 253 254RAGreedy::RAGreedy(): MachineFunctionPass(ID) { 255 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry()); 256 initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); 257 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); 258 initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); 259 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry()); 260 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry()); 261 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry()); 262 initializeLiveStacksPass(*PassRegistry::getPassRegistry()); 263 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry()); 264 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry()); 265 initializeVirtRegMapPass(*PassRegistry::getPassRegistry()); 266 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry()); 267 initializeSpillPlacementPass(*PassRegistry::getPassRegistry()); 268} 269 270void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const { 271 AU.setPreservesCFG(); 272 AU.addRequired<AliasAnalysis>(); 273 AU.addPreserved<AliasAnalysis>(); 274 AU.addRequired<LiveIntervals>(); 275 AU.addRequired<SlotIndexes>(); 276 AU.addPreserved<SlotIndexes>(); 277 AU.addRequired<LiveDebugVariables>(); 278 AU.addPreserved<LiveDebugVariables>(); 279 if (StrongPHIElim) 280 AU.addRequiredID(StrongPHIEliminationID); 281 AU.addRequiredTransitive<RegisterCoalescer>(); 282 AU.addRequired<CalculateSpillWeights>(); 283 AU.addRequired<LiveStacks>(); 284 AU.addPreserved<LiveStacks>(); 285 AU.addRequired<MachineDominatorTree>(); 286 AU.addPreserved<MachineDominatorTree>(); 287 AU.addRequired<MachineLoopInfo>(); 288 AU.addPreserved<MachineLoopInfo>(); 289 AU.addRequired<VirtRegMap>(); 290 AU.addPreserved<VirtRegMap>(); 291 AU.addRequired<EdgeBundles>(); 292 AU.addRequired<SpillPlacement>(); 293 MachineFunctionPass::getAnalysisUsage(AU); 294} 295 296 297//===----------------------------------------------------------------------===// 298// LiveRangeEdit delegate methods 299//===----------------------------------------------------------------------===// 300 301void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) { 302 // LRE itself will remove from SlotIndexes and parent basic block. 303 VRM->RemoveMachineInstrFromMaps(MI); 304} 305 306bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { 307 if (unsigned PhysReg = VRM->getPhys(VirtReg)) { 308 unassign(LIS->getInterval(VirtReg), PhysReg); 309 return true; 310 } 311 // Unassigned virtreg is probably in the priority queue. 312 // RegAllocBase will erase it after dequeueing. 313 return false; 314} 315 316void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { 317 unsigned PhysReg = VRM->getPhys(VirtReg); 318 if (!PhysReg) 319 return; 320 321 // Register is assigned, put it back on the queue for reassignment. 322 LiveInterval &LI = LIS->getInterval(VirtReg); 323 unassign(LI, PhysReg); 324 enqueue(&LI); 325} 326 327void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) { 328 // LRE may clone a virtual register because dead code elimination causes it to 329 // be split into connected components. Ensure that the new register gets the 330 // same stage as the parent. 331 ExtraRegInfo.grow(New); 332 ExtraRegInfo[New] = ExtraRegInfo[Old]; 333} 334 335void RAGreedy::releaseMemory() { 336 SpillerInstance.reset(0); 337 ExtraRegInfo.clear(); 338 GlobalCand.clear(); 339 RegAllocBase::releaseMemory(); 340} 341 342void RAGreedy::enqueue(LiveInterval *LI) { 343 // Prioritize live ranges by size, assigning larger ranges first. 344 // The queue holds (size, reg) pairs. 345 const unsigned Size = LI->getSize(); 346 const unsigned Reg = LI->reg; 347 assert(TargetRegisterInfo::isVirtualRegister(Reg) && 348 "Can only enqueue virtual registers"); 349 unsigned Prio; 350 351 ExtraRegInfo.grow(Reg); 352 if (ExtraRegInfo[Reg].Stage == RS_New) 353 ExtraRegInfo[Reg].Stage = RS_First; 354 355 if (ExtraRegInfo[Reg].Stage == RS_Second) 356 // Unsplit ranges that couldn't be allocated immediately are deferred until 357 // everything else has been allocated. Long ranges are allocated last so 358 // they are split against realistic interference. 359 Prio = (1u << 31) - Size; 360 else { 361 // Everything else is allocated in long->short order. Long ranges that don't 362 // fit should be spilled ASAP so they don't create interference. 363 Prio = (1u << 31) + Size; 364 365 // Boost ranges that have a physical register hint. 366 if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg))) 367 Prio |= (1u << 30); 368 } 369 370 Queue.push(std::make_pair(Prio, Reg)); 371} 372 373LiveInterval *RAGreedy::dequeue() { 374 if (Queue.empty()) 375 return 0; 376 LiveInterval *LI = &LIS->getInterval(Queue.top().second); 377 Queue.pop(); 378 return LI; 379} 380 381 382//===----------------------------------------------------------------------===// 383// Direct Assignment 384//===----------------------------------------------------------------------===// 385 386/// tryAssign - Try to assign VirtReg to an available register. 387unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, 388 AllocationOrder &Order, 389 SmallVectorImpl<LiveInterval*> &NewVRegs) { 390 Order.rewind(); 391 unsigned PhysReg; 392 while ((PhysReg = Order.next())) 393 if (!checkPhysRegInterference(VirtReg, PhysReg)) 394 break; 395 if (!PhysReg || Order.isHint(PhysReg)) 396 return PhysReg; 397 398 // PhysReg is available, but there may be a better choice. 399 400 // If we missed a simple hint, try to cheaply evict interference from the 401 // preferred register. 402 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) 403 if (Order.isHint(Hint)) { 404 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n'); 405 EvictionCost MaxCost(1); 406 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { 407 evictInterference(VirtReg, Hint, NewVRegs); 408 return Hint; 409 } 410 } 411 412 // Try to evict interference from a cheaper alternative. 413 unsigned Cost = TRI->getCostPerUse(PhysReg); 414 415 // Most registers have 0 additional cost. 416 if (!Cost) 417 return PhysReg; 418 419 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost 420 << '\n'); 421 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); 422 return CheapReg ? CheapReg : PhysReg; 423} 424 425 426//===----------------------------------------------------------------------===// 427// Interference eviction 428//===----------------------------------------------------------------------===// 429 430/// shouldEvict - determine if A should evict the assigned live range B. The 431/// eviction policy defined by this function together with the allocation order 432/// defined by enqueue() decides which registers ultimately end up being split 433/// and spilled. 434/// 435/// Cascade numbers are used to prevent infinite loops if this function is a 436/// cyclic relation. 437/// 438/// @param A The live range to be assigned. 439/// @param IsHint True when A is about to be assigned to its preferred 440/// register. 441/// @param B The live range to be evicted. 442/// @param BreaksHint True when B is already assigned to its preferred register. 443bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint, 444 LiveInterval &B, bool BreaksHint) { 445 bool CanSplit = getStage(B) <= RS_Second; 446 447 // Be fairly aggressive about following hints as long as the evictee can be 448 // split. 449 if (CanSplit && IsHint && !BreaksHint) 450 return true; 451 452 return A.weight > B.weight; 453} 454 455/// canEvictInterference - Return true if all interferences between VirtReg and 456/// PhysReg can be evicted. When OnlyCheap is set, don't do anything 457/// 458/// @param VirtReg Live range that is about to be assigned. 459/// @param PhysReg Desired register for assignment. 460/// @prarm IsHint True when PhysReg is VirtReg's preferred register. 461/// @param MaxCost Only look for cheaper candidates and update with new cost 462/// when returning true. 463/// @returns True when interference can be evicted cheaper than MaxCost. 464bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, 465 bool IsHint, EvictionCost &MaxCost) { 466 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never 467 // involved in an eviction before. If a cascade number was assigned, deny 468 // evicting anything with the same or a newer cascade number. This prevents 469 // infinite eviction loops. 470 // 471 // This works out so a register without a cascade number is allowed to evict 472 // anything, and it can be evicted by anything. 473 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; 474 if (!Cascade) 475 Cascade = NextCascade; 476 477 EvictionCost Cost; 478 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) { 479 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); 480 // If there is 10 or more interferences, chances are one is heavier. 481 if (Q.collectInterferingVRegs(10) >= 10) 482 return false; 483 484 // Check if any interfering live range is heavier than MaxWeight. 485 for (unsigned i = Q.interferingVRegs().size(); i; --i) { 486 LiveInterval *Intf = Q.interferingVRegs()[i - 1]; 487 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg)) 488 return false; 489 // Never evict spill products. They cannot split or spill. 490 if (getStage(*Intf) == RS_Spill) 491 return false; 492 // Once a live range becomes small enough, it is urgent that we find a 493 // register for it. This is indicated by an infinite spill weight. These 494 // urgent live ranges get to evict almost anything. 495 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable(); 496 // Only evict older cascades or live ranges without a cascade. 497 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade; 498 if (Cascade <= IntfCascade) { 499 if (!Urgent) 500 return false; 501 // We permit breaking cascades for urgent evictions. It should be the 502 // last resort, though, so make it really expensive. 503 Cost.BrokenHints += 10; 504 } 505 // Would this break a satisfied hint? 506 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg); 507 // Update eviction cost. 508 Cost.BrokenHints += BreaksHint; 509 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight); 510 // Abort if this would be too expensive. 511 if (!(Cost < MaxCost)) 512 return false; 513 // Finally, apply the eviction policy for non-urgent evictions. 514 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) 515 return false; 516 } 517 } 518 MaxCost = Cost; 519 return true; 520} 521 522/// evictInterference - Evict any interferring registers that prevent VirtReg 523/// from being assigned to Physreg. This assumes that canEvictInterference 524/// returned true. 525void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, 526 SmallVectorImpl<LiveInterval*> &NewVRegs) { 527 // Make sure that VirtReg has a cascade number, and assign that cascade 528 // number to every evicted register. These live ranges than then only be 529 // evicted by a newer cascade, preventing infinite loops. 530 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; 531 if (!Cascade) 532 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; 533 534 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI) 535 << " interference: Cascade " << Cascade << '\n'); 536 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) { 537 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); 538 assert(Q.seenAllInterferences() && "Didn't check all interfererences."); 539 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) { 540 LiveInterval *Intf = Q.interferingVRegs()[i]; 541 unassign(*Intf, VRM->getPhys(Intf->reg)); 542 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade || 543 VirtReg.isSpillable() < Intf->isSpillable()) && 544 "Cannot decrease cascade number, illegal eviction"); 545 ExtraRegInfo[Intf->reg].Cascade = Cascade; 546 ++NumEvicted; 547 NewVRegs.push_back(Intf); 548 } 549 } 550} 551 552/// tryEvict - Try to evict all interferences for a physreg. 553/// @param VirtReg Currently unassigned virtual register. 554/// @param Order Physregs to try. 555/// @return Physreg to assign VirtReg, or 0. 556unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, 557 AllocationOrder &Order, 558 SmallVectorImpl<LiveInterval*> &NewVRegs, 559 unsigned CostPerUseLimit) { 560 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled); 561 562 // Keep track of the cheapest interference seen so far. 563 EvictionCost BestCost(~0u); 564 unsigned BestPhys = 0; 565 566 // When we are just looking for a reduced cost per use, don't break any 567 // hints, and only evict smaller spill weights. 568 if (CostPerUseLimit < ~0u) { 569 BestCost.BrokenHints = 0; 570 BestCost.MaxWeight = VirtReg.weight; 571 } 572 573 Order.rewind(); 574 while (unsigned PhysReg = Order.next()) { 575 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit) 576 continue; 577 // The first use of a callee-saved register in a function has cost 1. 578 // Don't start using a CSR when the CostPerUseLimit is low. 579 if (CostPerUseLimit == 1) 580 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg)) 581 if (!MRI->isPhysRegUsed(CSR)) { 582 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " 583 << PrintReg(CSR, TRI) << '\n'); 584 continue; 585 } 586 587 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost)) 588 continue; 589 590 // Best so far. 591 BestPhys = PhysReg; 592 593 // Stop if the hint can be used. 594 if (Order.isHint(PhysReg)) 595 break; 596 } 597 598 if (!BestPhys) 599 return 0; 600 601 evictInterference(VirtReg, BestPhys, NewVRegs); 602 return BestPhys; 603} 604 605 606//===----------------------------------------------------------------------===// 607// Region Splitting 608//===----------------------------------------------------------------------===// 609 610/// addSplitConstraints - Fill out the SplitConstraints vector based on the 611/// interference pattern in Physreg and its aliases. Add the constraints to 612/// SpillPlacement and return the static cost of this split in Cost, assuming 613/// that all preferences in SplitConstraints are met. 614/// Return false if there are no bundles with positive bias. 615bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf, 616 float &Cost) { 617 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks(); 618 619 // Reset interference dependent info. 620 SplitConstraints.resize(UseBlocks.size()); 621 float StaticCost = 0; 622 for (unsigned i = 0; i != UseBlocks.size(); ++i) { 623 const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; 624 SpillPlacement::BlockConstraint &BC = SplitConstraints[i]; 625 626 BC.Number = BI.MBB->getNumber(); 627 Intf.moveToBlock(BC.Number); 628 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare; 629 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare; 630 631 if (!Intf.hasInterference()) 632 continue; 633 634 // Number of spill code instructions to insert. 635 unsigned Ins = 0; 636 637 // Interference for the live-in value. 638 if (BI.LiveIn) { 639 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) 640 BC.Entry = SpillPlacement::MustSpill, ++Ins; 641 else if (Intf.first() < BI.FirstUse) 642 BC.Entry = SpillPlacement::PrefSpill, ++Ins; 643 else if (Intf.first() < BI.LastUse) 644 ++Ins; 645 } 646 647 // Interference for the live-out value. 648 if (BI.LiveOut) { 649 if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) 650 BC.Exit = SpillPlacement::MustSpill, ++Ins; 651 else if (Intf.last() > BI.LastUse) 652 BC.Exit = SpillPlacement::PrefSpill, ++Ins; 653 else if (Intf.last() > BI.FirstUse) 654 ++Ins; 655 } 656 657 // Accumulate the total frequency of inserted spill code. 658 if (Ins) 659 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number); 660 } 661 Cost = StaticCost; 662 663 // Add constraints for use-blocks. Note that these are the only constraints 664 // that may add a positive bias, it is downhill from here. 665 SpillPlacer->addConstraints(SplitConstraints); 666 return SpillPlacer->scanActiveBundles(); 667} 668 669 670/// addThroughConstraints - Add constraints and links to SpillPlacer from the 671/// live-through blocks in Blocks. 672void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf, 673 ArrayRef<unsigned> Blocks) { 674 const unsigned GroupSize = 8; 675 SpillPlacement::BlockConstraint BCS[GroupSize]; 676 unsigned TBS[GroupSize]; 677 unsigned B = 0, T = 0; 678 679 for (unsigned i = 0; i != Blocks.size(); ++i) { 680 unsigned Number = Blocks[i]; 681 Intf.moveToBlock(Number); 682 683 if (!Intf.hasInterference()) { 684 assert(T < GroupSize && "Array overflow"); 685 TBS[T] = Number; 686 if (++T == GroupSize) { 687 SpillPlacer->addLinks(makeArrayRef(TBS, T)); 688 T = 0; 689 } 690 continue; 691 } 692 693 assert(B < GroupSize && "Array overflow"); 694 BCS[B].Number = Number; 695 696 // Interference for the live-in value. 697 if (Intf.first() <= Indexes->getMBBStartIdx(Number)) 698 BCS[B].Entry = SpillPlacement::MustSpill; 699 else 700 BCS[B].Entry = SpillPlacement::PrefSpill; 701 702 // Interference for the live-out value. 703 if (Intf.last() >= SA->getLastSplitPoint(Number)) 704 BCS[B].Exit = SpillPlacement::MustSpill; 705 else 706 BCS[B].Exit = SpillPlacement::PrefSpill; 707 708 if (++B == GroupSize) { 709 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B); 710 SpillPlacer->addConstraints(Array); 711 B = 0; 712 } 713 } 714 715 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B); 716 SpillPlacer->addConstraints(Array); 717 SpillPlacer->addLinks(makeArrayRef(TBS, T)); 718} 719 720void RAGreedy::growRegion(GlobalSplitCandidate &Cand) { 721 // Keep track of through blocks that have not been added to SpillPlacer. 722 BitVector Todo = SA->getThroughBlocks(); 723 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks; 724 unsigned AddedTo = 0; 725#ifndef NDEBUG 726 unsigned Visited = 0; 727#endif 728 729 for (;;) { 730 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive(); 731 // Find new through blocks in the periphery of PrefRegBundles. 732 for (int i = 0, e = NewBundles.size(); i != e; ++i) { 733 unsigned Bundle = NewBundles[i]; 734 // Look at all blocks connected to Bundle in the full graph. 735 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle); 736 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end(); 737 I != E; ++I) { 738 unsigned Block = *I; 739 if (!Todo.test(Block)) 740 continue; 741 Todo.reset(Block); 742 // This is a new through block. Add it to SpillPlacer later. 743 ActiveBlocks.push_back(Block); 744#ifndef NDEBUG 745 ++Visited; 746#endif 747 } 748 } 749 // Any new blocks to add? 750 if (ActiveBlocks.size() == AddedTo) 751 break; 752 addThroughConstraints(Cand.Intf, makeArrayRef(ActiveBlocks).slice(AddedTo)); 753 AddedTo = ActiveBlocks.size(); 754 755 // Perhaps iterating can enable more bundles? 756 SpillPlacer->iterate(); 757 } 758 DEBUG(dbgs() << ", v=" << Visited); 759} 760 761/// calcSpillCost - Compute how expensive it would be to split the live range in 762/// SA around all use blocks instead of forming bundle regions. 763float RAGreedy::calcSpillCost() { 764 float Cost = 0; 765 const LiveInterval &LI = SA->getParent(); 766 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks(); 767 for (unsigned i = 0; i != UseBlocks.size(); ++i) { 768 const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; 769 unsigned Number = BI.MBB->getNumber(); 770 // We normally only need one spill instruction - a load or a store. 771 Cost += SpillPlacer->getBlockFrequency(Number); 772 773 // Unless the value is redefined in the block. 774 if (BI.LiveIn && BI.LiveOut) { 775 SlotIndex Start, Stop; 776 tie(Start, Stop) = Indexes->getMBBRange(Number); 777 LiveInterval::const_iterator I = LI.find(Start); 778 assert(I != LI.end() && "Expected live-in value"); 779 // Is there a different live-out value? If so, we need an extra spill 780 // instruction. 781 if (I->end < Stop) 782 Cost += SpillPlacer->getBlockFrequency(Number); 783 } 784 } 785 return Cost; 786} 787 788/// calcGlobalSplitCost - Return the global split cost of following the split 789/// pattern in LiveBundles. This cost should be added to the local cost of the 790/// interference pattern in SplitConstraints. 791/// 792float RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) { 793 float GlobalCost = 0; 794 const BitVector &LiveBundles = Cand.LiveBundles; 795 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks(); 796 for (unsigned i = 0; i != UseBlocks.size(); ++i) { 797 const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; 798 SpillPlacement::BlockConstraint &BC = SplitConstraints[i]; 799 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)]; 800 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)]; 801 unsigned Ins = 0; 802 803 if (BI.LiveIn) 804 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg); 805 if (BI.LiveOut) 806 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg); 807 if (Ins) 808 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number); 809 } 810 811 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) { 812 unsigned Number = Cand.ActiveBlocks[i]; 813 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)]; 814 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)]; 815 if (!RegIn && !RegOut) 816 continue; 817 if (RegIn && RegOut) { 818 // We need double spill code if this block has interference. 819 Cand.Intf.moveToBlock(Number); 820 if (Cand.Intf.hasInterference()) 821 GlobalCost += 2*SpillPlacer->getBlockFrequency(Number); 822 continue; 823 } 824 // live-in / stack-out or stack-in live-out. 825 GlobalCost += SpillPlacer->getBlockFrequency(Number); 826 } 827 return GlobalCost; 828} 829 830/// splitAroundRegion - Split VirtReg around the region determined by 831/// LiveBundles. Make an effort to avoid interference from PhysReg. 832/// 833/// The 'register' interval is going to contain as many uses as possible while 834/// avoiding interference. The 'stack' interval is the complement constructed by 835/// SplitEditor. It will contain the rest. 836/// 837void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, 838 GlobalSplitCandidate &Cand, 839 SmallVectorImpl<LiveInterval*> &NewVRegs) { 840 const BitVector &LiveBundles = Cand.LiveBundles; 841 842 DEBUG({ 843 dbgs() << "Splitting around region for " << PrintReg(Cand.PhysReg, TRI) 844 << " with bundles"; 845 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i)) 846 dbgs() << " EB#" << i; 847 dbgs() << ".\n"; 848 }); 849 850 InterferenceCache::Cursor &Intf = Cand.Intf; 851 LiveRangeEdit LREdit(VirtReg, NewVRegs, this); 852 SE->reset(LREdit); 853 854 // Create the main cross-block interval. 855 const unsigned MainIntv = SE->openIntv(); 856 857 // First handle all the blocks with uses. 858 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks(); 859 for (unsigned i = 0; i != UseBlocks.size(); ++i) { 860 const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; 861 bool RegIn = BI.LiveIn && 862 LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; 863 bool RegOut = BI.LiveOut && 864 LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; 865 866 // Create separate intervals for isolated blocks with multiple uses. 867 if (!RegIn && !RegOut) { 868 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n"); 869 if (!BI.isOneInstr()) { 870 SE->splitSingleBlock(BI); 871 SE->selectIntv(MainIntv); 872 } 873 continue; 874 } 875 876 Intf.moveToBlock(BI.MBB->getNumber()); 877 878 if (RegIn && RegOut) 879 SE->splitLiveThroughBlock(BI.MBB->getNumber(), 880 MainIntv, Intf.first(), 881 MainIntv, Intf.last()); 882 else if (RegIn) 883 SE->splitRegInBlock(BI, MainIntv, Intf.first()); 884 else 885 SE->splitRegOutBlock(BI, MainIntv, Intf.last()); 886 } 887 888 // Handle live-through blocks. 889 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) { 890 unsigned Number = Cand.ActiveBlocks[i]; 891 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)]; 892 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)]; 893 if (!RegIn && !RegOut) 894 continue; 895 Intf.moveToBlock(Number); 896 SE->splitLiveThroughBlock(Number, RegIn ? MainIntv : 0, Intf.first(), 897 RegOut ? MainIntv : 0, Intf.last()); 898 } 899 900 ++NumGlobalSplits; 901 902 SmallVector<unsigned, 8> IntvMap; 903 SE->finish(&IntvMap); 904 DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); 905 906 ExtraRegInfo.resize(MRI->getNumVirtRegs()); 907 unsigned OrigBlocks = SA->getNumLiveBlocks(); 908 909 // Sort out the new intervals created by splitting. We get four kinds: 910 // - Remainder intervals should not be split again. 911 // - Candidate intervals can be assigned to Cand.PhysReg. 912 // - Block-local splits are candidates for local splitting. 913 // - DCE leftovers should go back on the queue. 914 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) { 915 LiveInterval &Reg = *LREdit.get(i); 916 917 // Ignore old intervals from DCE. 918 if (getStage(Reg) != RS_New) 919 continue; 920 921 // Remainder interval. Don't try splitting again, spill if it doesn't 922 // allocate. 923 if (IntvMap[i] == 0) { 924 setStage(Reg, RS_Global); 925 continue; 926 } 927 928 // Main interval. Allow repeated splitting as long as the number of live 929 // blocks is strictly decreasing. 930 if (IntvMap[i] == MainIntv) { 931 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) { 932 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks 933 << " blocks as original.\n"); 934 // Don't allow repeated splitting as a safe guard against looping. 935 setStage(Reg, RS_Global); 936 } 937 continue; 938 } 939 940 // Other intervals are treated as new. This includes local intervals created 941 // for blocks with multiple uses, and anything created by DCE. 942 } 943 944 if (VerifyEnabled) 945 MF->verify(this, "After splitting live range around region"); 946} 947 948unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, 949 SmallVectorImpl<LiveInterval*> &NewVRegs) { 950 float BestCost = Hysteresis * calcSpillCost(); 951 DEBUG(dbgs() << "Cost of isolating all blocks = " << BestCost << '\n'); 952 const unsigned NoCand = ~0u; 953 unsigned BestCand = NoCand; 954 unsigned NumCands = 0; 955 956 Order.rewind(); 957 while (unsigned PhysReg = Order.next()) { 958 // Discard bad candidates before we run out of interference cache cursors. 959 // This will only affect register classes with a lot of registers (>32). 960 if (NumCands == IntfCache.getMaxCursors()) { 961 unsigned WorstCount = ~0u; 962 unsigned Worst = 0; 963 for (unsigned i = 0; i != NumCands; ++i) { 964 if (i == BestCand) 965 continue; 966 unsigned Count = GlobalCand[i].LiveBundles.count(); 967 if (Count < WorstCount) 968 Worst = i, WorstCount = Count; 969 } 970 --NumCands; 971 GlobalCand[Worst] = GlobalCand[NumCands]; 972 } 973 974 if (GlobalCand.size() <= NumCands) 975 GlobalCand.resize(NumCands+1); 976 GlobalSplitCandidate &Cand = GlobalCand[NumCands]; 977 Cand.reset(IntfCache, PhysReg); 978 979 SpillPlacer->prepare(Cand.LiveBundles); 980 float Cost; 981 if (!addSplitConstraints(Cand.Intf, Cost)) { 982 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n"); 983 continue; 984 } 985 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost); 986 if (Cost >= BestCost) { 987 DEBUG({ 988 if (BestCand == NoCand) 989 dbgs() << " worse than no bundles\n"; 990 else 991 dbgs() << " worse than " 992 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; 993 }); 994 continue; 995 } 996 growRegion(Cand); 997 998 SpillPlacer->finish(); 999 1000 // No live bundles, defer to splitSingleBlocks(). 1001 if (!Cand.LiveBundles.any()) { 1002 DEBUG(dbgs() << " no bundles.\n"); 1003 continue; 1004 } 1005 1006 Cost += calcGlobalSplitCost(Cand); 1007 DEBUG({ 1008 dbgs() << ", total = " << Cost << " with bundles"; 1009 for (int i = Cand.LiveBundles.find_first(); i>=0; 1010 i = Cand.LiveBundles.find_next(i)) 1011 dbgs() << " EB#" << i; 1012 dbgs() << ".\n"; 1013 }); 1014 if (Cost < BestCost) { 1015 BestCand = NumCands; 1016 BestCost = Hysteresis * Cost; // Prevent rounding effects. 1017 } 1018 ++NumCands; 1019 } 1020 1021 if (BestCand == NoCand) 1022 return 0; 1023 1024 splitAroundRegion(VirtReg, GlobalCand[BestCand], NewVRegs); 1025 return 0; 1026} 1027 1028 1029//===----------------------------------------------------------------------===// 1030// Local Splitting 1031//===----------------------------------------------------------------------===// 1032 1033 1034/// calcGapWeights - Compute the maximum spill weight that needs to be evicted 1035/// in order to use PhysReg between two entries in SA->UseSlots. 1036/// 1037/// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1]. 1038/// 1039void RAGreedy::calcGapWeights(unsigned PhysReg, 1040 SmallVectorImpl<float> &GapWeight) { 1041 assert(SA->getUseBlocks().size() == 1 && "Not a local interval"); 1042 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front(); 1043 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots; 1044 const unsigned NumGaps = Uses.size()-1; 1045 1046 // Start and end points for the interference check. 1047 SlotIndex StartIdx = BI.LiveIn ? BI.FirstUse.getBaseIndex() : BI.FirstUse; 1048 SlotIndex StopIdx = BI.LiveOut ? BI.LastUse.getBoundaryIndex() : BI.LastUse; 1049 1050 GapWeight.assign(NumGaps, 0.0f); 1051 1052 // Add interference from each overlapping register. 1053 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) { 1054 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI) 1055 .checkInterference()) 1056 continue; 1057 1058 // We know that VirtReg is a continuous interval from FirstUse to LastUse, 1059 // so we don't need InterferenceQuery. 1060 // 1061 // Interference that overlaps an instruction is counted in both gaps 1062 // surrounding the instruction. The exception is interference before 1063 // StartIdx and after StopIdx. 1064 // 1065 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx); 1066 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) { 1067 // Skip the gaps before IntI. 1068 while (Uses[Gap+1].getBoundaryIndex() < IntI.start()) 1069 if (++Gap == NumGaps) 1070 break; 1071 if (Gap == NumGaps) 1072 break; 1073 1074 // Update the gaps covered by IntI. 1075 const float weight = IntI.value()->weight; 1076 for (; Gap != NumGaps; ++Gap) { 1077 GapWeight[Gap] = std::max(GapWeight[Gap], weight); 1078 if (Uses[Gap+1].getBaseIndex() >= IntI.stop()) 1079 break; 1080 } 1081 if (Gap == NumGaps) 1082 break; 1083 } 1084 } 1085} 1086 1087/// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only 1088/// basic block. 1089/// 1090unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, 1091 SmallVectorImpl<LiveInterval*> &NewVRegs) { 1092 assert(SA->getUseBlocks().size() == 1 && "Not a local interval"); 1093 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front(); 1094 1095 // Note that it is possible to have an interval that is live-in or live-out 1096 // while only covering a single block - A phi-def can use undef values from 1097 // predecessors, and the block could be a single-block loop. 1098 // We don't bother doing anything clever about such a case, we simply assume 1099 // that the interval is continuous from FirstUse to LastUse. We should make 1100 // sure that we don't do anything illegal to such an interval, though. 1101 1102 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots; 1103 if (Uses.size() <= 2) 1104 return 0; 1105 const unsigned NumGaps = Uses.size()-1; 1106 1107 DEBUG({ 1108 dbgs() << "tryLocalSplit: "; 1109 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 1110 dbgs() << ' ' << SA->UseSlots[i]; 1111 dbgs() << '\n'; 1112 }); 1113 1114 // Since we allow local split results to be split again, there is a risk of 1115 // creating infinite loops. It is tempting to require that the new live 1116 // ranges have less instructions than the original. That would guarantee 1117 // convergence, but it is too strict. A live range with 3 instructions can be 1118 // split 2+3 (including the COPY), and we want to allow that. 1119 // 1120 // Instead we use these rules: 1121 // 1122 // 1. Allow any split for ranges with getStage() < RS_Local. (Except for the 1123 // noop split, of course). 1124 // 2. Require progress be made for ranges with getStage() >= RS_Local. All 1125 // the new ranges must have fewer instructions than before the split. 1126 // 3. New ranges with the same number of instructions are marked RS_Local, 1127 // smaller ranges are marked RS_New. 1128 // 1129 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent 1130 // excessive splitting and infinite loops. 1131 // 1132 bool ProgressRequired = getStage(VirtReg) >= RS_Local; 1133 1134 // Best split candidate. 1135 unsigned BestBefore = NumGaps; 1136 unsigned BestAfter = 0; 1137 float BestDiff = 0; 1138 1139 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber()); 1140 SmallVector<float, 8> GapWeight; 1141 1142 Order.rewind(); 1143 while (unsigned PhysReg = Order.next()) { 1144 // Keep track of the largest spill weight that would need to be evicted in 1145 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1]. 1146 calcGapWeights(PhysReg, GapWeight); 1147 1148 // Try to find the best sequence of gaps to close. 1149 // The new spill weight must be larger than any gap interference. 1150 1151 // We will split before Uses[SplitBefore] and after Uses[SplitAfter]. 1152 unsigned SplitBefore = 0, SplitAfter = 1; 1153 1154 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]). 1155 // It is the spill weight that needs to be evicted. 1156 float MaxGap = GapWeight[0]; 1157 1158 for (;;) { 1159 // Live before/after split? 1160 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn; 1161 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut; 1162 1163 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' ' 1164 << Uses[SplitBefore] << '-' << Uses[SplitAfter] 1165 << " i=" << MaxGap); 1166 1167 // Stop before the interval gets so big we wouldn't be making progress. 1168 if (!LiveBefore && !LiveAfter) { 1169 DEBUG(dbgs() << " all\n"); 1170 break; 1171 } 1172 // Should the interval be extended or shrunk? 1173 bool Shrink = true; 1174 1175 // How many gaps would the new range have? 1176 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter; 1177 1178 // Legally, without causing looping? 1179 bool Legal = !ProgressRequired || NewGaps < NumGaps; 1180 1181 if (Legal && MaxGap < HUGE_VALF) { 1182 // Estimate the new spill weight. Each instruction reads or writes the 1183 // register. Conservatively assume there are no read-modify-write 1184 // instructions. 1185 // 1186 // Try to guess the size of the new interval. 1187 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1), 1188 Uses[SplitBefore].distance(Uses[SplitAfter]) + 1189 (LiveBefore + LiveAfter)*SlotIndex::InstrDist); 1190 // Would this split be possible to allocate? 1191 // Never allocate all gaps, we wouldn't be making progress. 1192 DEBUG(dbgs() << " w=" << EstWeight); 1193 if (EstWeight * Hysteresis >= MaxGap) { 1194 Shrink = false; 1195 float Diff = EstWeight - MaxGap; 1196 if (Diff > BestDiff) { 1197 DEBUG(dbgs() << " (best)"); 1198 BestDiff = Hysteresis * Diff; 1199 BestBefore = SplitBefore; 1200 BestAfter = SplitAfter; 1201 } 1202 } 1203 } 1204 1205 // Try to shrink. 1206 if (Shrink) { 1207 if (++SplitBefore < SplitAfter) { 1208 DEBUG(dbgs() << " shrink\n"); 1209 // Recompute the max when necessary. 1210 if (GapWeight[SplitBefore - 1] >= MaxGap) { 1211 MaxGap = GapWeight[SplitBefore]; 1212 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i) 1213 MaxGap = std::max(MaxGap, GapWeight[i]); 1214 } 1215 continue; 1216 } 1217 MaxGap = 0; 1218 } 1219 1220 // Try to extend the interval. 1221 if (SplitAfter >= NumGaps) { 1222 DEBUG(dbgs() << " end\n"); 1223 break; 1224 } 1225 1226 DEBUG(dbgs() << " extend\n"); 1227 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]); 1228 } 1229 } 1230 1231 // Didn't find any candidates? 1232 if (BestBefore == NumGaps) 1233 return 0; 1234 1235 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore] 1236 << '-' << Uses[BestAfter] << ", " << BestDiff 1237 << ", " << (BestAfter - BestBefore + 1) << " instrs\n"); 1238 1239 LiveRangeEdit LREdit(VirtReg, NewVRegs, this); 1240 SE->reset(LREdit); 1241 1242 SE->openIntv(); 1243 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]); 1244 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]); 1245 SE->useIntv(SegStart, SegStop); 1246 SmallVector<unsigned, 8> IntvMap; 1247 SE->finish(&IntvMap); 1248 DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); 1249 1250 // If the new range has the same number of instructions as before, mark it as 1251 // RS_Local so the next split will be forced to make progress. Otherwise, 1252 // leave the new intervals as RS_New so they can compete. 1253 bool LiveBefore = BestBefore != 0 || BI.LiveIn; 1254 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut; 1255 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter; 1256 if (NewGaps >= NumGaps) { 1257 DEBUG(dbgs() << "Tagging non-progress ranges: "); 1258 assert(!ProgressRequired && "Didn't make progress when it was required."); 1259 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) 1260 if (IntvMap[i] == 1) { 1261 setStage(*LREdit.get(i), RS_Local); 1262 DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg)); 1263 } 1264 DEBUG(dbgs() << '\n'); 1265 } 1266 ++NumLocalSplits; 1267 1268 return 0; 1269} 1270 1271//===----------------------------------------------------------------------===// 1272// Live Range Splitting 1273//===----------------------------------------------------------------------===// 1274 1275/// trySplit - Try to split VirtReg or one of its interferences, making it 1276/// assignable. 1277/// @return Physreg when VirtReg may be assigned and/or new NewVRegs. 1278unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, 1279 SmallVectorImpl<LiveInterval*>&NewVRegs) { 1280 // Local intervals are handled separately. 1281 if (LIS->intervalIsInOneMBB(VirtReg)) { 1282 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled); 1283 SA->analyze(&VirtReg); 1284 return tryLocalSplit(VirtReg, Order, NewVRegs); 1285 } 1286 1287 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled); 1288 1289 // Don't iterate global splitting. 1290 // Move straight to spilling if this range was produced by a global split. 1291 if (getStage(VirtReg) >= RS_Global) 1292 return 0; 1293 1294 SA->analyze(&VirtReg); 1295 1296 // FIXME: SplitAnalysis may repair broken live ranges coming from the 1297 // coalescer. That may cause the range to become allocatable which means that 1298 // tryRegionSplit won't be making progress. This check should be replaced with 1299 // an assertion when the coalescer is fixed. 1300 if (SA->didRepairRange()) { 1301 // VirtReg has changed, so all cached queries are invalid. 1302 invalidateVirtRegs(); 1303 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) 1304 return PhysReg; 1305 } 1306 1307 // First try to split around a region spanning multiple blocks. 1308 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); 1309 if (PhysReg || !NewVRegs.empty()) 1310 return PhysReg; 1311 1312 // Then isolate blocks with multiple uses. 1313 SplitAnalysis::BlockPtrSet Blocks; 1314 if (SA->getMultiUseBlocks(Blocks)) { 1315 LiveRangeEdit LREdit(VirtReg, NewVRegs, this); 1316 SE->reset(LREdit); 1317 SE->splitSingleBlocks(Blocks); 1318 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Global); 1319 if (VerifyEnabled) 1320 MF->verify(this, "After splitting live range around basic blocks"); 1321 } 1322 1323 // Don't assign any physregs. 1324 return 0; 1325} 1326 1327 1328//===----------------------------------------------------------------------===// 1329// Main Entry Point 1330//===----------------------------------------------------------------------===// 1331 1332unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, 1333 SmallVectorImpl<LiveInterval*> &NewVRegs) { 1334 // First try assigning a free register. 1335 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); 1336 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) 1337 return PhysReg; 1338 1339 LiveRangeStage Stage = getStage(VirtReg); 1340 DEBUG(dbgs() << StageName[Stage] 1341 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n'); 1342 1343 // Try to evict a less worthy live range, but only for ranges from the primary 1344 // queue. The RS_Second ranges already failed to do this, and they should not 1345 // get a second chance until they have been split. 1346 if (Stage != RS_Second) 1347 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs)) 1348 return PhysReg; 1349 1350 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs"); 1351 1352 // The first time we see a live range, don't try to split or spill. 1353 // Wait until the second time, when all smaller ranges have been allocated. 1354 // This gives a better picture of the interference to split around. 1355 if (Stage == RS_First) { 1356 setStage(VirtReg, RS_Second); 1357 DEBUG(dbgs() << "wait for second round\n"); 1358 NewVRegs.push_back(&VirtReg); 1359 return 0; 1360 } 1361 1362 // If we couldn't allocate a register from spilling, there is probably some 1363 // invalid inline assembly. The base class wil report it. 1364 if (Stage >= RS_Spill || !VirtReg.isSpillable()) 1365 return ~0u; 1366 1367 // Try splitting VirtReg or interferences. 1368 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs); 1369 if (PhysReg || !NewVRegs.empty()) 1370 return PhysReg; 1371 1372 // Finally spill VirtReg itself. 1373 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled); 1374 LiveRangeEdit LRE(VirtReg, NewVRegs, this); 1375 spiller().spill(LRE); 1376 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill); 1377 1378 if (VerifyEnabled) 1379 MF->verify(this, "After spilling"); 1380 1381 // The live virtual register requesting allocation was spilled, so tell 1382 // the caller not to allocate anything during this round. 1383 return 0; 1384} 1385 1386bool RAGreedy::runOnMachineFunction(MachineFunction &mf) { 1387 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n" 1388 << "********** Function: " 1389 << ((Value*)mf.getFunction())->getName() << '\n'); 1390 1391 MF = &mf; 1392 if (VerifyEnabled) 1393 MF->verify(this, "Before greedy register allocator"); 1394 1395 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>()); 1396 Indexes = &getAnalysis<SlotIndexes>(); 1397 DomTree = &getAnalysis<MachineDominatorTree>(); 1398 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); 1399 Loops = &getAnalysis<MachineLoopInfo>(); 1400 Bundles = &getAnalysis<EdgeBundles>(); 1401 SpillPlacer = &getAnalysis<SpillPlacement>(); 1402 DebugVars = &getAnalysis<LiveDebugVariables>(); 1403 1404 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops)); 1405 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree)); 1406 ExtraRegInfo.clear(); 1407 ExtraRegInfo.resize(MRI->getNumVirtRegs()); 1408 NextCascade = 1; 1409 IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI); 1410 1411 allocatePhysRegs(); 1412 addMBBLiveIns(MF); 1413 LIS->addKillFlags(); 1414 1415 // Run rewriter 1416 { 1417 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled); 1418 VRM->rewrite(Indexes); 1419 } 1420 1421 // Write out new DBG_VALUE instructions. 1422 DebugVars->emitDebugValues(VRM); 1423 1424 // The pass output is in VirtRegMap. Release all the transient data. 1425 releaseMemory(); 1426 1427 return true; 1428} 1429