RegisterScavenging.cpp revision 977679d6034791fd48a344e5b990503ba50fc242
1//===-- RegisterScavenging.cpp - Machine register scavenging --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the machine register scavenger. It can provide 11// information, such as unused registers, at any point in a machine basic block. 12// It also provides a mechanism to make registers available by evicting them to 13// spill slots. 14// 15//===----------------------------------------------------------------------===// 16 17#define DEBUG_TYPE "reg-scavenging" 18#include "llvm/CodeGen/RegisterScavenging.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineBasicBlock.h" 22#include "llvm/CodeGen/MachineInstr.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/Support/Debug.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Support/raw_ostream.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetInstrInfo.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/STLExtras.h" 34using namespace llvm; 35 36/// setUsed - Set the register and its sub-registers as being used. 37void RegScavenger::setUsed(unsigned Reg) { 38 RegsAvailable.reset(Reg); 39 40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); 41 unsigned SubReg = *SubRegs; ++SubRegs) 42 RegsAvailable.reset(SubReg); 43} 44 45bool RegScavenger::isAliasUsed(unsigned Reg) const { 46 if (isUsed(Reg)) 47 return true; 48 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R) 49 if (isUsed(*R)) 50 return true; 51 return false; 52} 53 54void RegScavenger::initRegState() { 55 ScavengedReg = 0; 56 ScavengedRC = NULL; 57 ScavengeRestore = NULL; 58 59 // All registers started out unused. 60 RegsAvailable.set(); 61 62 // Reserved registers are always used. 63 RegsAvailable ^= ReservedRegs; 64 65 if (!MBB) 66 return; 67 68 // Live-in registers are in use. 69 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 70 E = MBB->livein_end(); I != E; ++I) 71 setUsed(*I); 72 73 // Pristine CSRs are also unavailable. 74 BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB); 75 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) 76 setUsed(I); 77} 78 79void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { 80 MachineFunction &MF = *mbb->getParent(); 81 const TargetMachine &TM = MF.getTarget(); 82 TII = TM.getInstrInfo(); 83 TRI = TM.getRegisterInfo(); 84 MRI = &MF.getRegInfo(); 85 86 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && 87 "Target changed?"); 88 89 // Self-initialize. 90 if (!MBB) { 91 NumPhysRegs = TRI->getNumRegs(); 92 RegsAvailable.resize(NumPhysRegs); 93 94 // Create reserved registers bitvector. 95 ReservedRegs = TRI->getReservedRegs(MF); 96 97 // Create callee-saved registers bitvector. 98 CalleeSavedRegs.resize(NumPhysRegs); 99 const unsigned *CSRegs = TRI->getCalleeSavedRegs(&MF); 100 if (CSRegs != NULL) 101 for (unsigned i = 0; CSRegs[i]; ++i) 102 CalleeSavedRegs.set(CSRegs[i]); 103 } 104 105 MBB = mbb; 106 initRegState(); 107 108 Tracking = false; 109} 110 111void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { 112 BV.set(Reg); 113 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) 114 BV.set(*R); 115} 116 117void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) { 118 BV.set(Reg); 119 for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++) 120 BV.set(*R); 121} 122 123void RegScavenger::forward() { 124 // Move ptr forward. 125 if (!Tracking) { 126 MBBI = MBB->begin(); 127 Tracking = true; 128 } else { 129 assert(MBBI != MBB->end() && "Already past the end of the basic block!"); 130 MBBI = llvm::next(MBBI); 131 } 132 assert(MBBI != MBB->end() && "Already at the end of the basic block!"); 133 134 MachineInstr *MI = MBBI; 135 136 if (MI == ScavengeRestore) { 137 ScavengedReg = 0; 138 ScavengedRC = NULL; 139 ScavengeRestore = NULL; 140 } 141 142 if (MI->isDebugValue()) 143 return; 144 145 // Find out which registers are early clobbered, killed, defined, and marked 146 // def-dead in this instruction. 147 // FIXME: The scavenger is not predication aware. If the instruction is 148 // predicated, conservatively assume "kill" markers do not actually kill the 149 // register. Similarly ignores "dead" markers. 150 bool isPred = TII->isPredicated(MI); 151 BitVector EarlyClobberRegs(NumPhysRegs); 152 BitVector KillRegs(NumPhysRegs); 153 BitVector DefRegs(NumPhysRegs); 154 BitVector DeadRegs(NumPhysRegs); 155 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 156 const MachineOperand &MO = MI->getOperand(i); 157 if (!MO.isReg()) 158 continue; 159 unsigned Reg = MO.getReg(); 160 if (!Reg || isReserved(Reg)) 161 continue; 162 163 if (MO.isUse()) { 164 // Ignore undef uses. 165 if (MO.isUndef()) 166 continue; 167 // Two-address operands implicitly kill. 168 if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i))) 169 addRegWithSubRegs(KillRegs, Reg); 170 } else { 171 assert(MO.isDef()); 172 if (!isPred && MO.isDead()) 173 addRegWithSubRegs(DeadRegs, Reg); 174 else 175 addRegWithSubRegs(DefRegs, Reg); 176 if (MO.isEarlyClobber()) 177 addRegWithAliases(EarlyClobberRegs, Reg); 178 } 179 } 180 181 // Verify uses and defs. 182 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 183 const MachineOperand &MO = MI->getOperand(i); 184 if (!MO.isReg()) 185 continue; 186 unsigned Reg = MO.getReg(); 187 if (!Reg || isReserved(Reg)) 188 continue; 189 if (MO.isUse()) { 190 if (MO.isUndef()) 191 continue; 192 if (!isUsed(Reg)) { 193 // Check if it's partial live: e.g. 194 // D0 = insert_subreg D0<undef>, S0 195 // ... D0 196 // The problem is the insert_subreg could be eliminated. The use of 197 // D0 is using a partially undef value. This is not *incorrect* since 198 // S1 is can be freely clobbered. 199 // Ideally we would like a way to model this, but leaving the 200 // insert_subreg around causes both correctness and performance issues. 201 bool SubUsed = false; 202 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); 203 unsigned SubReg = *SubRegs; ++SubRegs) 204 if (isUsed(SubReg)) { 205 SubUsed = true; 206 break; 207 } 208 assert(SubUsed && "Using an undefined register!"); 209 (void)SubUsed; 210 } 211 assert((!EarlyClobberRegs.test(Reg) || MI->isRegTiedToDefOperand(i)) && 212 "Using an early clobbered register!"); 213 } else { 214 assert(MO.isDef()); 215#if 0 216 // FIXME: Enable this once we've figured out how to correctly transfer 217 // implicit kills during codegen passes like the coalescer. 218 assert((KillRegs.test(Reg) || isUnused(Reg) || 219 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && 220 "Re-defining a live register!"); 221#endif 222 } 223 } 224 225 // Commit the changes. 226 setUnused(KillRegs); 227 setUnused(DeadRegs); 228 setUsed(DefRegs); 229} 230 231void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) { 232 if (includeReserved) 233 used = ~RegsAvailable; 234 else 235 used = ~RegsAvailable & ~ReservedRegs; 236} 237 238unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { 239 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 240 I != E; ++I) 241 if (!isAliasUsed(*I)) { 242 DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) << 243 "\n"); 244 return *I; 245 } 246 return 0; 247} 248 249/// getRegsAvailable - Return all available registers in the register class 250/// in Mask. 251BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { 252 BitVector Mask(TRI->getNumRegs()); 253 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 254 I != E; ++I) 255 if (!isAliasUsed(*I)) 256 Mask.set(*I); 257 return Mask; 258} 259 260/// findSurvivorReg - Return the candidate register that is unused for the 261/// longest after StargMII. UseMI is set to the instruction where the search 262/// stopped. 263/// 264/// No more than InstrLimit instructions are inspected. 265/// 266unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI, 267 BitVector &Candidates, 268 unsigned InstrLimit, 269 MachineBasicBlock::iterator &UseMI) { 270 int Survivor = Candidates.find_first(); 271 assert(Survivor > 0 && "No candidates for scavenging"); 272 273 MachineBasicBlock::iterator ME = MBB->getFirstTerminator(); 274 assert(StartMI != ME && "MI already at terminator"); 275 MachineBasicBlock::iterator RestorePointMI = StartMI; 276 MachineBasicBlock::iterator MI = StartMI; 277 278 bool inVirtLiveRange = false; 279 for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) { 280 if (MI->isDebugValue()) { 281 ++InstrLimit; // Don't count debug instructions 282 continue; 283 } 284 bool isVirtKillInsn = false; 285 bool isVirtDefInsn = false; 286 // Remove any candidates touched by instruction. 287 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 288 const MachineOperand &MO = MI->getOperand(i); 289 if (!MO.isReg() || MO.isUndef() || !MO.getReg()) 290 continue; 291 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 292 if (MO.isDef()) 293 isVirtDefInsn = true; 294 else if (MO.isKill()) 295 isVirtKillInsn = true; 296 continue; 297 } 298 Candidates.reset(MO.getReg()); 299 for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++) 300 Candidates.reset(*R); 301 } 302 // If we're not in a virtual reg's live range, this is a valid 303 // restore point. 304 if (!inVirtLiveRange) RestorePointMI = MI; 305 306 // Update whether we're in the live range of a virtual register 307 if (isVirtKillInsn) inVirtLiveRange = false; 308 if (isVirtDefInsn) inVirtLiveRange = true; 309 310 // Was our survivor untouched by this instruction? 311 if (Candidates.test(Survivor)) 312 continue; 313 314 // All candidates gone? 315 if (Candidates.none()) 316 break; 317 318 Survivor = Candidates.find_first(); 319 } 320 // If we ran off the end, that's where we want to restore. 321 if (MI == ME) RestorePointMI = ME; 322 assert (RestorePointMI != StartMI && 323 "No available scavenger restore location!"); 324 325 // We ran out of candidates, so stop the search. 326 UseMI = RestorePointMI; 327 return Survivor; 328} 329 330unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, 331 MachineBasicBlock::iterator I, 332 int SPAdj) { 333 // Consider all allocatable registers in the register class initially 334 BitVector Candidates = 335 TRI->getAllocatableSet(*I->getParent()->getParent(), RC); 336 337 // Exclude all the registers being used by the instruction. 338 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 339 MachineOperand &MO = I->getOperand(i); 340 if (MO.isReg() && MO.getReg() != 0 && 341 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) 342 Candidates.reset(MO.getReg()); 343 } 344 345 // Try to find a register that's unused if there is one, as then we won't 346 // have to spill. Search explicitly rather than masking out based on 347 // RegsAvailable, as RegsAvailable does not take aliases into account. 348 // That's what getRegsAvailable() is for. 349 BitVector Available = getRegsAvailable(RC); 350 351 if ((Candidates & Available).any()) 352 Candidates &= Available; 353 354 // Find the register whose use is furthest away. 355 MachineBasicBlock::iterator UseMI; 356 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); 357 358 // If we found an unused register there is no reason to spill it. 359 if (!isAliasUsed(SReg)) { 360 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n"); 361 return SReg; 362 } 363 364 assert(ScavengedReg == 0 && 365 "Scavenger slot is live, unable to scavenge another register!"); 366 367 // Avoid infinite regress 368 ScavengedReg = SReg; 369 370 // If the target knows how to save/restore the register, let it do so; 371 // otherwise, use the emergency stack spill slot. 372 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) { 373 // Spill the scavenged register before I. 374 assert(ScavengingFrameIndex >= 0 && 375 "Cannot scavenge register without an emergency spill slot!"); 376 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI); 377 MachineBasicBlock::iterator II = prior(I); 378 TRI->eliminateFrameIndex(II, SPAdj, this); 379 380 // Restore the scavenged register before its use (or first terminator). 381 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI); 382 II = prior(UseMI); 383 TRI->eliminateFrameIndex(II, SPAdj, this); 384 } 385 386 ScavengeRestore = prior(UseMI); 387 388 // Doing this here leads to infinite regress. 389 // ScavengedReg = SReg; 390 ScavengedRC = RC; 391 392 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) << 393 "\n"); 394 395 return SReg; 396} 397