16f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// 2f976c856fcc5055f3fc7d9f070d72c2d027c1d9dMisha Brukman// 3b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell// The LLVM Compiler Infrastructure 4b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7f976c856fcc5055f3fc7d9f070d72c2d027c1d9dMisha Brukman// 8b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell//===----------------------------------------------------------------------===// 99208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner// 106f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman// This file implements the TargetRegisterInfo interface. 119208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner// 129208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner//===----------------------------------------------------------------------===// 139208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner 146f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1561de82d8853a02fe39c47302432abb70a586704fEvan Cheng#include "llvm/ADT/BitVector.h" 167eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen#include "llvm/CodeGen/MachineFunction.h" 177eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen#include "llvm/CodeGen/MachineRegisterInfo.h" 187eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen#include "llvm/CodeGen/VirtRegMap.h" 19414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesen#include "llvm/Support/raw_ostream.h" 20a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey 2120ea062192778c5cc1d05f771fbc58a6e99d753cChris Lattnerusing namespace llvm; 22d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 23a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan ChengTargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 243ad764290179871ad00253e2b6e235596caa3db1Chris Lattner regclass_iterator RCB, regclass_iterator RCE, 25a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen const char *const *SRINames, 26a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen const unsigned *SRILaneMasks) 27a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen : InfoDesc(ID), SubRegIndexNames(SRINames), 28a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen SubRegIndexLaneMasks(SRILaneMasks), 291fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen RegClassBegin(RCB), RegClassEnd(RCE) { 309208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner} 319208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner 326f0d024a534af18d9e60b3ea757376cd8a3a980eDan GohmanTargetRegisterInfo::~TargetRegisterInfo() {} 330aafc3289c3043abd5e8f2efdd8b9fc3e830d97fNate Begeman 344314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenvoid PrintReg::print(raw_ostream &OS) const { 354314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen if (!Reg) 364314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen OS << "%noreg"; 37be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen else if (TargetRegisterInfo::isStackSlot(Reg)) 38be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); 394314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen else if (TargetRegisterInfo::isVirtualRegister(Reg)) 404314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); 41be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen else if (TRI && Reg < TRI->getNumRegs()) 424314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen OS << '%' << TRI->getName(Reg); 43414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesen else 444314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen OS << "%physreg" << Reg; 454314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen if (SubIdx) { 464314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen if (TRI) 474314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen OS << ':' << TRI->getSubRegIndexName(SubIdx); 484314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen else 494314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen OS << ":sub(" << SubIdx << ')'; 504314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen } 51414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesen} 52414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesen 535ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesenvoid PrintRegUnit::print(raw_ostream &OS) const { 545ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen // Generic printout when TRI is missing. 555ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen if (!TRI) { 565ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen OS << "Unit~" << Unit; 575ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen return; 585ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen } 595ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 605ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen // Check for invalid register units. 615ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen if (Unit >= TRI->getNumRegUnits()) { 625ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen OS << "BadUnit~" << Unit; 635ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen return; 645ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen } 655ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 665ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen // Normal units have at least one root. 675ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen MCRegUnitRootIterator Roots(Unit, TRI); 685ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen assert(Roots.isValid() && "Unit has no roots."); 695ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen OS << TRI->getName(*Roots); 705ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen for (++Roots; Roots.isValid(); ++Roots) 715ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen OS << '~' << TRI->getName(*Roots); 725ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen} 735ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 74f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick/// getAllocatableClass - Return the maximal subclass of the given register 75f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick/// class that is alloctable, or NULL. 76f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trickconst TargetRegisterClass * 77f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew TrickTargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 78f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick if (!RC || RC->isAllocatable()) 79f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick return RC; 80f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick 81f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const unsigned *SubClass = RC->getSubClassMask(); 82f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick for (unsigned Base = 0, BaseE = getNumRegClasses(); 83f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick Base < BaseE; Base += 32) { 84f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick unsigned Idx = Base; 85f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) { 86f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick unsigned Offset = CountTrailingZeros_32(Mask); 87f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); 88f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick if (SubRC->isAllocatable()) 89f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick return SubRC; 90f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick Mask >>= Offset; 91f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick Idx += Offset + 1; 92f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick } 93f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick } 94f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick return NULL; 95f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick} 96f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick 97ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola/// getMinimalPhysRegClass - Returns the Register Class of a physical 98c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman/// register of the given type, picking the most sub register class of 99c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman/// the right type that contains this physreg. 100ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindolaconst TargetRegisterClass * 101d31f972bd33de85071c716f69bf5c6d735f730f2Rafael EspindolaTargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { 102ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola assert(isPhysicalRegister(reg) && "reg must be a physical register"); 103ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 104ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola // Pick the most sub register class of the right type that contains 105ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola // this physreg. 106ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola const TargetRegisterClass* BestRC = 0; 107ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ 108ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola const TargetRegisterClass* RC = *I; 109d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 110d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola (!BestRC || BestRC->hasSubClass(RC))) 111ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola BestRC = RC; 112ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola } 113ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 114ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola assert(BestRC && "Couldn't find the register class"); 115ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola return BestRC; 116ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola} 117ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 1187be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng/// getAllocatableSetForRC - Toggle the bits that represent allocatable 1197be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng/// registers for the specific register class. 120769b7f89534caed11d7595b5c84aa47d3de30ad9Dan Gohmanstatic void getAllocatableSetForRC(const MachineFunction &MF, 1213e234e757965a3c30f31227b60575841441368b6Jim Grosbach const TargetRegisterClass *RC, BitVector &R){ 122f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick assert(RC->isAllocatable() && "invalid for nonallocatable sets"); 123b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); 1248936b947760a278b6371335f3411de647989c665Jakob Stoklund Olesen for (unsigned i = 0; i != Order.size(); ++i) 1258936b947760a278b6371335f3411de647989c665Jakob Stoklund Olesen R.set(Order[i]); 1267be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng} 1277be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng 128769b7f89534caed11d7595b5c84aa47d3de30ad9Dan GohmanBitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, 1296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman const TargetRegisterClass *RC) const { 130a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng BitVector Allocatable(getNumRegs()); 1317be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng if (RC) { 132f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick // A register class with no allocatable subclass returns an empty set. 133f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass *SubClass = getAllocatableClass(RC); 134f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick if (SubClass) 135f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick getAllocatableSetForRC(MF, SubClass, Allocatable); 136bb5a039b76cc2cc6de6a5b6bdd4ebf6aefd9d564Jim Grosbach } else { 137bb5a039b76cc2cc6de6a5b6bdd4ebf6aefd9d564Jim Grosbach for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), 1387be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng E = regclass_end(); I != E; ++I) 139f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen if ((*I)->isAllocatable()) 140f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen getAllocatableSetForRC(MF, *I, Allocatable); 141bb5a039b76cc2cc6de6a5b6bdd4ebf6aefd9d564Jim Grosbach } 1425a0fabae5a1792d20df23b6cbd573a9121637d12Jim Grosbach 1435a0fabae5a1792d20df23b6cbd573a9121637d12Jim Grosbach // Mask out the reserved registers 1445a0fabae5a1792d20df23b6cbd573a9121637d12Jim Grosbach BitVector Reserved = getReservedRegs(MF); 14557ca3ccd455160e30e727ef53122c82edf3c6b50Benjamin Kramer Allocatable &= Reserved.flip(); 1465a0fabae5a1792d20df23b6cbd573a9121637d12Jim Grosbach 147bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos return Allocatable; 148f976c856fcc5055f3fc7d9f070d72c2d027c1d9dMisha Brukman} 149a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey 150fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesenstatic inline 151fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesenconst TargetRegisterClass *firstCommonClass(const uint32_t *A, 152fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const uint32_t *B, 153fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterInfo *TRI) { 154fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) 155fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (unsigned Common = *A++ & *B++) 156fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen return TRI->getRegClass(I + CountTrailingZeros_32(Common)); 157fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen return 0; 158fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen} 159fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 160ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesenconst TargetRegisterClass * 161e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund OlesenTargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, 162e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *B) const { 163c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen // First take care of the trivial cases. 164ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen if (A == B) 165ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen return A; 166ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen if (!A || !B) 167ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen return 0; 168ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen 169c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen // Register classes are ordered topologically, so the largest common 170c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen // sub-class it the common sub-class with the smallest ID. 171f191b43103113119e60b19b8e78966803a20c655Jakob Stoklund Olesen return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this); 172ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen} 173dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen 174dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesenconst TargetRegisterClass * 175dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund OlesenTargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 176dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen const TargetRegisterClass *B, 177dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen unsigned Idx) const { 178dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen assert(A && B && "Missing register class"); 179dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen assert(Idx && "Bad sub-register index"); 180dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen 181dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen // Find Idx in the list of super-register indices. 18289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) 183f191b43103113119e60b19b8e78966803a20c655Jakob Stoklund Olesen if (RCI.getSubReg() == Idx) 184f191b43103113119e60b19b8e78966803a20c655Jakob Stoklund Olesen // The bit mask contains all register classes that are projected into B 185f191b43103113119e60b19b8e78966803a20c655Jakob Stoklund Olesen // by Idx. Find a class that is also a sub-class of A. 186f191b43103113119e60b19b8e78966803a20c655Jakob Stoklund Olesen return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); 187dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen return 0; 188dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen} 189fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 190fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesenconst TargetRegisterClass *TargetRegisterInfo:: 191fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund OlesengetCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 192fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass *RCB, unsigned SubB, 193fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned &PreA, unsigned &PreB) const { 194fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen assert(RCA && SubA && RCB && SubB && "Invalid arguments"); 195fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 196fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Search all pairs of sub-register indices that project into RCA and RCB 197fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // respectively. This is quadratic, but usually the sets are very small. On 198fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // most targets like X86, there will only be a single sub-register index 199fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // (e.g., sub_16bit projecting into GR16). 200fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // 201fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // The worst case is a register class like DPR on ARM. 202fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // We have indices dsub_0..dsub_7 projecting into that class. 203fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // 204fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // It is very common that one register class is a sub-register of the other. 205fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Arrange for RCA to be the larger register so the answer will be found in 206fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // the first iteration. This makes the search linear for the most common 207fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // case. 208fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass *BestRC = 0; 209fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned *BestPreA = &PreA; 210fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned *BestPreB = &PreB; 211fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (RCA->getSize() < RCB->getSize()) { 212fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen std::swap(RCA, RCB); 2139b23d57dc480a34eee9867be52b9c2022e8979f6Jakob Stoklund Olesen std::swap(SubA, SubB); 214fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen std::swap(BestPreA, BestPreB); 215fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen } 216fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 217fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Also terminate the search one we have found a register class as small as 218fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // RCA. 219fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned MinSize = RCA->getSize(); 220fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 221fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) { 222fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); 223fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) { 224fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Check if a common super-register class exists for this index pair. 225fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass *RC = 226fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen firstCommonClass(IA.getMask(), IB.getMask(), this); 227fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (!RC || RC->getSize() < MinSize) 228fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen continue; 229fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 230fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // The indexes must compose identically: PreA+SubA == PreB+SubB. 231fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); 232fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (FinalA != FinalB) 233fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen continue; 234fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 235fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Is RC a better candidate than BestRC? 236fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (BestRC && RC->getSize() >= BestRC->getSize()) 237fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen continue; 238fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 239fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Yes, RC is the smallest super-register seen so far. 240fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen BestRC = RC; 241fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen *BestPreA = IA.getSubReg(); 242fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen *BestPreB = IB.getSubReg(); 243fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 244fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Bail early if we reached MinSize. We won't find a better candidate. 245fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (BestRC->getSize() == MinSize) 246fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen return BestRC; 247fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen } 248fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen } 249fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen return BestRC; 250fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen} 2517eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 2527eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen// Compute target-independent register allocator hints to help eliminate copies. 2537eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesenvoid 2547eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund OlesenTargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, 2557eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen ArrayRef<MCPhysReg> Order, 2567eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen SmallVectorImpl<MCPhysReg> &Hints, 2577eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen const MachineFunction &MF, 2587eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen const VirtRegMap *VRM) const { 2597eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MF.getRegInfo(); 2607eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 2617eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 2627eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Hints with HintType != 0 were set by target-dependent code. 2637eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Such targets must provide their own implementation of 2647eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // TRI::getRegAllocationHints to interpret those hint types. 2657eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints"); 2667eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 2677eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Target-independent hints are either a physical or a virtual register. 2687eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen unsigned Phys = Hint.second; 2697eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen if (VRM && isVirtualRegister(Phys)) 2707eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen Phys = VRM->getPhys(Phys); 2717eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 2727eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Check that Phys is a valid hint in VirtReg's register class. 2737eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen if (!isPhysicalRegister(Phys)) 2747eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen return; 2757eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen if (MRI.isReserved(Phys)) 2767eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen return; 2777eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Check that Phys is in the allocation order. We shouldn't heed hints 2787eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // from VirtReg's register class if they aren't in the allocation order. The 2797eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // target probably has a reason for removing the register. 2807eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen if (std::find(Order.begin(), Order.end(), Phys) == Order.end()) 2817eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen return; 2827eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 2837eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // All clear, tell the register allocator to prefer this register. 2847eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen Hints.push_back(Phys); 2857eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen} 286