1//===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements a wrapper around MCSchedModel that allows the interface 11// to benefit from information currently only available in TargetInstrInfo. 12// 13//===----------------------------------------------------------------------===// 14 15#include "llvm/CodeGen/TargetSchedule.h" 16#include "llvm/Support/CommandLine.h" 17#include "llvm/Support/raw_ostream.h" 18#include "llvm/Target/TargetInstrInfo.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/Target/TargetSubtargetInfo.h" 22 23using namespace llvm; 24 25static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true), 26 cl::desc("Use TargetSchedModel for latency lookup")); 27 28static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true), 29 cl::desc("Use InstrItineraryData for latency lookup")); 30 31bool TargetSchedModel::hasInstrSchedModel() const { 32 return EnableSchedModel && SchedModel.hasInstrSchedModel(); 33} 34 35bool TargetSchedModel::hasInstrItineraries() const { 36 return EnableSchedItins && !InstrItins.isEmpty(); 37} 38 39static unsigned gcd(unsigned Dividend, unsigned Divisor) { 40 // Dividend and Divisor will be naturally swapped as needed. 41 while(Divisor) { 42 unsigned Rem = Dividend % Divisor; 43 Dividend = Divisor; 44 Divisor = Rem; 45 }; 46 return Dividend; 47} 48static unsigned lcm(unsigned A, unsigned B) { 49 unsigned LCM = (uint64_t(A) * B) / gcd(A, B); 50 assert((LCM >= A && LCM >= B) && "LCM overflow"); 51 return LCM; 52} 53 54void TargetSchedModel::init(const MCSchedModel &sm, 55 const TargetSubtargetInfo *sti, 56 const TargetInstrInfo *tii) { 57 SchedModel = sm; 58 STI = sti; 59 TII = tii; 60 STI->initInstrItins(InstrItins); 61 62 unsigned NumRes = SchedModel.getNumProcResourceKinds(); 63 ResourceFactors.resize(NumRes); 64 ResourceLCM = SchedModel.IssueWidth; 65 for (unsigned Idx = 0; Idx < NumRes; ++Idx) { 66 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits; 67 if (NumUnits > 0) 68 ResourceLCM = lcm(ResourceLCM, NumUnits); 69 } 70 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; 71 for (unsigned Idx = 0; Idx < NumRes; ++Idx) { 72 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits; 73 ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0; 74 } 75} 76 77unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI, 78 const MCSchedClassDesc *SC) const { 79 if (hasInstrItineraries()) { 80 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); 81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI); 82 } 83 if (hasInstrSchedModel()) { 84 if (!SC) 85 SC = resolveSchedClass(MI); 86 if (SC->isValid()) 87 return SC->NumMicroOps; 88 } 89 return MI->isTransient() ? 0 : 1; 90} 91 92// The machine model may explicitly specify an invalid latency, which 93// effectively means infinite latency. Since users of the TargetSchedule API 94// don't know how to handle this, we convert it to a very large latency that is 95// easy to distinguish when debugging the DAG but won't induce overflow. 96static unsigned convertLatency(int Cycles) { 97 return Cycles >= 0 ? Cycles : 1000; 98} 99 100/// If we can determine the operand latency from the def only, without machine 101/// model or itinerary lookup, do so. Otherwise return -1. 102int TargetSchedModel::getDefLatency(const MachineInstr *DefMI, 103 bool FindMin) const { 104 105 // Return a latency based on the itinerary properties and defining instruction 106 // if possible. Some common subtargets don't require per-operand latency, 107 // especially for minimum latencies. 108 if (FindMin) { 109 // If MinLatency is invalid, then use the itinerary for MinLatency. If no 110 // itinerary exists either, then use single cycle latency. 111 if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) { 112 return 1; 113 } 114 return SchedModel.MinLatency; 115 } 116 else if (!hasInstrSchedModel() && !hasInstrItineraries()) { 117 return TII->defaultDefLatency(&SchedModel, DefMI); 118 } 119 // ...operand lookup required 120 return -1; 121} 122 123/// Return the MCSchedClassDesc for this instruction. Some SchedClasses require 124/// evaluation of predicates that depend on instruction operands or flags. 125const MCSchedClassDesc *TargetSchedModel:: 126resolveSchedClass(const MachineInstr *MI) const { 127 128 // Get the definition's scheduling class descriptor from this machine model. 129 unsigned SchedClass = MI->getDesc().getSchedClass(); 130 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); 131 132#ifndef NDEBUG 133 unsigned NIter = 0; 134#endif 135 while (SCDesc->isVariant()) { 136 assert(++NIter < 6 && "Variants are nested deeper than the magic number"); 137 138 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); 139 SCDesc = SchedModel.getSchedClassDesc(SchedClass); 140 } 141 return SCDesc; 142} 143 144/// Find the def index of this operand. This index maps to the machine model and 145/// is independent of use operands. Def operands may be reordered with uses or 146/// merged with uses without affecting the def index (e.g. before/after 147/// regalloc). However, an instruction's def operands must never be reordered 148/// with respect to each other. 149static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) { 150 unsigned DefIdx = 0; 151 for (unsigned i = 0; i != DefOperIdx; ++i) { 152 const MachineOperand &MO = MI->getOperand(i); 153 if (MO.isReg() && MO.isDef()) 154 ++DefIdx; 155 } 156 return DefIdx; 157} 158 159/// Find the use index of this operand. This is independent of the instruction's 160/// def operands. 161/// 162/// Note that uses are not determined by the operand's isUse property, which 163/// is simply the inverse of isDef. Here we consider any readsReg operand to be 164/// a "use". The machine model allows an operand to be both a Def and Use. 165static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) { 166 unsigned UseIdx = 0; 167 for (unsigned i = 0; i != UseOperIdx; ++i) { 168 const MachineOperand &MO = MI->getOperand(i); 169 if (MO.isReg() && MO.readsReg()) 170 ++UseIdx; 171 } 172 return UseIdx; 173} 174 175// Top-level API for clients that know the operand indices. 176unsigned TargetSchedModel::computeOperandLatency( 177 const MachineInstr *DefMI, unsigned DefOperIdx, 178 const MachineInstr *UseMI, unsigned UseOperIdx, 179 bool FindMin) const { 180 181 int DefLatency = getDefLatency(DefMI, FindMin); 182 if (DefLatency >= 0) 183 return DefLatency; 184 185 if (hasInstrItineraries()) { 186 int OperLatency = 0; 187 if (UseMI) { 188 OperLatency = 189 TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx); 190 } 191 else { 192 unsigned DefClass = DefMI->getDesc().getSchedClass(); 193 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx); 194 } 195 if (OperLatency >= 0) 196 return OperLatency; 197 198 // No operand latency was found. 199 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); 200 201 // Expected latency is the max of the stage latency and itinerary props. 202 // Rather than directly querying InstrItins stage latency, we call a TII 203 // hook to allow subtargets to specialize latency. This hook is only 204 // applicable to the InstrItins model. InstrSchedModel should model all 205 // special cases without TII hooks. 206 if (!FindMin) 207 InstrLatency = std::max(InstrLatency, 208 TII->defaultDefLatency(&SchedModel, DefMI)); 209 return InstrLatency; 210 } 211 assert(!FindMin && hasInstrSchedModel() && 212 "Expected a SchedModel for this cpu"); 213 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); 214 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); 215 if (DefIdx < SCDesc->NumWriteLatencyEntries) { 216 // Lookup the definition's write latency in SubtargetInfo. 217 const MCWriteLatencyEntry *WLEntry = 218 STI->getWriteLatencyEntry(SCDesc, DefIdx); 219 unsigned WriteID = WLEntry->WriteResourceID; 220 unsigned Latency = convertLatency(WLEntry->Cycles); 221 if (!UseMI) 222 return Latency; 223 224 // Lookup the use's latency adjustment in SubtargetInfo. 225 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); 226 if (UseDesc->NumReadAdvanceEntries == 0) 227 return Latency; 228 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); 229 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); 230 } 231 // If DefIdx does not exist in the model (e.g. implicit defs), then return 232 // unit latency (defaultDefLatency may be too conservative). 233#ifndef NDEBUG 234 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() 235 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) { 236 std::string Err; 237 raw_string_ostream ss(Err); 238 ss << "DefIdx " << DefIdx << " exceeds machine model writes for " 239 << *DefMI; 240 report_fatal_error(ss.str()); 241 } 242#endif 243 // FIXME: Automatically giving all implicit defs defaultDefLatency is 244 // undesirable. We should only do it for defs that are known to the MC 245 // desc like flags. Truly implicit defs should get 1 cycle latency. 246 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(&SchedModel, DefMI); 247} 248 249unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const { 250 // For the itinerary model, fall back to the old subtarget hook. 251 // Allow subtargets to compute Bundle latencies outside the machine model. 252 if (hasInstrItineraries() || MI->isBundle()) 253 return TII->getInstrLatency(&InstrItins, MI); 254 255 if (hasInstrSchedModel()) { 256 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI); 257 if (SCDesc->isValid()) { 258 unsigned Latency = 0; 259 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; 260 DefIdx != DefEnd; ++DefIdx) { 261 // Lookup the definition's write latency in SubtargetInfo. 262 const MCWriteLatencyEntry *WLEntry = 263 STI->getWriteLatencyEntry(SCDesc, DefIdx); 264 Latency = std::max(Latency, convertLatency(WLEntry->Cycles)); 265 } 266 return Latency; 267 } 268 } 269 return TII->defaultDefLatency(&SchedModel, MI); 270} 271 272unsigned TargetSchedModel:: 273computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, 274 const MachineInstr *DepMI) const { 275 // MinLatency == -1 is for in-order processors that always have unit 276 // MinLatency. MinLatency > 0 is for in-order processors with varying min 277 // latencies, but since this is not a RAW dep, we always use unit latency. 278 if (SchedModel.MinLatency != 0) 279 return 1; 280 281 // MinLatency == 0 indicates an out-of-order processor that can dispatch 282 // WAW dependencies in the same cycle. 283 284 // Treat predication as a data dependency for out-of-order cpus. In-order 285 // cpus do not need to treat predicated writes specially. 286 // 287 // TODO: The following hack exists because predication passes do not 288 // correctly append imp-use operands, and readsReg() strangely returns false 289 // for predicated defs. 290 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg(); 291 const MachineFunction &MF = *DefMI->getParent()->getParent(); 292 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 293 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI)) 294 return computeInstrLatency(DefMI); 295 296 // If we have a per operand scheduling model, check if this def is writing 297 // an unbuffered resource. If so, it treated like an in-order cpu. 298 if (hasInstrSchedModel()) { 299 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); 300 if (SCDesc->isValid()) { 301 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc), 302 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) { 303 if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->IsBuffered) 304 return 1; 305 } 306 } 307 } 308 return 0; 309} 310