172062f5744557e270a38192554c3126ea5f97434Tim Northover//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===// 272062f5744557e270a38192554c3126ea5f97434Tim Northover// 372062f5744557e270a38192554c3126ea5f97434Tim Northover// The LLVM Compiler Infrastructure 472062f5744557e270a38192554c3126ea5f97434Tim Northover// 572062f5744557e270a38192554c3126ea5f97434Tim Northover// This file is distributed under the University of Illinois Open Source 672062f5744557e270a38192554c3126ea5f97434Tim Northover// License. See LICENSE.TXT for details. 772062f5744557e270a38192554c3126ea5f97434Tim Northover// 872062f5744557e270a38192554c3126ea5f97434Tim Northover//===----------------------------------------------------------------------===// 972062f5744557e270a38192554c3126ea5f97434Tim Northover// 1072062f5744557e270a38192554c3126ea5f97434Tim Northover// This file contains the AArch64 implementation of the TargetInstrInfo class. 1172062f5744557e270a38192554c3126ea5f97434Tim Northover// 1272062f5744557e270a38192554c3126ea5f97434Tim Northover//===----------------------------------------------------------------------===// 1372062f5744557e270a38192554c3126ea5f97434Tim Northover 1472062f5744557e270a38192554c3126ea5f97434Tim Northover#ifndef LLVM_TARGET_AARCH64INSTRINFO_H 1572062f5744557e270a38192554c3126ea5f97434Tim Northover#define LLVM_TARGET_AARCH64INSTRINFO_H 1672062f5744557e270a38192554c3126ea5f97434Tim Northover 1772062f5744557e270a38192554c3126ea5f97434Tim Northover#include "llvm/Target/TargetInstrInfo.h" 1872062f5744557e270a38192554c3126ea5f97434Tim Northover#include "AArch64RegisterInfo.h" 1972062f5744557e270a38192554c3126ea5f97434Tim Northover 2072062f5744557e270a38192554c3126ea5f97434Tim Northover#define GET_INSTRINFO_HEADER 2172062f5744557e270a38192554c3126ea5f97434Tim Northover#include "AArch64GenInstrInfo.inc" 2272062f5744557e270a38192554c3126ea5f97434Tim Northover 2372062f5744557e270a38192554c3126ea5f97434Tim Northovernamespace llvm { 2472062f5744557e270a38192554c3126ea5f97434Tim Northover 2572062f5744557e270a38192554c3126ea5f97434Tim Northoverclass AArch64Subtarget; 2672062f5744557e270a38192554c3126ea5f97434Tim Northover 2772062f5744557e270a38192554c3126ea5f97434Tim Northoverclass AArch64InstrInfo : public AArch64GenInstrInfo { 2872062f5744557e270a38192554c3126ea5f97434Tim Northover const AArch64RegisterInfo RI; 2972062f5744557e270a38192554c3126ea5f97434Tim Northover const AArch64Subtarget &Subtarget; 3072062f5744557e270a38192554c3126ea5f97434Tim Northoverpublic: 3172062f5744557e270a38192554c3126ea5f97434Tim Northover explicit AArch64InstrInfo(const AArch64Subtarget &TM); 3272062f5744557e270a38192554c3126ea5f97434Tim Northover 3372062f5744557e270a38192554c3126ea5f97434Tim Northover /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 3472062f5744557e270a38192554c3126ea5f97434Tim Northover /// such, whenever a client has an instance of instruction info, it should 3572062f5744557e270a38192554c3126ea5f97434Tim Northover /// always be able to get register info as well (through this method). 3672062f5744557e270a38192554c3126ea5f97434Tim Northover /// 3772062f5744557e270a38192554c3126ea5f97434Tim Northover const TargetRegisterInfo &getRegisterInfo() const { return RI; } 3872062f5744557e270a38192554c3126ea5f97434Tim Northover 3972062f5744557e270a38192554c3126ea5f97434Tim Northover const AArch64Subtarget &getSubTarget() const { return Subtarget; } 4072062f5744557e270a38192554c3126ea5f97434Tim Northover 4172062f5744557e270a38192554c3126ea5f97434Tim Northover void copyPhysReg(MachineBasicBlock &MBB, 4272062f5744557e270a38192554c3126ea5f97434Tim Northover MachineBasicBlock::iterator I, DebugLoc DL, 4372062f5744557e270a38192554c3126ea5f97434Tim Northover unsigned DestReg, unsigned SrcReg, 4472062f5744557e270a38192554c3126ea5f97434Tim Northover bool KillSrc) const; 4572062f5744557e270a38192554c3126ea5f97434Tim Northover 4672062f5744557e270a38192554c3126ea5f97434Tim Northover MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, 4772062f5744557e270a38192554c3126ea5f97434Tim Northover uint64_t Offset, const MDNode *MDPtr, 4872062f5744557e270a38192554c3126ea5f97434Tim Northover DebugLoc DL) const; 4972062f5744557e270a38192554c3126ea5f97434Tim Northover 5072062f5744557e270a38192554c3126ea5f97434Tim Northover void storeRegToStackSlot(MachineBasicBlock &MBB, 5172062f5744557e270a38192554c3126ea5f97434Tim Northover MachineBasicBlock::iterator MI, 5272062f5744557e270a38192554c3126ea5f97434Tim Northover unsigned SrcReg, bool isKill, int FrameIndex, 5372062f5744557e270a38192554c3126ea5f97434Tim Northover const TargetRegisterClass *RC, 5472062f5744557e270a38192554c3126ea5f97434Tim Northover const TargetRegisterInfo *TRI) const; 5572062f5744557e270a38192554c3126ea5f97434Tim Northover void loadRegFromStackSlot(MachineBasicBlock &MBB, 5672062f5744557e270a38192554c3126ea5f97434Tim Northover MachineBasicBlock::iterator MBBI, 5772062f5744557e270a38192554c3126ea5f97434Tim Northover unsigned DestReg, int FrameIdx, 5872062f5744557e270a38192554c3126ea5f97434Tim Northover const TargetRegisterClass *RC, 5972062f5744557e270a38192554c3126ea5f97434Tim Northover const TargetRegisterInfo *TRI) const; 6072062f5744557e270a38192554c3126ea5f97434Tim Northover 6172062f5744557e270a38192554c3126ea5f97434Tim Northover bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 6272062f5744557e270a38192554c3126ea5f97434Tim Northover MachineBasicBlock *&FBB, 6372062f5744557e270a38192554c3126ea5f97434Tim Northover SmallVectorImpl<MachineOperand> &Cond, 6472062f5744557e270a38192554c3126ea5f97434Tim Northover bool AllowModify = false) const; 6572062f5744557e270a38192554c3126ea5f97434Tim Northover unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 6672062f5744557e270a38192554c3126ea5f97434Tim Northover MachineBasicBlock *FBB, 6772062f5744557e270a38192554c3126ea5f97434Tim Northover const SmallVectorImpl<MachineOperand> &Cond, 6872062f5744557e270a38192554c3126ea5f97434Tim Northover DebugLoc DL) const; 6972062f5744557e270a38192554c3126ea5f97434Tim Northover unsigned RemoveBranch(MachineBasicBlock &MBB) const; 7072062f5744557e270a38192554c3126ea5f97434Tim Northover bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 7172062f5744557e270a38192554c3126ea5f97434Tim Northover 7272062f5744557e270a38192554c3126ea5f97434Tim Northover bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 7372062f5744557e270a38192554c3126ea5f97434Tim Northover 7472062f5744557e270a38192554c3126ea5f97434Tim Northover /// Look through the instructions in this function and work out the largest 7572062f5744557e270a38192554c3126ea5f97434Tim Northover /// the stack frame can be while maintaining the ability to address local 7672062f5744557e270a38192554c3126ea5f97434Tim Northover /// slots with no complexities. 7772062f5744557e270a38192554c3126ea5f97434Tim Northover unsigned estimateRSStackLimit(MachineFunction &MF) const; 7872062f5744557e270a38192554c3126ea5f97434Tim Northover 7972062f5744557e270a38192554c3126ea5f97434Tim Northover /// getAddressConstraints - For loads and stores (and PRFMs) taking an 8072062f5744557e270a38192554c3126ea5f97434Tim Northover /// immediate offset, this function determines the constraints required for 8172062f5744557e270a38192554c3126ea5f97434Tim Northover /// the immediate. It must satisfy: 8272062f5744557e270a38192554c3126ea5f97434Tim Northover /// + MinOffset <= imm <= MaxOffset 8372062f5744557e270a38192554c3126ea5f97434Tim Northover /// + imm % OffsetScale == 0 8472062f5744557e270a38192554c3126ea5f97434Tim Northover void getAddressConstraints(const MachineInstr &MI, int &AccessScale, 8572062f5744557e270a38192554c3126ea5f97434Tim Northover int &MinOffset, int &MaxOffset) const; 8685d2760c8e1d36657ae4d86a6aeee03b3a723d9cTim Northover 8785d2760c8e1d36657ae4d86a6aeee03b3a723d9cTim Northover 8885d2760c8e1d36657ae4d86a6aeee03b3a723d9cTim Northover unsigned getInstSizeInBytes(const MachineInstr &MI) const; 8985d2760c8e1d36657ae4d86a6aeee03b3a723d9cTim Northover 9085d2760c8e1d36657ae4d86a6aeee03b3a723d9cTim Northover unsigned getInstBundleLength(const MachineInstr &MI) const; 9185d2760c8e1d36657ae4d86a6aeee03b3a723d9cTim Northover 9272062f5744557e270a38192554c3126ea5f97434Tim Northover}; 9372062f5744557e270a38192554c3126ea5f97434Tim Northover 9472062f5744557e270a38192554c3126ea5f97434Tim Northoverbool rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 9572062f5744557e270a38192554c3126ea5f97434Tim Northover unsigned FrameReg, int &Offset, 9672062f5744557e270a38192554c3126ea5f97434Tim Northover const AArch64InstrInfo &TII); 9772062f5744557e270a38192554c3126ea5f97434Tim Northover 9872062f5744557e270a38192554c3126ea5f97434Tim Northover 9972062f5744557e270a38192554c3126ea5f97434Tim Northovervoid emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 10072062f5744557e270a38192554c3126ea5f97434Tim Northover DebugLoc dl, const TargetInstrInfo &TII, 10172062f5744557e270a38192554c3126ea5f97434Tim Northover unsigned DstReg, unsigned SrcReg, unsigned ScratchReg, 10272062f5744557e270a38192554c3126ea5f97434Tim Northover int64_t NumBytes, 10372062f5744557e270a38192554c3126ea5f97434Tim Northover MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags); 10472062f5744557e270a38192554c3126ea5f97434Tim Northover 10572062f5744557e270a38192554c3126ea5f97434Tim Northovervoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 10672062f5744557e270a38192554c3126ea5f97434Tim Northover DebugLoc dl, const TargetInstrInfo &TII, 10772062f5744557e270a38192554c3126ea5f97434Tim Northover unsigned ScratchReg, int64_t NumBytes, 10872062f5744557e270a38192554c3126ea5f97434Tim Northover MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags); 10972062f5744557e270a38192554c3126ea5f97434Tim Northover 11072062f5744557e270a38192554c3126ea5f97434Tim Northover} 11172062f5744557e270a38192554c3126ea5f97434Tim Northover 11272062f5744557e270a38192554c3126ea5f97434Tim Northover#endif 113